JP6935638B2 - Semiconductor devices and manufacturing methods - Google Patents

Description

The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

When a MOS type semiconductor device is used in a radiation environment such as space or a nuclear facility, radiation may affect the semiconductor device. Known effects of radiation on semiconductor devices include TID (Total Ionizing Dose) and SEGR (Single Event Gate Rapture). The following documents are related prior art documents.
[Prior art literature]
[Patent Document]
Patent Document 1 Japanese Patent Application Laid-Open No. 6-244428 Patent Document 2 US Pat. No. 7,791,147, Patent Document 3 US Patent Application Publication No. 2014/01244851.

The semiconductor device preferably has a high radiation tolerance such as SEGR tolerance and TID tolerance.

The semiconductor device according to the first aspect of the present invention includes a first conductive type semiconductor substrate. The semiconductor device has a second conductive type, and may have a first body region and a second body region provided on the surface side of the semiconductor substrate. The semiconductor device may have a first conductive neck portion provided between the first body region and the second body region. The semiconductor device may have a first source region formed in the first body region and a second source region formed in the second body region. The semiconductor device has a first gate electrode provided so as to face the first body region between the first source region and the neck portion, and a second source region between the second source region and the neck portion. It may have a second gate electrode provided facing the body region. The semiconductor device may have an insulating film continuously provided between the first gate electrode and the semiconductor substrate, between the second gate electrode and the semiconductor substrate, and on the surface side of the neck portion.

On the surface of the semiconductor substrate, the end portion of the first body region and the end portion of the first gate electrode may be provided at opposite positions. On the surface of the semiconductor substrate, the end portion of the second body region and the end portion of the second gate electrode may be provided at opposite positions.

ただし、Ｌは第１のゲート電極と第２のゲート電極との距離、Ｋは真空の誘電率、ε_０は半導体基板の比誘電率、ｑは電子の電荷量、Ｎ_Ａはボディ領域およびネック部のうちＰ型の導電型の領域のアクセプタ濃度、Ｎ_Ｄはボディ領域およびネック部のうちＮ型の導電型の領域のドナー濃度、φ_ｂｉはボディ領域およびネック部の間の空乏層で発生するビルトインポテンシャルを示す。 The first body region and the second body region may have a protruding portion that protrudes toward the neck portion rather than the end portion on the surface of the semiconductor substrate. The length A of the protruding portion protruding toward the neck portion from the end portion on the surface of the semiconductor substrate in each body region may be in the range of the following equation.

However, L is a distance between the first gate electrode and second gate electrode, K is the dielectric constant of vacuum, epsilon ₀ is the dielectric constant of the semiconductor substrate, q is the electron charge quantity, N _A is the body region and a neck acceptor concentration of the P-type conductivity type region of the section, N _D is the donor concentration N-type conductivity type region of the body region and a neck portion, phi _bi is generated in the depletion layer between the body region and a neck portion Shows the built-in potential to do.

The protruding portion may have a convex recessed portion on the back surface side of the semiconductor substrate between the front surface of the semiconductor substrate and the tip projecting to the most neck portion side. The recessed portion may have the same width in the depth direction of the semiconductor substrate and the width in the direction parallel to the surface of the semiconductor substrate. The thickness of at least a part of the insulating film facing the neck portion may be different from the thickness of the insulating film facing the first gate electrode and the second gate electrode.

In the second aspect of the present invention, which is a method for manufacturing a semiconductor device, a second conductive type impurity is injected into the surface side of the first conductive type semiconductor substrate to form a second conductive type. A step of forming a first conductive neck portion provided between the first body region and the second body region, and the first body region and the second body region, and a first body region. A step of forming a first conductive type first source region inside and a first conductive type second source region in a second body region, and forming an insulating film on the surface of the semiconductor substrate. In the insulating film forming step, on the surface side of the insulating film, a first gate electrode facing the first body region between the first source region and the neck portion, and a second source region and the neck portion. In the step of forming the second body region in between and the facing second gate electrode, and after forming the first gate electrode and the second gate electrode, in the first body region and the second body region. Provided is a manufacturing method including a step of forming a protruding portion protruding toward the neck portion rather than the end portion on the surface of the semiconductor substrate.

At the stage of forming the first gate electrode and the second gate electrode, each gate electrode may be formed inside the body region rather than the end portion on the surface of the semiconductor substrate in each body region.

The step of forming the protrusion may have an oxidation step of oxidizing the surface of the semiconductor substrate. In the oxidation step, the insulating film not covered by each gate electrode may absorb impurities in the body region not covered by each gate electrode. In the oxidation step, the end of the first body region and the end of the first gate electrode are opposed to each other, and the end of the second body region and the end of the second gate electrode are opposed to each other. Impurities in each body region may be absorbed by the insulating film until the position is reached.

In the insulating film forming step, the insulating film may be formed by oxidizing the surface of the semiconductor substrate. The oxidation temperature in the oxidation step may be lower than the oxidation temperature in the insulating film forming step.

The step of forming the protruding portion may include a counter impurity injection step of injecting a second conductive type counter impurity into the neck portion using the first gate electrode and the second gate electrode as masks. The step of forming the protrusion may further include an annealing step of annealing the semiconductor substrate after injecting counter impurities.

At the stage of forming the first gate electrode and the second gate electrode, a conductive film is formed on the surface side of the insulating film, and the conductive film is patterned to form the first gate electrode and the second gate electrode. Moreover, in the patterning, the insulating film on the surface side of the neck portion may be etched.

The outline of the above invention does not list all the features of the present invention. Sub-combinations of these feature groups can also be inventions.

It is sectional drawing which shows an example of the semiconductor device 100 which concerns on one Embodiment of this invention. It is a figure which shows an example of the shape of the body region 12. It is a figure which shows the substrate preparation stage. It is a figure which shows the mask formation stage. It is a figure which shows the impurity injection stage. It is a figure which shows the insulating film formation stage. It is a figure which shows the gate electrode formation stage. It is a figure which shows the oxidation stage. It is a figure which shows the electrode formation stage. It is a figure explaining the length A of the protrusion 32. It is a figure which shows an example of the shape of the protrusion 32. It is a figure which shows another example of a gate electrode formation stage. It is a figure which shows an example of the shape of the insulating film 28 in a semiconductor device 100. It is a figure which shows the other structural example of the semiconductor device 100. It is a figure which shows another example of the process of forming a protrusion 32.

Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the inventions that fall within the scope of the claims. Also, not all combinations of features described in the embodiments are essential to the means of solving the invention.

FIG. 1 is a cross-sectional view showing an example of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 includes a semiconductor substrate 10, a first gate electrode 30-1, a second gate electrode 30-2, an insulating film 28, an interlayer insulating portion 27, a source electrode 26, and a drain electrode 24.

The semiconductor substrate 10 has a first conductive type. In this example, the first conductive type is described as N type and the second conductive type is described as P type, but the first conductive type may be P type and the second conductive type may be N type. The semiconductor substrate 10 is, for example, a silicon substrate to which a predetermined N-type impurity is added.

The semiconductor substrate 10 has a first body region 12-1 and a second body region 12-2 provided apart from each other in a cross section perpendicular to the surface. In this example, each body region 12 is P-shaped. Each body region 12 is exposed on the surface of the semiconductor substrate 10.

An N-shaped drift region 16 is provided on the surface side of the semiconductor substrate 10. The first body region 12-1 and the second body region 12-2 are formed in a region on the surface side of the drift region 16. An N-shaped region of the drift region 16 remains between the first body region 12-1 and the second body region 12-2. In the present specification, the N-type region between the first body region 12-1 and the second body region 12-2 is referred to as a neck portion 18.

A first source region 14-1 is formed in the first body region 12-1. A second source region 14-2 is formed in the second body region 12-2. Each source region 14 is exposed on the surface of the semiconductor substrate 10. In addition to the surface of the semiconductor substrate 10, the source region 14 is covered with the body region 12. In this example, the source region 14 is N-type. The impurity concentration of the source region 14 may be higher than the impurity concentration of the semiconductor substrate 10.

On the surface of the semiconductor substrate 10, the first body region 12-1 between the first source region 14-1 and the neck portion 18 functions as a channel. The first gate electrode 30-1 is provided so as to face the first body region 12-1 that functions as a channel. The second body region 12-2 between the second source region 14-2 and the neck portion 18 also functions as a channel. The second gate electrode 30-2 is provided so as to face the second body region 12-2 that functions as a channel. An insulating film 28 is provided between each gate electrode 30 and the semiconductor substrate 10. The first gate electrode 30-1 and the second gate electrode 30-2 may be connected in an annular shape on the surface side of the semiconductor substrate 10 and may be stretched in parallel.

By applying a predetermined voltage to each gate electrode 30, an inversion region is formed on the surface of the body region 12 facing the gate electrode 30. As a result, the source region 14 and the neck portion 18 are electrically connected. A drift region 16 continuous with the neck portion 18 is provided on the back surface side of each body region 12. The drift region 16 may have the same impurity concentration as the neck portion 18.

An intermediate region 20 is provided on the back surface side of the drift region 16. The intermediate region 20 of this example is N-type. The intermediate region 20 may have a higher impurity concentration than the drift region 16. A drain region 22 is provided on the back surface side of the intermediate region 20. The drain region 22 of this example is N-shaped. The drain region 22 may have a higher impurity concentration than the intermediate region 20.

A drain electrode 24 is provided on the back surface side of the drain region 22. By applying a predetermined voltage to the gate electrode 30 with a predetermined voltage applied between the source electrode 26 and the drain electrode 24, a current flows between the source and drain.

Further, the semiconductor device 100 further includes an interlayer insulating portion 27 that covers the gate electrode 30. The interlayer insulating portion 27 insulates the gate electrode 30 from the source electrode 26. The interlayer insulating portion 27 may be formed by depositing BPSG, PSG, or the like. The interlayer insulating portion 27 may also be provided at a position facing the neck portion 18. However, an insulating film 28 is provided between the neck portion 18 and the interlayer insulating portion 27.

The source electrode 26 is connected to the source region 14 and the body region 12 which are not covered by the interlayer insulating portion 27. The source electrode 26 and the drain electrode 24 may be made of a metal such as aluminum. The gate electrode 30 may be made of a conductive material such as polysilicon.

The insulating film 28 is continuously provided between the first gate electrode 30-1 and the semiconductor substrate 10, between the second gate electrode 30-2 and the semiconductor substrate 10, and on the surface side of the neck portion 18. The insulating film 28 has higher insulating properties than the interlayer insulating portion 27. The insulating film 28 is formed by, for example, oxidizing the surface of the semiconductor substrate 10.

When radiation enters the insulating film 28, electron-hole pairs are generated in the insulating film 28. The mobility of holes in the insulating film 28 is smaller than that of electrons. For example, when the insulating film 28 is a silicon oxide film, the mobility is 6 orders of magnitude or more smaller. When holes are trapped in the defects in the insulating film 28 between the gate electrode 30 and the semiconductor substrate 10, a fixed charge is generated. In addition, the interface state is generated by the holes that reach the interface. The threshold value of the MOS transistor fluctuates depending on the fixed charge and the interface state. Such a phenomenon is called TID.

On the other hand, by forming the insulating film 28 in the low temperature process, it is possible to suppress the formation of defects in the insulating film 28. The insulating film 28 is formed by oxidizing the surface of the semiconductor substrate 10 at, for example, 1000 degrees or less. The oxidation temperature may be 900 degrees or less. Thereby, the TID withstand capacity can be improved.

Further, when heavy particles are incident on the semiconductor substrate 10, plasma filaments (electron-hole pairs) are generated along the path through which the heavy particles have passed. Therefore, when heavy particles are incident on the neck portion 18, the back surface of the insulating film 28 and the drain electrode 24 are electrically connected via the plasma filament generated in the N-shaped region. If the gate electrode is provided at a position facing the neck portion 18, a large drain voltage is applied between the front surface and the back surface of the insulating film 28 facing the neck portion 18, and the insulating film 28 is destroyed. Such a phenomenon is called SEGR.

In order to increase the SEGR resistance, the thickness of the insulating film 28 may be increased. However, if the thickness of the insulating film 28 that functions as the gate oxide film is increased, the amount of electric charge generated when the gate oxide film is irradiated with electron radiation increases, and the TID resistance deteriorates.

On the other hand, the semiconductor device 100 has a split gate structure, and the gate electrode 30 is not provided at a position facing the neck portion 18. Therefore, even when heavy particles are incident on the neck portion 18 and the back surface of the insulating film 28 is electrically connected to the drain electrode 24, the electric field concentration in the insulating film 28 can be relaxed. As a result, both the improvement of the TID withstand capacity and the improvement of the SEGR withstand capacity can be achieved at the same time.

Further, since the insulating film 28 extends to the surface side of the neck portion 18, it is possible to prevent the neck portion 18 from coming into contact with the interlayer insulating portion 27 having a relatively low insulating property. Therefore, the reliability of the semiconductor device 100 can be maintained while improving the TID withstand and SEGR withstand by the split gate structure. The insulating film 28 may cover the entire surface of the neck portion 18. The surface of the neck portion 18 refers to an N-shaped region sandwiched or surrounded by a first body region 12-1 and a second body region 12-2 on the surface of the semiconductor substrate 10. Further, since the insulating film 28 extends to a position facing the neck portion 18, the shape of the body region 12 can be controlled at the time of manufacturing the semiconductor device 100, as will be described later.

FIG. 2 is a diagram showing an example of the shape of the body region 12. Although the shape of the first body region 12-1 is shown in FIG. 2, the second body region 12-2 may also have a shape symmetrical to that of the first body region 12-1.

As shown in FIG. 2, on the surface of the semiconductor substrate 10, the end 38 of the body region 12 and the end 36 of the gate electrode 30 are provided at opposite positions. The end 38 of the body region 12 and the end 36 of the gate electrode 30 refer to the end on the neck 18 side. Further, the fact that the ends face each other means that the positions of the end 38 and the end 36 in the plane parallel to the surface of the semiconductor substrate 10 are substantially the same. As an example, when the error in the positions of the end 38 and the end 36 in the plane is within 0.2 μm, the end 38 and the end 36 may be regarded as facing each other.

However, when the gate electrode 30 has the above-mentioned position error, it is preferable that the end portion 36 of the gate electrode 30 projects toward the neck portion 18 side with respect to the end portion 38 of the body region 12. By arranging the end 38 of the body region 12 and the end 36 of the gate electrode 30 so as to face each other, the SEGR tolerance can be maximized while ensuring the controllability of the channel in the body region 12.

Further, the body region 12 has a protruding portion 32 protruding toward the neck portion 18 from the end portion 38 on the surface of the semiconductor substrate 10. An N-shaped neck portion 18 extends between the protruding portion 32 and the surface of the semiconductor substrate 10. The protruding portion 32 has a tip 34 located inside the semiconductor substrate 10 so as to be located closer to the neck portion 18 than the end portion 38 on the surface of the semiconductor substrate 10. The tip 34 refers to the portion of the protruding portion 32 that is closest to the neck portion 18 in the plane parallel to the surface of the semiconductor substrate 10.

When the protruding portion 32 is provided so that the positional error between the end portion 36 of the gate electrode 30 and the end portion 38 of the body region 12 is larger than 0 and is formed within a range of 0.2 μm (that is, the end portion 36 is formed). The insulating film 28 sandwiched between the gate electrodes 30 facing the neck portion 18 is protected by the protruding portion 32 (when the tip portion 34 is displaced from the end portion 38). Therefore, even if heavy particles are incident to form a plasma filament, it is possible to prevent a large drain voltage from being applied to the insulating film 28 sandwiched between the gate electrode 30 and the neck portion 18. Further, by providing the protruding portion 32, the neck portion 18 can be made thinner. Therefore, when heavy particles are incident on the semiconductor substrate 10, it becomes difficult to form a path of the plasma filament penetrating the N-type region. Therefore, the SEGR resistance can be improved.

3A to 3G are diagrams illustrating an example of a method for manufacturing the semiconductor device 100. FIG. 3A shows the substrate preparation stage. In the substrate preparation stage, the semiconductor substrate 10 is prepared. The semiconductor substrate 10 of this example has a drain region 22, an intermediate region 20, and a drift region 16. As an example, an N ++ type base substrate is prepared. The semiconductor substrate 10 is prepared by sequentially epitaxially growing the N + type intermediate region 20 and the N-type drift region 16 on the base substrate. After forming the N-shaped drift region 16, the base substrate may be polished to a predetermined thickness.

FIG. 3B shows the mask forming stage. At the mask forming stage, the oxide film mask 50 is formed on the surface of the semiconductor substrate 10. As an example, after the entire surface of the semiconductor substrate 10 is oxidized to form an oxide film, the oxide film is patterned by plasma etching or the like to form an oxide film mask 50.

FIG. 3C shows the impurity injection stage. In the impurity injection step, a predetermined impurity is injected from the surface of the semiconductor substrate 10. As an example, first, a P-type impurity such as boron is injected using the oxide film mask 50 as a mask. The P-type impurities are diffused by heat treatment or the like to form the first body region 12-1 and the second body region 12-2.

In the impurity injection step, the body region 12 may be formed in a ring shape along the edge of the oxide film mask 50. The first body region 12-1 and the second body region 12-2 may refer to two regions arranged across an N-shaped region in the annular body region. As a result, the neck portion 18 is also formed. Further, using the oxide film mask 50 as a mask, N-type impurities such as arsenic are injected and diffused into a part of the body region 12 to form the source region 14 in the body region 12. By using the oxide film mask 50 as a mask, the body region 12 and the source region 14 can be formed by self-alignment. The source region 14 may also be formed in a ring shape like the body region 12. Further, the gate electrode 30 described later may also be formed in an annular shape like the body region 12.

FIG. 3D shows the insulating film forming stage. In the insulating film forming step, the insulating film 52 is formed by removing the oxide film mask 50 shown in FIG. 3C and then thermally oxidizing the surface of the semiconductor substrate 10. The insulating film 52 is formed by, for example, a low temperature process of 1000 degrees or less in order to suppress the occurrence of defects. The temperature at which the insulating film 52 is formed may be 900 degrees or less. In this example, the temperature at which the insulating film 52 is formed is 900 degrees. The film thickness of the insulating film 52 may be 300 Å or more and 1200 Å or less.

When the insulating film 52 is formed, impurities contained in the body region 12 are sucked into the insulating film 52. Therefore, the shape of the body region 12 is such that the boundary portion with the neck portion 18 is caught in the source region 14 side in the vicinity of the surface of the semiconductor substrate 10. Impurities of the type sucked into the insulating film 52 when the semiconductor substrate 10 is oxidized are injected into the body region 12.

In this example, the semiconductor substrate 10 is silicon, and the impurity injected into the body region 12 is boron. After forming the insulating film 52, the conductive material 54 is formed on the surface side of the insulating film 52. The conductive material 54 is, for example, polysilicon. However, the materials of the semiconductor substrate 10, impurities, and the conductive material 54 are not limited to the above examples.

FIG. 3E shows the gate electrode forming stage. In the gate electrode forming step, the conductive material 54 is etched to form the first electrode 30-1 and the second electrode 30-2. The etching is, for example, plasma etching.

Each gate electrode 30 is formed at a position facing the body region 12 between the source region 14 and the neck portion 18. However, in the gate electrode forming stage, the end portion 36 on the neck portion 18 side of each gate electrode 30 is located closer to the source region 14 than the end portion on the surface of the semiconductor substrate 10 on the neck portion 18 side of the body region 12. The conductive material 54 is etched.

At this stage, the gate electrode 30 is not provided on the surface of the semiconductor substrate 10 at a position facing the end of the body region 12 on the neck portion 18 side. That is, the end portion 36 of the gate electrode 30 is arranged inside the body region 12 in a plane parallel to the surface of the semiconductor substrate 10.

FIG. 3F shows a step of forming a protruding portion 32 protruding toward the neck portion 18 from the end portion 38 on the surface of the semiconductor substrate 10 in the first body region 12-1 and the second body region 12-2. show. The step of forming the protrusion 32 of this example has an oxidation step. In the oxidation step, after the gate electrode 30 is formed, the surface of the semiconductor substrate 10 is further thermally oxidized. The oxidation temperature in the oxidation step is lower than the oxidation temperature in the insulating film forming step, for example, lower than 900 degrees. The oxidation temperature in the oxidation step of this example is 850 degrees.

Due to the oxidation step, the film thickness of the insulating film 52 is increased to form the insulating film 28. However, in the region covered by the gate electrode 30, oxidation of the semiconductor substrate 10 does not proceed easily, so that the film thickness of the insulating film 52 hardly increases. In the region not covered by the gate electrode 30, impurities contained in the body region 12 are absorbed by the insulating film 28.

Therefore, the end portion 38 on the surface of the semiconductor substrate 10 in the body region 12 is further involved in the source region 14 side. That is, the position of the end 38 of the body region 12 moves toward the source region 14 as the surface of the semiconductor substrate 10 is oxidized.

In the oxidation step, the insulating film 28 absorbs impurities in each body region 12 until the end 38 of each body region 12 and the end 36 of each gate electrode 30 face each other. However, in the region covered by the gate electrode 30, impurities contained in the body region 12 are hardly absorbed by the insulating film 28. When the end 38 of the body region 12 moves to a position facing the end 36 of the gate electrode 30, it does not move to the source region 14 side even if oxidation is further advanced.

Therefore, the position of the end portion 38 of the body region 12 can be self-aligned with respect to the end portion 36 of the gate electrode 30. Further, the position of the end 38 of each body region 12 can be accurately aligned with the position of the end 36 of the gate electrode 30 in the same process.

FIG. 3G shows the electrode formation stage. In the electrode forming stage, an insulating film is formed on the surface side of the semiconductor substrate 10 and etched into a predetermined pattern to form the interlayer insulating portion 27. The interlayer insulating portion 27 is formed, and the insulating film 28 is etched to expose a part of the source region 14 and a part of the body region 12. Then, on the surface side of the semiconductor substrate 10, the source electrode 26 connected to the source region 14 and the body region 12 is formed. Further, the drain electrode 24 is formed on the back surface side of the semiconductor substrate 10. Before forming the drain electrode 24, the base substrate may be polished to a predetermined thickness. By such a method, the semiconductor device 100 can be manufactured.

According to the manufacturing method of this example, both that the gate electrode 30 is not arranged on the neck portion 18 and that the gate electrode 30 is arranged on the channel of the body region 12 can be achieved with high accuracy. That is, it is possible to achieve both improvement in SEGR withstand capability and channel controllability. Further, since the protruding portion 32 is formed in the body region 12, the SEGR resistance can be further improved.

Further, by forming the insulating film 28 by a low temperature process, the TID resistance can be improved. Further, since it is not necessary to thicken the insulating film 28 below the gate electrode 30, the TID resistance can be improved. Further, since the insulating film 28 is provided on the neck portion 18, it is possible to prevent the neck portion 18 from coming into contact with the interlayer insulating portion 27 having a relatively low insulating property. As described above, according to the manufacturing method of this example or the semiconductor device 100, it is possible to achieve both improvement of TID withstand capability and SEGR withstand capability at a high level.

ただし、Ｌは第１のゲート電極３０−１と、第２のゲート電極３０−２との距離、Ｋは真空の誘電率、ε_０は半導体基板１０の比誘電率、ｑは電子の電荷量、Ｎ_Ａはボディ領域１２およびネック部１８のうちＰ型の導電型の領域のアクセプタ濃度、Ｎ_Ｄはボディ領域１２およびネック部１８のうちＮ型の導電型の領域のドナー濃度、φ_ｂｉはボディ領域１２およびネック部１８の間の空乏層で発生するビルトインポテンシャルを示す。 FIG. 4 is a diagram for explaining the length A of the protruding portion 32. The length A refers to the distance between the end 38 of the body region 12 and the tip 34 of the protrusion 32 in a plane parallel to the surface of the semiconductor substrate 10. The length A is preferably in the following range.

However, L is the distance between the first gate electrode 30-1 and the second gate electrode 30-2, K is the dielectric constant of the vacuum, ε ₀ is the relative permittivity of the semiconductor substrate 10, and q is the amount of electron charge. , donor concentration of N-type conductivity type region of the P-type acceptor concentration of the conductive type region, N _D is the body region 12 and a neck portion 18 of the N _a body region 12 and a neck portion 18, phi _bi is The built-in potential generated in the depletion layer between the body region 12 and the neck portion 18 is shown.

When the depletion layer 40 extending from the first body region 12-1 to the neck portion 18 and the depletion layer 40 extending from the second body region 12-2 to the neck portion 18 come into contact with each other, the current path disappears and the on-resistance increases. .. Therefore, the length A of the protruding portion 32 is preferably a range in which the depletion layer 40 from the first body region 12-1 and the depletion layer 40 from the second body region 12-2 do not come into contact with each other. ..

ネック部１８がＮ型の場合、ネック部１８側の空乏層幅Ｗ_ｎは次式で与えられる。

数２および数３から、数１が得られる。空乏層間に所定の距離を設けるために、長さＡの上限は、数１の右辺の半分であってもよい。 _{That is, assuming} that the width of the depletion layer 40 on the neck portion 18 side is W n, it is preferable to satisfy the following equation.

When the neck portion 18 is N-shaped, the depletion layer width W _n on the neck portion 18 side is given by the following equation.

From Equation 2 and Equation 3, Equation 1 is obtained. The upper limit of the length A may be half of the right side of Equation 1 in order to provide a predetermined distance between the depletion layers.

The length of the protruding portion 32 may be 0.3 μm or more and 0.5 μm or less. The distance L between the gate electrodes 30 may be 2 μm or more and 4 μm or less. The distance between the tips 34 of the body region 12 may be 1 μm or more and 3 μm or less.

FIG. 5 is a diagram showing an example of the shape of the protruding portion 32. The protruding portion 32 of this example has a recessed portion 42 having a convex shape on the back surface side of the semiconductor substrate 10 between the end portion 38 on the front surface of the semiconductor substrate 10 and the tip end 34. The recessed portion 42 in this example is a region in which the inclination of the tangent line of the protruding portion 32 with respect to the surface of the semiconductor substrate 10 gradually decreases from the end portion 38 side toward the tip end 34 in a cross section perpendicular to the surface of the semiconductor substrate 10. It may be there. However, the recessed portion 42 may include a portion where the tangent line of the protruding portion 32 is substantially parallel to the surface of the semiconductor substrate 10 and the inclination does not change.

Since the protruding portion 32 has the recessed portion 42, the current path between the insulating film 28 and the protruding portion 32 can be widened. Thereby, the on-resistance can be reduced.

The recessed portion 42 has a depth D1 in the depth direction of the semiconductor substrate 10 and a width W1 in the direction parallel to the surface of the semiconductor substrate. One end of the recessed portion 42 may be the end portion 38 of the protruding portion 32. Further, in the cross section of the other end of the recessed portion 42 perpendicular to the surface of the semiconductor substrate 10, the inclination of the tangential line of the protruding portion 32 with respect to the surface of the semiconductor substrate 10 gradually increases from the end portion 38 side toward the tip end 34. It may be the boundary point 44 of the starting region.

The width W1 of the recessed portion 42 may be at least half the length A of the protruding portion 32. Further, the depth D1 of the recessed portion 42 may be half or more of the depth D2 of the tip 34 of the protruding portion 32. By enlarging the recessed portion 42, the current path between the insulating film 28 and the protruding portion 32 can be widened. As an example, the depth D1 of the recessed portion 42 is 0.1 μm or more and 0.5 μm or less, and the width W1 is 0.1 μm or more and 0.5 μm or less.

The width W1 and the depth D1 of the recess 42 may be equal. Equal does not mean that they are exactly the same. If the ratio of the width W1 and the depth D1 is about 80% or more and 120% or less, the width W1 and the depth D1 may be considered to be equal. With such a shape, it is possible to prevent the shape of the recessed portion 42 from becoming steep and prevent local electric field concentration.

The recessed portion 42 can be formed in the oxidation step described in FIG. 3F. As described above, in the body region 12 covered with the gate electrode 30, impurities are not easily sucked out to the insulating film 28, and even if oxidation is promoted, the position of the end 38 of the body region 12 is the gate electrode 30. It stops at a position facing the end portion 36 of the. When the position of the end 38 of the body region 12 becomes a position facing the end 36 of the gate electrode 30 and then further oxidation is carried out, the position of the end 38 of the body region 12 hardly moves, but the gate electrode 30 Impurities near the surface of the body region 12 not covered with the insulating film 28 are sucked into the insulating film 28. Therefore, the recessed portion 42 is formed.

FIG. 6 is a diagram showing another example of the gate electrode forming stage described with reference to FIG. 3E. As described above, in the gate electrode forming step, the conductive material 54 formed on the surface side of the insulating film 52 is etched into a predetermined pattern to form the first gate electrode 30-1 and the second gate electrode 30-2. Form. In this example, in the patterning of the conductive material 54, the insulating film 52 in the region 46 on the surface side of the neck portion 18 is also etched. The etching of the insulating film 52 may be performed continuously with the etching of the conductive material 54, or may be performed separately.

As a result, the thickness T2 of the insulating film 52 in the region 46 facing the neck portion 18 becomes smaller than the thickness T1 of the insulating film 52 in the region 48 facing the gate electrode 30. In this state, the oxidation step shown in FIG. 3F is performed. By thinning the insulating film 52 in the region 46, the initial growth rate of the insulating film 52 in the region 46 at the oxidation stage can be improved. Therefore, impurities can be efficiently sucked out to form the protruding portion 32 and the recessed portion 42.

Further, by thinning the insulating film 52, impurities can be efficiently sucked out even in a process at a lower temperature. Therefore, it is possible to suppress the occurrence of defects in the insulating film 52 and improve the TID resistance.

The thickness T2 of the insulating film 52 in the region 46 may be half or less of the thickness T1 of the insulating film 52 in the region 48. Thereby, the growth rate of the insulating film 52 in the region 46 can be further improved. The thickness T2 may be half or more of the thickness T1.

FIG. 7 is a diagram showing an example of the shape of the insulating film 28 in the semiconductor device 100. In the insulating film 28 of this example, the thickness in the region 46 facing the neck portion 18 is different from the thickness in the region 48 facing the gate electrode 30. In the above-mentioned example of the manufacturing method, since the semiconductor substrate 10 is further oxidized after the gate electrode 30 is formed, the insulating film is formed between the region covered by the gate electrode 30 and the region not covered by the gate electrode 30. The thicknesses of 28 do not always match.

As shown in FIG. 7, the thickness of the insulating film 28 in the region 46 facing the neck portion 18 may be smaller than the thickness in the region 48 facing the gate electrode 30. As described in FIG. 6, when the insulating film 28 in the region 46 is etched before the oxidation step, the shape of the insulating film 28 can be obtained.

Further, the thickness of the insulating film 28 in the region 46 facing the neck portion 18 may be larger than the thickness in the region 48 facing the gate electrode 30. If the insulating film 28 in the region 46 is not etched before the oxidation step, the shape of the insulating film 28 can be obtained. Further, even when the insulating film 28 in the region 46 is etched before the oxidation step, the shape of the insulating film 28 can be obtained by sufficiently increasing the film thickness of the insulating film 28 in the oxidation step. In this case, the insulating film 28 facing the gate electrode 30 can be thinned to improve the TID resistance, and the insulating film 28 facing the neck portion 18 can be made thicker.

FIG. 8 is a diagram showing another configuration example of the semiconductor device 100. In the semiconductor device 100 of this example, the shape of the body region 12 is different from the configuration of the semiconductor device 100 shown in FIG. Other structures may be the same as the semiconductor device 100 shown in FIG.

In the body region 12 of this example, the end portion on the back surface side reaches the intermediate region 20. That is, the body region 12 and the drift region 16 form a super junction structure. The withstand voltage of the semiconductor device 100 is improved by the super junction structure. The structures described in FIGS. 1 to 7 can also be applied to the semiconductor device 100 having a super junction structure. The protruding portion 32 is formed so as to protrude in the direction of the neck portion 18 from the portion extending inside the drift region 16 to reach the intermediate region 20.

FIG. 9 is a diagram showing another example of the step of forming the protrusion 32. In this example, the steps from FIG. 3A to FIG. 3E are the same. In this example, the counter impurity injection step is provided instead of the oxidation step shown in FIG. 3F.

In the counter impurity injection step, the first conductive type counter impurity is injected into the neck portion 18 using the first gate electrode 30-1 and the second electrode 30-2 as masks. The first conductive type is a conductive type opposite to the conductive type of the body region 12. That is, when N-type impurities have already been injected into the body region 12, the counter impurities are P-type impurities in the body region 12. The counter impurity is injected in an amount sufficient to form a part of the body region 12 into the first conductive type.

As an example, when the semiconductor device 100 is a silicon N-channel MOS transistor, the counter impurity may be arsenic ion or phosphorus ion. As an example, the dose amount of counter impurities is about ^{5 × 10 13} / cm ^2.

Further, when the semiconductor device 100 is a silicon P-channel MOS transistor, the counter impurity may be boron ions. As an example, the dose amount of counter impurities is about ^{1 × 10 14} / cm ^2.

In the counter impurity injection step, the resist 60 may be formed on the surface of the semiconductor substrate 10 before the counter impurities are injected. The resist 60 covers the surface of the semiconductor substrate 10 other than the neck portion 18. However, a part of the gate electrode 30 on the neck portion 18 side does not have to be covered with the resist 60. As a result, even if the resist 60 is displaced during the formation of the resist 60, it is possible to prevent the resist 60 from covering the neck portion 18.

The step of forming the protrusion 32 further includes an annealing step of injecting counter impurities into the neck portion 18 and then annealing the semiconductor substrate 10. This activates the counter impurities injected into the neck portion 18. Due to the activated counter impurities, the upper part of the body region 12 not covered by the gate electrode 30 is changed to the first conductive type.

The annealing temperature in the annealing step is lower than the oxidation temperature in the insulating film forming step shown in FIG. 3D, for example, lower than 900 degrees. The oxidation temperature in the oxidation step of this example is 850 degrees. As an example, the lower limit of the annealing temperature in the annealing step is 700 degrees in order to activate the counter impurities. As a result, the protrusion 32 can be formed by activating the counter impurities while preventing the insulating film 28 from deteriorating.

By such a step, the protruding portion 32 described in FIGS. 1 to 8 can be formed. The shape of the body region 12 in this example is the same as that of the body region 12 shown in FIG. 5, for example. However, the end 38 of the protrusion 32 may be provided on the source region 14 side of the end of the gate electrode 30 depending on the diffusion length of the counter impurities.

When the semiconductor device 100 is a silicon P-channel MOS transistor, it may be difficult to suck out impurities in the body region 12 in the oxidation step shown in FIG. 3F. On the other hand, according to the manufacturing method of this example, even when the semiconductor device 100 is a silicon P-channel MOS transistor, the protruding portion 32 can be easily formed in the body region 12.

Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear from the description of the claims that such modified or improved forms may also be included in the technical scope of the present invention.

It should be noted that the scope of claims, the specification, and the execution order of each process in the method shown in the drawings are not specified as "before", "prior to", etc. It can be achieved in any order unless the output is used in later processing.

10 ... Semiconductor substrate, 12 ... Body region, 14 ... Source region, 16 ... Drift region, 18 ... Neck part, 20 ... Intermediate region, 22 ... Drain region, 24 ... drain electrode, 26 ... source electrode, 27 ... interlayer insulating part, 28 ... insulating film, 30 ... gate electrode, 32 ... protruding part, 34 ... tip, 36 ... .. end, 38 ... end, 40 ... depletion layer, 42 ... depression, 44 ... boundary point, 46 ... region, 48 ... region, 50 ... oxidation Film mask, 52 ... Insulating film, 54 ... Conductive material, 60 ... Resist, 100 ... Semiconductor device

Claims (1)

The first conductive semiconductor substrate and
A first body region and a second body region having a second conductive type and provided on the surface side of the semiconductor substrate,
The first conductive type neck portion provided between the first body region and the second body region, and
A first source region having the first conductive type and formed in the first body region, and a second source region formed in the second body region.
The first body region between the first source region and the neck portion is provided at a position facing the first body region, and the end portion is provided at a position facing the end portion of the first body region on the surface of the semiconductor substrate. The end of the second body region on the surface of the semiconductor substrate, which faces the first gate electrode and the second body region between the second source region and the neck. A second gate electrode provided at a position facing the
An insulating film continuously provided between the first gate electrode and the semiconductor substrate, between the second gate electrode and the semiconductor substrate, and on the surface side of the neck portion.
The insulating film on the surface side of the neck portion, the interlayer insulating film covering the first gate electrode and the second gate electrode, and the interlayer insulating film.
A source electrode connected to the first source region and the second source region, and the first body region and the second body region, and covers the interlayer insulating film on the surface side of the neck portion. With and
The interlayer insulating film insulates the source electrode from the first gate electrode and the second gate electrode.
The bottom surface of the source electrode between the first gate electrode and the second gate electrode is arranged above both the upper surface of the first gate electrode and the upper surface of the second gate electrode. ,
The insulating film is a thermal oxide film.
A semiconductor device in which the interlayer insulating film is in contact with the insulating film at the neck portion.

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