JP2018061065A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve reliability of a semiconductor device by preventing fluctuation in element characteristics due to field concentration in a LDMOS transistor which has an isolation insulation film embedded in a semiconductor substrate in order to increase withstand voltage between a source and a drain.SOLUTION: In a semiconductor device, by forming a trench HL on a top face of an isolation insulation film SIS of a LDMOS transistor PD1, a part of a gate electrode GE is embedded in the trench HL. This prevents field concentration in a semiconductor substrate SB near an end of the isolation insulation film SIS on a source side.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a semiconductor device, and more particularly to a structure of a lateral diffusion transistor having an isolation insulating film between a gate and a drain among MOS (Metal Oxide Semiconductor) transistors.

  In element isolation of advanced logic MOS transistors, an STI (Shallow Trench Isolation) structure is often used instead of a LOCOS (Local Oxidation of Silicon) structure in order to reduce the isolation area. In the case of forming a high breakdown voltage LDMOS (Laterally Diffused MOS) transistor, it is known to use an STI structure for gate-drain separation in order to secure a breakdown voltage.

  In Patent Document 1 (Japanese Patent Laid-Open No. 2010-258226), in an N-channel LDMOS transistor, in order to prevent the on-resistance from fluctuating due to the concentration of an electric field at the end of the STI structure on the source side, It is described that a step is provided at the end of the structure.

  Patent Document 2 (US Pat. No. 8,357,986) describes that in an LDMOS transistor, a part of a gate electrode is embedded in a groove provided in a main surface of a semiconductor substrate. Here, in order to reduce the capacitance between the gate electrode and the drain region, the gate electrode is not formed on the drain region side of the trench. In order to reduce the capacitance, no n-type drift region is formed on the source region side of the trench. The insulating film separating the gate electrode in the groove and the substrate constituting the side wall and bottom surface of the groove is equivalent to the gate insulating film of the LDMOS transistor because the substrate in contact with the insulating film is a channel region. It has a film thickness.

  In Non-Patent Document 1, since the electric field is directed in the direction in which electrons are injected into the gate oxide film in the substrate of the P-channel LDMOS transistor, the electrons are accelerated when the electric field is concentrated at the end of the STI structure. It is described that it is implanted into the gate oxide film. It is also described that the gate oxide film is destroyed at the upper end of the STI structure due to the damage caused by the implantation.

  Non-Patent Document 2 describes that in addition to the destruction of the gate oxide film, the electric field balance is lost and the breakdown voltage is reduced.

JP 2010-258226 A US Pat. No. 8,357,986

Investigation of Multistage Linear Region Drain Current Degradation and Gate-Oxide Breakdown Under Hot-Carrier Stress in BCD HV PMOS, Yu-Hui Huang et al., Proc. Of IRPS'11, pp.444-448 HCI-induced off-state I-V curve shifting and subsequent destruction in an STI-based LD-PMOS transistor, H. Fujii et al., Proc. Of ISPSD’13, pp.379-382

  In a horizontal LDMOS transistor, when hot carrier stress occurs, the electric field concentrates at the end of the source side of the STI structure and a high electric field is generated to generate an interface state, or electrons generated by impact ionization are injected into the end of the STI structure. As a result, there arises a problem that the on-resistance varies.

  In addition, in the substrate of the P-channel LDMOS transistor, the electric field is directed in the direction in which electrons are injected into the gate oxide film. Therefore, the electrons are accelerated at the end of the STI structure and injected into the gate oxide film. The balance is lost and the pressure resistance decreases. Further, as described in Non-Patent Document 1, there is a problem that the gate oxide film is destroyed at the upper end portion of the STI structure due to the damage caused by the implantation.

  In Patent Document 1, a step is provided at the end of the bottom surface of the STI structure for the purpose of suppressing the concentration of the electric field. However, with this structure, even if the electric field in the substrate can be reduced as a whole, The decline cannot be prevented. That is, the electric field concentration is likely to occur in the substrate at the end portion of the bottom surface of the STI structure. In the structure of Patent Document 1, a plurality of corner portions where the electric field concentrates are formed at the end portion, and further, the gate insulation is further increased. Since the electric field concentrates in the vicinity of the step formed near the film, injection of electrons into the gate insulating film becomes significant.

  Other objects and novel features will become apparent from the description of the specification and the accompanying drawings.

  Of the embodiments disclosed in the present application, the outline of typical ones will be briefly described as follows.

  In a semiconductor device according to an embodiment, a groove is formed on the upper surface of an isolation insulating film of an LDMOS transistor so that a part of the gate electrode is embedded in the groove.

  According to one embodiment disclosed in the present application, the reliability of a semiconductor device can be improved. In particular, fluctuations in on-resistance during hot carrier stress can be suppressed, and fatal phenomena such as a decrease in breakdown voltage and gate oxide film breakdown during hot carrier stress can be prevented.

1 is a plan view showing a semiconductor device according to a first embodiment of the present invention. It is sectional drawing in the AA of FIG. It is sectional drawing explaining the manufacturing method of the semiconductor device which is Embodiment 1 of this invention. FIG. 4 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 3. FIG. 5 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 4. FIG. 6 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 5; FIG. 7 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 6; FIG. 8 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 7; 4 is a graph showing a change in gate current with respect to a groove width in the LDMOS transistor according to the first embodiment of the present invention. It is an expanded sectional view which shows a part of FIG. It is a graph which shows the electric field by the side of the semiconductor substrate along the source side edge of an isolation insulating film. It is a graph which shows the impact ionization generation | occurrence | production rate by the side of the semiconductor substrate along the source side edge of an isolation insulating film. It is a graph which shows the electric field by the side of the semiconductor substrate of the bottom part of an isolation insulating film. It is a graph which shows the impact ionization generation | occurrence | production rate by the side of the semiconductor substrate of the bottom part of an isolation insulating film. It is a graph which shows the change of the off breakdown voltage and the on breakdown voltage with respect to the width of a groove. It is a graph which shows the change of ON resistance to the width of a groove. It is a graph which shows the change of the gate current with respect to the distance of the source side edge of an isolation insulating film, and a groove | channel. 6 is a graph showing changes in off breakdown voltage and on breakdown voltage with respect to a distance between a source side end of an isolation insulating film and a groove. It is a graph which shows the change of gate current with respect to the covering amount of a gate electrode. It is a graph which shows the relationship between the distance ratio of the covering amount of a gate electrode, an off-breakdown voltage, and an on-breakdown voltage. It is a graph which shows the relationship between the distance ratio of the covering amount of a gate electrode, and ON resistance. It is a graph which shows the change of the gate current with respect to the depth of a groove | channel. It is a graph which shows the relationship between the off breakdown voltage and the on breakdown voltage with respect to the depth of the groove. It is a graph which shows the electric field by the side of the semiconductor substrate of the bottom part of an isolation insulating film. It is a graph which shows the impact ionization generation | occurrence | production rate by the side of the semiconductor substrate of the bottom part of an isolation insulating film. It is a top view which shows the semiconductor device which is Embodiment 2 of this invention. It is a top view which shows the modification of the semiconductor device which is Embodiment 2 of this invention. It is sectional drawing in the DD line | wire of FIG. It is a graph which compares the gate current in each LDMOS transistor of Embodiment 1 and Embodiment 2 of this invention. 4 is a graph comparing off breakdown voltage and on breakdown voltage in LDMOS transistors according to the first and second embodiments of the present invention. It is a graph which compares the on-resistance in each LDMOS transistor of Embodiment 1 and Embodiment 2 of this invention. It is sectional drawing which shows the semiconductor device which is Embodiment 3 of this invention. It is sectional drawing which shows the semiconductor device which is Embodiment 4 of this invention. It is a graph which compares the well current in each LDMOS transistor of Embodiment 4 of this invention, and a 1st comparative example. 6 is a graph comparing the off breakdown voltage and the on breakdown voltage in LDMOS transistors of the fourth embodiment of the present invention and the first comparative example. It is a graph which compares the on-resistance in each LDMOS transistor of Embodiment 4 of this invention, and a 1st comparative example. It is sectional drawing which shows the N channel type LDMOS transistor which is a semiconductor device of a 1st comparative example. It is sectional drawing which shows the P channel type LDMOS transistor which is a semiconductor device of a 1st comparative example. It is sectional drawing which shows the N channel type LDMOS transistor which is a semiconductor device of the 2nd comparative example. It is sectional drawing which shows the P channel type LDMOS transistor which is a semiconductor device of the 2nd comparative example. It is a graph which shows the relationship between progress of the time which gives stress to the semiconductor device of the 1st and 2nd comparative example, and an off breakdown voltage. It is a graph which shows the relationship between passage of time which gives stress to the semiconductor device of the 1st and 2nd comparative examples, and gate current. It is a graph which shows the relationship between progress of the time which gives stress to the semiconductor device of a 1st, 2nd comparative example, and ON resistance. It is a graph which shows the change of gate current to the amount of covering of the gate electrode of the semiconductor device of the 1st comparative example. It is a graph which shows the change of an off-proof pressure and an ON-proof pressure to the amount of covering of a gate electrode of a semiconductor device of the 1st comparative example.

  Hereinafter, embodiments will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the following embodiments, even a plan view may be partially hatched to make the drawings easy to see.

(Embodiment 1)
Hereinafter, the structure of the semiconductor device of this embodiment will be described with reference to FIGS. FIG. 1 is a plan view showing a structure of an LDMOS transistor which is a semiconductor device of the present embodiment. 2 is a cross-sectional view taken along line AA in FIG. The LDMOS transistor PD1 shown in FIGS. 1 and 2 is a P-channel MOS type FET (Field Effect Transistor).

In FIG. 1, a semiconductor substrate SB, an isolation insulating film SIS made of an insulating film embedded in an isolation trench (separation trench) TNC formed on the upper surface of the semiconductor substrate SB, and the semiconductor substrate SB and the isolation insulating film SIS. The gate electrode GE formed on each of these is shown. The semiconductor substrate SB, p ⁺ -type source region is a semiconductor region (source diffusion layer) SC, p ⁺ -type drain region is a semiconductor region (drain diffusion layer) DC, n ⁺ -type semiconductor region is a well A region WC, a well region WL that is an n-type semiconductor region, and a drift region DFT that is a p-type semiconductor region are formed. In FIG. 1, the boundaries of the semiconductor substrate SB, the drift region DFT, and the well region WL in the region covered with the isolation insulating film SIS are indicated by broken lines. In addition, the area where the gate electrode GE is formed is hatched in plan view.

  As shown in FIG. 1, the upper surfaces of the source region SC, the drain region DC, the well region WC, a part of the drift region DFT, and a part of the well region WL are exposed from the isolation insulating film SIS. A trench HL is formed on the upper surface of the isolation insulating film SIS.

As shown in FIG. 2, the P-channel type LDMOS transistor PD1 includes a source region SC, a drain region DC, a well region WC, a well region WL, a drift region DFT, an n ⁻ type semiconductor formed in a semiconductor substrate SB. The region includes a well region HWL, a gate electrode GE, a gate insulating film GIS, an isolation insulating film SIS, and a trench HL. The upper portion of the LDMOS transistor PD1 is covered with an interlayer insulating film IS, and contact plugs CN1, CN2 and CN3 penetrating the interlayer insulating film IS are connected to the LDMOS transistor PD1. The plurality of wirings INC formed on the interlayer insulating film IS are connected to the upper surface of the contact plug CN1, the upper surface of CN2, and the upper surface of CN3, respectively.

The semiconductor substrate SB is, for example, a p ⁻ type silicon substrate, and the gate insulating film GIS formed on the semiconductor substrate SB is made of, for example, a silicon oxide film, and the gate electrode formed on the semiconductor substrate SB via the gate insulating film GIS. The GE is made of polysilicon, for example. Near the upper surface of the semiconductor substrate SB, a well region HWL which is an n ⁻ type semiconductor region is formed with a relatively deep depth.

On the upper surface of the semiconductor substrate SB, a drift region DFT that is a p ⁺ type semiconductor region and a well region WL that is an n type semiconductor region are formed shallower than the well region HWL. The gate insulating film GIS is formed closer to the source region SC than the trench TNC and the isolation insulating film SIS. That is, the gate insulating film GIS and the isolation insulating film SIS are disposed adjacent to each other in plan view and do not overlap each other.

The n ⁻ type well region HWL having a lighter concentration than the n type well region WL is provided over the entire region of the LDMOS transistor PD1, and the well region WL and the drift region DFT include the gate electrode GE and the gate oxide film. They are arranged so that they are adjacent to each other directly below. The well region WL is formed with a shallower depth than the drift region DFT.

  For example, the isolation insulating film SIS mainly made of a silicon oxide film is buried in a trench TNC formed on the upper surface of the semiconductor substrate SB at a depth shallower than the well region WL and the drift region DFT. The source region SC and the drain region DC are arranged on the upper surface of the semiconductor substrate SB so as to sandwich the gate electrode GE, the gate insulating film GIS, and the isolation insulating film SIS in plan view. The distance between the gate electrode GE and the drain region DC is larger than the distance between the gate electrode GE and the source region SC. The isolation insulating film SIS is provided between the gate electrode GE and the drain region DC, and is disposed immediately below the gate electrode GE.

The well region WL where the channel of the LDMOS transistor PD1 is formed is formed so as to cover the lower surface and the side wall of the source region SC, and the drift region DFT includes the lower surface of the drain region DC, the lower surface and the side wall of the isolation insulating film SIS. And so as to cover. One side wall of the well region WC that is an n ⁺ type semiconductor region is in contact with the source region SC, and the lower surface of the well region WC is covered with the well region WL. The source region SC, drain region DC, and well region WC are formed on the upper surface of the semiconductor substrate SB at a depth shallower than the well region WL, the drift region DFT, and the isolation insulating film SIS. The drift region DFT is formed immediately below the gate insulating film GIS and directly below the isolation insulating film SIS, and the end of the drift region DFT on the source region SC side is located immediately below the gate insulating film GIS.

  A gate electrode GE is partially covered on the isolation insulating film SIS provided to ensure a desired source-drain breakdown voltage, and a high breakdown voltage can be obtained by the field plate effect obtained by this structure. it can. By increasing the amount of covering, the electric field at the end of the isolation insulating film SIS is relaxed, and electron injection into the source side end of the isolation insulating film SIS and the gate insulating film GIS during hot carrier stress is suppressed. Note that the withstand voltage in this application refers to the electrical withstand voltage between the source and the drain unless otherwise specified. The withstand voltage when the gate is off is the off withstand voltage, and the withstand voltage when the gate is on is on. Called pressure resistance.

  The contact plug CN1 is electrically connected to the upper surfaces of the well region WC and the source region SC via a silicide layer (not shown). That is, the well region WC and the source region SC are short-circuited via a silicide layer (not shown) formed on the upper surface thereof. The reason why the well region WC and the source region SC are short-circuited in this way is to suppress the base resistance of the parasitic bipolar transistor in the semiconductor substrate. By short-circuiting the well region WC and the source region SC, it is possible to prevent the parasitic bipolar transistor from being turned on. The parasitic bipolar here can be constituted by, for example, a PNP junction including a source region SC, a well region WL, and a drift region DFT.

  The contact plug CN2 is electrically connected to the upper surface of the gate electrode GE via a silicide layer (not shown). The contact plug CN3 is electrically connected to the upper surface of the drain region DC via a silicide layer (not shown).

  Thus, a pair of source region SC and drain region DC is formed on the main surface of the semiconductor substrate SB, and an isolation insulating film SIS is provided in the trench TNC between the source region SC and the drain region DC. A gate insulating film GIS is formed closer to the source region SC than the insulating film SIS. The gate electrode GE is formed so as to straddle over the gate insulating film GIS and the isolation insulating film SIS between the source region SC and the drain region DC. That is, the gate electrode GE is formed over the gate insulating film GIS and directly over the isolation insulating film SIS.

  A gate electrode GE is embedded in the trench HL formed on the upper surface of the isolation insulating film SIS. Here, when the trench HL is not formed on the upper surface of the isolation insulating film SIS like the P-channel type LDMOS transistor CD2 which is the semiconductor device of the first comparative example shown in FIG. That is, since the electric field on the surface of the semiconductor substrate SB below the end of the gate electrode GE becomes strong, there is a problem that the off breakdown voltage is lowered. Further, there is a problem in that electrons due to impact ionization increase on the surface of the semiconductor substrate SB below the end of the gate electrode GE, and this electron current causes the parasitic bipolar transistor to operate, thereby reducing the on-breakdown voltage. As shown in FIG. 37, this also applies to the N-channel LDMOS transistor CD1 that does not have the trench HL. FIG. 37 is a cross-sectional view showing an N-channel type LDMOS transistor which is a semiconductor device of a first comparative example.

  In each of the N-channel and P-channel LDMOS transistors, an interface state is generated because the electric field is concentrated and becomes a high electric field at the end of the source side of the STI structure at the time of hot carrier stress. When electrons generated by impact ionization are injected into the end portion of the STI structure, there arises a problem that the on-resistance varies. In addition, in the P-channel type LDMOS transistor, since the electric field is directed in the direction in which electrons are injected into the gate insulating film, electrons are accelerated at the end of the STI structure and injected into the gate insulating film, There is a problem in that the electric field is lost and the breakdown voltage is reduced, and the gate oxide film is destroyed at the upper end of the STI structure due to the damage caused by the implantation.

  On the other hand, the STI structure, that is, the STI where the electric field is most concentrated is provided by providing a step at the end of the isolation insulating film SIS as in the LDMOS transistors CD3 and CD4 shown as the second comparative example in FIGS. It is conceivable to reduce the electric field at the end of the structure. FIG. 39 is a cross-sectional view showing an N-channel type LDMOS transistor CD3 which is a semiconductor device of a second comparative example. FIG. 40 is a cross-sectional view showing a P-channel type LDMOS transistor CD4 which is a semiconductor device of a second comparative example.

  Unlike the LDMOS transistor PD1 (see FIG. 2) of the present embodiment, the LDMOS transistors CD3 and CD4 of the second comparative example shown in FIGS. 39 and 40 do not have the trench HL, and the isolation insulating film SIS. Is provided with a step at the end on the source region SC side.

The N-channel LDMOS transistors shown in FIGS. 37 and 39 are different from the P-channel LDMOS transistors shown in FIGS. 38 and 40 in the following points. That is, the N channel type LDMOS transistor has no well region HWL, and the conductivity types of the source region SC, drain region DC, drift region DFT, well region WL and well region WC are different from those of the P channel type LDMOS transistor. It differs from a P-channel LDMOS transistor in that it has a conductivity type opposite to that of each region. That is, in the N channel type LDMOS transistor CD3, the source region SC and the drain region DC are n ⁺ type, the drift region DFT is n type, the well region WL is p type, and the well region WC is p ⁺ type. It is.

  Note that the structure of an N-channel LDMOS transistor PD4 (see FIG. 33) of the fourth embodiment to be described later is different from that of the P-channel LDMOS transistor PD1 (see FIG. 2) of the present embodiment, as described above.

  Here, FIG. 41 shows the actual measurement results of the withstand voltage fluctuation during hot carrier stress of the LDMOS transistor CD2 (see FIG. 38) and the LDMOS transistor CD4 (see FIG. 40). FIG. 41 is a graph showing the relationship between the passage of time for applying stress to the semiconductor devices of the first and second comparative examples and the off breakdown voltage BVoff. The results of the LDMOS transistor CD2 are shown by broken lines and white rhombus plots. The results for transistor CD4 are shown as a solid line and a black square plot. That is, FIG. 41 compares the breakdown voltage lifetimes of the LDMOS transistor CD2 of the first comparative example that does not have a step in the STI structure and the LDMOS transistor CD4 of the second comparative example that has a step in the STI structure.

  From the graph of FIG. 41, it can be seen that the breakdown voltage is reduced during the hot carrier stress in the structure having the step as shown in FIG. 40 as well as the structure without the step as shown in FIG. This is thought to be because the corners at the source side end of the STI structure where the electric field concentrates increased to two places, and the injection of electrons into the end of the STI structure was promoted. As can be seen from the actual measurement result of FIG. 42, the gate current Ig, which is an index indicating the amount of electron injection, increases.

  For this reason, as shown in the actual measurement result of FIG. 43, even if the step is provided, the variation amount of the on-resistance Rsp is not reduced. As described above, the P-channel LDMOS transistor has various problems due to positive injection of electrons in hot carrier stress into the STI structure or the gate oxide film. As can be seen from the actual measurement results, it is difficult to solve these problems with the structure shown in FIG. Compared to the P-channel type, the N-channel type LDMOS transistor (see FIGS. 37 and 39) is less likely to cause problems of electrons being injected into the gate insulating film and the gate insulating film being destroyed. As described with reference to FIG. 43, even if a step is provided in the STI structure, it is difficult to solve the problem that electrons are injected into the STI structure during hot carrier stress and the breakdown voltage of the element is lowered.

  Note that the gate current in the present application refers to a current that flows between a semiconductor substrate and a gate electrode through a gate insulating film or an isolation insulating film. FIG. 42 is a graph showing the relationship between the passage of time for applying stress to the semiconductor devices of the first and second comparative examples and the gate current Ig. FIG. 43 is a graph showing the relationship between the passage of time for applying stress to the semiconductor devices of the first and second comparative examples and the on-resistance Rsp. 42 and 43, similarly to FIG. 41, the results of the LDMOS transistor CD2 are indicated by a broken line and a white rhombus plot, and the results of the LDMOS transistor CD4 are indicated by a solid line and a black square plot.

  In order to deal with the above problem, in this embodiment, a trench HL is provided in a region on the upper surface of the isolation insulating film SIS shown in FIG. A part of the electrode GE is embedded. Here, the gate electrode GE embedded in the trench HL relaxes the electric field in the semiconductor substrate SB in the vicinity of the source side end of the isolation insulating film SIS, so that the amount of coverage of the gate electrode GE on the isolation insulating film SIS is more than necessary. There is no need to make it long. Therefore, it is possible to improve the hot carrier characteristics while preventing a decrease in the off breakdown voltage and the on breakdown voltage due to the length Lov being the covering amount of the gate electrode GE being increased. As a result, fluctuations in the breakdown voltage of the LDMOS transistor can be prevented and the reliability of the gate insulating film can be improved, so that the reliability of the semiconductor device can be improved.

  According to the present embodiment, since the gate electrode GE is embedded in a part of the isolation insulating film SIS, the electric field in the vicinity of the end of the isolation insulating film SIS where the electric field is concentrated is alleviated. Therefore, electron injection into the edge of the isolation insulating film SIS or the gate insulating film GIS during hot carrier stress is suppressed, variation in on-resistance can be reduced, and destruction of the gate insulating film GIS can be prevented. It becomes possible.

  Next, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. 3 to 8 are cross-sectional views showing a method of manufacturing an LDMOS transistor which is the semiconductor device of the present embodiment shown in FIGS.

First, as shown in FIG. 3, a semiconductor substrate SB which is a p ⁻ type silicon substrate is prepared. Next, a photoresist film is formed so as to open a region where the LDMOS transistor is formed by a well-known photolithography technique, and an n-type impurity is implanted into the upper surface of the semiconductor substrate SB. After removing the photoresist film, an n ^- type well region HWL is formed by diffusing n-type impurities from the upper surface of the semiconductor substrate SB to a deep region by high-temperature heat treatment exceeding 1000 ° C., for example.

  Next, as shown in FIG. 4, a hard mask HM for forming the STI structure is deposited on the surface of the semiconductor substrate SB. The hard mask HM is made of, for example, a silicon nitride film or a laminated film of a silicon oxide film and a silicon nitride film. Next, a photoresist film is formed so as to open the STI formation scheduled region by photolithography. Thereafter, the semiconductor substrate SB exposed from the opening of the photoresist film is removed by a depth of about several hundred nm by anisotropic etching, and then the photoresist film is removed.

  Next, as shown in FIG. 5, after depositing a silicon oxide film on the entire surface of the semiconductor substrate SB and filling the trench TNC, the silicon on the hard mask HM is formed by CMP (Chemical Mechanical Polishing) method or etch back method. By removing the oxide film, the isolation insulating film SIS made of the silicon oxide film is left only in the trench TNC. Thereafter, the hard mask HM is removed by isotropic etching or the like. Next, a p-type drift region DFT and an n-type well region WL are sequentially formed on the upper surface of the semiconductor substrate SB by a method such as ion implantation by photolithography. Either the p-type drift region DFT or the n-type well region WL may be formed first.

  Next, as shown in FIG. 6, a photoresist film (not shown) having an opening so as to expose a portion where the groove HL is to be formed is formed on the upper surface of the isolation insulating film SIS in the trench TNC by photolithography. The position where the photoresist film is opened is directly above the isolation insulating film SIS, is away from the end of the isolation insulating film SIS, and the gate electrode GE (see FIG. 7) is formed in a later step. It is located in a region that overlaps the planned region in plan view. Next, for example, anisotropic etching is performed using the photoresist film as a mask, thereby forming a groove HL on the upper surface of the isolation insulating film SIS. The depth of the trench HL is formed to be 1/3 or more of the isolation insulating film SIS, but does not reach the bottom surface of the isolation insulating film SIS. Thereafter, the photoresist film is removed.

  Next, as shown in FIG. 7, a gate insulating film GIS is formed with a thickness of about several to several tens of nanometers by, for example, thermal oxidation, and polysilicon serving as the gate electrode GE is formed thereon by CVD (Chemical Vapor Deposition). It is formed by the method. At this time, polysilicon is also buried in the trench HL. Next, a pattern of a photoresist film that covers only the region where the gate electrode GE is to be formed is formed by photolithography. At this time, the trench HL is covered with a photoresist film. Thereafter, the polysilicon is removed by anisotropic etching to expose the upper surfaces of the semiconductor substrate SB and the isolation insulating film SIS, thereby forming the gate electrode GE and then removing the photoresist film.

  Next, as shown in FIG. 8, the drain region DC, the source region SC, and the well region WC are sequentially formed by a method such as ion implantation by photolithography. Thereby, the LDMOS transistor PD1 having the source region SC, the drain region DC, the well region WC, the well region WL, the drift region DFT, the well region HWL, the gate electrode GE, the gate insulating film GIS, the isolation insulating film SIS, and the trench HL is formed. To do.

  Next, after an interlayer insulating film IS is deposited on the entire surface of the semiconductor substrate SB by using, for example, a CVD method, a plurality of connection holes are formed in the interlayer insulating film IS by photolithography. Contact plugs CN1 to CN3 are formed by embedding a conductor such as tungsten in these connection holes. Next, a necessary number of wiring layers are formed on the interlayer insulating film IS. The wiring INC connected to the LDMOS transistor constitutes this wiring layer. For example, Al (aluminum) or Cu (copper) is used as the main material of the wiring. In this way, the structure as shown in FIGS. 1 and 2 is formed. Although not shown, electrode pads are formed on the uppermost wiring layer.

  Below, the effect of the semiconductor device of this Embodiment is demonstrated. The gate current that reflects the amount of electron injection during stress is an effective index for suppressing the change in on-resistance during hot carrier stress and preventing gate oxide film destruction, which is the object of this embodiment. Ig. It will be described in detail below that the gate electrode GE (see FIG. 2) in the trench HL (see FIG. 2), which is a characteristic part of the structure of the present embodiment, is effective in reducing the gate current Ig. explain.

  First, the gate current Ig of the LDMOS transistor CD2 (see FIG. 38) having a structure in which the trench HL is not provided will be described. This gate current Ig can be reduced by reducing the electric field in the vicinity of the end of the isolation insulating film SIS. In the LDMOS transistor CD2, an effective method for reducing the gate current Ig is to increase the length Lov, which is the amount of covering of the gate electrode GE with respect to the isolation insulating film SIS. FIG. 44 is a graph of device simulation results showing changes in the gate current Ig with respect to the length Lov in the LDMOS transistor CD2.

  Here, the length Lov is indicated by a ratio (in percentage) to the length of the drift region DFT immediately below the isolation insulating film SIS, that is, the length Ld of the drain region immediately below the isolation insulating film SIS. The length Ld of the drift region DFT is constant. When the length Lov, which is the amount of covering of the gate electrode GE, increases, the electric field at the source side end of the isolation insulating film SIS is relaxed, and the gate current Ig decreases. However, as shown in FIG. 45, there arises a problem that the off breakdown voltage BVoff and the on breakdown voltage BVon are lowered.

  FIG. 45 is a graph showing changes in the off breakdown voltage BVoff and the on breakdown voltage BVon with respect to the length Lov in the LDMOS transistor CD2. In FIG. 45, the graph of the off breakdown voltage BVoff is indicated by a solid line and a black rhombus plot, and the graph of the on breakdown voltage BVon is indicated by a broken line and a white triangular plot.

  Next, the structure of the present embodiment will be described by paying attention to the influence of the planar position of the gate electrode GE in the trench HL shown in FIG. 2 on the gate current Ig. Layout parameters representing the planar position of the gate electrode GE in the trench HL include the width Lt of the trench HL, the distance Ls between the source side end of the isolation insulating film SIS and the trench HL, and the isolation insulating film of the gate electrode GE. The length Lov which is the amount of covering with respect to SIS is mentioned. Note that the width Lt, the distance Ls, and the length Lov are all the lengths in the direction along the main surface of the semiconductor substrate, in which the source and drain regions constituting the LDMOS transistor are arranged.

  Further, as shown in FIG. 2, the thickness of the isolation insulating film SIS in the direction perpendicular to the main surface of the semiconductor substrate SB is represented by Ly, and the depth of the trench HL in the same direction is represented by Lx. That is, the depth Lx of the trench HL is a distance from the top surface of the isolation insulating film SIS to the bottom surface of the trench HL.

  Hereinafter, changes in the gate current Ig when the values of the respective parameters are changed will be described along with device simulation results.

  FIG. 9 is a graph of a device simulation result showing a change in the gate current Ig with respect to the width Lt of the trench HL in the LDMOS transistor PD1 of the present embodiment shown in FIG. Here, the width Lt of the trench HL is indicated by a ratio (expressed as a percentage) to the length Lov, which is a covering amount of the gate electrode GE with respect to the isolation insulating film SIS, and the value of the length Lov is constant. In this simulation, the distance ratio Ls / Lov is fixed at 6.8%, and the depth ratio Lx / Ly is fixed at 77%. Further, as in the LDMOS transistor CD2 (see FIG. 38) of the first comparative example, the value of the gate current Ig when the groove HL is not formed, that is, when the width Lt of the groove HL is fixed at 0% is In FIG. 9, the values are indicated by broken-line circles.

  As shown in FIG. 9, as the width Lt of the trench HL is increased from 0% to about 50%, the gate current Ig decreases, and at about 50%, the gate current Ig becomes minimum. Therefore, the LDMOS transistor PD1 (see FIG. 2) of the present embodiment can reduce the gate current Ig by about three digits as compared with the LDMOS transistor CD2 (see FIG. 38) of the first comparative example in which the trench HL is not provided. Is possible.

  Here, FIG. 10 shows an enlarged cross-sectional view of an end portion on the source region side of the isolation insulating film in the semiconductor device of this embodiment. FIG. 10 shows specific points B1, B2, and C1 along the boundary between the isolation insulating film SIS and the semiconductor substrate SB. B1 is an upper end portion at the boundary between the isolation insulating film SIS and the semiconductor substrate SB, B2 is an end portion on the source region side on the bottom surface of the isolation insulating film SIS, and C1 is an end portion on the drain region side of the gate electrode GE. This is the boundary between the isolation insulating film SIS and the semiconductor substrate SB immediately below.

  A graph of the simulation result of the electric field on the semiconductor substrate SB side in the boundary line B1-B2 in the cross-sectional view of FIG. 10 along the source side end of the isolation insulating film SIS is shown in FIG. 11, and the semiconductor substrate SB in the boundary line B1-B2 The graph of the simulation result of the impact ionization generation rate (IIGR) on the side is shown in FIG. As these results show, the gate electrode GE in the trench HL shown in FIG. 10 alleviates the electric field at the source side end of the isolation insulating film SIS, and suppresses the generation amount of impact ions. Therefore, since the impact ionization rate can be lowered, electron injection into the isolation insulating film SIS or the gate insulating film GIS can be reduced.

  11 and 12, the result of the LDMOS transistor PD1 of the present embodiment is indicated by a solid line, and the result of the LDMOS transistor CD2 (see FIG. 38) of the first comparative example is indicated by a broken line. Here, the distance ratio Lt / Lov of the graph of the present embodiment indicated by the solid line is 43%, and the width Lt = 0 in the graph of the first comparative example indicated by the broken line.

  As shown in FIG. 9, when the width Lt of the trench HL is further increased from about 50%, the gate current increases conversely. This is because, as shown in FIGS. 13 and 14, the high electric field region shifts to the drain side, the amount of impact ions generated increases, and the gate current Ig flows through the bottom portion of the trench HL. FIG. 13 is a graph showing a simulation result of the electric field on the semiconductor substrate SB side at the boundary line B2-C1 of the cross-sectional view of FIG. FIG. 14 is a graph showing a simulation result of the impact ionization generation rate (IIGR) on the boundary line B2-C1 in the cross-sectional view of FIG. 10, that is, the semiconductor substrate SB side at the bottom of the isolation insulating film SIS.

  In FIGS. 13 and 14, the result of the LDMOS transistor PD1 of the present embodiment is indicated by a solid line and a one-dot chain line, and the result of the LDMOS transistor CD2 (see FIG. 38) of the first comparative example is indicated by a broken line. Here, the distance ratio Lt / Lov of the graph of the present embodiment indicated by a solid line is 43%, and the distance ratio Lt / Lov of the graph of the present embodiment indicated by an alternate long and short dash line is 98%, which is indicated by a broken line. The width of the graph of one comparative example is Lt = 0. In FIGS. 13 and 14, the distance ratio Ls / Lov is fixed at 6.8%, and the depth ratio Lx / Ly is fixed at 77%.

  FIG. 15 is a graph of device simulation results showing changes in the off breakdown voltage BVoff and the on breakdown voltage BVon with respect to the width Lt of the groove HL shown in FIG. Similarly to FIG. 9, the horizontal axis of the graph is indicated by the ratio (in percentage) between the width Lt of the trench HL and the length Lov that is the amount of coverage of the gate electrode GE with respect to the isolation insulating film SIS. The value of Lov is constant. The solid line graph connecting the black rhombus plots in FIG. 15 and the broken line graph connecting the white triangle plots indicate the OFF breakdown voltage BVoff and the ON breakdown voltage BVon for the LDMOS transistor PD1 of this embodiment (see FIG. 2). It shows the measurement result.

  Both the off-breakdown voltage BVoff and the on-breakdown voltage BVon rapidly decrease when the width Lt exceeds about 50%. However, as long as the width Lt is within about 50%, there is almost no decrease in each breakdown voltage. Therefore, if the width Lt is set to 40%, for example, the gate current Ig can be reduced by three orders of magnitude without substantially decreasing each breakdown voltage (see FIG. 9). That is, the hot carrier characteristics are improved and the gate current Ig can be prevented from flowing through the gate insulating film GIS, so that the life of the semiconductor device can be extended. As described above, it is desirable that the width Lt of the trench HL has such a length that the decrease in the off breakdown voltage BVoff and the on breakdown voltage BVon is small and the gate current Ig can be made as small as possible.

  The on-resistance Rsp, which is an important item along with the breakdown voltage, will be described below as a performance index of the LDMOS transistor. As shown in FIG. 16, in the structure of the present embodiment, the LDMOS transistor CD2 of the first comparative example in which the groove HL is not formed by setting the width Lt of the groove HL to about 40% (see FIG. 38). As compared with the above, an improvement effect of about 5% can be obtained. FIG. 16 is a graph showing the relationship between the distance ratio Lt / Lov and the on-resistance Rsp. Again, the distance ratio Ls / Lov is 6.8%, the depth ratio Lx / Ly is 77%, and the value of the length Lov is constant. Further, the value of the on-resistance Rsp when the width Lt of the trench HL is fixed at 0% as in the LDMOS transistor CD2 (see FIG. 38) of the first comparative example is a value indicated by a broken-line circle in FIG. It becomes.

  The on-resistance Rsp can be reduced in this way by providing the trench HL and forming the gate electrode GE in the trench HL, thereby forming a hole accumulation layer in the semiconductor substrate SB immediately below the gate electrode GE. This is because the resistance in the semiconductor substrate SB on which the storage layer is formed decreases.

  On the other hand, in the LDMOS transistor CD2 (see FIG. 38) of the first comparative example, as shown in FIG. 21, the ratio (in percentage) between the length Lov, which is the amount of coverage of the gate electrode GE, and the length Ld of the drift region DFT. Is increased to about 70%, which is the upper limit for securing the off breakdown voltage BVoff and the on breakdown voltage BVon to be 70 V or more, the on resistance Rsp can be improved only by about 2%. Therefore, the structure of the present embodiment has an advantage that a relatively large effect can be obtained with respect to the reduction of the on-resistance Rsp.

  FIG. 21 is a graph showing the relationship between the ratio (in percentage) between the length Lov and the length Ld and the on-resistance Rsp. In FIG. 21, the result of the LDMOS transistor PD1 (see FIG. 2) of the present embodiment is indicated by a solid line, and the result of the LDMOS transistor CD2 of the first comparative example is indicated by a broken line. The ratio of the distances of the LDMOS transistor PD1 measured in FIG. 21 is fixed at Ls / Ld = 5%, Lt / Ld = 15%, and Lx / Ly = 77%. Further, the value of the length Ld is constant.

  In the following, when the position of the drain side end of the trench HL shown in FIG. 2 is fixed, that is, when Ls + Lt is constant, the distance Ls between the source side end of the isolation insulating film SIS and the trench HL is changed. The result of is described.

  FIG. 17 is a graph of a device simulation result showing a change in the gate current Ig with respect to the distance Ls between the source side end of the isolation insulating film SIS and the trench HL. A solid line graph connecting black rhombus plots shows the measurement results for the LDMOS transistor PD1 (see FIG. 2) of the present embodiment. Further, the measurement result of the gate current Ig in the LDMOS transistor CD2 (see FIG. 38) of the first comparative example is indicated by a broken line.

  Here, the distance Ls between the source side end of the isolation insulating film SIS and the trench HL is indicated by a ratio (in percentage) to the length Lov, which is the amount of coverage of the gate electrode GE with respect to the isolation insulating film SIS. The value of Lov is constant. In this simulation, the distance ratio (Ls + Lt) / Lov is fixed at 27% and the depth ratio Lx / Ly is fixed at 77%.

  In FIG. 17, since the solid line graph is shown at a position higher than the broken line, when the distance Ls of the groove HL is 0.068 to 2.3% of the length Lov, the gate current Ig of the LDMOS transistor PD1 is It can be seen that the value of the gate current Ig of the LDMOS transistor CD2 is increased by about 1/3 digit. Note that Ls / Lov being 0.068% means that the distance Ls corresponds to the thickness of the gate insulating film GIS. The reason why the gate current Ig increases in this way is that the distance Ls is too short, and the electron current passing through the region between the source-side end of the isolation insulating film SIS and the trench HL shown in FIG. This is because it is added to the current Ig. Note that the thickness (film thickness) of the gate insulating film GIS referred to in this application refers to the distance from the upper surface to the lower surface of the gate insulating film GIS in the direction perpendicular to the main surface of the semiconductor substrate SB.

  That is, when the distance Ls is equal to the thickness of the gate insulating film GIS, the gate current Ig increases and the reliability of the semiconductor device decreases, so the distance Ls is larger than the thickness of the gate insulating film GIS. There is a need. Thus, the trench HL is formed away from the end of the isolation insulating film SIS on the source region SC side. Specifically, the end portion on the source region SC side of the trench HL is located at a position farther on the drain region DC side than the end portion on the source region SC side of the isolation insulating film SIS.

  As shown in FIG. 17, when the distance Ls is increased from 2.3% to about 7%, the gate current Ig decreases, and when it is about 7%, the gate current Ig becomes minimum. When the distance Ls of the groove HL is further increased, the gate current Ig starts to increase. This is because the field plate effect is weakened because the gate electrode GE in the trench HL is separated from the source side end of the isolation insulating film SIS having the strongest electric field.

  As can be seen from the breakdown voltage simulation results of FIG. 18, the OFF breakdown voltage BVoff and the ON breakdown voltage BVon are not reduced by changing the distance Ls of the groove HL. FIG. 18 is a graph of device simulation results representing the values of the off breakdown voltage BVoff and the on breakdown voltage BVon with respect to the distance Ls. The solid line graph connecting the black rhombus plots in FIG. 18 and the broken line graph connecting the white triangle plots indicate the OFF breakdown voltage BVoff and the ON breakdown voltage BVon for the LDMOS transistor PD1 of this embodiment (see FIG. 2). It shows the measurement result.

  In FIG. 18, the distance Ls between the source side end of the isolation insulating film SIS and the trench HL shown in FIG. 2 is indicated by a ratio (expressed as a percentage) to the length Lov that is the amount of coverage of the gate electrode GE with respect to the isolation insulating film SIS. The value of the length Lov is constant. In this simulation, the distance ratio (Ls + Lt) / Lov is fixed at 27% and the depth ratio Lx / Ly is fixed at 77%.

  Thus, when determining the value of the distance Ls of the trench HL, it is desirable to set an optimum value so that the gate current Ig becomes as small as possible. For example, if the distance Ls is approximately the same as the thickness of the gate insulating film GIS, the gate current Ig increases as compared with the LDMOS transistor CD2, which is not preferable. The value of the distance Ls needs to be larger than the thickness of the gate insulating film GIS. .

  Further, the end of the trench HL on the drain region DC side is located closer to the source region SC than the end of the gate electrode GE on the drain region DC side. That is, the gate electrode GE is formed so as to protrude from the trench HL toward the drain region DC. That is, in the region on the drain region DC side with respect to the trench HL, the isolation insulating film SIS is interposed between the gate electrode GE and the semiconductor substrate SB immediately below the gate electrode GE. Thus, if the gate electrode GE is not extended to the drain region DC side than the trench HL, the field plate effect cannot be sufficiently obtained, and the electric field is large in the semiconductor substrate SB under the gate electrode GE. Problem arises.

  Therefore, in the present embodiment, the end of the gate electrode GE on the drain region DC side is not terminated on the trench or on the source region SC side but directly on the end of the trench HL on the drain region DC side. Rather than the drain region DC. In other words, the trench HL is formed farther toward the source region SC than the end of the gate electrode GE on the drain region DC side.

  Hereinafter, the results when the length Lov, which is the amount of covering of the gate electrode GE with respect to the isolation insulating film SIS, is changed will be described. FIG. 19 is a graph of device simulation results showing changes in the gate current Ig with respect to the length Lov, which is the amount of covering of the gate electrode GE with respect to the isolation insulating film SIS. Here, the length Lov is indicated by a ratio (expressed as a percentage) to the length Ld of the drift region DFT immediately below the isolation insulating film SIS shown in FIG. 2, and the length Lov of the drift region DFT immediately below the isolation insulating film SIS is shown. The length Ld is constant. In this simulation, for the configuration of the LDMOS transistor PD1 (see FIG. 2), the distance ratio Ls / Ld is 5.0%, the distance ratio Lt / Ld is 15%, and the depth ratio Lx / Ly is 77%. It is fixed. In FIG. 19, a solid line graph connecting black rhombus plots shows the measurement results for the LDMOS transistor PD1 (see FIG. 2) of the present embodiment.

  As shown in FIG. 19, when the length Lov, which is the amount of coverage of the gate electrode GE, is reduced, the electric field at the source side end of the isolation insulating film SIS is increased, and thus the gate current Ig is increased. On the other hand, when the length Lov is less than 50%, the off breakdown voltage BVoff decreases as shown in the breakdown voltage simulation result of FIG. This is because the electric field at the source side end of the isolation insulating film SIS is strengthened, and the breakdown point in the OFF state is from the surface of the semiconductor substrate SB immediately below the drain side end of the gate electrode GE to the source side end of the isolation insulating film SIS. This is because the off breakdown voltage BVoff is determined by the electric field here. The breakdown point refers to a portion where the electric field is maximum, and impact ionization occurs at the breakdown point, thereby generating electron / hole pairs.

  FIG. 20 is a graph showing the relationship between the distance ratio Lov / Ld, the off breakdown voltage BVoff, and the on breakdown voltage BVon. In this simulation, the distance ratio Ls / Ld for the configuration of the LDMOS transistor PD1 (see FIG. 2) The distance ratio Lt / Ld is fixed at 15%, and the depth ratio Lx / Ly is fixed at 77%. The solid line graph connecting the black rhombus plots in FIG. 20 and the broken line graph connecting the white triangle plots indicate the OFF breakdown voltage BVoff and the ON breakdown voltage BVon for the LDMOS transistor PD1 of this embodiment (see FIG. 2). It shows the measurement result.

  The on-resistance Rsp also increases as the length Lov decreases as shown in the simulation result of the on-resistance Rsp in FIG. Therefore, both the provision of the gate electrode GE in the trench HL shown in FIG. 2 and the sufficient length Lov, which is the covering amount of the gate electrode GE, cause the on-resistance Rsp breakdown voltage and the gate current Ig to be reduced. It turns out that it is indispensable for improving the comprehensive characteristics including. That is, the length Lov, which is the amount of covering, needs to be set so that the gate electrode GE sufficiently covers the trench HL.

  Next, the structure of the semiconductor device according to the present embodiment will be described focusing on the influence of the depth Lx of the gate electrode GE in the trench HL on the gate current Ig. FIG. 22 is a graph of device simulation results showing changes in the gate current Ig with respect to the depth Lx of the trench HL shown in FIG. Here, the depth Lx is indicated by a ratio (in percentage) to the thickness Ly of the isolation insulating film SIS, and the thickness Ly is constant. In this simulation and the graphs of FIGS. 23 to 25 described later, the distance ratio Ls / Lov is fixed at 6.8%, and the distance ratio Lt / Lov is fixed at 20%. Further, the value of the gate current Ig when the groove HL is not formed as in the LDMOS transistor CD2 (see FIG. 38) of the first comparative example, that is, when the depth Lx of the groove HL is 0, is shown in FIG. The value indicated by a broken-line circle in FIG.

  As shown in FIG. 22, when the depth ratio Lx / Ly of the trench HL is increased from 0% to 77%, the gate current Ig decreases, and at about 77%, the gate current Ig is minimized. Become. Here, compared with the case where the depth ratio Lx / Ly is 0%, the gate current Ig is reduced by about one digit when the depth ratio Lx / Ly is 33%, and good gate current characteristics can be obtained. it can. The reason why the gate current Ig decreases in this way is that the field plate effect of the gate electrode GE in the trench HL is strengthened. At this time, as shown in the breakdown voltage simulation result of FIG. 23, the OFF breakdown voltage BVoff and the ON breakdown voltage BVon are not reduced.

  FIG. 23 is a graph showing the relationship between the depth ratio Lx / Ly, the off breakdown voltage BVoff, and the on breakdown voltage BVon. The solid line graph connecting the black rhombus plots in FIG. 23 and the broken line graph connecting the white triangle plots indicate the OFF breakdown voltage BVoff and the ON breakdown voltage BVon for the LDMOS transistor PD1 of this embodiment (see FIG. 2). It shows the measurement result.

  As shown in FIG. 22, when the depth ratio Lx / Ly of the trench HL is further increased from about 77%, the gate current Ig starts to increase. This is because, as shown in the simulation results of the electric field shown in FIG. 24 and the impact ionization generation rate shown in FIG. 25, the electric field at the bottom of the groove HL is strengthened and the amount of impact ions is increased. Further, when the depth ratio Lx / Ly of the trench HL is excessively increased from 77%, the isolation insulating film SIS remaining at the bottom of the trench HL becomes thin, and a large gate current Ig flows there, whereby the insulating film There is a concern that it will induce destruction.

  FIG. 24 is a graph showing a simulation result of the electric field on the semiconductor substrate SB side of the boundary line B2-C1 in the cross-sectional view of FIG. FIG. 25 is a graph showing a simulation result of the impact ionization generation rate (IIGR) on the semiconductor substrate SB side of the boundary line B2-C1 in the cross-sectional view of FIG.

  Thus, it is desirable to set the gate current Ig to an optimum value that can be as small as possible also in the depth of the trench HL. For example, the depth ratio Lx / Ly of 96% corresponds to the thickness of the insulating film remaining at the bottom of the trench HL being about the thickness of the gate insulating film GIS. The current Ig is larger than that of the LDMOS transistor CD2 (see FIG. 38) of the first comparative example in which the groove HL is not provided, which is not preferable. That is, it is desirable that the thickness of the isolation insulating film SIS at the bottom of the trench HL is larger than the thickness of the gate insulating film GIS. Therefore, the bottom of the trench HL is located at an intermediate depth of the isolation insulating film SIS, and the trench HL does not penetrate the isolation insulating film SIS.

  Therefore, from the viewpoint of reducing the gate current Ig by weakening the electric field at the bottom of the trench HL, the depth of the trench HL is desirably 33% or more of the thickness of the isolation insulating film SIS. In other words, the depth of the trench HL is desirably 1/3 or more of the thickness of the isolation insulating film SIS. Further, it is desirable that the thickness of the isolation insulating film SIS immediately below the trench HL is larger than the thickness of the gate insulating film GIS.

(Embodiment 2)
In this embodiment, the width of the groove provided on the upper surface of the isolation insulating film of the LDMOS transistor is made smaller than that in the above embodiment, and a plurality of such grooves are provided on the upper surface of the isolation insulating film. This will be described with reference to FIG. FIG. 26 is a plan view showing an LDMOS transistor PD2a which is a semiconductor device of this embodiment, and FIG. 27 is a plan view showing an LDMOS transistor PD2b which is a modification of the semiconductor device of this embodiment. FIG. 28 is a cross-sectional view showing an LDMOS transistor PD2a which is a semiconductor device of the present embodiment, and FIG. 28 is a cross-sectional view taken along the line DD of FIG. Note that the cross-sectional view taken along line EE in FIG. 27 has the same structure as the cross-sectional view shown in FIG.

  The LDMOS transistor PD2a shown in FIG. 28 is a P-channel element as in the first embodiment described with reference to FIG. The LDMOS transistor PD2a of the present embodiment has the same configuration as the LDMOS transistor PD1 (see FIG. 2) described in the first embodiment except that a plurality of trenches HL are arranged. In plan view, the shape of the groove HL may be a slit shape as shown in FIG. 26, or may be a dot shape as shown in FIG. Moreover, the space | interval between slits or between dots may be the same, and may differ.

  FIG. 29 shows a graph comparing the gate current Ig in the LDMOS transistor PD2a of the present embodiment with the gate current Ig of the LDMOS transistor PD1 (see FIG. 2). Here, in the LDMOS transistor PD2a shown in FIG. 26, the shortest distance from the source-side end of the isolation insulating film SIS to the groove HL is Ls, and the entire groove including all the grooves HL in the direction between the source and the drain. The width of the region is represented as Lt. In FIG. 29 and FIGS. 30 and 31 described later, the distance ratio Ls / Lov is fixed at 6.8%, the distance ratio Lt / Lov is fixed at 20%, and the depth ratio Lx / Ly is fixed at 77%.

  As shown in FIG. 29, when comparing the LDMOS transistor PD2a and the LDMOS transistor PD1, if at least the values of Ls and Lt of the LDMOS transistor PD2a are the same as the values of Ls and Lt of the LDMOS transistor PD1, respectively, the LDMOS transistor It can be seen that the same effect as in the first embodiment can be obtained also in the PD 2a. Further, as shown in FIGS. 30 and 31, it can be seen that the values of the off breakdown voltage BVoff, the on breakdown voltage BVon, and the on resistance Rsp are also maintained to be equal to those in the first embodiment. That is, also in the LDMOS transistor PD2a of the present embodiment, the same effect as that of the first embodiment can be obtained.

  FIG. 30 is a graph comparing the off breakdown voltage BVoff and the on breakdown voltage BVon in the LDMOS transistor PD2a and the LDMOS transistor PD1, respectively. In FIG. 30, the off breakdown voltage BVoff is indicated by a solid line graph, and the on breakdown voltage BVon is indicated by a broken line graph. FIG. 31 is a graph comparing the on-resistance Rsp in each of the LDMOS transistor PD2a and the LDMOS transistor PD1. Similar to the LDMOS transistor PD2a shown in FIGS. 26 and 28, the LDMOS transistor PD2b shown in FIG. 27 can achieve the same effects as those of the first embodiment.

  In the present embodiment, since the width of each of the plurality of trenches HL is smaller than that in the first embodiment, the embedding property of the polysilicon serving as the gate electrode GE is improved, and the upper portion of the trench HL is improved. The step difference in the surface of the polysilicon can be reduced. That is, when the width of the trench HL is large, a large recess is formed on the upper surface of the gate electrode GE that embeds the trench HL, and a problem may occur during processing due to the step of the recess. Then, the problem can be prevented from occurring. That is, it is possible to solve a problem assumed when processing the gate electrode GE, for example, a problem that an ARC (Anti-Reflective Coating) used in fine processing remains as a residue in this portion. .

(Embodiment 3)
In this embodiment, the case where a liner insulating film is formed at the bottom of an isolation insulating film of an LDMOS transistor will be described.

  FIG. 32 is a cross-sectional view showing an LDMOS transistor PD3 which is a semiconductor device of the present embodiment. The LDMOS transistor PD3 has the same structure as the LDMOS transistor PD1 (see FIG. 2) according to the first embodiment except that the liner insulating film LIS is formed under the isolation insulating film SIS. Yes. That is, the isolation insulating film SIS is formed in the trench TNC via the liner insulating film LIS. That is, the liner insulating film LIS and the isolation insulating film SIS are sequentially formed on the bottom surface of the trench TNC. The liner insulating film LIS is made of, for example, a silicon nitride film. Even with such a configuration, the same effect as in the first embodiment can be obtained.

  Here, the liner insulating film LIS also constitutes an isolation insulating film. That is, in this embodiment mode, the isolation insulating film has a stacked structure including two insulating films. The bottom surface of the trench HL reaches the boundary between the two insulating films, that is, the boundary between the isolation insulating film SIS and the liner insulating film LIS. That is, the trench HL reaches the liner insulating film LIS, and the bottom surface of the trench HL does not reach the bottom surface of the isolation insulating film including the isolation insulating film SIS and the liner insulating film LIS. In other words, when the isolation insulating film has a structure in which a plurality of insulating films are stacked, the trench HL reaches the lowermost insulating film among the plurality of insulating films constituting the isolation insulating film.

  In the present embodiment, further, when anisotropic etching for forming the trench HL on the upper surface of the isolation insulating film SIS is performed, the formation of the trench HL is caused by a difference in etching selectivity between the isolation insulating film SIS and the liner insulating film LIS. Since it can be relatively easily stopped immediately above the liner insulating film LIS, the depth Lx of the trench HL can be controlled by the thickness of the liner insulating film LIS. Therefore, the controllability of the depth of the trench HL is improved, and the reduction of the gate current Ig can be realized relatively stably.

(Embodiment 4)
FIG. 33 shows a cross-sectional view of an LDMOS transistor PD4 which is a semiconductor device of the present embodiment. The LDMOS transistor PD4 is obtained by changing the LDMOS transistor PD1 (see FIG. 2) of the first embodiment to an N-channel type. Also in the present embodiment, a high field plate effect is obtained by the gate electrode GE embedded in the trench HL. Therefore, as shown in the simulation result of FIG. 34, the LDMOS transistor PD4 generates impact ionization by reducing the electric field compared to the N-channel type LDMOS transistor CD1 (see FIG. 37) of the first comparative example. The well current Iw reflecting the magnitude of the rate (IIGR) is reduced by about one digit. Therefore, in the semiconductor device of this embodiment, the variation of the on-resistance Rsp during hot carrier stress can be suppressed, so that the reliability of the semiconductor device can be improved.

  Here, as shown in the simulation result of FIG. 35, the OFF breakdown voltage BVoff and the on breakdown voltage BVon are not reduced by providing the groove HL, and the ON resistance is reduced by 6.0% as shown in the simulation result of FIG. There is an effect that.

  FIG. 34 is a graph comparing the well current Iw in each of the LDMOS transistor PD4 and the LDMOS transistor CD1. FIG. 35 is a graph comparing the off breakdown voltage BVoff and the on breakdown voltage BVon in the LDMOS transistor PD4 and the LDMOS transistor CD1, respectively. In FIG. 35, the off breakdown voltage BVoff is indicated by a solid line graph, and the on breakdown voltage BVon is indicated by a broken line graph. FIG. 36 is a graph comparing the on-resistance Rsp in each of the LDMOS transistor PD4 and the LDMOS transistor CD1. In each of FIGS. 34 to 36, the plot of the position indicated as having no groove HL is the value of the LDMOS transistor CD1, and the plot of the position indicated as having the groove HL is the value of the LDMOS transistor PD4.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in each of the above embodiments, the isolation insulating film of the LDMOS transistor has been described as having an STI structure, but the isolation insulating film may have a LOCOS structure.

BVoff OFF breakdown voltage BVon ON breakdown voltage CD1 to CD4 LDMOS transistors CN1 to CN3 Contact plug DC Drain region DFT Drift region GE Gate electrode GIS Gate insulating film HL Groove HM Hard mask HWL Well region Ig Gate current INC Wiring IS Interlayer insulating film Iw Well current LIS Liner insulating film Lt Width Ls of trench HL Distance between source side end of isolation insulating film SIS and trench HL Lov Length Ld which is the amount of gate electrode GE covered with isolation insulating film SIS of drain region immediately below isolation insulating film SIS Length Lx Depth Ly of trench HL Thickness of isolation insulating film SIS PD1 to PD4 LDMOS transistor SB Semiconductor substrate SC Source region SIS Isolation insulating film TNC Groove WC Well region WL Well region

Claims (5)

A semiconductor substrate;
A pair of first conductivity type source region and the first conductivity type drain region formed on the main surface of the semiconductor substrate;
An isolation insulating film embedded in an isolation trench formed in the main surface of the semiconductor substrate between the source region and the drain region;
A gate insulating film formed on the semiconductor substrate between the isolation insulating film and the source region;
Between the source region and the drain region, a gate electrode formed over the gate insulating film and directly over the isolation insulating film;
A drift region of the first conductivity type formed in the semiconductor substrate under the isolation insulating film, one end of which is located immediately below the gate insulating film;
A groove formed on an upper surface of the isolation insulating film and having a portion of the gate electrode embedded therein;
Have
An interval between the gate electrode and the drain region is larger than an interval between the gate electrode and the source region,
The trench is disposed away from an end of the isolation insulating film on the source region side and spaced from an end of the gate electrode on the drain region side toward the source side,
The bottom surface of the groove is located at an intermediate depth of the isolation insulating film,
In plan view, the direction in which the source region and the drain region are arranged is a first direction, and the direction orthogonal to the first direction is a second direction,
The width of the gate electrode in the second direction is larger than the length of the trench in the second direction. The semiconductor device according to claim 1,
The depth of the groove is 1/3 or more of the thickness of the isolation insulating film,
A distance between the bottom of the trench and the semiconductor substrate immediately below the trench is greater than the thickness of the gate insulating film. The semiconductor device according to claim 1,
The distance between the trench and the end of the isolation insulating film on the source region side is a semiconductor device, which is larger than the thickness of the gate insulating film. The semiconductor device according to claim 1,
A semiconductor device, wherein a plurality of the grooves are provided on the upper surface of the isolation insulating film. The semiconductor device according to claim 1,
The isolation insulating film has a configuration in which a plurality of insulating films are stacked,
The trench is a semiconductor device that reaches a lowermost insulating film among the plurality of insulating films.

Images