JP6931708B2 - How to evaluate semiconductor structure - Google Patents

Description

Cross-references to related applications This application claims the interests of US Provisional Patent Application 62 / 457,699 filed on February 10, 2017 and incorporates all of them as forming part of this specification. ..

The field of the present disclosure evaluates the quality of a semiconductor structure having a charge capture layer, eg, for determining whether the structure is suitable for use in a radio frequency device, eg, for determining charge capture layer efficiency. Regarding the method. The method of the present invention comprises measuring electrostatic parameters while generating charge carriers by exposing them to light. The electrostatic parameters are used to determine the charge capture layer efficiency.

Semiconductor wafers include, for example, semiconductor devices such as integrated circuit (IC) chips, silicon-on-insulator (SOI) wafers, and radio frequency SOI (radio factory-SOI (RF-SOI) wafers). Generally, semiconductor wafers used for RF-SOI include high resistance substrates that are sensitive to the formation of highly conductive inversion or storage layers. Inversion or storage layers interfere with the performance of semiconductor devices.

In some processes, layers such as polycrystalline silicon layers are deposited on the surface of semiconductor wafers to provide density charge capture, thereby suppressing the formation of highly conductive inversions or storage layers. For example, the layer can be deposited on a surface that forms an interface between a high resistance substrate and a buried oxide (BOX) to impede the movement of charges across the interface.

The effectiveness of charge capture of semiconductor structures includes crystal defect density, polycrystalline silicon structure (grain size), polycrystalline silicon deposition (CVD) conditions, interface state between polycrystalline silicon and silicon substrate, doping level, resistivity, and interface. It depends on multiple factors, including conditions, surface contamination, and heat treatment applied during equipment manufacturing. To ensure proper charge capture efficiency, various technical parameters are carefully controlled and monitored during the manufacture of charge capture layer semiconductor wafers for RF equipment applications. The measurement of charge capture efficiency is an important component in quality control in the manufacture of charge capture layer semiconductor structures.

Conventional methods for measuring charge capture efficiency of semiconductor wafers are based on testing the performance of radio frequency (RF) devices. The RF device is built on top of the wafer and then tested. The process of manufacturing RF equipment involves many technical steps and is time consuming. The quality feedback of the wafer process is delayed, which incurs significant throughput and yield losses in wafer manufacturing.

There is a continuous need for methods of assessing the quality of semiconductor structures, such as for the use of radio frequency devices, especially those that are relatively quick, non-destructive and do not require RF device manufacturing.

This portion is intended to introduce the reader into various aspects of the art with respect to the various aspects of the present disclosure described and / or claimed below. We believe that this discussion will help provide background information to the reader in order to facilitate a better understanding of the various aspects of this disclosure. Therefore, it should be understood that these references are in this reference and are not read as confessions of the prior art.

One aspect of the present disclosure relates to a method of assessing the quality of a semiconductor structure. The semiconductor structure has a front surface and a back surface that is approximately parallel to the front surface. The semiconductor structure includes a charge capture layer. The structure is illuminated to generate charge carriers in the semiconductor structure. The electrostatic parameters of the structure are measured during or after exposure to the structure to generate charge carriers in the semiconductor structure. The electrostatic parameter is selected from the group consisting of (1) the capacitance of the structure and (2) the potential difference between the front of the semiconductor structure and the electrodes. The quality of a semiconductor structure is evaluated based on the measured electrostatic parameters of the structure.

Another aspect of the disclosure relates to a method of assessing the quality of a semiconductor structure. The semiconductor structure has a front surface and a back surface that is approximately parallel to the front surface. The semiconductor structure includes a charge capture layer. The initial electrostatic parameters of the structure are measured. The electrostatic parameter is selected from the group consisting of (1) the capacitance of the structure and (2) the potential difference between the front of the semiconductor structure and the electrodes. Charge carriers are generated in the semiconductor structure. The excitation electrostatic parameters of the structure are measured during or after the generation of charge carriers in the structure. The excitation electrostatic parameter is the same as the initial electrostatic parameter.

There are various improvements that have the characteristics described with respect to the aspects described above in the present disclosure. Further features are also incorporated into the aforementioned aspects of the present disclosure. These improvements and additional features exist individually or in any combination. For example, the various features discussed below with respect to any of the described embodiments of the present disclosure can be incorporated into any of the above aspects of the present disclosure, alone or in any combination.

It is the schematic of the silicon on insulator (SOI) structure which has a charge capture layer. Includes an energy band diagram in the SOI structure without (or ineffective) charge capture layer. Includes an energy band diagram in an SOI structure with a charge capture layer. The evaluation result in the bulk wafer having the charge capture layer of Example 3 is drawn. The evaluation result in the SOI structure having the charge capture layer of Example 4 is drawn. Polysilicon deterioration evaluation vs. annealing calorific value is drawn. SPV signal map pattern Draw origin vs. CVD tool design and anti-iron contamination level. The SPV signal correlation for RF HD2 evaluation was drawn. It is a schematic diagram of the SPV characterization method (CTLX). Represents SPV tool correlation based on SPV laser power calibration. Draw a second harmonic (HD2) pair measured voltage.

Corresponding reference numerals indicate corresponding parts throughout the drawings.

The present disclosure relates to, for example, a method of assessing the quality of a semiconductor structure for determining the efficiency of a charge trapping layer for determining the suitability of a structure for use in radio frequency devices. Suitable structures evaluated include a charge trapping layer and a bulk layer having a laminated structure, such as a silicon on insulator structure having a charge trapping layer. A typical structure 1 is shown in FIG. 1 and is disposed between the handle layer 5 (also referred to as the handle “wafer” 5), the device layer 9 (typically a silicon device layer) and the device layer 9 and the handle layer 5. Includes a dielectric layer or an "embedded oxide" layer 13. The charge capture layer 17 is arranged between the handle layer 5 and the dielectric layer 13. The structure 1 has a back surface 30 that is approximately parallel to the front surface 25 and the front surface 25 and perpendicular to the central axis of the structure 1.

Charge-capturing silicon-on-insulator structures are prepared by any of the known methods for preparing such structures. Methods of producing multilayer structures and, in particular, silicon-on-insulator structures and silicon-on-insulator structures are generally known to those of skill in the art (eg, US Pat. No. 5,189,500, 5,436,175 and 6,790). , 747, each of which is incorporated for all relevant and consistent purposes as forming part of this specification). In a typical process for creating a multi-layer structure, two separate structures are prepared and joined along the junction boundary, and the donor structure, unlike the junction boundary, is formed by an injection technique, a separation surface (ie, ie). Etched or split into thin layers (ie cleaved) along the "cleavage surface"). One structure is typically referred to as the "handle" structure and the other is typically referred to as the "donor" structure. After the process, the resulting laminated semiconductor structure includes a device layer and a handle layer that supports the device layer.

The SOI structure includes an additional dielectric layer 13 disposed between the handle wafer 5 and the device layer 9. The dielectric layer is formed on the bonding surface of the donor and / or handle structure before the donor and handle are bonded. The dielectric layer 13 is, for _{example, SiO 2, Si 3 N 4} , etc. material containing aluminum oxide or magnesium oxide, is any electrically insulating material suitable for use in the SOI structure. In some embodiments, the dielectric layer 13 is SiO ₂ (ie, the dielectric layer is essentially composed of SiO ₂ ). However, it should be noted that in some cases it is preferable to use a material for the dielectric layer having a melting point higher than the melting point of _{pure SiO 2 (ie higher than 1700 ° C.).} Examples of such materials are silicon _{(Si 3 N} 4) nitride, aluminum oxide, magnesium oxide.

The handle wafer can comprise a material selected from the group consisting of silicon, silicon carbide, silicon germanium, gallium arsenide, gallium nitride, indium phosphide, indium gallium arsenide, germanium, and combinations thereof. In some embodiments of the present disclosure, the donor and / or handle wafer used to create the SOI structure is composed of single crystal silicon and is obtained by slicing the wafer from an ingot formed by the chokralski process. Be done. Handle wafers and / or donor wafers (and the resulting SOI structure) are of any diameter suitable for use by those skilled in the art, including, for example, 200 mm, 300 mm, larger than 300 mm, or even 450 mm diameter wafers.

In general, the handle layer has any thickness that allows delamination of the device layer and can provide sufficient structural integrity. Generally, the handle layer has an average thickness of at least about 100 μm, typically at least about 200 μm, and about 100 to about 900 μm, or even 500 to about 800 μm. In some embodiments, the dielectric layer, eg, the embedded oxide layer, has a thickness of at least about 10 nm, such as about 10 nm to about 10,000 nm, about 10 nm to about 5000 nm, or about 100 nm to about 800 nm. Generally, the device layer is 0.01 to 20 μm thick, for example 0.05 to 20 μm.

The charge capture layer 17 is formed by depositing a semiconductor material on the exposed front surface of the single crystal semiconductor handle wafer before bonding. The thickness of the charge capture layer 17 is from about 0.3 μm to about 5 μm, for example from about 0.3 μm to about 3 μm, for example from about 0.3 μm to about 2 μm or from about 2 μm to about 3 μm. The handle wafer preferably has an oxidized front layer exposed prior to deposition. A semiconductor material suitable for use in forming a charge capture layer in a silicon-on-insulator device can adequately form a high defect layer in the manufactured device. Such materials are polycrystalline or amorphous semiconductor materials, all of which are polycrystalline or amorphous silicon (Si), silicon germanium (SiGe), carbon-doped silicon (SiC), and germanium (Ge). Can include.

As referred to herein, "polycrystalline" silicon means a material containing small silicon crystals with random crystal orientation. The polycrystalline silicon grain has a small size of about 20 nm. Generally, when the size of the crystal grains of polycrystalline silicon is small, the defect property of the charge trapping layer is high. Amorphous silicon has a non-crystalline polymorphic form of silicon and lacks short-range and long-range order. Silicon grains with a crystallinity of about 10 nm or less are also considered to be amorphous in nature. The charge capture layer has a resistivity of at least about 1000 Ωcm or at least about 3000 Ωcm, for example, about 1000 Ωcm to about 100,000 Ωcm or about 1000 Ωcm to about 10000 Ωcm.

The optionally oxidized material for depositing on the front surface of the single crystal semiconductor handle wafer is deposited by means known in the art. For example, semiconductor materials include metalorganic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), chemical vapor deposition, and chemical vapor deposition (PVD). Growth (low pressure chemical vapor deposition (LPCVD)), plasma chemical vapor deposition (PECVD), or molecular beam epitaxy can be carried out by metalorganic vapor deposition (PECVD). .. Silicon precursors for LPCVD or PECVD include, among other things, methylsilane, silicon hydride (silane), trisilane, disilane, pentasilane, neopentasilane, tetrasilane, dichlorosilane (SiH ₂ Cl ₂ ), silicon tetrachloride (SiCl ₄ ). include. For example, polycrystalline silicon is deposited on the surface oxide layer by pyrolyzing _{silane (SiH 4} ) in the range of about 550 ° C to about 690 ° C, for example at a temperature of about 580 ° C to about 650 ° C. Chamber pressures range from about 70 to about 400 mTorr.

Amorphous silicon is generally deposited by plasma chemical vapor deposition (PECVD) at temperatures in the range of about 75 ° C to about 300 ° C. Silicon-germanium, particularly amorphous silicon-germanium, is deposited at temperatures up to about 300 ° C. by chemical vapor deposition methods containing organogermanium compounds such as isobutyl germanium, alkyl germanium trichloride, and dimethylamino germanium trichloride. Carbon-doped silicon is deposited by thermal plasma chemical vapor deposition in an epitaxial reactor using precursors such as silicon tetrachloride and methane. Suitable carbon precursors in CVD or PECVD include, among other things, methylsilane, methane, ethane, ethylene. In the LPCVD deposition method, methylsilane is a particularly preferred precursor as it provides both carbon and silicon. In the PECVD deposition method, preferred precursors include silane and methane. In some embodiments, the silicon layer can contain a carbon concentration of at least about 1%, eg, about 1% to about 10%, on an atomic basis.

In some embodiments, the semiconductor handle layer 5, such as a single crystal silicon handle wafer, comprises a region near the charge capture layer 17 having a relatively high minimum bulk resistivity or containing such a high resistivity. .. High resistance wafers are generally sliced from single crystal ingots grown by the Czochralski method or the float zone method. In some embodiments, the handle layer 5 is doped to have a minimum bulk resistivity of at least 100 Ωcm or at least 500 Ω cm, at least 1000 Ω cm or even at least 10000 Ω cm. Methods of preparing high resistance wafers are known in the art, and such high resistance wafers are commercial suppliers such as, for example, SunEdison Semiconductor (St. Peters, Missouri, formerly MEMC Electrical Materials). Obtained from. The high resistivity region of the handle wafer (as opposed to a wafer with high resistivity overall) is incorporated for all relevant and consistent purposes as forming part of this specification. It can be formed by the method disclosed in 846, 493.

According to embodiments of the present disclosure, a semiconductor structure having a charge trapping layer (eg, a bulk wafer or silicon on insulator structure) is a charge trapping layer (eg, for suitability for use in radio frequency (RF) equipment). Evaluated to determine efficiency. Electrostatic parameters are measured while generating charge carriers by shining light.

The charge trapping layer of a generally evaluated structure (bulk wafer or SOI structure) is uninterrupted, i.e., the structure has no device features such as trenches, vias, etc. on the surface of the silicon device layer and is by conventional evaluation methods. It does not include other features used (eg, coplanar waveguides on the surface of silicon or box layers).

Appropriate electrostatic parameters measured by the embodiments of the present disclosure include (1) the capacitance of the structure and (2) the potential difference such as the potential difference between the front surface 25 (FIG. 1) and the electrode 35 (FIG. 9) of the semiconductor structure. include.

Charge carriers are generated by directing any light that can generate electrons to the silicon in the structure. For light with wavelengths less than about 1.1 μm, the wafer is exposed to ^{an intensity of at least about 50 mW / cm 2} , and in other embodiments at least about 100 mW / cm ² or even about 200 mW / cm ^2. .. It should be noted that light at wavelengths longer than about 1.1 μm is also used. However, in some embodiments, the light is irradiated with high power or for a long period of time to light of a short wavelength (eg, at least about 500 mW / cm ² or even at least about 1000 mW / cm ² ). In one or more embodiments, the light is applied by a laser or heating lamp located in a belt heating furnace or a rapid thermal annealing device. It is preferable to illuminate the entire surface of the structure with respect to the inflowing charge carriers. However, in one or more embodiments of the present disclosure, only the front surface of the structure is illuminated.

One or more laser wavelengths are used in embodiments where the laser is used to shed light on the wafer to generate charge carriers. For example, one wavelength is selected to extend to the charge capture layer (eg, 670 nm +/- 300 nm) and a second wavelength is selected to extend to the substrate (1015 nm +/- 400 nm). In this regard, in other embodiments, 3, 4, 5, 6, 7, 8 or additional wavelengths can be used, for example, for a particular depth or range of structure.

In some embodiments, the electrostatic parameters (eg, voltage or capacitance) are normalized to electrostatic parameters at a particular trap density (eg, to bulk wafers without capture layers or SOI structures). Differences in normalized electrostatic parameters can be translated into "capture efficiency" (eg, normalized to zero capture conditions for structures without capture layers.

In some embodiments, baseline electrostatic parameters are defined and capacitance or potential tolerance limits (eg, maximum) are determined. The measured differences in each evaluated structure are compared to a baseline that determines if the structure is suitable for use (eg, use of radio frequency equipment).

Electrostatic parameters are measured at multiple positions on the wafer (eg, first position, second position, third position, etc.) and the parameters are used to determine the suitability of the structure for the use of RF equipment. Is averaged to. Alternatively or in addition, capacitance or potential can be used to create a state map of the structure.

In some embodiments, the initial or "pause" electrostatic parameters of the structure are measured first. The "excited" state of the structure's electrostatic parameters is measured during or after the generation of charge carriers in the structure. The difference between the initial electrostatic parameter and the excited electrostatic parameter is determined and used to determine the suitability of the structure for use in RF equipment.

Initial electrostatic parameters are measured while the structure is in a "pause" state, i.e., while it is not generating charge carriers. The electrostatic state is measured while the structure is not exposed to light. When the initial values of capacitance and potential are measured, charge carriers are generated in the semiconductor structure. The electrostatic parameters measured in the initial, dormant state as soon as charge carriers are generated are measured again during or shortly after charge carriers are generated. The difference between the initial electrostatic parameter and the excited electrostatic parameter is determined to assess the suitability of the structure for the use of RF equipment. As described in Examples 1 and 2, a small difference in capacitance or potential indicates that the charge capture layer of the structure is good and vice versa (ie, the suitability of the RF device is good).

As mentioned above, the characterization of the charge capture layer (CTL) is based on the measured voltage signal (ie, surface light voltage or SPV). The evaluation is performed after excitation of the minority carriers caused by a laser of a particular wavelength. The wavelength of the laser is chosen to penetrate the CTL layer (wavelength 657 nm, etc. and / or longer wavelengths). The same wavelength can be used to evaluate the sample over time so that the data can be compared. The same light injection level is also used (in relation to the assigned laser power) to fix the method to be repeatable / repeatable.

SPV signal evaluation uses conventional SPV tools to perform at least two wavelength injections (eg, 657 nm and 1013 nm). The measured SPV signal is equal to / proportional to the actual recombination efficiency of the polysilicon-based CTL. Generally, the lower the SPV signal, the higher the CTL recombination efficiency. In the case of polysilicon layer degradation caused by recrystallization and / or metal contamination, the SPV signal is expected to increase and show low recombination efficiency of the CTL layer (see FIG. 9).

The structure is mounted on a grounded platform during SPV characterization. As shown in FIG. 9, the SPV tool includes an electrode 35 (eg, a transparent electrode) located just above the front surface 25 of structure 1. The potential difference between the front surface 25 and the electrode 35 of the structure relating to grounding is then measured.

The SPV tools used for evaluation are calibrated using previously measured monitor samples. Tool calibration is useful in assessing layers with different tools on separate production lines. SPV tool calibration uses SPV laser power parametric scans to measure monitor samples under different injection (photoexcitation) conditions. Different fixed injection levels per tool are used to have the same CTL layer SPV tool evaluation results. FIG. 10 shows two SPV tool calibrations based on SPV laser power calibration.

In some embodiments, the use of a long wavelength SPV laser (penetrating a polysilicon layer through a high resistance handle wafer bulk, such as 1013 nm) correlates the relevant SPV signal to the actual resistivity of the handle wafer. Improve. The resistivity of the handle wafer (along with the CTL layer recombination efficiency) significantly affects the second harmonic (HD2) of the RF device (see FIG. 11).

In general, each structure of a plurality of structures is unstructured (eg, to create a radio frequency device) by measuring the initial and excitation electrostatic parameters of each structure at one or more positions of each structure. Evaluated to determine if it is passed or qualified. Differences in electrostatic parameters in each structure are compared to baseline differences to determine if the semiconductor is acceptable, for example for the use of radio frequency devices. In other embodiments, one structure of a batch of structures can be evaluated to determine the suitability of that batch for use in RF applications.

After evaluating the structure, the structure can be further processed, for example by forming a radio frequency device of the structure.

The methods of the present disclosure have several advantages as compared to conventional methods of evaluating structures, such as, for example, methods of evaluating structures with charge capture layers for the suitability of radio frequency devices. The method of evaluation does not include the manufacture of RF equipment or the production of additional structures on the surface of the equipment layer or structure. This allows it to be executed relatively quickly and without destroying the structure being evaluated. The evaluation method is performed at multiple positions in the structure and averaged to account for in-wafer variation of electrostatic parameters. The evaluation method is performed on each wafer in a batch of wafers to account for variations between wafers in the batch.

The electrostatic parameters (eg, SPV signals) correlate well with the post-deposition thermal annealing that affects the polysilicon deposition conditions and the CTL layer properties of the foundation. The results obtained correlate well with the commonly used second harmonic (HD2) evaluation in RF.

The evaluation methods of the present disclosure are generally fast conversion, non-destructive, high resolution and can be performed on samples after any process step to monitor CTL layer quality. After at least two (a) polysilicon deposits and (b) the upper silicon layer has been removed, it can be measured in the sample in the final step of the line.

(Example)
The process of the present disclosure is further described by the following examples. These examples should not be considered in a limited sense.

(Difference between potential and capacitance of structure without charge capture layer)
The potential difference before and between charge carriers in the SOI structure without (or ineffective CTL) charge capture layer is shown in the energy band diagram in FIG. The positive charge of the BOX induces the depletion and inversion layer of the high resistance substrate (FIG. 2A). A related energy band diagram before charge carriers are generated is shown in FIG. 2B. The difference between the front and back surface (grounded) surface potentials is V ₀ . Illuminating the structure with intense light produces dense optical carriers (holes and electrons) that change the energy band at the BOX substrate boundary towards a flat band state (FIG. 2C). Therefore, the charge at this boundary is redistributed, causing a change in the electric field that alters the energy band of the upper silicon. As a result, the potential difference V ₁ on the front and back surfaces can also change and reverse the charge. A large difference between V ₁ and V ₀ indicates a lack of charge trapping layer in the SOI structure.

The effective capacitance of the SOI structure is set by the BOX and the depletion layer of the substrate (Fig. 2D). Illuminating the structure with intense light fills the depletion region with high-density optical carriers and overcomes the depletion. As a result, the effective SOI wafer capacity is changed to that which is mainly controlled by the BOX (Fig. 2E). Significant changes in capacitance indicate a lack of charge capture layer in the SOI structure.

(Difference between potential and capacitance of the structure including the charge capture layer)
The potential difference between before and after the generation of charge carriers in an SOI structure with an efficient charge capture layer is schematically shown in the energy band diagram of FIG. The positive charge of the BOX is completely compensated for in the negative charge state of the charge capture layer (CTL) (FIG. 3A). A related energy band diagram with no charge generation is shown in FIG. 3B. The energy band of the substrate is flat. The difference between the front and back side (grounded) surface potentials is V ₀ . When the structure is illuminated with intense light, the mid-gap energy level is inherently close to the Fermi level, so the energy band of high-resistance (light-doped) semiconductors cannot be significantly changed. Generates holes and electrons). Therefore, the charge at this boundary remains almost the same and the energy band of the upper silicon is affected relatively small (Fig. 3C). The difference V1 in surface potential between the front surface and the back surface side does not change much. A small difference between V ₁ and V ₀ indicates efficient charge capture of the SOI structure at the BOX substrate boundary.

The effective capacitance of the SOI structure with an efficient charge capture layer (FIG. 3A) is dominated by the BOX alone (FIG. 3D). Illuminating the structure with intense light fills a light-doped substrate with a high density optical carrier that does not significantly change the band structure of the semiconductor element of the SOI. Therefore, the effective wafer capacity does not change significantly and is further related to BOX (Fig. 3E). The low capacitance change indicates efficient charge capture of the SOI substrate.

(Evaluation of quality of bulk wafers for RF equipment applications)
Bulk wafers with a charge capture layer on their surface were evaluated with a surface photovoltage (SPV) tool. Evaluation recipes (but not limited to) included: (A) SPV laser wavelengths at 657 nm and 1013 nm (b) SPV laser power adjusted to use optimal levels in measured samples (c) Photovoltage reading analysis at 657 nm lasers (adjusted for each measured sample type) Excitation at a particular laser power determined) (d) RF HD2 and HD3 CTL performance predicted based on actual SPV readings that correlate with evaluation results (e) 657nm laser excitation is made of polysilicon with the addition of a shallow semiconductor wafer layer. It was chosen to maintain a layer-limited penetration depth. (F) The penetration depth was chosen to avoid silicon bulk impact. (Rather operated by silicon doping levels and by metal contamination levels) (g) The sample design was a CTL polysilicon layer with or without a P-type high resistance substrate and thermal oxides.

The evaluation results in the sample after polysilicon deposition are shown in FIG.

(Evaluation of RF wafer quality for equipment applications)
SOI structures with charge capture layers were evaluated with a surface photovoltage (SPV) tool. The evaluation protocol of Example 3 was used in the sample design of P-type high resistance substrate + CTL polysilicon layer + BOX + upper Si layer. The evaluation results in the sample after polysilicon deposition are shown in FIG.

(A further example of the embodiments of the present disclosure of FIG. 6-8)
Figure 6: polysilicon deterioration evaluation vs. annealing heat quantity. The SPV signal evaluation technique was performed [657 nm SPV laser excitation]. It is completely lowered after cumulative annealing at 1100 ° C. for 5 hours.

Figure 7: SPV signal map pattern origin vs. CVD tool design and vs. Fe contamination level. For samples after a polysilicon deposition pattern, it depends on the CVD tool design. For samples with an upper Si-on pattern, it is determined by Fe contamination.

Figure 8: SPV signal correlation to RF HD2 evaluation. The results relate to the specific CTL SOI sample design and preparation procedure.

As used herein, the terms "about", "substantially" (substantially), "essentially" and "approximately" are size, concentration, temperature or When used with a range of other physical or chemical properties or features, including variations that exist at the upper and / or lower limits of the range of properties or features, including variations caused by, for example, rounding, measurement methods or other statistical variations. Means.

When introducing an element of the present disclosure or an embodiment of the present disclosure, the articles "one" (a), "one" (an), "that" (the), and "said" are one or more. There is an intention to mean that there is an element of. The terms "comprising," "inclusion," "contining," and "having" mean that there can be additional elements in addition to those described. I have an intention to do it. The use of terms that indicate a particular orientation (eg, "top" (top), "bottom", "side", etc.) is for convenience of description and is any of the articles described. Does not require a specific orientation.

Various changes may be made in the above configurations and methods without departing from the scope of the present disclosure, and all matters contained in the above description and shown in the accompanying drawings are to be construed as explanations and are not intended to be limiting. It is intended to be interpreted as not.

Claims (13)

It is a method of evaluating the quality of semiconductor structures.
The semiconductor structure has a front surface and a back surface substantially parallel to the front surface, and includes a charge trapping layer.
The method is
A step of shining light on the semiconductor structure in order to generate charge carriers in the semiconductor structure,
A step of measuring an electrostatic parameter of the semiconductor structure while or after irradiating the semiconductor structure with light to generate charge carriers in the semiconductor structure, wherein the electrostatic parameter is (1) the semiconductor structure. capacity and (2) is selected from the group consisting of a potential difference between the front and the electrode of the semiconductor structure, comprising the steps of measuring,
A step of evaluating the charge capture efficiency of the semiconductor structure to determine the suitability of the semiconductor structure for use in a radio frequency device based on the measured electrostatic parameters of the semiconductor structure.
How to prepare. The method of claim 1, wherein the measured electrostatic parameters are normalized to the measured electrostatic parameters of a semiconductor structure that does not include a charge capture layer. The method of claim 1, wherein the measured electrostatic parameters are compared to baseline parameters to evaluate the charge capture efficiency of the semiconductor structure. The method according to claim 1, wherein the electrostatic parameter is the capacitance of the semiconductor structure. The method of claim 1, wherein the electrostatic parameters are measured during the generation of charge carriers. A method for evaluating the quality of multiple semiconductor structures.
The semiconductor structure has a front surface and a back surface substantially parallel to the front surface, and includes a charge trapping layer.
The method is
A step of shining light on the semiconductor structure in order to generate charge carriers in the semiconductor structure,
A step of measuring an electrostatic parameter of the semiconductor structure while or after irradiating the semiconductor structure with light to generate charge carriers in the semiconductor structure, wherein the electrostatic parameter is (1) the semiconductor structure. capacity and (2) selected from the group consisting of a potential difference between the front and the electrode of the semiconductor structure, comprising the steps of measuring,
A step of evaluating the charge capture efficiency of the semiconductor structure based on the measured electrostatic parameters of the semiconductor structure, and
With the step of forming the radio frequency device only in the semiconductor structure determined to be appropriate,
A method comprising the steps of evaluating each semiconductor structure by means of. The semiconductor structure includes a handle wafer, a dielectric layer, a charge capture layer arranged between the dielectric layer and the handle wafer, and a silicon device layer.
The method according to claim 6, wherein the dielectric layer is arranged between the silicon device layer and the charge capture layer. The method of claim 7, wherein the handle wafer has a resistivity of at least about 1000 Ωcm. It is a method of evaluating the quality of semiconductor structures.
The semiconductor structure has a front surface and a back surface substantially parallel to the front surface, and includes a charge trapping layer.
The method is
A step of measuring the initial electrostatic parameter of the semiconductor structure, the electrostatic parameter consists of a group consisting of (1) the capacitance of the semiconductor structure and (2) the potential difference between the front surface of the semiconductor structure and the electrodes. Selected steps to measure and
A step of generating charge carriers in the semiconductor structure at a fixed injection level,
A step of measuring the excitation electrostatic parameter of the semiconductor structure while or after generating charge carriers in the semiconductor structure, wherein the excitation electrostatic parameter is the same as the initial electrostatic parameter. How to prepare for. A step of determining the difference between the initial electrostatic parameter and the excitation electrostatic parameter.
The method according to claim 9. 10. The method of claim 10, wherein the difference is compared to a baseline difference to determine if the semiconductor structure is suitable for use in a radio frequency device. With steps to evaluate the quality of multiple semiconductor structures
Each semiconductor structure is
A step of measuring the initial electrostatic parameter of the semiconductor structure, wherein the initial electrostatic parameter is a group consisting of (1) the capacitance of the semiconductor structure and (2) the potential difference between the front surface of the semiconductor structure and the electrode. Select from the steps to measure and
The step of generating charge carriers in the semiconductor structure and
A step of measuring the excitation electrostatic parameter of the semiconductor structure while or after generating charge carriers in the semiconductor structure, wherein the excitation electrostatic parameter is the same as the initial electrostatic parameter. ,
The step of determining the difference between the initial electrostatic parameter and the excitation electrostatic parameter,
In order to evaluate the semiconductor structure, a step of comparing the difference between the initial electrostatic parameter and the excitation electrostatic parameter in each of the semiconductor structures with a baseline difference, and
With the step of forming a radio frequency device only in the semiconductor structure determined to be appropriate,
9. The method of claim 9. It is a method of evaluating the quality of semiconductor structures.
The semiconductor structure has a front surface and a back surface substantially parallel to the front surface, and includes a charge trapping layer.
The method is
A step of measuring the initial electrostatic parameter of the semiconductor structure, wherein the initial electrostatic parameter is a group consisting of (1) the capacitance of the semiconductor structure and (2) the potential difference between the front surface of the semiconductor structure and the electrode. Selected from the steps to measure and
A step of generating charge carriers in the semiconductor structure by shining light on the semiconductor structure at two different wavelengths with one or more lasers.
A step of measuring the excitation electrostatic parameter of the semiconductor structure during or after generating charge carriers in the semiconductor structure, wherein the excitation electrostatic parameter is the same as the initial electrostatic parameter. When,
How to prepare.

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