JP5454298B2 - Manufacturing method of semiconductor substrate - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor substrate, and more specifically to a method for manufacturing a semiconductor substrate capable of manufacturing a semiconductor substrate having a metal impurity concentration in the substrate lower than that of a conventional substrate at a high yield.

  In recent years, an epitaxial substrate that has come to be used as a substrate for an image sensor such as a CCD or CIS has a single crystal thin film formed on a base substrate. This epitaxial substrate can be formed by stacking layers having different resistivity and conductivity type, and various layer structures can be formed on the substrate surface layer.

In such an epitaxial substrate for an image sensor, it is very important to reduce the level of heavy metal impurities in the substrate. This is because it is generally considered that a metal impurity present in a silicon single crystal substrate forms a deep level and becomes a recombination center. In particular, the presence of metal impurities in the vicinity of the substrate surface is thought to affect device characteristics.
For example, when a metal impurity is present in the device active layer, a charge is generated from the generation center, and as a result, a dark current is generated. If this dark current level is deteriorated, a device characteristic defect unique to the imaging element called white scratch occurs.

  In general, in order to manufacture an epitaxial substrate, a single crystal thin film is vapor-phase grown at a high temperature. Therefore, when a single crystal thin film is deposited, if a metal impurity is present in the vapor phase growth furnace, the single crystal thin film is contaminated by the metal impurity. Sources of contamination of these metals include, for example, silicon crystals and silicon-containing compounds used as raw materials, metal impurities deposited during cleaning or drying of reaction furnaces such as quartz bell jars and quartz cylinders, and materials constituting the reaction furnace. Metal impurities, stainless steel components commonly used in equipment piping systems, and the like.

Among Mo, Fe, Ni, and Cr contained in the stainless steel member among the metal impurities that are taken into the silicon single crystal substrate or the epitaxial substrate, it is Fe and Mo that require special attention.
Since Fe becomes a strong recombination center, it becomes a production center and tends to deteriorate the dark current level. Further, Mo is less likely to become a chloride and is likely to remain in the reaction furnace as compared with other impurities. Therefore, it is difficult to clean by so-called baking in a reactor or vapor etching, and as a result, it is taken into a silicon single crystal substrate or an epitaxial substrate.

  Examples of such metal impurity element evaluation methods include a wafer lifetime measurement method (WLT method), a surface photovoltaic method (SPV method), a deep level transient spectroscopy method (DLTS method), and the like (for example, see Non-Patent Document 1). ).

  Of these, the SPV method requires less time for evaluation than the WLT method, DLTS method, etc., and the preparation is simple. Therefore, contamination control of the heat treatment furnace at the manufacturing site and evaluation of the silicon single crystal substrate after heat treatment are performed. It is used for.

“Semiconductor Encyclopedia” (Industry Research Committee, published on November 22, 1999) pages 146-147, pages 1065-1066

  However, for epitaxial wafers with a high degree of cleanliness, there is a case where a difference in quality is observed when a device is manufactured, although a difference cannot be seen by the diffusion length measurement by the conventional SPV method.

This is because in the conventional diffusion length measurement by the SPV method, an estimated value is used for the recombination velocity of the back surface, which is one of the parameters necessary for calculating the diffusion length.
In addition, the value of the diffusion length changes depending on the frequency of incident light incident upon measurement, and the change in the diffusion length is larger as the wavelength of the incident light is longer.
Furthermore, since the thickness of the epitaxial wafer which is the measurement target is not taken into consideration, the diffusion length is saturated depending on the wafer thickness.

  For this reason, the SPV method, which is a simpler contamination monitoring method than the WLT method, has a problem that the difference in diffusion length cannot be directly evaluated as a contamination level difference in a wafer with high cleanliness as in recent years.

  The present invention has been made in view of the above problems, and even if a semiconductor substrate has a high degree of cleanliness in recent years, a semiconductor substrate optimum for an advanced device can be obtained by performing the cleanliness evaluation by the SPV method in the manufacturing process. It is an object of the present invention to provide a method of manufacturing a semiconductor substrate made of a silicon single crystal in which a wafer selection process that can be supplied is incorporated.

In order to solve the above problems, in the present invention, a method of manufacturing a semiconductor substrate made of a silicon single crystal, at least,
Preparing the semiconductor substrate;
For the semiconductor substrate,
(1) The back surface recombination speed of the semiconductor substrate is measured.
(2) When calculating the diffusion length of minority carriers generated by irradiating light to the semiconductor substrate by the SPV method, the backside recombination velocity measured in the step (1) and the thickness of the semiconductor substrate are incorporated. Calculate with
(3) The step (2) is performed a predetermined number of times while changing the wavelength of the irradiated light.
(4) The relationship between the diffusion length calculated in the step (2) and the frequency of the irradiated light is plotted for the number of times performed in the step (3), an approximate line is derived from the plot, and the approximate line is the frequency. Extrapolate to ₀ and calculate the diffusion length L ₀ when the frequency is 0.
An evaluation step for obtaining the diffusion length L ₀ by performing the steps of
Diffusion length L ₀ as determined in the evaluation step, a step of selecting a good or bad of the silicon substrate,
Provided is a method of manufacturing a semiconductor substrate, wherein a semiconductor substrate that has become non-defective in the sorting step is sent to the next step.

As described above, when the cleanliness is evaluated by the SPV method in the manufacturing process of the semiconductor substrate, the calculation accuracy is improved by the above steps (1) and (2) as compared with the calculation using the estimated value as in the past. be able to. Further, the influence of the fluctuation of the diffusion length value depending on the frequency can be reduced by the step (3). Then, the step (4) makes it possible to calculate the diffusion length with a small fluctuation of the measurement value depending on the incident light. This makes it possible to evaluate the difference in cleanliness level between semiconductor substrates having high cleanliness in recent years, whose diffusion length is longer than the thickness of the substrate.
And, by such a more accurate evaluation of heavy metal concentration in the evaluation process than before, it is possible to select non-defective / defective products (non-defective products are substrates whose heavy metal concentration is below a desired value). Can be manufactured more efficiently than before.

Here, the resistivity of the semiconductor substrate is the same as a silicon single crystal wafer having a resistivity of 1 Ω · cm or more and a conductivity type of P type, or a silicon single crystal wafer having a resistivity of 1 Ω · cm or more and a conductivity type of P type. Is a P / P epitaxial wafer in which a silicon epitaxial layer with a conductivity type of P type is formed and a diffusion length L ₀ is 1500 μm or more and 2300 μm or less in the sorting step. Can be sorted as
Thus, when the semiconductor substrate to be manufactured is a P-type silicon single crystal wafer or a P / P epitaxial wafer, the heavy metal concentration is low when the diffusion length L ₀ determined in the evaluation process of the present invention is 1500 μm or more and 2300 μm or less. The present inventors have clarified that the semiconductor substrate sufficiently satisfies recent requirements for cleanliness.
Accordingly, a semiconductor substrate having a diffusion length L ₀ of 1500 μm or more and 2300 μm or less is judged as a non-defective product in the sorting step, and a high-quality semiconductor substrate with sufficiently high cleanliness can be manufactured more efficiently by sending it to the next step. .
If the resistivity is less than 1 Ω · cm, the diffusion length cannot be effectively measured by the SPV method.

Further, the resistivity of the semiconductor substrate is the same as that of a silicon single crystal wafer having a resistivity of 1 Ω · cm or more and an N conductivity type, or a silicon single crystal wafer having a resistivity of 1 Ω · cm or more and an N conductivity type. In the case of an N / N epitaxial wafer having a silicon epitaxial layer of 1 Ω · cm or more and N-type conductivity, a product having a diffusion length L ₀ of 1200 μm to 2300 μm as a non-defective product in the sorting step Can be sorted.
When the semiconductor substrate to be manufactured is an N-type silicon single crystal wafer or an N / N epitaxial wafer, if the diffusion length L ₀ determined in the evaluation process of the present invention is 1200 μm or more and 2300 μm or less, the heavy metal concentration is low, The semiconductor substrate sufficiently satisfies the requirement for cleanliness.
Therefore, by making the diffusion length L ₀ from 1200 μm to 2300 μm as a non-defective product, a high-quality N-type silicon single crystal wafer or N / N epitaxial wafer having a low heavy metal impurity concentration can be manufactured at a high yield. become able to.
If the resistivity is less than 1 Ω · cm, the diffusion length cannot be effectively measured by the SPV method.

  As described above, according to the present invention, even a semiconductor substrate having a high cleanliness in recent years can be easily evaluated in a short time by performing the cleanliness evaluation by the SPV method in the manufacturing process. Provided is a method for manufacturing a semiconductor substrate made of a silicon single crystal, which incorporates a wafer selection process capable of supplying an optimal semiconductor substrate.

It is the figure which showed the outline of an example of the measuring method of the back surface recombination velocity of a semiconductor substrate. It is the figure which showed the evaluation result of the diffusion length of the P / P epitaxial wafer from which the cleanliness in Example 1 and the comparative example 1 differ. It is the figure which showed the relationship between the diffusion length evaluated with the evaluation method of Example 1, and a characteristic defect. It is the figure which showed the evaluation result of the diffusion length of the N / N epitaxial wafer in Example 2 from which the cleanliness differs. It is the figure which showed the relationship between the diffusion length evaluated with the evaluation method of Example 2, and a characteristic defect.

Hereinafter, the present invention will be described more specifically.
First, an outline of the SPV method used for measuring the carrier diffusion length will be described.

First, minority carriers are induced by irradiating an epitaxial silicon wafer having a transparent electrode with light having different wavelengths. The minority carriers induced here are collected on the wafer surface and surface electromotive force is generated.
Next, the irradiation light intensity is changed so that the surface electromotive force at each wavelength is constant. Then, since the absorption coefficient changes when the wavelength of the irradiation light is different, the reciprocal of the absorption coefficient and the irradiation light intensity are plotted.
A linear relationship is obtained from both, and the diffusion length can be obtained from a value obtained by extrapolating the straight line and crossing the axis of the absorption coefficient.

Hereinafter, the present invention will be described in detail with reference to the drawings, but the present invention is not limited thereto.
First, a semiconductor substrate made of a silicon single crystal is prepared.
The semiconductor substrate to be prepared may be a generally used semiconductor substrate having a resistivity of 1 Ω · cm or more. For example, a semiconductor substrate sliced from a silicon single crystal rod grown by the CZ method may be used. Further, the electrical characteristics such as the conductivity type, the presence or absence of the epitaxial layer, the crystal orientation, the crystal diameter, and other conditions are not particularly limited.

Thereafter, an evaluation process is performed on the prepared semiconductor substrate.
In this evaluation step, first, as step (1), the back surface recombination rate of the semiconductor substrate is measured. Here, the back surface is a surface opposite to the surface on the side where the diffusion length is measured in the later step (2).
For example, as shown in FIG. 1, the back surface recombination speed is measured by preparing a semiconductor substrate 13 having a transparent electrode 11 on the substrate back surface 13 b side and a surface electrode 12 on the substrate surface 13 a side. Irradiation with light having different wavelengths induces minority carriers, and the generated surface electromotive force is measured. Next, the intensity of irradiation light is changed so that the surface electromotive force at each wavelength is constant, and the changed absorption coefficient is measured. Then plot the reciprocal of the measured absorption coefficient and the irradiation light intensity, extrapolate the obtained linear relationship, obtain the diffusion length from the value crossing the axis of the absorption coefficient, and reconstruct the backside surface from this diffusion length and the diffusion coefficient of the minority carrier. The binding speed can be obtained.

  Then, as the step (2), when calculating the diffusion length of minority carriers generated by irradiating the semiconductor substrate with light by the SPV method, the back surface recombination velocity measured in step (1) and the semiconductor substrate to be measured Including the thickness of the calculation.

The following formula (1) can be used as a calculation method incorporating the backside recombination velocity and the thickness of the semiconductor substrate.
Formula (1)
ΔV = φ _eff × (C ₀ / C ₁ ) × (α ² L ² / (α ² L ² −1)) × (1-S _b / αD) × [(1 / αL) sinh (T / L) −cosh (T / L) + exp (−αT)]
Here, in the equation (1), ΔV: electromotive force generated on the surface by irradiation of measurement incident light = SPV (Surface Photo Voltage),
φ _eff : Effective incident light flux,
C ₀ = − (δQsc / δn + δQs / δn) / (δQsc / δVs + δQs / δVs) (where δQs / δn and δQs / δVs are substantially 0),
C ₁ = (S _f × S _b × L / D + D / L) sinh (T / L) + (S _f + S _b ) cosh (T / L),
L _i ⁻² = L ₀ ⁻² + Aω,
Qsc: space charge density,
Qs: surface state charge density,
n: excess minority carrier density,
Vs: barrier height,
α: Absorption coefficient of incident light,
L: diffusion length,
A: constant,
ω: frequency of incident light,
L ₀ : diffusion length at ω = 0,
S _b : back surface recombination speed,
S _f : surface recombination velocity,
D: minority carrier diffusion coefficient,
T: substrate thickness,
It is.

  Thereafter, as the step (3), the previous step (2) is performed a predetermined number of times while changing the wavelength of the irradiated light.

Further, as the step (4), the relationship between the diffusion length calculated in the previous step (2) and the frequency of the irradiated light is plotted for the number of times performed in the step (3). Then, an approximate line is derived from the plot, the approximate line is extrapolated to frequency 0, and the diffusion length at frequency ₀ is set to L ₀ to obtain the diffusion length L ₀ .
The plot at this time preferably takes the square of the inverse of the diffusion length with respect to the frequency of light.

In such an evaluation process, the back surface recombination velocity is actually measured by the steps (1) and (2), and the diffusion length is calculated from the evaluation result of the SPV method in consideration of the actual measurement value and the thickness of the semiconductor substrate to be measured. Therefore, the calculation accuracy can be improved as compared with the conventional calculation of the diffusion length based on the estimated value and the calculation without incorporating the thickness.
And since the diffusion length is calculated multiple times by changing the wavelength of the irradiated light in the step (3), the influence of the fluctuation of the diffusion length value depending on the frequency can be reduced, and the calculation accuracy is further improved. Will also contribute.
Further, in step (4), the diffusion length L ₀ is calculated from the relationship between the diffusion length value calculated over a predetermined number of times and the frequency of the incident light. Thus, the diffusion length of a semiconductor substrate having a high cleanliness can be calculated with high accuracy. Then the L ₀ that this calculation, by using as an indicator in the assessment process described later, it becomes possible to produce a small semiconductor substrate of heavy metal contamination in the above conventional accuracy.

And the diffusion length L ₀ as determined in the evaluation step, a step of selecting a good or bad of the silicon substrate.

Here, when the previously prepared semiconductor substrate is a P-type silicon single crystal wafer having a resistivity of 1 Ω · cm or more or a P / P epitaxial wafer having a resistivity of 1 Ω · cm or more, the diffusion length is determined in this selection step. Those having a value of L ₀ of 1500 μm or more and 2300 μm or less can be selected as non-defective products.

When the semiconductor substrate to be manufactured is a P-type silicon single crystal wafer having a resistivity of 1 Ω · cm or more or a P / P epitaxial wafer having a resistivity of 1 Ω · cm or more, the diffusion length L ₀ is 1500 μm or more and 2300 μm or less. It is a semiconductor substrate that is low and sufficiently satisfies the recent requirements for cleanliness.
Therefore, in the sorting process, a P-type silicon single crystal wafer or P / P epitaxial wafer having a diffusion length L ₀ of 1500 μm or more and 2300 μm or less is judged as a non-defective product, and sent to the next process, so that high-quality P with sufficiently high cleanliness is obtained. Type silicon single crystal wafers and P / P epitaxial wafers can be manufactured more efficiently than in the prior art.

Note that the limit to which the above-described calculation formula (1) used for evaluating the diffusion length can be applied is 2.5 to 3 times the semiconductor substrate thickness.
For example, in the case of a 300 mm diameter wafer, the substrate thickness is generally 775 μm and 775 × 3 = 2325 μm. Therefore, if the diffusion length is larger than 2300 μm, there is a possibility that the evaluation accuracy is not sufficiently ensured. Therefore, the upper limit of the diffusion length L ₀ is desirably 2300 μm.

Further, when the previously prepared semiconductor substrate is an N-type silicon single crystal wafer having a resistivity of 1 Ω · cm or more or an N / N epitaxial wafer having a resistivity of 1 Ω · cm or more, in this sorting step, the diffusion length L Those having a value of ₀ of 1200 μm or more and 2300 μm or less can be selected as non-defective products.

When the semiconductor substrate to be manufactured is an N-type silicon single crystal wafer having a resistivity of 1 Ω · cm or more or an N / N epitaxial wafer having a resistivity of 1 Ω · cm or more, the diffusion length L ₀ is 1200 μm or more and 2300 μm or less. It is a semiconductor substrate that is low and sufficiently satisfies the recent requirements for cleanliness.
Therefore, an N-type silicon single crystal wafer or N / N epitaxial wafer having a diffusion length L ₀ of 1200 μm or more and 2300 μm or less is judged as a non-defective product and is sent to the next process, so that a high-quality N-type silicon single crystal with sufficiently high cleanliness is obtained. Crystal wafers and N / N epitaxial wafers can be manufactured more efficiently than in the past.

  Then, the semiconductor substrate that has become non-defective in the sorting process is sent to the next process, and the semiconductor substrate is completed. Examples of the next process include cleaning, packing, and shipping process.

By such a method of manufacturing a semiconductor substrate according to the present invention, a semiconductor substrate that is considered defective with a high heavy metal concentration can be removed at the inspection stage.
Since only non-defective products can be sent to the next process, waste in the next process can be eliminated, and the manufacturing cost can be further reduced.
In addition, when processing into a semiconductor device, it is possible to greatly reduce the possibility of occurrence of defects due to a high heavy metal concentration, and thus it is possible to improve the yield in manufacturing semiconductor devices.

As described above, according to the present invention, it is possible to accurately evaluate the heavy metal concentration and to select the non-defective product / defective product during the manufacturing process of the semiconductor substrate without deteriorating the manufacturing yield. Thus, a high-quality semiconductor substrate can be manufactured more efficiently than before.
In particular, if the diffusion length L ₀ is 1500 μm or more and 2300 μm or less for a P-type silicon single crystal wafer or a P / P epitaxial wafer, and the N-type silicon single crystal wafer or N / N epitaxial wafer is 1200 μm or more and 2300 μm or less, the heavy metal concentration is low. This is a semiconductor substrate that sufficiently satisfies recent requirements for cleanliness, and can be selected as a high-quality semiconductor substrate.

EXAMPLES Hereinafter, although an Example and a comparative example are shown and this invention is demonstrated more concretely, this invention is not limited to these.
(Example 1, Comparative Example 1)
As a sample, an epitaxial layer in which an epitaxial layer of conductivity type P type and resistivity 10 Ω · cm is formed on a silicon single crystal wafer of conductivity type P type, diameter 200 mm, crystal orientation <100>, resistivity 8-12 Ω · cm A total of 24 wafers with different levels of cleanliness were prepared in 6 levels (4 per level).

  With respect to such a six-level epitaxial wafer, the evaluation steps (Example 1) as described above (Example 1) and the conventional wafer thickness are not incorporated, and the backside recombination speed Was used as an estimated value to calculate the diffusion length (Comparative Example 1) to obtain the diffusion length. The result is shown in FIG.

As shown in FIG. 2, in the evaluation method of Comparative Example 1, it was found that there was almost no difference between the wafers, and it was virtually impossible to determine whether the product was non-defective or defective.
On the other hand, in the evaluation method of Example 1, the difference in diffusion length could be evaluated for each level. In addition, there was a difference among the levels, and it was found that the diffusion length of each wafer could be evaluated with high accuracy.

Then, in order to evaluate the diffusion length and the occurrence rate of device characteristic defects, the occurrence rate of device characteristic defects when using the wafers of the same six batches and the same batch of wafers prepared previously was followed up. The result is shown in FIG.
As shown in FIG. 3, when using a wafer with a diffusion length of 1500 μm or more and the same batch of wafers, the occurrence rate of characteristic defects is extremely low, and the yield is lower than when using a wafer of less than 1500 μm and the same batch of wafers. Was found to be good.

(Example 2)
As a sample, an epitaxial layer in which an epitaxial layer having an N conductivity type and a resistivity of 10 Ω · cm is formed on a silicon single crystal wafer having an N conductivity type, a diameter of 200 mm, a crystal orientation <100>, and a resistivity of 8-12 Ω · cm. A total of 15 wafers having different levels of cleanliness, 5 levels (3 per level), were prepared.

  With respect to such five-level epitaxial wafers, the above-described evaluation steps (1) to (4) (Example 1) were performed, and the diffusion lengths were obtained. The result is shown in FIG.

  As shown in FIG. 4, similarly to Example 1 in which the P / P epitaxial wafer was evaluated, even in the case of the N / N epitaxial wafer, the difference in diffusion length could be evaluated for each level. Moreover, as in Example 1, differences were observed among the levels, and it was found that the diffusion length of each wafer can be evaluated with high accuracy.

Thereafter, in order to evaluate the diffusion length and the occurrence rate of device defects, the occurrence rate of device characteristic failures when using the wafers in the same batch as the previously prepared five-level wafers was followed up. The result is shown in FIG.
As shown in FIG. 5, when using a wafer with the diffusion length of 1200 μm or more and the same batch of wafers, the occurrence rate of characteristic defects is extremely low, and the yield is lower than when using a wafer of less than 1200 μm and the same batch of wafers. Was found to be good.

  The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has any configuration that has substantially the same configuration as the technical idea described in the claims of the present invention and that exhibits the same effects. Are included in the technical scope.

11 ... Transparent electrode, 12 ... Surface electrode,
13 ... Semiconductor substrate, 13a ... Substrate surface, 13b ... Substrate back surface.

Claims (3)

A method for manufacturing a semiconductor substrate comprising a silicon single crystal, at least,
Preparing the semiconductor substrate;
An evaluation step for obtaining the diffusion length L ₀ by performing the following steps (1) to (4) on the semiconductor substrate:
Diffusion length L ₀ as determined in the evaluation step, a step of selecting a good or bad of the semiconductor substrate,
A method of manufacturing a semiconductor substrate, comprising: transferring a semiconductor substrate that has become non-defective in the sorting step to the next step.
(1) The back surface recombination speed of the semiconductor substrate is measured.
(2) When calculating the diffusion length of minority carriers generated by irradiating light to the semiconductor substrate by a surface photovoltage (SPV) method, the backside recombination velocity measured in the step (1) And calculating the thickness of the semiconductor substrate.
(3) The step (2) is performed a predetermined number of times while changing the wavelength of the irradiated light.
(4) The relationship between the diffusion length calculated in the step (2) and the frequency of the irradiated light is plotted for the number of times performed in the step (3), an approximate line is derived from the plot, and the approximate line is the frequency. Extrapolate to ₀ and calculate the diffusion length L ₀ when the frequency is 0. The semiconductor substrate is a silicon single crystal wafer having a resistivity of 1 Ω · cm or more and a conductivity type of P, or a silicon single crystal wafer having a resistivity of 1 Ω · cm or more and a conductivity type of P type. When it is a P / P epitaxial wafer in which a silicon epitaxial layer having a conductivity type of P type and a P type is formed,
2. The method of manufacturing a semiconductor substrate according to claim 1, wherein, in the selecting step, the diffusion length L _{0 having} a value of 1500 μm to 2300 μm is selected as a good product. The semiconductor substrate has a resistivity of 1 Ω · cm or more and a conductivity type of N single-type silicon single crystal wafer or a resistivity of 1 Ω · cm or more and conductivity type of N-type silicon single crystal wafer. When it is an N / N epitaxial wafer having a silicon epitaxial layer with a conductivity type of N type and N type,
2. The method of manufacturing a semiconductor substrate according to claim 1, wherein, in the selecting step, the diffusion length L _{0 having} a value of 1200 μm or more and 2300 μm or less is selected as a non-defective product.

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