JP6930427B2 - Semiconductor device - Google Patents

Description

The present technology relates to semiconductor devices. More specifically, the present invention relates to a semiconductor device provided with an electromagnetic shield.

Conventionally, in a semiconductor device, in order to reduce electromagnetic noise due to electrostatic induction or electromagnetic induction, a conductor or a magnetic material is often arranged as an electromagnetic shield around a circuit to be protected. For example, a semiconductor device has been proposed in which a linear conductor is wired around an inductor as an electromagnetic shield to reduce electromagnetic noise generated in the inductor (see, for example, Patent Document 1).

Japanese Unexamined Patent Publication No. 2009-188343

However, in the above-mentioned semiconductor device, when the circuits are distributed and arranged on a plurality of stacked semiconductor chips, the electromagnetic noise generated in the inductor may not be sufficiently reduced. This is because when the wiring is used as an electromagnetic shield, the electromagnetic noise due to the magnetic field from the direction parallel to the substrate can be reduced, but the electromagnetic noise due to the magnetic field from the direction perpendicular to the substrate cannot be reduced. be. On the other hand, when the upper surface and the lower surface of the inductor are covered with a plate-shaped electromagnetic shield, the magnetic field in the direction perpendicular to the substrate can be blocked to sufficiently reduce the electromagnetic noise, but the eddy current generated by the electromagnetic shield can be sufficiently reduced. The current may reduce the inductance of the inductor. This is because the eddy current generates a magnetic field in the direction opposite to the direction of the magnetic field generated by the inductor, and the magnetic field causes a counter electromotive force in the inductor. When the inductance is lowered, the Q value of the inductor is deteriorated, which causes the signal quality to be deteriorated. Further, for example, when an inductor is used in an LC resonance circuit, it causes a change in the oscillation frequency. Therefore, it is desirable that the amount of decrease in inductance is small. As described above, it is difficult to reduce electromagnetic noise while suppressing a decrease in inductance with the above-mentioned linear or plate-shaped electromagnetic shield.

This technology was created in view of such a situation, and aims to reduce electromagnetic noise while suppressing a decrease in inductance in a semiconductor device provided with an electromagnetic shield.

The present technology has been made to solve the above-mentioned problems, and the first side surface thereof is the substrate on which the inductor is arranged and the inductor in a predetermined direction perpendicular to the substrate plane of the substrate as an upward direction. It is a semiconductor device provided above the above-mentioned shield with an upper layer slit, which is an electromagnetic shield in which slits are formed along a direction parallel to the substrate plane. As a result, the shield with the upper slit has the effect of reducing electromagnetic noise.

Further, on the first side surface, a circuit arrangement board on which a circuit is arranged may be further provided, and the circuit arrangement board may be laminated on the substrate. This has the effect of reducing electromagnetic noise in the semiconductor device on which the circuit board is laminated.

Further, on the first side surface, the inductor is a first wiring wound clockwise from a predetermined start point to a predetermined connection point about a first central axis perpendicular to the substrate plane, and the substrate. It is provided with a second wiring wound counterclockwise from the predetermined connection point to the predetermined end point about a second central axis that is perpendicular to the plane and is different from the first central axis. May be good. This has the effect of generating a magnetic field in the opposite direction in each of the first and second wirings.

Further, on the first side surface, the slit may be formed along a direction parallel to a straight line connecting the first central axis and the second central axis. This has the effect of suppressing the generation of eddy currents in the insertion shield.

Further, in the first aspect, the inductor is wound along a spiral path that swirls a plurality of times from a predetermined start point to a predetermined connection point about a predetermined central axis perpendicular to the substrate plane. The first wiring is provided and the second wiring is wound along a spiral path that swirls a plurality of times from the predetermined connection point to the predetermined end point around the predetermined central axis. The first wiring has a smaller turning radius each time it turns from the predetermined start point to the predetermined connection point, and the second wiring is from the predetermined connection point to the predetermined end point. The turning radius may increase each time the vehicle is turned. This has the effect of reducing the electromagnetic noise generated in the inductor that outputs the differential signal.

Also, on this first aspect, the inductor may include wiring wound along a spiral path. This has the effect of reducing the electromagnetic noise generated in the spiral inductor.

Further, on the first side surface, an outer peripheral shield which is an electromagnetic shield surrounding the outer periphery of the inductor may be further provided. This has the effect of reducing electromagnetic noise due to the magnetic field generated in the circuit around the inductor.

Further, on the first side surface, a lower layer shield which is an electromagnetic shield arranged below the inductor may be further provided. This has the effect of reducing electromagnetic noise due to the magnetic field generated in the circuit below the inductor.

Further, on the first side surface, a shield with a lower layer slit, which is arranged below the inductor and has slits formed in a direction parallel to the substrate plane, may be further provided. This has the effect of reducing electromagnetic noise due to the magnetic field generated in the circuit below the inductor.

Further, on the first side surface, a fixed potential may be applied to the shield with the upper layer slit. This has the effect of reducing electromagnetic noise due to electrostatic induction.

Further, in the first aspect thereof, a capacitance connected to the inductor may be further provided, and the inductor and the capacitance may resonate. This has the effect of reducing electromagnetic noise in the resonant circuit.

Further, in the first aspect, a phase comparator that compares the phases of the input signal and the feedback signal and outputs a detection signal indicating the phase difference, and a voltage signal having a voltage corresponding to the phase difference indicated by the detection signal. A charge pump for generating the May be a variable capacitance whose capacitance value changes according to the voltage signal. This has the effect of multiplying the period of the input signal.

Further, in the first aspect, the input signal may be a clock signal. This has the effect of multiplying the clock signal.

According to the present technology, in a semiconductor device provided with an electromagnetic shield, it is possible to achieve an excellent effect that electromagnetic noise can be reduced while suppressing a decrease in inductance. The effects described here are not necessarily limited, and may be any of the effects described in the present disclosure.

It is a block diagram which shows one structural example of the semiconductor device in 1st Embodiment of this technique. It is a block diagram which shows one configuration example of the phase-locked loop in the 1st Embodiment of this technique. It is a circuit diagram which shows one configuration example of the voltage control oscillator and the electromagnetic shield in the 1st Embodiment of this technique. This is an example of a perspective view of a semiconductor device according to the first embodiment of the present technology. It is an example of the plan view of the inductor in the 1st Embodiment of this technique. This is an example of a plan view of the upper shield in the first embodiment of the present technology. It is a figure which shows an example of the direction of the current flowing through the inductor in the 1st Embodiment of this technique. It is a figure which shows an example of the direction of the induced current in the upper layer shield in 1st Embodiment of this technique. It is a figure for demonstrating the method of measuring the insulation level in 1st Embodiment of this technique. It is a graph which shows the insulation level for every frequency in 1st Embodiment of this technique. It is a graph which shows the inductance for every frequency in 1st Embodiment of this technique. It is a graph which shows the Q value for every frequency in the 1st Embodiment of this technique. It is an example of the plan view of the inductor in the 2nd Embodiment of this technique. It is an example of the plan view of the inductor in the 3rd Embodiment of this technique. It is a circuit diagram which shows one configuration example of the voltage control oscillator and the electromagnetic shield in 4th Embodiment of this technique. This is an example of a perspective view of an inductor and an electromagnetic shield according to a fourth embodiment of the present technology. This is an example of a cross-sectional view of an inductor and an electromagnetic shield according to a fourth embodiment of the present technology.

Hereinafter, embodiments for carrying out the present technology (hereinafter referred to as embodiments) will be described. The explanation will be given in the following order.
1. 1. First Embodiment (Example in which a shield with a slit is inserted between the inductor and the circuit)
2. Second embodiment (an example in which a shield with a slit is inserted between an inductor that generates a differential signal and a circuit)
3. 3. Third Embodiment (Example in which a shield with a slit is inserted between the spiral inductor and the circuit)
4. Fourth embodiment (an example in which a shield with a slit is inserted between the inductor and the circuit, and a lower layer shield and an outer peripheral shield are provided).

<1. First Embodiment>
[Semiconductor device configuration example]
FIG. 1 is a block diagram showing a configuration example of a semiconductor device 100 according to an embodiment of the present technology. As the semiconductor device 100, for example, a device equipped with an image pickup device, an LSI (Large Scale Integration), or the like is assumed. The semiconductor device 100 is provided with a plurality of stacked semiconductor chips such as an upper chip 110 and a lower chip 150. A logic circuit 111 is arranged on the upper chip 110. A logic circuit 151 and a phase-locked loop 200 are arranged on the lower chip 150.

Although two semiconductor chips are laminated, the number of semiconductor chips to be laminated is not limited to two, and may be three or more.

The logic circuit 111 executes a predetermined process. The logic circuit 111 transmits / receives data to / from the lower logic circuit 151 via the signal line 119. As the logic circuit 111, for example, a pixel circuit or a vertical drive circuit for driving the pixel circuit is assumed.

The logic circuit 151 executes a predetermined process in synchronization with _{the clock signal CLK out} from the phase-locked loop 200. As the logic circuit 151, for example, an AD (Analog to Digital) converter and a horizontal drive circuit for driving the AD converter are assumed.

_{A clock signal CLK in} having a predetermined period generated by an external crystal oscillator or the like is input to the phase-locked loop 200. The phase-locked loop 200 _{multiplies the clock signal CLK in} by a predetermined multiplication ratio and outputs the clock signal CLK _out to the logic circuit 151 via the signal line 209.

[Phase-locked loop configuration example]
FIG. 2 is a block diagram showing a configuration example of the phase-locked loop 200 according to the first embodiment. The phase-locked loop 200 includes a phase comparator 210, a charge pump 220, a frequency divider 230, and a voltage controlled oscillator 240.

The phase comparator 210 compares the phases of the clock signal CLK _in from the crystal oscillator 152 and the clock signal CLK _fb from the frequency divider 230. Based on the comparison result, the phase comparator 210 generates detection signals UP and DN indicating the phase difference between the signals and supplies them to the charge pump 220. For example, the difference in pulse width between the detection signals UP and DN indicates the phase difference _{between the clock signal CLK in} and the clock signal CLK _fb.

The charge pump 220 generates a control signal Vc of a voltage corresponding to the phase difference indicated by the detection signal UP and DN. The charge pump 220 supplies the control signal Vc to the voltage controlled oscillator 240.

_{The voltage controlled oscillator 240 generates a clock signal CLK out} having a frequency corresponding to the voltage of the control signal Vc, and supplies the clock signal CLK out to the frequency divider 230 and the logic circuit 151. This clock signal CLK _out is, for example, a single-ended signal.

The frequency divider 230 divides the clock signal CLK _out from the voltage controlled oscillator 240 by a predetermined frequency division ratio. The frequency divider 230 _{feeds the divided} signal back to the phase comparator 210 as a clock signal CLK fb. _{By feeding back the signal obtained by dividing the clock signal CLK out} from the voltage controlled oscillator 240 in this way, the phase-locked loop 200 can generate a signal obtained by multiplying the _{clock signal CLK in.}

[Configuration example of voltage controlled oscillator]
FIG. 3 is a circuit diagram showing a configuration example of the voltage controlled oscillator 240 and the electromagnetic shield according to the first embodiment. The voltage controlled oscillator 240 includes an amplifier circuit 241, an inductor 250, and a variable capacitance 242. The variable capacitance 242 and the inductor 250 are connected in parallel to the amplifier circuit 241. Further, the upper layer shield 260 is laminated above the inductor 250 with the direction from the lower chip 150 toward the upper chip 110 as the upward direction.

The variable capacitance 242 is a capacitor whose electric capacitance changes according to the voltage of the control signal Vc from the charge pump 220. For example, a varicap diode is used as the variable capacitance 242. The variable capacity 242 is an example of the capacity described in the claims.

The inductor 250 resonates with the variable capacitance 242 to generate a clock signal. The inductor 250 also generates an upward or downward magnetic field.

The amplifier circuit 241 amplifies the signal generated by the LC resonance circuit including the variable capacitance 242 and the inductor 250, _{and supplies the clock signal CLK out} to the frequency divider 230 and the logic circuit 151.

The upper layer shield 260 is an electromagnetic shield in which slits are formed along the directions parallel to the respective substrate planes of the upper chip 110 and the lower chip 150. Further, a predetermined fixed potential (for example, ground potential) is applied to the upper shield 260. The upper layer shield 260 shields electromagnetic noise due to the magnetic field generated in the upper logic circuit 111, and protects the lower inductor 250 from the electromagnetic noise.

Although the potential of the upper shield 260 is a fixed potential, it may be a floating potential. In this case, the upper layer shield 260 functions as a magnetic field shield that shields only electromagnetic noise due to electromagnetic induction. When it is necessary to shield electromagnetic noise due to electrostatic induction, a fixed potential is applied to the upper shield 260.

Further, although the upper layer shield 260 is arranged above the inductor 250 in the voltage controlled oscillator 240, it is arranged above the inductor provided in a circuit other than the voltage controlled oscillator 240 (buffer circuit, clock distribution circuit, etc.). May be good.

FIG. 4 is an example of a perspective view of the semiconductor device according to the first embodiment. In the figure, a is an example of a perspective view of the upper chip 110 and the lower chip 150. In the figure, b is an example of an enlarged perspective view of the upper shield 260, and c in the figure is an example of an enlarged perspective view of the inductor 250.

As illustrated in a in FIG. 4, an inductor 250 is arranged on the lower chip 150, and an upper layer shield 260 is laminated above the inductor 250. In other words, the upper shield 260 is inserted between the inductor 250 and the upper chip 110. Then, the logic circuit 111 is arranged on the upper chip 110 above the upper shield 260. In this logic circuit 111, it is assumed that an inductor having the same shape as the inductor 250 is not provided above the inductor 250.

The upper chip 110 is an example of the circuit arrangement board described in the claims, and the lower chip 150 is an example of the inductor arrangement board described in the claims. Further, the upper layer shield 260 is an example of a shield with an upper layer slit described in the claims.

Further, although the upper layer shield 260 is inserted between the inductor 250 and the upper chip 110, the present invention is not limited to this configuration as long as the upper layer shield 260 is arranged between the inductor 250 and other circuits. .. For example, the upper layer shield 260 may be provided on the upper chip 110, and the logic circuit 111 may be laminated above the upper chip 110.

Further, as illustrated in b in FIG. 4, a predetermined number of slits are formed in the upper shield 260 along a direction parallel to the substrate plane of the upper chip 110 and the lower chip 150.

Further, as illustrated in c in FIG. 4, the inductor 250 is composed of the connected wiring 251 and the wiring 252. These wirings 251 and 252 are wound in a circle about a central axis perpendicular to the substrate plane. Further, these wirings 251 and 252 are laminated in a plurality of layers. It should be noted that these wirings may be made into a single layer instead of having a plurality of layers.

The centers of the wiring 251 and the wiring 252 are not the same, and are arranged at a certain distance. The direction parallel to the straight line connecting these centers is hereinafter referred to as the X direction. Further, the direction parallel to the substrate plane and perpendicular to the X direction is hereinafter referred to as the Y direction. The direction perpendicular to the substrate plane is hereinafter referred to as the Z direction. The slit of the upper layer shield 260 described above is formed along the X direction.

[Inductor configuration example]
FIG. 5 is an example of a plan view of the inductor 250 according to the first embodiment. The inductor 250 is composed of the connected wiring 251 and the wiring 252. Here, one end of both ends of the wiring 251 that is not connected to the wiring 252 is set as a start point 501, and the other end is set as a connection point 502. Further, one end of both ends of the wiring 252 that is not connected to the wiring 251 is set as the end point 503.

The wiring 251 is wound clockwise from the start point 501 to the connection point 502 about a central axis parallel to the Z direction. On the other hand, the wiring 252 is wound counterclockwise from the connection point 502 to the end point 503 about the central axis parallel to the Z direction. The number of turns of each of the wirings 251 and 252 is, for example, two. The number of turns is not limited to two.

The centers of the wiring 251 and the wiring 252 are not the same, and these centers are arranged on a straight line parallel to the X direction. In such a figure-eight inductor 250, when a current is passed from one of the start point 501 and the end point 503 to the other, a magnetic field in opposite directions is generated in the wiring 251 and the wiring 252. For example, when the wiring 251 generates an upward magnetic field, the wiring 252 generates a downward magnetic field.

[Configuration example of upper shield]
FIG. 6 is an example of a plan view of the upper shield 260 according to the first embodiment. A predetermined number of slits are formed in the upper shield 260 along the X direction. Further, a predetermined fixed potential (ground potential or the like) is applied to the upper shield 260.

FIG. 7 is a diagram showing an example of the direction of the current flowing through the inductor 250 according to the first embodiment. When a current flows from the start point 501 to the end point 503, the current flows clockwise in the wiring 251 and counterclockwise in the wiring 252.

FIG. 8 is a diagram showing an example of the direction of the induced current in the upper layer shield 260 according to the first embodiment. In the figure, the thick dotted line indicates the current flowing through the wiring 251 and the thin dotted line indicates the eddy current induced in the upper shield 260 by the magnetic field generated in the wiring 251. The thick solid line indicates the path of the current flowing through the wiring 252, and the thin solid line indicates the eddy current induced in the upper shield 260 by the magnetic field generated in the wiring 252.

A current flows clockwise in the wiring 251 and a downward magnetic field is generated by the current. Due to this magnetic field, a counterclockwise eddy current (dotted line) flows through the upper shield 260 according to the law of electromagnetic induction. On the other hand, in the wiring 252, a current flows counterclockwise, and the current causes an upward magnetic field. Due to this magnetic field, a clockwise eddy current (solid line) flows through the upper shield 260 according to the law of electromagnetic induction.

As described above, in the upper shield 260, the slits are formed along the X direction. Further, in the inductor 250, the wirings 251 and 252 are arranged along the X direction. Therefore, with the wiring 251 side on the left side and the wiring 252 side on the right side, the eddy current induced on the right side of the upper shield 260 flows to the left side along the slit, and the eddy current induced on the left side flows to the right side along the slit. Slit. These eddy currents cancel each other out because they are opposite to each other. Therefore, almost no eddy current is generated in the entire upper shield 260, and there is no possibility that a back electromotive force is generated in the inductor 250 due to the magnetic field generated by the eddy current. Therefore, it is possible to suppress a decrease in the inductance of the inductor 250 due to the counter electromotive force. Further, by suppressing the decrease in inductance, it is possible to suppress the decrease in the Q value of the inductor 250. Here, the Q value is expressed by, for example, the following equation.
Q = 2πfL / R
In the above equation, L represents the inductance of the inductor 250, and the unit is, for example, Henry (H). “F” indicates an oscillation frequency when the inductor 250 resonates with a variable capacitance 242 or the like, and the unit is, for example, Hertz (Hz). R indicates the internal resistance of the inductance 250, and the unit is, for example, ohm (Ω).

Further, an eddy current is also generated in the upper shield 260 by the magnetic field generated in the logic circuit 111 above the inductor 250, but as described above, an element having the same shape as the inductor 250 is not provided above the inductor 250. .. Therefore, the eddy current generated by the magnetic field from the logic circuit 111 is not canceled, and the magnetic field from the logic circuit 111 is canceled by the magnetic field in the opposite direction generated by the eddy current. As a result, electromagnetic noise from above is shielded. Therefore, it is possible to protect the inductor 250 from the electromagnetic noise by reducing the electromagnetic noise caused by the magnetic field generated in the circuit other than the inductor 250 while suppressing the decrease in the inductance of the inductor 250.

Here, it is assumed that the upper shield 260 of the comparative example has slits formed along the Y direction instead of the X direction. In this comparative example, an eddy current flows in the Y direction along the slit. However, since the wirings 251 and 252 are arranged in the X direction, the eddy current induced on the right side of the upper shield 260 does not flow to the left side, and the eddy current induced on the left side does not flow to the right side. Therefore, the eddy current is not canceled except in the vicinity of the center, and the magnetic field generated by the eddy current may reduce the inductance of the inductor 250.

Further, regardless of the direction, when the slit itself is not provided on the upper shield 260, the direction of the eddy current is not limited by the slit, so that the total current value of the eddy current is larger than that when the slit is provided. Will also grow. Therefore, the amount of decrease in inductance becomes large as compared with the case where the slit is provided.

FIG. 9 is a diagram for explaining a method of measuring the insulation level in the first embodiment. An inductor 302 having a shape different from that of the inductor 250 (such as a spiral shape) is arranged above the upper shield 260, and the AC power supply 301 is connected to the inductor 302. The supply current of the AC power supply 301 when the frequency of the AC signal from the AC power supply 301 is f is _{measured as i in} (f). The unit of frequency f is, for example, hertz (Hz). Further, both ends of the inductance 250 are grounded. By a magnetic field inductor 302 is generated, the current of the positive-phase signal induced in the inductor 250 is determined as i p _(f), the current of the reverse-phase signal, is measured as i n _(f). The unit of these currents is, for example, amperes (A). _{Then, the insulation level LV ISO} is calculated by the following formula based on these measured values.

This insulation level LV _ISO shows a high effect of shielding electromagnetic noise generated in a circuit (inductor 302 or the like) above the inductor 250. The smaller the insulation level LV _ISO value, the higher the shielding effect of electromagnetic noise. The unit of insulation level LV _ISO is decibel (dB).

FIG. 10 is a graph showing the insulation level for each frequency in the first embodiment. In the figure, the vertical axis represents the insulation level LV _ISO (dB), and the horizontal axis represents the frequency f (Hz) of the AC signal. Further, in the figure, the dotted line curve _{shows the characteristics of the insulation level LV ISO} when the upper layer shield 260 is not provided, and the solid line curve shows the characteristics of the insulation level LV _ISO when the upper layer shield 260 is provided.

As illustrated in FIG. 10, by providing the upper layer shield 260, the insulation level LV _ISO can be made smaller than that in the case where the upper layer shield 260 is not provided. That is, it is possible to improve the shielding effect of electromagnetic noise from circuits other than the inductor 250.

FIG. 11 is a graph showing the inductance for each frequency in the first embodiment. In the figure, the vertical axis represents the inductance L (H) of the inductor 250, and the horizontal axis represents the frequency f (Hz) of the AC signal. Further, in the figure, the dotted line curve shows the characteristic of the inductance L when the upper layer shield 260 is not provided, and the solid line curve shows the characteristic of the inductance L when the upper layer shield 260 is provided.

As illustrated in FIG. 11, even if the upper layer shield 260 is provided, the value of the inductance L hardly decreases (deteriorates) as compared with the case where the upper layer shield 260 is not provided.

FIG. 12 is a graph showing the Q value for each frequency in the first embodiment. In the figure, the vertical axis represents the Q value of the inductor 250, and the horizontal axis represents the frequency f (Hz) of the AC signal. Further, in the figure, the dotted line curve shows the characteristic of the Q value when the upper layer shield 260 is not provided, and the solid line curve shows the characteristic of the Q value when the upper layer shield 260 is provided.

As illustrated in FIG. 12, even if the upper layer shield 260 is provided, the Q value hardly decreases (deteriorates) as compared with the case where the upper layer shield 260 is not provided.

As illustrated in FIGS. 10 to 12, by providing the upper layer shield 260, it is possible to reduce electromagnetic noise while suppressing deterioration of the inductance L and Q values.

As described above, according to the first embodiment of the present technology, since the upper layer shield 260 having the slit formed is inserted between the inductor 250 and the logic circuit 111, electromagnetic noise due to the magnetic field generated in the logic circuit 111 is reduced. can do. Further, since the eddy current is reduced by the slit of the upper shield 260, it is possible to suppress the decrease in the inductance of the inductor 250.

<2. Second Embodiment>
In the first embodiment described above, the upper layer shield 260 is arranged above the figure eight inductor 250 to protect the inductor 250 from electromagnetic noise, but an inductor having a shape other than the figure eight is used. It can also be protected. For example, when a clock signal is used as a differential signal, an inductor having a special shape in which two spiral wires having the same center are connected is used. The semiconductor device 100 of the second embodiment is different from the first embodiment in that the inductor 265 composed of two spiral wirings having the same center is protected.

FIG. 13 is an example of a plan view of the inductor 265 in the second embodiment. The upper shield 260 is arranged above the inductor 265. In the second embodiment, the slit direction of the upper shield 260 may be a direction parallel to the substrate plane, and is not limited to the X direction.

The inductor 265 is composed of the connected wiring 266 and the wiring 267. Here, one end of both ends of the wiring 266 that is not connected to the wiring 267 is set as a start point 511, and the other end is set as a connection point 512. Further, one end of both ends of the wiring 267 that is not connected to the wiring 266 is set as the end point 513.

The wiring 266 is wound around a central axis parallel to the Z-axis direction along a spiral path that swirls clockwise a plurality of times from a start point 511 to a connection point 512. On the other hand, the wiring 267 is wound around the same central axis as the wiring 266 along a spiral path that swirls clockwise a plurality of times from the connection point 512 to the end point 513. Further, the turning radius of the wiring 266 decreases each time it turns from the start point 511 to the connection point 512, and the turning radius of the wiring 267 increases each time it turns from the connection point 512 to the end point 513. A positive phase signal is input / output to the start point 511, and a negative phase signal is input / output to the end point 513. As described above, since the wiring 266 and the wiring 267 have a contrasting shape, the duty ratios of the positive phase signal and the negative phase signal can be made about the same.

When the inductor 265 having the above shape is protected by the upper layer shield 260, unlike the figure eight inductor 250 of the first embodiment, the directions of the currents flowing through the wiring 266 and the wiring 267 are the same, so that the upper layer shield The eddy current generated at 260 is not canceled. Therefore, although the effect of suppressing the decrease in inductance is higher than that of the plate-shaped electromagnetic shield having no slit, it is lower than that of the first embodiment. However, instead, the magnetic field generated in the inductor 265 can be canceled by the eddy current, so that the electromagnetic noise generated in the upper logic circuit 111 can be reduced. That is, the upper layer shield 260 can protect the logic circuit 111 from electromagnetic noise in addition to the inductor 265.

As described above, according to the second embodiment of the present technology, since the upper layer shield 260 is inserted between the inductor 265 composed of two spiral wirings having the same center and the logic circuit 111, in addition to the inductor 265. The logic circuit 111 can also be protected from electromagnetic noise. Further, by using the inductor 265 composed of two spiral wires, when the differential signal is output, the duty ratios of the positive phase signal and the negative phase signal in the differential signal are made uniform to the same extent. Can be done.

<3. Third Embodiment>
In the first embodiment described above, the upper shield 260 is arranged above the figure-eight inductor 250 to protect the inductor 250 from electromagnetic noise, but an inductor having a shape other than the figure-eight shape is used. It can also be protected. For example, when the clock signal is a single-ended signal, a spiral inductor may be used instead of the figure eight shape. The semiconductor device 100 of the third embodiment is different from the first embodiment in that the spiral inductor 270 is protected.

FIG. 14 is an example of a plan view of the inductor 270 according to the third embodiment. The upper shield 260 is arranged above the inductor 270. In the third embodiment, the direction of the slit of the upper layer shield 260 may be a direction parallel to the substrate plane, and is not limited to the X direction.

The inductor 270 is composed of wiring wound spirally from a start point 521 to an end point 522 with a central axis parallel to the Z direction as a center.

When the inductor 270 having the above-mentioned shape is protected by the upper layer shield 260, the effect of suppressing the decrease in inductance is higher than that of the plate-shaped electromagnetic shield without slits, but it is lower than that of the first embodiment. However, instead, the upper layer shield 260 can shield the electromagnetic noise generated in the upper logic circuit 111.

As described above, according to the third embodiment of the present technology, since the upper layer shield 260 is inserted between the spiral inductor 270 and the logic circuit 111, the logic circuit 111 is protected from electromagnetic noise in addition to the inductor 270. can do. In addition, a single-ended signal can be output by the spiral inductor 270, which is simpler than the figure eight shape.

<4. Fourth Embodiment>
In the first embodiment described above, the electromagnetic shield (upper layer shield 260) is arranged only above the inductor 250, but the magnetic field generated below the inductor 250 or in the circuit on the same substrate (lower chip 150). May also generate electromagnetic noise. It is difficult to reduce such electromagnetic noise only with the upper shield 260. The semiconductor device 100 of the fourth embodiment is different from the first embodiment in that electromagnetic noise due to a circuit below the inductor 250 or on the same substrate is reduced.

FIG. 15 is a circuit diagram showing a configuration example of the voltage controlled oscillator 240 and the electromagnetic shield according to the fourth embodiment. In this fourth embodiment, as the electromagnetic shield, in addition to the upper layer shield 260, an outer peripheral shield 280 and a lower layer shield 290 are further provided.

The outer peripheral shield 280 is an electromagnetic shield that surrounds the outer circumference of the inductor 250 in the lower chip 150. For example, conductive wiring surrounding the inductor 250 is used as the outer shield 280. The potential of the outer peripheral shield 280 is, for example, a floating potential. The potential of the outer peripheral shield 280 may be a fixed potential.

The lower layer shield 290 is an electromagnetic shield arranged below the inductor 250. The lower shield 290 is inserted, for example, between the lower chip 150 and the inductor 250. Further, a fixed potential (ground potential or the like) is applied to the lower layer shield 290. The potential of the lower shield 290 may be a floating potential.

FIG. 16 is an example of a perspective view of the inductor 250 and the electromagnetic shield according to the fourth embodiment. In the figure, a is an example of a perspective view of the upper shield 260, and b in the figure is an example of a perspective view of the inductor 250. Further, c in the figure is an example of a perspective view of the outer peripheral shield 280. The outer peripheral shield 280 is laminated according to the height of the inductor 250. In the figure, d is an example of a perspective view of the lower shield 290. As the lower layer shield 290, for example, a PGS (patterned ground shield) having a certain pattern (a shape similar to X, etc.) is used. Instead of PGS, a shield having the same shape as the upper shield 260 may be arranged as the lower shield 290.

Although both the outer peripheral shield 280 and the lower layer shield 290 are arranged, only one of them may be arranged.

FIG. 17 is an example of a cross-sectional view of the inductor 250 and the electromagnetic shield according to the fourth embodiment. As illustrated in the figure, the side surface of the inductor 250 is covered with the outer peripheral shield 280, the upper surface is covered with the upper layer shield 260, and the lower surface is covered with the lower layer shield 290. Therefore, the inductor 250 can be protected from the electromagnetic noise caused by the magnetic field generated in the circuits on the upper, lower, and lower chips 150 of the inductor 250. Further, it is possible to protect the circuit below the inductor 250 and the circuit on the lower chip 150 from electromagnetic noise caused by the magnetic field generated in the inductor 250.

As described above, according to the fourth embodiment of the present technology, since the outer peripheral shield 280 and the lower layer shield 290 are further arranged on the outer periphery and the lower side of the inductor 250, the magnetic field from the circuit on and below the same substrate as the inductor 250 is used. Electromagnetic noise can be reduced.

It should be noted that the above-described embodiment shows an example for embodying the present technology, and the matters in the embodiment and the matters specifying the invention in the claims have a corresponding relationship with each other. Similarly, the matters specifying the invention within the scope of claims and the matters in the embodiment of the present technology having the same name have a corresponding relationship with each other. However, the present technology is not limited to the embodiment, and can be embodied by applying various modifications to the embodiment without departing from the gist thereof.

It should be noted that the effects described in the present specification are merely examples and are not limited, and other effects may be obtained.

The present technology can have the following configurations.
(1) The substrate on which the inductor is placed and
A shield with an upper layer slit, which is an electromagnetic shield arranged above the inductor in a predetermined direction perpendicular to the substrate plane of the substrate and having slits formed along a direction parallel to the substrate plane, is provided. Semiconductor device.
(2) Further provided with a circuit arrangement board on which circuits are arranged,
The semiconductor device according to (1) above, wherein the circuit arrangement board is laminated on the board.
(3) The inductor is
The first wiring wound clockwise from a predetermined start point to a predetermined connection point about the first central axis perpendicular to the substrate plane, and
A second wiring wound counterclockwise from the predetermined connection point to a predetermined end point about a second central axis that is perpendicular to the substrate plane and is different from the first central axis. The semiconductor device according to (1) above.
(4) The semiconductor device according to (3) above, wherein the slit is formed along a direction parallel to a straight line connecting the first central axis and the second central axis.
(5) The inductor is
A first wiring wound along a spiral path that swirls a plurality of times from a predetermined start point to a predetermined connection point about a predetermined central axis perpendicular to the substrate plane.
It is provided with a second wiring wound along a spiral path that swirls a plurality of times from the predetermined connection point to the predetermined end point about the predetermined central axis.
Each time the first wiring turns from the predetermined start point to the predetermined connection point, the turning radius becomes smaller.
The semiconductor device according to claim 1, wherein the second wiring has a turning radius that increases each time it turns from the predetermined connection point to the predetermined end point. The semiconductor device according to (1) above.
(6) The semiconductor device according to (1) above, wherein the inductor includes wiring wound along a spiral path.
(7) The semiconductor device according to any one of (1) to (6) above, further comprising an outer peripheral shield which is an electromagnetic shield surrounding the outer periphery of the inductor.
(8) The semiconductor device according to any one of (1) to (7) above, further comprising a lower layer shield which is an electromagnetic shield arranged below the inductor.
(9) The method according to any one of (1) to (8) above, further comprising a shield with a lower layer slit, which is arranged below the inductor and has slits formed along a direction parallel to the substrate plane. Semiconductor device.
(10) The semiconductor device according to any one of (1) to (9) above, wherein a fixed potential is applied to the shield with an upper layer slit.
(11) Further provided with a capacitance connected to the inductor,
The semiconductor device according to any one of (1) to (10), wherein the inductor and the capacitance resonate.
(12) A phase comparator that compares the phases of the input signal and the feedback signal and outputs a detection signal indicating a phase difference.
A charge pump that generates a voltage signal of a voltage corresponding to the phase difference indicated by the detection signal, and a charge pump.
A frequency divider that divides the oscillation signal generated by the inductor and the resonance circuit including the capacitance and feeds it back to the phase difference detector as the feedback signal is further provided.
The semiconductor device according to (11), wherein the capacitance is a variable capacitance whose capacitance value changes according to the voltage signal.
(13) The semiconductor device according to (12) above, wherein the input signal is a clock signal.

100 Semiconductor device 110 Upper chip 111, 151 Logic circuit 150 Lower chip 200 Phase-locked loop 210 Phase-locked loop 220 Charge pump 230 Divider 240 Voltage-controlled oscillator 241 Amplifier circuit 242 Variable capacity 250, 265, 270, 302 Inductor 260 Upper layer Shield 280 Outer shield 290 Lower shield 301 AC power supply

Claims (9)

The board on which the inductor is placed and
With an upper layer slit, which is an electromagnetic shield arranged above the inductor with a predetermined direction perpendicular to the substrate plane of the substrate as the upward direction, and having a plurality of slits formed along a specific direction parallel to the substrate plane. Equipped with a shield,
The length of each of the plurality of slits is shorter than the length of the shield with upper slits in the specific direction.
The inductor is
The first wiring wound clockwise from a predetermined start point to a predetermined connection point about the first central axis perpendicular to the substrate plane, and
A second wiring wound counterclockwise from the predetermined connection point to a predetermined end point about a second central axis that is perpendicular to the substrate plane and is different from the first central axis. Prepare,
The specific direction is a direction parallel to the line segment connecting the first central axis and the second central axis.
All of the plurality of slits are formed along the specific direction.
A semiconductor device in which the length of each of the plurality of slits is longer than the line segment. Further equipped with a circuit arrangement board on which circuits are arranged,
The semiconductor device according to claim 1, wherein the circuit board is laminated on the board. The semiconductor device according to claim 1, further comprising an outer peripheral shield which is an electromagnetic shield surrounding the outer periphery of the inductor. The semiconductor device according to claim 1, further comprising a lower layer shield which is an electromagnetic shield arranged below the inductor. The semiconductor device according to claim 1, further comprising a shield with a lower layer slit, which is arranged below the inductor and has slits formed along a direction parallel to the substrate plane. The semiconductor device according to claim 1, wherein a fixed potential is applied to the shield with an upper slit. Further comprising a capacitance connected to the inductor
The semiconductor device according to claim 1, wherein the inductor and the capacitance resonate. A phase comparator that compares the phases of the input signal and the feedback signal and outputs a detection signal that indicates the phase difference.
A charge pump that generates a voltage signal of a voltage corresponding to the phase difference indicated by the detection signal, and a charge pump.
A frequency divider that divides the oscillation signal generated by the inductor and the resonance circuit including the capacitance and feeds it back to the phase comparator as the feedback signal is further provided.
The semiconductor device according to claim 7, wherein the capacitance is a variable capacitance whose capacitance value changes according to the voltage signal. The semiconductor device according to claim 8, wherein the input signal is a clock signal.

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