JP2009135327A - Wiring arranging method, and wiring arranging program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide noise countermeasure techniques for an electronic device. <P>SOLUTION: A method of determining an arrangement of wiring of a wiring layer of a semiconductor device includes a first process of determining an arrangement of main power supply wiring in a predetermined region of the wiring layer; a second process of determining an arrangement of a spiral coil for a noise filter in the predetermined region according to the arrangement of the main power supply wiring, and a third process of determining an arrangement of a plurality of cells in a region other than the arrangement positions of the main power supply wiring and the spiral coil in the predetermined region. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a wiring arrangement method and a wiring arrangement program, and more particularly to a method and program for determining the arrangement of wiring in a wiring layer of a semiconductor device.

  In recent years, there has been an increasing demand for solutions to noise problems in electronic devices such as semiconductor devices. That is, EMI (Electromagnetic Interference) measures that suppress noise generated by itself and EMS (Electromagnetic Susceptibility) measures that improve resistance when exposed to noise are required at a high level.

  In order to solve such a noise problem, various techniques including a noise filter have been proposed. For example, a technique is known in which a planar spiral wiring is arranged in a double layer on a multilayer printed circuit board (for example, Patent Document 1). According to the present technology, noise radiated from the power supply system of the multilayer circuit board can be suppressed.

JP 2000-323844 A JP 2005-227256 A

  However, the demand for noise suppression has only increased, and further improvement of noise suppression measures has been demanded.

  One embodiment of the present invention has been made to solve at least a part of the above problems, and an object thereof is to provide a noise countermeasure technique in an electronic device, for example.

  The present invention can be realized as the following forms or application examples in order to solve at least a part of the above-described problems.

[Application Example 1] A method for determining a wiring arrangement in a wiring layer of a semiconductor device,
A first step of determining an arrangement of main power supply wirings in a predetermined region of the wiring layer;
A second step of determining an arrangement of a spiral coil for a noise filter in the predetermined region in accordance with an arrangement of the main power supply wiring;
A third step of determining an arrangement of a plurality of cells in an area other than the arrangement part of the main power supply wiring and the spiral coil in the predetermined area;
A method comprising:

  According to the method according to the application example 1, since the arrangement of the spiral coil is determined before the cell arrangement is determined and the cell arrangement is determined in an area other than the portion where the spiral coil is arranged, the cell is arranged first and the spiral is arranged. It is possible to prevent the space for arranging the coil from being lost.

  The method according to Application Example 1 may further include a fourth step of determining an arrangement of wirings connecting the plurality of cells. In this way, the layout of the spiral coil is determined before determining the wiring between the cells, and the layout of the wiring between the cells is determined in a region other than the portion where the spiral coil is disposed. It is possible to prevent the space for arranging the spiral coil wiring from being lost.

  The method according to Application Example 1 may further include a fifth step of deleting unnecessary spiral coils between the third step and the fourth step. In this way, unnecessary spiral coil arrangement can be prevented.

  The method according to Application Example 1 further includes, after the third step, a sixth step of determining an arrangement of a power supply wiring for supplying power to the plurality of cells from the main power supply wire via the spiral coil. May be provided. In this way, since the arrangement of the power supply wiring is determined after the spiral coil is arranged, the arrangement of the power supply wiring can be determined so that power is supplied to the cell via the spiral coil as seen from the main power supply wiring.

[Application Example 2] A method for determining a wiring arrangement in a wiring layer of a semiconductor device,
A first step of determining an arrangement of main power supply wirings in a predetermined region of the wiring layer;
A second step of determining a first region for disposing a spiral coil for a noise filter in the predetermined region according to the disposition of the main power supply wiring;
A third step of determining an arrangement of a plurality of cells in an arrangement portion of the main power supply wiring in the predetermined area and a second area that is an area other than the first area;
A fourth step of determining an arrangement of the spiral coil in the first region;
A method comprising:

  According to the method according to the application example 2, the first region is determined, and the cell arrangement is determined in a region other than the first region. Therefore, when the spiral coil is arranged, there is no region where the spiral coil is arranged. Can be prevented.

  In the method according to Application Example 2, in the fourth step, the spiral coil may be arranged according to the arrangement of the plurality of cells defined in the third step. In this way, unnecessary spiral coil arrangement can be prevented.

  The method according to Application Example 2 may further include a fifth step of determining an arrangement of wirings connecting the plurality of cells after the fourth step. In this way, the layout of the spiral coil is determined before determining the wiring between the cells, and the layout of the wiring between the cells is determined in a region other than the portion where the spiral coil is disposed. It is possible to prevent the space for arranging the spiral coil wiring from being lost.

  The method according to Application Example 2 further includes, after the fourth step, a sixth step of determining an arrangement of the power supply wiring for supplying power to the plurality of cells from the main power supply wire via the spiral coil. May be. In this way, since the arrangement of the power supply wiring is determined after the spiral coil is arranged, the arrangement of the power supply wiring can be determined so that power is supplied to the cell via the spiral coil as seen from the main power supply wiring.

Application Example 3 There is a computer program for causing a computer to determine the layout of wiring in a wiring layer of a semiconductor device,
A first function for determining an arrangement of main power supply wirings in a predetermined region of the wiring layer;
A second function for determining the arrangement of the spiral coil for the noise filter in the predetermined area according to the arrangement of the main power supply wiring;
A third function for determining the arrangement of a plurality of cells in an area other than the arrangement area of the main power supply wiring and the spiral coil in the predetermined area;
A computer program for causing the computer to realize the above.

Application Example 4 There is a computer program for causing a computer to determine the wiring arrangement in the wiring layer of a semiconductor device,
A first function for determining an arrangement of main power supply wirings in a predetermined region of the wiring layer;
A second function for defining a first area for arranging a spiral coil for a noise filter in the predetermined area according to the arrangement of the main power supply wiring;
A third function for determining the arrangement of a plurality of cells in an arrangement portion of the main power supply wiring in the predetermined area and a second area that is an area other than the first area;
A fourth function for determining an arrangement of the spiral coil in the first region;
A computer program for causing the computer to realize the above.

  According to the computer program according to the application example 3 and the application example 4, it is possible to obtain the same effects as the methods according to the application example 1 and the application example 2, respectively. In addition, the computer program according to application example 3 or application example 4 can be realized in various modes in the same manner as the method according to application example 1 and application example 2, respectively.

  The present invention can be realized in various modes, and can be realized as an apparatus invention such as a wiring arrangement apparatus that determines the arrangement of wirings in a wiring layer of a semiconductor device.

  Hereinafter, the present invention will be described based on examples with reference to the drawings.

A. Example:
・ Noise filter circuit configuration:
FIG. 1 is a diagram illustrating a circuit configuration of a noise filter. The noise filter 1 includes a first coil L1, a second coil L2, a first phase compensation capacitor C1, and a second phase compensation capacitor C2.

  The first coil L1 and the second coil L2 are connected in series. The first coil L1 and the second coil L2 are arranged so as to form electromagnetic coupling having a negative mutual inductance (−M) when the current flowing through these coils fluctuates.

  The first phase compensation capacitor C1 is disposed between the electrode on the opposite side of the electrode connected to the second coil L2 among the electrodes of the first coil L1 and the ground voltage VSS. The second phase compensation capacitor C2 is disposed between the electrode on the opposite side of the electrode connected to the first coil L1 among the electrodes of the second coil L2, and the ground voltage VSS.

  Of the electrodes of the first coil L1, the electrode opposite to the electrode connected to the second coil L2 is connected to the power supply voltage VDD output from the constant pressure power supply 2. Of the electrodes of the second coil L2, the electrode opposite to the electrode connected to the first coil L1 is connected to a load 3 that is a noise generation source. That is, the load 3 is supplied with the power supply voltage VDD from the constant voltage power supply 2 via the first coil L1 and the second coil L2.

-Noise filter 1 implementation example 1:
Next, a specific mounting example of the noise filter 1 will be described. FIG. 2 is a plan view of the semiconductor device 100 on which the noise filter 1 is mounted. The semiconductor device 100 is formed of a semiconductor such as single crystal silicon, and includes a central cell region A1 and an input / output region A2 surrounding the cell region A1.

  In the cell region A1, a gate array in which transistors (for example, MOS field effect transistors) are regularly arranged is formed (not shown). In the cell region A1, a large amount of a basic logic circuit such as a NAND circuit or a NOR circuit is constituted by these transistors and a wiring layer (hereinafter referred to as a multilayer wiring portion) formed in a number of layers above them. Cells are configured, and a predetermined logic circuit is configured by further wiring these cells.

  In the input / output region A2, a plurality of pads for electrically connecting the semiconductor device 100 and the lead frame LF are disposed along the outer edge portion. In the input / output region A2, transistors for connecting each pad to the cell region A1 are further arranged (not shown). The transistor in the input / output region A2 constitutes a protection circuit for protecting the cell region A1 from defects such as electrostatic discharge (ESD) and latch-up. In FIG. 2, to avoid complication of the drawing, among the plurality of pads, the power supply pad 10 for receiving the supply of the power supply voltage VDD for driving the cells in the cell region A1 from the outside, and the ground for the cells in the cell region A1 Only the ground pad 20 for receiving the supply of the voltage VSS from the outside is shown.

  Note that the cell region A1 and the input / output region A2 are formed with an aluminum wiring layer extending over a plurality of layers to electrically connect each electrode of the transistor on the upper surface thereof to form a circuit that exhibits a desired function. Yes.

  FIG. 3 is a schematic view showing a state in which the semiconductor device 100 is disposed on the printed circuit board 200. In FIG. 3, only the manner in which the power supply pad 10 is connected to the printed circuit board 200 is illustrated in order to avoid the complexity of the drawing, and the portions relating to the other pads are not illustrated. In FIG. 3, as elements arranged on the printed circuit board 200, a power supply line 220 that is a wiring to which the power supply voltage VDD is applied, a ground voltage line 230 that is a wiring to which the ground voltage VSS is applied, A bypass capacitor 210 is shown, and the other elements are not shown.

  As shown for the power supply pad 10 in FIG. 3, each pad is connected to one end of the lead frame LF by a wire W. The other end of the lead frame LF is located on the printed board 200 and is connected to the wiring formed on the printed board 200. As shown in FIG. 3, the power pad 10 is connected to the power supply line 220 on the printed circuit board 200 via the wire W and the lead frame LF. As a result, the power supply voltage VDD for driving each cell is supplied to the cells in the cell region A1.

  Further, a bypass capacitor 210 is disposed between the power supply line 220 and the ground voltage line 230. The bypass capacitor 210 is a capacitor for stabilizing the power supply voltage VDD.

  Although not shown, the above-described ground pad 20 has the same configuration as that of FIG. 3 and is connected to the above-described ground voltage line 230 via another wire and a lead frame. As a result, the ground voltage VSS is supplied to the cells in the cell region A1.

  Actually, the semiconductor device 100 including the cell region A1 and the input / output region A2 excludes the end portion of the lead frame LF located on the printed circuit board 200 in order to protect the semiconductor from external humidity and light. The resin is not shown in FIG. 3 to show the internal structure.

  Next, the internal configuration of the cell area A1 will be described in more detail. FIG. 4 is a diagram for explaining the arrangement of main power supply wirings in the cell region A1. The main power supply wiring includes the main power supply voltage wiring 110 to which the above-described power supply voltage VDD is supplied and the main ground voltage wiring 120 to which the above-described ground voltage VSS is supplied. In FIG. 4, the main power supply voltage wiring 110 is indicated by a thick line, and the main ground voltage wiring 120 is indicated by a thin line. The main power supply voltage wiring 110 and the main ground voltage wiring 120 include a first wiring layer (first wiring layer) and a second wiring layer (second wiring) as viewed from the semiconductor side in the multilayer wiring portion. Layer). In FIG. 3, a solid line indicates a wiring arranged in the first wiring layer, and a broken line shows a wiring arranged in the second wiring layer. Black circles D1 to D3 indicate locations where the wiring of the first wiring layer and the wiring of the second wiring layer are electrically connected by vias. Both the main power supply voltage wiring 110 and the main ground voltage wiring 120 have an annular structure along the outer edge of the cell region A1. Furthermore, the main power supply voltage wiring 110 and the main ground voltage wiring 120 both have a linear wiring connecting the vicinity of the center of the upper side of the annular structure and the vicinity of the center of the lower side.

  FIG. 5 is a diagram showing the detailed wiring configuration of regions A3 to A5 indicated by the one-dot broken line in FIG. 4A to 4C show regions A3 to A5, respectively. A plurality of power supply voltage supply lines 111 and a plurality of ground voltage supply lines 121 are arranged in the first wiring layer in the cell region A1. The power supply voltage power supply wiring 111 is a wiring for supplying the power supply voltage VDD to the transistors constituting the above-described cell. The power supply voltage supply wiring 111 is a wiring extending in the left-right direction in FIG. 4 inside the main power supply voltage wiring 110 having an annular structure. Both end portions and the central portion of the power supply voltage supply wiring 111 overlap with the main power supply voltage wiring 110 arranged in the second wiring layer, as indicated by black circles DP in FIGS. In the overlapping portion, the power supply voltage power supply wiring 111 arranged in the first wiring layer and the main power supply voltage wiring 110 arranged in the second wiring layer are electrically connected by vias. The ground voltage power supply wiring 121 is a wiring for supplying the ground voltage VSS to the transistors constituting the cells described above. The ground voltage power supply wiring 121 is a wiring extending in the left-right direction in FIG. 4 inside the main ground voltage wiring 120 having a ring structure. Both ends and the center of the ground voltage power supply wiring 121 overlap with the main ground voltage wiring 120 arranged in the second wiring layer, as indicated by black circles DP in FIGS. In this overlapping portion, the ground voltage power supply wiring 121 arranged in the first wiring layer and the main ground voltage wiring 120 arranged in the second wiring layer are electrically connected by vias.

  In the cell region A1, two power supply voltage supply lines 111 and two ground voltage supply lines 121 are alternately arranged. A spiral coil wiring 150 is formed in the middle of each power supply voltage power supply wiring 111. As shown in FIG. 5, the spiral coil wiring 150 is arranged along the wiring extending in the vertical direction in FIG. 5 in the main power supply voltage wiring 110. The detailed structure of the spiral coil wiring 150 will be described later.

  In FIGS. 5A to 5C, fine wirings other than the power supply voltage power supply wiring 111 and the ground voltage power supply wiring 121 in a region surrounded by a one-dot broken line realize a function as a basic logic circuit of the cell. In-cell wiring for connecting and inter-cell wiring which connects cells and constitutes a logic circuit is shown. The power supply voltage VDD is supplied to the transistors constituting these cells by electrically connecting the electrode of the transistor (for example, the source electrode of the P-channel MOSFET) and the power supply voltage power supply wiring 111 by the wiring. Here, there is always a spiral coil wiring 150 between the electrical connection point of the transistor electrode and the power supply voltage supply wiring 111 and the electrical connection point of the power supply voltage supply wiring 111 and the main power supply voltage wiring 110. As shown, an electrical connection point between the electrode of the transistor and the power supply voltage supply wiring 111 is arranged. In other words, as viewed from the main power supply voltage wiring 110, the wiring is performed so that power is supplied to the cell transistor via the spiral coil wiring 150 without fail.

  Next, the configuration of the spiral coil wiring 150 will be described. FIG. 6 is an enlarged view showing a region near the spiral coil wiring 150 in FIG. 7 is a cross-sectional view showing an AA cross section in FIG. FIG. 8 is a cross-sectional view showing a BB cross section in FIG. 6. FIG. 9 is a cross-sectional view showing a CC cross section in FIG. 6.

  6 to 9, a portion with rough single hatching indicates a region where wiring is formed in the first wiring layer, and a portion with fine single hatching forms wiring in the second wiring layer. The area that is being shown. In FIG. 6, the portion with cross hatching indicates a region where wiring is formed in both the first wiring layer and the second wiring layer. 6 to 9, black portions indicate regions where vias connecting the wirings of the first wiring layer and the wirings of the second wiring layer are arranged. 6 to 9, a hatched region 300 indicates an insulating layer (for example, a silicon oxide layer) that insulates between the wiring layers, and a hatched region 400 indicates a transistor or the like. The semiconductor 400 used as the board | substrate with which is formed is shown.

  The spiral coil wiring 150 includes a first spiral coil 151 formed in the second wiring layer, and a second spiral coil 152 formed in the first wiring layer. Both the first spiral coil 151 and the second spiral coil 152 have a spiral shape. Each of the first spiral coil 151 and the second spiral coil 152 has a first end that is the end on the center side of the vortex shape and a second end that is the end on the outside of the vortex shape. is doing. The first end of the first spiral coil 151 and the first end of the second spiral coil 152 are electrically connected by a via 156. Thereby, the first spiral coil 151 and the second spiral coil 152 are connected in series.

  In the second wiring layer, the first spiral coil 151 is formed in a spiral shape in which the radius is increased stepwise from the first end to the second end in a spiral shape. The second end is located on the left side in FIG.

  In the first wiring layer, the second spiral coil 152 is formed in a spiral shape that is wound twice in a spiral shape while gradually increasing the radius from the first end to the second end. The second end is located on the right side in FIG. As shown by cross hatching in FIG. 6, the second spiral coil 152 overlaps the first spiral coil 151 in the normal direction of the first wiring layer and the second wiring layer.

  Here, one spiral coil wiring 150 is arranged for one end of two adjacent power supply voltage supply wirings 111. As shown in FIGS. 6 and 7, two adjacent power supply voltage supply lines 111 are connected on the main power supply voltage line 110 side of the power supply voltage supply line 111 from the spiral coil line 150. As shown in FIG. 6 and FIG. 7, the two power supply voltage supply wirings 111 extending from the end connected to the main power supply voltage wiring 110 and the second end of the first spiral coil 151 include a plurality of They are electrically connected by vias 155.

  As shown in FIGS. 6 and 9, two power supply voltage supply wirings 111 are connected to the second end of the second spiral coil 152. The power supply voltage VDD is supplied to the transistors of each cell through the power supply voltage supply wiring 111 connected to the second end of the second spiral coil 152.

  In this embodiment, as shown in FIGS. 6 to 9, in the semiconductor 400, a column of P-channel transistors PCH formed in the horizontal direction in FIG. 6 and an N channel formed in the horizontal direction in FIG. Two rows of transistors NCH are alternately arranged. The reason why the transistors are arranged in this manner is to reduce the number of well junctions formed in the semiconductor 400. Since two power supply voltage supply wirings 111 are arranged corresponding to two columns of P-channel transistors PCH, and two ground voltage supply wirings 121 are arranged corresponding to two columns of N-channel transistors NCH, the above-mentioned As described above, the two power supply voltage supply lines 111 and the two ground voltage supply lines 121 are alternately arranged as described above.

  In the semiconductor 400, stoppers STP are formed between two adjacent P-channel transistor PCH columns and between two adjacent N-channel transistor NCH columns as shown in FIGS. The stopper STP plays a role of electrically separating two transistors facing each other across the stopper STP. The stopper STP is an impurity implantation region arranged so as to form a PN junction, the stopper STP between the columns of the P-channel transistors PCH is a P-type region, and the stopper STP between the columns of the N-channel transistors NCH is , N-type region. The stopper STP becomes a parasitic capacitance on the semiconductor 400 by the PN junction. The power supply voltage power supply wiring 111 connected to the second end of the second spiral coil 152 described above is connected to a stopper STP disposed between two columns of the P-channel transistors PCH via an aluminum wiring. (Not shown).

  The specific mounting example of the noise filter 1 shown in FIG. 1 has been described above with reference to FIGS. Here, the correspondence between the components of the mounting example described and the components of the noise filter 1 shown in FIG. 1 will be described. The first spiral coil 151 in the mounting example corresponds to the first coil L1 in FIG. The second spiral coil 152 in the mounting example corresponds to the second coil L2 in FIG. The bypass capacitor 210 in the mounting example corresponds to the first phase compensation capacitor C1 in FIG. That is, the bypass capacitor 210 in the mounting example serves as the phase compensation capacitor in the noise filter 1 as well as the original role of the bypass capacitor. A stopper STP as a parasitic capacitance corresponds to the second phase compensation capacitor C2 in FIG.

  Further, the load 3 in FIG. 1 corresponds to a cell arranged in the cell region A1 in the mounting example. 1 corresponds to a power supply that supplies the power supply voltage VDD to the power supply line 220 in the mounting example (not shown).

  A configuration corresponding to the noise filter 1 shown in FIG. 1 is mounted on the semiconductor device 100 according to the embodiment described above. Thereby, it is possible to suppress the noise generated by the operation of the logic circuit realized in the cell region A1 of the semiconductor device 100 corresponding to the load 3 from being released from the main power supply voltage wiring 110 to the outside.

  Further description will be given with reference to FIGS. FIG. 10 is a diagram schematically showing the noise filter 1 mounted on the semiconductor device 100. FIG. 11 is a diagram for explaining the effect of the noise filter 1 mounted on the semiconductor device 100. FIG. 12 is a diagram illustrating the impedance of the noise filter 1. FIG. 13 is a diagram illustrating the relationship between the phase compensation capacitance and the effect of the noise filter 1.

As shown in FIG. 10, the voltage on the load (cell region) side from the spiral coil wiring 150 among the voltages of the power supply voltage power supply wiring 111 is V _i . In the power supply voltage supply wiring 111, the voltage on the constant pressure power supply side from the spiral coil wiring 150 is set to V _O.

FIG. 11A shows the change of the voltage V _i with respect to the time axis, and FIG. 11B shows the change of the voltage V _O with respect to the time axis. As shown in FIG.
Of the voltages of the power supply voltage feed line 111, the voltage V _i of the load from the spiral coil wires 150 (cell region) side, it can be seen that contain noise generated in the load (AC component). As shown in FIG. 11B, among the voltages of the power supply voltage power supply wiring 111, the voltage V _O on the constant pressure power supply side from the spiral coil wiring 150 is significantly less in noise (AC component) than the voltage V _i. It can be seen that there is a reduction.

The reason for this will be described with reference to FIG. When noise (alternating current component) is included in the voltage V _i , current fluctuation (noise current fluctuation) occurs with the noise (alternating current component). As shown in FIG. 10, a case where the generated noise current fluctuation is in the direction shown in FIG. Then, the noise current fluctuation passes through the second spiral coil 152 and flows into the first spiral coil 151 through the via 156. The noise current fluctuation in the direction shown in FIG. 10 flows counterclockwise in the second spiral coil 152 and clockwise in the first spiral coil 151 when viewed from the upper side of FIG. Thus, the winding direction of both coils is set so that the direction in which the noise fluctuation current flows through the second spiral coil 152 and the direction in which the noise fluctuation current flows through the first spiral coil 151 are opposite to each other. Yes.

  Then, the magnetic field generated by the second spiral coil 152 (for example, the magnetic field indicated by the arrow in FIG. 10) penetrates the first spiral coil 151, and the magnetic field generated by the second spiral coil 152 The directions of the magnetic fields that pass through the spiral coil 152 are opposite to each other. Therefore, the first spiral coil 151 and the second spiral coil 152 form an electromagnetic coupling having a negative mutual inductance.

Therefore, in the first spiral coil 151, a predetermined electromotive force is generated by electromagnetic induction by the magnetic field generated by the second spiral coil 152. The predetermined electromotive force generated acts to cancel the noise fluctuation current that has passed through the second spiral coil 152. As a result, noise (alternating current component) included in the voltage V _i , that is, voltage fluctuation, is prevented from passing through the spiral coil wiring 150.

  However, in practice, if the noise filter 1 is configured by only the spiral coil wiring 150, the impedance of the spiral coil wiring 150 is inductive, so that the phase of the current change is advanced by π / 2 with respect to the phase of the voltage change. End up. Thereby, the effect as a filter hardly appears. In FIG. 12, a vector VL represents the impedance of the spiral coil wiring 150.

  Therefore, the noise filter 1 is configured by loading the spiral coil wiring 150 with a phase compensation capacitor, thereby making the impedance of the noise filter 1 capacitive. In FIG. 12, a vector VC represents the impedance of the phase compensation capacitor. When a sufficiently large phase compensation capacitor is added, the impedance of the entire noise filter 1 represented by the sum of the vector VL and the vector VC becomes capacitive as indicated by a vector VT in FIG. That is, the leading phase of the spiral coil wiring 150 is compensated by the lagging phase of the phase compensation capacitance, and the noise filter 1 as a whole has an impedance close to a resistance load (a load having no current and voltage phase shift). Then, the effect of the noise filter 1 as a filter appears remarkably.

Further description will be given with reference to FIG. FIG. 13 is a graph in which the common logarithm (log ₁₀ (V _o / V _i )) of the ratio (V _o / V _i ) of the voltage V _{o to} the voltage V _i is plotted with the frequency as the horizontal axis. The lower the value of log ₁₀ (V _o / V _i ) for a component having a higher frequency, the higher the ability as a filter (EMI filter) to suppress the noise generated on the load side from being emitted to the outside. ing. The plot G1 shows a case where the bypass capacitor 210 in the mounting example, that is, the first phase compensation capacitor C1 in the circuit diagram of the noise filter 1 shown in FIG. 1 is not added. The plot G2 shows a case where the capacitance of the bypass capacitor 210, that is, the first phase compensation capacitor C1, is set to a predetermined value A (μF: microfarad). The plot G3 shows a case where the capacitance of the bypass capacitor 210, that is, the first phase compensation capacitor C1, is 10A (μF), which is 10 times that of the plot G2. The plot G4 shows a case where the capacitance of the bypass capacitor 210, that is, the first phase compensation capacitor C1, is 100A (μF), which is 100 times the plot G2. In the plots G1 to G4, the parasitic capacitance of the stopper STP in the mounting example, that is, the second phase compensation capacitor C2 in the circuit diagram of the noise filter 1 shown in FIG. 1 is not added.

  From the graph of FIG. 13, it can be seen that the capacity of the noise filter 1 as an EMI filter increases as the first phase compensation capacitor C1 increases. That is, the larger the first phase compensation capacitor C1, the lower the AC component (noise) at a lower frequency, and the higher the AC component at a higher frequency.

  On the other hand, the size of the first phase compensation capacitor C1 is set to 10A (μF) similar to the plot G3, and the size of the second phase compensation capacitor C2 is set to a predetermined value B (μF), 10B (μF), 20B. The same plot was made with (μF). As a result, the same result as the plot G3 in which the second phase compensation capacitor C2 was not added was obtained. Therefore, it was found that the ability of the noise filter 1 as an EMI filter does not depend on the second phase compensation capacitor C2.

  In the noise filter 1, when the power supply voltage VDD is exposed to noise, the ability as an EMS filter not to propagate this noise to the additional side is opposite to the ability as an EMI filter, as opposed to the second phase compensation capacitor C2. Is larger, and does not depend on the first phase compensation capacitor C1.

  In the noise filter 1 mounted on the semiconductor device 100 in the present embodiment, the bypass capacitor 210 corresponding to the first phase compensation capacitor C1 and the stopper STP as the parasitic capacitance corresponding to the second phase compensation capacitor C2 are provided. Both are added. As a result, the noise filter 1 (the spiral coil wiring 150, the bypass capacitor 210, and the stopper STP as a parasitic capacitance) mounted on the semiconductor device 100 can function as an EMI filter that suppresses external emission of noise emitted by the load. In addition, it can function as an EMS filter that improves resistance when the power supply voltage VDD is exposed to noise.

  Further, according to this embodiment, the function of the noise filter 1 as the first phase compensation capacitor C1 is also used as the bypass capacitor 210 of the power supply voltage VDD, so that the first phase compensation capacitor for the noise filter 1 is used. There is no need to provide C1 independently. As a result, the number of parts can be reduced and the board can be downsized.

  Further, according to the present embodiment, since the parasitic capacitance of the stopper STP for separating the P-channel transistor PCH is used as the second phase compensation capacitor C2 of the noise filter 1, the second filter for the noise filter 1 is used. It is not necessary to provide the phase compensation capacitor C2 separately. As a result, the semiconductor device 100 can be reduced in size.

・ Noise filter 1 implementation example 2:
In the mounting example 1, the logic circuit is formed in the cell region, but the present invention is not limited to this. Various circuits can be formed in the cell region. In addition, since the main power supply wiring and the power supply voltage power supply wiring can be arranged in various modes in the cell region according to the circuit to be formed, the spiral coil wiring is also used for the arrangement of the main power supply wiring and the power supply voltage power supply wiring. Depending on the situation, it can be arranged in various ways.

  Another example of the cell region will be described as a mounting example 2. FIG. 14 is a diagram schematically showing a cell region A10 in the second mounting example. In FIG. 14, only the main power supply voltage wiring 110, the power supply voltage power supply wiring 111, and the spiral coil wiring 150 are illustrated, and other components are not illustrated in order to avoid the complexity of the drawing.

  The cell region A10 in the mounting example 2 is divided into a plurality of regions as indicated by broken lines, and a plurality of types of circuits are formed. That is, the cell area A10 includes a memory area A11 in which a memory such as ROM and RAM is formed, a logic area A12 in which a digital logic circuit is formed, a PLL area A13 in which a PLL (Phase Locked Loop) circuit is formed, and an analog area And an analog region A14 in which a circuit is formed. In the mounting example 2, the annular main power supply voltage wiring 110 independent of each of the regions A11 to A14 is disposed along the outer edge portion of each region. Each main power supply voltage wiring 110 is supplied with the power supply voltage VDD from the outside via an input / output region (not shown).

  In the mounting example 2, a plurality of power supply voltage supply wirings 111 having both ends connected to the main power supply voltage wiring 110 are arranged inside the annular main power supply voltage wiring 110 in each of the regions A11 to A14. A plurality of spiral coil wirings 150 are provided in the middle of each power supply voltage supply wiring 111 and in the vicinity of both ends, along the vertical power supply wiring in FIG. 19 of the main power supply voltage wiring 110. One is provided at one end of each of the two power supply voltage supply wirings 111. The cells formed in each of the regions A11 to A14 are wired so that the power supply voltage VDD is supplied via the spiral coil wiring 150.

  According to the semiconductor device having the cell region A10 configured as described above, the noise generated by the operation of the cells formed in the regions A11 to A14 by the spiral coil wiring 150 mounted as the noise filter 1 is reduced. , Can be prevented from being released to the outside. In addition, it is possible to suppress noise that has entered the power supply voltage VDD from the outside from entering cells formed in the regions A11 to A14.

-Wiring arrangement method of mounting example 1 and mounting example 2:
Next, a method for determining the wiring arrangement in the multilayer wiring portion of the semiconductor devices of mounting example 1 and mounting example 2 described above will be described. FIG. 15 is a block diagram illustrating an internal configuration of the wiring arrangement apparatus according to the embodiment. FIG. 16 is a flowchart illustrating processing steps of the wiring arrangement processing in the embodiment.

  The wiring arrangement device 1000 includes a central processing unit (CPU) 1010, an internal storage device 1020 such as a ROM and a RAM, a display unit 1030 such as a liquid crystal display, and an input unit 1040 such as a keyboard and a mouse that accept user operations. And an external storage device 1050 such as a hard disk. The wiring arrangement device 1000 is configured by, for example, a general-purpose personal computer or workstation.

  The internal storage device 1020 stores a wiring arrangement program 1021. The wiring arrangement program 1021 can be provided in the form of a storage medium such as a CD-ROM or a DVD-ROM. The wiring arrangement program 1021 is stored in the external storage device 1050 when not used, read out from the external storage device 1050 and stored in the internal storage device 1020 when used. Further, the internal storage device 1020 has a buffer area 1022 for temporarily storing various processing data when the CPU 1010 executes the wiring arrangement program 1021.

  The wiring arrangement program 1021 includes a floor plan acquisition unit M10, a netlist acquisition unit M20, a main power supply wiring arrangement unit M30, a noise filter arrangement unit M40, a cell arrangement unit M50, and a clock tree synthesis unit M60 as submodules. And a power supply wiring arrangement part M70 and an inter-cell wiring arrangement part M80.

  The external storage device 1050 stores a database DB. The database DB includes a library including cell data describing names, wiring shapes, sizes, etc., for basic logic cells such as NAND and OR, and / or composite cells combining these basic logic cells. Various data for placement and routing, such as wiring convention data defining rules, are stored.

  When the wiring arrangement process is started, the floor plan acquisition unit M10 of the wiring arrangement program 1021 acquires floor plan data, and performs floor planning based on the floor plan data (step S101). Floor planning is to determine what functions are arranged in which area on the cell area. The floor plan data is created in advance by the user using a floor plan tool or the like. As in the cell area A1 of the first mounting example, when the logic circuit is arranged on the whole, the floor planning may be omitted.

  FIG. 17 is a diagram illustrating floor planning in the cell region A10 according to the second mounting example. In the cell area A10, as shown by a broken line in FIG. 17, a memory area A11 in which a memory is arranged, a logic area A12 in which a logic circuit is arranged, a PLL area A13 in which a PLL circuit is arranged, and an analog circuit are provided. An analog area A14 to be arranged is defined.

  When the floor planning is completed, the net list acquisition unit M20 of the wiring arrangement program 1021 reads the net list and stores it in the buffer area 1022 of the internal storage device 1020 (step S102). The netlist is described in a format such as Verilog-HDL, IDIF, or VHDL, and is text data that describes basic logic cells constituting a circuit and wiring between the basic logic cells. The net list is created in advance by the user and stored in the external storage device 1050.

  When the netlist is acquired, the main power supply wiring arrangement unit M30 of the wiring arrangement program 1021 determines the arrangement of the main power supply voltage wiring 110 and the main ground voltage wiring 120 as the main power supply wiring in the cell region. (Step S103)

  FIG. 18 is a diagram conceptually illustrating a state in which the arrangement of the main power supply wiring is determined in the mounting example 1. FIG. 19 is a diagram conceptually illustrating a state in which the arrangement of the main power supply wiring is determined in the mounting example 2. 18 and 19, only the main power supply voltage wiring 110 is illustrated among the main power supply wirings in order to avoid the complexity of the drawings. In practice, the main ground voltage wiring 120 is also arranged along the main power supply voltage wiring 110 as shown in FIG. As described with reference to FIG. 4, the main power supply wiring is arranged in the cell region A1 in the mounting example 1 (FIG. 18). In the cell region A10 in the mounting example 2, a main power supply voltage wire 110 and a main ground voltage wire 120 are arranged as main power supply wires along the outer peripheral edge of each of the regions A11 to A14 shown in FIG. The voltage wiring 120 is not shown).

  When the arrangement of the main power supply wiring is determined, the noise filter arrangement unit M40 of the wiring arrangement program 1021 determines the arrangement of the spiral coil wiring 150 constituting the noise filter 1 described above (step S104).

  FIG. 20 is a diagram conceptually illustrating a state in which the arrangement of the spiral coil wiring 150 is determined in the first mounting example. FIG. 21 is a diagram conceptually illustrating a state in which the arrangement of the spiral coil wiring 150 is determined in the mounting example 2. The spiral coil wiring 150 is arranged inside the annular main power supply voltage wiring 110 along the vertical wiring in the figure of the annular main power supply voltage wiring 110. The spiral coil wirings 150 are arranged at regular intervals so as to correspond to the power supply voltage power supply wirings 111 arranged later. The spiral coil wiring 150 is arranged from the vicinity of the upper end to the lower end of the vertical power supply wiring 110 in the figure in the annular main power supply voltage wiring 110. As shown in FIG. 21, in the cell region A10, a spiral coil wiring 150 is disposed inside each main power supply voltage wiring 110 in each region A11 to A14.

  When the arrangement of the spiral coil wiring 150 is determined, the cell arrangement unit M50 of the wiring arrangement program 1021 determines the arrangement of the cells (step S105). FIG. 22 is a diagram conceptually illustrating a state in which the arrangement of the cells CL is determined in the first mounting example. FIG. 23 is a diagram conceptually illustrating a state in which the arrangement of the cells CL is determined in the mounting example 2. The cell CL is arranged in a region other than the portion where the spiral coil wiring 150 is arranged inside the annular main power supply voltage wiring 110 and main ground voltage wiring 120. The cell arrangement unit M50 arranges basic logic cells necessary for realizing the circuit described in the net list as the cell CL in accordance with the net list acquired in step S102.

  When the arrangement of the cells CL is determined, the clock tree synthesis unit M60 of the wiring arrangement program 1021 executes clock tree synthesis (step S106). Specifically, the clock tree synthesizing unit M60 determines the arrangement of wiring (clock tree wiring) related to clock load cells that operate in synchronization with the clock, such as flip-flops and registers, among the arranged cells. The clock tree synthesizing unit M60 calculates a wiring delay from the clock source to the clock load cell, and inserts a buffer on the clock tree wiring so as to reduce the clock skew.

  When the clock tree synthesis is completed, the noise filter arrangement unit M40 of the wiring arrangement program 1021 deletes the unnecessary spiral coil wiring 150. In FIG. 23, four spiral coil wirings 150 indicated by black arrows are unnecessary spiral coil wirings 150. The cells CL are not arranged in the lowermost stage of the analog area A14 and the lowermost stage of the PLL area A13. Therefore, it is not necessary to arrange the power supply voltage supply wiring 111 for supplying the power supply voltage VDD to the cell CL at the lowermost stage of the analog area A14 and the lowermost stage of the PLL area A13, and the arrangement of the spiral coil wiring 150 is also unnecessary.

  When the unnecessary spiral coil wiring 150 is deleted, the power supply wiring arrangement unit M70 of the wiring arrangement program 1021 determines the arrangement of the power supply voltage power supply wiring 111 and the ground voltage power supply wiring 121 as the power supply wiring (step S108). FIG. 24 is a diagram conceptually illustrating a state in which the arrangement of the power supply wiring is determined in the mounting example 1. FIG. 25 is a diagram conceptually illustrating a state in which the arrangement of the power supply wiring is determined in the mounting example 2. In FIGS. 24 and 25, only the power supply voltage power supply wiring 111 connected to the spiral coil wiring 150 is shown in the power supply wiring, and the ground voltage power supply wiring 121 is not shown in order to avoid the complexity of the drawings. . The power supply voltage power supply wiring 111 determines the arrangement of the power supply voltage power supply wiring so that the power supply voltage VDD is supplied to each cell CL through the spiral coil wiring 150 as viewed from the main power supply voltage wiring 110.

  When the arrangement of the power supply wiring is determined, the power supply wiring arrangement unit M70 of the wiring arrangement program 1021 determines the arrangement of the wiring (inter-cell wiring) connecting the plurality of cells according to the net list (Step S109), and the wiring arrangement processing. Exit.

  According to the wiring arrangement process described above, the arrangement of the spiral coil wiring 150 is determined before the arrangement of the cell CL, and the arrangement of the cell CL is determined in a region other than the portion where the spiral coil wiring 150 is arranged. It can be prevented that there is no space for the spiral coil wiring 150 to be disposed first.

  Further, since the arrangement of the spiral coil wiring 150 is determined before the inter-cell wiring is determined and the arrangement of the inter-cell wiring is determined in a region other than the portion where the spiral coil wiring 150 is arranged, the inter-cell wiring is arranged first and the spiral is arranged. It is possible to prevent the space for arranging the coil wiring 150 from being lost.

  Furthermore, since the arrangement of the power supply voltage power supply wiring 111 is determined after the spiral coil wiring 150 is arranged, the power supply voltage VDD is supplied to the cell CL via the spiral coil wiring 150 as viewed from the main power supply voltage wiring 110. Further, the arrangement of the power supply voltage power supply wiring 111 can be determined.

  Furthermore, since the spiral coil wiring 150 is arranged along the main power supply voltage wiring 110 in accordance with the main power supply voltage wiring 110, the power is supplied to the cell CL via the spiral coil wiring 150 as viewed from the main power supply voltage wiring 110. The power supply voltage supply wiring 111 can be easily wired so that the voltage VDD is supplied.

B. Variations:
・ First modification:
A first modification of the wiring arrangement method in the embodiment will be described. FIG. 26 is a flowchart showing the processing steps of the wiring arrangement processing in the first modification. FIG. 27 is a diagram for explaining the cell arrangement prohibition zone.

  The first modification differs from the embodiment in that instead of the arrangement of the spiral coil wiring 150 in FIG. 16 (step S104), step S1040 for setting the cell arrangement prohibition band BB is executed, and the arrangement of the cells CL. After step (S105) and clock tree synthesis (step S106), step S1070 for determining the arrangement of the spiral coil wiring 150 in the cell arrangement prohibition band BB is executed. In addition, since the arrangement of the spiral coil wiring 150 is determined according to the cell CL after the cell CL is arranged, the step S107 for removing the unnecessary spiral coil wiring 150 in the embodiment can be omitted.

  The other steps (S101 to S103, S105, S106, S108, S109) are basically the same as the steps of the same name in the embodiment, so in FIG. 26, the same reference numerals as those in FIG. Is omitted.

  When the wiring arrangement process in the first modification is started, the processes from Steps S101 to S103 are performed similarly to the wiring arrangement process in the embodiment, and the arrangement of the main power supply wiring is determined (for example, FIG. 19).

  Next, the noise filter placement unit M40 of the wiring placement program 1021 sets the cell placement prohibited band BB (step S1040). The cell placement prohibition band BB is a region for prohibiting the placement of the cells CL as a space for placing the spiral coil wiring 150 later. As shown in FIG. 27, the cell placement prohibiting band BB is provided inside the main power supply voltage wiring 110 in a band shape along the vertical wiring of the power supply voltage power supply wiring 111 in the drawing. The cell arrangement prohibition band BB extends from the upper end to the lower end of the main power supply voltage wiring 110 in the drawing. The width of the band shape of the cell arrangement prohibition band BB is determined according to the size of the spiral coil wiring 150 to be arranged.

  When the cell arrangement prohibition band BB is determined, the cell arrangement unit M50 arranges the cell CL in a region other than the cell arrangement prohibition band BB inside the annular main power supply voltage wiring 110 and main ground voltage wiring 120 (step) S105).

  Thereafter, after clock tree synthesis similar to that in the embodiment (step S106), the noise filter placement unit M40 determines the placement of the spiral coil wiring 150 inside the cell placement prohibition band BB. Since the arrangement of the cells CL has already been determined, the noise filter arrangement unit M40 determines the arrangement of the spiral coil wiring 150 according to the arranged cells CL. Specifically, the noise filter arrangement unit M40 arranges the spiral coil wiring 150 as necessary at a stage where the power supply voltage supply wiring 111 that supplies power to the cell CL needs to be arranged. Therefore, as described above, the unnecessary spiral coil wiring 150 is not disposed, and the step of deleting the unnecessary spiral coil wiring 150 can be omitted.

  When the arrangement of the spiral coil wiring 150 is determined, the arrangement of the power supply wiring (step S108) and the arrangement of the inter-cell wiring (step S109) are performed as in the embodiment, and the wiring arrangement processing is completed.

  Also in the first modified example described above, the wiring arrangement as shown in FIGS. 24 and 25 is finally performed as in the embodiment.

  According to the wiring arrangement process in the first modification, since the arrangement of the cell CL is determined after the cell arrangement prohibition band BB is set, when the spiral coil wiring 150 is arranged later, the spiral coil wiring is placed in the cell arrangement prohibition band BB. 150 can be arranged. Accordingly, it is possible to prevent the region where the spiral coil wiring 150 is disposed from being lost.

・ Second modification:
In the above-described embodiment, the wiring placement apparatus 1000 basically performs automatic placement of various wirings and cells CL. However, for example, the user uses the wiring placement apparatus 1000 to finely adjust the placement position of the cells CL and wiring. It may be operated.

・ Third modification:
In the embodiment and the first modification, the spiral coil wiring 150 is disposed in the first wiring layer and the second wiring layer. Therefore, when the semiconductor device 100 includes a multilayer wiring portion having three or more layers, other wiring (for example, in the normal direction of the spiral coil wiring 150 and the wiring layer in the third or more wiring layers, for example) , Inter-cell wiring) may be arranged.

-Fourth modification:
In the above embodiment, the logic circuit is a load as a noise generation source, but the present invention is not limited to this. The noise filter 1 can be applied to any load driven by a constant voltage. Specifically, the noise filter 1 can be applied as an EMI filter or an EMS filter for an analog circuit such as an amplifier circuit or an oscillation circuit, or a digital circuit such as a central processing unit (CPU) or a memory device. Therefore, the wiring arrangement process in the embodiment can also be used for wiring of various semiconductor devices.

-5th modification:
In the said Example, although the spiral coils 151 and 152 formed on a plane are employ | adopted as the 1st coil L1 and the 2nd coil L2 of the noise filter 1, it is not restricted to this. As the first coil L1 and the second coil L2, various coils such as a wound coil such as a spring coil or a laminated coil obtained by printing and laminating a wiring on a thin film such as a ceramic sheet can be used.

-6th modification:
In the above embodiment, a part of the configuration realized by hardware may be replaced by software, and conversely, a part of the configuration realized by software may be replaced by hardware.

  As mentioned above, although this invention was demonstrated based on the Example and the modification, Embodiment mentioned above is for making an understanding of this invention easy, and does not limit this invention. The present invention can be changed and improved without departing from the spirit and scope of the claims, and equivalents thereof are included in the present invention.

The figure which shows the circuit structure of a noise filter. The top view of the semiconductor device with which a noise filter is mounted. Schematic of the state by which the semiconductor device is arrange | positioned on the printed circuit board. The figure explaining arrangement | positioning of the main power supply wiring in a cell area | region. The figure which each showed the detailed wiring structure of the area | region shown with the dashed-dotted line in FIG. The figure which expands and shows the area | region of the spiral coil wiring vicinity in FIG. Sectional drawing which shows the AA cross section in FIG. Sectional drawing which shows the BB cross section in FIG. Sectional drawing which shows CC cross section in FIG. The figure which shows schematically the noise filter mounted in the semiconductor device. 4A and 4B illustrate an effect of a noise filter mounted on a semiconductor device. The figure which shows the impedance of a noise filter. The figure which shows the relationship between phase compensation capacity | capacitance and the effect of a noise filter. The figure which shows schematically the cell area | region in the example 2 of mounting. The block diagram which shows the internal structure of the wiring arrangement | positioning apparatus in an Example. The flowchart which shows the process step of the wiring arrangement | positioning process in an Example. It is a figure which shows the floor planning in the cell area | region of the example 2 of mounting. The figure which shows notionally the mode that arrangement | positioning of the main power supply wiring was defined in the example 1 of mounting. The figure which shows notionally the mode that arrangement | positioning of the main power supply wiring was defined in the example 2 of mounting. The figure which shows notionally the mode that arrangement | positioning of the spiral coil wiring was defined in the example 1 of mounting. The figure which shows notionally the mode that arrangement | positioning of spiral coil wiring was defined in the example 2 of mounting. The figure which shows notionally the mode that the arrangement | positioning of the cell was defined in the example 1 of mounting. The figure which shows notionally the mode that the arrangement | positioning of the cell was defined in the example 2 of mounting. The figure which shows notionally the mode that arrangement | positioning of the electric power feeding wiring was defined in the example 1 of mounting. The figure which shows notionally the mode that arrangement | positioning of the electric power feeding wiring was defined in the example 2 of mounting. The flowchart which shows the process step of a wiring arrangement | positioning process in a 1st modification. It is a figure explaining a cell arrangement prohibition zone.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Noise filter 2 ... Constant voltage power supply 3 ... Load 10 ... Power supply pad 20 ... Grounding pad 100 ... Semiconductor device 110 ... Main power supply voltage wiring 111 ... Power supply voltage power supply wiring 120 ... Main ground voltage wiring 121 ... Ground voltage power supply wiring 150 ... Spiral Coil wiring 151... First spiral coil 152... Second spiral coil 155. Via 200 .. Printed circuit board 210 .. Bypass capacitor 220 .. Power supply line 230 .. Ground voltage line 1000.
DESCRIPTION OF SYMBOLS 1020 ... Internal storage device 1021 ... Wiring arrangement program 1022 ... Buffer area 1030 ... Display part 1040 ... Input part 1050 ... External storage device A10 ... Cell area M10 ... Floor plan acquisition part M20 ... Net list acquisition part M30 ... Main power supply wiring arrangement part M40 ... Noise filter placement unit M50 ... Cell placement unit M60 ... Clock tree synthesis unit M70 ... Power supply wiring placement unit M80 ... Inter-cell wiring placement unit L1 ... First coil L2 ... Second coil C1 ... First phase compensation capacitor C2 ... Second phase compensation capacitor LF ... Lead frame PCH ... P channel transistor NCH ... N channel transistor STP ... Stopper

Claims (10)

A method for determining a wiring arrangement in a wiring layer of a semiconductor device,
A first step of determining an arrangement of main power supply wirings in a predetermined region of the wiring layer;
A second step of determining an arrangement of a spiral coil for a noise filter in the predetermined region in accordance with an arrangement of the main power supply wiring;
A third step of determining an arrangement of a plurality of cells in an area other than the arrangement part of the main power supply wiring and the spiral coil in the predetermined area;
A method comprising: The method of claim 1 further comprises:
A method comprising a fourth step of determining an arrangement of wirings connecting the plurality of cells. The method of claim 2 further comprises:
A method comprising a fifth step of removing unnecessary spiral coils between the third step and the fourth step. The method according to any one of claims 1 to 3, further comprises:
A method comprising, after the third step, a sixth step of determining an arrangement of a power supply wiring for supplying power to the plurality of cells from the main power supply wiring via the spiral coil. A method for determining a wiring arrangement in a wiring layer of a semiconductor device,
A first step of determining an arrangement of main power supply wirings in a predetermined region of the wiring layer;
A second step of determining a first region for disposing a spiral coil for a noise filter in the predetermined region according to the disposition of the main power supply wiring;
A third step of determining an arrangement of a plurality of cells in an arrangement portion of the main power supply wiring in the predetermined area and a second area that is an area other than the first area;
A fourth step of determining an arrangement of the spiral coil in the first region;
A method comprising: The method of claim 5, wherein
In the fourth step, the spiral coil is arranged according to the arrangement of the plurality of cells defined in the third step. The method according to claim 5 or claim 6 further comprises:
A method comprising, after the fourth step, a fifth step of determining an arrangement of wirings connecting the plurality of cells. The method according to any one of claims 5 to 7, further comprising:
A method comprising, after the fourth step, a sixth step of determining an arrangement of a power supply wiring for supplying power to the plurality of cells from the main power supply wiring via the spiral coil. There is a computer program for making a computer determine the wiring arrangement in the wiring layer of a semiconductor device,
A first function for determining an arrangement of main power supply wirings in a predetermined region of the wiring layer;
A second function for determining the arrangement of the spiral coil for the noise filter in the predetermined area according to the arrangement of the main power supply wiring;
A third function for determining the arrangement of a plurality of cells in an area other than the arrangement area of the main power supply wiring and the spiral coil in the predetermined area;
A computer program for causing the computer to realize the above. There is a computer program for making a computer determine the wiring arrangement in the wiring layer of a semiconductor device,
A first function for determining an arrangement of main power supply wirings in a predetermined region of the wiring layer;
A second function for determining a first region for arranging a spiral coil for a noise filter in the predetermined region according to the arrangement of the main power supply wiring;
A third function for determining the arrangement of a plurality of cells in an arrangement portion of the main power supply wiring in the predetermined area and a second area that is an area other than the first area;
A fourth function for determining an arrangement of the spiral coil in the first region;
A computer program for causing the computer to realize the above.

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