JP2009135815A - Noise filter and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a noise measure technology in an electronic device. <P>SOLUTION: A noise filter comprises: a first spiral coil; and a second spiral coil electrically series-connected to the first spiral coil. The first spiral coil and the second spiral coil are disposed so as to form an inductive coupling having a negative mutual inductance when a current flows. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a noise filter and a semiconductor device, and more particularly to a noise filter and a semiconductor device that suppress noise using a coil.

  In recent years, there has been an increasing demand for solutions to noise problems in electronic devices such as semiconductor devices. That is, EMI (Electromagnetic Interference) measures that suppress noise generated by itself and EMS (Electromagnetic Susceptibility) measures that improve resistance when exposed to noise are required at a high level.

  In order to solve such a noise problem, various techniques including a noise filter have been proposed. For example, a technique is known in which a planar spiral wiring is arranged in a double layer on a multilayer printed circuit board (for example, Patent Document 1). According to the present technology, noise radiated from the power supply system of the multilayer circuit board can be suppressed.

JP 2000-323844 A JP 2005-227256 A

  However, the demand for noise suppression has only increased, and further improvement of noise suppression measures has been demanded.

  One embodiment of the present invention has been made to solve at least a part of the above problems, and an object thereof is to provide a noise countermeasure technique in an electronic device, for example.

  The present invention can be realized as the following forms or application examples in order to solve at least a part of the above-described problems.

[Application Example 1] A noise filter,
A first spiral coil;
A second spiral coil electrically connected in series with the first spiral coil;
With
The first spiral coil and the second spiral coil are arranged so as to form an electromagnetic coupling having a negative mutual inductance when a current flows.

  According to the noise filter according to Application Example 1, it is possible to configure a noise filter that passes a constant voltage and removes a noise component.

  In the noise filter according to Application Example 1, the first spiral coil is disposed in a first region of the first layer, and the second spiral coil is a second substantially parallel to the first layer. The first spiral coil and the second spiral coil are arranged in a second region of the layer, and when the current flows, the winding direction is set so that the directions of the currents are opposite to each other, The first region and the second region may overlap in the normal direction of the first layer. In this way, it is possible to easily configure a noise filter that passes a constant voltage and removes noise components.

  In the noise filter according to Application Example 1, the first spiral coil is disposed in the first layer, the second spiral coil is disposed in the first layer, and a central portion thereof is the first layer. The winding direction of the first spiral coil and the second spiral coil is set so that the directions of the currents are opposite to each other when a current flows. The windings of the first spiral coil and the windings of the second spiral coil may be alternately arranged from the center of the first and second spiral coils toward the outer edge. In this way, it is possible to easily configure a noise filter that passes a constant voltage and removes noise components.

  The noise filter according to Application Example 1 further includes a first phase compensation capacitor, and each of the first spiral coil and the second spiral coil has a first end and a second end. The first end of the first spiral coil is electrically connected to the first end of the second spiral coil, and the second end of the second spiral coil. Is an end for connecting to a load, and the second end of the first spiral coil may be connected to the first phase compensation capacitor. In this way, it is possible to configure an EMI noise filter that suppresses the noise generated by the load from being released to the outside.

  The noise filter according to Application Example 1 further includes a second phase compensation capacitor, and each of the first spiral coil and the second spiral coil has a first end and a second end. The first end of the first spiral coil is electrically connected to the first end of the second spiral coil, and the second end of the second spiral coil. Is an end for connecting to a load, and the second end of the second spiral coil may be further connected to the second phase compensation capacitor. In this way, it is possible to configure an EMS noise filter that suppresses noise generated from the outside from propagating to the load.

  In the noise filter according to the application example 1, each of the first spiral coil and the second spiral coil has a first end and a second end, and the first spiral coil includes the first spiral coil and the second spiral coil. One end portion is electrically connected to the first end portion of the second spiral coil, and the second end portion of the second spiral coil is an end portion for connecting to a load. In addition, the second end of the first spiral coil may be an end for connecting to a constant voltage source. In this way, a constant voltage from the constant voltage source passes to the load side, but a noise filter that suppresses the passage of noise components can be configured.

  In the noise filter according to Application Example 1, the first spiral coil and the second spiral coil may be formed in a wiring layer formed on one side of the semiconductor. In this way, a noise filter can be easily formed inside the semiconductor device.

  In the noise filter according to Application Example 1, even if a plurality of voltage supply wirings for supplying a constant voltage to the load are arranged in the wiring layer, and one noise filter is arranged for the plurality of voltage supply wirings. good. In this way, the number of noise filters can be reduced.

  In the noise filter according to Application Example 1, the wiring layer may include a main power supply wiring disposed along an outer peripheral edge of the semiconductor, and the noise filter may be disposed along the main power supply wiring. good.

  In the noise filter according to Application Example 1, the second end of the first spiral coil is further connected to a constant voltage source, and the first phase compensation capacitor is configured to output the output voltage of the constant voltage source. It may also serve as a stabilizing capacity for stabilization. In this way, it is not necessary to arrange an independent first phase compensation capacitor, and the number of parts can be reduced.

  In the noise filter according to Application Example 1, the second phase compensation capacitor may be a parasitic capacitor included in a device serving as the load. In this way, it is not necessary to arrange an independent second phase compensation capacitor, and the number of parts can be reduced.

[Application Example 2] A noise filter,
A first spiral coil disposed in a first region of the first layer;
A second spiral coil disposed in a second region of the second layer substantially parallel to the first layer and electrically connected in series with the first spiral coil;
With
The winding direction of the first spiral coil and the second spiral coil is set so that the directions of the currents are opposite to each other when a current flows,
The noise filter, wherein the first region and the second region overlap in a normal direction of the first layer.

[Application Example 3] A noise filter,
A first spiral coil disposed in the first layer;
A second spiral coil disposed in the first layer, electrically connected in series with the first spiral coil, and having a central portion adjacent to the central portion of the first spiral coil;
With
The winding direction of the first spiral coil and the second spiral coil is set so that the directions of the currents are opposite to each other when a current flows,
A noise filter in which the windings of the first spiral coil and the windings of the second spiral coil are alternately arranged from the center part of the first and second spiral coils toward the outer edge part.

  According to the noise filter according to application example 2 or application example 3, it is possible to obtain the same operational effects as the noise filter according to application example 1, respectively. In addition, the noise filter according to Application Example 2 or Application Example 3 can be realized in various manners in the same manner as the noise filter according to Application Example 1.

  In addition, this invention can be implement | achieved in various aspects, for example, can be implement | achieved as a semiconductor device provided with the noise filter which concerns on the said aspect in the wiring layer formed in one side of the semiconductor.

  Hereinafter, the present invention will be described based on examples with reference to the drawings.

A. Example:
・ Noise filter circuit configuration:
FIG. 1 is a diagram illustrating a circuit configuration of a noise filter. The noise filter 1 includes a first coil L1, a second coil L2, a first phase compensation capacitor C1, and a second phase compensation capacitor C2.

  The first coil L1 and the second coil L2 are connected in series. The first coil L1 and the second coil L2 are arranged so as to form electromagnetic coupling having a negative mutual inductance (−M) when the current flowing through these coils fluctuates.

  The first phase compensation capacitor C1 is disposed between the electrode on the opposite side of the electrode connected to the second coil L2 among the electrodes of the first coil L1 and the ground voltage VSS. The second phase compensation capacitor C2 is disposed between the electrode on the opposite side of the electrode connected to the first coil L1 among the electrodes of the second coil L2, and the ground voltage VSS.

  Of the electrodes of the first coil L1, the electrode opposite to the electrode connected to the second coil L2 is connected to the power supply voltage VDD output from the constant pressure power supply 2. Of the electrodes of the second coil L2, the electrode opposite to the electrode connected to the first coil L1 is connected to a load 3 that is a noise generation source. That is, the load 3 is supplied with the power supply voltage VDD from the constant voltage power supply 2 via the first coil L1 and the second coil L2.

・ Noise filter 1 implementation example:
Next, a specific mounting example of the noise filter 1 will be described. FIG. 2 is a plan view of the semiconductor device 100 on which the noise filter 1 is mounted. The semiconductor device 100 is formed of a semiconductor such as single crystal silicon, and includes a central cell region A1 and an input / output region A2 surrounding the cell region A1.

  In the cell region A1, a gate array in which transistors (for example, MOS field effect transistors) are regularly arranged is formed (not shown). In the cell region A1, a large amount of a basic logic circuit such as a NAND circuit or a NOR circuit is constituted by these transistors and a wiring layer (hereinafter referred to as a multilayer wiring portion) formed in a number of layers above them. Cells are configured, and a predetermined logic circuit is configured by further wiring these cells.

  In the input / output region A2, a plurality of pads for electrically connecting the semiconductor device 100 and the lead frame LF are disposed along the outer edge portion. In the input / output region A2, transistors for connecting each pad to the cell region A1 are further arranged (not shown). The transistor in the input / output region A2 constitutes a protection circuit for protecting the cell region A1 from defects such as electrostatic discharge (ESD) and latch-up. In FIG. 2, to avoid complication of the drawing, among the plurality of pads, the power supply pad 10 for receiving the supply of the power supply voltage VDD for driving the cells in the cell region A1 from the outside, and the ground for the cells in the cell region A1 Only the ground pad 20 for receiving the supply of the voltage VSS from the outside is shown.

  Note that the cell region A1 and the input / output region A2 are formed with an aluminum wiring layer extending over a plurality of layers to electrically connect each electrode of the transistor on the upper surface thereof to form a circuit that exhibits a desired function. Yes.

  FIG. 3 is a schematic view showing a state in which the semiconductor device 100 is disposed on the printed circuit board 200. In FIG. 3, only the manner in which the power supply pad 10 is connected to the printed circuit board 200 is illustrated in order to avoid the complexity of the drawing, and the portions relating to the other pads are not illustrated. In FIG. 3, as elements arranged on the printed circuit board 200, a power supply line 220 that is a wiring to which the power supply voltage VDD is applied, a ground voltage line 230 that is a wiring to which the ground voltage VSS is applied, A bypass capacitor 210 is shown, and the other elements are not shown.

  As shown for the power supply pad 10 in FIG. 3, each pad is connected to one end of the lead frame LF by a wire W. The other end of the lead frame LF is located on the printed board 200 and is connected to the wiring formed on the printed board 200. As shown in FIG. 3, the power pad 10 is connected to the power supply line 220 on the printed circuit board 200 via the wire W and the lead frame LF. As a result, the power supply voltage VDD for driving each cell is supplied to the cells in the cell region A1.

  Further, a bypass capacitor 210 is disposed between the power supply line 220 and the ground voltage line 230. The bypass capacitor 210 is a capacitor for stabilizing the power supply voltage VDD.

  Although not shown, the above-described ground pad 20 has the same configuration as that of FIG. 3 and is connected to the above-described ground voltage line 230 via another wire and a lead frame. As a result, the ground voltage VSS is supplied to the cells in the cell region A1.

  Actually, the semiconductor device 100 including the cell region A1 and the input / output region A2 excludes the end portion of the lead frame LF located on the printed circuit board 200 in order to protect the semiconductor from external humidity and light. The resin is not shown in FIG. 3 to show the internal structure.

  Next, the internal configuration of the cell area A1 will be described in more detail. FIG. 4 is a diagram for explaining the arrangement of main power supply wirings in the cell region A1. The main power supply wiring includes the main power supply voltage wiring 110 to which the above-described power supply voltage VDD is supplied and the main ground voltage wiring 120 to which the above-described ground voltage VSS is supplied. In FIG. 4, the main power supply voltage wiring 110 is indicated by a thick line, and the main ground voltage wiring 120 is indicated by a thin line. The main power supply voltage wiring 110 and the main ground voltage wiring 120 include a first wiring layer (first wiring layer) and a second wiring layer (second wiring) as viewed from the semiconductor side in the multilayer wiring portion. Layer). In FIG. 3, a solid line indicates a wiring arranged in the first wiring layer, and a broken line shows a wiring arranged in the second wiring layer. Black circles D1 to D3 indicate locations where the wiring of the first wiring layer and the wiring of the second wiring layer are electrically connected by vias. Both the main power supply voltage wiring 110 and the main ground voltage wiring 120 have an annular structure along the outer edge of the cell region A1. Furthermore, the main power supply voltage wiring 110 and the main ground voltage wiring 120 both have a linear wiring connecting the vicinity of the center of the upper side of the annular structure and the vicinity of the center of the lower side.

  FIG. 5 is a diagram showing the detailed wiring configuration of regions A3 to A5 indicated by the one-dot broken line in FIG. 4A to 4C show regions A3 to A5, respectively. A plurality of power supply voltage supply lines 111 and a plurality of ground voltage supply lines 121 are arranged in the first wiring layer in the cell region A1. The power supply voltage power supply wiring 111 is a wiring for supplying the power supply voltage VDD to the transistors constituting the above-described cell. The power supply voltage supply wiring 111 is a wiring extending in the left-right direction in FIG. 4 inside the main power supply voltage wiring 110 having an annular structure. Both end portions and the central portion of the power supply voltage supply wiring 111 overlap with the main power supply voltage wiring 110 arranged in the second wiring layer, as indicated by black circles DP in FIGS. In the overlapping portion, the power supply voltage power supply wiring 111 arranged in the first wiring layer and the main power supply voltage wiring 110 arranged in the second wiring layer are electrically connected by vias. The ground voltage power supply wiring 121 is a wiring for supplying the ground voltage VSS to the transistors constituting the cells described above. The ground voltage power supply wiring 121 is a wiring extending in the left-right direction in FIG. 4 inside the main ground voltage wiring 120 having a ring structure. Both ends and the center of the ground voltage power supply wiring 121 overlap with the main ground voltage wiring 120 arranged in the second wiring layer, as indicated by black circles DP in FIGS. In this overlapping portion, the ground voltage power supply wiring 121 arranged in the first wiring layer and the main ground voltage wiring 120 arranged in the second wiring layer are electrically connected by vias.

  In the cell region A1, two power supply voltage supply lines 111 and two ground voltage supply lines 121 are alternately arranged. A spiral coil wiring 150 is formed in the middle of each power supply voltage power supply wiring 111. As shown in FIG. 5, the spiral coil wiring 150 is arranged along the wiring extending in the vertical direction in FIG. 5 in the main power supply voltage wiring 110. The detailed structure of the spiral coil wiring 150 will be described later.

  In FIGS. 5A to 5C, fine wirings other than the power supply voltage power supply wiring 111 and the ground voltage power supply wiring 121 in a region surrounded by a one-dot broken line realize a function as a basic logic circuit of the cell. In-cell wiring for connecting and inter-cell wiring which connects cells and constitutes a logic circuit is shown. The power supply voltage VDD is supplied to the transistors constituting these cells by electrically connecting the electrode of the transistor (for example, the source electrode of the P-channel MOSFET) and the power supply voltage power supply wiring 111 by the wiring. Here, there is always a spiral coil wiring 150 between the electrical connection point of the transistor electrode and the power supply voltage supply wiring 111 and the electrical connection point of the power supply voltage supply wiring 111 and the main power supply voltage wiring 110. As shown, an electrical connection point between the electrode of the transistor and the power supply voltage supply wiring 111 is arranged. In other words, as viewed from the main power supply voltage wiring 110, the wiring is performed so that power is supplied to the cell transistor via the spiral coil wiring 150 without fail.

  Next, the configuration of the spiral coil wiring 150 will be described. FIG. 6 is an enlarged view showing a region near the spiral coil wiring 150 in FIG. 7 is a cross-sectional view showing an AA cross section in FIG. FIG. 8 is a cross-sectional view showing a BB cross section in FIG. 6. FIG. 9 is a cross-sectional view showing a CC cross section in FIG. 6.

  6 to 9, a portion with rough single hatching indicates a region where wiring is formed in the first wiring layer, and a portion with fine single hatching forms wiring in the second wiring layer. The area that is being shown. In FIG. 6, the portion with cross hatching indicates a region where wiring is formed in both the first wiring layer and the second wiring layer. 6 to 9, black portions indicate regions where vias connecting the wirings of the first wiring layer and the wirings of the second wiring layer are arranged. 6 to 9, a hatched region 300 indicates an insulating layer (for example, a silicon oxide layer) that insulates between the wiring layers, and a hatched region 400 indicates a transistor or the like. The semiconductor 400 used as the board | substrate with which is formed is shown.

  The spiral coil wiring 150 includes a first spiral coil 151 formed in the second wiring layer, and a second spiral coil 152 formed in the first wiring layer. Both the first spiral coil 151 and the second spiral coil 152 have a spiral shape. Each of the first spiral coil 151 and the second spiral coil 152 has a first end that is the end on the center side of the vortex shape and a second end that is the end on the outside of the vortex shape. is doing. The first end of the first spiral coil 151 and the first end of the second spiral coil 152 are electrically connected by a via 156. Thereby, the first spiral coil 151 and the second spiral coil 152 are connected in series.

  In the second wiring layer, the first spiral coil 151 is formed in a spiral shape in which the radius is increased stepwise from the first end to the second end in a spiral shape. The second end is located on the left side in FIG.

  In the first wiring layer, the second spiral coil 152 is formed in a spiral shape that is wound twice in a spiral shape while gradually increasing the radius from the first end to the second end. The second end is located on the right side in FIG. As shown by cross hatching in FIG. 6, the second spiral coil 152 overlaps the first spiral coil 151 in the normal direction of the first wiring layer and the second wiring layer.

  Here, one spiral coil wiring 150 is arranged for one end of two adjacent power supply voltage supply wirings 111. As shown in FIGS. 6 and 7, two adjacent power supply voltage supply lines 111 are connected on the main power supply voltage line 110 side of the power supply voltage supply line 111 from the spiral coil line 150. As shown in FIG. 6 and FIG. 7, the two power supply voltage supply wirings 111 extending from the end connected to the main power supply voltage wiring 110 and the second end of the first spiral coil 151 include a plurality of They are electrically connected by vias 155.

  As shown in FIGS. 6 and 9, two power supply voltage supply wirings 111 are connected to the second end of the second spiral coil 152. The power supply voltage VDD is supplied to the transistors of each cell through the power supply voltage supply wiring 111 connected to the second end of the second spiral coil 152.

  In this embodiment, as shown in FIGS. 6 to 9, in the semiconductor 400, a column of P-channel transistors PCH formed in the horizontal direction in FIG. 6 and an N channel formed in the horizontal direction in FIG. Two rows of transistors NCH are alternately arranged. The reason why the transistors are arranged in this manner is to reduce the number of well junctions formed in the semiconductor 400. Since two power supply voltage supply wirings 111 are arranged corresponding to two columns of P-channel transistors PCH, and two ground voltage supply wirings 121 are arranged corresponding to two columns of N-channel transistors NCH, the above-mentioned As described above, the two power supply voltage supply lines 111 and the two ground voltage supply lines 121 are alternately arranged as described above.

  In the semiconductor 400, stoppers STP are formed between two adjacent P-channel transistor PCH columns and between two adjacent N-channel transistor NCH columns as shown in FIGS. The stopper STP plays a role of electrically separating two transistors facing each other across the stopper STP. The stopper STP is an impurity implantation region arranged so as to form a PN junction, the stopper STP between the columns of the P-channel transistors PCH is a P-type region, and the stopper STP between the columns of the N-channel transistors NCH is , N-type region. The stopper STP becomes a parasitic capacitance on the semiconductor 400 by the PN junction. The power supply voltage power supply wiring 111 connected to the second end of the second spiral coil 152 described above is connected to a stopper STP disposed between two columns of the P-channel transistors PCH via an aluminum wiring. (Not shown).

  The specific mounting example of the noise filter 1 shown in FIG. 1 has been described above with reference to FIGS. Here, the correspondence between the components of the mounting example described and the components of the noise filter 1 shown in FIG. 1 will be described. The first spiral coil 151 in the mounting example corresponds to the first coil L1 in FIG. The second spiral coil 152 in the mounting example corresponds to the second coil L2 in FIG. The bypass capacitor 210 in the mounting example corresponds to the first phase compensation capacitor C1 in FIG. That is, the bypass capacitor 210 in the mounting example serves as the phase compensation capacitor in the noise filter 1 as well as the original role of the bypass capacitor. A stopper STP as a parasitic capacitance corresponds to the second phase compensation capacitor C2 in FIG.

  Further, the load 3 in FIG. 1 corresponds to a cell arranged in the cell region A1 in the mounting example. 1 corresponds to a power supply that supplies the power supply voltage VDD to the power supply line 220 in the mounting example (not shown).

  A configuration corresponding to the noise filter 1 shown in FIG. 1 is mounted on the semiconductor device 100 according to the embodiment described above. Thereby, it is possible to suppress the noise generated by the operation of the logic circuit realized in the cell region A1 of the semiconductor device 100 corresponding to the load 3 from being released from the main power supply voltage wiring 110 to the outside.

  Further description will be given with reference to FIGS. FIG. 10 is a diagram schematically showing the noise filter 1 mounted on the semiconductor device 100. FIG. 11 is a diagram for explaining the effect of the noise filter 1 mounted on the semiconductor device 100. FIG. 12 is a diagram illustrating the impedance of the noise filter 1. FIG. 13 is a diagram illustrating the relationship between the phase compensation capacitance and the effect of the noise filter 1.

As shown in FIG. 10, the voltage on the load (cell region) side from the spiral coil wiring 150 among the voltages of the power supply voltage power supply wiring 111 is V _i . In the power supply voltage supply wiring 111, the voltage on the constant pressure power supply side from the spiral coil wiring 150 is set to V _O.

FIG. 11A shows the change of the voltage V _i with respect to the time axis, and FIG. 11B shows the change of the voltage V _O with respect to the time axis. As shown in FIG.
Of the voltages of the power supply voltage feed line 111, the voltage V _i of the load from the spiral coil wires 150 (cell region) side, it can be seen that contain noise generated in the load (AC component). As shown in FIG. 11B, among the voltages of the power supply voltage power supply wiring 111, the voltage V _O on the constant pressure power supply side from the spiral coil wiring 150 is significantly less in noise (AC component) than the voltage V _i. It can be seen that there is a reduction.

The reason for this will be described with reference to FIG. When noise (alternating current component) is included in the voltage V _i , current fluctuation (noise current fluctuation) occurs with the noise (alternating current component). As shown in FIG. 10, a case where the generated noise current fluctuation is in the direction shown in FIG. Then, the noise current fluctuation passes through the second spiral coil 152 and flows into the first spiral coil 151 through the via 156. The noise current fluctuation in the direction shown in FIG. 10 flows counterclockwise in the second spiral coil 152 and clockwise in the first spiral coil 151 when viewed from the upper side of FIG. Thus, the winding direction of both coils is set so that the direction in which the noise fluctuation current flows through the second spiral coil 152 and the direction in which the noise fluctuation current flows through the first spiral coil 151 are opposite to each other. Yes.

  Then, the magnetic field generated by the second spiral coil 152 (for example, the magnetic field indicated by the arrow in FIG. 10) penetrates the first spiral coil 151, and the magnetic field generated by the second spiral coil 152 The directions of the magnetic fields that pass through the spiral coil 152 are opposite to each other. Therefore, the first spiral coil 151 and the second spiral coil 152 form an electromagnetic coupling having a negative mutual inductance.

Therefore, in the first spiral coil 151, a predetermined electromotive force is generated by electromagnetic induction by the magnetic field generated by the second spiral coil 152. The predetermined electromotive force generated acts to cancel the noise fluctuation current that has passed through the second spiral coil 152. As a result, noise (alternating current component) included in the voltage V _i , that is, voltage fluctuation, is prevented from passing through the spiral coil wiring 150.

  However, in practice, if the noise filter 1 is configured by only the spiral coil wiring 150, the impedance of the spiral coil wiring 150 is inductive, so that the phase of the current change is advanced by π / 2 with respect to the phase of the voltage change. End up. Thereby, the effect as a filter hardly appears. In FIG. 12, a vector VL represents the impedance of the spiral coil wiring 150.

  Therefore, the noise filter 1 is configured by loading the spiral coil wiring 150 with a phase compensation capacitor, thereby making the impedance of the noise filter 1 capacitive. In FIG. 12, a vector VC represents the impedance of the phase compensation capacitor. When a sufficiently large phase compensation capacitor is added, the impedance of the entire noise filter 1 represented by the sum of the vector VL and the vector VC becomes capacitive as indicated by a vector VT in FIG. That is, the leading phase of the spiral coil wiring 150 is compensated by the lagging phase of the phase compensation capacitance, and the noise filter 1 as a whole has an impedance close to a resistance load (a load having no current and voltage phase shift). Then, the effect of the noise filter 1 as a filter appears remarkably.

Further description will be given with reference to FIG. FIG. 13 is a graph in which the common logarithm (log ₁₀ (V _o / V _i )) of the ratio (V _o / V _i ) of the voltage V _{o to} the voltage V _i is plotted with the frequency as the horizontal axis. The lower the value of log ₁₀ (V _o / V _i ) for a component having a higher frequency, the higher the ability as a filter (EMI filter) to suppress the noise generated on the load side from being emitted to the outside. ing. The plot G1 shows a case where the bypass capacitor 210 in the mounting example, that is, the first phase compensation capacitor C1 in the circuit diagram of the noise filter 1 shown in FIG. 1 is not added. The plot G2 shows a case where the capacitance of the bypass capacitor 210, that is, the first phase compensation capacitor C1, is set to a predetermined value A (μF: microfarad). The plot G3 shows a case where the capacitance of the bypass capacitor 210, that is, the first phase compensation capacitor C1, is 10A (μF), which is 10 times that of the plot G2. The plot G4 shows a case where the capacitance of the bypass capacitor 210, that is, the first phase compensation capacitor C1, is 100A (μF), which is 100 times the plot G2. In the plots G1 to G4, the parasitic capacitance of the stopper STP in the mounting example, that is, the second phase compensation capacitor C2 in the circuit diagram of the noise filter 1 shown in FIG. 1 is not added.

  From the graph of FIG. 13, it can be seen that the capacity of the noise filter 1 as an EMI filter increases as the first phase compensation capacitor C1 increases. That is, the larger the first phase compensation capacitor C1, the lower the AC component (noise) at a lower frequency, and the higher the AC component at a higher frequency.

  On the other hand, the size of the first phase compensation capacitor C1 is set to 10A (μF) similar to the plot G3, and the size of the second phase compensation capacitor C2 is set to a predetermined value B (μF), 10B (μF), 20B. The same plot was made with (μF). As a result, the same result as the plot G3 in which the second phase compensation capacitor C2 was not added was obtained. Therefore, it was found that the ability of the noise filter 1 as an EMI filter does not depend on the second phase compensation capacitor C2.

  In the noise filter 1, when the power supply voltage VDD is exposed to noise, the ability as an EMS filter not to propagate this noise to the additional side is opposite to the ability as an EMI filter, as opposed to the second phase compensation capacitor C2. Is larger, and does not depend on the first phase compensation capacitor C1.

  In the noise filter 1 mounted on the semiconductor device 100 in the present embodiment, the bypass capacitor 210 corresponding to the first phase compensation capacitor C1 and the stopper STP as the parasitic capacitance corresponding to the second phase compensation capacitor C2 are provided. Both are added. As a result, the noise filter 1 (the spiral coil wiring 150, the bypass capacitor 210, and the stopper STP as a parasitic capacitance) mounted on the semiconductor device 100 can function as an EMI filter that suppresses external emission of noise emitted by the load. In addition, it can function as an EMS filter that improves resistance when the power supply voltage VDD is exposed to noise.

  Further, according to this embodiment, the function of the noise filter 1 as the first phase compensation capacitor C1 is also used as the bypass capacitor 210 of the power supply voltage VDD, so that the first phase compensation capacitor for the noise filter 1 is used. There is no need to provide C1 independently. As a result, the number of parts can be reduced and the board can be downsized.

  Further, according to the present embodiment, since the parasitic capacitance of the stopper STP for separating the P-channel transistor PCH is used as the second phase compensation capacitor C2 of the noise filter 1, the second filter for the noise filter 1 is used. It is not necessary to provide the phase compensation capacitor C2 separately. As a result, the semiconductor device 100 can be reduced in size.

B. Variations:
・ First modification:
In the above embodiment, the spiral coil wiring is configured by using two layers of the first wiring layer and the second wiring layer, but is not limited thereto. For example, the spiral coil wiring can be configured using only one wiring layer. Spiral wiring configured using one wiring layer will be described as a first modification and a second modification.

  FIG. 14 is a diagram showing a spiral coil wiring 150a according to a first modification. All the wirings shown in FIG. 14 are arranged in one layer, for example, the first wiring layer. In the spiral coil wiring 150a shown in FIG. 14, the single hatched portion indicates the first spiral coil 151a, and the cross-hatched portion indicates the second spiral coil 152a.

  In the first modified example, a power supply voltage power supply wiring 111a extending from a connection end with the main power supply voltage wiring 110 is connected to an outer end of the first spiral coil 151a. The first spiral coil 151a forms a spiral shape that is spirally wound over approximately three turns counterclockwise from the outer end portion toward the center end portion. The end portion of the center portion of the first spiral coil 151a is connected to the end portion of the center portion of the second spiral coil 152a.

  The second spiral coil 152a was spirally wound along the vortex shape of the first spiral coil 151a from the end of the central portion toward the outer end, approximately three turns clockwise. A vortex shape is formed. The outer end of the second spiral coil 152a is connected to the power supply voltage power supply wiring 111a. The power supply voltage VDD is supplied to the transistors of each cell through the power supply voltage supply wiring 111a connected to the outer end of the second spiral coil 152a.

  In the spiral coil wiring 150a according to the first modified example configured as described above, the first spiral coil 151a and the second spiral coil 152a are connected in series so as to be equivalent to the circuit diagram shown in FIG. Are combined. Further, the winding direction is set so that the directions of the currents are reversed when current flows through the first spiral coil 151a and the second spiral coil 152a. That is, the first spiral coil 151a and the second spiral coil 152a are arranged so as to form electromagnetic coupling that generates a negative mutual inductance.

  The ends of the central portions of the first spiral coil 151a and the second spiral coil 152a are close to each other. Then, as can be seen by referring to the straight line LN shown in FIG. 14, the winding of the first spiral coil 151a and the winding of the second spiral coil 152a from the central part of these spiral coils 151a, 152a toward the outer edge part. The windings are arranged alternately.

  According to the first modified example described above, the same operation and effect as the example are realized.

・ Second modification:
FIG. 15 is a diagram illustrating a spiral coil wiring 150b according to a second modification. The spiral coil wiring 150b is formed in the second wiring layer. The first spiral coil 151b and the second spiral coil 152 are arranged in substantially the same shape and positional relationship as in the first modified example, but unlike the first modified example, the first spiral in the second modified example. The coil 151b and the second spiral coil 152b are connected in series at the outer end of the vortex. The power supply voltage power supply wiring 111b extending from the connection end with the main power supply voltage wiring 110 is connected to the central end of the first spiral coil 151b through the via 155b. The end of the central portion of the second spiral coil 152a is connected to the power supply voltage power supply wiring 111a on the load side. The power supply voltage VDD is supplied to the transistors of each cell through the power supply voltage supply wiring 111b connected to the end of the center portion of the second spiral coil 152b.

  In the spiral coil wiring 150b in the second modified example, as in the first modified example, the ends of the central portions of the first spiral coil 151b and the second spiral coil 152b are close to each other. Then, as can be seen by referring to the straight line LN shown in FIG. 15, the windings of the first spiral coil 151b and the second spiral coil 152b move from the center of the spiral coils 151b and 152b toward the outer edge. The windings are arranged alternately.

  According to the spiral coil wiring 150b according to the second modified example, the same operation and effect as the first modified example are realized.

・ Third modification:
In the above embodiment, one spiral coil wiring is provided for the two power supply voltage power supply wirings 111, but the present invention is not limited to this. For example, one spiral coil wiring may be provided for one power supply voltage power supply wiring 111.

  FIG. 16 is a diagram showing a spiral coil wiring 150c according to a third modification. 17 is a diagram showing a DD cross section and an EE cross section in FIG. 16.

  In FIGS. 16 and 17, a portion with rough single hatching indicates a region where wiring is formed in the first wiring layer, and a portion with fine single hatching forms wiring in the second wiring layer. The area that is being shown. In FIG. 16, the portion with cross-hatching indicates a region where wiring is formed on both the first wiring layer and the second wiring layer. In FIGS. 16 and 17, black portions indicate regions where vias connecting the wirings of the first wiring layer and the wirings of the second wiring layer are arranged. In FIG. 17, the hatched area with broken lines indicates an insulating layer (for example, a silicon oxide layer) that insulates between the wiring layers.

  In the third modification, one power supply voltage power supply wiring 111c in the first wiring layer extending from the connection end with the main power supply voltage wiring 110 is connected to the second via 155c as shown in FIGS. 16 and 17B. It is connected to the outer end of the first spiral coil 151c formed in the wiring layer. In the second wiring layer, the first spiral coil 151c is spirally wound over approximately three turns counterclockwise from the outer end toward the center end. The end portion of the center portion of the first spiral coil 151c is connected to the end portion of the center portion of the second spiral coil 152c formed in the first wiring layer via the via 156c (FIG. 16, FIG. 17 (A)).

  The second spiral coil 152c is spirally formed so as to overlap with the first spiral coil 151c of the second wiring layer over approximately three turns clockwise from the end of the central portion toward the outer end. It is rolled up. The outer end of the second spiral coil 152c is connected to the power supply voltage power supply wiring 111c. The power supply voltage VDD is supplied to the transistors of each cell through the power supply voltage supply wiring 111c connected to the outer end of the second spiral coil 152c.

  In the spiral coil wiring 150c according to the third modified example configured as described above, the first spiral coil 151c and the second spiral coil 152c are connected to the via 156c so as to be equivalent to the circuit diagram shown in FIG. Are connected in series. In addition, the winding direction is set so that the directions of the currents are opposite to each other when the current flows through the first spiral coil 151c and the second spiral coil 152c. That is, the first spiral coil 151c and the second spiral coil 152c are arranged so as to form electromagnetic coupling that generates a negative mutual inductance.

  According to the third modified example described above, the same operation and effect as the example are realized.

-Fourth modification:
In the above-described embodiments and modifications, one turn of the first spiral coil and the second spiral coil is formed in a substantially octagonal shape, but the shape of the spiral coil wiring is not limited to this. For example, spiral coil wirings having various shapes such as a polygonal shape having more than eight corners, a polygonal shape having fewer than eight corners, and a curved shape can be used.

  FIG. 18 is a diagram illustrating another example of the shape of the spiral coil wiring. A spiral coil wiring 150d shown in FIG. 18A employs a first spiral coil 151d and a second spiral coil 152d each having a substantially square shape. A spiral coil wiring 150e shown in FIG. 18B employs a first spiral coil 151e and a second spiral coil 152e each having a substantially circular shape. The configurations other than the planar shape of the spiral coil in the spiral coil wirings 150d and 150e shown in FIG. 18 are the same as the configuration of the spiral coil wiring 150c in the third modification described with reference to FIGS. Detailed explanation is omitted.

  Note that the shapes of the first spiral coil and the second spiral coil are not necessarily the same. For example, the first spiral coil may have a substantially octagonal shape, and the second spiral coil 152 may have a substantially rectangular shape.

-5th modification:
In the above embodiment, the logic circuit is formed in the cell region, but the present invention is not limited to this. Various circuits can be formed in the cell region. In addition, since the main power supply wiring and the power supply voltage power supply wiring can be arranged in various modes in the cell region according to the circuit to be formed, the spiral coil wiring is also used for the arrangement of the main power supply wiring and the power supply voltage power supply wiring. Depending on the situation, it can be arranged in various ways.

  Another example of the cell region will be described as a fifth modification. FIG. 19 is a diagram schematically showing a cell region A10 in the fifth modification. In FIG. 19, only the main power supply voltage wiring 110, the power supply voltage power supply wiring 111, and the spiral coil wiring 150 are illustrated, and other components are not illustrated in order to avoid complication of the drawing.

  The cell region A10 in the fifth modification is divided into a plurality of regions as shown by broken lines, and a plurality of types of circuits are formed. That is, the cell area A10 includes a memory area A11 in which a memory such as ROM and RAM is formed, a logic area A12 in which a digital logic circuit is formed, a PLL area A13 in which a PLL (Phase Locked Loop) circuit is formed, and an analog area And an analog region A14 in which a circuit is formed. In the present embodiment, an annular main power supply voltage wiring 110 that is independent of each of the regions A11 to A14 is disposed along the outer edge of each region. Each main power supply voltage wiring 110 is supplied with the power supply voltage VDD from the outside via an input / output region (not shown).

  In the third modification, a plurality of power supply voltage supply wirings 111 each having both ends connected to the main power supply voltage wiring 110 are arranged inside the annular main power supply voltage wiring 110 in each of the regions A11 to A14. A plurality of spiral coil wirings 150 are provided in the middle of each power supply voltage supply wiring 111 and in the vicinity of both ends, along the vertical power supply wiring in FIG. 19 of the main power supply voltage wiring 110. One is provided at one end of each of the two power supply voltage supply wirings 111. The cells formed in each of the regions A11 to A14 are wired so that the power supply voltage VDD is supplied via the spiral coil wiring 150.

  According to the semiconductor device having the cell region A10 configured as described above, the noise generated by the operation of the cells formed in the regions A11 to A14 by the spiral coil wiring 150 mounted as the noise filter 1 is reduced. , Can be prevented from being released to the outside. In addition, it is possible to suppress noise that has entered the power supply voltage VDD from the outside from entering cells formed in the regions A11 to A14.

-6th modification:
In the spiral coil wiring 150 in the embodiment and the spiral coil wirings 150b to 150d in the modification, the first spiral coil formed in the second wiring layer and the second spiral coil formed in the first wiring layer include It overlaps neatly, but it may be slightly off. It is sufficient that at least the first spiral coil and the second spiral coil connected in series are arranged so as to form an electromagnetic coupling that generates a negative mutual inductance when a current flows. For this purpose, the wirings of both the coils do not have to be neatly overlapped, but it is preferable that at least a part of the region where both the coils are arranged overlaps in the vertical direction of the wiring layer.

-Seventh modification:
In the above-described embodiments and modifications, the supply of the power supply voltage VDD to the cells in the cell region is all performed via the spiral coil wiring as a noise filter, but is not limited thereto. For example, a power supply voltage VDD is supplied to a cell having a large amount of noise during operation via a spiral coil wiring, and a power supply voltage VDD is not supplied to a cell having a small noise generation amount via a spiral coil wiring. May be fed. For example, the spiral coil wiring 150 may not be disposed in the power supply voltage power supply wiring 111 that supplies the power supply voltage VDD to a cell that generates a small amount of noise.

-Eighth modification:
In the embodiment, the logic circuit is a load as a noise generation source, but is not limited thereto. The noise filter 1 can be applied to any load driven by a constant voltage. Specifically, the noise filter 1 can be applied as an EMI filter or an EMS filter for an analog circuit such as an amplifier circuit or an oscillation circuit, or a digital circuit such as a central processing unit (CPU) or a memory device.

-Ninth modification:
In the above embodiment, the bypass capacitor 210 is employed as the first phase compensation capacitor C1 of the noise filter 1, and the stopper STP as the parasitic capacitance is employed as the second phase compensation capacitor C2. I can't. As the first phase compensation capacitor C1 and the second phase compensation capacitor C2, independent dedicated capacitors may be arranged inside or outside the semiconductor device 100. Further, when the noise filter 1 is used as an EMI filter, the second phase compensation capacitor C2 may not be provided. When the noise filter 1 is used as an EMS filter, the first phase compensation capacitor C1 is not provided. Also good.

10th modification:
In the above embodiment, the spiral coil wiring 150 is arranged between the main power supply voltage wiring 110 and the cell as a load. However, the present invention is not limited to this. For example, the spiral coil wiring 150 may be formed between the main power supply voltage wiring 110 and the power supply pad 10, specifically, in the input / output region A2.

Eleventh modification:
In the said Example, although the spiral coil formed on a plane is employ | adopted as the 1st coil L1 and the 2nd coil L2 of the noise filter 1, it is not restricted to this. As the first coil L1 and the second coil L2, various coils such as a wound coil such as a spring coil or a laminated coil obtained by printing and laminating a wiring on a thin film such as a ceramic sheet can be used.

  As mentioned above, although this invention was demonstrated based on the Example and the modification, Embodiment mentioned above is for making an understanding of this invention easy, and does not limit this invention. The present invention can be changed and improved without departing from the spirit and scope of the claims, and equivalents thereof are included in the present invention.

The figure which shows the circuit structure of a noise filter. The top view of the semiconductor device with which a noise filter is mounted. Schematic of the state by which the semiconductor device is arrange | positioned on the printed circuit board. The figure explaining arrangement | positioning of the main power supply wiring in a cell area | region. The figure which each showed the detailed wiring structure of the area | region shown with the dashed-dotted line in FIG. The figure which expands and shows the area | region of the spiral coil wiring vicinity in FIG. Sectional drawing which shows the AA cross section in FIG. Sectional drawing which shows the BB cross section in FIG. Sectional drawing which shows CC cross section in FIG. The figure which shows schematically the noise filter mounted in the semiconductor device. 4A and 4B illustrate an effect of a noise filter mounted on a semiconductor device. The figure which shows the impedance of a noise filter. The figure which shows the relationship between a phase compensation capacity | capacitance and the effect of the noise filter 1. FIG. The figure which shows the spiral coil wiring which concerns on a 1st modification. The figure which shows the spiral coil wiring which concerns on a 2nd modification. The figure which shows the spiral coil wiring which concerns on a 3rd modification. The figure which shows the DD cross section and EE cross section in FIG. The figure which shows the other example of the shape of spiral coil wiring. The figure which shows schematically the cell area | region in a 5th modification.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Noise filter 2 ... Constant voltage power supply 3 ... Load 10 ... Power supply pad 20 ... Grounding pad 100 ... Semiconductor device 110 ... Main power supply voltage wiring 111, 111a-111e ... Power supply voltage power supply wiring 120 ... Main ground voltage wiring 121 ... Ground voltage power supply Wiring 150, 150-150e ... Spiral coil wiring 151, 151a-151e ... First spiral coil 152, 152a-152e ... Second spiral coil 155, 155c-155e, 156c-156e ... Via 200 ... Printed circuit board 210 ... Bypass Capacitor 220 ... Power supply line 230 ... Ground voltage line L1 ... First coil L2 ... Second coil C1 ... First phase compensation capacitor C2 ... Second phase compensation capacitor LF ... Lead frame PCH ... P channel transistor NCH ... N Channel transistor STP ... stopper

Claims (14)

A noise filter,
A first spiral coil;
A second spiral coil electrically connected in series with the first spiral coil;
With
The first spiral coil and the second spiral coil are arranged so as to form an electromagnetic coupling having a negative mutual inductance when a current flows. The noise filter according to claim 1,
The first spiral coil is disposed in a first region of a first layer;
The second spiral coil is disposed in a second region of a second layer substantially parallel to the first layer;
The winding direction of the first spiral coil and the second spiral coil is set so that the directions of the currents are opposite to each other when a current flows,
The noise filter, wherein the first region and the second region overlap in a normal direction of the first layer. The noise filter according to claim 1,
The first spiral coil is disposed in a first layer;
The second spiral coil is disposed in the first layer, and a central portion is close to a central portion of the first spiral coil,
The winding direction of the first spiral coil and the second spiral coil is set so that the directions of the currents are opposite to each other when a current flows,
A noise filter in which the windings of the first spiral coil and the windings of the second spiral coil are alternately arranged from the center part of the first and second spiral coils toward the outer edge part. The noise filter according to any one of claims 1 to 3,
A first phase compensation capacitor;
Each of the first spiral coil and the second spiral coil has a first end and a second end;
The first end of the first spiral coil is electrically connected to the first end of the second spiral coil;
The second end of the second spiral coil is an end for connecting to a load;
The noise filter, wherein the second end of the first spiral coil is connected to the first phase compensation capacitor. The noise filter according to any one of claims 1 to 4,
A second phase compensation capacitor;
Each of the first spiral coil and the second spiral coil has a first end and a second end;
The first end of the first spiral coil is electrically connected to the first end of the second spiral coil;
The second end of the second spiral coil is an end for connecting to a load;
The noise filter, wherein the second end of the second spiral coil is further connected to the second phase compensation capacitor. The noise filter according to any one of claims 1 to 5,
Each of the first spiral coil and the second spiral coil has a first end and a second end;
The first end of the first spiral coil is electrically connected to the first end of the second spiral coil;
The second end of the second spiral coil is an end for connecting to a load;
The noise filter, wherein the second end of the first spiral coil is an end for connection to a constant voltage source. The noise filter according to any one of claims 1 to 6,
The first spiral coil and the second spiral coil are noise filters formed in a wiring layer formed on one side of a semiconductor. The noise filter according to claim 7,
In the wiring layer, a plurality of voltage supply wirings for supplying a constant voltage to the load are arranged,
A noise filter in which one noise filter is arranged for a plurality of voltage supply wirings. The noise filter according to claim 7,
In the wiring layer, the main power supply wiring arranged along the outer periphery of the semiconductor is arranged,
The noise filter is a noise filter disposed along the main power supply wiring. The noise filter according to claim 4,
The second end of the first spiral coil is further connected to a constant voltage source;
The first phase compensation capacitor is a noise filter that also serves as a stabilization capacitor for stabilizing the output voltage of the constant voltage source. The noise filter according to claim 5,
The second phase compensation capacitor is a noise filter that is a parasitic capacitor included in the device serving as the load.   A semiconductor device comprising the noise filter according to claim 1 in a wiring layer formed on one side of a semiconductor. A noise filter,
A first spiral coil disposed in a first region of the first layer;
A second spiral coil disposed in a second region of the second layer substantially parallel to the first layer and electrically connected in series with the first spiral coil;
With
The winding direction of the first spiral coil and the second spiral coil is set so that the directions of the currents are opposite to each other when a current flows,
The noise filter, wherein the first region and the second region overlap in a normal direction of the first layer. A noise filter,
A first spiral coil disposed in the first layer;
A second spiral coil disposed in the first layer, electrically connected in series with the first spiral coil, and having a central portion adjacent to the central portion of the first spiral coil;
With
The winding direction of the first spiral coil and the second spiral coil is set so that the directions of the currents are opposite to each other when a current flows,
A noise filter in which the windings of the first spiral coil and the windings of the second spiral coil are alternately arranged from the center part of the first and second spiral coils toward the outer edge part.

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