JP6930266B2 - How to drive the power converter - Google Patents
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Description
本発明は、直流電力から交流電力に変換を行う電力変換装置に関する発明であり、そのスイッチング素子の駆動方法に関する技術をここに開示する。 The present invention relates to a power conversion device that converts DC power to AC power, and discloses a technique relating to a driving method of the switching element.
直流電力を交流電力に変換する電力変換装置には、ＩＧＢＴ（Insulated Gate Bipolar Transistor）、ＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor）等のスイッチング素子が使用される。その代表的な回路構成について、特許文献１の図７に示される三相交流電動機を参照して説明する。この三相交流電動機を駆動する当該電力変換装置の主回路では、還流ダイオードを逆並列接続したスイッチング素子を２つ同極性で直列接続して一相分の上下アームが構成されている。そのスイッチング素子の接続点が交流出力端子となる。この一相分の上下アームが直流電源の高電位側と低電位側との間に三相分、並列接続されている。 Switching elements such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are used in the power conversion device that converts DC power into AC power. A typical circuit configuration thereof will be described with reference to the three-phase AC motor shown in FIG. 7 of Patent Document 1. In the main circuit of the power conversion device that drives the three-phase AC motor, two switching elements in which freewheeling diodes are connected in antiparallel are connected in series with the same polarity to form an upper and lower arm for one phase. The connection point of the switching element becomes an AC output terminal. The upper and lower arms for one phase are connected in parallel for three phases between the high potential side and the low potential side of the DC power supply.
直流−交流変換動作時、上下アームのスイッチング素子がスイッチング駆動されて交互にオン・オフを繰り返す。このスイッチング素子は、特にオンからオフへ切り換わるターンオフ時に、本質的にスイッチング応答の遅れをもつため、直列接続された上下アームのスイッチング素子が同時にオン状態となり、電力変換装置に接続された直流電源の短絡が発生し得る。この短絡を防ぐため、上下アームのスイッチング素子のオン−オフ切り換え時、短絡防止期間として両スイッチング素子を共にオフさせるデッドタイムを設けている。 During the DC-AC conversion operation, the switching elements of the upper and lower arms are switched and driven to alternately turn on and off. Since this switching element essentially has a delay in the switching response, especially at the time of turn-off when switching from on to off, the switching elements of the upper and lower arms connected in series are turned on at the same time, and the DC power supply connected to the power converter. Short circuit can occur. In order to prevent this short circuit, a dead time is provided as a short circuit prevention period when both switching elements are turned off when the switching elements of the upper and lower arms are switched on and off.
上記デッドタイムにおいて、特許文献１の段落０００６〜０００８にも述べられているように、スイッチング素子がスイッチングする時にサージ電圧が発生し、関連素子に悪影響を与える。本発明は、このデッドタイムにおいて発生するサージ電圧を抑制することを目的とする。 In the dead time, as described in paragraphs 0006 to 0008 of Patent Document 1, a surge voltage is generated when the switching element is switched, which adversely affects the related element. An object of the present invention is to suppress a surge voltage generated during this dead time.
本発明に係る電力変換装置は、ダイオードがそれぞれ逆並列接続された少なくとも２つのスイッチング素子を直流電源の高電位側と低電位側との間に直列接続して上下アームを構成した電力変換装置である。本発明によれば、前記スイッチング素子として逆導通可能な素子を使用し、その駆動方法において、前記スイッチング素子を両方ともオフにするデッドタイムの期間に、オンからオフへターンオフさせる前記スイッチング素子の駆動電圧を、オフ電圧より高く且つ当該スイッチング素子のしきい値電圧より低い電圧に維持することを特徴とする。 The power conversion device according to the present invention is a power conversion device in which at least two switching elements in which diodes are connected in antiparallel are connected in series between the high potential side and the low potential side of a DC power supply to form an upper and lower arm. be. According to the present invention, an element capable of reverse conduction is used as the switching element, and in the driving method thereof, the switching element is driven to turn off from on to off during a dead time period in which both of the switching elements are turned off. The voltage is maintained at a voltage higher than the off voltage and lower than the threshold voltage of the switching element.
本発明の駆動方法によれば、デッドタイムにおいて、ターンオフさせるスイッチング素子の駆動電圧、すなわち制御端子の電圧を、オフ電圧ではなく且つしきい値電圧より低い電圧に維持する。しきい値電圧よりは低い電圧なので当該スイッチング素子は順方向に関しオンにはならず、前述の同時オン短絡は防止される。一方、このスイッチング素子は逆導通可能素子なので、オフ電圧ではない駆動電圧の印加で還流電流を通す能力をもつ。すなわち、デッドタイムにおいて、逆並列接続したダイオードとスイッチング素子の両者を通じて還流電流を流すことができる。並列接続となったスイッチング素子を通して還流電流を分流するので、ダイオードの逆回復電流についてｄｉ／ｄｔ（電流変化率）が緩和され、サージ電圧が抑制される。 According to the driving method of the present invention, the driving voltage of the switching element to be turned off, that is, the voltage of the control terminal is maintained at a voltage lower than the threshold voltage and not the off voltage during the dead time. Since the voltage is lower than the threshold voltage, the switching element does not turn on in the forward direction, and the above-mentioned simultaneous on short circuit is prevented. On the other hand, since this switching element is a reverse conductive element, it has the ability to pass a reflux current by applying a drive voltage other than the off voltage. That is, in the dead time, a reflux current can flow through both the diode connected in antiparallel and the switching element. Since the return current is shunted through the switching elements connected in parallel, the di / dt (current change rate) of the reverse recovery current of the diode is relaxed and the surge voltage is suppressed.
一例として図１に示す電力変換装置の主回路は、２レベルインバータの主要部であり、前述の特許文献１の図７に示された三相電力変換装置における一相分に相当する。電力変換装置は、負荷に接続されている。
この電力変換装置は、２つの逆導通可能なスイッチング素子Ｑ１，Ｑ２と、これに逆並列接続された還流用のダイオードＤ１，Ｄ２と、を用いて構成される。スイッチング素子Ｑ１，Ｑ２のそれぞれにダイオードＤ１，Ｄ２が逆並列接続されていて、当該スイッチング素子Ｑ１，Ｑ２及びダイオードＤ１，Ｄ２の組が、直流電源Ｅの高電位側と低電位側との間に同極性で直列接続されている。スイッチング素子Ｑ１及びダイオードＤ１の組から上アームが、スイッチング素子Ｑ２及びダイオードＤ２の組から下アームが、それぞれ構成されて、これら上アームと下アームの接続点から交流出力が得られる。上述のように電力変換装置は負荷に接続されているが、図１では、上アームと下アームの接続点に接続されるインダクタンス（Ｌ）として図示している。この接続される負荷のため、一般的に出力電流と出力電圧に位相差が生じる。本実施形態では位相差９０°とするが、出力電圧のゼロクロスポイント付近で出力電流の極性が変化しないのであれば、位相差はこの値に限らない。
As an example, the main circuit of the power conversion device shown in FIG. 1 is the main part of the two-level inverter, and corresponds to one phase in the three-phase power conversion device shown in FIG. 7 of Patent Document 1 described above. The power converter is connected to the load.
This power conversion device is configured by using two reverse conductive switching elements Q1 and Q2 and return diodes D1 and D2 connected in antiparallel to the switching elements Q1 and Q2. Diodes D1 and D2 are connected in antiparallel to each of the switching elements Q1 and Q2, and the pair of the switching elements Q1 and Q2 and the diodes D1 and D2 is located between the high potential side and the low potential side of the DC power supply E. They are connected in series with the same polarity. An upper arm is formed from the set of the switching element Q1 and the diode D1, and a lower arm is formed from the set of the switching element Q2 and the diode D2, respectively, and an AC output is obtained from the connection point between the upper arm and the lower arm. As described above, the power conversion device is connected to the load, but in FIG. 1, it is shown as an inductance (L) connected to the connection point between the upper arm and the lower arm. Due to this connected load, there is generally a phase difference between the output current and the output voltage. In the present embodiment, the phase difference is 90 °, but the phase difference is not limited to this value as long as the polarity of the output current does not change near the zero cross point of the output voltage.
本実施形態の逆導通可能なスイッチング素子Ｑ１，Ｑ２には、ＭＯＳＦＥＴが現時点で適している。ＭＯＳＦＥＴは、構造的にボディダイオードを有することにより常に逆導通が可能な素子である。このＭＯＳＦＥＴに対し逆並列接続するダイオードＤ１，Ｄ２には、匹敵する高速のダイオードとしてＳＢＤ（Schottky Barrier Diode）を使用する。各素子は、通常Ｓｉからなる半導体で構成されるが、ワイドバンドギャップ半導体で構成してもよい。ワイドバンドギャップ半導体とは、例えばＳｉＣ、ＧａＮ、ダイヤモンド等の半導体である。 MOSFETs are currently suitable for the reverse conductive switching elements Q1 and Q2 of the present embodiment. A MOSFET is an element that can always be reverse-conducted by having a body diode structurally. For the diodes D1 and D2 connected in antiparallel to this MOSFET, SBD (Schottky Barrier Diode) is used as a comparable high-speed diode. Each element is usually composed of a semiconductor made of Si, but may be composed of a wide bandgap semiconductor. The wide bandgap semiconductor is, for example, a semiconductor such as SiC, GaN, or diamond.
図２に、図１に示すスイッチング素子Ｑ１，Ｑ２の制御端子に、図示しない駆動回路から印加する駆動電圧の従来技術に従う波形（ゲート−ソース間の電圧波形）と、そのデッドタイムにおけるサージ電圧の発生について示してある。
図２Ａに示す通り、スイッチング素子Ｑ１，Ｑ２の制御端子であるゲートには、オン電圧（一例として１５Ｖ）とオフ電圧（一例として−５Ｖ）とを交互に繰り返す駆動電圧が印加され、この駆動電圧は、上アームのスイッチング素子Ｑ１と下アームのスイッチング素子Ｑ２とに対し互いに逆位相で印加される。且つ、前述した同時オン短絡を防ぐ目的で、一方のスイッチング素子Ｑ１（Ｑ２）をターンオフさせるときに、他方のスイッチング素子Ｑ２（Ｑ１）のターンオンを遅らせて両者オフの期間を設けるデッドタイムが、オン電圧からオフ電圧へ遷移する一方の駆動電圧とオフ電圧からオン電圧へ遷移する他方の駆動電圧との間に設定されている。
FIG. 2 shows a waveform (voltage waveform between gate and source) of a drive voltage applied to the control terminals of the switching elements Q1 and Q2 shown in FIG. 1 according to the prior art of a drive voltage (not shown), and a surge voltage at the dead time. The outbreak is shown.
As shown in FIG. 2A, a drive voltage that alternately repeats an on voltage (15 V as an example) and an off voltage (-5 V as an example) is applied to the gate that is the control terminal of the switching elements Q1 and Q2, and this drive voltage is applied. Is applied to the switching element Q1 of the upper arm and the switching element Q2 of the lower arm in opposite phases to each other. Further, for the purpose of preventing the simultaneous on-circuit short circuit described above, when one switching element Q1 (Q2) is turned off, the dead time for delaying the turn-on of the other switching element Q2 (Q1) and providing a period during which both are off is set to on. It is set between one drive voltage that transitions from voltage to off voltage and the other drive voltage that transitions from off voltage to on voltage.
ここでは、出力電圧の極性が正から負へ変化するゼロクロスポイント付近であって、出力電流が正（図１の矢印の向き）である場合の動作を説明している。なお、出力電圧の極性が負から正へ変化するゼロクロスポイント付近であって、出力電流が負である場合も、回路の対称性から動作としては同じである。以下、動作についての説明は同様とする。例えば、スイッチング素子Ｑ２の駆動電圧がオン電圧からオフ電圧へ遷移し、スイッチング素子Ｑ１の駆動電圧がオフ電圧からオン電圧へ遷移するときのデッドタイムを見てみる。このデッドタイムより前からスイッチング素子Ｑ１はオフしているので、スイッチング素子Ｑ２がターンオフする前には、該スイッチング素子Ｑ２及びダイオードＤ２を通して還流電流が流れている。デッドタイムに入ってスイッチング素子Ｑ２がターンオフすると、還流電流はダイオードＤ２のみを通して流れることになる。次いでデッドタイムの終わりにスイッチング素子Ｑ１がターンオンすると、図２Ｂに示す通り、ダイオードＤ２に逆回復電圧がかかって逆回復電流が流れる。この初期に、ダイオードＤ２のもつ寄生容量が充電されるため、当該寄生容量と回路にある寄生インダクタンスＬとで共振が発生し、逆回復電圧にサージ電圧が発生する。このときの詳細波形が図３のシミュレーション結果に示されていて、スイッチング素子Ｑ１のゲート電圧がオン電圧へ向かい上昇してしきい値電圧（素子のターンオンに必要な最低限のゲート電圧）を越えるのに合わせて、ダイオードＤ２の逆回復電圧及び逆回復電流が生じて一時的に発振し、サージ電圧を生成している。 Here, the operation when the polarity of the output voltage changes from positive to negative near the zero cross point and the output current is positive (in the direction of the arrow in FIG. 1) will be described. Even when the polarity of the output voltage is near the zero cross point where the polarity changes from negative to positive and the output current is negative, the operation is the same due to the symmetry of the circuit. Hereinafter, the description of the operation will be the same. For example, let's look at the dead time when the drive voltage of the switching element Q2 transitions from the on voltage to the off voltage and the drive voltage of the switching element Q1 transitions from the off voltage to the on voltage. Since the switching element Q1 is turned off before the dead time, a reflux current flows through the switching element Q2 and the diode D2 before the switching element Q2 is turned off. When the switching element Q2 turns off in the dead time, the return current flows only through the diode D2. Then, when the switching element Q1 is turned on at the end of the dead time, as shown in FIG. 2B, a reverse recovery voltage is applied to the diode D2 and a reverse recovery current flows. Since the parasitic capacitance of the diode D2 is charged at this initial stage, resonance occurs between the parasitic capacitance and the parasitic inductance L in the circuit, and a surge voltage is generated in the reverse recovery voltage. The detailed waveform at this time is shown in the simulation result of FIG. 3, and the gate voltage of the switching element Q1 rises toward the on voltage and exceeds the threshold voltage (the minimum gate voltage required for turning on the element). In accordance with the above, the reverse recovery voltage and the reverse recovery current of the diode D2 are generated and temporarily oscillate to generate a surge voltage.
このサージ電圧を抑制するために、特許文献１では、ツェナーダイオードをスイッチング素子のゲート−ドレイン間に接続し、サージ電圧を当該ツェナーダイオードの降伏電圧でもってクランプすることが提案されている。これを実現するため、特許文献１の場合、ツェナーダイオードの降伏電圧でスイッチング素子が容易にオン状態へ移行するように、デッドタイムにおいてスイッチング素子のゲートをしきい値電圧近くまで予め充電する制御を実行する（特許文献１の段落００２８）。すなわち、オフ電圧によりスイッチング素子を完全にオフさせてしまうと、降伏電流が流れ込んでもスイッチング素子がオン状態に移行しないためである。特許文献１の実施例におけるスイッチング素子は逆方向に導通させることができないので、ツェナーダイオードによる降伏電圧制御を行うしかない。 In order to suppress this surge voltage, Patent Document 1 proposes connecting a Zener diode between the gate and drain of the switching element and clamping the surge voltage with the breakdown voltage of the Zener diode. In order to realize this, in the case of Patent Document 1, control is performed in which the gate of the switching element is pre-charged to near the threshold voltage during the dead time so that the switching element easily shifts to the on state due to the breakdown voltage of the Zener diode. Execute (Patent Document 1 paragraph 0028). That is, if the switching element is completely turned off by the off voltage, the switching element does not shift to the on state even if the yield current flows. Since the switching element in the embodiment of Patent Document 1 cannot be conducted in the opposite direction, there is no choice but to control the yield voltage by a Zener diode.
本発明の実施形態に係る駆動電圧の波形と、そのデッドタイムにおけるサージ電圧の発生について、図４に示す。
図４Ａに示す通り、スイッチング素子Ｑ１，Ｑ２の制御端子であるゲートには、オン電圧（一例として上記同様１５Ｖ）とオフ電圧（一例として上記同様−５Ｖ）とを交互に繰り返す駆動電圧が印加され、この駆動電圧は、上アームのスイッチング素子Ｑ１と下アームのスイッチング素子Ｑ２とに対し互いに逆位相で提供される。且つ、前述した同時オン短絡を防ぐ目的で、一方のスイッチング素子Ｑ１（Ｑ２）をターンオフさせるときに、他方のスイッチング素子Ｑ２（Ｑ１）のターンオンを遅らせて両者オフの期間を設けるデッドタイムが、オン電圧からオフ電圧へ遷移する一方の駆動電圧とオフ電圧からオン電圧へ遷移する他方の駆動電圧との間に設定されている。
FIG. 4 shows the waveform of the drive voltage according to the embodiment of the present invention and the generation of the surge voltage during the dead time.
As shown in FIG. 4A, a drive voltage that alternately repeats an on voltage (15 V as above as an example) and an off voltage (-5 V as above as an example) is applied to the gate which is a control terminal of the switching elements Q1 and Q2. , This drive voltage is provided in opposite phases to the switching element Q1 of the upper arm and the switching element Q2 of the lower arm. Further, for the purpose of preventing the simultaneous on-circuit short circuit described above, when one switching element Q1 (Q2) is turned off, the dead time for delaying the turn-on of the other switching element Q2 (Q1) and providing a period during which both are off is set to on. It is set between one drive voltage that transitions from voltage to off voltage and the other drive voltage that transitions from off voltage to on voltage.
本実施形態において、例えば、スイッチング素子Ｑ２の駆動電圧がオン電圧からオフ電圧へ遷移し、スイッチング素子Ｑ１の駆動電圧がオフ電圧からオン電圧へ遷移するときのデッドタイムを見てみると、ターンオフさせるスイッチング素子Ｑ２のゲートへ印加する駆動電圧が、完全にスイッチング素子Ｑ２をオフさせるオフ電圧まで下がらず、このオフ電圧よりも高いが、スイッチング素子Ｑ２のしきい値電圧よりは低い電圧（例えばオフ電圧としきい値電圧の中間電位近傍）に、維持されている。一例としてＭＯＳＦＥＴのしきい値電圧、すなわち当該素子を順方向にオンさせるターンオン電圧は５Ｖ程度に設定されるので、このデッドタイムにおけるスイッチング素子Ｑ２の駆動電圧は、５Ｖよりも１Ｖ程度低い値に設定する。逆の場合も同様であり、ターンオフさせるスイッチング素子Ｑ１の駆動電圧がデッドタイムの間、オフ電圧よりは高く且つしきい値電圧よりは低い値に維持される。 In the present embodiment, for example, looking at the dead time when the drive voltage of the switching element Q2 transitions from the on voltage to the off voltage and the drive voltage of the switching element Q1 transitions from the off voltage to the on voltage, it turns off. The drive voltage applied to the gate of the switching element Q2 does not drop to the off voltage that completely turns off the switching element Q2, which is higher than this off voltage but lower than the threshold voltage of the switching element Q2 (for example, the off voltage). And near the intermediate potential of the threshold voltage). As an example, the threshold voltage of the MOSFET, that is, the turn-on voltage for turning on the element in the forward direction is set to about 5 V, so the drive voltage of the switching element Q2 at this dead time is set to a value about 1 V lower than 5 V. do. The same applies to the opposite case, and the drive voltage of the switching element Q1 to be turned off is maintained at a value higher than the off voltage and lower than the threshold voltage during the dead time.
この例のデッドタイムにおいてターンオフさせるスイッチング素子Ｑ２に対し維持される駆動電圧は、デッドタイムの終了と同時にオフ電圧へ落とすように制御してもよいが、デッドタイム終了でターンオンさせる他方のスイッチング素子Ｑ１の駆動電圧をオン電圧へ上げた後に、例示する−５Ｖのオフ電圧まで落とす方が好ましい。すなわち、デッドタイムの期間よりも長く維持してからオフ電圧へ落とすようにする。サージ電圧は他方のスイッチング素子Ｑ１のターンオンに伴って生じるので、このような制御が適している。 The drive voltage maintained for the switching element Q2 to be turned off at the dead time of this example may be controlled to drop to the off voltage at the same time as the end of the dead time, but the other switching element Q1 to be turned on at the end of the dead time. It is preferable to raise the driving voltage of the above to the on-voltage and then drop it to the off-voltage of -5V as illustrated. That is, the voltage is reduced to the off voltage after being maintained longer than the dead time period. Since the surge voltage is generated with the turn-on of the other switching element Q1, such control is suitable.
本実施形態に係る図４の駆動方法によれば、デッドタイムにおいて、ターンオフさせるスイッチング素子Ｑ２に印加する駆動電圧は、該素子Ｑ２のしきい値電圧よりは低い電圧なので当該スイッチング素子Ｑ２は順方向に関しオンにはならず、したがって、前述のような同時オン短絡は防止される。一方、ＭＯＳＦＥＴを用いたスイッチング素子Ｑ２は逆導通可能素子なので、オフ電圧ではない駆動電圧の印加で還流電流を通す能力をもつ（図１の点線矢示）。すなわち、デッドタイムにおいて、逆並列接続したダイオードＤ２と共にスイッチング素子Ｑ２も、還流電流を流すために使用される。並列接続となったスイッチング素子Ｑ２を通して還流電流を分流するので、ダイオードＤ２については、逆回復電流についてｄｉ／ｄｔ（電流変化率）が緩和される。 According to the drive method of FIG. 4 according to the present embodiment, the drive voltage applied to the switching element Q2 to be turned off during the dead time is lower than the threshold voltage of the element Q2, so that the switching element Q2 is in the forward direction. Therefore, the simultaneous on short circuit as described above is prevented. On the other hand, since the switching element Q2 using MOSFET is a reverse conductive element, it has the ability to pass a reflux current by applying a drive voltage other than the off voltage (dotted arrow in FIG. 1). That is, in the dead time, the switching element Q2 is also used to pass the reflux current together with the diode D2 connected in antiparallel. Since the return current is diverted through the switching element Q2 connected in parallel, the di / dt (current change rate) of the reverse recovery current is relaxed for the diode D2.
この還流電流の分流に使用するＭＯＳＦＥＴのスイッチング素子に起因するサージ電圧は、ダイオードに比べて格段に低い。したがって、ダイオードＤ２だけで還流を行う従来の駆動方法に比べて、スイッチング素子Ｑ２及びダイオードＤ２の並列接続で還流を行う本実施形態の方が、図４Ｂから分かる通り、サージ電圧が抑制される。このときの詳細波形について、図５のシミュレーション結果に、図３で示した波形と重ねて示してある。図３の波形に比べると、図５の波形はなだらかになっていて、サージ電圧のピーク値が抑えられていることが分かる。なお、本実施形態の説明では、出力電圧の極性が正から負へ変化するゼロクロスポイント付近であって、出力電流が正である場合としているが、ゼロクロスポイント付近以外の場合であっても、還流電流を分流させるという動作は適用可能である。 The surge voltage caused by the switching element of the MOSFET used for the shunting of the reflux current is much lower than that of the diode. Therefore, as can be seen from FIG. 4B, the surge voltage is suppressed in the present embodiment in which the switching element Q2 and the diode D2 are connected in parallel to perform reflux, as compared with the conventional driving method in which reflux is performed only by the diode D2. The detailed waveform at this time is shown in the simulation result of FIG. 5 by superimposing the waveform shown in FIG. Compared with the waveform of FIG. 3, the waveform of FIG. 5 is gentle, and it can be seen that the peak value of the surge voltage is suppressed. In the description of the present embodiment, it is assumed that the polarity of the output voltage is near the zero cross point where the polarity changes from positive to negative and the output current is positive. The operation of splitting the current is applicable.
前述した特許文献１の場合、ツェナーダイオードの降伏電圧でスイッチング素子を逆回復時にオンさせ、順方向の電流を流すことによってサージ電圧をクランプする。これとは仕組みが異なり、本発明の場合、しきい値より低いゲート電圧をスイッチング素子に与えておくことで逆回復時に逆導通させ、還流電流を分流することによってサージ電圧を抑制する。ツェナーダイオードを使用する必要が無く、回路素子の追加が不要なので、電力変換装置の簡素化、小型化に貢献する。 In the case of Patent Document 1 described above, the breakdown voltage of the Zener diode turns on the switching element at the time of reverse recovery, and the surge voltage is clamped by passing a current in the forward direction. The mechanism is different from this, and in the case of the present invention, by applying a gate voltage lower than the threshold value to the switching element, the switching element is reverse-conducted at the time of reverse recovery, and the surge voltage is suppressed by dividing the reflux current. Since it is not necessary to use a Zener diode and no additional circuit element is required, it contributes to simplification and miniaturization of the power conversion device.
図４の駆動方法は、３レベルのマルチレベルインバータである中性点クランプ（ＮＰＣ：Neutral Point Clamped）方式の電力変換装置にも応用することができる。図６にその回路例を示す。直流電源Ｅの高電位側と低電位側との間に２つのコンデンサＣ１，Ｃ２を同極性で直列に接続してあり、該２つのコンデンサＣ１，Ｃ２どうしの相互接続点に中性点（中間電位Ｅ／２）が設けられている。 The drive method of FIG. 4 can also be applied to a neutral point clamp (NPC: Neutral Point Clamped) type power conversion device, which is a three-level multi-level inverter. FIG. 6 shows an example of the circuit. Two capacitors C1 and C2 are connected in series with the same polarity between the high potential side and the low potential side of the DC power supply E, and the neutral point (intermediate) is at the interconnection point between the two capacitors C1 and C2. The potential E / 2) is provided.
直流電源Ｅの高電位側と低電位側との間に、ＭＯＳＦＥＴとした２つのスイッチング素子Ｑ１，Ｑ２が同極性で直列に接続され、そして、このスイッチング素子Ｑ１，Ｑ２のそれぞれに対してＳＢＤとしたダイオードＤ１，Ｄ２を逆並列接続してある。高電位側のスイッチング素子Ｑ１及びダイオードＤ１により上アームが構成され、低電位側のスイッチング素子Ｑ２及びダイオードＤ２により下アームが構成される。また、上アームと下アームの接続点と中性点との間に、ＭＯＳＦＥＴとした２つのスイッチング素子Ｑ３，Ｑ４が逆極性で直列に接続され、そして、このスイッチング素子Ｑ３，Ｑ４のそれぞれに対してＳＢＤとしたダイオードＤ３，Ｄ４が逆並列に接続されている。これらスイッチング素子Ｑ３，Ｑ４及びダイオードＤ３，Ｄ４により双方向スイッチの中間アームが構成されている。この図６に示す主回路を３組接続してハーフブリッジ回路を構成すれば、三相交流用の電力変換装置とすることができる。 Two switching elements Q1 and Q2 as MOSFETs are connected in series with the same polarity between the high potential side and the low potential side of the DC power supply E, and SBD and SBD are attached to each of the switching elements Q1 and Q2. The diodes D1 and D2 are connected in antiparallel. The upper arm is formed by the switching element Q1 and the diode D1 on the high potential side, and the lower arm is formed by the switching element Q2 and the diode D2 on the low potential side. Further, two switching elements Q3 and Q4 as MOSFETs are connected in series with opposite polarities between the connection point and the neutral point of the upper arm and the lower arm, and for each of the switching elements Q3 and Q4. The diodes D3 and D4, which are SBDs, are connected in antiparallel. These switching elements Q3 and Q4 and diodes D3 and D4 form an intermediate arm of a bidirectional switch. If three sets of main circuits shown in FIG. 6 are connected to form a half-bridge circuit, a power conversion device for three-phase alternating current can be obtained.
図６の電力変換装置の場合、デッドタイムでは、中間アームのスイッチング素子Ｑ３，Ｑ４のいずれか一方がオン電圧で駆動されて還流電流が流れるが、このときスイッチング素子Ｑ３，Ｑ４の他方は、従来の制御では、オフ電圧で駆動される。これに本発明を適用し、当該スイッチング素子Ｑ３，Ｑ４の他方に対するデッドタイムの駆動電圧を、オフ電圧よりは高く且つ該スイッチング素子のしきい値電圧よりは低い電圧に維持する。そして、デッドタイム終了でターンオンさせる上アーム又は下アームのスイッチング素子Ｑ１，Ｑ２の駆動電圧をオン電圧へ上げた後に、オフ電圧まで落とす制御とする。図６中には、スイッチング素子Ｑ１，Ｑ２，Ｑ４がオフ、スイッチング素子Ｑ３がオンの場合のデッドタイムにおける還流電流を一点鎖線で示してあり（Ｑ３→Ｄ４）、これに加えて、ここに説明する駆動方法に従ってスイッチング素子Ｑ４を通しても点線矢示するように還流電流が流れる。したがって、この駆動方法によって当該回路でも、上述した通りサージ電圧が抑制される。 In the case of the power conversion device of FIG. 6, in the dead time, one of the switching elements Q3 and Q4 of the intermediate arm is driven by the on-voltage and a return current flows. At this time, the other of the switching elements Q3 and Q4 is conventionally used. In the control of, it is driven by the off voltage. The present invention is applied to this, and the drive voltage of the dead time for the other of the switching elements Q3 and Q4 is maintained at a voltage higher than the off voltage and lower than the threshold voltage of the switching element. Then, the drive voltage of the switching elements Q1 and Q2 of the upper arm or the lower arm to be turned on at the end of the dead time is raised to the on voltage and then lowered to the off voltage. In FIG. 6, the return current at the dead time when the switching elements Q1, Q2, and Q4 are off and the switching element Q3 is on is shown by a alternate long and short dash line (Q3 → D4). A return current flows through the switching element Q4 according to the driving method as shown by the dotted line. Therefore, this driving method also suppresses the surge voltage in the circuit as described above.
Ｑ１，Ｑ２，Ｑ３，Ｑ４ 逆導通可能なスイッチング素子
Ｄ１，Ｄ２，Ｄ３，Ｄ４ ダイオード
Ｅ 直流電源
Ｌ インダクタンス
Q1, Q2, Q3, Q4 Reverse conductive switching elements D1, D2, D3, D4 Diode E DC power supply L Inductance
Claims (6)
ターンオンさせる前記スイッチング素子の駆動電圧をデッドタイム期間中にオフ電圧に維持すると共に、ターンオフさせる前記スイッチング素子の駆動電圧を、デッドタイム期間中にオフ電圧より高く且つ当該スイッチング素子のしきい値電圧より低い電圧に維持することを特徴とする、駆動方法。 In the driving method of a power conversion device in which at least two reverse-conducting switching elements, each of which is connected in anti-parallel to each other, are connected in series between the high-potential side and the low-potential side of a DC power supply to form an upper and lower arm.
The drive voltage of the switching element to be turned on is maintained at the off voltage during the dead time period, and the drive voltage of the switching element to be turned off is higher than the off voltage and higher than the threshold voltage of the switching element during the dead time period. A driving method characterized by maintaining a low voltage.
ターンオフさせる前記スイッチング素子の駆動電圧を、デッドタイム期間中にオフ電圧より高く且つ当該スイッチング素子のしきい値電圧より低い電圧に維持し、
デッドタイム終了でターンオンさせる前記スイッチング素子の駆動電圧をオン電圧へ上げた後に、前記ターンオフさせるスイッチング素子の駆動電圧をオフ電圧にする、駆動方法。 In the driving method of a power conversion device in which at least two reverse-conducting switching elements, each of which is connected in anti-parallel to each other, are connected in series between the high-potential side and the low-potential side of a DC power supply to form an upper and lower arm.
The drive voltage of the switching element to be turned off is maintained at a voltage higher than the off voltage and lower than the threshold voltage of the switching element during the dead time period.
After raising the driving voltage of the switching element to turn on in the dead time ends to the on-voltage to turn off the voltage the drive voltage of the switching element to the off driving method.
前記上下アームのスイッチング素子を両方ともオフにし且つ前記中間アームのスイッチング素子のいずれか一方をオフにするデッドタイムの期間に、
前記上下アームのオフにするスイッチング素子の駆動電圧をオフ電圧にすると共に、
前記中間アームのオフにするスイッチング素子の駆動電圧を、オフ電圧より高く且つ当該スイッチング素子のしきい値電圧より低い電圧に維持することを特徴とする、駆動方法。 At least two switching elements, each of which is connected in anti-parallel to a diode, are connected in series between the high potential side and the low potential side of the DC power supply with the same polarity to form the upper and lower arms, and the neutral point of the intermediate potential and the above. In the driving method of a power conversion device in which an intermediate arm is formed by connecting at least two reverse-conducting switching elements in which diodes are connected in antiparallel to each of the connection points of the upper and lower arms in series with opposite polarities.
During the dead time period in which both the switching elements of the upper and lower arms are turned off and one of the switching elements of the intermediate arm is turned off.
While setting the drive voltage of the switching element for turning off the upper and lower arms to the off voltage,
A driving method, characterized in that the driving voltage of a switching element for turning off the intermediate arm is maintained at a voltage higher than the off voltage and lower than the threshold voltage of the switching element.
前記上下アームのスイッチング素子を両方ともオフにし且つ前記中間アームのスイッチング素子のいずれか一方をオフにするデッドタイムの期間に、前記中間アームのオフにするスイッチング素子の駆動電圧を、オフ電圧より高く且つ当該スイッチング素子のしきい値電圧より低い電圧に維持し、
前記上下アームのスイッチング素子のうちのデッドタイム終了でターンオンさせるスイッチング素子の駆動電圧をオン電圧へ上げた後に、前記中間アームのオフさせるスイッチング素子の駆動電圧をオフ電圧にする、駆動方法。 At least two switching elements, each of which is connected in anti-parallel to a diode, are connected in series between the high potential side and the low potential side of the DC power supply with the same polarity to form the upper and lower arms, and the neutral point of the intermediate potential and the above. In the driving method of a power conversion device in which an intermediate arm is formed by connecting at least two reverse-conducting switching elements in which diodes are connected in antiparallel to each of the connection points of the upper and lower arms in series with opposite polarities.
During the dead time period in which both the switching elements of the upper and lower arms are turned off and one of the switching elements of the intermediate arm is turned off, the drive voltage of the switching element to be turned off of the intermediate arm is set higher than the off voltage. And keep the voltage lower than the threshold voltage of the switching element.
After raising the driving voltage of the switching element to be turned on at the dead time ends of the switching elements of the upper and lower arms to the on-voltage to turn off the voltage the drive voltage of the switching elements to be off of the intermediate arm, the driving method.
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