JP6927692B2 - Multi-layer wiring structure, manufacturing method of multi-layer wiring structure, semiconductor device and fan-out type wafer level package - Google Patents

Description

The present invention relates to a multi-layer wiring structure, a method for manufacturing a multi-layer wiring structure, a semiconductor device, and a fan-out type wafer level package.

In recent years, there has been a demand for higher functionality and lighter, thinner, shorter and smaller portable small electronic devices such as mobile phones. Therefore, in order to meet these demands, high-density integration of electronic components and further high-density mounting are progressing. The semiconductor packages used in these electronic devices are becoming smaller than ever before, and in recent years, in order to meet such demands, semiconductor chips are chip size packages (CSPs) that are close to the chip size. ) May be implemented.

In the chip size package, the rewiring layer for pulling out the terminal electrode of the semiconductor chip to the connection position with the external circuit and the electrode for external connection connecting with the external circuit at the pulled out position are in the area of almost the same size as the semiconductor chip. It is formed in and sealed with an insulating resin or the like. Therefore, it is possible to mount the product on a mounting board at a high density.

As one of the methods for embodying CSP, a packaging method called a wafer level package (hereinafter, also referred to as "WLP") is known. WLP is a method of forming an external terminal electrode or the like on a silicon wafer before it is individualized by dicing, and individualization by dicing is performed after WLP. By using WLP, external terminal electrodes and the like can be formed on a large number of semiconductor chips at the same time, so that productivity can be improved.

The WLP includes a fan-in type WLP and a fan-out type WLP.
The fan-in type WLP is provided with an external electrode (external terminal) as a semiconductor device in a region equivalent to the chip size. For example, an external terminal is formed in the surface region of the chip through rewiring or the like formed on the passivation film on the chip (see Patent Document 1).

On the other hand, the fan-out type WLP is provided with an external terminal as a semiconductor device in a region larger than the chip size. For example, an external terminal is formed in the surface region of the insulating resin in which the chip is embedded through rewiring or the like formed on the passivation film on the chip. In the fan-out type WLP, for example, rewiring and external electrodes are formed on an insulating resin wafer formed of an insulating resin in which a plurality of chips are embedded (see Patent Document 2).

As shown in FIG. 4, Patent Document 3 includes a semiconductor device including a first insulating layer 214 including a semiconductor device 202 and a first wiring 230, and a second insulating layer 250 including a second wiring 240. It is shown.
In this semiconductor device, a conductive connection between two layers of the first wiring 230 and the second wiring 240 is provided in the first insulating layer on the via 224 and the via 224 filled with the conductive material. It is described that it is performed by the conductive connecting member 225 provided continuously.

FIG. 5 shows a multi-layer wiring structure having a five-layer structure in which three layers are built up on a layer in which the semiconductor device 1 is built by a conventional method, and FIG. 6 shows the manufacturing process thereof. be. This structure is a step of fixing the semiconductor device 1 on the first insulating layer 21 that seals the first wiring 11 with an adhesive (see FIGS. 6A and 6B), and is used for vias on the second insulating layer 22. It is manufactured by a step of forming the openings 32a and 42a of the above (see FIG. 6C) and a step of forming the via 32, the via 42 and the wiring 12 by electroplating (see FIG. 6D).

As shown in FIG. 6, a via 32 is formed to connect the wiring of the first wiring 11 and the wiring of the second wiring 12 formed under the second insulating layer 22 in which the semiconductor device 1 is incorporated. There is a need to. However, if the thickness of the second insulating layer 22 becomes thicker due to the height of the semiconductor device 1, the hole diameter of the via 32 becomes larger.

For example, when the height of the semiconductor device 1 is 50 μm, the total thickness of the thickness of the first insulating layer 21 and the thickness of the second insulating layer 22 is about 100 μm. Considering that the via diameter / depth aspect ratio needs to be 0.8 or more from the connection yield, the via diameter of the via 32 is 100 μm / 0.8 ≈ 125 μm, and the via diameter is increased to about 125 μm. Must. In general, if the via diameter is 100 μm or more, filling by copper plating cannot be performed, and a staggered structure that offsets the via directly above the build-up portion must be used. The via diameter of 125 μm or more and the staggered structure reduce the degree of freedom in wiring design, which is a major problem in terms of package miniaturization and high density.

Japanese Unexamined Patent Publication No. 2007-157879 Japanese Unexamined Patent Publication No. 2005-167191 U.S. Pat. No. 9,406658

According to the present invention, even when the layer thickness of the layer in which the semiconductor device is built is thick, the connection structure between the wirings is a stack structure and the via diameter is suppressed, so that the package can be miniaturized without reducing the degree of freedom in wiring design. It is an object of the present invention to provide a multi-layer wiring structure that enables high density.

In order to solve the above-mentioned problems, the present inventors have conducted diligent studies and found that the above-mentioned problems can be solved by adopting the following multi-layer wiring structure.
That is, the present invention is as follows.
(1) A first insulating layer including the first wiring and
A second insulating layer including a semiconductor device laminated on the first insulating layer,
A multi-layer wiring structure including a second wiring formed on the second insulating layer.
The first insulating layer has a first via that extends from the first wiring to the surface of the first insulating layer.
The second insulating layer has a via land that reaches from the bottom surface of the second insulating layer to the inside of the second insulating layer, and a second via that reaches from the upper surface of the via land to the upper surface of the second insulating layer. death,
The via land is conductively connected to the first wiring by the first via.
The second via has a multi-layer wiring structure that is conductively connected to the second wiring.
(2) The multilayer wiring structure according to (1) above, wherein the thickness of the vialand is equal to or less than the height of the upper surface of the semiconductor device arranged in the second insulating layer.
(3) A semiconductor device having the multilayer wiring structure according to (1) or (2) above.
(4) A fan-out type wafer level package having the multi-layer wiring structure according to (1) or (2) above.
(5) A step of forming a first via opening from the first wiring to the surface of the first insulating layer in the first insulating layer in which the first wiring is sealed with an insulating material.
A step of filling the first via opening with a conductive material by electroplating to form a first via and forming a via land on the first via.
A step of mounting a semiconductor device on the first insulating layer using an adhesive.
A step of sealing the semiconductor device and the vialand with an insulating material to form a second insulating layer.
A step of forming a second via opening reaching the via land from the surface of the second insulating layer,
A step of forming a second via by electroplating in the opening for the second via and forming a second wiring conductively connected to the second via.
A method of manufacturing a multi-layer wiring structure, including.

According to the present invention, it is possible to provide a multi-layer wiring structure capable of downsizing and increasing the density of a semiconductor device.

FIG. 1 is a diagram showing a multilayer wiring structure according to an embodiment of the present invention. FIG. 2-1 is a diagram showing a part of a manufacturing process of a multilayer wiring structure according to an embodiment of the present invention. 2A to 2D are diagrams showing a process of forming vias and vialands on the first insulating layer and mounting the semiconductor device 1. FIG. 2-2 is a diagram showing a part of a manufacturing process of the multilayer wiring structure according to the embodiment of the present invention. 2E to 2G are diagrams showing the steps from forming the second insulating layer on the first insulating layer to forming the second wiring. FIG. 3 is a diagram comparing the multilayer wiring structure of the present invention with the conventional multilayer wiring structure. 3A is a diagram showing a multilayer wiring structure of the present invention, and 3B is a diagram showing a conventional multilayer wiring structure. FIG. 4 is a diagram showing a multilayer wiring structure described in Patent Document 3. FIG. 5 is a diagram showing a conventional multilayer wiring structure. FIG. 6 is a diagram showing a manufacturing process of the conventional multilayer wiring structure shown in FIG.

Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. It should be noted that it is easy for a person skilled in the art to modify or modify the present invention to form another embodiment, and these modifications or modifications are included in the present invention. This is an example of the form of the above, and does not limit the present invention.

(First Embodiment)
A configuration example of the multilayer wiring structure of the present invention will be described with reference to FIG.
In FIG. 1, a first insulating layer 21 is provided below a second insulating layer 22 in which a semiconductor device 1 is incorporated, and a third insulating layer 23 and a fourth insulating layer are provided above the second insulating layer 22. It shows a multi-layer wiring structure having a build-up structure of five layers provided with 24 and a fifth insulating layer 25.

In the first insulating layer 21, the first wiring 11 is sealed with an insulating material, and the first via 31 is provided.
Further, an external terminal 3 is formed on the first wiring 11, and a solder resist layer 4 is formed on the surface other than the portion of the external terminal 3.
The semiconductor device 1 is sealed in the second insulating layer 22 by an insulating material, and the via land 10 and the via 32 and the via 42 are provided on the semiconductor device 1.
In the third insulating layer 23, the second wiring 12 is sealed with an insulating material, and the third via 33 and the via 43 are formed.
In the fourth insulating layer 24, the third wiring 13 is sealed with an insulating material, and the fourth via 34 and the via 44 are formed.
A fourth wiring 14 is sealed in the fifth insulating layer 25 by an insulating material, and a fifth via 35 and a via 45 are formed.
A fifth wiring 15 is formed on the surface of the fifth insulating layer 25, an external terminal 3 is formed, and a solder resist layer 4 is formed on the surface other than the portion of the external terminal 3.

If the connecting via diameter is larger than 100 μm, the via cannot be filled by copper plating, but by reducing the via diameter, it becomes possible to fill by copper plating.
As described above, the via land 10 and the second via 32 have two conductive paths that conductively connect the first wiring 11 and the second wiring 12 through the second insulating layer 22 including the semiconductor device 1. The depth d2 of the second via 32 can be reduced by increasing the thickness d1 of the beer land 10 by forming the steps. Then, by reducing the depth d2 of the second via 32, the via diameter of the second via 32 can be reduced, so that the second via 32 can be filled with copper plating.
That is, even when the layer thickness d of the second insulating layer 22 becomes thicker due to the thickness d3 of the built-in semiconductor device 1, the via diameter value of the second via 32 can be kept small, and via filling becomes possible. As a result, it becomes a full-layer stack via structure, and the degree of design freedom can be dramatically improved.

(Second Embodiment)
The method of forming the multilayer wiring structure shown in FIG. 1 will be described with reference to FIGS. 2-1 and 2-2.
In the following, only the method of forming the first insulating layer and the second insulating layer is shown.

<Step of preparing the first insulating layer (see FIG. 2A)>
A first insulating layer 21 in which the first wiring 11 is sealed with an insulating material is prepared.

<Step of forming an opening (see FIG. 2B)>.
A via opening 31a for forming the first via 31 is formed in the first insulating layer 21.
The method for forming the via opening 31a is not limited, but a general laser drilling method can be adopted. Lasers that can be used to form via holes include _{gas lasers such as CO 2} , CO, and excimer, and solid-state lasers such as YAG (yttrium aluminum garnet).

<Step of forming beer land (see Fig. 2C)>
A conductive material is filled in the opening 31a and the peripheral portion of the opening 31a by a general electroplating wiring forming process to form a first via (filled via) 31 and a via land 10.
By increasing the plating thickness here, the vialand 10 becomes thicker, and the thickness of the insulating layer on the vialand 10 can be relatively reduced.
However, as shown in FIG. 2E, when the thickness d1 of the vialand 10 is higher than the height d3 of the semiconductor device 1, the minimum layer thickness of d2 is defined, so that the layer thickness d4 of the insulating layer on the semiconductor device 1 is defined. Becomes thicker, and the value of the via diameter of the via 42 becomes large. Therefore, it is desirable that the thickness d1 of the vialand 10 is equal to or less than the height d3 of the semiconductor device 1.

<Process for mounting semiconductor devices (see Fig. 2D)>
The semiconductor device 1 is mounted on the first insulating layer 21 by using the adhesive 2.

<Process of sealing semiconductor devices and vialands (see Fig. 2E)>
The semiconductor device 1 and the vialand 10 are sealed with an insulating material to form the second insulating layer 22.
Since the wiring is formed on the second insulating layer 22 in the subsequent step, a resin composition sheet with a single-sided metal foil is used as the insulating material for sealing, and the resin composition sheet is laminated. , A copper foil may be provided on the surface of the insulating material.

<Step of forming an opening (see Fig. 2F)>
For vias 32a for vias reaching the upper surface of the vialand 10 from the surface of the second insulating layer 22, and for vias reaching the connection terminals of the semiconductor device 1 from the surface of the second insulating layer 22. Forming a via opening 42a

<Process of forming vias and wiring (see Fig. 2G)>
The second vias 32 and 42 are formed by electroplating the via openings 32a and 42a.
Smear is removed from the second via 32 and via 42 by plasma or the like, and the second wiring 12 is formed through a wiring forming process by general electroplating, and the second wiring 12 and the second via 32 are formed. And are conductively connected.

<Process of forming build-up layer>
After that, a semiconductor package having the multi-layer wiring structure of the present invention as shown in FIG. Obtainable.

According to the present invention, the diameter of vias connected to the upper and lower layers of the semiconductor device built-in portion can be reduced. In addition, it is possible to stack vias directly above when building up, further reducing the design area.
FIG. 3A shows a land plan view and a land area of an example of the via structure of the present invention, and FIG. 3B shows a land plan view and a land area of an example of the conventional via structure.
As shown in FIG. 3A, in the via structure of the present invention, a via land 5 is formed around the via 32.
Further, as shown in FIG. 3B, in the conventional via structure, the via land 5a and the via land 5b are formed around the via 52a and the via 52b.
A comparison of the via diameter, the via land diameter, and the design area of the via land between the one shown in FIG. 3A and the one shown in FIG. 3B is as shown in the table below.
As shown in the table below, the one shown in FIG. 3A has a design area of about 35% per land as compared with the one shown in FIG. 3B, and it can be seen that the package becomes smaller and has a higher density. ..

1 Semiconductor device 2 Adhesive material 3 External terminal 4 Solder resist layer 10 Vialand 11 First wiring 12 Second wiring 13 Third wiring 14 Fourth wiring 15 Fifth wiring 21 First insulating layer 22 Second Insulation layer 23 Third insulation layer 24 Fourth insulation layer 25 Fifth insulation layer 31 First via 32 via, second via 32a Opening for via 33 Third via 34 Fourth via 35 Fifth Via 42a Openings for vias 42, 43, 44, 45 Via d Layer thickness of the second insulating layer d1 Thickness of vialand d2 Depth of the second via d3 Thickness of the semiconductor device d4 Thickness of the insulating layer on the semiconductor device

Claims (9)

With the first insulating layer including the first wiring,
Laminated on the first insulating layer, a second insulating layer containing the device,
A third insulating layer including a second wiring formed on the second insulating layer,
A via structure connecting the first wiring and the second wiring,
It is a multi-layer wiring structure including
The via structure is
A first via extending from front Symbol first wiring to the surface of the first insulating layer,
A vialand extending from the bottom surface of the second insulating layer to the inside of the second insulating layer,
It has a second via that reaches the upper surface of the second insulating layer from the upper surface of the via land.
The via land is conductively connected to the first wiring by the first via.
The second via is conductively connected to the second wiring .
The first via and the first wiring are provided in the same insulating layer, and the first via is provided in the same insulating layer.
The second via is provided in an insulating layer different from the insulating layer including the second wiring.
A multi-layer wiring structure in which the first via is provided between the via land and the first wiring. The thickness of the via land is, the multilayer wiring structure according to claim 1 or less the height of the upper surface of the deployed device in the second insulating layer. The semiconductor device having the multilayer wiring structure according to claim 1 or 2. A fan-out type wafer level package having the multilayer wiring structure according to claim 1 or 2. A step of forming a first via opening from the first wiring to the surface of the first insulating layer in the first insulating layer in which the first wiring is sealed with an insulating material.
A step of filling the first via opening with a conductive material by electroplating to form a first via and forming a via land on the first via.
Step of mounting the device using an adhesive on the first insulating layer,
Forming a second insulating layer prior Kide vice and the via land sealed by an insulating material,
A step of forming a second via opening reaching the via land from the surface of the second insulating layer,
A step of forming a second via by electroplating in the opening for the second via and forming a second wiring conductively connected to the second via.
Only including,
The first via and the first wiring are formed in the same insulating layer, and the first via is formed in the same insulating layer.
The second via is formed in an insulating layer different from the insulating layer including the second wiring.
A method for manufacturing a multi-layer wiring structure in which the first via is formed between the via land and the first wiring. The multilayer wiring structure according to claim 1, wherein the device is a semiconductor device. The multilayer wiring structure according to claim 1, wherein the via land is in contact with the surface of the first insulating layer, and the thickness of the via land is at least 50% of the thickness of the device. The method for manufacturing a multilayer wiring structure according to claim 5, wherein the device is a semiconductor device. The method for manufacturing a multilayer wiring structure according to claim 5, wherein the via land is in contact with the surface of the first insulating layer and is formed so that the thickness of the via land has at least 50% of the thickness of the device.

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