JP6916751B2 - ハイブリッドメモリーモジュール及びその動作方法 - Google Patents

ハイブリッドメモリーモジュール及びその動作方法 Download PDF

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JP6916751B2
JP6916751B2 JP2018023874A JP2018023874A JP6916751B2 JP 6916751 B2 JP6916751 B2 JP 6916751B2 JP 2018023874 A JP2018023874 A JP 2018023874A JP 2018023874 A JP2018023874 A JP 2018023874A JP 6916751 B2 JP6916751 B2 JP 6916751B2
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dram
data
controller
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JP2018133086A (ja
JP2018133086A5 (enExample
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牧 天 張,
牧 天 張,
迪 民 牛,
迪 民 牛,
宏 忠 ズン,
宏 忠 ズン,
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Samsung Electronics Co Ltd
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    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
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    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/06Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646Configuration or reconfiguration
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
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    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
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    • G06F12/0893Caches characterised by their organisation or structure
    • G06F12/0895Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
    • GPHYSICS
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    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0668Interfaces specially adapted for storage systems adopting a particular infrastructure
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    • G06F3/0673Single storage device
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    • G06F2212/1016Performance improvement
    • G06F2212/1024Latency reduction
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    • G06F2212/10Providing a specific technical effect
    • G06F2212/1048Scalability
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    • G06FELECTRIC DIGITAL DATA PROCESSING
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    • G06F2212/202Non-volatile memory
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    • G06FELECTRIC DIGITAL DATA PROCESSING
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    • G06F2212/22Employing cache memory using specific memory technology
    • G06F2212/221Static RAM
    • GPHYSICS
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    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/28Using a specific disk cache architecture
    • GPHYSICS
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    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/28Using a specific disk cache architecture
    • G06F2212/283Plural cache memories
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/46Caching storage objects of specific type in disk cache
    • G06F2212/466Metadata, control data
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/50Control mechanisms for virtual memory, cache or TLB
    • G06F2212/507Control mechanisms for virtual memory, cache or TLB using speculative control
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/62Details of cache specific to multiprocessor cache arrangements
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2018023874A 2017-02-15 2018-02-14 ハイブリッドメモリーモジュール及びその動作方法 Active JP6916751B2 (ja)

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US201762459414P 2017-02-15 2017-02-15
US62/459414 2017-02-15
US15/587286 2017-05-04
US15/587,286 US10282294B2 (en) 2017-02-15 2017-05-04 Mitigating DRAM cache metadata access overhead with SRAM metadata cache and bloom filter

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US20180232310A1 (en) 2018-08-16
TW201832086A (zh) 2018-09-01
TWI744457B (zh) 2021-11-01
CN108427647A (zh) 2018-08-21
KR102231792B1 (ko) 2021-03-25
CN108427647B (zh) 2023-08-08
US10282294B2 (en) 2019-05-07
KR20180094469A (ko) 2018-08-23
JP2018133086A (ja) 2018-08-23

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