JP6916430B2 - Integrated circuit with chemically modified spacer surface - Google Patents

Integrated circuit with chemically modified spacer surface Download PDF

Info

Publication number
JP6916430B2
JP6916430B2 JP2019079500A JP2019079500A JP6916430B2 JP 6916430 B2 JP6916430 B2 JP 6916430B2 JP 2019079500 A JP2019079500 A JP 2019079500A JP 2019079500 A JP2019079500 A JP 2019079500A JP 6916430 B2 JP6916430 B2 JP 6916430B2
Authority
JP
Japan
Prior art keywords
dielectric material
side wall
gate stack
spacer
dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2019079500A
Other languages
Japanese (ja)
Other versions
JP2019145825A (en
Inventor
ケイ カークパトリック ブライアン
ケイ カークパトリック ブライアン
ジェイン アミターブ
ジェイン アミターブ
Original Assignee
テキサス インスツルメンツ インコーポレイテッド
テキサス インスツルメンツ インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/427,062 external-priority patent/US9496359B2/en
Application filed by テキサス インスツルメンツ インコーポレイテッド, テキサス インスツルメンツ インコーポレイテッド filed Critical テキサス インスツルメンツ インコーポレイテッド
Publication of JP2019145825A publication Critical patent/JP2019145825A/en
Application granted granted Critical
Publication of JP6916430B2 publication Critical patent/JP6916430B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)

Description

開示される実施例は、多層側壁スペーサを有するＭＯＳトランジスタを含む、金属酸化物半導体（ＭＯＳ）トランジスタを含む、半導体処理及び集積回路（ＩＣ）デバイスに関する。 The disclosed examples relate to semiconductor processing and integrated circuit (IC) devices, including metal oxide semiconductor (MOS) transistors, including MOS transistors with multilayer sidewall spacers.

半導体ウエハを処理する一方で、後に堆積される又は形成されるフィルムが取り除かれるときエッチストップ層として機能し得るフィルムを堆積又は形成することがしばしば有利である。しかし、そのフィルムが後の処理の間充分なエッチング耐性を有さない場合、このようなフィルムは意図せず取り除かれ得る。 While processing a semiconductor wafer, it is often advantageous to deposit or form a film that can function as an etch stop layer when the film that is later deposited or formed is removed. However, if the film does not have sufficient etching resistance during the subsequent treatment, such a film can be unintentionally removed.

意図しない除去の一例は、ＭＯＳトランジスタのための薄いシリコンナイトライド側壁（又はオフセット）スペーサに関与する。薄いシリコンナイトライド側壁スペーサは、一般に、半導体表面への軽くドープされたドレイン（ＬＤＤ）注入とゲートスタックとの間の空間を提供するためのインプラントマスクとして用いられる。典型的なプロセスフローは、まずオフセットスペーサとして機能し、その後、ＳｉＧｅを含むディスポーザブルな第２の側壁スペーサなどの、付加的なフィルムが頂部上に堆積される間、下部層／エッチストップとして用いられる第１のスペーサ層を有し、これは後に取り除かれる。一つのプロセスフローにおいて、第２の側壁スペーサを取り除くために熱リン酸（ＨＰＡ）が用いられる。しかし、ビスーターシャリーブチルアミノシラン（ｂｉｓ−ｔｅｒｔｉａｒｙｂｕｔｙｌａｍｉｎｏ−ｓｉｌａｎｅ：ＢＴＢＡＳ）及びアンモニア試薬から形成されるシリコンナイトライドスペーサでさえ（なお、ＢＴＢＡＳベースのシリコンナイトライドはＨＰＡに最もウェットエッチング耐性があるシリコンナイトライドフィルムであると知られている）、ディスポーザブルなＳｉＧｅ第２の側壁スペーサが取り除かれるとき、必ずしもＨＰＡエッチングを止めることは可能であるとは限らない。特に、シリコンナイトライド側壁スペーサが、Ｈ２又はＮ２を含有するプラズマなど、還元剤に曝される場合、エッチストップ特性は失われ得、シリコンナイトライドオフセット側壁スペーサの意図しない除去、及びその結果、ゲート、ソース、及びドレイン上にその後堆積されるシリサイドに起因するなど、ゲート及びソース及び／又はドレイン間の後続の短絡となり得る。また、半導体デバイスのサイズが縮小されるにつれて、ゲートスタックの頂部とソース／ドレイン領域の頂部表面との間の距離が低減され、ゲートスタックの側壁上に形成するシリサイドに起因する電気的短絡の可能性が増大する。 An example of unintended removal involves a thin silicon nitride side wall (or offset) spacer for a MOS transistor. Thin silicon nitride side wall spacers are commonly used as implant masks to provide space between lightly doped drain (LDD) injections onto the semiconductor surface and the gate stack. A typical process flow first acts as an offset spacer and then is used as a bottom layer / etch stop while an additional film, such as a disposable second side wall spacer containing SiGe, is deposited on the top. It has a first spacer layer, which is later removed. In one process flow, thermal phosphoric acid (HPA) is used to remove the second side wall spacer. However, even silicon nitride spacers formed from bis-tertiary butylaminosilane (BTBAS) and ammonia reagents (BTBAS-based silicon nitrides are the most wet-etch resistant silicon nitrides for HPA. It is not always possible to stop HPA etching when the disposable SiGe second sidewall spacers (known to be films) are removed. Especially when the silicon nitride side wall spacer is exposed to a reducing agent such as plasma containing H2 or N2, the etch stop property can be lost and the silicon nitride offset side wall spacer is unintentionally removed and, as a result, the gate. Subsequent short circuits between the gate and the source and / or drain, such as due to VDD subsequently deposited on the source and drain. Also, as the size of the semiconductor device is reduced, the distance between the top of the gate stack and the top surface of the source / drain region is reduced, allowing for electrical short circuits due to silicides formed on the sidewalls of the gate stack. Increases sex.

開示される実施例は、多層側壁スペーサを用いる金属酸化物半導体（ＭＯＳ）トランジスタのための薄い側壁スペーサの上述の意図しない除去に対する解決策を記載する。第２の誘電性材料を形成するため少なくとも１つの要素を付加することにより第１の材料を含む第１の側壁スペーサの頂部表面を化学的に変換することにより、第２の材料は、第１のスペーサ材料に較べてエッチング耐性を実質的に増大させ得る。その結果、第１のスペーサ上のディスポーザブルな第２のスペーサの後続の除去は、第２の誘電性材料がエッチストップとして機能し得るため第１のスペーサを取り除かないか、又は第１のスペーサの第１の誘電体材料のための少なくとも何らかのエッチング保護を提供し得る。 The disclosed examples describe solutions to the above-mentioned unintended removal of thin side wall spacers for metal oxide semiconductor (MOS) transistors using multilayer side wall spacers. By chemically transforming the top surface of the first side wall spacer containing the first material by adding at least one element to form the second dielectric material, the second material is made of first material. Etching resistance can be substantially increased as compared with the spacer material of. As a result, subsequent removal of the disposable second spacer on the first spacer does not remove the first spacer because the second dielectric material can act as an etch stop, or the first spacer It may provide at least some etching protection for the first dielectric material.

１つの開示される実施例が、ゲート誘電体上のゲート電極を含むゲートスタックを、その上に有する基板の半導体表面上に第１の誘電体材料を堆積することを含む、集積回路を製造する方法を含む。第１の誘電体材料は、ＲＩＥを用いるなど、ゲートスタックの側壁上に側壁スペーサを形成するためエッチングされる。第１の誘電体材料の頂部表面が、表面変換された側壁スペーサを提供するため少なくとも１つの要素を付加することにより第２の誘電体材料に化学的に変換される。第２の誘電体材料は、遷移領域にわたって）第１の誘電性材料に化学的に結合される。 One disclosed embodiment manufactures an integrated circuit comprising depositing a first dielectric material on a semiconductor surface of a substrate having a gate stack comprising a gate electrode on the gate dielectric. Including methods. The first dielectric material is etched to form side wall spacers on the side walls of the gate stack, such as by using RIE. The top surface of the first dielectric material is chemically transformed into the second dielectric material by adding at least one element to provide a surface-transformed side wall spacer. The second dielectric material is chemically bonded to the first dielectric material (over the transition region).

表面変換された側壁スペーサを形成することに続いて、ゲートスタックの横の半導体表面に軽くドープされたドレイン（ＬＤＤ）を形成するためイオン注入が続き得る。その後、表面変換された側壁スペーサ上に第２のスペーサが形成される。その後、ゲートスタックの横にソース及びドレインが形成される。第２のスペーサを形成した後ゲートスタックの横の半導体表面にソース及びドレインを形成するためにイオン注入を用いることができる。代替として、ＳｉＧｅ Ｓ／Ｄプロセス（例えば、典型的にＰＭＯＳ領域に窪みが形成され、ＳｉＧｅで置換される）のために第２の側壁スペーサを用いることができる。第２のスペーサはその後、ソース／ドレイン形成後に選択的に取り除かれ得る。化学的に変換された層の表面は、第１の誘電体材料が表面変換された層により保護されるように、選択的エッチング後も元のままである。 Following the formation of the surface-transformed side wall spacers, ion implantation may follow to form a lightly doped drain (LDD) on the semiconductor surface beside the gate stack. After that, a second spacer is formed on the surface-transformed side wall spacer. The source and drain are then formed beside the gate stack. Ion implantation can be used to form the source and drain on the semiconductor surface beside the gate stack after forming the second spacer. Alternatively, a second side wall spacer can be used for the SiGe S / D process (eg, recesses typically formed in the MIMO region and replaced by SiGe). The second spacer can then be selectively removed after source / drain formation. The surface of the chemically transformed layer remains intact after selective etching so that the first dielectric material is protected by the surface transformed layer.

図１は、例示の一実施例に従って、表面変換された側壁スペーサを含むＭＯＳトランジスタを有する集積回路（ＩＣ）デバイスを製造するための例示の方法における工程を示すフローチャートである。FIG. 1 is a flow chart illustrating steps in an exemplary method for manufacturing an integrated circuit (IC) device having a MOS transistor including a surface-transformed side wall spacer according to an exemplary embodiment.

図２Ａは、例示の一実施例に従って、表面変換された側壁スペーサを含むＭＯＳトランジスタを有するＩＣデバイスを製造する例示の方法のための処理進行を図示する断面図である。FIG. 2A is a cross-sectional view illustrating processing progress for an exemplary method of manufacturing an IC device having a MOS transistor including a surface-transformed side wall spacer according to an exemplary embodiment. 図２Ｂは、例示の一実施例に従って、表面変換された側壁スペーサを含むＭＯＳトランジスタを有するＩＣデバイスを製造する例示の方法のための処理進行を図示する断面図である。FIG. 2B is a cross-sectional view illustrating processing progress for an exemplary method of manufacturing an IC device having a MOS transistor including a surface-transformed side wall spacer according to an exemplary embodiment.

図２Ｃは、例示の一実施例に従って、表面変換された側壁スペーサを含むＭＯＳトランジスタを有するＩＣデバイスを製造する例示の方法のための処理進行を図示する断面図である。FIG. 2C is a cross-sectional view illustrating processing progress for an exemplary method of manufacturing an IC device having a MOS transistor including a surface-transformed side wall spacer according to an exemplary embodiment. 図２Ｄは、例示の一実施例に従って、表面変換された側壁スペーサを含むＭＯＳトランジスタを有するＩＣデバイスを製造する例示の方法のための処理進行を図示する断面図である。FIG. 2D is a cross-sectional view illustrating processing progress for an exemplary method of manufacturing an IC device having a MOS transistor comprising a surface-transformed side wall spacer according to an exemplary embodiment.

図２Ｅは、例示の一実施例に従って、表面変換された側壁スペーサを含むＭＯＳトランジスタを有するＩＣデバイスを製造する例示の方法のための処理進行を図示する断面図である。FIG. 2E is a cross-sectional view illustrating processing progress for an exemplary method of manufacturing an IC device having a MOS transistor including a surface-transformed side wall spacer according to an exemplary embodiment. 図２Ｆは、例示の一実施例に従って、表面変換された側壁スペーサを含むＭＯＳトランジスタを有するＩＣデバイスを製造する例示の方法のための処理進行を図示する断面図である。FIG. 2F is a cross-sectional view illustrating processing progress for an exemplary method of manufacturing an IC device having a MOS transistor including a surface-transformed side wall spacer according to an exemplary embodiment. 図２Ｇは、窒化物オフセットスペーサの意図しない除去の結果を示す既知のスペーサプロセス後の結果のスペーサ構造を示す。FIG. 2G shows the resulting spacer structure after a known spacer process showing the results of unintended removal of nitride offset spacers.

図３は、例示の一実施例に従った、第１の誘電性材料上の第２の誘電体材料を含む側壁スペーサを有するＭＯＳトランジスタを含むＩＣデバイスの一部の断面図であり、第２の誘電体材料は遷移領域にわたって第１の誘電性材料に化学的に結合されている。FIG. 3 is a cross-sectional view of a portion of an IC device comprising a MOS transistor having a side wall spacer containing a second dielectric material on a first dielectric material, according to an exemplary embodiment. Dielectric material is chemically bonded to the first dielectric material over the transition region.

図４は、例示の一実施例に従って、表面変換された側壁スペーサの厚みにわたって提供される化学的結合の高度に簡略化した描写を含み、例示の表面変換された側壁スペーサのための厚みの関数として組成を示す。FIG. 4 includes a highly simplified depiction of the chemical bonds provided over the thickness of the surface-transformed side wall spacers according to one example example, and is a function of thickness for the illustrated surface-transformed side wall spacers. The composition is shown as.

図１は、例示の一実施例に従って、表面変換された側壁スペーサを含むＭＯＳトランジスタを有するＩＣデバイスを製造するための例示の方法１００における工程を示すフローチャートである。ステップ１０１が、ゲート誘電体上のゲート電極を含むゲートスタックを、その上に有する基板の半導体表面上に第１の誘電体材料を堆積することを含む。ステップ１０２が、ＲＩＥを用いるなど、ゲートスタックの側壁上に側壁スペーサを形成するため第１の誘電体材料をエッチングすることを含む。 FIG. 1 is a flowchart showing a process in an exemplary method 100 for manufacturing an IC device having a MOS transistor including a surface-transformed side wall spacer according to an exemplary embodiment. Step 101 comprises depositing a first dielectric material on the semiconductor surface of a substrate having a gate stack comprising a gate electrode on the gate dielectric. Step 102 includes etching a first dielectric material to form a sidewall spacer on the sidewall of the gate stack, such as by using RIE.

ステップ１０３が、表面変換された側壁スペーサを提供するため少なくとも１つの要素を付加することにより第１の誘電体材料の頂部表面を第２の誘電体材料に化学的に変換させることを含む。第２の誘電体材料は、遷移領域にわたって第１の誘電性材料に化学的に結合される。側壁スペーサの化学的に変換された頂部表面は、第２の誘電性材料を形成するため少なくとも１つの要素を付加することによりエッチストップとなり、これは、熱リン酸（ＨＰＡ）エッチングなどに対し、変換されていない第１の誘電性材料と較べて、フィルムのウェットエッチング耐性を実質的に増大させる。一実施例において付加される要素は炭素である。別の実施例において、炭素及び酸素両方が付加される。 Step 103 involves chemically transforming the top surface of the first dielectric material into a second dielectric material by adding at least one element to provide a surface-transformed side wall spacer. The second dielectric material is chemically bonded to the first dielectric material over the transition region. The chemically converted top surface of the sidewall spacers becomes an etch stop by adding at least one element to form a second dielectric material, which, as opposed to thermal phosphoric acid (HPA) etching, etc. It substantially increases the wet etching resistance of the film as compared to the unconverted first dielectric material. The element added in one embodiment is carbon. In another embodiment, both carbon and oxygen are added.

一つの特定の例において、第１の誘電性材料は、ＢＴＢＡＳ派生のシリコンナイトライドを含み、シリコンカーバイド（ＳｉＣ）、シリコンカーボナイトライド（ＳｉＣＮ）、及び／又はシリコンオキシカーボナイトライド（ＳｉＯＣＮ）フィルムを含む第２の誘電性材料の、典型的に１０〜２０オングストロームの厚みの、薄い層を形成するシリコンナイトライドの頂部表面に炭素が付加される。これは、予めゲートスタック側壁として用いられたＢＴＢＡＳシリコンナイトライドフィルムを、後続のディスポーザブルなスペーサフィルムを堆積する前に、概して３００℃〜８００℃の温度、及び約０．１〜１０Ｔｏｒｒの圧力で、１５〜６００秒間又はそれ以上の間、３０〜３０００ｓｅｅｍまでの流量のエチレン、アセチレン、又は同様の炭化水素ガスに曝すことにより成される。実行された試験において、ＳｉＣ、ＳｉＣＮ、又はＳｉＯＣＮが形成され、これらは全て、２１５℃を下回る温度のＨＰＡエッチングに大きく影響されないことが分かった。ＨＰＡは概して１２０℃〜１８０℃の温度で用いられるため、下にあるシリコンナイトライド側壁スペーサは、第２の誘電性材料により保護される。 In one particular example, the first dielectric material comprises BTBAS-derived silicon nitride, including silicon carbide (SiC), silicon carbonitride (SiCN), and / or silicon oxycarbonoxide (SiOCN) film. Carbon is added to the top surface of the second dielectric material, which forms a thin layer, typically 10 to 20 angstrom thick. This is a BTBAS silicon nitride film previously used as a gate stack sidewall at a temperature of generally 300 ° C. to 800 ° C. and a pressure of about 0.1-10 Torr before depositing the subsequent disposable spacer film. It is accomplished by exposure to ethylene, acetylene, or similar hydrocarbon gases at flow rates up to 30-3000 seam for 15-600 seconds or longer. In the tests performed, SiC, SiCN, or SiOCN were formed, all of which were found to be significantly unaffected by HPA etching at temperatures below 215 ° C. Since HPA is generally used at temperatures between 120 ° C and 180 ° C, the underlying silicon nitride side wall spacer is protected by a second dielectric material.

明らかなプロセス差異のほかに、共に化学的に結合されている開示される表面変換された側壁スペーサのための第２の誘電体材料の第１の誘電体材料に対する関係は、第１の誘電性材料上の第２の誘電体材料の気相成長（例えば化学気相成長）に起因する既知の配置とは異なり、第２の誘電体材料は、比較的弱いファン・デル・ワールスの力により第１の誘電体材料に取り付けられるようになる。また、開示される化学的変換プロセスに本質的に起因して、第２の誘電体材料のエリアは、第１の誘電性材料のエリアと整合する。これに対し、第１の誘電性材料上の第２の誘電体材料の気相成長に起因する既知の配置では、第２の誘電体材料のエリアは、スペーサ形成のために必要とされるエッチングプロセスに起因して第１の誘電体材料のエリアと比較して異なり得る。 In addition to obvious process differences, the relationship of the second dielectric material for the disclosed surface-transformed side wall spacers, which are both chemically bonded, to the first dielectric material is the first dielectric property. Unlike known arrangements due to vapor deposition (eg, chemical vapor deposition) of the second dielectric material on the material, the second dielectric material is seconded by the relatively weak van der Waals force. It will be attached to the dielectric material of 1. Also, due essentially to the disclosed chemical conversion process, the area of the second dielectric material is consistent with the area of the first dielectric material. In contrast, in a known arrangement due to vapor deposition of the second dielectric material on the first dielectric material, the area of the second dielectric material is the etching required for spacer formation. Due to the process, it may differ compared to the area of the first dielectric material.

ステップ１０４が、ゲートスタックの横の半導体表面に軽くドープされたドレイン（ＬＤＤ）を形成するためイオン注入することを含む。ＣＭＯＳプロセスでは、ＰＭＯＳトランジスタ及びＮＭＯＳトランジスタは概して各々、個別のＬＤＤ注入を受ける。ステップ１０５が、表面変換された側壁スペーサ上に第２のスペーサを形成することを含む。ステップ１０６が、ゲートスタックの横にソース及びドレインを形成することを含む。第２のスペーサを形成した後、ゲートスタックの横の半導体表面にソース及びドレインを形成するためにイオン注入を用いることができる。典型的なＣＭＯＳプロセスでは、ＰＭＯＳトランジスタ及びＮＭＯＳトランジスタは各々個別のソース／ドレイン注入を受ける。しかし、代替として、第２の側壁スペーサは、ＳｉＧｅ Ｓ／Ｄプロセス（例えば、典型的にＰＭＯＳ領域に窪みが形成され、ＳｉＧｅで置換される）に用いることもできる。ステップ１０７が、ソース／ドレイン形成（ステップ１０６）後第２のスペーサを選択的に取り除くことを含む。化学的に変換された層の表面は、第１の誘電体材料が表面変換された層により保護されるように、選択的エッチング後も元のままである。 Step 104 involves ion implantation to form a lightly doped drain (LDD) on the semiconductor surface beside the gate stack. In a CMOS process, a MOSFET transistor and an NMOS transistor generally each undergo a separate LDD injection. Step 105 comprises forming a second spacer on the surface-transformed side wall spacer. Step 106 involves forming sources and drains beside the gate stack. After forming the second spacer, ion implantation can be used to form the source and drain on the semiconductor surface beside the gate stack. In a typical CMOS process, a MOSFET transistor and an NMOS transistor each undergo a separate source / drain injection. However, as an alternative, the second side wall spacer can also be used in a SiGe S / D process (eg, a recess typically formed in the MIMO region and replaced by SiGe). Step 107 comprises selectively removing the second spacer after source / drain formation (step 106). The surface of the chemically transformed layer remains intact after selective etching so that the first dielectric material is protected by the surface transformed layer.

図２Ａ〜図２Ｆは、例示の一実施例に従って、表面変換された側壁スペーサを有するＩＣデバイスを製造する例示の方法のための処理進行を図示する断面図である。図２Ｇは、側壁スペーサの意図しない除去を示す既知のスペーサプロセス後の結果のスペーサ構造を示す。図２Ａは、如何なる側壁スペーサが基板３０５上に形成される前のゲート誘電体２１２上のゲート電極２１１を含むゲートスタックを示す。基板３０５は、シリコン、シリコンゲルマニウム、並びにＩＩ−ＶＩ及びＩＩＩ−Ｖ基板、並びにＳＯＩ基板など、任意の基板材料を含み得る。ゲート電極２１１は、ポリシリコン、又は種々のその他のゲート電極材料を含み得る。ゲート誘電体２１２は、任意選択の高ｋ誘電体を含む種々のゲート誘電体を含み得、例えばｋ＞３．９、典型的にはｋ＞７、を有すると定義される。一つの特定の実施例において、高ｋ誘電体はシリコンオキシナイトライドを含む。 2A-2F are cross-sectional views illustrating processing progress for an exemplary method of manufacturing an IC device having surface-transformed side wall spacers according to an exemplary embodiment. FIG. 2G shows the resulting spacer structure after a known spacer process showing unintended removal of sidewall spacers. FIG. 2A shows a gate stack containing a gate electrode 211 on a gate dielectric 212 before any side wall spacer is formed on the substrate 305. Substrate 305 may include any substrate material, such as silicon, silicon germanium, and II-VI and III-V substrates, as well as SOI substrates. The gate electrode 211 may include polysilicon, or various other gate electrode materials. The gate dielectric 212 may include various gate dielectrics, including optionally high k dielectrics, and is defined to have, for example, k> 3.9, typically k> 7. In one particular embodiment, the high k dielectric comprises silicon oxynitride.

図２Ｂは、ＲＩＥプロセスにより、シリコンナイトライドオフセットスペーサなど、側壁スペーサ（例えば、窒化物オフセットスペーサ）２１５が形成された後のゲートスタックを示す。図２Ｃは、ＬＤＤ領域２２５を形成するためのＬＤＤイオン注入などのイオン注入プロセス後の結果を示し、このプロセスは、側壁スペーサ２１５によって提供されるインプラント阻止を用いた。図２Ｄは、図示する表面変換された層２１６を形成する炭化水素ガスを流すことを含む開示される化学的表面変換ステップ後の結果の構造を示す。図２Ｅは、例えば化学的堆積により及びその後続くＲＩＥより、後続のディスポーザブルな第２のスペーサ２３５が形成された後のゲートスタック２１１／２１２を示す。典型的なＣＭＯＳプロセスの場合、ＰＭＯＳトランジスタ及びＮＭＯＳトランジスタは各々個別のソース／ドレイン注入を受ける。 FIG. 2B shows the gate stack after the sidewall spacers (eg, nitride offset spacers) 215 have been formed, such as silicon nitride offset spacers, by the RIE process. FIG. 2C shows the results after an ion implantation process, such as LDD ion implantation to form the LDD region 225, which used the implant block provided by the side wall spacer 215. FIG. 2D shows the resulting structure after the disclosed chemical surface conversion step, which involves flowing a hydrocarbon gas to form the illustrated surface-transformed layer 216. FIG. 2E shows the gate stack 211/212 after the subsequent disposable second spacer 235 has been formed, for example by chemical deposition and from subsequent RIE. In a typical CMOS process, the MOSFET and NMOS transistors each undergo a separate source / drain injection.

ディスポーザブルな第２のスペーサ２３５はその後、ソース／ドレイン形成後に選択的に取り除かれる。図２Ｆは、熱（例えば、１２０〜１８０℃）ＨＰＡエッチングになどにより、ディスポーザブルな第２のスペーサ２３５が選択的に取り除かれた後のゲートスタック２１２／２１１を示す。表面変換された層２１６は、側壁スペーサ２１５が表面変換された層２１６により保護されるように、エッチング後も元のままであることに留意されたい。開示される表面変換された層がない場合、それがシリコンナイトライドを含むなどの側壁スペーサ２１５は、ディスポーザブルな第２のスペーサ２３５を取り除くために用いられるプロセスを用いた除去を受ける。図２Ｇは、既知のスペーサプロセス後の結果のスペーサ構造を示し、側壁スペーサ２１５の意図しない完全な除去後の結果を示す。 The disposable second spacer 235 is then selectively removed after source / drain formation. FIG. 2F shows the gate stack 212/211 after the disposable second spacer 235 has been selectively removed, such as by thermal (eg, 120-180 ° C.) HPA etching. Note that the surface-transformed layer 216 remains intact after etching so that the side wall spacer 215 is protected by the surface-transformed layer 216. In the absence of the disclosed surface-transformed layer, the sidewall spacer 215, such as which it contains silicon nitride, undergoes removal using the process used to remove the disposable second spacer 235. FIG. 2G shows the spacer structure as a result of the known spacer process and shows the result after unintended complete removal of the sidewall spacer 215.

図３は、例示の一実施例に従った、第１の誘電性材料上の第２の誘電体材料を含む表面変換された側壁スペーサを有するＭＯＳトランジスタを含むＩＣデバイス３００（例えば、半導体ダイ）の一部の断面図であり、第２の誘電体材料は、遷移領域にわたって第１の誘電性材料に化学的に結合される。バックエンドオブライン（ＢＥＯＬ）メタライゼーションは簡潔にするため図示しない。ＩＣ３００は、半導体表面３０６を有する、Ｐ型シリコン又はＰ型シリコンゲルマニウム基板などの基板３０５を含む。シャロートレンチアイソレーション（ＳＴＩ）など任意選択のトレンチアイソレーション３０８が示されている。ＮチャネルＭＯＳ（ＮＭＯＳ）トランジスタ３１０が、Ｎウェル３０７内にあるＰチャネルＭＯＳ（ＰＭＯＳ）トランジスタ３２０と共に示されている。 FIG. 3 shows an IC device 300 (eg, a semiconductor die) comprising a MOS transistor having a surface-transformed side wall spacer containing a second dielectric material on a first dielectric material, according to an exemplary embodiment. It is a partial cross-sectional view of the above, wherein the second dielectric material is chemically bonded to the first dielectric material over the transition region. Back-end of line (BEOL) metallization is not shown for brevity. The IC 300 includes a substrate 305, such as a P-type silicon or P-type silicon germanium substrate, having a semiconductor surface 306. Optional trench isolation 308, such as shallow trench isolation (STI), is shown. An N-channel MOS (

ＮＭＯＳトランジスタ３１０は、ゲートスタックの側壁上の側壁スペーサを有するゲート誘電体３１２上のゲート電極３１１を含むゲートスタックを含む。側壁スペーサは、第１の誘電体材料３１５ｂ上の第２の誘電体材料３１５ａを含み、第２の誘電体材料３１５ａは、遷移領域３１５ｃにわたって第１の誘電体材料３１５ｂに化学的に結合される。第２の誘電体材料３１５ａは炭素を含み、第１の誘電体材料は炭素を含まず、本明細書において用いられる「炭素を含まない」とは、Ｃ＜３％の重量パーセントを指す。 The NMOS transistor 310 includes a gate stack that includes a gate electrode 311 on a gate dielectric 312 that has a side wall spacer on the side wall of the gate stack. The sidewall spacers include a second dielectric material 315a on a first dielectric material 315b, the second dielectric material 315a being chemically bonded to the first dielectric material 315b over the transition region 315c. .. The second dielectric material 315a contains carbon, the first dielectric material does not contain carbon, and as used herein, "carbon-free" refers to a weight percent of C <3%.

ＮＭＯＳトランジスタ３１０は、側壁スペーサの横のソース３２１領域及びドレイン３２２領域を含み、軽くドープされた拡張部３２１ａ及び３２２ａを含む。シリサイド層３１６が、ゲート電極３１１及びソース３２１及びドレイン３２２上に示されている。 The NMOS transistor 310 includes a source 321 region and a drain 322 region beside the side wall spacer, and includes lightly doped extensions 321a and 322a. The silicide layer 316 is shown on the gate electrode 311 and the source 321 and drain 322.

同様に、ＰＭＯＳトランジスタ３２０は、ゲートスタックの側壁上の側壁スペーサを有するゲート誘電体３３２（これは、ゲート電極３１１下のゲート誘電体３１２と同じ材料であってもよい）上のゲート電極３３１を含むゲートスタックを含み、第１の誘電体材料３１５ｂ上の第２の誘電体材料３１５ａを含み、第２の誘電体材料３１５ａは、遷移領域３１５ｃにわたって第１の誘電体材料３１５ｂに化学的に結合される。第２の誘電体材料３１５ａは、炭素を含み、第１の誘電体材料は炭素を含まない。ＰＭＯＳトランジスタ３２０は、側壁スペーサの横のソース３４１領域及びドレイン３４２領域を含み、軽くドープされた拡張部３４１ａ及び３４２ａを含む。シリサイド層３１６が、ゲート電極３３１上及びソース３４１及びドレイン３４２上に示されている。 Similarly, the PRIVATE transistor 320 has a gate electrode 331 on a gate dielectric 332 having a side wall spacer on the side wall of the gate stack, which may be of the same material as the gate dielectric 312 under the gate electrode 311. Containing a gate stack comprising, including a second dielectric material 315a on a first dielectric material 315b, the second dielectric material 315a chemically bonds to the first dielectric material 315b over the transition region 315c. Will be done. The second dielectric material 315a contains carbon and the first dielectric material does not contain carbon. The epitaxial transistor 320 includes a source 341 region and a drain 342 region beside the side wall spacer, and includes lightly doped extensions 341a and 342a. Silicide layers 316 are shown on the gate electrode 331 and on the source 341 and drain 342.

側壁スペーサ３１５ａ／３１５ｃ／３１５ｂのその基部でその最も幅広いポイントでの総厚は、４０〜７０オングストローム厚みなど、概して≦１００オングストロームである。例えば、一つの特定の実施例において、第２の誘電体材料３１５ａは約５〜１０オングストローム厚みであり、遷移領域３１５ｃは１５〜２５オングストローム厚みであり、第１の誘電体材料３１５ｂは２０〜３０オングストローム厚みである。 The total thickness at its widest point at its base of the sidewall spacers 315a / 315c / 315b is generally ≤100 angstroms, such as 40-70 angstrom thickness. For example, in one particular embodiment, the second dielectric material 315a has a thickness of about 5-10 angstroms, the transition region 315c has a thickness of 15-25 angstroms, and the first dielectric material 315b has a thickness of 20-30. Angstrom thickness.

図４は、例示の一実施例に従って、例示の表面変換された側壁スペーサ４００の厚みの関数として組成を示し、表面変換された側壁スペーサ４００の厚みにわたって提供される化学的結合の高度に簡略化した描写を含む。表面変換された側壁スペーサ４００は、ゲートスタック材料の側壁上の第１の誘電体材料３１５ｂと、遷移領域３１５ｃにわたって第１の誘電体材料３１５ｂに化学的に結合される第２の誘電体材料３１５を含む化学的に変換された頂部（外側）表面とを含む、その厚みにわたって非一定の化学的組成プロファイルを含む。図示する実施例において、第１の誘電体材料３１５ｂはシリコンナイトライド（概してＳｉ３Ｎ４）を含み、第２の誘電体材料３１５ａはシリコンカーバイド（ＳｉＣ）を含み、遷移領域３１５ｃは、Ｓｉ、Ｎ、及びＣを含む材料を含み、ここで、第２の誘電体材料３１５ａ／ゲートスタックまでの距離が低減されるにつれてＣ含有量が減少しＮ含有量が増大する。 FIG. 4 shows the composition as a function of the thickness of the illustrated surface-transformed side wall spacer 400 according to an exemplary embodiment, with a high degree of simplification of the chemical bonds provided over the thickness of the surface-transformed side wall spacer 400. Includes depictions. The surface-transformed side wall spacer 400 is a second dielectric material 315 that is chemically bonded to the first dielectric material 315b on the side wall of the gate stack material and the first dielectric material 315b over the transition region 315c. Includes a non-constant chemical composition profile over its thickness, including with a chemically transformed top (outer) surface. In the illustrated embodiment, the first dielectric material 315b comprises silicon nitride (generally Si3N4), the second dielectric material 315a comprises silicon carbide (SiC), and the transition region 315c comprises Si, N, and It contains a material containing C, where the C content decreases and the N content increases as the distance to the second dielectric material 315a / gate stack is reduced.

開示される半導体ダイは、その中の種々の要素及び／又はその上の層を含み得る。これらは、障壁層、誘電体層、デバイス構造、ソース領域、ドレイン領域、ビット線、ベース、エミッタ、コレクタ、導電性線、導電性ビアなどを含む能動要素及び受動要素を含み得る。また、半導体ダイは、バイポーラ、ＣＭＯＳ、ＢｉＣＭＯＳ、及びＭＥＭＳを含む種々のプロセスから形成することができる。 The disclosed semiconductor dies may include various elements therein and / or layers above it. These may include active and passive elements including barrier layers, dielectric layers, device structures, source regions, drain regions, bit wires, bases, emitters, collectors, conductive wires, conductive vias and the like. Also, semiconductor dies can be formed from a variety of processes, including bipolar, CMOS, BiCMOS, and MEMS.

本開示に関連する技術に習熟した者であれば、本発明の特許請求の範囲内で、他の実施例及び実施例の変形が可能であること、及び本発明の特許請求の範囲から逸脱することなく、説明した実施例に更なる付加、削除、代替、及び変更が成され得ることが分かるであろう。 Any person who is proficient in the art related to the present disclosure can modify other examples and examples within the scope of the claims of the present invention, and deviates from the scope of the claims of the present invention. Without it, it will be found that further additions, deletions, substitutions, and changes can be made to the described embodiments.

Claims (4)

集積回路を製造する方法であって、
その上にゲートスタックを有する基板の半導体表面上に第１の誘電体材料を堆積することであって、前記ゲートスタックがゲート誘電体上のゲート電極を含む、前記堆積することと、
前記ゲートスタックの側壁上に前記第１の誘電体材料を含む側壁スペーサを形成するために前記第１の誘電体材料をエッチングすることと、
前記側壁スペーサを形成するエッチングの後に、変換された側壁スペーサ表面を提供するために、そこに少なくとも１つの要素を付加することにより前記側壁スペーサの前記第１の誘電体材料の頂部表面を第２の誘電体材料に化学的に変換させることと、
を含み、
前記第２の誘電体材料が遷移領域にわたって前記第１の誘電体材料に化学的に結合され、
前記遷移領域が炭素を含み、前記炭素の含有量が前記ゲートスタックへの距離が低減されるにつれて減少する、方法。 A method of manufacturing integrated circuits
The deposition of a first dielectric material on the semiconductor surface of a substrate having a gate stack on it, wherein the gate stack contains a gate electrode on the gate dielectric.
Etching the first dielectric material to form a side wall spacer containing the first dielectric material on the side wall of the gate stack.
The top surface of the first dielectric material of the sidewall spacer is seconded by adding at least one element therein to provide a converted sidewall spacer surface after etching to form the sidewall spacer. To be chemically converted to a dielectric material of
Including
It said second dielectric material is chemically bonded to said first dielectric material over the transition region,
A method in which the transition region contains carbon and the carbon content decreases as the distance to the gate stack decreases. 請求項１に記載の方法であって、
前記エッチングすることが、反応性イオンエッチング（ＲＩＥ）を含み、前記化学的に変換させることが、前記第１の誘電体材料との化学反応を起こすための条件下でガスを流すことを含む、方法。 The method according to claim 1.
That said etching comprises reactive ion etching (RIE), thereby converting the chemically comprises flowing a gas under conditions to cause chemical reaction between the first dielectric material, Method. 請求項１に記載の方法であって、
前記第１の誘電体材料がシリコンナイトライドを含む、方法。 The method according to claim 1.
It said first dielectric material comprises silicon nitride, methods. 集積回路（ＩＣ）であって、
半導体表面を有する基板と、
前記半導体表面上の少なくとも１つの金属酸化物半導体（ＭＯＳ）トランジスタと、
を含み、
前記ＭＯＳトランジスタが、
ゲートスタックの側壁上の側壁スペーサを有するゲート誘電体上のゲート電極を含む前記ゲートスタックであって、前記側壁スペーサが第１の誘電体材料と第２の誘電体材料と前記第２の誘電体材料と前記第１の誘電体材料との間の遷移領域とを含む、前記ゲートスタックと、
前記半導体表面における前記側壁スペーサの隣接側面のソース及びドレイン領域と、
を含み、
前記第１の誘電体材料がシリコンナイトライドを含んで炭素を含まず、
前記第２の誘電体材料がシリコンカーバイド（ＳｉＣ）を含み、
前記第２の誘電体材料が遷移領域にわたって前記第１の誘電体材料に化学的に結合され、
前記遷移領域が炭素を含み、前記炭素の含有量が前記ゲートスタックへの距離が低減されるにつれて減少する、ＩＣ。 It is an integrated circuit (IC)
A substrate with a semiconductor surface and
With at least one metal oxide semiconductor (MOS) transistor on the semiconductor surface,
Including
The MOS transistor
The gate stack comprising a gate electrode on a gate dielectric having a side wall spacer on the side wall of the gate stack, wherein the side wall spacer is a first dielectric material, a second dielectric material, and the second dielectric. A gate stack comprising a transition region between the material and the first dielectric material.
Source and drain regions on adjacent sides of the side wall spacers on the semiconductor surface,
Including
The first dielectric material contains silicon nitride and does not contain carbon.
The second dielectric material comprises silicon carbide (SiC).
The second dielectric material is chemically bonded to the first dielectric material over the transition region.
An IC in which the transition region contains carbon and the carbon content decreases as the distance to the gate stack decreases.
JP2019079500A 2011-03-28 2019-04-18 Integrated circuit with chemically modified spacer surface Active JP6916430B2 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201161468308P 2011-03-28 2011-03-28
US61/468,308 2011-03-28
US13/427,062 2012-03-22
US13/427,062 US9496359B2 (en) 2011-03-28 2012-03-22 Integrated circuit having chemically modified spacer surface
JP2017088445A JP6534163B2 (en) 2011-03-28 2017-04-27 Integrated circuit having a chemically modified spacer surface

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2017088445A Division JP6534163B2 (en) 2011-03-28 2017-04-27 Integrated circuit having a chemically modified spacer surface

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2021017147A Division JP7157835B2 (en) 2011-03-28 2021-02-05 Integrated circuit with chemically modified spacer surface

Publications (2)

Publication Number Publication Date
JP2019145825A JP2019145825A (en) 2019-08-29
JP6916430B2 true JP6916430B2 (en) 2021-08-11

Family

ID=46932319

Family Applications (4)

Application Number Title Priority Date Filing Date
JP2014502758A Pending JP2014514757A (en) 2011-03-28 2012-03-28 Integrated circuits having chemically modified spacer surfaces
JP2017088445A Active JP6534163B2 (en) 2011-03-28 2017-04-27 Integrated circuit having a chemically modified spacer surface
JP2019079500A Active JP6916430B2 (en) 2011-03-28 2019-04-18 Integrated circuit with chemically modified spacer surface
JP2021017147A Active JP7157835B2 (en) 2011-03-28 2021-02-05 Integrated circuit with chemically modified spacer surface

Family Applications Before (2)

Application Number Title Priority Date Filing Date
JP2014502758A Pending JP2014514757A (en) 2011-03-28 2012-03-28 Integrated circuits having chemically modified spacer surfaces
JP2017088445A Active JP6534163B2 (en) 2011-03-28 2017-04-27 Integrated circuit having a chemically modified spacer surface

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2021017147A Active JP7157835B2 (en) 2011-03-28 2021-02-05 Integrated circuit with chemically modified spacer surface

Country Status (2)

Country Link
JP (4) JP2014514757A (en)
WO (1) WO2012135363A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104952725B (en) * 2014-03-24 2018-02-06 中芯国际集成电路制造(上海)有限公司 A kind of semiconductor devices and its manufacture method
JP7019085B1 (en) 2021-04-26 2022-02-14 Dmg森精機株式会社 Machine Tools

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3811518B2 (en) * 1995-01-12 2006-08-23 松下電器産業株式会社 Semiconductor device and manufacturing method thereof
JP2002246463A (en) * 2001-02-13 2002-08-30 Sony Corp Method for manufacturing semiconductor device, and semiconductor device
KR100416628B1 (en) * 2002-06-22 2004-01-31 삼성전자주식회사 Manufacturing method for semiconductor device including gate spacer
US6806149B2 (en) 2002-09-26 2004-10-19 Texas Instruments Incorporated Sidewall processes using alkylsilane precursors for MOS transistor fabrication
JP2004134687A (en) 2002-10-15 2004-04-30 Toshiba Corp Semiconductor device and method for manufacturing the same
US6812073B2 (en) 2002-12-10 2004-11-02 Texas Instrument Incorporated Source drain and extension dopant concentration
KR20040051696A (en) * 2002-12-11 2004-06-19 주식회사 하이닉스반도체 Method for forming spacer of intermediate layer of semicoductor device
JP2004200550A (en) 2002-12-20 2004-07-15 Renesas Technology Corp Method of manufacturing semiconductor device
JP4193638B2 (en) * 2003-08-20 2008-12-10 ソニー株式会社 Semiconductor device manufacturing method and semiconductor device
US6991979B2 (en) * 2003-09-22 2006-01-31 International Business Machines Corporation Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs
US7229869B2 (en) 2005-03-08 2007-06-12 Texas Instruments Incorporated Method for manufacturing a semiconductor device using a sidewall spacer etchback
JP2007053296A (en) * 2005-08-19 2007-03-01 Elpida Memory Inc Semiconductor device and its manufacturing method
US7371649B2 (en) * 2005-09-13 2008-05-13 United Microelectronics Corp. Method of forming carbon-containing silicon nitride layer
JP2007157870A (en) * 2005-12-02 2007-06-21 Renesas Technology Corp Semiconductor device and method of manufacturing same
JP2008047820A (en) * 2006-08-21 2008-02-28 Toshiba Corp Semiconductor device and manufacturing method thereof
JP2008117848A (en) * 2006-11-01 2008-05-22 Nec Electronics Corp Manufacturing method of semiconductor device
JP2009140967A (en) * 2007-12-03 2009-06-25 Panasonic Corp Method of manufacturing semiconductor device
JP2009170751A (en) * 2008-01-18 2009-07-30 Fujitsu Ltd Method of manufacturing semiconductor device
US8138045B2 (en) * 2008-05-19 2012-03-20 Texas Instruments Incorporated Method of forming sidewall spacers to reduce formation of recesses in the substrate and increase dopant retention in a semiconductor device
JP2010118500A (en) * 2008-11-13 2010-05-27 Toshiba Corp Semiconductor device and its production process

Also Published As

Publication number Publication date
JP2019145825A (en) 2019-08-29
JP7157835B2 (en) 2022-10-20
JP2021073735A (en) 2021-05-13
JP2014514757A (en) 2014-06-19
WO2012135363A2 (en) 2012-10-04
JP2017143302A (en) 2017-08-17
WO2012135363A3 (en) 2012-12-06
JP6534163B2 (en) 2019-06-26

Similar Documents

Publication Publication Date Title
US10483261B2 (en) Integrated circuit having chemically modified spacer surface
US8450834B2 (en) Spacer structure of a field effect transistor with an oxygen-containing layer between two oxygen-sealing layers
US9589803B2 (en) Gate electrode of field effect transistor
US7592232B2 (en) Method for manufacturing semiconductor device
US20060166457A1 (en) Method of making transistors and non-silicided polysilicon resistors for mixed signal circuits
US10304745B2 (en) Structure for CMOS metal gate stack
US7858484B2 (en) Semiconductor device and method for producing the same
US20190148151A1 (en) Selective High-K Formation in Gate-Last Process
JP2009026997A (en) Semiconductor device, and manufacturing method thereof
CN105789275A (en) Semiconductor device structure with gate spacer having protruding bottom portion and method for forming the same
JP7157835B2 (en) Integrated circuit with chemically modified spacer surface
US11271103B2 (en) Semiconductor device and manufacturing process thereof
WO2005112104A2 (en) Cmos transistor using high stress liner layer
US8273645B2 (en) Method to attain low defectivity fully silicided gates
US9397182B2 (en) Transistor structure with silicided source and drain extensions and process for fabrication
JPWO2008117430A1 (en) Semiconductor device manufacturing method, semiconductor device
US7709349B2 (en) Semiconductor device manufactured using a gate silicidation involving a disposable chemical/mechanical polishing stop layer
CN109786254B (en) Selective high-k formation in gate last process
EP1843397A1 (en) Semiconductor device
JP2007234740A (en) Manufacturing method of semiconductor device
JP2014514757A5 (en)
JP3954589B2 (en) Manufacturing method of semiconductor device
KR20100108419A (en) Thin film and method for manufacturing semiconductor device using the thin film
JP2009016754A (en) Semiconductor device and its manufacturing method
TW569346B (en) Method for forming etch stop layer in borderless contact processing

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20190419

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20190516

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20190516

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20200228

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20200305

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20200603

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20200802

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20201021

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20210206

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20210208

C60 Trial request (containing other claim documents, opposition documents)

Free format text: JAPANESE INTERMEDIATE CODE: C60

Effective date: 20210206

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20210218

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20210217

C21 Notice of transfer of a case for reconsideration by examiners before appeal proceedings

Free format text: JAPANESE INTERMEDIATE CODE: C21

Effective date: 20210224

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20210323

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20210602

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20210616

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20210617

R150 Certificate of patent or registration of utility model

Ref document number: 6916430

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150