JP6902000B2 - 演算装置 - Google Patents
演算装置 Download PDFInfo
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- JP6902000B2 JP6902000B2 JP2018131057A JP2018131057A JP6902000B2 JP 6902000 B2 JP6902000 B2 JP 6902000B2 JP 2018131057 A JP2018131057 A JP 2018131057A JP 2018131057 A JP2018131057 A JP 2018131057A JP 6902000 B2 JP6902000 B2 JP 6902000B2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
- G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
- G06F7/5443—Sum of products
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
- G11C19/282—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements with charge storage in a depletion layer, i.e. charge coupled devices [CCD]
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
- G11C19/287—Organisation of a multiplicity of shift registers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
- G06F2207/4802—Special implementations
- G06F2207/4818—Threshold devices
- G06F2207/4824—Neural networks
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Description
図面は模式的または概念的なものであり、各部分の厚さと幅との関係、部分間の大きさの比率などは、必ずしも現実のものと同一とは限らない。同じ部分を表す場合であっても、図面により互いの寸法や比率が異なって表される場合もある。
本願明細書と各図において、既出の図に関して前述したものと同様の要素には同一の符号を付して詳細な説明は適宜省略する。
図1は、第1実施形態に係る演算装置を例示する模式図である。
図1に示すように、実施形態に係る演算装置110は、1つまたは複数の演算ユニット10Uを含む。1つまたは複数の演算ユニット10Uの1つは、記憶部10及び演算部20を含む。記憶部10は、複数の記憶領域10Rを含む。
図2に示すように、複数の記憶領域10Rの少なくとも1つは、シフトレジスタ型の記憶素子10Dを含む。
これらの図は、シフトレジスタ型の記憶素子10Dの例を示している。記憶素子10Dは、電荷結合型素子40(Charge-Coupled Device:CCD)を含む。
図4に示すように、シフトレジスタ型の記憶素子10Dは、電荷結合型素子40に加えた、発光素子40E及び受光素子40Rをさらに含んでも良い。
第2実施形態においては、シフトレジスタ型の記憶素子10Dは、デジタル・シフトレジスタを含む。
これらの図は、本実施形態に係る演算装置120の記憶部10におけるシフトレジスタ型の記憶素子10Dを例示している。演算装置120におけるこれ以外の構成は、例えば、演算装置110と同様である。以下、演算装置120におけるシフトレジスタ型の記憶素子10Dの例について説明する。
複数のフリップ・フロップ回路61は、一列に電気的に接続される。フリップ・フロップ素子60の1つの端部(例えば、左端)に、1つの情報(この例では”1010”)が入力される。例えば、”T端子”にパルス信号が入力されるごとに、情報が、1つの端部(例えば、左端)から、別の端部(例えば右端)に向けてシフトする。
図6に示すように、1つの演算ユニット10Uは、例えば、コアC(1,1)に対応する。コアC(1,1)は、例えば、イジング・マシンの少なくとも一部となる。この例では、「i」は、1であり、「j」は、1〜100の整数である。
図7は、1つのサブコア(この例では、subC(1,1))の例を示している。例えば、複数のシフトレジスタ型の記憶素子10Dが設けられる。
図8も、1つのサブコア(この例では、サブコアsubC(1,1))の例を示している。複数のシフトレジスタ型の記憶素子10Dが設けられる。
図9に示すように、演算装置110または120は、複数の演算ユニット10Uを含んでも良い。複数の演算ユニット10Uは、複数のコアに対応する。この例では、コアC(1,1)〜コア(10,10)が設けられている。複数のコアの数は、100である。
Claims (5)
- 1つまたは複数の演算ユニットを備え、
前記1つまたは複数の前記演算ユニットの1つは、
複数の記憶領域を含む記憶部と、
演算部と、
を含み、
前記複数の記憶領域のそれぞれは、シフトレジスタ型の記憶素子を含み、
前記複数の記憶領域の前記記憶素子のそれぞれは、電荷結合型素子と、発光素子と、受光素子と、を含み、
前記記憶素子のそれぞれにおいて、前記発光素子から出射する光が、前記受光素子に入り、前記受光素子の出力信号が、前記電荷結合型素子に供給される、演算装置。 - 前記電荷結合型素子は、3値以上の状態を保持可能である、請求項1記載の演算装置。
- 前記電荷結合型素子は、2値の状態を保持可能である、請求項1記載の演算装置。
- 電荷結合型素子は、酸化物半導体を含む、請求項1〜3のいずれか1つに記載の演算装置。
- 前記複数の演算ユニットの少なくとも2つは、並列に動作する、請求項1〜4のいずれか1つに記載の演算装置。
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JP2018131057A JP6902000B2 (ja) | 2018-07-10 | 2018-07-10 | 演算装置 |
US16/351,287 US11163534B2 (en) | 2018-07-10 | 2019-03-12 | Arithmetic device |
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JP6902000B2 true JP6902000B2 (ja) | 2021-07-14 |
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Publication number | Priority date | Publication date | Assignee | Title |
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US4326192A (en) * | 1979-06-11 | 1982-04-20 | International Business Machines Corporation | Sequential successive approximation analog-to-digital converter |
JPS574538A (en) * | 1980-06-11 | 1982-01-11 | Sanki Eng Kk | Picture type corpuscle counter |
US5008833A (en) * | 1988-11-18 | 1991-04-16 | California Institute Of Technology | Parallel optoelectronic neural network processors |
JP2746350B2 (ja) | 1990-05-22 | 1998-05-06 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 学習機械シナプス・プロセッサ・システム装置 |
US5508538A (en) * | 1993-04-19 | 1996-04-16 | California Institute Of Technology | Signal processing applications of massively parallel charge domain computing devices |
US6356973B1 (en) * | 1993-10-15 | 2002-03-12 | Image Telecommunications Corporation | Memory device having a cyclically configured data memory and having plural data portals for outputting/inputting data |
JP4538310B2 (ja) | 2004-12-24 | 2010-09-08 | 株式会社リコー | 画像形成装置及び画像形成方法 |
CN101502100A (zh) | 2006-08-09 | 2009-08-05 | 松下电器产业株式会社 | 图象传感器驱动装置 |
US8127075B2 (en) | 2007-07-20 | 2012-02-28 | Seagate Technology Llc | Non-linear stochastic processing storage device |
CN110050267B (zh) * | 2016-12-09 | 2023-05-26 | 北京地平线信息技术有限公司 | 用于数据管理的系统和方法 |
US12001945B2 (en) * | 2018-04-26 | 2024-06-04 | Aistorm Inc. | Event driven mathematical engine and method |
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US11163534B2 (en) | 2021-11-02 |
US20200019377A1 (en) | 2020-01-16 |
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