JP6890668B2 - Manufacturing method of metal-filled microstructure and insulating base material - Google Patents

Description

The present invention relates to an insulating base material used in a method for manufacturing a metal-filled microstructure in which a plurality of through holes penetrating in the thickness direction of the insulating base material are filled with metal and a method for manufacturing a metal-filled microstructure. In particular, the present invention relates to a method for producing a metal-filled microstructure in which a plurality of through holes are filled with metal, and an insulating base material.

A metal-filled microstructure in which a plurality of through holes penetrating in the thickness direction of an insulating base material are filled with metal is one of the fields that have been attracting attention in nanotechnology in recent years. Metal-filled microstructures are expected to be used, for example, in battery electrodes, gas permeable membranes, sensors, and anisotropic conductive members.
Since the heterogeneous conductive member can obtain an electrical connection between the electronic component and the circuit board simply by inserting it between the electronic component such as a semiconductor element and the circuit board and pressurizing it, the electronic component such as the semiconductor element can be used. It is widely used as an electrical connection member and an inspection connector for performing functional inspections.
In particular, electronic components such as semiconductor elements are significantly downsized. As a method of directly connecting wiring boards such as conventional wire bonding, flip-chip bonding, thermocompression bonding, etc., it is not possible to sufficiently guarantee the stability of electrical connection of electronic components, so it can be used as an electronic connection member. An anisotropic conductive member is attracting attention.

As a method for manufacturing the above-mentioned metal-filled microstructure, for example, in Patent Document 1, the filling of a metal in a through hole continuously increases the current value at the time of electrolytic plating in a negative direction with respect to the plating time. It is described that it is done by the method.
Further, as an electrolytic plating method used for filling the through holes with metal, Patent Document 2 describes that an electrolytic plating treatment is performed so as to satisfy the following (1) to (4).
(1) Start the electrolytic plating process as a constant current electrolytic plating process.
(2) When the virtual filling rate of the metal in the through hole reaches 75% to 125%, the current value at the time of electrolytic plating is increased in the negative direction.
(3) Electroplating is performed until the virtual filling rate of the metal in the through holes is 101% or more.
(4) The electrolytic plating process is performed so that the virtual filling rate of the metal in the through holes from the increase of the current value at the time of electrolytic plating in the negative direction to the end of the electrolytic plating process is 1% or more.

Japanese Unexamined Patent Publication No. 2009-287115 Japanese Unexamined Patent Publication No. 2011-202194

Regarding the above-mentioned metal-filled microstructure, for example, when manufacturing a large area, the through-holes are not sufficiently filled with metal, and even if the through-holes are filled with metal, cavities are formed. It is necessary to consider the possibility of filling defects such as the above. However, the above-mentioned Patent Document 1 and the above-mentioned Patent Document 2 do not assume the above-mentioned filling defect. Therefore, in Patent Document 1 and Patent Document 2, there is a possibility that not all through holes can be filled with metal.

An object of the present invention is to solve the above-mentioned problems based on the prior art, and to prevent the through holes from being sufficiently filled with metal and from forming cavities when filling the plurality of through holes with metal. To provide a method for producing a metal-filled microstructure and an insulating base material.

In order to achieve the above object, the present invention is a method for producing a metal-filled microstructure in which a plurality of through holes penetrating in the thickness direction of an insulating base material are filled with metal, and the plurality of through holes are formed. It has a metal filling step of filling metal, and in the metal filling step, an insulating base material having a plurality of through holes is immersed in a plating solution containing metal ions for a time exceeding 5 seconds without applying a voltage. After that, the present invention provides a method for manufacturing a metal-filled microstructure in which a plurality of through holes are filled with metal by electrolytic plating by continuously or multi-stage increasing the current value.

In the metal filling step, the immersion time for immersing an insulating base material having a plurality of through holes in a plating solution in a plating solution without applying a voltage is preferably 1 minute or more and 150 minutes or less.
In the metal filling step, it is preferable to vibrate at least one of the insulating base material having a plurality of through holes and the plating solution.
Immersion without applying voltage When the plating processing time indicating the time from the end of immersion to the end of electrolytic plating is T, and the maximum value of the current applied in electrolytic plating is Im, the current is less than 0.1 T. It is preferable to set the current value to less than 0.05 Im and then increase the current value to the maximum value Im in the range of less than 0.1 T.
Electroplating is preferably performed multiple times. When the electrolytic plating is carried out a plurality of times, it is preferable to carry out the electrolytic plating continuously. Further, when the electrolytic plating is performed a plurality of times, it is preferable to provide a period during which no current is applied between the electrolytic platings.
The insulating base material is preferably an aluminum anodic oxide film.
The plating solution preferably contains a surfactant.
It is preferable that the main component of the solid content of the plating solution is copper sulfate.
The present invention also provides an insulating base material used in the above-mentioned method for producing a metal-filled microstructure of the present invention.

According to the present invention, when filling a plurality of through holes with metal, it is possible to prevent the through holes from being sufficiently filled with metal and the occurrence of cavities.

It is a schematic cross-sectional view which shows one step of the 1st aspect of the manufacturing method of the metal-filled microstructure of the embodiment of this invention. It is a schematic cross-sectional view which shows one step of the 1st aspect of the manufacturing method of the metal-filled microstructure of the embodiment of this invention. It is a schematic cross-sectional view which shows one step of the 1st aspect of the manufacturing method of the metal-filled microstructure of the embodiment of this invention. It is a schematic cross-sectional view which shows one step of the 1st aspect of the manufacturing method of the metal-filled microstructure of the embodiment of this invention. It is a schematic cross-sectional view which shows one step of the 1st aspect of the manufacturing method of the metal-filled microstructure of the embodiment of this invention. It is a schematic cross-sectional view which shows one step of the 2nd aspect of the manufacturing method of the metal-filled microstructure of the embodiment of this invention. It is a schematic cross-sectional view which shows one step of the 2nd aspect of the manufacturing method of the metal-filled microstructure of the embodiment of this invention. It is a schematic cross-sectional view which shows one step of the 2nd aspect of the manufacturing method of the metal-filled microstructure of the embodiment of this invention. It is a schematic cross-sectional view which shows one step of the 3rd aspect of the manufacturing method of the metal-filled microstructure of the embodiment of this invention. It is a schematic cross-sectional view which shows one step of the 3rd aspect of the manufacturing method of the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows an example of the supply form of the metal-filled microstructure produced by the 3rd aspect of the manufacturing method of the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which expands and shows the main part of the example of the supply form of the metal-filled microstructure manufactured by the 3rd aspect of the method of manufacturing the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows the electrolytic plating apparatus used in the metal filling process among the manufacturing method of the metal filling microstructure of the embodiment of this invention. It is a flowchart which shows the metal filling process among the manufacturing method of the metal filling microstructure of embodiment of this invention. It is a graph which shows an example of the electric current pattern of the electrolytic plating of the metal filling process among the manufacturing method of the metal-filled microstructure of the embodiment of this invention. It is a graph which shows an example of the electric current pattern of the electrolytic plating of the metal filling process among the manufacturing method of the metal-filled microstructure of the embodiment of this invention. It is a graph which shows an example of the electric current pattern of the electrolytic plating of the metal filling process among the manufacturing method of the metal-filled microstructure of the embodiment of this invention. It is a graph which shows an example of the electric current pattern of the electrolytic plating of the metal filling process among the manufacturing method of the metal-filled microstructure of the embodiment of this invention. It is a graph which shows an example of the electric current pattern of the electrolytic plating of the metal filling process among the manufacturing method of the metal-filled microstructure of the embodiment of this invention. It is a graph which shows an example of the electric current pattern of the electrolytic plating of the metal filling process among the manufacturing method of the metal-filled microstructure of the embodiment of this invention. It is a graph which shows an example of the electric current pattern of the electrolytic plating of the metal filling process among the manufacturing method of the metal-filled microstructure of the embodiment of this invention. It is a graph which shows an example of the electric current pattern of the electrolytic plating of the metal filling process among the manufacturing method of the metal-filled microstructure of the embodiment of this invention. It is a top view which shows an example of the metal-filled microstructure of the embodiment of this invention. It is a schematic cross-sectional view which shows an example of the metal-filled microstructure of embodiment of this invention. It is a schematic cross-sectional view which shows an example of the structure of the anisotropic conductive material using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows the 1st example of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows the 2nd example of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows the 3rd example of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows the 4th example of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the 1st example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the 1st example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the 1st example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the 2nd example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the 2nd example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the 2nd example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the 3rd example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the 3rd example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows the 5th example of the laminated device of embodiment of this invention. It is a schematic diagram which shows the 6th example of the laminated device of embodiment of this invention. It is a schematic diagram which shows the 7th example of the laminated device of embodiment of this invention. It is a schematic diagram which shows the 8th example of the laminated device of embodiment of this invention. It is a schematic diagram which shows the 9th example of the laminated device of embodiment of this invention. It is a schematic diagram which shows one step of the 4th example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the 4th example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the 4th example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the 4th example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the 4th example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the 4th example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the 4th example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the 4th example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the 4th example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the 4th example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the 4th example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the manufacturing method of the laminated body used in the 4th example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the manufacturing method of the laminated body used in the 4th example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the manufacturing method of the laminated body used in the 4th example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the manufacturing method of the laminated body used in the 4th example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the manufacturing method of the laminated body used in the 4th example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the 5th example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the 5th example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the 5th example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the 5th example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the 5th example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the 5th example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the 5th example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the 5th example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the 5th example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the 5th example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the 5th example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the 5th example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the 5th example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the 6th example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the 6th example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the 6th example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the 6th example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a schematic diagram which shows one step of the 6th example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of this invention. It is a graph which shows the 1st example of this joining condition. It is a graph which shows the 2nd example of this joining condition. It is a graph which shows the 3rd example of this joining condition. It is a graph which shows the 4th example of this joining condition. It is a graph which shows the 5th example of this joining condition. It is a graph which shows the sixth example of this joining condition. It is a graph which shows the 7th example of this joining condition. It is a graph which shows the current pattern of a pulse.

Hereinafter, the method for producing the metal-filled microstructure and the insulating base material of the present invention will be described in detail based on the preferred embodiments shown in the attached drawings.
It should be noted that the figures described below are exemplary for explaining the present invention, and the present invention is not limited to the figures shown below.
In the following, "~" indicating the numerical range includes the numerical values described on both sides. For example, when ε is a numerical value α to a numerical value β, the range of ε is a range including the numerical value α and the numerical value β, and is α ≦ ε ≦ β in mathematical symbols.
Angles such as "orthogonal" include error ranges generally tolerated in the art in question, unless otherwise stated. In addition, “identical” includes an error range generally accepted in the relevant technical field. In addition, "whole surface" and the like include an error range generally allowed in the relevant technical field.

There is a lot of demand for filling and plating a metal in the through holes of an insulating base material such as an aluminum anodized film having very fine through holes. However, there is a problem that a partial filling defect (hereinafter, also referred to as an unfilled portion) or a filling defect in which voids remain inside occurs. These are not a problem for experimental use, but if the area of the metal-filled microstructure is increased for use in battery electrodes, gas permeable membranes, sensors, etc., the above-mentioned filling defects and filling defects will have an effect. Occurs. The basic cause of this is poor plating, and it is thought that it is the presence of the cationic depletion layer that suppresses uniform plating, and pulse electrolysis that coexists with electric transport by electric field and transport by diffusion has been proposed and put into practical use in various ways. Has been done.

However, although pulse electrolysis is effective in constantly supplying cations to the surface of the adherend, it is considered that diffusion does not remain inside the very fine through holes.
Therefore, as a means for realizing efficient cation transport in the through hole, a combination of supplying a cation by immersing it in a plating solution without applying a voltage and consuming the cation stepwise by current control. The present invention has been completed with the finding that is effective. Even when manufacturing a large area, it is effective because cations can be supplied to all through holes. Immersion in the plating solution without applying voltage is also referred to as pre-immersion.
Hereinafter, a method for manufacturing a metal-filled microstructure will be specifically described.

<First aspect>
1 to 5 are schematic cross-sectional views showing a first aspect of the method for manufacturing a metal-filled microstructure according to an embodiment of the present invention in order of steps.
The metal-filled microstructure has an insulating base material. The insulating base material is not particularly limited, and an aluminum anodic oxide film will be described as an example of the insulating base material.
First, as shown in FIG. 1, an aluminum substrate 10 is prepared.
The aluminum substrate 10 has a thickness and a thickness depending on the thickness of the anodized film 14 of the finally obtained metal-filled microstructure 20 (see FIG. 5), that is, the thickness of the insulating base material, the processing device, and the like. It will be decided as appropriate. The aluminum substrate 10 is, for example, a rectangular plate material.

Next, the surface 10a (see FIG. 1) on one side of the aluminum substrate 10 is anodized. As a result, the surface 10a (see FIG. 1) on one side of the aluminum substrate 10 is anodized and exists at the bottom of the plurality of through holes 12 extending in the thickness direction Dt of the aluminum substrate 10 as shown in FIG. An anodic oxide film 14 having a barrier layer 13 is formed. The above-mentioned anodic oxidation step is called an anodic oxidation treatment step.
In the anodic oxide film 14 having the plurality of through holes 12, the barrier layer 13 exists at the bottom of the through holes 12 as described above, but the barrier layer 13 is removed as shown in FIG. The step of removing the barrier layer 13 is called a barrier layer removing step.
In the barrier layer removing step, the barrier layer 13 of the anodized film 14 is removed by using an alkaline aqueous solution containing ions of the metal M1 having a higher hydrogen overvoltage than aluminum, and at the same time, the metal (metal M1) is formed on the bottom of the through hole 12. A metal layer 15a made of the material is formed. As a result, the aluminum substrate 10 at the bottom of the through hole 12 is covered with the metal layer 15a.
The anodized film 14 having a plurality of through holes 12 shown in FIG. 3, that is, the insulating base material having a plurality of through holes is referred to as a structure 17.

Next, as shown in FIG. 4, the inside of the through hole 12 of the anodic oxide film 14 is filled with the metal 15b. By filling the inside of the through hole 12 with the metal 15b, a conductive passage 16 having conductivity is formed. In this case, the metal layer 15a made of metal (metal M1) can be used as an electrode for electrolytic plating.
Filling the inside of the through hole 12 with the metal 15b is called a metal filling step. Electroplating is used in the metal filling step, and the metal filling step will be described in detail later.
After the metal filling step, the aluminum substrate 10 is removed as shown in FIG. As a result, the metal-filled microstructure 20 is obtained. The step of removing the aluminum substrate 10 is called a substrate removing step.
As shown in FIG. 1, if the insulating base material 40 having a plurality of through holes 12 can be formed, the present invention is not limited to the aluminum substrate 10.

In the barrier layer removing step before the metal filling step, the barrier layer 13 is not only removed but also through holes are removed by removing the barrier layer using an alkaline aqueous solution containing ions of metal M1 having a higher hydrogen overvoltage than aluminum. A metal layer 15a of metal M1 that is less likely to generate hydrogen gas than aluminum is formed on the aluminum substrate 10 exposed at the bottom of 12. As a result, the in-plane uniformity of the metal filling becomes good. It is considered that this is because the generation of hydrogen gas by the plating solution was suppressed and the metal filling by the electrolytic plating proceeded easily.
Further, in the barrier layer removing step, a holding step of holding the voltage of 95% or more and 105% or less of the voltage (holding voltage) selected from the range of less than 30% of the voltage in the anodic oxidation treatment step for a total of 5 minutes or more is provided. It has been found that the uniformity of metal filling during the plating process is greatly improved by combining the application of an alkaline aqueous solution containing the ions of the metal M1.
Although the detailed mechanism is unknown, in the barrier layer removal step, a layer of metal M1 is formed under the barrier layer by using an alkaline aqueous solution containing ions of metal M1, which damages the interface between the aluminum substrate and the anodic oxide film. It is considered that this is because the reception can be suppressed and the uniformity of dissolution of the barrier layer is improved.

In the barrier layer removing step, a metal layer 15a made of metal (metal M1) was formed at the bottom of the through hole 12, but the present invention is not limited to this, and only the barrier layer 13 is removed to form the through hole 12. The aluminum substrate 10 is exposed on the bottom. The aluminum substrate 10 may be used as an electrode for electrolytic plating with the aluminum substrate 10 exposed.

<Second aspect>
6 to 8 are schematic cross-sectional views showing a second aspect of the method for manufacturing a metal-filled microstructure according to the embodiment of the present invention in order of steps.
In FIGS. 6 to 8, the same components as those shown in FIGS. 1 to 5 are designated by the same reference numerals, and detailed description thereof will be omitted. Note that FIG. 6 shows the state after FIG. 4 described above.
In the second aspect, the steps shown below are different from those in the first aspect described above. As shown in FIG. 6, after the metal filling step, a part of the surface of the anodic oxide film 14 on the side where the aluminum substrate 10 is not provided is removed in the thickness direction, and the metal 15 filled in the metal filling step is anodic oxide film 14. Protrude from the surface of. That is, the conduction path 16 is projected from the surface of the anodic oxide film 14. Protruding the filled metal 15 from the surface of the anodic oxide film 14 is called a surface metal projecting step.
After the surface metal projecting step, the aluminum substrate 10 is removed as shown in FIG. 7 (substrate removing step).

Next, as shown in FIG. 8, the surface of the anodic oxide film 14 on the side where the aluminum substrate 10 is provided is partially removed in the thickness direction after the substrate removing step, and the metal 15 filled in the metal filling step, that is, , The conduction path 16 is projected from the surface of the anodic oxide film 14. As a result, the metal-filled microstructure 20 shown in FIG. 8 is obtained.
The front surface metal projecting step and the back surface metal projecting step may have both steps, but may have one of the front surface metal projecting process and the back surface metal projecting process. The front surface metal projecting process and the back surface metal projecting process are collectively referred to as a "metal projecting process".

<Third aspect>
9 and 10 are schematic cross-sectional views showing a third aspect of the method for manufacturing a metal-filled microstructure according to the embodiment of the present invention in order of steps.
In FIGS. 9 and 10, the same components as those shown in FIGS. 1 to 5 are designated by the same reference numerals, and detailed description thereof will be omitted. Note that FIG. 9 shows the state after FIG. 4 described above.
In the third aspect, the steps shown below are different from those in the first aspect described above. As shown in FIG. 9, the resin layer 19 is provided on the surface of the anodized film 14 on the side where the aluminum substrate 10 is not provided after the metal filling step. Providing the resin layer 19 is called a resin layer forming step.

Next, as shown in FIG. 10, the aluminum substrate 10 is removed after the resin layer forming step (the substrate removing step). As a result, the metal-filled microstructure 20 shown in FIG. 5 is obtained.
In the third aspect, the metal-filled microstructure 20 manufactured as shown in FIG. 11 is intended to be supplied in a state of being wound around the winding core 21 in a roll shape. By peeling off the resin layer 19 (see FIG. 12) when the metal-filled microstructure 20 is used, it can be used as an anisotropic conductive member, for example.

<Other aspects>
As a manufacturing method, for example, the above-mentioned anodization treatment step, holding step, barrier layer removal step, metal filling step, surface metal protrusion step, resin layer formation step, substrate removal step and back surface metal protrusion step are carried out in this order. May be good.
Further, a part of the surface of the aluminum substrate may be anodized using a mask layer having a desired shape.

[Insulating base material]
The insulating base material is particularly limited as long as it ^{is made of an inorganic material and has the same electrical resistivity (about 10 14} Ω · cm) as the insulating base material constituting a conventionally known anisotropic conductive film or the like. Not done.
It should be noted that "consisting of an inorganic material" is a regulation for distinguishing from a polymer material constituting a resin layer, which will be described later, and is not limited to an insulating base material composed only of an inorganic material, but an inorganic material. Is the main component (50% by mass or more).

Examples of the insulating base material include metal oxide base materials, metal nitride base materials, glass base materials, ceramic base materials such as silicon carbide and silicon nitride, carbon base materials such as diamond-like carbon, and polyimide base materials. Examples thereof include these composite materials. The insulating base material may be, for example, a film formed on an organic material having through holes with an inorganic material containing 50% by mass or more of a ceramic material or a carbon material.

The insulating base material is preferably a metal oxide base material because through holes having a desired average opening diameter are formed and it is easy to form a conduction path described later, and the anodized film of the valve metal is used. More preferably.
Here, specific examples of the valve metal include aluminum, tantalum, niobium, titanium, hafnium, zirconium, zinc, tungsten, bismuth, and antimony. Of these, an aluminum anodic oxide film (base material) is preferable because it has good dimensional stability and is relatively inexpensive. Therefore, it is preferable to form an anodized film as an insulating base material using an aluminum substrate to produce a metal-filled microstructure.

[Aluminum substrate]
The aluminum substrate is not particularly limited, and specific examples thereof include a pure aluminum plate; an alloy plate containing aluminum as a main component and containing a trace amount of foreign elements; high-purity aluminum is vapor-deposited on low-purity aluminum (for example, a recycled material). Substrate; Substrate obtained by coating the surface of silicon wafer, quartz, glass or the like with high-purity aluminum by a method such as vapor deposition or sputtering;

Of the aluminum substrate, the surface on which the anodic oxide film is provided by the anodic oxidation treatment step preferably has an aluminum purity of 99.5% by mass or more, more preferably 99.9% by mass or more, and 99.99% by mass. It is more preferably mass% or more. When the aluminum purity is in the above range, the regularity of the through-hole arrangement becomes sufficient.

Further, in the present invention, it is preferable that the surface of one side of the aluminum substrate to be subjected to the anodic oxidation treatment step is subjected to heat treatment, degreasing treatment and mirror finish treatment in advance.
Here, regarding the heat treatment, the degreasing treatment, and the mirror finish treatment, the same treatments as those described in paragraphs <0044> to <0054> of JP-A-2008-270158 can be performed.

[Anodic oxidation treatment process]
In the anodizing step, one side of the above-mentioned aluminum substrate is anodized, so that one side of the above-mentioned aluminum substrate has a through hole penetrating in the thickness direction and a barrier layer existing at the bottom of the through hole. This is the process of forming a film.
For the anodic oxidation treatment, a conventionally known method can be used, but from the viewpoint of increasing the regularity of the through-hole arrangement and ensuring the anisotropic conductivity of the metal-filled microstructure, a self-regularization method or a constant voltage treatment can be used. Is preferably used.
Here, regarding the self-regularization method and the constant voltage treatment of the anodic oxidation treatment, the same treatments as those described in paragraphs <0056> to <0108> and [FIG. 3] of JP-A-2008-270158 are performed. Can be applied.

<Anooxidation treatment>
The average flow rate of the electrolytic solution in the anodic oxidation treatment is preferably 0.5 to 20.0 m / min, more preferably 1.0 to 15.0 m / min, and 2.0 to 10.0 m / min. It is more preferably min.
The method for flowing the electrolytic solution under the above conditions is not particularly limited, but for example, a method using a general stirring device such as a stirrer is used. In particular, it is preferable to use a stirrer whose stirring speed can be controlled by a digital display because the average flow velocity can be controlled. Examples of such a stirrer include "Magnetic stirrer HS-50D (manufactured by AS ONE)" and the like.

For the anodic oxidation treatment, for example, a method of energizing an aluminum substrate as an anode in a solution having an acid concentration of 1 to 10% by mass can be used.
The solution used for the anodic oxidation treatment is preferably an acid solution, and is preferably sulfuric acid, phosphoric acid, chromic acid, oxalic acid, sulfamic acid, benzenesulfonic acid, amidosulfonic acid, glycolic acid, tartaric acid, apple acid and citric acid. Etc. are more preferable, and sulfuric acid, phosphoric acid, and oxalic acid are particularly preferable. These acids can be used alone or in combination of two or more.

The conditions of the anodic oxidation treatment cannot be unconditionally determined because they vary depending on the electrolytic solution used, but generally, the electrolytic solution concentration is 0.1 to 20% by mass, the liquid temperature is -10 to 30 ° C, and the current. The density is preferably 0.01 to 20 A / dm ² , the voltage is 3 to 300 V, the electrolysis time is preferably 0.5 to 30 hours, the electrolyte concentration is 0.5 to 15 mass%, the liquid temperature is -5 to 25 ° C, and the current density is high. More preferably, it is 0.05 to 15 A / dm ² , a voltage of 5 to 250 V, an electrolysis time of 1 to 25 hours, an electrolytic solution concentration of 1 to 10 mass%, a liquid temperature of 0 to 20 ° C., and a current density of 0.1 to 10 A. It is more preferable that / dm ² , the voltage is 10 to 200 V, and the electrolysis time is 2 to 20 hours.

In the above-mentioned anodic oxidation treatment step, the anode formed by the anodic oxidation treatment is formed from the viewpoint of supplying the metal-filled microstructure 20 in a shape wound around a winding core 21 having a predetermined diameter and a predetermined width as shown in FIG. The average thickness of the oxide film is preferably 30 μm or less, more preferably 5 to 20 μm. The average thickness is obtained by cutting the anodized film in the thickness direction with a focused ion beam (FIB) and cutting the cross section with a field emission scanning electron microscope (FE-SEM). ) Was taken, and a surface photograph (magnification of 50,000 times) was taken and calculated as an average value measured at 10 points.

[Holding process]
The method for producing a metal-filled microstructure may include a holding step. The holding step is a voltage of 95% or more and 105% or less of the holding voltage selected from the range of 1 V or more and less than 30% of the voltage in the above-mentioned anodic oxidation treatment step after the above-mentioned anodic oxidation treatment step for a total of 5 minutes or more. This is the process of holding. In other words, the holding step is a total of 95% or more and 105% or less of the holding voltage selected from the range of 1 V or more and less than 30% of the voltage in the above-mentioned anodic oxidation treatment step after the above-mentioned anodic oxidation treatment step. This is a step of performing electrolytic treatment for 5 minutes or more.
Here, the "voltage in the anodic oxidation treatment" is a voltage applied between the aluminum and the counter electrode. For example, if the electrolysis time by the anodic oxidation treatment is 30 minutes, the voltage maintained for 30 minutes. The average value.

From the viewpoint of controlling the thickness of the side wall of the anodic oxide film, that is, the thickness of the barrier layer to an appropriate thickness with respect to the depth of the through hole, the voltage in the holding step is 5% or more and 25% or less of the voltage in the anodic oxidation treatment. It is preferably 5% or more and 20% or less.

Further, for the reason that the in-plane uniformity is further improved, the total holding time in the holding step is preferably 5 minutes or more and 20 minutes or less, more preferably 5 minutes or more and 15 minutes or less, and 5 minutes or more. It is more preferably 10 minutes or less.
The holding time in the holding step may be 5 minutes or more in total, but is preferably 5 minutes or more continuously.

Further, the voltage in the holding step may be set by continuously or stepwise (step-like) dropping from the voltage in the anodic oxidation treatment step to the voltage in the holding step, but for the reason that the in-plane uniformity is further improved. It is preferable to set the voltage to 95% or more and 105% or less of the above-mentioned holding voltage within 1 second after the completion of the anodic oxidation treatment step.

The above-mentioned holding step can also be performed continuously with the above-mentioned anodic oxidation treatment step by, for example, lowering the electrolytic potential at the end of the above-mentioned anodic oxidation treatment step.
In the above-mentioned holding step, the same electrolytic solution and treatment conditions as those of the above-mentioned conventionally known anodic oxidation treatment can be adopted for conditions other than the electrolytic potential.
In particular, when the holding step and the anodic oxidation treatment step are continuously performed, it is preferable to carry out the treatment using the same electrolytic solution.

[Barrier layer removal process]
The barrier layer removing step is a step of removing the barrier layer of the anodic oxide film by using, for example, an alkaline aqueous solution containing ions of a metal M1 having a hydrogen overvoltage higher than that of aluminum.
By the barrier layer removing step described above, the barrier layer is removed, and as shown in FIG. 3, a metal layer 15a made of metal M1 is formed at the bottom of the through hole 12.
Here, the hydrogen overvoltage means a voltage required for hydrogen to be generated. For example, the hydrogen overvoltage of aluminum (Al) is −1.66 V (Journal of the Japanese Society of Chemistry, 1982, (8). ), P1305-1313). An example of the metal M1 having a higher hydrogen overvoltage than that of aluminum and the value of the hydrogen overvoltage thereof are shown below.
<Metal M1 and hydrogen (1NH ₂ SO ₄ ) overvoltage>
-Platinum (Pt): 0.00V
-Gold (Au): 0.02V
-Silver (Ag): 0.08V
-Nickel (Ni): 0.21V
-Copper (Cu): 0.23V
-Tin (Sn): 0.53V
-Zinc (Zn): 0.70V

In the present invention, the barrier layer is removed as described above because it causes a substitution reaction with the metal M2 to be filled in the anodization treatment step described later and has less influence on the electrical characteristics of the metal filled inside the through hole. The metal M1 used in the step is preferably a metal having a higher ionization tendency than the metal M2 used in the metal filling step.
Specifically, when copper (Cu) is used as the metal M2 in the metal filling step, examples of the metal M1 used in the above-mentioned barrier layer removing step include Zn, Fe, Ni, Sn, and the like. , Zn, Ni is preferably used, and Zn is more preferably used.
When Ni is used as the metal M2 in the metal filling step, examples of the metal M1 used in the barrier layer removing step described above include Zn and Fe, and among them, Zn is preferably used.

The method of removing the barrier layer using such an alkaline aqueous solution containing the ions of the metal M1 is not particularly limited, and examples thereof include the same methods as those of the conventionally known chemical etching treatment.

<Chemical etching process>
To remove the barrier layer by chemical etching treatment, for example, the structure after the anodization treatment step is immersed in an alkaline aqueous solution, the inside of the through hole is filled with the alkaline aqueous solution, and then the opening side of the through hole of the anodized film is formed. Only the barrier layer can be selectively dissolved by a method of contacting the surface of the solution with a pH (hydrogen ion index) buffer solution or the like.

Here, as the alkaline aqueous solution containing the ions of the metal M1 described above, it is preferable to use at least one alkaline aqueous solution selected from the group consisting of sodium hydroxide, potassium hydroxide and lithium hydroxide. The concentration of the alkaline aqueous solution is preferably 0.1 to 5% by mass. The temperature of the alkaline aqueous solution is preferably 10 to 60 ° C, more preferably 15 to 45 ° C, and further preferably 20 to 35 ° C.
Specifically, for example, 50 g / L, 40 ° C. phosphoric acid aqueous solution, 0.5 g / L, 30 ° C. sodium hydroxide aqueous solution, 0.5 g / L, 30 ° C. potassium hydroxide aqueous solution and the like are preferably used. Be done.
As the pH buffer solution, a buffer solution corresponding to the above-mentioned alkaline aqueous solution can be appropriately used.

The immersion time in the alkaline aqueous solution is preferably 5 to 120 minutes, more preferably 8 to 120 minutes, further preferably 8 to 90 minutes, and preferably 10 to 90 minutes. Especially preferable. Of these, 10 to 60 minutes is preferable, and 15 to 60 minutes is more preferable.

[Other examples of barrier layer removal process]
In addition to the above, the barrier layer removing step may be a step of removing the barrier layer of the anodic oxide film and exposing a part of the aluminum substrate to the bottom of the through hole.
In this case, the method for removing the barrier layer is not particularly limited, and for example, a method for electrochemically dissolving the barrier layer at a potential lower than the potential in the anodic treatment in the anodic oxidation treatment step (hereinafter, "electrolytic removal treatment"". (Also also referred to as); a method of removing the barrier layer by etching (hereinafter, also referred to as “etching removal treatment”); a method combining these (particularly, after performing an electrolytic removal treatment, the remaining barrier layer is subjected to an etching removal treatment. Method of removing with); etc.

<Electrolytic removal treatment>
The electrolytic removal treatment is not particularly limited as long as it is an electrolytic treatment performed at a potential lower than the potential (electrolytic potential) in the anodic oxidation treatment in the anodic oxidation treatment step.
The electrolytic dissolution treatment can be performed continuously with the anodic oxidation treatment, for example, by lowering the electrolytic potential at the end of the anodic oxidation treatment step.

For the electrolytic removal treatment, the same electrolytic solution and treatment conditions as those of the conventionally known anodic oxidation treatment described above can be adopted except for the conditions other than the electrolytic potential.
In particular, when the electrolytic removal treatment and the anodic oxidation treatment are continuously performed as described above, it is preferable to perform the treatment using the same electrolytic solution.

(Electrolytic potential)
The electrolytic potential in the electrolytic removal treatment is preferably lowered continuously or stepwise (step-like) to a potential lower than the electrolytic potential in the anodic oxidation treatment.
Here, the reduction width (step width) when the electrolytic potential is gradually lowered is preferably 10 V or less, more preferably 5 V or less, and 2 V or less from the viewpoint of the withstand voltage of the barrier layer. It is more preferable to have.
Further, the voltage drop rate when the electrolytic potential is continuously or stepwise lowered is preferably 1 V / sec or less, more preferably 0.5 V / sec or less, and 0.2 V / sec, from the viewpoint of productivity and the like. Seconds or less is more preferable.

<Etching removal process>
The etching removal treatment is not particularly limited, but may be a chemical etching treatment that dissolves using an acid aqueous solution or an alkaline aqueous solution, or may be a dry etching treatment.

(Chemical etching process)
To remove the barrier layer by chemical etching treatment, for example, the structure after the anodic oxidation treatment step is immersed in an acid aqueous solution or an alkaline aqueous solution, the inside of the micropore is filled with the acid aqueous solution or the alkaline aqueous solution, and then the anodic oxide film is removed. A method of contacting the surface of the micropore on the opening side with a pH (hydrogen ion index) buffer solution or the like can selectively dissolve only the barrier layer.

Here, when an aqueous acid solution is used, it is preferable to use an aqueous solution of an inorganic acid such as sulfuric acid, phosphoric acid, nitric acid, or hydrochloric acid, or a mixture thereof. The concentration of the aqueous acid solution is preferably 1% by mass to 10% by mass. The temperature of the aqueous acid solution is preferably 15 ° C to 80 ° C, more preferably 20 ° C to 60 ° C, and further preferably 30 ° C to 50 ° C.
On the other hand, when an alkaline aqueous solution is used, it is preferable to use at least one alkaline aqueous solution selected from the group consisting of sodium hydroxide, potassium hydroxide and lithium hydroxide. The concentration of the alkaline aqueous solution is preferably 0.1% by mass to 5% by mass. The temperature of the alkaline aqueous solution is preferably 10 ° C. to 60 ° C., more preferably 15 ° C. to 45 ° C., and further preferably 20 ° C. to 35 ° C. The alkaline aqueous solution may contain zinc and other metals.
Specifically, for example, 50 g / L, 40 ° C. phosphoric acid aqueous solution, 0.5 g / L, 30 ° C. sodium hydroxide aqueous solution, 0.5 g / L, 30 ° C. potassium hydroxide aqueous solution and the like are preferably used. Be done.
As the pH buffer solution, a buffer solution corresponding to the above-mentioned acid aqueous solution or alkaline aqueous solution can be appropriately used.

The immersion time in the acid aqueous solution or the alkaline aqueous solution is preferably 8 minutes to 120 minutes, more preferably 10 minutes to 90 minutes, and further preferably 15 minutes to 60 minutes.

(Dry etching process)
For the dry etching treatment, it is preferable to use a gas type such as _{Cl 2 / Ar mixed gas.}

[Metal filling process]
The metal filling step is a step of filling the inside of the through holes in the anodic oxide film with metal M2 by using electrolytic plating after the barrier layer removing step described above.
Here, FIG. 13 is a schematic view showing an electroplating apparatus used in the metal filling step among the methods for manufacturing a metal-filled microstructure according to the embodiment of the present invention, and FIG. 14 is a schematic view showing the metal filling according to the embodiment of the present invention. It is a flowchart which shows the metal filling process among the manufacturing methods of a microstructure.

The electrolytic plating apparatus 30 shown in FIG. 13 includes a plating tank 32, a counter electrode 34, a power supply unit 36, and a control unit 38. The above-mentioned structure 17 is arranged in the plating tank 32 so as to face the counter electrode 34. Further, the plating tank 32 is filled with the plating solution AQ, and the structure 17 and the counter electrode 34 are immersed. As described above, the structure 17 is an anodized film 14 having a plurality of through holes 12, that is, an insulating base material having a plurality of through holes.
The power supply unit 36 is electrically connected to the structure 17 and the counter electrode 34, and applies a current to the structure 17.
The control unit 38 is connected to the power supply unit 36 and controls the power supply unit 36. The control unit 38 controls the current value, timing, and period of the current applied by the power supply unit 36. For example, a plurality of current patterns of the applied current are stored in the control unit 38, and a current is applied from the power supply unit 36 to the structure 17 in any of the current patterns.
The power supply unit 36 may be provided with the function of the control unit 38, and in this case, the control unit 38 is unnecessary. Further, the current pattern of the applied current is also referred to as a current control pattern.

The electrolytic plating apparatus 30 may have a structure having a vibrating portion 39. The vibrating portion 39 gives vibration to at least one of the structure 17 and the plating solution AQ. For example, vibration is applied during electrolytic plating.
The form of vibration by the vibrating unit 39 is not particularly limited, and various techniques can be applied as a method of giving vibration to an object. The easiest method is to apply ultrasonic vibration. In this case, the plating tank 32 itself may be used as an ultrasonic treatment tank, but a method of immersing the ultrasonic vibrator in the plating tank 32 is desirable.
As another method of giving vibration, there is a method of vibrating the structure 17, but there is a possibility that the distance between the electrodes may fluctuate. Further, as a method of applying vibration, a method of generating microbubbles in the plating tank 32 and spraying the microbubbles on the structure 17 may be used.

The structure 17 and the counter electrode 34 are arranged to face each other in the plating tank 32 shown in FIG. Then, the inside of the plating tank 32 is filled with the plating solution AQ.
The structure 17 is immersed in the plating solution for a time of more than 5 seconds without applying a voltage to the structure 17 from the power supply unit 36 (step S10). As a result, the cation is supplied from the plating solution into the through hole 12, and in the metal filling step, the unfilled portion in the through hole 12 and the filling defect in which voids remain inside are suppressed. Even when the area of the structure 17 is large, it is effective because cations can be supplied to all the through holes 12. The time exceeding 5 seconds does not include within 5 seconds.

The immersion time for immersing the structure 17 in the plating solution without applying a voltage is preferably 1 minute or more and 150 minutes or less. That is, if the pre-immersion immersion time is 1 minute or more and 150 minutes or less, the cation is supplied from the plating solution into the through hole 12, and voids remain in the unfilled portion in the through hole 12 and inside in the metal filling step. Poor filling is further suppressed.
The state in which no voltage is applied means that the structure 17 is immersed in the plating solution AQ and is not electrically connected to the power supply unit 36, or is electrically connected to the power supply unit. From 36, it means a state in which no current and voltage signals are applied to the structure 17. The state in which the above-mentioned current and voltage signals are not applied is realized by turning off the power supply unit 36. In addition, the state in which no voltage is applied includes a state in which no current or voltage is substantially applied, such as a sufficiently low voltage.

Next, a current is applied from the power supply unit 36 to the structure 17 based on the current pattern output from the control unit 38. In this case, electrolytic plating is performed by continuously or multi-stage increasing the current value (step S12), and the plurality of through holes 12 are filled with metal.
In the metal filling step, the number of times the electrolytic plating is set is predetermined (step S14). Repeat electrolytic plating until the set number of times is reached. The number of times of electrolytic plating is not particularly limited, and it may be performed at least once, or may be performed a plurality of times.

In step S12, the plating processing time indicating the time from the end of immersion in which no voltage is applied (when the end of immersion in a state where no voltage is applied) to the end of electrolytic plating is defined as T. The maximum value of the current applied in electrolytic plating is Im. At this time, the current value is set to less than 0.05 Im when it is less than 0.1 T, and then the current value is increased to the maximum value Im when it is less than 0.1 T. That is, the current value is set to less than 5% of the electrolytic current value while the plating processing time T is less than 10%. Then, during a time of less than 10% with respect to the plating processing time T, the current value is continuously or multi-staged to increase the current value to the electrolytic current value to increase the current value.
To continuously increase the current value means to increase the current value with the passage of the electrolysis time. In this case, the current value can be represented by a linear function, a higher-order function such as a quadratic function, a plurality of linear functions, or a combination of a linear function and a higher-order function. It is assumed that all of the above functions are increasing functions and have no inflection points.
Increasing the current value in multiple stages means increasing the current value in a stepwise manner as the electrolysis time increases. Therefore, when the current value is increased in multiple stages, there is a period in which the current value does not increase even after the electrolysis time elapses and the current value has a constant value.

The current value is not particularly limited as long as the current value is continuously or multistagely increased, and more specifically, the current patterns shown in FIGS. 15 to 22 are exemplified.
Here, FIGS. 15 to 22 are graphs showing an example of the current pattern of electrolytic plating in the metal filling step in the method for manufacturing the metal-filled microstructure according to the embodiment of the present invention. FIG. 16 shows an example of the rising portion of FIG. 18 to 20 show an example of the rising portion of FIG.

As shown in FIG. 15, the current pattern of electroplating in the metal filling step has a rising portion and a steady electrolytic portion. The plating processing time T, which indicates the time from the end of immersion to the end of electrolytic plating, is the total time of the rising portion and the steady electrolytic portion. When the rise time of the rise portion is Tu and the steady electrolysis time of the steady electrolysis section is Ts, T = Tu + Ts. The steady-state electrolysis unit indicates a region maintained at a predetermined electrolysis current value. The electrolytic current value of the steady electrolysis unit Ts is the maximum value of the current value of electroplating.

The rising portion is a region where the current value is increased, and as described above, for example, the current value is set to less than 0.05 Im during less than 0.1 T, and then the current value is set to less than 0.1 T up to the maximum value Im. Increase between.
Further, for example, as shown in FIG. 16, in the rising portion, the current value is set to less than 0.05 Im in the range of less than 0.1 T, the degree of increase is increased to increase the current value, and the degree of increase is further increased. The current value is increased to reach the electrolytic current value of the steady-state electrolysis unit, that is, the maximum value Im of the current value. At the rising portion, for example, the current value is increased in three stages with different degrees of increase. The current value is represented by three linear functions.
The pattern of increase in the current value is not limited to that shown in FIGS. 15 and 16, and may be the pattern shown in FIGS. 18 to 20. Also in the patterns shown in FIGS. 18 to 20, the current value is increased in three stages in which the degree of increase is different, and the degree of increase in the current value is increased as time elapses.

When the electroplating is carried out a plurality of times, the electroplating may be carried out continuously, or a period in which no current is applied may be provided between the electroplating. The period during which no current is applied is appropriately determined in consideration of the time required for the metal filling step and the like.
When electroplating is performed a plurality of times, for example, it is performed with the current pattern shown in FIG. Although it is repeated continuously in FIG. 21, it is not limited to this as described above. As shown in FIG. 22, it may be carried out in a current pattern having a period in which no current is applied.

<Metal M2>
Metal M2 described above, it is preferable that the electric resistivity is less material 10 ³ Ω · cm, and specific examples thereof include gold (Au), silver (Ag), copper (Cu), aluminum (Al), Magnesium (Mg), nickel (Ni), zinc (Zn) and the like are preferably exemplified.
Among them, from the viewpoint of electrical conductivity, Cu, Au, Al and Ni are preferable, Cu and Au are more preferable, and Cu is further preferable.

<Filling method>
An electrolytic plating method is used as a method of plating for filling the inside of the through hole with the metal M2 described above. In the electroless plating method, it takes a long time to completely fill the holes formed by the through holes having a high aspect with the metal.
Here, it is difficult to selectively deposit (grow) a metal in the pores with a high aspect ratio by a conventionally known electrolytic plating method used for coloring or the like. It is considered that this is because the precipitated metal is consumed in the pores and the plating does not grow even if electrolysis is performed for a certain period of time or longer.

Therefore, when the metal is filled by the electroplating method, it is necessary to allow a rest time during pulse electrolysis or constant potential electrolysis. The rest time is required to be 10 seconds or more, preferably 30 to 60 seconds.
It is also desirable to add ultrasonic waves to promote the agitation of the electrolyte.
Further, the electrolytic voltage is usually 20 V or less, preferably 10 V or less, but it is preferable to measure the precipitation potential of the target metal in the electrolytic solution to be used in advance and perform constant potential electrolysis within the potential + 1 V. When performing constant potential electrolysis, it is desirable that cyclic voltammetry can be used in combination, and potentiometer devices such as Solartron, BAS, Hokuto Denko, and IVIUM can be used.

(Plating liquid)
The plating solution contains metal ions, and a conventionally known plating solution is used depending on the metal to be filled. As the plating solution, the main component of the solid content is preferably copper sulfate, and for example, a mixed aqueous solution of copper sulfate, sulfuric acid, and hydrochloric acid is used. Specifically, an aqueous solution of copper sulfate is generally used for precipitating copper, but the concentration of copper sulfate is preferably 1 to 300 g / L, more preferably 100 to 200 g / L. preferable. Further, the precipitation can be promoted by adding hydrochloric acid to the plating solution. In this case, the hydrochloric acid concentration is preferably 10 to 20 g / L.
The main component of the solid content is that the proportion of the electrolytic solution in the solid content is 20% by mass or more. For example, copper sulfate is contained in the solid content of the electrolytic solution in an amount of 20% by mass or more. That is.
When depositing gold, it is desirable to use a sulfuric acid solution of tetrachloroauric acid and perform plating by AC electrolysis.

The plating solution preferably contains a surfactant.
Known surfactants can be used. Sodium lauryl sulfate, which is conventionally known as a surfactant to be added to the plating solution, can be used as it is. Both ionic (cationic / anionic / bimodal) and nonionic (nonionic) hydrophilic parts can be used, but the point of avoiding the generation of bubbles on the surface of the object to be plated. A cation ray activator is desirable. The concentration of the surfactant in the plating solution composition is preferably 1% by mass or less.

[Substrate removal process]
The substrate removing step is a step of removing the above-mentioned aluminum substrate after the metal filling step. The method for removing the aluminum substrate is not particularly limited, and for example, a method for removing by melting is preferable.

<Melting aluminum substrate>
For the above-mentioned dissolution of the aluminum substrate, it is preferable to use a treatment liquid that is difficult to dissolve the anodized film and easily dissolves aluminum.
Such a treatment liquid preferably has a dissolution rate in aluminum of 1 μm / min or more, more preferably 3 μm / min or more, and further preferably 5 μm / min or more. Similarly, the dissolution rate for the anodized film is preferably 0.1 nm / min or less, more preferably 0.05 nm / min or less, and even more preferably 0.01 nm / min or less.
Specifically, it is preferably a treatment liquid containing at least one metal compound having a lower ionization tendency than aluminum and having a pH of 4 or less or 8 or more, and the pH is 3 or less or 9 or more. Is more preferable, and 2 or less or 10 or more is further preferable.

The treatment liquid for dissolving aluminum is based on an acid or alkaline aqueous solution, for example, manganese, zinc, chromium, iron, cadmium, cobalt, nickel, tin, lead, antimony, bismuth, copper, mercury, silver, palladium, platinum. , A gold compound (for example, chloroplatinic acid), these fluorides, these chlorides and the like are preferably blended.
Of these, an acid aqueous solution base is preferable, and a chloride blend is preferable.
In particular, a treatment liquid obtained by blending a hydrochloric acid aqueous solution with mercury chloride (hydrochloric acid / mercury chloride) and a treatment liquid obtained by blending a hydrochloric acid aqueous solution with copper chloride (hydrochloric acid / copper chloride) are preferable from the viewpoint of treatment latitude.
The composition of the treatment liquid that dissolves aluminum is not particularly limited, and for example, a bromine / methanol mixture, a bromine / ethanol mixture, aqua regia, or the like can be used.

The acid or alkali concentration of the treatment liquid that dissolves aluminum is preferably 0.01 to 10 mol / L, more preferably 0.05 to 5 mol / L.
Further, the treatment temperature using the treatment liquid for dissolving aluminum is preferably −10 ° C. to 80 ° C., preferably 0 ° C. to 60 ° C.

Further, the above-mentioned melting of the aluminum substrate is performed by bringing the aluminum substrate after the above-mentioned metal filling step into contact with the above-mentioned treatment liquid. The contact method is not particularly limited, and examples thereof include a dipping method and a spraying method. Above all, the dipping method is preferable. The contact time at this time is preferably 10 seconds to 5 hours, more preferably 1 minute to 3 hours.

[Metal protrusion process]
For the reason that the metal bondability of the metal-filled microstructure to be produced is improved, it is possible to have at least one of the front surface metal projecting step and the back surface metal projecting step as in the second aspect described above. preferable.
Here, the surface metal projecting step is the thickness direction of the surface of the anodized film on the side where the aluminum substrate is not provided, after the metal filling step and before the substrate removing step. This is a step of projecting the above-mentioned metal M2 filled in the above-mentioned metal filling step from the surface of the above-mentioned anodic oxide film by partially removing the metal.
Further, in the back surface metal projecting step, after the above-mentioned substrate removing step, a part of the surface of the above-mentioned anodic oxide film on the side where the above-mentioned aluminum substrate is provided is removed in the thickness direction, and the above-mentioned metal filling step is performed. This is a step of projecting the filled metal M2 from the surface of the anodized film.

Partial removal of the anodic oxide film in the metal projecting step does not dissolve the above-mentioned metal M1 and metal M2 (particularly metal M2), but for the anodic oxide film, that is, an acid aqueous solution or an alkaline aqueous solution that dissolves aluminum oxide. This can be done by bringing an anodic oxide film having through holes filled with metal into contact with each other. The contact method is not particularly limited, and examples thereof include a dipping method and a spraying method. Above all, the dipping method is preferable.

When an aqueous acid solution is used, it is preferable to use an aqueous solution of an inorganic acid such as sulfuric acid, phosphoric acid, nitric acid, or hydrochloric acid, or a mixture thereof. Above all, an aqueous solution containing no chromic acid is preferable because it is excellent in safety. The concentration of the aqueous acid solution is preferably 1 to 10% by mass. The temperature of the aqueous acid solution is preferably 25 to 60 ° C.
When an alkaline aqueous solution is used, it is preferable to use at least one alkaline aqueous solution selected from the group consisting of sodium hydroxide, potassium hydroxide and lithium hydroxide. The concentration of the alkaline aqueous solution is preferably 0.1 to 5% by mass. The temperature of the alkaline aqueous solution is preferably 20 to 35 ° C.
Specifically, for example, a 50 g / L, 40 ° C. phosphoric acid aqueous solution, a 0.5 g / L, 30 ° C. sodium hydroxide aqueous solution, or a 0.5 g / L, 30 ° C. potassium hydroxide aqueous solution is preferably used. ..
The immersion time in the acid aqueous solution or the alkaline aqueous solution is preferably 8 to 120 minutes, more preferably 10 to 90 minutes, and further preferably 15 to 60 minutes. Here, the immersion time means the total of each immersion time when the immersion treatment for a short time is repeated. A cleaning treatment may be performed between the immersion treatments.

Further, the above-mentioned front surface metal projecting step and back surface metal projecting are performed because the pressure-bonding property with an object to be adhered such as a wiring substrate is improved when the produced metal-filled microstructure is used as an anisotropic conductive member. Of the steps, at least one step is preferably a step of projecting the above-mentioned metal M2 from the surface of the above-mentioned anodic oxide film by 10 to 1000 nm, and more preferably a step of projecting the above-mentioned metal M2 by 50 to 500 nm.

Further, when the metal-filled microstructure to be produced and the electrode are connected (joined) by a method such as crimping, the above-mentioned surface can be sufficiently secured in the surface direction when the protruding portion is crushed. Of the metal protrusion step and the back surface metal protrusion step, the aspect ratio (height of the protrusion / diameter of the protrusion) of the protrusion formed by at least one step is preferably 0.01 or more and less than 20. It is preferably ~ 20.

The conduction path made of metal formed by the above-mentioned metal filling step, substrate removing step, and arbitrary metal projecting step is preferably columnar, and its diameter is preferably more than 5 nm and 10 μm or less, and 40 nm to 1000 nm. Is more preferable.

Further, the above-mentioned conduction paths exist in a state of being insulated from each other by an anodic oxide film of an aluminum substrate, and the density thereof ^{is preferably 20,000 pieces / mm 2} or more, preferably 2 million pieces / mm. more preferably ² or more, and more preferably, especially preferably at 50 million / mm ² or more, and most preferably 100 million / mm ² or more and 10,000,000 / mm ² or more ..

Further, the distance between the centers of the adjacent conduction paths is preferably 20 nm to 500 nm, more preferably 40 nm to 200 nm, and further preferably 50 nm to 140 nm.

[Resin layer forming process]
It is preferable to have a resin layer forming step as shown in the above-mentioned third aspect and FIG. 3 for the reason that the transportability of the produced metal-filled microstructure is improved.
Here, the resin layer forming step is after the above-mentioned metal filling step (after the above-mentioned surface metal projecting step if the above-mentioned surface metal projecting step is provided) and before the above-mentioned substrate removing step. This is a step of providing a resin layer on the surface of the above-mentioned anodized film on the side where the above-mentioned aluminum substrate is not provided.

Specific examples of the resin material constituting the above-mentioned resin layer include ethylene-based copolymers, polyamide resins, polyester resins, polyurethane resins, polyolefin-based resins, acrylic resins, and cellulose-based resins. However, from the viewpoint of transportability and ease of use as an anisotropic conductive member, the above-mentioned resin layer is preferably a film with a peelable adhesive layer, and is adhered by heat treatment or ultraviolet exposure treatment. It is more preferable that the film has an adhesive layer that has weakened properties and can be peeled off.

The above-mentioned film with an adhesive layer is not particularly limited, and examples thereof include a heat-peeling type resin layer and an ultraviolet (ultraviolet) peeling type resin layer.
Here, the heat-peeling type resin layer has adhesive strength at room temperature and can be easily peeled off only by heating, and most of them mainly use effervescent microcapsules or the like.
Specific examples of the adhesive constituting the adhesive layer include a rubber adhesive, an acrylic adhesive, a vinyl alkyl ether adhesive, a silicone adhesive, a polyester adhesive, and a polyamide adhesive. , Urethane-based pressure-sensitive adhesives, styrene-diene block copolymer-based pressure-sensitive adhesives, and the like.

Further, the UV peeling type resin layer has a UV curable adhesive layer, and the adhesive strength is lost by curing so that the resin layer can be peeled off.
Examples of the UV curable adhesive layer include a polymer in which a carbon-carbon double bond is introduced into the polymer side chain or the main chain or at the end of the main chain as the base polymer. As the base polymer having a carbon-carbon double bond, it is preferable to use an acrylic polymer as a basic skeleton.
Further, since the acrylic polymer is crosslinked, a polyfunctional monomer or the like can be included as a monomer component for copolymerization, if necessary.
The base polymer having a carbon-carbon double bond can be used alone, but UV curable monomers or oligomers can also be blended.
It is preferable to use a photopolymerization initiator in combination with the UV curable adhesive layer in order to cure it by UV irradiation. Photopolymerization initiators include benzoin ether compounds; ketal compounds; aromatic sulfonyl chloride compounds; photoactive oxime compounds; benzophenone compounds; thioxanthone compounds; camphorquinone; halogenated ketones; acylphosphinoxides; acyls. Phosphonate and the like can be mentioned.

Examples of commercially available heat-release type resin layers include Intellimar [registered trademark] tapes (manufactured by Nitta Corporation) such as WS5130C02 and WS5130C10; Somatac [registered trademark] TE series (manufactured by SOMAR Corporation); 3198, No. 3198LS, No. 3198M, No. 3198MS, No. 3198H, No. 3195, No. 3196, No. 3195M, No. 3195MS, No. 3195H, No. 3195HS, No. 3195V, No. 3195VS, No. 319Y-4L, No. 319Y-4LS, No. 319Y-4M, No. 319Y-4MS, No. 319Y-4H, No. 319Y-4HS, No. 319Y-4LSC, No. 31935MS, No. 31935HS, No. 3193M, No. Riva Alpha [registered trademark] series (manufactured by Nitto Denko KK) such as 3193MS; etc.

Commercially available products of the UV peeling type resin layer include, for example, ELP holders such as ELP DU-300, ELP DU-2385KS, ELP DU-2187G, ELP NBD-3190K, ELP UE-2091J [registered trademark] (Nitto Denko). (Made by Lintec Corporation); Adwill D-210, Adwill D-203, Adwill D-202, Adwill D-175, Adwill D-675 (all manufactured by Lintec Corporation); Sumilite (registered trademark) FLS N8000 series (Sumitomo Bakelite) UC353EP-110 (Furukawa Electric Co., Ltd.); etc. Dicing tape, ELP RF-7232DB, ELP UB-5133D (all manufactured by Nitto Denko Corporation); SP-575B-150, SP-541B Back grind tapes such as -205, SP-537T-160, SP-537T-230 (all manufactured by Furukawa Electric Co., Ltd.) can be used.

Further, the method of attaching the above-mentioned film with an adhesive layer is not particularly limited, and the film can be attached using a conventionally known surface protective tape affixing device and a laminator.

[Winding process]
For the reason that the transportability of the metal-filled microstructure to be produced is further improved, a winding step of winding the metal-filled microstructure into a roll shape with the above-mentioned resin layer after the above-mentioned arbitrary resin layer forming step. It is preferable to have.
Here, the winding method in the above-mentioned winding step is not particularly limited, and for example, as shown in FIG. 4, a method of winding on a winding core 21 (see FIG. 11) having a predetermined diameter and a predetermined width can be mentioned.

Further, from the viewpoint of ease of winding in the above-mentioned winding step, the average thickness of the metal-filled microstructure excluding the resin layer 19 (see FIG. 12) is preferably 30 μm or less, preferably 5 to 20 μm. More preferred. The average thickness was measured at 10 points by cutting a metal-filled microstructure excluding the resin layer with FIB in the thickness direction and taking a surface photograph (magnification of 50,000 times) of the cross section by FE-SEM. It can be calculated by using an average value or the like.

[Other processing processes]
In addition to the above-mentioned steps, the production method of the present invention includes a polishing step, a surface smoothing step, a protective film forming treatment, and a water washing treatment described in paragraphs <0049> to <0057> of International Publication No. 2015/029881. You may have.
Further, from the viewpoint of manufacturing handleability and the use of the metal-filled microstructure as the anisotropic conductive member, various processes and types as shown below can be applied.

<Process example using temporary adhesive>
In the present invention, after the metal-filled microstructure is obtained by the above-mentioned substrate removing step, the metal-filled microstructure is fixed on a silicon wafer using temporary bonding materials and thinned by polishing. It may have a step to do.
Then, after the step of thinning the layer, after thoroughly cleaning the surface, the above-mentioned surface metal projecting step can be performed.
Next, a temporary adhesive having a stronger adhesive force than the previous temporary adhesive is applied to the surface on which the metal is projected and fixed on the silicon wafer, and then the silicon wafer bonded with the previous temporary adhesive is peeled off. Then, the above-mentioned back surface metal projecting step can be performed on the surface of the peeled metal-filled microstructure side.

<Example of process using wax>
The present invention has a step of obtaining a metal-filled microstructure by the above-mentioned substrate removing step, fixing the metal-filled microstructure on a silicon wafer with wax, and thinning the layer by polishing. May be good.
Then, after the step of thinning the layer, after thoroughly cleaning the surface, the above-mentioned surface metal projecting step can be performed.
Next, a temporary adhesive is applied to the surface on which the metal is projected and fixed on the silicon wafer, and then the wax is melted by heating to peel off the silicon wafer, and the surface on the side of the peeled metal-filled microstructure is peeled off. On the other hand, the above-mentioned back surface metal projecting step can be performed.
Although solid wax may be used, liquid wax such as Skycoat (manufactured by Nikka Seiko Co., Ltd.) can be used to improve the uniformity of coating thickness.

<Example of process for removing the substrate later>
In the present invention, after the metal filling step described above and before the substrate removing step described above, the aluminum substrate is subjected to a rigid substrate (for example, a silicon wafer, a glass substrate) using a temporary adhesive, wax or a functional adsorption film. Etc.), and then the surface of the above-mentioned anodic oxide film on the side where the above-mentioned aluminum substrate is not provided may be thinned by polishing.
Then, after the step of thinning the layer, after thoroughly cleaning the surface, the above-mentioned surface metal projecting step can be performed.
Next, a resin material (for example, epoxy resin, polyimide resin, etc.), which is an insulating material, is applied to the surface on which the metal is projected, and then a rigid substrate can be attached to the surface by the same method as described above. For sticking with a resin material, select one whose adhesive strength is greater than the adhesive strength with a temporary adhesive or the like, and after sticking with a resin material, peel off the rigid substrate pasted first, and then peel off the above-mentioned substrate. It can be performed by sequentially performing the removal step, the polishing step, and the back surface metal protrusion treatment step.
As the functional adsorption film, Q-chuck (registered trademark) (manufactured by Maruishi Sangyo Co., Ltd.) or the like can be used.

In the present invention, it is preferable that the metal-filled microstructure is provided as a product in a state of being attached to a rigid substrate (for example, a silicon wafer, a glass substrate, etc.) by a peelable layer.
In such a supply form, when the metal-filled microstructure is used as a joining member, the surface of the metal-filled microstructure is temporarily adhered to the device surface, the rigid substrate is peeled off, and then the device to be connected is attached. The upper and lower devices can be joined by a metal-filled microstructure by installing in an appropriate place and heat-pressing.
Further, as the peelable layer, a heat peeling layer may be used, or a light peeling layer may be used in combination with a glass substrate.

In addition, each of the above-mentioned steps can be performed on a single sheet, or can be continuously processed on a web using an aluminum coil as a raw material.
Further, in the case of continuous treatment, it is preferable to set an appropriate cleaning step and drying step between each step.

By the manufacturing method having each of the above-mentioned treatment steps, a metal-filled microstructure in which a metal is filled inside a through hole derived from a through hole provided in an insulating base material made of an anodized film of an aluminum substrate can be obtained. ..
Specifically, by the above-mentioned production method, for example, in the anisotropic conductive member described in Japanese Patent Application Laid-Open No. 2008-270158, that is, in an insulating base material (anodized film of an aluminum substrate having through holes). , A plurality of conduction paths made of conductive members (metals) penetrate the above-mentioned insulating base material in the thickness direction in a state of being insulated from each other, and one end of each of the above-mentioned conduction paths is the above-mentioned insulating base material. It is possible to obtain an anisotropic conductive member which is exposed on one surface and is provided in a state where the other end of each of the above-mentioned conduction paths is exposed on the other surface of the above-mentioned insulating base material.

Hereinafter, an example of the metal-filled microstructure 20 manufactured by the above-mentioned manufacturing method will be described. FIG. 23 is a plan view showing an example of the metal-filled microstructure according to the embodiment of the present invention, and FIG. 24 is a schematic cross-sectional view showing an example of the metal-filled microstructure according to the embodiment of the present invention. FIG. 24 is a cross-sectional view taken along the line IB-IB of FIG. 23. Further, FIG. 25 is a schematic cross-sectional view showing an example of the configuration of the anisotropic conductive material using the metal-filled microstructure of the embodiment of the present invention.

As shown in FIGS. 23 and 24, the metal-filled microstructure 20 manufactured as described above has, for example, an insulating base material 40 made of an anodic oxide film of aluminum and a thickness direction of the insulating base material 40. It is a member provided with a plurality of conduction paths 16 that penetrate Dt (see FIG. 24) and are provided in a state of being electrically insulated from each other. The metal-filled microstructure 20 further includes a resin layer 44 provided on the front surface 40a and the back surface 40b of the insulating base material 40.
Here, the "state of being electrically insulated from each other" means that the conduction paths existing inside the insulating base material have sufficiently low conductivity between the conduction paths inside the insulating base material. It means that it is in a state.
In the metal-filled microstructure 20, the conductive paths 16 are electrically insulated from each other, and the conductivity is sufficiently low in the direction x orthogonal to the thickness direction Dt (see FIG. 24) of the insulating base material 40, and the thickness is high. It has conductivity in the direction Dt (see FIG. 24). As described above, the metal-filled microstructure 20 is a member exhibiting anisotropic conductivity. For example, the metal-filled microstructure 20 is arranged so that the thickness direction Dt (see FIG. 24) coincides with the stacking direction Ds of the stacking device 60.

As shown in FIGS. 23 and 24, the conduction path 16 is provided so as to penetrate the insulating base material 40 in the thickness direction Dt in a state of being electrically insulated from each other.
Further, as shown in FIG. 24, the conduction path 16 may have a protruding portion 16a and a protruding portion 16b protruding from the front surface 40a and the back surface 40b of the insulating base material 40. The metal-filled microstructure 20 may further include a resin layer 44 provided on the front surface 40a and the back surface 40b of the insulating base material 40. The resin layer 44 has adhesiveness and also imparts bondability. The length of the protruding portion 16a and the protruding portion 16b is preferably 6 nm or more, and more preferably 30 nm to 500 nm.

Further, in FIGS. 25 and 24, those having the resin layer 44 on the front surface 40a and the back surface 40b of the insulating base material 40 are shown, but the present invention is not limited to this, and at least the insulating base material 40 is at least. A resin layer 44 may be provided on one surface.
Similarly, the conduction passages 16 of FIGS. 25 and 24 have projecting portions 16a and projecting portions 16b at both ends, but the present invention is not limited to these, and the surface of the insulating base material 40 on the side having at least the resin layer 44. It may be configured to have a protruding portion.

The thickness h of the metal-filled microstructure 20 shown in FIG. 24 is, for example, 30 μm or less. Further, the metal-filled microstructure 20 preferably has a TTV (Total Thickness Variation) of 10 μm or less.
Here, the thickness h of the metal-filled microstructure 20 is obtained by observing the metal-filled microstructure 20 with an electrolytic discharge scanning electron microscope at a magnification of 200,000 times to obtain the contour shape of the metal-filled microstructure 20. It is an average value measured at 10 points in the region corresponding to the thickness h.
Further, the TTV (Total Thickness Variation) of the metal-filled microstructure 20 is a value obtained by cutting the metal-filled microstructure 20 together with the support 46 by dicing and observing the cross-sectional shape of the metal-filled microstructure 20. is there.

The metal-filled microstructure 20 is provided on the support 46 as shown in FIG. 25 for transfer, transport, transport, storage and the like. A release layer 47 is provided between the support 46 and the metal-filled microstructure 20. The support 46 and the metal-filled microstructure 20 are separably bonded by a release layer 47. As described above, the metal-filled microstructure 20 provided on the support 46 via the release layer 47 is referred to as an anisotropic conductive material 50.
The support 46 supports the metal-filled microstructure 20, and is made of, for example, a silicon substrate. As the support 46, in addition to the silicon substrate, for example, _{a ceramic substrate such as SiC, SiC, GaN and alumina (Al 2} O ₃ ), a glass substrate, a fiber reinforced plastic substrate, and a metal substrate can be used. The fiber reinforced plastic substrate also includes a FR-4 (Flame Retardant Type 4) substrate, which is a printed wiring board.

Further, as the support 46, one having flexibility and being transparent can be used. Examples of the flexible and transparent support 46 include PET (polyethylene terephthalate), polycycloolefin, polycarbonate, acrylic resin, PEN (polyethylene naphthalate), PE (polyethylene), PP (polypropylene), and the like. Examples thereof include plastic films such as polypropylene, polyvinyl chloride, polyvinylidene chloride and TAC (triacetyl cellulose).
Here, "transparency" means that the light having a wavelength used for alignment has a transmittance of 80% or more. Therefore, the transmittance may be low in the entire visible light range of the wavelength of 400 to 800 nm, but the transmittance is preferably 80% or more in the entire visible light range of the wavelength of 400 to 800 nm. The transmittance is measured by a spectrophotometer.

The release layer 47 is preferably a laminate of the support layer 48 and the release agent 49. The release agent 49 is in contact with the metal-filled microstructure 20, and the support 46 and the metal-filled microstructure 20 are separated from each other starting from the release layer 47. In the anisotropic conductive material 50, for example, by heating to a predetermined temperature, the adhesive force of the release agent 49 is weakened, and the support 46 is removed from the metal-filled microstructure 20.
As the release agent 49, for example, Riva Alpha (registered trademark) manufactured by Nitto Denko Corporation, Somatac (registered trademark) manufactured by Somar Corporation, or the like can be used.

Further, the resin layer 44 may be provided with a protective layer (not shown). Since the protective layer is used to protect the surface of the structure from scratches and the like, an easily peelable tape is preferable. As the protective layer, for example, a film with an adhesive layer may be used.
As a film with an adhesive layer, for example, SANYTECT [registered trademark] (manufactured by Sanei Kaken Co., Ltd.) in which an adhesive layer is formed on the surface of a polyethylene resin film, and an adhesive layer is formed on the surface of a polyethylene terephthalate resin film. E-MASK [registered trademark] (manufactured by Nitto Denko Co., Ltd.), Massac [registered trademark] (manufactured by Fujimori Kogyo Co., Ltd.) with an adhesive layer formed on the surface of the polyethylene terephthalate resin film, etc. Commercially available products can be used.
Further, the method of attaching the film with the adhesive layer is not particularly limited, and the film can be attached using a conventionally known surface protective tape affixing device and a laminator.

Hereinafter, the configuration of the metal-filled microstructure 20 will be described more specifically.
[Insulating base material]
The physical characteristics and composition of the insulating base material are as described above.
The thickness ht of the insulating base material 40 is preferably in the range of 1 to 1000 μm, more preferably in the range of 5 to 500 μm, and further preferably in the range of 10 to 300 μm. When the thickness of the insulating base material is within this range, the handleability of the insulating base material is improved.
The thickness ht of the insulating base material 40 is obtained by cutting the insulating base material 40 with a focused ion beam (FIB) in the thickness direction Dt and cutting a cross section thereof with a field emission scanning electron microscope 20. It is an average value obtained by observing at a magnification of 10,000 times, acquiring the contour shape of the insulating base material 40, and measuring 10 points in a region corresponding to the thickness ht.

The spacing between the through holes in the insulating substrate is preferably 5 nm to 800 nm, more preferably 10 nm to 200 nm, and even more preferably 50 nm to 140 nm. When the distance between the through holes in the insulating base material is within this range, the insulating base material sufficiently functions as an insulating partition wall. The spacing between the through holes is the same as the spacing between the conduction paths.
Here, the interval between the through holes, that is, the interval between the conduction paths means the width w between the adjacent conduction paths (see FIG. 24), and the cross section of the idiosyncratic conductive member is measured by a field emission scanning electron microscope 20. It is the average value measured at 10 points by observing at a magnification of 10,000 times and measuring the width between adjacent conduction paths.

[Conduction path]
The conduction path is made of metal. Specific examples of the metal are preferably gold (Au), silver (Ag), copper (Cu), aluminum (Al), magnesium (Mg), nickel (Ni) and the like. From the viewpoint of electrical conductivity, copper, gold, aluminum, and nickel are preferable, and copper and gold are more preferable.

<Protruding part>
When the anisotropic conductive member and the electrode are electrically connected or physically joined by a method such as crimping, the conductive path can be provided with sufficient insulation in the surface direction when the protruding portion is crushed. The aspect ratio of the protruding portion (height of the protruding portion / diameter of the protruding portion) is preferably 0.5 or more and less than 50, more preferably 0.8 to 20, and further preferably 1 to 10. preferable.

Further, from the viewpoint of following the surface shape of the semiconductor member to be connected, the height of the protruding portion of the conduction path is preferably 20 nm or more, more preferably 100 nm to 500 nm, as described above.
The height of the protruding portion of the conduction path is the average obtained by observing the cross section of the metal-filled microstructure with a field emission scanning electron microscope at a magnification of 20,000 times and measuring the height of the protruding portion of the conduction path at 10 points. The value.
The diameter of the protruding portion of the conduction path is an average value obtained by observing the cross section of the metal-filled microstructure with a field emission scanning electron microscope and measuring the diameter of the protruding portion of the conduction path at 10 points.

As described above, the conduction paths 16 exist in a state of being electrically insulated from each other by the insulating base material 40, but the density thereof ^{is preferably 20,000 / mm 2} or more, and 2 million. more preferably / mm ² or more, still more preferably 10,000,000 / mm ² or more, particularly preferably at 50 million / mm ² or more, 100 million / mm ² or more Most preferred.
Further, the distance p between the centers of the adjacent conduction paths 16 (see FIG. 2) is preferably 20 nm to 500 nm, more preferably 40 nm to 200 nm, and further preferably 50 nm to 140 nm.

[Resin layer]
As described above, the resin layer is provided on the front surface and the back surface of the insulating base material, and the protruding portion of the conduction path is embedded as described above. That is, the resin layer covers the end of the conduction path protruding from the insulating base material and protects the protruding portion.
The resin layer is formed by the above-mentioned resin layer forming step. The resin layer preferably exhibits fluidity in the temperature range of 50 ° C. to 200 ° C. and cures at 200 ° C. or higher.
The resin layer is formed by the above-mentioned resin layer forming step, but the composition of the resin agent shown below can also be used. Hereinafter, the composition of the resin layer will be described. The resin layer contains a polymer material. The resin layer may contain an antioxidant material.

<Polymer material>
The polymer material contained in the resin layer is not particularly limited, but the gap between the semiconductor chip or the semiconductor wafer and the anisotropic conductive member can be efficiently filled, and the adhesion to the semiconductor chip or the semiconductor wafer is further improved. For this reason, it is preferably a thermosetting resin.
Specific examples of the thermosetting resin include epoxy resin, phenol resin, polyimide resin, polyester resin, polyurethane resin, bismaleimide resin, melamine resin, isocyanate resin and the like.
Of these, a polyimide resin and / or an epoxy resin is preferably used because the insulation reliability is further improved and the chemical resistance is excellent.

<Antioxidant material>
Specific examples of the antioxidant material contained in the resin layer include 1,2,3,4-tetrazole, 5-amino-1,2,3,4-tetrazole, 5-methyl-1,2, 3,4-tetrazole, 1H-tetrazol-5-acetic acid, 1H-tetrazole-5-succinic acid, 1,2,3-triazole, 4-amino-1,2,3-triazole, 4,5-diamino-1 , 2,3-Triazole, 4-carboxy-1H-1,2,3-Triazole, 4,5-Dicarboxy-1H-1,2,3-Triazole, 1H-1,2,3-Triazole-4- Acetic acid, 4-carboxy-5-carboxymethyl-1H-1,2,3-triazole, 1,2,4-triazole, 3-amino-1,2,4-triazole, 3,5-diamino-1,2 , 4-Triazole, 3-carboxy-1,2,4-Triazole, 3,5-dicarboxy-1,2,4-Triazole, 1,2,4-Triazole-3-acetic acid, 1H-benzotriazole, 1H -Benzotriazole-5-carboxylic acid, benzofloxane, 2,1,3-benzothiazole, o-phenylenediamine, m-phenylenediamine, catechol, o-aminophenol, 2-mercaptobenzothiazole, 2-mercaptobenzoimidazole , 2-Mercaptobenzoxazole, melamine, and derivatives thereof.
Of these, benzotriazole and its derivatives are preferred.
Examples of the benzotriazole derivative include a hydroxyl group, an alkoxy group (for example, methoxy group, ethoxy group, etc.), an amino group, a nitro group, and an alkyl group (for example, a methyl group, an ethyl group, a butyl group, etc.) on the benzene ring of benzotriazole. , Substituted benzotriazole having a halogen atom (for example, fluorine, chlorine, bromine, iodine, etc.) and the like. Moreover, the substituted naphthalene triazole, the substituted naphthalene bistriazole and the like which have been substituted in the same manner as naphthalene triazole and naphthalene bistriazole can also be mentioned.

In addition, as another example of the antioxidant material contained in the resin layer, general antioxidants such as higher fatty acids, higher fatty acid copper, phenol compounds, alkanolamines, hydroquinones, copper chelating agents, organic amines, and organic substances are used. Examples include ammonium salts.

The content of the antioxidant material contained in the resin layer is not particularly limited, but from the viewpoint of the anticorrosion effect, 0.0001% by mass or more is preferable, and 0.001% by mass or more is more preferable with respect to the total mass of the resin layer. Further, 5.0% by mass or less is preferable, and 2.5% by mass or less is more preferable, for the reason of obtaining an appropriate electric resistance in this joining process.

<Migration prevention material>
The resin layer contains a migration prevention material for the reason that the insulation reliability is further improved by trapping the metal ions and halogen ions that can be contained in the resin layer and the metal ions derived from the semiconductor chip and the semiconductor wafer. Is preferable.

As the migration prevention material, for example, an ion exchanger, specifically, a mixture of a cation exchanger and an anion exchanger, or only a cation exchanger can be used.
Here, the cation exchanger and the anion exchanger can be appropriately selected from, for example, the inorganic ion exchanger and the organic ion exchanger described later, respectively.

(Inorganic ion exchanger)
Examples of the inorganic ion exchanger include hydrous oxides of metals typified by zirconium hydroxide.
As the type of metal, for example, in addition to zirconium, iron, aluminum, tin, titanium, antimony, magnesium, beryllium, indium, chromium, bismuth and the like are known.
Of these, the zirconium-based one has the ability to exchange ^{the cations Cu 2+} and Al ^3+. In addition, iron-based products also have exchangeability for ^{Ag +} and Cu ^2+.
Similarly, tin-based, titanium-based, and antimony-based ones are cation exchangers.
On the other hand, those of bismuth-based, anion Cl ^- has exchange capacity for.
In addition, zirconium-based products show anion exchange ability depending on the manufacturing conditions. The same applies to aluminum-based and tin-based ones.
As other inorganic ion exchangers, compounds such as acid salts of polyvalent metals typified by zirconium phosphate, heteropolylates typified by ammonium molybdrinate, and insoluble ferrocyanides are known.
Some of these inorganic ion exchangers are already on the market, and for example, various grades under the trade name IXE of Toagosei Co., Ltd. are known.
In addition to synthetic products, natural zeolite or powder of an inorganic ion exchanger such as montmorillonite can also be used.

(Organic ion exchanger)
Examples of the organic ion exchanger include crosslinked polystyrene having a sulfonic acid group as a cation exchanger, and those having a carboxylic acid group, a phosphonic acid group or a phosphinic acid group.
Examples of the anion exchanger include crosslinked polystyrene having a quaternary ammonium group, a quaternary phosphonium group or a tertiary sulfonium group.

These inorganic ion exchangers and organic ion exchangers may be appropriately selected in consideration of the types of cations and anions to be captured and the exchange capacity for the ions. Of course, it goes without saying that the inorganic ion exchanger and the organic ion exchanger may be mixed and used.
Since the manufacturing process of the electronic device includes a heating process, an inorganic ion exchanger is preferable.

Further, the mixing ratio of the migration prevention material and the above-mentioned polymer material is preferably 10% by mass or less for the migration prevention material and 5% by mass or less for the migration prevention material, for example, from the viewpoint of mechanical strength. It is more preferable, and it is further preferable that the migration prevention material is 2.5% by mass or less. Further, from the viewpoint of suppressing migration when the semiconductor chip or semiconductor wafer is bonded to the anisotropic conductive member, the migration prevention material is preferably 0.01% by mass or more.

<Inorganic filler>
The resin layer preferably contains an inorganic filler.
The inorganic filler is not particularly limited and may be appropriately selected from known ones. For example, kaolin, barium sulfate, barium titanate, silicon oxide powder, finely powdered silicon oxide, vapor phase silica, amorphous silica. , Crystalline silica, molten silica, spherical silica, talc, clay, magnesium carbonate, calcium carbonate, aluminum oxide, aluminum hydroxide, mica, aluminum nitride, zirconium oxide, yttrium oxide, silicon carbide, silicon nitride and the like.

It is preferable that the average particle size of the inorganic filler is larger than the distance between the conduction paths in order to prevent the inorganic filler from entering between the conduction paths and further improve the conduction reliability.
The average particle size of the inorganic filler is preferably 30 nm to 10 μm, more preferably 80 nm to 1 μm.
Here, the average particle size is the primary particle size measured by a laser diffraction / scattering type particle size measuring device (Microtrac MT3300 manufactured by Nikkiso Co., Ltd.) as the average particle size.

<Hardener>
The resin layer may contain a curing agent.
When a curing agent is contained, a solid curing agent is not used at room temperature, but a liquid curing agent at room temperature is contained from the viewpoint of suppressing poor bonding with the surface shape of the semiconductor chip or semiconductor wafer to be connected. Is more preferable.
Here, "solid at room temperature" means a solid at 25 ° C., for example, a substance having a melting point higher than 25 ° C.

Specific examples of the curing agent include aromatic amines such as diaminodiphenylmethane and diaminodiphenylsulfone, aliphatic amines, imidazole derivatives such as 4-methylimidazole, dicyandiamide, tetramethylguanidine, thiourea-added amines, and methyl. Examples thereof include carboxylic acid anhydrides such as hexahydrophthalic anhydride, carboxylic acid hydrazide, carboxylic acid amides, polyphenol compounds, novolak resins, and polymercaptans. From these curing agents, liquid ones at 25 ° C. are appropriately selected. Can be used. The curing agent may be used alone or in combination of two or more.

The resin layer may contain various additives such as a dispersant, a buffer, and a viscosity regulator, which are generally added to the resin insulating film of a semiconductor package, as long as the characteristics are not impaired.

<Shape>
For the reason of protecting the conduction path, the thickness of the resin layer is preferably larger than the height of the protruding portion of the conduction path and is preferably 1 μm to 5 μm.

Hereinafter, as an application example of the metal-filled microstructure 20, an example in which the metal-filled microstructure 20 is used for the anisotropic conductive member 22 (see FIG. 26 and the like) will be described.
FIG. 26 is a schematic view showing a first example of a laminated device using the metal-filled microstructure of the embodiment of the present invention, and FIG. 27 is a laminated device using the metal-filled microstructure of the embodiment of the present invention. FIG. 28 is a schematic view showing a second example of the above, FIG. 28 is a schematic view showing a third example of a laminated device using the metal-filled microstructure of the embodiment of the present invention, and FIG. 29 is an embodiment of the present invention. It is a schematic diagram which shows the 4th example of the laminated device which used the metal-filled microstructure of the form.

Further, as in the laminated device 60 shown in FIG. 26, the semiconductor element 62 and the semiconductor element 64 are joined in the stacking direction Ds via the anisotropic conductive member 22 exhibiting anisotropic conductivity, and the semiconductor element 62 and the semiconductor are joined. The element 64 may be electrically connected. The anisotropic conductive member 22 has the same configuration as the metal-filled microstructure 20 described above, has a conduction path 16 (see FIG. 5) conducting in the stacking direction Ds, and fulfills the function of a TSV (Through Silicon Via). .. The anisotropic conductive member 22 can also be used as an interposer.

In addition to the configuration shown in FIG. 26, for example, as in the laminated device 60 shown in FIG. 27, the semiconductor element 62, the semiconductor element 64, and the semiconductor element 66 are laminated and joined in the lamination direction Ds via the anisotropic conductive member 22. However, the configuration may be electrically connected.
Further, as in the laminated device 60 shown in FIG. 28, the semiconductor element 62, the semiconductor element 64, and the semiconductor element 66 are laminated and joined in the stacking direction Ds by using the interposer 23 and the anisotropic conductive member 22. It may be electrically connected.

Further, it may function as an optical sensor as in the laminated device 60 shown in FIG. 29. In the laminated device 60 shown in FIG. 29, the semiconductor element 72 and the sensor chip 74 are laminated in the lamination direction Ds via the anisotropic conductive member 22. Further, the sensor chip 74 is provided with a lens 76.
The semiconductor element 72 is formed with a logic circuit, and its configuration is not particularly limited as long as it can process the signal obtained by the sensor chip 74.
The sensor chip 74 has an optical sensor that detects light. The optical sensor is not particularly limited as long as it can detect light, and for example, a CCD (Charge Coupled Device) image sensor or a CMOS (Complementary Metal Oxide Semiconductor) image sensor is used.
In the laminated device 60 shown in FIG. 29, the semiconductor element 72 and the sensor chip 74 are connected via the anisotropic conductive member 22, but the present invention is not limited to this, and the semiconductor element 72 and the sensor chip 74 are connected to each other. May be directly joined.
The configuration of the lens 76 is not particularly limited as long as it can condense light on the sensor chip 74, and for example, a lens called a microlens is used.

The semiconductor element 62, the semiconductor element 64, and the semiconductor element 66 described above have an element region (not shown).
The element region is an region in which various element constituent circuits such as a capacitor, a resistor, and a coil for functioning as an electronic element are formed. In the element area, for example, a memory circuit such as a flash memory, an area in which a microprocessor and a logic circuit such as an FPGA (field-programmable gate array) are formed, a communication module such as a wireless tag, and wiring are formed. There is an area. In addition to this, a transmission circuit or a MEMS (Micro Electro Mechanical Systems) may be formed in the element region. MEMS is, for example, a sensor, an actuator, an antenna, or the like. Sensors include, for example, various sensors such as acceleration, sound and light.

As described above, an element constituent circuit or the like is formed in the element region, and the semiconductor element is provided with, for example, a rewiring layer (not shown).
In the laminated device, for example, a combination of a semiconductor element having a logic circuit and a semiconductor element having a memory circuit can be used. Further, all the semiconductor elements may have a memory circuit, or all the semiconductor elements may have a logic circuit. Further, the combination of the semiconductor elements in the laminated device 60 may be a combination of a sensor, an actuator, an antenna or the like, a memory circuit and a logic circuit, and is appropriately determined according to the application of the laminated device 60 and the like.

In addition to the above, the above-mentioned semiconductor element 62, semiconductor element 64, and semiconductor element 66 include, for example, logic integration of ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array), ASSP (Application Specific Standard Product), and the like. The circuit can be mentioned. Further, for example, a microprocessor such as a CPU (Central Processing Unit) and a GPU (Graphics Processing Unit) can be mentioned. Further, for example, DRAM (Dynamic Random Access Memory), HMC (Hybrid Memory Cube), MRAM (Magnetoresistive Random Access Memory), PCM (Phase-Change Memory), ReRAM (Resistance Random Access Memory), FeRAM (Ferroelectric Random Access Memory) , Memory such as flash memory. Further, for example, analog integrated circuits such as LEDs (Light Emitting Diodes), power devices, DC (Direct Current) -DC (Direct Current) converters, and insulated gate bipolar transistors (IGBTs) can be mentioned.
Further, as semiconductor elements, for example, GPS (Global Positioning System), FM (Frequency Modulation), NFC (Near Field Communication), RFEM (RF Expansion Module), MMIC (Monolithic Microwave Integrated Circuit), WLAN (Wireless Local Area Network). ) Etc., discrete elements, Passive devices, SAW (Surface Acoustic Wave) filters, RF (Radio Frequency) filters, IPDs (Integrated Passive Devices) and the like.

Next, a first example of a method for manufacturing a laminated device using a metal-filled microstructure will be described.
The first example of the method for manufacturing a laminated device using a metal-filled microstructure relates to a chip-on-wafer, and shows the method for manufacturing the laminated device 60 shown in FIG. 26.
30 to 32 are schematic views showing a first example of a method for manufacturing a laminated device using the metal-filled microstructure according to the embodiment of the present invention in order of steps.
In the first example of the method for manufacturing a laminated device using a metal-filled microstructure, first, a semiconductor element 64 in which the anisotropic conductive member 22 is provided on the surface 64a is prepared.
Next, the semiconductor element 64 is arranged so that the anisotropic conductive member 22 is directed toward the first semiconductor wafer 80. Next, the alignment mark of the semiconductor element 64 and the alignment mark of the first semiconductor wafer 80 are used to align the semiconductor element 64 with respect to the first semiconductor wafer 80.
Regarding the alignment, the configuration is particularly limited as long as digital image data can be obtained for the image or reflection image of the alignment mark of the first semiconductor wafer 80 and the image or reflection image of the alignment mark of the semiconductor element 64. A known imaging device can be used as appropriate.

Next, the semiconductor element 64 is placed in the element region of the first semiconductor wafer 80 via the anisotropic conductive member 22, and for example, a predetermined pressure is applied to heat the semiconductor element 64 to a predetermined temperature in advance. It is held for a predetermined time and temporarily joined using the resin layer 44 (see FIG. 24). This is performed for all the semiconductor elements 64, and as shown in FIG. 31, all the semiconductor elements 64 are temporarily bonded to the element region of the first semiconductor wafer 80.
Using the resin layer 44 for temporary bonding is one of the methods, and the method shown below may also be used. For example, a sealing resin or the like may be supplied onto the first semiconductor wafer 80 by a dispenser or the like to temporarily bond the semiconductor element 64 to the element region of the first semiconductor wafer 80, or the first semiconductor wafer 80 may be temporarily bonded. Above, the semiconductor element 64 may be temporarily bonded to the element region by using an insulating resin film (NCF (Non-conductive Film)) supplied in advance.

Next, in a state where all the semiconductor elements 64 are temporarily bonded to the element region of the first semiconductor wafer 80, a predetermined pressure is applied to the semiconductor element 64, and the semiconductor element 64 is heated to a predetermined temperature in advance. While holding for a predetermined time, all of the plurality of semiconductor elements 64 are collectively bonded to the element region of the first semiconductor wafer 80. This joint is called a main joint. As a result, the terminal (not shown) of the semiconductor element 64 is bonded to the anisotropic conductive member 22, and the terminal (not shown) of the first semiconductor wafer 80 is bonded to the anisotropic conductive member 22.
Next, as shown in FIG. 32, the first semiconductor wafer 80 to which the semiconductor element 64 is bonded via the anisotropic conductive member 22 is separated into individual pieces by dicing, laser scribing, or the like for each element region. As a result, it is possible to obtain a laminated device 60 in which the semiconductor element 62, the anisotropic conductive member 22, and the semiconductor element 64 are bonded.

If the temporary joining strength is weak at the time of temporary joining, the temporary joining strength is important because the position shift occurs in the transfer process and the process until joining.
The temperature conditions in the temporary joining process are not particularly limited, but are preferably 0 ° C. to 300 ° C., more preferably 10 ° C. to 200 ° C., and particularly preferably room temperature (23 ° C.) to 100 ° C. preferable.
Similarly, the pressurizing conditions in the temporary joining process are not particularly limited, but are preferably 10 MPa or less, more preferably 5 MPa or less, and particularly preferably 1 MPa or less.

The temperature condition in the main bonding is not particularly limited, but it is preferably a temperature higher than the temperature of the temporary bonding, specifically, 150 ° C. to 350 ° C., more preferably 200 ° C. to 300 ° C. Is particularly preferable.
The pressurizing conditions in this joining are not particularly limited, but are preferably 30 MPa or less, and more preferably 0.1 MPa to 20 MPa.
The time of the main joining is not particularly limited, but is preferably 1 second to 60 minutes, and more preferably 5 seconds to 10 minutes.
By performing the main bonding under the above conditions, the resin layer flows between the electrodes of the semiconductor element 64, and it becomes difficult for the resin layer to remain in the bonding portion.
As described above, in the main bonding, the tact time can be reduced and the productivity can be increased by collectively bonding the plurality of semiconductor elements 64.

A second example of a method for manufacturing a laminated device using a metal-filled microstructure will be described.
33 to 35 are schematic views showing a second example of a method for manufacturing a laminated device using the metal-filled microstructure according to the embodiment of the present invention in order of steps.
The second example of the method for manufacturing a laminated device using a metal-filled microstructure has three semiconductor elements 62, 64 as compared with the first example of the method for manufacturing a laminated device using a metal-filled microstructure. , 66 is the same as the first example of the method for manufacturing a laminated device using a metal-filled microstructure, except that 66 is laminated and joined via an anisotropic conductive member 22. Therefore, a detailed description of the manufacturing method common to the second example of the manufacturing method of the laminated device will be omitted.
The semiconductor element 64 is provided with an alignment mark (not shown) on the back surface 64b and a terminal (not shown). Further, the semiconductor element 64 is provided with an anisotropic conductive member 22 on the surface 64a. Further, the semiconductor element 66 is also provided with the anisotropic conductive member 22 on the surface 66a.

As shown in FIG. 33, in a state where all the semiconductor elements 64 are temporarily bonded to the element region of the first semiconductor wafer 80 via the anisotropic conductive member 22, the alignment marks on the back surface 64b of the semiconductor element 64 and the alignment marks. The alignment mark of the semiconductor element 66 is used to align the semiconductor element 66 with respect to the semiconductor element 64.

Next, as shown in FIG. 34, the semiconductor element 66 is temporarily joined to the back surface 64b of the semiconductor element 64 via the anisotropic conductive member 22. Next, all the semiconductor elements 64 are temporarily bonded to the element region of the first semiconductor wafer 80 via the anisotropic conductive member 22, and all the semiconductor elements 64 are temporarily bonded to the semiconductor elements via the anisotropic conductive member 22. With the 66 temporarily joined, the main joining is performed under predetermined conditions. As a result, the semiconductor element 64 and the semiconductor element 66 are joined via the anisotropic conductive member 22, and the semiconductor element 64 and the first semiconductor wafer 80 are joined via the anisotropic conductive member 22. The semiconductor element 64, the semiconductor element 66, and the terminals (not shown) of the first semiconductor wafer 80 are joined to the anisotropic conductive member 22.
Next, as shown in FIG. 35, the first semiconductor wafer 80 in which the semiconductor element 64 and the semiconductor element 66 are joined via the anisotropic conductive member 22 is placed in each element region, for example, by dicing or laser scribing. It is individualized by. Thereby, the laminated device 60 in which the semiconductor element 62, the semiconductor element 64, and the semiconductor element 66 are bonded via the anisotropic conductive member 22 can be obtained.

A third example of a method for manufacturing a laminated device using a metal-filled microstructure will be described.
A third example of a method for manufacturing a laminated device using a metal-filled microstructure relates to a wafer-on-wafer, and shows a method for manufacturing the laminated device 60 shown in FIG.
36 and 37 are schematic views showing a third example of a method for manufacturing a laminated device using the metal-filled microstructure according to the embodiment of the present invention in order of steps.
A third example of a method for manufacturing a laminated device using a metal-filled microstructure is a first semiconductor wafer 80 via an anisotropic conductive member 22 as compared with the first example of a method for manufacturing a laminated device. It is the same as the third example of the manufacturing method of the laminated device except that the second semiconductor wafer 82 is bonded to the second semiconductor wafer 82. Therefore, detailed description of the manufacturing method common to the first example of the manufacturing method of the laminated device will be omitted. Further, since the anisotropic conductive member 22 is also as described above, detailed description thereof will be omitted.

First, the first semiconductor wafer 80 and the second semiconductor wafer 82 are prepared. The anisotropic conductive member 22 is provided on either the surface 80a of the first semiconductor wafer 80 or the surface 82a of the second semiconductor wafer 82.
Next, the surface 80a of the first semiconductor wafer 80 and the surface 82a of the second semiconductor wafer 82 are opposed to each other. Then, the alignment mark of the first semiconductor wafer 80 and the alignment mark of the second semiconductor wafer 82 are used to align the second semiconductor wafer 82 with respect to the first semiconductor wafer 80.
Next, the surface 80a of the first semiconductor wafer 80 and the surface 82a of the second semiconductor wafer 82 are opposed to each other, and using the above method, the first semiconductor wafer 80 and the second semiconductor wafer 80 and the second The semiconductor wafer 82 is joined via the anisotropic conductive member 22. In this case, after the temporary joining, the main joining may be performed, or only the main joining may be performed.

Next, as shown in FIG. 37, in a state where the first semiconductor wafer 80 and the second semiconductor wafer 82 are joined via the anisotropic conductive member 22, for each element region, for example, dicing or laser scribing. Individualize by etc. Thereby, the laminated device 60 in which the semiconductor element 62 and the semiconductor element 64 are bonded to each other via the anisotropic conductive member 22 can be obtained. In this way, the laminated device 60 can also be obtained by using a wafer-on-wafer.
Since the individualization is as described above, detailed description thereof will be omitted.
Further, as shown in FIG. 37, it is necessary to make the first semiconductor wafer 80 and the second semiconductor wafer 82 thinner in a state where the first semiconductor wafer 80 and the second semiconductor wafer 82 are joined. If there is a semiconductor wafer, it can be thinned by chemical mechanical polishing (CMP) or the like.

In the third example of the method for manufacturing a laminated device using a metal-filled microstructure, a two-layer structure in which a semiconductor element 62 and a semiconductor element 64 are laminated has been described as an example, but the present invention is not limited to this. Of course, as described above, three or more layers may be used. In this case, as in the second example of the method for manufacturing the laminated device 60 described above, the alignment mark (not shown) and the terminal (not shown) are provided on the back surface 82b of the second semiconductor wafer 82. A laminated device 60 having more than one layer can be obtained.

As described above, by providing the anisotropic conductive member 22 in the laminated device 60, even if the semiconductor element has irregularities, the irregularities are absorbed by using the protruding portion 16a and the protruding portion 16b as a buffer layer. can do. Since the protruding portion 16a and the protruding portion 16b function as a buffer layer, high surface quality can be unnecessary for the surface of the semiconductor element having the element region. Therefore, smoothing treatment such as polishing is not required, production cost can be suppressed, and production time can be shortened.
Further, since the laminated device 60 can be manufactured using the chip-on-wafer, by joining only the non-defective product of the semiconductor chip to the non-defective product portion in the semiconductor wafer, the profitability can be maintained and the manufacturing loss can be reduced. Can be done.
Further, as described above, the resin layer 44 has adhesiveness and can be used as a temporary bonding agent at the time of temporary bonding, and can be collectively main-bonded.

The semiconductor element 64 provided with the anisotropic conductive member 22 described above can be formed by using the anisotropic conductive member 22 and a semiconductor wafer having a plurality of element regions (not shown). As described above, the element region is provided with an alignment mark (not shown) and a terminal (not shown) for alignment. In the anisotropic conductive material 50 (see FIG. 25), the anisotropic conductive member 22 is formed in a pattern that matches the element region.

First, a predetermined pressure is applied, the temperature is heated to a predetermined temperature, and the temperature is held for a predetermined time to join the anisotropic conductive member 22 of the anisotropic conductive material 50 to the element region of the semiconductor wafer. ..
Next, the support 46 of the anisotropic conductive material 50 is removed, and only the anisotropic conductive member 22 is bonded to the semiconductor wafer. In this case, the anisotropic conductive material 50 is heated to a predetermined temperature to reduce the adhesive force of the release agent 49 of the release layer 47, and the support 46 starts from the release layer 47 of the anisotropic conductive material 50. Get rid of. Next, the semiconductor wafer is fragmented for each element region to obtain a plurality of semiconductor elements 64.
Although the semiconductor element 64 provided with the anisotropic conductive member 22 has been described as an example, the semiconductor element 66 provided with the anisotropic conductive member 22 also has a second semiconductor element 22 provided with the anisotropic conductive member 22. In the same way as the semiconductor element 64 in which the anisotropic conductive member 22 is provided, the anisotropic conductive member 22 can be provided in the semiconductor wafer 82.

The joining of semiconductor devices has been described in the form of joining another semiconductor element to the semiconductor element, but the present invention is not limited to this, and is a form of joining a plurality of semiconductor elements to one semiconductor element. It may be in a one-to-many form. Further, a plurality of to a plurality of forms in which a plurality of semiconductor elements and a plurality of semiconductor elements are joined may be used.
FIG. 38 is a schematic view showing a fifth example of the laminated device according to the embodiment of the present invention, FIG. 39 is a schematic view showing a sixth example of the laminated device according to the embodiment of the present invention, and FIG. 40 is a schematic view showing the sixth example. FIG. 41 is a schematic view showing a seventh example of a laminated device according to an embodiment of the present invention, FIG. 41 is a schematic view showing an eighth example of a laminated device according to an embodiment of the present invention, and FIG. 42 is a schematic view showing an eighth example of the laminated device according to the embodiment of the present invention. It is a schematic diagram which shows the 9th example of the laminated device of.

As a one-to-many form, for example, as shown in FIG. 38, the semiconductor element 62, the semiconductor element 64, and the semiconductor element 66 are joined by using an anisotropic conductive member 22, and are electrically connected to each other. A laminated device 83 in a different form is exemplified. The semiconductor element 62 may have an interposer function. In the laminated device 83, a semiconductor element wafer may be used instead of the semiconductor element 62, the semiconductor element 64, and the semiconductor element 66.
Further, as a plurality of to a plurality of forms, for example, as shown in FIG. 39, the semiconductor element 64 and the semiconductor element 66 are bonded to one semiconductor element 62 by using the anisotropic conductive member 22. An example is an electrically connected laminated device 84. The semiconductor element 62 may have an interposer function.

Further, for example, it is possible to stack a plurality of devices such as a logic chip having a logic circuit and a memory chip on a device having an interposer function. Further, in this case, even if the electrode size is different for each device, the bonding can be performed.
In the laminated device 85 shown in FIG. 40, the electrodes 88 are not the same in size, but are mixed in different sizes. However, a semiconductor using an anisotropic conductive member 22 is used for one semiconductor element 62. The element 64 and the semiconductor element 66 are joined and electrically connected. Further, the semiconductor element 86 is joined to the semiconductor element 64 by using the anisotropic conductive member 22, and is electrically connected. The semiconductor element 87 is joined and electrically connected by using the anisotropic conductive member 22 across the semiconductor element 64 and the semiconductor element 66.

Further, as in the laminated device 89 shown in FIG. 41, the semiconductor element 64 and the semiconductor element 66 are joined to one semiconductor element 62 by using an anisotropic conductive member 22, and are electrically connected to each other. There is. Further, the semiconductor element 86 and the semiconductor element 87 are joined to the semiconductor element 64 by using the heterogeneous conductive member 22, and the semiconductor element 91 is joined to the semiconductor element 66 by using the heterogeneous conductive member 22 and electrically. It can also be a connected configuration.

In the case of the above configuration, a light emitting element such as a VCSEL (Vertical Cavity Surface Emitting Laser) and a light receiving element such as a CMOS (Complementary Metal Oxide Semiconductor) image sensor are laminated on a device surface including an optical waveguide. This makes it possible to support silicon photonics assuming high frequencies.
For example, as in the laminated device 89a shown in FIG. 42, the semiconductor element 64 and the semiconductor element 66 are joined to one semiconductor element 62 by using an anisotropic conductive member 22, and are electrically connected to each other. There is. Further, the semiconductor element 86 and the semiconductor element 87 are joined to the semiconductor element 64 by using the heterogeneous conductive member 22, and the semiconductor element 91 is joined to the semiconductor element 66 by using the heterogeneous conductive member 22 and electrically. It is connected. The semiconductor element 62 is provided with an optical waveguide 81. The semiconductor element 66 is provided with a light emitting element 95, and the semiconductor element 64 is provided with a light receiving element 96. The light Lo output from the light emitting element 95 of the semiconductor element 66 passes through the optical waveguide 81 of the semiconductor element 62 and is emitted as the emitted light Ld to the light receiving element 96 of the semiconductor element 64. This makes it possible to deal with the above-mentioned silicon photonics.
The anisotropic conductive member 22 is formed with holes 27 at locations corresponding to the optical paths of the light Lo and the emitted light Ld.

A specific assembly process in three-dimensional lamination using a laminate will be described.
In order to realize three-dimensional stacking, it is necessary that the wiring responsible for the electrical connection in the stacking direction is formed in the device to be stacked, and the wiring responsible for the connection in the stacking direction is TSV (Through Silicon Via). be called. Devices with TSVs are classified into three types, via first, viamidol, and vialast, depending on the stage at which the TSV is formed. The one that forms the TSV before forming the transistor of the device is called via first. What is formed after the formation of the transistor and before the formation of the rewiring layer is called viamidol. What is formed after the rewiring layer is formed is called a via last. TSV formation by either method requires thinning of the silicon substrate in order to perform the penetration process.

A method of joining a semiconductor chip or wafer to which TSV is applied will be described together with an example of a usage pattern of the laminate.
A typical example of beer first or via midol is a stacked memory chip called HBM (High Bandwidth Memory) or HMC (Hybrid Memory Cube). In these examples, the memory area is formed and the TSV area is formed in the same die shape, the base wafer is thinned, the TSV is formed, an electrode called a microbump is formed on the surface of the via, and the electrodes are laminated and bonded. Is going.
An example of a vialast is a step of joining a semiconductor chip or wafer having no metal bumps with an insulating adhesive or an insulating oxide, and then forming a TSV.

Conventionally, after forming a bond between layers, holes are formed by a method such as the BOSCH method or a laser drill method, plating nuclei are formed on the wall surface by sputtering or the like, and metal is filled by plating to wire each layer. It is electrically joined to the part.
However, since the metal filling is formed by the growth of the plating nucleus, the bonding between the filling metal and the wiring portion is not always guaranteed. On the other hand, when the bumps are connected to each other by using the anisotropic conductive member, the conductive path of the anisotropic conductive member directly forms a bond with the bump, so that the electrical connection is strengthened and the signal connection is further enhanced. It will be good. At this time, by providing electrodes that do not contribute to signal transmission on the surface of the semiconductor chip or the surface of the wafer, the area of the joint portion can be increased and the resistance per shear stress can be improved. Further, since the heat conduction between the layers is good, the heat is easily diffused to the entire laminated body. These mechanisms further improve connection strength and heat dissipation.

Examples of bonding methods applicable to any of ViaFirst, Viamidol, and Vialast include metal diffusion bonding, oxide film direct bonding, metal bump bonding, and eutectic bonding.
Metal diffusion bonding or oxide film direct bonding has good bondability under low pressure and low temperature conditions. On the other hand, as a high degree of cleanliness for the joint surface, for example, a level equivalent to that immediately after surface cleaning by Ar etching is required. Further, as the flatness, for example, since the arithmetic mean roughness Ra is required to be 1 nm or less, strict atmosphere control and parallelism control are required at the time of joining. In addition, different companies, or semiconductor device product groups manufactured in different factories even if the companies are the same, may have different types of semiconductor devices or wiring rules, and such semiconductor device product groups are three-dimensional. When stacking, the strictest precision or control is required.

On the other hand, metal bump bonding or eutectic bonding has good bondability even when there are some defects or the process is redundant. In addition, due to deformation or flow of bumps or solder, the cleanliness or flatness of the device surface when joining dissimilar devices may be lower than that of metal diffusion bonding or oxide film direct bonding.
The problems with these bonding methods are that the bonding strength is lower than that of metal diffusion bonding and oxide film direct bonding, and that the already bonded portion may be reheated each time stacking is repeated, causing device failure. Can be mentioned. Literature (AIST Research Results Report March 8, 2013: "Multifunctional High Density 3D Integration Technology (2) Research and Development of Evaluation and Analysis Technology for Next-Generation 3D Integration <(2) -B Thermal / Laminated Bonding Technology research and development> ”) proposes a method of avoiding the influence of temperature history by temporarily fixing at the time of lamination with an organic resin and heating and joining all layers at once after lamination. Since heat dissipation can be improved by forming electrodes that do not contribute to signal transmission, it is particularly useful to apply the laminate to an embodiment using an organic resin layer having low thermal conductivity.

Next, a case where the anisotropic conductive member constituting the laminated body is used for the above-mentioned joining will be described.
The anisotropic conductive member used in the laminate preferably has a resin layer formed on at least one surface, and more preferably formed on both sides.
Further, the resin layer 44 of the above-mentioned anisotropic conductive member preferably contains a thermosetting resin. The formed resin layer is used as a temporary bonding layer to suppress misalignment after lamination. Since the temporary joining can be performed at a low temperature and in a short time, the adverse effect on the device can be reduced. From the viewpoint of suppressing misalignment due to heat during the process, the thickness of the above-mentioned resin layer is preferably 100 nm to 1000 nm, and the thermal conductivity of the anisotropic conductive member is 20 to 100 W / (m. K) is preferable, and the coefficient of thermal expansion (CTE) of the anisotropic conductive member is preferably 5 ppm to 10 ppm.

The anisotropic conductive member is preferably supplied in a form held by the support via a peelable adhesive layer. The material of the support is not particularly limited, but a material such as silicon or glass is preferable because it is difficult to bend and a certain flatness can be secured.
The peelable adhesive layer may be an adhesive layer having low adhesiveness, but an adhesive layer whose adhesiveness is lowered by heating or light irradiation is preferable. Examples of the adhesive layer whose adhesiveness is lowered by heating include Riva Alpha (registered trademark) manufactured by Nitto Denko Corporation or Somatac (registered trademark) manufactured by SOMAR Corporation. As the adhesive layer whose adhesiveness is lowered by light irradiation, a material such as that used as a general dicing tape can be used, and an optical release layer manufactured by 3M Co., Ltd. is also mentioned as an example.

The anisotropic conductive member may have a pattern formed at the stage of being held by the support. Examples of pattern formation include, for example, uneven pattern formation, individualization, and prohydrophobic pattern formation, and it is preferable that a prohydrophobic pattern is formed, and that the prohydrophobic pattern is individualized. More preferred.
Since the anisotropic conductive member contains a conductive material, it is sufficient that an electrode is formed on the surface of the object to be joined in order to perform the joining, and a special metal bump such as a fine conical gold bump or Connectec Japan Corporation is used. No special technology such as monster pack core technology by the company, Tohoku Microtech Co., Ltd. and Masahiro Aoyagi Research Group of AIST is required. In particular, in order to enable joining even when the surface flatness of the object to be joined is low, the anisotropic conductive member preferably has protrusions on the surface, and as described above, the protruding portion 16a, that is, the protrusions are conductive. It is more preferable to include protrusions made of wood.
Further, since the laminated body having the terminals having the area ratio of the present invention has good heat conduction between the layers, heat is easily diffused to the entire laminated body, so that the heat dissipation property is particularly good.

Next, a laminating method of the laminating device will be described.
Examples of laminating different semiconductor chips include a COC (Chip on Chip) method, a COW (Chip on Wafer) method, and a WOW (Wafer on Wafer) method. The COC method is a method in which semiconductor chips are laminated on a semiconductor chip fixed to a substrate, and it is possible to laminate semiconductor chips of different sizes, and it is possible to select good semiconductor chips before joining. However, when a large number of semiconductor chips are laminated, alignment is required each time, which is expensive. The COW method is a method in which semiconductor chips are laminated on a substrate wafer, and when a large number of semiconductor chips are laminated, alignment is required each time as in the COC method, which is costly. The WOW method is a method of joining wafers to each other, and has advantages such as shortening of joining time and easy alignment. However, since good semiconductor chips cannot be selected, the yield of multilayer laminates tends to decrease. ..

For the purpose of shortening the alignment time, a method called self-alignment in which batch alignment is performed on a wafer has been studied, and for example, the technique is disclosed in Japanese Patent Application Laid-Open No. 2005-150385 or Japanese Patent Application Laid-Open No. 2014-57019. .. However, these documents only disclose a technique for aligning the positions of fixed semiconductor chips, and it is necessary to further perform any of the above-mentioned bonding methods in order to electrically bond the layers. there were. In order to apply the metal diffusion bonding or the oxide film direct bonding, it is necessary to precisely control the heights of all the arranged semiconductor chips, which is costly. On the other hand, when applying metal bump bonding or eutectic bonding, it is necessary to take measures against reheating of the existing bonded part in the method of heating and joining each time, and in the method of heating and joining all layers at once, stacking is performed. At times, it was necessary to devise ways to prevent the semiconductor chips from shifting and to take measures to dissipate heat.

Three-dimensional lamination using an anisotropic conductive member is useful for the above-mentioned problems.
Therefore, it is preferable to use an anisotropic conductive member for each joining of the laminated body, but the laminated body may include joining by a conventional method. Examples of including bonding by the conventional method include a mode in which a laminate having bonding by an anisotropic conductive member has hybrid bonding between an optical semiconductor and an ASIC (Application Specific Integrated Circuit), and a surface between a memory and an ASIC. Examples include an embodiment having an activated junction. Joining by the conventional method has an advantage that devices manufactured according to different rules can be easily laminated.

The following aspects can be mentioned as an example of three-dimensional lamination using an anisotropic conductive member.
First, the first semiconductor chip group is inspected and individualized, and the first non-defective semiconductor chip group is selected.
The first non-defective semiconductor chip group is arranged on the first substrate via the first anisotropic conductive member, and temporary bonding is performed. Temporary joining can be performed by a device such as a flip chip bonder. The first substrate is not particularly limited, and examples thereof include a device having a transistor or a substrate having a wiring layer and a through electrode.
After inspecting the semiconductor chip group to be laminated, the semiconductor chips to be laminated are separated into individual pieces and the good semiconductor chip group to be laminated is selected. The group of semiconductor chips to be laminated is not particularly limited, and examples thereof include a mode having a through electrode or a mode in which the back surface of the semiconductor chip having an embedded via is removed. Examples of the method for removing the back surface include back grind, CMP, and chemical etching. In particular, a removal method such as chemical etching with less lateral stress is preferable.

The group of non-defective semiconductor chips to be laminated is arranged at a position corresponding to the arrangement of the first group of non-defective semiconductor chips on the first substrate of the second substrate.
After aligning the first substrate and the second substrate, a second anisotropic conductive member is sandwiched between the first substrate and the second substrate, and the second anisotropic conductive member is sandwiched between the first substrate and the second substrate. Temporarily joins the first non-defective semiconductor chip group and the laminated non-defective semiconductor chip group through the above. Next, the second substrate is peeled off from the group of good semiconductor chips to be laminated and removed.
The structure consisting of the first non-defective semiconductor chip group, the second anisotropic conductive member, and the laminated non-defective semiconductor chip group is designated as a new first non-defective semiconductor chip group, and a predetermined hierarchical structure is formed. The stacking of the second anisotropic conductive member and the semiconductor chip group to be laminated is repeated until.
After the structure of the predetermined layer is formed, the layers are mainly joined by heating and pressurizing all at once to obtain a three-dimensional bonded structure.
The obtained three-dimensional bonded structure is sealed by a method such as compression bonding and individualized to obtain the desired element. In addition, you may perform processing such as thinning, rewiring, electrode formation, etc. before performing individualization.

As another example, an embodiment in which the semiconductor chip group to be laminated is individualized after being bonded to the first non-defective semiconductor chip group via the second anisotropic conductive member, and the anisotropic conductivity in which a pattern is formed. An embodiment in which the member is used as a first or second anisotropic conductive member, and an anisotropic conductive member in which a pattern is formed are used as an adhesive for arranging a group of semiconductor chips to be laminated on a second substrate. Examples thereof include a mode in which peeling is performed at the interface between the second substrate and the anisotropic conductive member.

In addition, as another example, the following aspects can be mentioned.
First, the first anisotropic conductive member is provided on the surface of the first substrate. The first substrate may have a mode in which MOS (Metal Oxide Semiconductor) is present or a mode in which MOS (Metal Oxide Semiconductor) does not exist.
The first semiconductor chip group is inspected, individualized, and the first non-defective semiconductor chip group is selected.
A second anisotropic conductive member is provided on the surface of the support via a temporary bonding layer whose adhesiveness is reduced by the treatment. The material of the support is not particularly limited, but silicon or glass is preferable. As the temporary bonding layer whose adhesiveness is lowered by the treatment, a temporary bonding layer whose adhesiveness is lowered by heating or a temporary bonding layer whose adhesiveness is lowered by light irradiation is preferable.

A pattern is provided on the second anisotropic conductive member. As the pattern, an individualized prohydrophobic pattern is more preferable. When the hydrophobic pattern is fragmented, it becomes easy to transfer the anisotropic conductive member to the first non-defective semiconductor chip group in a later step. The individualizing method is not particularly limited, and examples thereof include a dicing method, a laser irradiation method, a stealth dicing method, a wet etching method, and a dry etching method.

By the self-assembly technique using a pattern, the first non-defective semiconductor chip group is arranged on the support via the second anisotropic conductive member, and temporary joining is performed. As a self-assembly technique, for example, a droplet containing an activator is formed on a mounting region of a substrate, a group of semiconductor chips is placed on the droplet, a device is positioned in the mounting region, and the droplet is dried. Examples thereof include a method in which the element and the mounting substrate are joined via a curable resin layer to wash away the activator. These techniques are disclosed in Japanese Patent Application Laid-Open No. 2005-150385 or Japanese Patent Application Laid-Open No. 2014-57019. Electrodes may be used as alignment marks during self-assembly.

The first substrate and the first non-defective semiconductor chip group are temporarily joined via the first anisotropic conductive member. Next, a treatment for lowering the adhesiveness of the temporary bonding layer is performed, and peeling is performed at the interface between the second anisotropic conductive member and the support.
The structure consisting of the first substrate, the first anisotropic conductive member, and the first non-defective semiconductor chip group is used as a new first substrate, and the second anisotropic conductive member is used as a new first anisotropic member. The conductive member is used, and the first non-defective semiconductor chip group and the second anisotropic conductive member are repeatedly laminated until a predetermined hierarchical structure is formed.

After the structure of the predetermined hierarchy is formed, the layers are mainly joined by performing batch processing under the conditions of higher pressure and higher temperature than the conditions used for the temporary joining to obtain a three-dimensional joining structure. Since the temporary bonding layer remains in the laminated body, it is preferable to use a material in which the curing reaction proceeds under the main bonding conditions as the temporary bonding layer.
The obtained three-dimensional bonded structure is sealed by a method such as compression bonding and individualized to obtain the desired laminated device. It should be noted that treatments such as thinning, rewiring, and electrode formation may be performed before the individualization.
As described above, since the temporary bonding and the main bonding can be separated by using the anisotropic conductive member, it is not necessary to perform a high temperature process such as solder reflow a plurality of times, and the risk of device failure can be reduced. Further, as described above, in the embodiment in which the anisotropic conductive member having the resin layer on the surface is used, the influence of the process conditions on the joint portion can be alleviated by the resin layer. Further, in the embodiment in which the anisotropic conductive member having protrusions on the surface is used, joining is possible even when the surface flatness of the object to be joined is low, so that the flattening process can be simplified.

Hereinafter, the three-dimensional lamination using the laminate will be described more specifically with reference to FIGS. 43 to 58.
43 to 53 are schematic views showing a fourth example of a method for manufacturing a laminated device using the metal-filled microstructure according to the embodiment of the present invention in order of steps.
54 to 56 are schematic views showing the manufacturing method of the laminated body used in the fourth example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of the present invention in the order of steps.
57 and 58 are schematic views showing the manufacturing method of the laminated body used in the fourth example of the manufacturing method of the laminated device using the metal-filled microstructure of the embodiment of the present invention in the order of steps.
The fourth example of the method for manufacturing a laminated device using a metal-filled microstructure relates to three-dimensional lamination, and is different from the second example of the method for manufacturing a laminated device using a metal-filled microstructure. A direction conductive member is used. Therefore, a detailed description of the manufacturing method common to the second example of the manufacturing method of the laminated device using the metal-filled microstructure will be omitted.

First, as shown in FIG. 43, a first laminated substrate 90 provided with an anisotropic conductive member 22 on the entire surface 92a of the semiconductor wafer 92 is prepared. The semiconductor wafer 92 can have, for example, the same configuration as the first semiconductor wafer 80 having a plurality of element regions (not shown). The semiconductor wafer 92 can also be the above-mentioned interposer 23.
Further, as shown in FIG. 44, a second laminated substrate 100 provided with a plurality of semiconductor elements 64 is prepared. In the second laminated substrate 100, the peeling functional layer 104 and the anisotropic conductive member 22 are laminated on the surface 102a of the second substrate 102. A plurality of semiconductor elements 64 are provided on the anisotropic conductive member 22. A hydrophobic film 105 is provided on the anisotropic conductive member 22 in a region where the semiconductor element 64 is not provided.
In the second laminated substrate 100, the back surface 64b of the semiconductor element 64 is the surface on the second substrate 102 side, and the surface 64a is the surface on the opposite side. As the semiconductor element 64, for example, a non-defective semiconductor element that has been inspected and selected is used.

The peeling functional layer 104 is composed of, for example, an adhesive layer whose adhesiveness is lowered by heating or light irradiation. Examples of the adhesive layer whose adhesiveness is lowered by heating include Riva Alpha (registered trademark) manufactured by Nitto Denko Corporation or Somatac (registered trademark) manufactured by SOMAR Corporation. As the adhesive layer whose adhesiveness is lowered by light irradiation, a material such as that used as a general dicing tape can be used, and an optical release layer manufactured by 3M Co., Ltd. is also mentioned as an example.

Next, as shown in FIG. 45, the first laminated substrate 90 and the second laminated substrate 100 are temporarily joined. The method of temporary joining is as described above. Further, a device such as a flip chip bonder can be used for temporary joining.
Next, as shown in FIG. 46, the second substrate 102 of the second laminated substrate 100 is removed. In this case, the semiconductor element 64 is in a state of being temporarily bonded to the anisotropic conductive member 22 of the semiconductor wafer 92, and the anisotropic conductive member 22 is reprinted on the surface 64a of the semiconductor element 64.
The second substrate 102 is removed by, for example, heating or irradiating with light to reduce the adhesiveness of the peeling functional layer 104.

Next, as shown in FIG. 47, another second laminated substrate 100 is temporarily joined to the anisotropic conductive member 22 on the surface 64a side of the semiconductor element 64 by aligning the positions of the semiconductor elements 64 with each other. In this case, the back surface 64b of the semiconductor element 64 of another second laminated substrate 100 and the anisotropic conductive member 22 on the front surface 64a side of the semiconductor element 64 temporarily bonded to the semiconductor wafer 92 are temporarily bonded. The method of temporary joining is as described above.
Next, as shown in FIG. 48, the second substrate 102 of another second laminated substrate 100 is removed. The method for removing the second substrate 102 is as described above.
As shown in FIG. 48, the semiconductor element 64 is in a state of being temporarily joined to the anisotropic conductive member 22 of the semiconductor element 64 on the side of the semiconductor wafer 92, and the anisotropic conductive member 22 is attached to the surface 64a of the semiconductor element 64. Is reprinted. FIG. 48 shows a configuration in which the semiconductor element 64 is provided in two layers. By repeating the temporary bonding of the second laminated substrate 100 in this way, the number of laminated semiconductor elements 64 can be controlled.

Here, the third composite laminate 106 shown in FIG. 49 is prepared. The third composite laminate 106 has a third substrate 108, and a hydrophobic film 109 is formed on the surface 108a thereof in a specific pattern. Further, the semiconductor element 64 is provided on the surface 108a of the third substrate 108, that is, in a region where the hydrophobic film 109 is not provided. In this case as well, as the semiconductor element 64, for example, a non-defective semiconductor element that has been inspected and selected is used.
For the hydrophobic membrane 109, for example, a water-repellent material is applied through a mask to form a desired pattern to obtain a specific pattern. As the water-repellent material, a compound such as alkylsilane or fluoroalkylsilane can be used. As the water-repellent material, a material that exhibits a water-repellent effect depending on the shape, for example, a phase-separated structure of isotactic polypropylene (i-PP) or the like can be used.

Next, as shown in FIG. 50, a third composite laminate is formed on the anisotropic conductive member 22 on the surface 64a side of the semiconductor element 64 with respect to the first laminate 90 provided with two layers of the semiconductor element 64. The body 106 is temporarily joined by aligning the positions of the semiconductor elements 64 with each other. As a result, the semiconductor element 64 is provided with three layers.
Next, as shown in FIG. 51, the third substrate 108 of the third composite laminate 106 is removed. The method for removing the third substrate 108 is the same as the method for removing the second substrate 102 described above.
Next, the semiconductor element 64, the anisotropic conductive member 22, and the semiconductor wafer 92 are main-bonded by performing batch processing under conditions of higher pressure and higher temperature than those used in the temporary bonding, and the three dimensions shown in FIG. 52 are obtained. A bonded structure 94 is obtained. The three-dimensional bonded structure 94 may be subjected to processing such as thinning, rewiring, and electrode formation.

Next, the semiconductor wafer 92 of the three-dimensional bonded structure 94 and the anisotropic conductive member 22 are cut into pieces as shown in FIG. 53. As a result, it is possible to obtain a laminated device 60 in which three semiconductor elements 64 are bonded via an anisotropic conductive member 22. As the method of individualization, the above-mentioned method can be appropriately used.

As shown in FIG. 54, the second laminated substrate 100 shown in FIG. 44 is formed by laminating the peeling functional layer 104 and the anisotropic conductive member 22 on the surface 102a of the second substrate 102.
Next, as shown in FIG. 55, the anisotropic hydrophobic film 105 is formed on the anisotropic conductive member 22 in a specific pattern.
The hydrophobic film 105 is formed with a pattern on the anisotropic conductive member 22 by a method such as a lithography method or a self-assembling method. Among the hydrophilic membrane 105, examples of the hydrophilic material forming the hydrophilic pattern include a hydrophilic polymer such as polyvinyl alcohol.
Further, the material used for the above-mentioned prohydrophobic membrane 109 can also be used to form the prohydrophobic membrane 105. The hydrophilic film 105 can also form a specific pattern by exposure development using, for example, a resist material containing a fluorine-based compound.

Next, as shown in FIG. 56, the semiconductor element 64 is provided in the region where the hydrophobic film 105 is not provided. As a result, the second laminated substrate 100 shown in FIG. 44 is obtained.
As a method of providing the semiconductor element 64, for example, a droplet containing an activator is formed in a region where the hydrophobic membrane 105 is not provided, the semiconductor element 64 is placed on the droplet, positioned, and the droplet is placed. A method is used in which the semiconductor element 64 and the second substrate 102 are joined to each other via a curable resin layer after drying, and the activator is washed away.

The third composite laminate 106 shown in FIG. 49 prepares a third substrate 108 as shown in FIG. 57. Next, as shown in FIG. 58, the hydrophobic film 109 is formed on the surface 108a of the third substrate 108 in a specific pattern. The hydrophobic membrane 109 has the same structure as the above-mentioned hydrophobic membrane 105 and can be formed by the same method.
Next, the semiconductor element 64 is provided in the region where the hydrophobic film 109 is not provided. As a method of providing the semiconductor element 64, for example, a droplet containing an activator is formed in a region where the hydrophobic film 109 is not provided, the semiconductor element 64 is placed on the droplet, positioned, and the droplet is placed. A method is used in which the semiconductor element 64 and the third substrate 108 are joined to each other via a curable resin layer after drying, and the activator is washed away. As a result, the third composite laminate 106 shown in FIG. 49 is obtained.

It is also possible to support a new method that does not use TSV. In three-dimensional mounting, as described above, there are cases where one-to-many forms or multiple-to-many forms are required to be joined. In that case, it is usually necessary to give an interposer function to one of the devices in advance. However, considering a heterogeneous bonding environment, it is not preferable to design in advance to assemble individual devices.
As a method of solving such a problem, a rewiring layer (RDL: Re-Distribution Layer)
Has been proposed as a method of using alone. By joining the rewiring layer having an interposer function that connects various devices to the anisotropic conductive film and including it, it is possible to realize low profile and TSV-free without being particular about individual device design.
It is also possible to install a stack in which a plurality of devices are stacked on an organic substrate by the same mechanism.
Examples of these assemblies are shown in FIGS. 59-76. Of course, the specific assembly method is not limited to those shown in FIGS. 59 to 76.
59 to 71 are schematic views showing a fifth example of a method for manufacturing a laminated device using the metal-filled microstructure of the embodiment of the present invention in process order, and FIGS. 72 to 76 are embodiments of the present invention. It is a schematic diagram which shows the 6th example of the manufacturing method of the laminated device using the metal-filled microstructure of the above in the order of steps. In FIGS. 59 to 76, the same components as those of the anisotropic conductive material 50 shown in FIG. 12 and the laminated device 60 shown in FIG. 13 are designated by the same reference numerals, and detailed description thereof will be omitted.

First, an anisotropic conductive material 50 having a support 46 and an anisotropic conductive member 22, and a wafer 112 provided with a rewiring layer 110 are prepared. The rewiring layer 110 has the above-mentioned interposer function.
As shown in FIG. 59, the rewiring layer 110 is arranged so as to face the anisotropic conductive member 22, and as shown in FIG. 60, the anisotropic conductive member 22 and the rewiring layer 110 are joined and electrically. Connecting.
Next, as shown in FIG. 61, the wafer 112 is separated from the rewiring layer 110.

Next, as shown in FIG. 62, the anisotropic conductive material 50 is arranged on the rewiring layer 110 with the anisotropic conductive member 22 facing each other.
Next, as shown in FIG. 63, the rewiring layer 110 and the anisotropic conductive member 22 are joined, and as shown in FIG. 64, one support 46 is separated.
Next, as shown in FIG. 65, the semiconductor element 62 is arranged so that one of the supports 46 faces the isolated anisotropic conductive member 22. Next, as shown in FIG. 66, the anisotropic conductive member 22 and the semiconductor element 62 are joined and electrically connected. Next, as shown in FIG. 67, the remaining support 46 is separated.
Next, as shown in FIG. 68, the semiconductor element 64 is arranged so that the remaining support 46 on the side where the semiconductor element 62 is not provided faces the anisotropic conductive member 22 from which the semiconductor element 62 is separated.

Next, as shown in FIG. 69, the anisotropic conductive member 22 and the semiconductor element 64 are joined and electrically connected. As a result, the semiconductor element 62 and the semiconductor element 64 can be laminated without using the TSV.
Although the semiconductor element 64 is arranged in FIG. 68, the present invention is not limited to this, and as shown in FIG. 70, the semiconductor element 64 and the semiconductor element 66 may be arranged with respect to one semiconductor element 62. Good. In this case, as shown in FIG. 71, a plurality of semiconductor elements 64 and semiconductor elements 66 are arranged in one semiconductor element 62. Also in this case, the semiconductor element 64 and the semiconductor element 66 can be laminated on the semiconductor element 62 without using the TSV.

Further, the rewiring layer 110 is not limited to being used alone, and can be used by being embedded in an organic substrate.
In this case, as shown in FIG. 72, the organic substrate 120 is arranged so as to face the rewiring layer 110 with respect to the anisotropic conductive material 50 provided with the rewiring layer 110. The organic substrate 120 functions as, for example, an interposer.
Next, as shown in FIG. 73, the organic substrate 120 is electrically connected to the rewiring layer 110 by using, for example, solder. In this case, the rewiring layer 110 may be embedded in the organic substrate 120.
Next, the support 46 is separated as shown in FIG. 74. Next, as shown in FIG. 75, the semiconductor element 62 is arranged so as to face the anisotropic conductive member 22.
Next, as shown in FIG. 76, the semiconductor element 62 is joined to the anisotropic conductive member 22 and electrically connected. As a result, it is possible to obtain a product in which the rewiring layer 110 and the semiconductor element 62 are laminated.
In the above description, the semiconductor element has been described as an example, but the present invention is not limited to this, and a semiconductor wafer may be used instead of the semiconductor element.
Further, the configuration of the semiconductor element is not particularly limited, and the above-exemplified ones can be appropriately used.

Here, temporary bonding means fixing a semiconductor element or a semiconductor wafer on an object to be bonded in a state of being aligned with the object to be bonded.
This joining refers to joining objects under predetermined conditions in a temporarily joined state. This joining refers to a state in which the joining state is not permanently released unless a special external force or the like acts on it.
By performing this joining collectively as described above, the tact time can be reduced and the productivity can be increased.

The joining method is not particularly limited to the above-mentioned method, and DBI (Direct Bond Interconnect) and SAB (Surface Activated Bond) can be used.
In the above-mentioned DBI, for example, when joining an anisotropic conductive member and a semiconductor wafer, a silicon oxide film is laminated on the anisotropic conductive member and the semiconductor wafer, and chemical mechanical polishing is performed. After that, the silicon oxide film interface is activated by plasma treatment, and the anisotropic conductive member semiconductor wafers are brought into contact with each other to bond the two.
In the above-mentioned SAB, for example, when joining an anisotropic conductive member and a semiconductor wafer, each bonding surface of the anisotropic conductive member and the semiconductor wafer is surface-treated and activated in a vacuum. In this state, the anisotropic conductive member and the semiconductor wafer are brought into contact with each other in a room temperature environment to join them. For the surface treatment, ion irradiation of an inert gas such as argon or irradiation with a neutral atom beam is used.

Further, in the case of temporarily joining the heterogeneous conductive member and the semiconductor wafer, the semiconductor wafer and the semiconductor element are inspected so that the good product and the defective product can be identified in advance, and only the good product of the semiconductor element is weird. Manufacturing loss can be reduced by joining to a non-defective portion in the semiconductor wafer via a conductive member. A non-defective semiconductor device whose quality is guaranteed is called KGD (Know Good Die).

Further, in the step of joining the semiconductor element to the element region, a plurality of semiconductor elements are temporarily joined and then all are joined together, but the present invention is not limited to this. Depending on the joining method, temporary joining may not be possible. In this case, the temporary bonding of the semiconductor element may be omitted. Further, the semiconductor elements may be bonded to the element region of the semiconductor wafer one by one.
Transport and picking of semiconductor elements and semiconductor wafers, as well as temporary bonding and main bonding, can be realized by using known semiconductor manufacturing equipment.

In the case of the above-mentioned temporary joining, the devices of Toray Engineering, Shibuya Kogyo Co., Ltd., Shinkawa Co., Ltd., Yamaha Motor Co., Ltd. and the like can be used.
Wafers of various companies such as Mitsubishi Heavy Industries Machine Tool, Bond Tech, PMT Co., Ltd., Ayumi Kogyo, Tokyo Electron (TEL), EVG, Sus Microtech Co., Ltd. (SUSS), Musashino Engineering, etc. A joining device can be used.
For each of the temporary joining and the main joining, the atmosphere at the time of joining, the heating temperature, the pressing force (load), and the processing time are listed as control factors, but it is necessary to select the conditions suitable for the device such as the semiconductor element to be used. it can.

The atmosphere at the time of joining can be selected from the atmosphere, an inert atmosphere such as a nitrogen atmosphere, and a vacuum state.
The heating temperature can be variously selected from a temperature of 100 ° C. to 400 ° C., and the heating rate can also be selected from 10 ° C./min to 10 ° C./sec according to the performance of the heating stage or the heating method. The same applies to cooling. It is also possible to heat in steps, and it is also possible to divide into several stages and sequentially raise the heating temperature to join.
Regarding the pressure (load), it is possible to select to pressurize rapidly or in steps depending on the characteristics of the resin encapsulant.

The atmosphere at the time of joining, the holding time of each of heating and pressurization, and the changing time can be appropriately set. In addition, the order can be changed as appropriate. For example, after the vacuum is reached, the first stage is pressurized, and then the temperature is raised by heating, then the second stage is pressurized to hold it for a certain period of time, and at the same time it is unloaded and cooled to below a certain temperature. It is possible to take steps such as returning to the atmosphere at the stage when it becomes.
Such a procedure can be rearranged in various ways, and may be heated in a vacuum state after being pressurized in the atmosphere, or may be evacuated, pressurized, and heated at once. Examples of these combinations are shown in FIGS. 77 to 83.
Further, if a mechanism for individually controlling the in-plane pressure distribution and heat distribution at the time of joining is used, the yield of joining can be improved.
The temporary bonding can be changed in the same manner. For example, by creating an inert atmosphere, oxidation of the electrode surface of the semiconductor element can be suppressed. It is also possible to perform bonding while adding ultrasonic waves.

77 to 83 are graphs showing first to seventh examples of the present joining conditions. 77 to 83 show the atmosphere at the time of joining, the heating temperature, the pressing force (load), and the processing time, where the reference numeral V indicates the degree of vacuum, the reference numeral L indicates the load, and the reference numeral T indicates the temperature. .. In FIGS. 77 to 83, a high degree of vacuum means a low pressure.
Regarding the atmosphere at the time of joining, the heating temperature, and the load, for example, as shown in FIGS. 77 to 79, the temperature may be increased after the load is applied in a state where the pressure is reduced. Further, as shown in FIGS. 80, 82 and 83, the timing of applying the load and the timing of raising the temperature may be matched. As shown in FIG. 81, the load may be applied after the temperature is raised. Further, as shown in FIGS. 80 and 81, the timing of reducing the pressure and the timing of raising the temperature may be matched.
The temperature may be raised in steps as shown in FIGS. 77, 78 and 82, or may be heated in two steps as shown in FIG. 83. The load may also be applied in steps as shown in FIGS. 79 and 82.
Further, the timing of reducing the pressure may be the timing of reducing the pressure as shown in FIGS. 77, 79, 81, 82 and 83, and then applying the load, and the timing of reducing the pressure as shown in FIGS. 78 and 80. And the timing of applying the load may be matched. In this case, depressurization and joining are performed in parallel.

The present invention is basically configured as described above. Although the method for producing the metal-filled microstructure and the insulating base material of the present invention have been described in detail above, the present invention is not limited to the above-described embodiment, and various improvements are made without departing from the gist of the present invention. Or, of course, you may change it.

Hereinafter, the present invention will be described in more detail with reference to examples. The materials, reagents, amounts of substances used, amounts of substances, proportions, treatment contents, treatment procedures, etc. shown in the following examples can be appropriately changed as long as they do not deviate from the gist of the present invention. Therefore, the scope of the present invention should not be construed as limited by the specific examples shown below.
In this example, the metal-filled microstructures of Examples 1 to 14 and the metal-filled microstructures of Comparative Examples 1 to 3 were produced. The number of defects, the presence or absence of voids, and the film state after plating were evaluated for the metal-filled microstructures of Examples 1 to 14 and the metal-filled microstructures of Comparative Examples 1 to 3. Table 5 below shows the evaluation results of the number of defects, the presence or absence of voids, and the film state after plating.
Hereinafter, the number of defects, the presence or absence of voids, and the film state after plating will be described.

The evaluation of the number of defects will be described.
<Evaluation of the number of defects>
After polishing one side of the manufactured metal-filled microstructure, the polished surface was observed with an optical microscope to try to find defects. Then, the number of defects was counted, the number of defects per unit area was obtained, and the number of defects was evaluated according to the evaluation criteria shown in Table 1 below. In the evaluation, it is necessary to satisfy both the evaluation criteria of 20 to 50 μm in diameter and the evaluation criteria of more than 50 μm in diameter. For example, in the evaluation AA, those having a diameter of 20 to 50 μm satisfying 0.001 to 0.1 and having a diameter of more than 50 μm were not detected.
The above-mentioned single-sided polishing was carried out as follows. First, the metal-filled microstructure manufactured on a 4-inch wafer is attached with Q-chuck (registered trademark) (manufactured by Maruishi Sangyo Co., Ltd.), and the metal-filled microstructure is subjected to arithmetic average roughness using a polishing device manufactured by MAT. (JIS (Japanese Industrial Standards) B0601: 2001) was polished to 0.02 μm. Abrasive grains containing alumina were used for polishing.

The evaluation of the presence or absence of voids will be described.
<Evaluation of the presence or absence of voids>
For the manufactured metal-filled microstructure, 10 cross sections were cut out, and FE-SEM (Field Emission Scanning Electron Microscope) images of 50,000 times the 10 fields of view were taken and observed in each cross section, and the number of voids in each field of view image was determined. I counted. Then, the number of voids per length (per 0.26 mm) was determined, and the presence or absence of voids was evaluated according to the evaluation criteria shown in Table 2 below.
The cross section was obtained by cutting using a focused ion beam (FIB).

The state of the film after plating will be described.
<Evaluation of film condition after plating>
The manufactured metal-filled microstructure was visually observed, and the film state after plating was evaluated according to the evaluation criteria shown in Table 3 below.

Hereinafter, Examples 1 to 14 and Comparative Examples 1 to 3 will be described.
(Example 1)
The metal-filled microstructure of Example 1 will be described.
[Metal-filled microstructure]
<Manufacturing of aluminum substrate>
Si: 0.06% by mass, Fe: 0.30% by mass, Cu: 0.005% by mass, Mn: 0.001% by mass, Mg: 0.001% by mass, Zn: 0.001% by mass, Ti: A molten metal containing 0.03% by mass, the balance of which is Al and an aluminum alloy of unavoidable impurities is prepared, and after the molten metal is treated and filtered, an ingot having a thickness of 500 mm and a width of 1200 mm is DC (Direct Chill). ) Made by the casting method.
Next, the surface was scraped to an average thickness of 10 mm by a surface mill, kept at 550 ° C. for about 5 hours, and when the temperature dropped to 400 ° C., the thickness was 2.7 mm using a hot rolling mill. It was made into a rolled plate.
Further, heat treatment was performed at 500 ° C. using a continuous annealing machine, and then cold rolling was performed to finish the thickness to 1.0 mm to obtain a JIS (Japanese Industrial Standards) 1050 aluminum substrate.
After forming the aluminum substrate into a wafer shape having a diameter of 200 mm (8 inches), each of the following treatments was performed.

<Electropolishing treatment>
The above-mentioned aluminum substrate was subjected to electrolytic polishing treatment under the conditions of a voltage of 25 V, a liquid temperature of 65 ° C., and a liquid flow velocity of 3.0 m / min using an electrolytic polishing liquid having the following composition.
The cathode was a carbon electrode, and the power supply was GP0110-30R (manufactured by Takasago Seisakusho Co., Ltd.). The flow velocity of the electrolytic solution was measured using a vortex flow monitor FLM22-10PCW (manufactured by AS ONE Corporation).
(Electropolishing liquid composition)
・ 85% by mass phosphoric acid (reagent manufactured by Wako Pure Chemical Industries, Ltd.) 660 mL
・ Pure water 160mL
・ Sulfuric acid 150mL
・ Ethylene glycol 30 mL

<Anodic oxidation process>
Next, the aluminum substrate after the electrolytic polishing treatment was subjected to an anodic oxidation treatment by a self-regularization method according to the procedure described in JP-A-2007-204802.
The aluminum substrate after the electrolytic polishing treatment was subjected to a pre-anodination treatment for 5 hours with an electrolytic solution of 0.50 mol / L oxalic acid under the conditions of a voltage of 40 V, a liquid temperature of 16 ° C., and a liquid flow velocity of 3.0 m / min. ..
Then, the pre-anodized aluminum substrate was subjected to a film removal treatment by immersing it in a mixed aqueous solution of 0.2 mol / L chromic anhydride and 0.6 mol / L phosphoric acid (liquid temperature: 50 ° C.) for 12 hours.
Then, the electrolytic solution of 0.50 mol / L oxalic acid was subjected to reanodination treatment for 3 hours and 45 minutes under the conditions of a voltage of 40 V, a liquid temperature of 16 ° C., and a liquid flow velocity of 3.0 m / min, and an anode having a film thickness of 30 μm An oxide film was obtained.
In both the pre-anode oxidation treatment and the re-anode oxidation treatment, the cathode was a stainless steel electrode, and the power supply was GP0110-30R (manufactured by Takasago Seisakusho Co., Ltd.). A NeoCool BD36 (manufactured by Yamato Scientific Co., Ltd.) was used as the cooling device, and a pair stirrer PS-100 (manufactured by EYELA Tokyo Rika Kikai Co., Ltd.) was used as the stirring and heating device. Further, the flow velocity of the electrolytic solution was measured using a vortex type flow monitor FLM22-10PCW (manufactured by AS ONE Corporation).

<Barrier layer removal process>
Then, under the same treatment liquid and treatment conditions as the above-mentioned anodic oxidation treatment, electrolytic treatment (electrolytic removal treatment) was performed while continuously lowering the voltage from 40 V to 0 V at a voltage drop rate of 0.2 V / sec.
After that, an etching treatment (etching removal treatment) is performed in which the aluminum substrate is immersed in 5% by mass phosphoric acid at 30 ° C. for 30 minutes to remove the barrier layer at the bottom of the micropores of the anodic oxide film, and the aluminum substrate is exposed through the micropores. I let you.

Here, the average opening diameter of the micropores, which are through holes existing in the anodic oxide film after the barrier layer removing step, was 60 nm. The average opening diameter was calculated as an average value measured at 50 points by taking a surface photograph (magnification of 50,000 times) with an FE-SEM (Field emission-Scanning Electron Microscope). The average opening diameter is referred to as "hole diameter" in Table 5 below.
The average thickness of the anodic oxide film after the barrier layer removing step was 80 μm. The average thickness was measured at 10 points by cutting the anodized film with FIB (Focused Ion Beam) in the thickness direction and taking a surface photograph (magnification of 50,000 times) of the cross section with FE-SEM. Calculated as an average value.
The density of micropores present in the anodic oxide film was about 100 million / mm ² . The density of micropores was measured and calculated by the method described in paragraphs <0168> and <0169> of JP-A-2008-270158.
The degree of regularization of the micropores present in the anodic oxide film was 92%. The degree of regularization was calculated by taking a surface photograph (magnification of 20000 times) with an FE-SEM and measuring by the method described in paragraphs <0024> to <0027> of JP-A-2008-270158.

<Metal filling process>
Next, electrolytic plating was performed once on the aluminum substrate on which the anodized film was formed, with the aluminum substrate as the cathode and platinum as the positive electrode.
Prior to electrolytic plating, an aluminum substrate on which an anodized film was formed was immersed in a plating solution for 1 minute without applying a voltage.
Prior to electrolytic plating, the above-mentioned pre-immersion is to immerse an aluminum substrate on which an anodized film is formed in a plating solution without applying a voltage. In Example 1, the pre-immersion time is 1 minute.
Specifically, for electrolytic plating, a copper plating solution having the composition shown below is used, and copper is formed inside the micropores by applying a current in the "type-0" current control pattern shown in Table 4 below. Filled.
Here, the current is applied by using the extended function of the programmable power supply (PRK45-78 (model name) manufactured by Matsusada Precision Co., Ltd.), and "Type-0", "Type-1", and "Type" shown in Table 4 below. Current control patterns of "-2", "Type-3", "Type-4" and "Pulse" were created and one of the patterns was used to apply the current. “Type-4” is a current control pattern in which the reached current value is maintained for 5 seconds between step 1 and step 2 of “type-3” and between step 2 and step 3, respectively. The maintenance time in Table 4 below indicates the time for maintaining the reached current value.
The precipitation potential was confirmed by cyclic voltammetry in the plating solution.
(Copper plating solution composition and conditions)
・ Copper sulfate 100g / L
・ Sulfuric acid 10g / L
・ Hydrochloric acid 5g / L
・ Temperature 25 ℃

<Substrate removal process>
Next, a metal-filled microstructure was prepared by dissolving and removing the aluminum substrate by immersing it in a 20 mass% mercury chloride aqueous solution (rise) at 20 ° C. for 3 hours.

(Example 2)
In Example 2, as compared with Example 1, heat treatment was performed at a temperature of 400 ° C. for 1 hour between the barrier layer removing step and the metal filling step after forming the anodic oxide film. Further, Example 2 is different from Example 1 in that the pre-immersion time is 15 minutes and that an Au (gold) electrode film is used for the positive electrode of the electrolytic plating. Other than these, Example 2 was the same as Example 1.
To form the electrode film after the heat treatment, specifically, a 0.7 g / L gold chloride aqueous solution is applied to one surface, dried at 140 ° C. for 1 minute, and further baked at 500 ° C. for 1 hour. After producing a gold plating nucleus, a precious fab ACG2000 basic solution / reduction solution (manufactured by Nippon Electroplating Engineers Co., Ltd.) was used as an electroless plating solution, and the surface was immersed for 1 hour at 50 ° C. This was done by forming an electrode film without voids.
In Example 2, the average opening diameter of the micropores was 60 nm as in Example 1, and the degree of regularization of the micropores was 92%.

(Example 3)
Example 3 was the same as that of Example 1 except that the barrier layer removing step was different from that of Example 1.
In the barrier layer removing step of Example 3, after forming the anodic oxide film, an alkaline aqueous solution in which zinc oxide was dissolved in an aqueous sodium hydroxide solution (50 g / l) so as to be 2000 ppm was used for an aluminum substrate. It was carried out by performing an etching treatment in which the mixture was immersed at ° C. for 150 seconds. As a result, the barrier layer at the bottom of the micropores of the anodic oxide film was removed, and zinc (metal M1) was simultaneously deposited on the surface of the exposed aluminum substrate.

(Example 4)
Example 4 was the same as Example 3 except that the pre-immersion time was 15 minutes as compared with Example 3.
(Example 5)
Example 5 was the same as Example 3 except that the pre-immersion time was 30 minutes as compared with Example 3.
(Example 6)
Example 6 was the same as Example 3 except that the pre-immersion time was 90 minutes as compared with Example 3.

(Example 7)
Example 7 is the same as Example 3 except that the pre-immersion time is 15 minutes and the current control pattern is "Type-1" shown in Table 4 as compared with Example 3. And said.
(Example 8)
Example 8 is the same as Example 3 except that the pre-immersion time is 15 minutes and the current control pattern is “Type-2” shown in Table 4 as compared with Example 3. And said.
(Example 9)
Example 9 is the same as Example 3 except that the pre-immersion time is 15 minutes and the current control pattern is "Type-3" shown in Table 4 as compared with Example 3. And said.

(Example 10)
Example 10 was the same as Example 3 except that the pre-immersion time was 30 minutes and the electrolytic plating was performed three times as compared with Example 3.
As shown in FIG. 22, an interval of 10 minutes was provided between each electroplating as a period in which no current was applied.
(Example 11)
Example 11 was the same as Example 3 except that the pre-immersion time was 200 minutes as compared with Example 3.

(Example 12)
Example 12 was the same as that of Example 3 except that the pre-immersion time was 30 minutes and that the plating solution was subjected to ultrasonic vibration as compared with Example 3.
In Example 12, a throw-in type ultrasonic wave generating device was thrown into the plating solution during electrolysis to apply ultrasonic waves having a frequency of 28 KHz to the plating solution. A combination of a transmitter manufactured by Honda Electronics Co., Ltd. (WD-600-28T (model)) and a throw-in oscillator unit manufactured by Honda Electronics Co., Ltd. (WS-600-28N (model)) is used as an ultrasonic wave generating device. Using.
(Example 13)
Example 13 was the same as Example 3 except that the pre-immersion time was 30 minutes and the addition of the surfactant to the plating solution was different from that of Example 3.
In Example 13, sodium lauryl sulfate was used as the surfactant, and the surfactant concentration of the plating solution was 0.2 mass ppm.
(Example 14)
Example 14 is the same as Example 3 except that the pre-immersion time is 15 minutes and the current control pattern is "Type-4" shown in Table 4 as compared with Example 3. And said.

(Comparative Example 1)
In Comparative Example 1, the pre-immersion time was 0 minutes as compared with Example 1, that is, prior to electrolytic plating, the aluminum substrate on which the anodized film was formed was soaked in the plating solution as soon as possible ( It was the same as in Example 1 except that the electrolytic plating was started within 5 seconds).
(Comparative Example 2)
In Comparative Example 2, the pre-immersion time was 0 minutes as compared with Example 3, that is, prior to electrolytic plating, the aluminum substrate on which the anodized film was formed was soaked in the plating solution as soon as possible ( It was the same as in Example 3 except that the electrolytic plating was started within 5 seconds).
(Comparative Example 3)
Comparative Example 3 was the same as that of Example 1 except that the current control pattern was a “pulse” (see FIG. 84) shown in Table 4 as compared with Example 1.

As shown in Table 1, in Examples 1 to 14, the number of defects was small, the number of voids was small, and the film condition after plating was good as compared with Comparative Examples 1 to 3.
In Comparative Example 1 and Comparative Example 2, since the pre-immersion was not performed, the supply of cations was insufficient, the number of defects was large, and the number of voids was large.
In Comparative Example 3, since the current control pattern was a pulse, the supply of cations was insufficient, the number of defects was large, and the number of voids was large.
Further, from Examples 5 and 12, the voids were further reduced by applying ultrasonic waves to the plating solution during plating.
From Examples 5 and 13, the film condition after plating was further improved by adding the surfactant to the plating solution.
From Example 4, Example 7, Example 8, Example 9, and Example 14, the void generation state differs depending on the current control pattern, and the void generation state is different from Type-0 and Type-1, Type-2 and Type-3. And type-4 had even less voids. In the current control pattern, the longer the time of step 2, the smaller the voids.

10 Aluminum substrate 10a Surface 11 Electrolysis time 12 Electrolysis time 12 Insulation base material 12 Through hole 13 Electrolysis time 13 Barrier layer 14 Insulation base material 14 Anodized film 14 Through hole 15 Metal 15a Metal layer 15b Metal 16 Conduction path 17 Structure 19 Resin layer 20 Metal-filled microstructure 21 Winding core 22 Idiosyncratic conductive member 23 Interposer 27 Hole 30 Electrolytic plating device 32 Plating tank 34 Counter electrode 36 Power supply unit 38 Control unit 39 Vibration unit 40 Insulation base material 40a Surface 40b Back surface 16a, 16b Protruding part 44 Resin layer 46 Support 47 Release layer 48 Support layer 49 Release agent 50 Heterogeneous conductive material 60 Laminated device 62 Semiconductor element 64 Laminated device 64 Semiconductor element 64a, 66a, 80a Front surface 64b, 82b Back surface 66, 72, 86, 87 Semiconductor element 74 Sensor chip 76 Lens 80 First semiconductor wafer 81 Optical waveguide 82 Second semiconductor wafer 83, 84, 85, 89, 89a Laminated device 88 Electrode 90 First laminated substrate 91 Semiconductor element 92 Semiconductor wafers 92a, 102a, 108a Surface 94 Three-dimensional bonded structure 95 Light emitting element 96 Light receiving element 100 Second laminated base 102 Second base 104 Peeling functional layer 105 Hydrophobic film 106 Third composite laminated body 108 Third Base 109 Hydrophobic film 110 Rewiring layer 112 Wafer 120 Organic substrate AQ Plating liquid Ds Lamination direction Dt Thickness direction Im Maximum value Ld Emission light Lo light S10 step S12 step S14 Step T Plating processing time Z Thickness direction h Thickness x direction

Claims (10)

A method for manufacturing a metal-filled microstructure in which a metal is filled in a plurality of the through holes of an insulating base material having a plurality of through holes penetrating in the thickness direction.
It has a metal filling step of filling a plurality of the through holes with the metal.
In the metal filling step, the insulating base material is immersed in a plating solution containing metal ions for a time of more than 5 seconds without applying a voltage, and then the current value is continuously or multi-staged. This is a step of filling a plurality of the through holes with the metal by electroplating.
A method for producing a metal-filled microstructure in which ultrasonic vibration is applied to at least one of the insulating base material and the plating solution in the metal filling step. The metal-filled microstructure according to claim 1, wherein in the metal filling step, the immersion time of immersing the insulating base material in the plating solution without applying the voltage is 1 minute or more and 150 minutes or less. Manufacturing method. When the plating processing time indicating the time from the end of immersion to the end of the electrolytic plating in a state where the voltage is not applied is T, and the maximum value of the current applied in the electrolytic plating is Im, the current is The production of the metal-filled microstructure according to claim 1 or 2 , wherein the current value is set to less than 0.05 Im during less than 0.1 T, and then the current value is increased up to the maximum value Im within less than 0.1 T. Method. The method for producing a metal-filled microstructure according to any one of claims 1 to 3 , wherein the electrolytic plating is repeatedly performed. The method for producing a metal-filled microstructure according to any one of claims 1 to 3, wherein the electroplating is repeatedly carried out with a period during which the current is not applied between the electroplating. The method for producing a metal-filled microstructure according to any one of claims 1 to 5 , wherein the insulating base material is an anodic oxide film of aluminum. The method for producing a metal-filled microstructure according to any one of claims 1 to 6 , wherein the plating solution contains a surfactant. The method for producing a metal-filled microstructure according to any one of claims 1 to 7 , wherein the main component of the solid content of the plating solution is copper sulfate. The method for producing a metal-filled microstructure according to any one of claims 1 to 8, wherein the through hole has a diameter of more than 5 nm and 10 μm or less. An insulating base material used in the method for producing a metal-filled microstructure according to any one of claims 1 to 9.

Images