JP7305770B2 - Method for manufacturing structure and method for manufacturing joined body - Google Patents

Description

TECHNICAL FIELD The present invention relates to a method for manufacturing a structure used for bonding to an object to be bonded and a method for manufacturing a bonded body using the structure, and more particularly to a structure having a plurality of projections formed on a conductive surface having conductivity. and a method for manufacturing a bonded body using the structure.

2. Description of the Related Art Currently, various methods are used for electrical connection between electronic components such as semiconductor elements and for electrical connection between electronic components and circuit boards.
Electronic parts such as semiconductor devices are undergoing remarkable downsizing. Conventional methods of directly connecting wiring boards such as wire bonding, flip chip bonding, thermocompression bonding, and the like cannot sufficiently guarantee the stability of electrical connections of electronic components. Therefore, for example, Cu/Sn bumps and adhesive underfill are used for electrical connection of electronic components. However, depending on the electronic component or circuit board to be connected, local stress is induced due to mismatch of CTE (coefficient of thermal expansion), and the reliability of electrical connection is lowered.
Further, in semiconductor devices, a connection density of tens of millions or more per die is required, and in order to meet this requirement, it is necessary to reduce the size of the bumps to a diameter of about 1 to 2 μm. However, it is difficult to reduce the size of current Cu/Sn bumps by electroplating to 5 μm or less.

Therefore, with respect to the reliability of the electrical connection described above and the required connection density, the bonding surface of the wafer constituting the semiconductor element or the semiconductor element to be connected is subjected to CMP (chemical mechanical polishing). ), a bonding method called so-called hybrid bonding has been developed (see, for example, Non-Patent Document 1).

R. Taibi, et al., “Full characterization of Cu/Cu direct bonding for 3D integration”, Electronic Components and Technology Conference (ECTC), 2010 Proceedings 60th, 2010, p.219-225

In the bonding method called hybrid bonding described in Non-Patent Document 1, it is necessary to mirror-finish the bonding surfaces of wafers, semiconductor elements, or the like by CMP (Chemical Mechanical Polishing). When mirror-finished by CMP, the Cu for electrical connection or the insulating Si is exposed, but it is necessary to precisely control the flatness of the bonding surface so that unevenness such as dishing is not formed on the bonding surface. be. As a result, there is a problem that the joining process becomes complicated.
Furthermore, in hybrid bonding, in order to ensure electrical connection at the joint, it is necessary to strictly control the environment during bonding in order to suppress contamination such as particles entering between the bonding surfaces during bonding. Therefore, there is a problem that the joining process becomes complicated. In addition, if the environmental control during bonding is neglected, the bonding surface will become contaminated, increasing the number of areas where electrical connection cannot be secured after bonding, resulting in a rapid drop in yield and making it difficult to achieve bonding that satisfies the specifications. In bonding, it is difficult to simplify the bonding process.

SUMMARY OF THE INVENTION The object of the present invention has been made in view of the above-mentioned problems based on the prior art, and a method for manufacturing a structure capable of easily achieving highly reliable bonding with an object to be bonded, and a bonded body using the bonded body. To provide a manufacturing method of

In order to achieve the above object, the present invention provides a conductive substrate having a conductive surface having conductivity, and a mold member having a portion to be filled composed of a plurality of recesses or a plurality of through holes. an applying step of bringing the portion to be filled of the mold member into contact with at least a conductive surface; and a removing step of removing the mold member, wherein between the preparing step and the removing step, the portion to be filled is electrically conductive. It has a first filling step of filling a substance, or a second filling step of filling a portion to be filled with a treatment liquid that dissolves the conductive base material, and the mold member is removed by the removing step, leaving the conductive surface with: Provided is a method of manufacturing a structure in which a plurality of electrically conductive protrusions are formed.

The conductive substance filled in the first filling step is preferably the same as the conductive substance contained in the conductive surface of the conductive substrate.
The first filling step or the second filling step is preferably performed between the preparation step and the application step.
The first filling step or the second filling step is preferably performed between the application step and the removal step.
The first filling step is a step of filling the plurality of recesses of the mold member with a conductive substance, and the applying step is a state in which the plurality of recesses of the mold member are filled with the conductive substance, and the conductive surface is filled with the mold. It is preferable that the step is to bring the concave portion of the member into contact.
The applying step is a step of bringing the plurality of through-holes of the mold member into contact with the conductive surface, and the first filling step is a step of contacting the plurality of through-holes of the mold member with the conductive surface, while the plurality of through-holes of the mold member are in contact with the conductive surface. The step of filling the through holes with a conductive substance is preferable.
The mold member is preferably composed of an anodized membrane of a valve metal with a plurality of micropores.
Preferably, the valve metal is aluminum.
In the removing step, the mold member is preferably removed by etching.

Alternatively, at least one structure manufactured by the structure manufacturing method of the present invention is prepared, and a plurality of conductive projections formed on the conductive surface of the structure are arranged facing the object to be bonded. Then, the present invention provides a method for manufacturing a joined body, which has a joining step of joining a structure and an object to be joined.
Preferably, a plurality of structures are prepared, and the joining step is a step of joining one structure out of the plurality of structures and a joining object comprising another structure out of the plurality of structures.

According to the structure manufacturing method of the present invention, it is possible to obtain a structure capable of easily achieving highly reliable bonding with an object to be bonded.
Further, according to the method for manufacturing a joined body of the present invention, it is possible to obtain a joined body that can easily achieve highly reliable joining with an object to be joined using a structure.

1 is a schematic cross-sectional view showing one step of a first example of a method for manufacturing a structure according to an embodiment of the present invention; FIG. 1 is a schematic cross-sectional view showing one step of a first example of a method for manufacturing a structure according to an embodiment of the present invention; FIG. 1 is a schematic cross-sectional view showing one step of a first example of a method for manufacturing a structure according to an embodiment of the present invention; FIG. 1 is a schematic cross-sectional view showing one step of a first example of a method for manufacturing a structure according to an embodiment of the present invention; FIG. FIG. 4 is a schematic cross-sectional view showing one step of a second example of a method for manufacturing a structure according to an embodiment of the present invention; FIG. 4 is a schematic cross-sectional view showing one step of a second example of a method for manufacturing a structure according to an embodiment of the present invention; FIG. 4 is a schematic cross-sectional view showing one step of a second example of a method for manufacturing a structure according to an embodiment of the present invention; It is a schematic cross-sectional view showing one step of the third example of the method for manufacturing the structure of the embodiment of the present invention. It is a schematic cross-sectional view showing one step of the third example of the method for manufacturing the structure of the embodiment of the present invention. 1 is a schematic cross-sectional view showing one step of a first example of a method for manufacturing a joined body according to an embodiment of the present invention; FIG. 1 is a schematic cross-sectional view showing one step of a first example of a method for manufacturing a joined body according to an embodiment of the present invention; FIG. FIG. 4 is a schematic cross-sectional view showing one step of the second example of the method for manufacturing a joined body according to the embodiment of the present invention; 1 is a schematic cross-sectional view showing an example of the configuration of a structure according to an embodiment of the invention; FIG. 1 is a schematic cross-sectional view showing one step of an example of a method for manufacturing a joined body according to an embodiment of the present invention; FIG. 1 is a schematic cross-sectional view showing one step of an example of a method for manufacturing a joined body according to an embodiment of the present invention; FIG. 1 is a schematic diagram showing a first example of a laminated device using a structure according to an embodiment of the invention; FIG. FIG. 4 is a schematic diagram showing a second example of a laminated device using the structure of the embodiment of the invention; FIG. 4 is a schematic diagram showing a third example of a laminated device using the structure of the embodiment of the invention; FIG. 5 is a schematic diagram showing a fourth example of a laminated device using the structure of the embodiment of the invention; 1 is a schematic diagram showing a step of a first example of a method for manufacturing a laminated device using a structure according to an embodiment of the invention; FIG. 1 is a schematic diagram showing a step of a first example of a method for manufacturing a laminated device using a structure according to an embodiment of the invention; FIG. 1 is a schematic diagram showing a step of a first example of a method for manufacturing a laminated device using a structure according to an embodiment of the invention; FIG. It is a schematic diagram which shows one process of the 2nd example of the manufacturing method of the laminated device using the structure of embodiment of this invention. It is a schematic diagram which shows one process of the 3rd example of the manufacturing method of the laminated device using the structure of embodiment of this invention. It is a schematic diagram which shows one process of the 3rd example of the manufacturing method of the laminated device using the structure of embodiment of this invention. 4 is a graph showing a first example of this bonding condition for a laminated device using the structure of the embodiment of the present invention; FIG. 5 is a graph showing a second example of this bonding condition for a laminated device using the structure of the embodiment of the present invention; FIG. FIG. 5 is a graph showing a third example of the actual bonding conditions for a laminated device using the structure of the embodiment of the present invention; FIG. FIG. 10 is a graph showing a fourth example of this bonding condition for a laminated device using the structure of the embodiment of the present invention; FIG. FIG. 11 is a graph showing a fifth example of the actual bonding conditions for a laminated device using the structure of the embodiment of the present invention; FIG. FIG. 11 is a graph showing a sixth example of the actual bonding conditions for a laminated device using the structure of the embodiment of the present invention; FIG. FIG. 11 is a graph showing a seventh example of the actual bonding conditions for a laminated device using the structure of the embodiment of the invention; FIG. 1 is a schematic cross-sectional view showing a first example of a semiconductor package; FIG. FIG. 4 is a schematic cross-sectional view for explaining a coaxial structure; FIG. 4 is a schematic plan view for explaining a coaxial structure; FIG. 4 is a schematic cross-sectional view showing a second example of a semiconductor package; 1 is a schematic diagram showing a first example of an electronic device using a structure according to an embodiment of the invention; FIG. FIG. 4 is a schematic diagram showing a second example of an electronic device using the structure of the embodiment of the invention; FIG. 4 is a schematic diagram showing a third example of an electronic device using the structure of the embodiment of the invention; FIG. 5 is a schematic diagram showing a fourth example of an electronic device using the structure of the embodiment of the invention;

Hereinafter, a method for manufacturing a structure and a method for manufacturing a joined body according to the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings.
It should be noted that the drawings described below are examples for explaining the present invention, and the present invention is not limited to the drawings shown below.
In the following, "~" indicating a numerical range includes the numerical values described on both sides. For example, when ε is a numerical value α to a numerical value β, the range of ε is a range including the numerical values α and β, and represented by mathematical symbols α≦ε≦β.
Angles such as "perpendicular" include the margin of error generally accepted in the relevant technical field unless otherwise specified. In addition, unless otherwise specified, the environment represented by temperature, humidity, or atmospheric pressure also includes an error range that is generally allowed in the relevant technical field.

Here, a structure has an electrode or an element region. Examples of those having electrodes include, for example, a semiconductor element that performs a specific function by itself, but also includes a semiconductor element that performs a specific function by combining a plurality of elements. Furthermore, wiring members and the like that only transmit electrical signals are included, and printed wiring boards and the like are also included in those having electrodes.
The device region is a region in which various device configuration circuits and the like are formed for functioning as an electronic device. In the element region, for example, memory circuits such as flash memories, regions in which logic circuits such as microprocessors and FPGAs (field-programmable gate arrays) are formed, communication modules such as wireless tags, and wiring are formed. area. In addition to this, MEMS (Micro Electro Mechanical Systems) may be formed in the element region. MEMS include, for example, sensors, actuators and antennas. Sensors include, for example, various sensors such as acceleration, sound, and light.
As described above, in the element region, an element configuration circuit and the like are formed, and electrodes (not shown) are provided for electrically connecting the semiconductor chip to the outside. The element region has an electrode region in which electrodes are formed. The electrodes in the element region are, for example, Cu posts. An electrode area is basically an area that includes all electrodes formed. However, if the electrodes are discretely provided, the area where each electrode is provided is also called the electrode area.
The structure may be in the form of individual pieces such as semiconductor chips, in the form of semiconductor wafers, or in the form of wiring layers.
Also, the structure may be a heat sink, and is not limited to the above-described semiconductor element or the like.
The structure is bonded to the object to be bonded, but the object to be bonded is not particularly limited. become things.

[First Example of Method for Manufacturing Structure]
1 to 4 are schematic cross-sectional views showing a first example of a method for manufacturing a structure according to an embodiment of the present invention in order of steps.
First, in the method for manufacturing a structure, a preparation step of preparing a conductive base material having a conductive surface having conductivity, and a mold member having a portion to be filled composed of a plurality of recesses or a plurality of through holes. implement.
In the first example of the method for manufacturing the structure shown in FIGS. 1 to 4, the conductive substrate having a conductive surface having conductivity is provided on the semiconductor element 10 as shown in FIG. An example of the conductive layer 12 that has been formed will be described. The conductive layer 12 constitutes a conductive substrate, and the surface 12a of the conductive layer 12 is a conductive surface. Incidentally, the conductive layer 12 is formed on an element region (not shown) of the semiconductor element 10 .
As shown in FIG. 2, the mold member 14 has, for example, a plurality of through holes 15b passing through the substrate 15a in the thickness direction. The portion to be filled 15 is configured by the plurality of through holes 15b.
The mold member 14 is used to form a plurality of protrusions, which will be described later. The diameter d of the through-holes 15b of the mold member 14 and the width w of the base material 15a representing the interval between the through-holes 15b are appropriately determined according to the size of the protrusions to be formed.

For example, the surface 10a of the semiconductor device 10 has a device region (not shown). In the conductive layer forming step, the conductive layer 12 is formed on the element region of the surface 10 a of the semiconductor element 10 .
The conductive layer 12 is formed by forming a resist layer (not shown) on the surface 10a of the semiconductor element 10, and removing the resist layer on the element region by, for example, patterning using photolithography. Next, for example, a seed layer (not shown) is formed on the resist layer, and the conductive layer 12 is formed by plating. When forming the conductive layer 12, the surfaces of the resist layer and the conductive layer 12 are flattened by a planarization process. Although the conductive layer 12 is formed by plating, the method of forming the conductive layer 12 is not particularly limited. However, it is preferable to use a film formation method with a low temperature, because a film formation method with a high temperature raises the temperature of the element region and leads to a failure or the like. For example, it is preferable to place the semiconductor element or the like on a cooling plate and maintain the temperature of the insulating support at 60° C. or less to form the electrodes.

Next, as shown in FIG. 2, an application step is performed in which the filling portion 15 of the mold member 14 is brought into contact with at least the conductive surface, that is, the surface 12a of the conductive layer 12. Next, as shown in FIG. The mold member 14 shown in FIG. 2 has a plurality of through holes 15b as described above, and the base material 15a has an open surface 15c opposite to the surface 12a of the conductive layer 12. As shown in FIG.
Next, as shown in FIG. 3, a first filling step is performed in which the filling portion 15 of the mold member 14 is filled with the conductive material 16 while the filling portion 15 of the mold member 14 is in contact with the conductive surface. implement. More specifically, in the first filling step, while the plurality of through holes 15b of the mold member 14 are in contact with the surface 12a of the conductive layer 12, the plurality of through holes 15b of the mold member 14 are filled from the opposite surface 15c. A conductive material 16 is filled in the hole 15b.

The method of filling the plurality of through-holes 15b with the conductive substance 16 in the first filling step is not particularly limited as long as the plurality of through-holes 15b can be filled with the conductive substance 16. method, sputtering method, or the like can be used. Other than this, for example, an inkjet method, a transfer method, a spray method, a screen printing method, or the like can be used.
In addition, in the first filling step, it is preferable to fill the semiconductor element 10 with the conductive material at a temperature of 60° C. or less. Even when the temperature is high when the conductive substance is filled, the temperature of the element region rises, leading to failures, etc. Therefore, it is preferable to set the temperature to 60° C. or less.

Depending on the properties of the conductive substance 16 and the like, the filled portion 15 of the mold member 14 is held in contact with the surface 12a of the conductive layer 12 as shown in FIG. If the conductive substance 16 is photocurable, the conductive substance 16 is irradiated with light necessary for curing. Also, if the conductive substance 16 is thermosetting, the conductive substance 16 is heated. When heating, for example, the conductive material 16 is heated while cooling the semiconductor element 10 so that the temperature of the element region does not rise.
After the conductive material 16 in the through-holes 15b is solidified and stabilized, the mold member 14 is removed by a removal step. In the removing step, for example, the mold member 14 is removed by etching. The removal step removes the mold member 14 to form a plurality of conductive protrusions on the conductive surface. Thereby, as shown in FIG. 4, a structure 18 in which a plurality of projecting portions 17 are formed on the conductive layer 12 can be obtained.
The plurality of protruding portions 17 are responsible for joining with the object to be joined, and have a function of electrical conductivity with the object to be joined. A conductive member 19 is configured by the conductive layer 12 and the plurality of protrusions 17 .
Since the protruding portion 17 is formed using the through hole 15b as a mold or mask, the diameter Dc of the protruding portion 17 is defined by the diameter d of the through hole 15b. The height H of the projecting portion 17 is determined by the amount of the conductive material 16 filled into the through hole 15b or the thickness h of the mold member 14. As shown in FIG. The interval Wc of the gap 17a of the protruding portion 17 is determined by the width w of the base material 15a. Therefore, the size of the projecting portion 17 can be adjusted by adjusting the dimensions of each portion of the mold member and the filling amount of the conductive material.

The mold member 14 is made of, for example, an anodized film. In this case, the plurality of through-holes 15b of the mold member 14 are a plurality of micropores extending in the thickness direction of the anodized film and penetrating therethrough. In the anodized film, the number of micropores, the density of micropores, and the diameter of micropores can be controlled by adjusting the anodization process.
The anodized film is composed of, for example, an anodized film of a valve metal, such as aluminum. If the valve metal is aluminum, the anodized film is composed of aluminum oxide.

In the structure 18, a bonded body can be obtained by aligning and bonding with the object to be bonded. By providing a plurality of projecting portions 17, even if there is unevenness in the bonding surface, the projecting portions 17 follow the unevenness of the bonding surface. Therefore, mirror surface treatment by CMP, which is necessary in the hybrid bonding described above, is not required. Moreover, since the plurality of protruding portions 17 follow the unevenness of the bonding surface, highly reliable bonding can be realized. Furthermore, the environment during bonding does not need to be strictly controlled, and can be selected from atmosphere, an inert atmosphere such as a nitrogen atmosphere, and a reduced-pressure atmosphere including a vacuum atmosphere. Moreover, a normal wafer bonding apparatus can be used. In this way, the structure obtained by the above-described manufacturing method can easily achieve highly reliable bonding with the object to be bonded.

[Second example of method for manufacturing structure]
5 to 7 are schematic cross-sectional views showing a second example of the method for manufacturing the structure according to the embodiment of the present invention in order of steps. 5 to 7, the same components as in the manufacturing method of the structure shown in FIGS. 1 to 4 are denoted by the same reference numerals, and detailed description thereof will be omitted.
In the second example of the structure manufacturing method, as compared with the first example of the structure manufacturing method, as shown in FIG. and the timing of filling the conductive material is different, and other steps are the same as those of the first example of the structure manufacturing method.
In the second example of the structure manufacturing method, as shown in FIG. , the step of bringing the filled portion 15 of the mold member 20 into contact with the surface 12a of the conductive layer 12 is carried out.

A mold member 20 shown in FIG. 6 has a plurality of recesses 21 formed in a base material 22 , and a bottom portion 23 common to the plurality of recesses 21 . For this reason, the mold member 20 is different from the mold member 14 shown in FIG. cannot be filled into Therefore, after preparing the mold member 20 as shown in FIG. 6, as a first filling step, as shown in FIG. implement. This makes it possible to carry out the application step described above. In this case, as the conductive substance 16, it is preferable to use a substance that does not harden until it comes into contact with the surface 12a of the conductive layer 12 in the application process.

In the second example of the structure manufacturing method, as shown in FIG. After contacting the recesses 21 of the mold member 20, the mold member 20 is removed. As a result, the structure 18 shown in FIG. 4 can be obtained in the second example of the structure manufacturing method as well as in the first example of the structure manufacturing method.
In the second example of the structure manufacturing method, the diameter Dc of the protrusion 17 is defined by the diameter dt of the recess 21 . Also, the height H of the protruding portion 17 is determined by the filling amount of the conductive material 16 in the recess 21 or the length ht of the recess 21 of the mold member 20 . The width Wc of the gap 17a between the protrusions 17 is determined by the width wt of the base material 22. As shown in FIG. Therefore, the size of the projecting portion 17 can be adjusted by adjusting the dimensions of each portion of the mold member and the filling amount of the conductive material.

[Third Example of Method for Manufacturing Structure]
8 and 9 are schematic cross-sectional views showing a third example of the method for manufacturing the structure according to the embodiment of the present invention in order of steps. 8 and 9, the same components as in the manufacturing method of the structure shown in FIGS. 1 to 4 are denoted by the same reference numerals, and detailed description thereof will be omitted.
The third example of the structure manufacturing method dissolves the surface 12a of the conductive layer 12 to form a plurality of protrusions 17, unlike the second example of the structure manufacturing method.
In the third example of the structure manufacturing method, as shown in FIG. A step of bringing the filled portion 15 of the mold member 20 into contact with the surface 12 a of the conductive layer 12 is performed.
The treatment liquid 16 a does not dissolve the mold member 20 but dissolves the conductive layer 12 . For example, when the mold member 20 is made of an anodized aluminum film and the conductive layer 12 is made of copper, a nitric acid aqueous solution is used as the treatment liquid 16a.
The mold member 20 with the plurality of recesses 21 filled with the treatment liquid 16 a is removed from the surface 12 a of the conductive layer 12 . Thereby, as shown in FIG. 9, a structure 18 in which a plurality of projecting portions 17 are formed on the conductive layer 12 can be obtained.

Note that the structure manufacturing method may include the above-described first filling step or the above-described second filling step between the preparation step and the removal step. Thus, the first filling step or the second filling step is performed between the preparation step and the application step, or between the application step and the removal step.
In the application step of contacting the mold member to the surface 12a of the conductive layer 12, the mold member may be adhered to the surface 12a of the conductive layer 12 with an adhesive, and the mold member may be pressed against the surface 12a of the conductive layer 12. It may be pressed.
The process of removing the mold member is not particularly limited, and examples thereof include etching, physical peeling of the mold member by applying force, and removal of the force pressing the mold member.

[First Example of Method for Manufacturing Joined Body]
A method for manufacturing a bonded body includes preparing at least one structure, arranging a plurality of conductive projections formed on a conductive surface of the structure toward an object to be bonded, and forming the structure and the object to be bonded. It has a joining step of joining the . Further, in the method for manufacturing a joined body, a plurality of structures are prepared, and in the joining step, one structure out of the plurality of structures and another structure out of the plurality of structures are joined to an object to be joined. You may have a joining process to join.

10 and 11 are schematic cross-sectional views showing the order of steps in a first example of the method for manufacturing a joined body according to the embodiment of the present invention. 10 and 11, the same components as in the manufacturing method of the structure shown in FIGS. 1 to 4 are denoted by the same reference numerals, and detailed description thereof will be omitted.
In a first example of the method of manufacturing a joined body, for example, two structures 18 are prepared.
Then, as shown in FIG. 10, in the two structures 18, the plurality of protruding portions 17 formed on the surface 12a of the conductive layer 12 are arranged to face each other, and the structures 18 are heated and pressurized. A joining step of joining is carried out. By heating and pressurizing, the facing protruding portions 17 are brought into contact with each other and joined together. As a result, as shown in FIG. 11, the conductive layers 12 are bonded to each other to obtain a bonded body 26 in which the two structural bodies 18 are bonded.

In the first example of the manufacturing method of the joined body, the mirror-finishing by CMP, which is required in the hybrid bonding described above, is unnecessary. Moreover, since the plurality of protruding portions 17 follow the unevenness of the bonding surface, highly reliable bonding can be achieved. Furthermore, the environment during bonding does not need to be strictly controlled, and can be selected from atmosphere, an inert atmosphere such as a nitrogen atmosphere, and a reduced-pressure atmosphere including a vacuum atmosphere. Moreover, a normal wafer bonding apparatus can be used. As described above, in the above-described method for manufacturing a joined body, it is possible to easily achieve a highly reliable joint with the object to be joined.

[Second Example of Method for Manufacturing Joined Body]
FIG. 12 is a schematic cross-sectional view showing one step of the second example of the method for manufacturing a joined body according to the embodiment of the present invention. 12, the same components as in the manufacturing method of the structure shown in FIGS. 1 to 4 are denoted by the same reference numerals, and detailed description thereof will be omitted.
Compared to the first example of the method of manufacturing a bonded structure, the second example of the method of manufacturing a bonded structure uses only one structure 18, and a semiconductor in which the conductive layer 12 is formed on the bonding target. The difference is that the element 10 is used, and the other steps are the same as those of the first example of the manufacturing method of the joined body.
A structure 18 and a semiconductor element 10 to be bonded are prepared. Then, as shown in FIG. 12, a plurality of protruding portions 17 formed on the surface 12a of the conductive layer 12 of the structure 18 are arranged facing the surface 12a of the conductive layer 12 of the semiconductor element 10, which is the object to be bonded. , a bonding step of bonding the structure 18 and the semiconductor element 10, which is the object to be bonded, is performed. Thereby, the joined body 26 shown in FIG. 11 can be obtained.

In the second example of the manufacturing method of the bonded body, since one structure 18 has a plurality of protrusions 17, even if the surface 12a of the conductive layer 12 of the semiconductor element 10, which is the object to be bonded, has unevenness, the protrusions Since 17 follows the unevenness of the surface 12a of the conductive layer 12, mirror finishing by CMP, which is required in the hybrid bonding described above, is not required. Moreover, since the plurality of protruding portions 17 follow the unevenness of the bonding surface, highly reliable bonding can be achieved. Furthermore, the environment during bonding does not need to be strictly controlled, and can be selected from atmosphere, an inert atmosphere such as a nitrogen atmosphere, and a reduced-pressure atmosphere including a vacuum atmosphere. Moreover, a normal wafer bonding apparatus can be used. As described above, in the above-described method for manufacturing a joined body, it is possible to easily achieve a highly reliable joint with the object to be joined.
Each step of the structure manufacturing method will be further described below.

[Preparation process]
The preparation step is a step of preparing a conductive substrate having a conductive surface having conductivity as described above.
Moreover, the preparation step includes a step of preparing a mold member having a portion to be filled which is composed of a plurality of recesses or a plurality of through holes as described above.
Here, preparing a conductive base material means purchasing a commercially available product such as a semiconductor element having electrodes formed thereon, purchasing a conductive base material for which production is requested, and furthermore, manufacturing a conductive base material. including.
Preparing a mold member includes purchasing a commercially available product, purchasing a mold member for which production is requested, and further manufacturing the mold member, as in the case of the conductive base material.

<Conductive substrate>
The conductive substrate is not particularly limited to the conductive layer 12 shown in FIG. 1 as long as it has a conductive surface having conductivity. include.
The form of the conductive substrate is not particularly limited, and may be a conductive layer such as an electrode formed on a pieced piece such as a semiconductor chip, or formed on various wafers such as a silicon wafer. It may be in the form of a conductive layer such as an electrode provided on a wiring layer, or in the form of a conductive layer such as an electrode provided on a wiring layer.
A metal layer provided for bonding the heat sink to another member is also included in the conductive substrate. The semiconductor element 10 shown in FIG. 1 described above may be used as a heat sink.

A conductive surface having electrical conductivity supplies current or voltage to the semiconductor element 10 (see FIG. 1) or the like. A conductive surface is, for example, the surface of a conductive layer such as an electrode. In addition, the conductive surface is not particularly limited as long as it has conductivity.
The electrical conductivity of the conductive surface is achieved by the included conductive material. The conductive substance is not particularly limited as long as it has conductivity, and may be, for example, a metal or an alloy, but may also be a conductive resin or the like. The conductive material may be contained in the conductive surface in the form of particulates, eg nanoparticles.
When the conductive surface is composed of a conductive layer such as an electrode, the conductive layer is provided in the element region or the wiring region of the semiconductor device, and supplies current or voltage to the device region or the wiring region or the like. It extracts current or voltage to a region or wiring region.

<Mold member>
The mold member is a member for forming a plurality of conductive projections on a conductive surface, and functions as a mold for forming the projections.
The configuration of the mold member is particularly limited if the conductive material can be supplied in a specific shape to the conductive surface having conductivity, or if the conductive surface having conductivity can be melted into a specific shape. not a thing
As shown in FIG. 2, the mold member may have a plurality of through holes 15b penetrating through the substrate 15a in the thickness direction. In this form, the conductive material 16 is filled in the through holes 15b as shown in FIG.
Moreover, as a mold member, as shown in FIG. In this form, a plurality of recesses 21 are filled with conductive material 16 . Further, when the conductive layer 12 is to be dissolved, the recess 21 is filled with the treatment liquid 16a.
In the mold member, the cross-sectional shape in the direction perpendicular to the length direction of the through-hole is not particularly limited, but is preferably circular. The cross-sectional shape of the concave portion in the direction orthogonal to the length direction is not particularly limited, but a circular or honeycomb shape is preferable.

The mold member can be made of, for example, glass such as quartz glass, fine porous alumina, or an anodized film.
The mold member is preferably made of an anodic oxide film of a valve metal because it facilitates the formation of through-holes or recesses having a desired average opening diameter.
Specific examples of valve metals include aluminum, tantalum, niobium, titanium, hafnium, zirconium, zinc, tungsten, bismuth, and antimony. Among these, the anodized film of aluminum is preferable because it has good dimensional stability and is relatively inexpensive. Therefore, it is preferable to form the anodized film using aluminum as the valve metal.

<Aluminum>
Aluminum is not particularly limited, and specific examples thereof include pure aluminum and aluminum alloys containing aluminum as a main component and a small amount of foreign elements.
Among aluminum, the purity of aluminum is preferably 99.5% by mass or more, more preferably 99.9% by mass or more, and even more preferably 99.99% by mass or more. When the aluminum purity is within the above range, the regularity of the through-hole arrangement is sufficient.

Moreover, when forming an anodized film with aluminum, it is preferable that the surface to be anodized is previously subjected to heat treatment, degreasing treatment and mirror finish treatment.
Here, the heat treatment, the degreasing treatment and the mirror finish treatment can be performed in the same manner as the treatments described in paragraphs [0044] to [0054] of JP-A-2008-270158.

<Anodizing treatment>
A conventionally known method can be used for the anodizing treatment, but from the viewpoint of increasing the regularity of the arrangement of the through holes or the arrangement of the recesses, it is preferable to use a self-ordering method or a constant voltage treatment.
Here, with regard to the self-ordering method of the anodizing treatment and the constant voltage treatment, the same treatments as those described in paragraphs [0056] to [0108] and [Fig. can apply.
The average flow velocity of the electrolytic solution in the anodizing treatment is preferably 0.5 to 20.0 m/min, more preferably 1.0 to 15.0 m/min, and more preferably 2.0 to 10.0 m/min. More preferably, it is min.
The method of flowing the electrolytic solution under the above conditions is not particularly limited, but for example, a method using a general stirring device such as a stirrer is used. In particular, it is preferable to use a stirrer that can control the stirring speed by digital display, because the average flow speed can be controlled. Such a stirring device includes, for example, "Magnetic Stirrer HS-50D (manufactured by AS ONE)".

For the anodizing treatment, for example, a method can be used in which an electric current is passed through the conductive layer as a cathode and the valve metal layer as an anode as described above in a solution having an acid concentration of 1 to 10% by mass.
The solution used for anodizing treatment is preferably an acid aqueous solution, more preferably sulfuric acid, phosphoric acid, chromic acid, oxalic acid, benzenesulfonic acid, amidosulfonic acid, glycolic acid, tartaric acid, malic acid, citric acid, or the like. Preferred are sulfuric acid, phosphoric acid and oxalic acid. These acids can be used alone or in combination of two or more.

The conditions for the anodizing treatment vary depending on the electrolyte used and cannot be determined indiscriminately. It is preferable that the density is 0.01 to 20 A/dm ² , the voltage is 3 to 300 V, the electrolysis time is 0.5 to 30 hours, the electrolyte concentration is 0.5 to 15% by mass, the liquid temperature is -5 to 25° C., and the current density. more preferably 0.05 to 15 A/dm ² , voltage of 5 to 250 V, electrolysis time of 1 to 25 hours, electrolyte concentration of 1 to 10% by mass, liquid temperature of 0 to 20° C., current density of 0.1 to 10 A. /dm ² , a voltage of 10 to 200 V, and an electrolysis time of 2 to 20 hours.

[Holding process]
The method for producing an anodized film may have a holding step. In the holding step, after the above-described anodizing treatment step, a voltage of 95% or more and 105% or less of the holding voltage selected from the range of 1 V or more and less than 30% of the voltage in the above-mentioned anodizing treatment step is applied for a total of 5 minutes or more This is the process of holding. In other words, in the holding step, after the above-described anodizing treatment step, the total voltage is 95% or more and 105% or less of the holding voltage selected from the range of 1 V or more and less than 30% of the voltage in the above-mentioned anodizing treatment step. This is a step of applying electrolytic treatment for 5 minutes or more.
Here, "the voltage in the anodizing process" is the voltage applied between the valve metal layer and the conductive layer. For example, if the electrolysis time by the anodizing process is 30 minutes, It is the average value of the applied voltage.

From the viewpoint of controlling the sidewall thickness of the anodized film, that is, the thickness of the barrier layer to an appropriate thickness with respect to the depth of the through-hole, the voltage in the holding step should be 5% or more and 25% or less of the voltage in the anodization treatment. It is preferably 5% or more and 20% or less.

In order to further improve the in-plane uniformity, the total holding time in the holding step is preferably 5 minutes or more and 20 minutes or less, more preferably 5 minutes or more and 15 minutes or less, and 5 minutes or more. It is more preferably 10 minutes or less.
The holding time in the holding step may be 5 minutes or more in total, but preferably 5 minutes or more continuously.

Furthermore, the voltage in the holding step may be set by dropping continuously or stepwise from the voltage in the anodizing step to the voltage in the holding step. It is preferable to set the voltage to 95% or more and 105% or less of the holding voltage within 1 second after the process is completed.

The above-described holding step can also be performed continuously with the above-described anodizing step, for example by lowering the electrolytic potential at the end of the above-described anodizing step.
In the holding step described above, the electrolytic solution and treatment conditions similar to those of the above-described conventionally known anodizing treatment can be adopted, except for the electrolytic potential.
In particular, when the holding step and the anodizing treatment step are continuously performed, it is preferable to use the same electrolytic solution for treatment.

The method for removing the barrier layer is not particularly limited. For example, a method of electrochemically dissolving the barrier layer at a potential lower than the potential in the anodizing treatment in the anodized film forming step (hereinafter also referred to as "electrolytic removal treatment"). ), a method of removing the barrier layer by etching (hereinafter also referred to as “etching removal treatment”), a method combining these (in particular, after performing electrolytic removal treatment, the remaining barrier layer is removed by etching removal treatment. method) and the like.
In the case where the mold member has a concave portion with a bottom instead of a through hole, it is not necessary to remove the barrier layer. When the valve metal layer is anodized to produce the mold member, the valve metal layer that has not been anodized may be left.

<Electrolytic removal treatment>
The electrolytic removal treatment is not particularly limited as long as the electrolytic treatment is performed at a potential lower than the potential (electrolytic potential) in the anodizing treatment in the anodized film forming step.
The electrolytic dissolution treatment can be performed continuously with the anodizing treatment, for example, by lowering the electrolytic potential at the end of the anodized film forming step.

For the electrolytic removal treatment, the same electrolytic solution and treatment conditions as those of the above-described conventionally known anodizing treatment can be employed except for the electrolytic potential.
In particular, when the electrolytic removal treatment and the anodizing treatment are continuously performed as described above, it is preferable to use the same electrolytic solution for the treatment.

<Etching removal treatment>
Although the etching removal treatment is not particularly limited, it may be a chemical etching treatment in which an acid aqueous solution or an alkaline aqueous solution is used for dissolution, or a dry etching treatment.
<Chemical etching treatment>
Removal of the barrier layer by chemical etching treatment is performed, for example, by immersing the structure after the anodization treatment in an acid aqueous solution or an alkaline aqueous solution, filling the inside of the through holes with the acid aqueous solution or the alkaline aqueous solution, and then removing the through holes of the anodized film. In this method, the surface on the opening side of the layer is brought into contact with a pH (hydrogen ion index) buffer solution, and only the barrier layer can be selectively dissolved.

<Dry etching treatment>
For the removal of the barrier layer by dry etching, it is preferable to use gas species such as Cl ₂ /Ar mixed gas.

[First filling step]
The first filling step is a step of filling the through holes or recesses of the mold member with a conductive material.

<Conductive substance>
The metal to be filled as the conductive material is preferably a material having an electrical resistivity of 10 ³ Ω·cm or less. Specific examples thereof include gold (Au), silver (Ag), copper (Cu), Preferred examples are aluminum (Al), magnesium (Mg), nickel (Ni), zinc (Zn), and the like.
Among these, Cu, Au, Al, and Ni are preferred, Cu and Au are more preferred, and Cu is even more preferred, from the viewpoint of electrical conductivity.

The conductive substance filled in the first filling step is preferably the same as the conductive substance contained in the conductive surface of the conductive substrate. For example, if the conductive surface is composed of copper, the conductive material filled in the first filling step is preferably copper. In this case, the plurality of protrusions are made of copper. By using the same conductive material contained in the conductive surface and the conductive material to be filled, for example, the connection between the conductive layer and the plurality of protrusions is improved, and an increase in electrical resistance can be suppressed. Furthermore, the occurrence of electromigration can also be suppressed. As a result, disconnection of the joint between the projecting portion and the conductive layer is suppressed, and the electrical reliability of the joint of the joined body and the physical reliability of the joint and the like are improved.

In the first filling step, it is described that metal is filled, but the protruding portion is not limited to metal, and may be an oxide conductor or the like as long as it is a conductive material. Therefore, instead of metal, for example, indium-doped tin oxide (ITO) or the like may be filled.
However, metal is superior in ductility and the like compared to oxide conductors and is easily deformed, and is easily deformed even when compressed during bonding. Among the metals, Cu and Au are more preferable because they are metals that have the property of being easily deformed by compression in addition to the above-described electrical conductivity, and Cu is more preferable in consideration of cost and the like.
Moreover, as the conductive substance, a conductive resin containing nanoparticles such as Cu or Ag can be used in addition to the metal.

<Filling method>
Electroplating or electroless plating, for example, can be used as a plating method for filling the inside of the through-holes or recesses of the mold member with the metal described above.
Here, it is difficult to selectively deposit (grow) a metal in the pores with a high aspect ratio by the conventionally known electroplating method used for coloring or the like. It is considered that this is because the deposited metal is consumed in the pores and the plating does not grow even if electrolysis is performed for a certain period of time or longer.

Therefore, when metal is filled by electroplating, it is necessary to provide a rest time during pulse electrolysis or constant potential electrolysis. The pause time should be 10 seconds or more, preferably 30 to 60 seconds.
It is also desirable to apply ultrasonic waves to promote agitation of the electrolyte.
Furthermore, the electrolysis voltage is usually 20 V or less, preferably 10 V or less, but it is preferable to measure the deposition potential of the target metal in the electrolyte to be used in advance and perform constant potential electrolysis within +1 V of the potential. When performing constant potential electrolysis, it is desirable to use cyclic voltammetry together, and a potentiostat device such as Solartron, BAS, Hokuto Denko, and IVIUM can be used.

A conventionally known plating solution can be used as the plating solution.
Specifically, when copper is deposited, an aqueous solution of copper sulfate is generally used, and the concentration of copper sulfate is preferably 1 to 300 g/L, more preferably 100 to 200 g/L. more preferred. In addition, the addition of hydrochloric acid to the electrolytic solution can promote the deposition. In this case, the hydrochloric acid concentration is preferably 10-20 g/L.
When depositing gold, it is desirable to use a sulfuric acid solution of tetrachlorogold and perform plating by alternating current electrolysis.

It should be noted that, in the electroless plating method, it takes a long time to completely fill the metal into the pores composed of high-aspect micropores, so in the manufacturing method of the present invention, it is desirable to fill the metal by the electroplating method. .

When filling the recesses of the mold member with the conductive substance, for example, the recesses of the mold member are filled with the conductive substance by using an inkjet method, a transfer method, a spray method, a screen printing method, or the like.

[Second filling step]
The second filling step is a step of filling the concave portions with a treatment liquid that dissolves the conductive substrate.
<Processing liquid>
The treatment liquid dissolves the conductive substrate without dissolving the mold member.
The treatment liquid is not particularly limited as long as it dissolves the conductive base material without dissolving the mold member as described above. When the surface is made of copper, a nitric acid aqueous solution or an alkaline aqueous solution such as a NaOH aqueous solution and a KOH (potassium hydroxide) aqueous solution can be used as the treatment liquid. When the mold member is made of aluminum oxide and the conductive surface is made of aluminum, the treatment liquid can be an aqueous chromic acid solution or an aqueous nitric acid solution.

<Filling method>
When filling the concave portions of the mold member with the treatment liquid, for example, the concave portions of the mold member are filled with the treatment liquid using an inkjet method, a transfer method, a spray method, a screen printing method, or the like. Alternatively, the mold member may be immersed in the treatment liquid to fill the plurality of recesses with the treatment liquid.

[Applied process]
The applying step is a step of bringing the portion of the mold member to be filled into contact with at least the conductive surface. The contact method in the application step is not particularly limited. In the application step, as described above, the mold member may be adhered to the surface of the conductive layer using an adhesive, or the portion to be filled of the mold member may be pressed against the surface of the conductive layer for pressure contact. .
As mentioned above, the application step may involve a treatment depending on the nature of the conductive material 16 that is filled. For example, if the filled conductive substance is a photocurable material, the conductive substance is irradiated with light necessary for curing. If the electrically conductive material is a thermosetting material, the electrically conductive material is heated. When heating, it is preferable to heat the conductive material while cooling the semiconductor element, for example, so that the temperature of the element region does not rise.

[Removal process]
The removing step is the step of removing the mold member as described above. The removing step removes the mold member to form a plurality of conductive projections on the conductive surface.
The step of removing the mold member is not particularly limited. For example, the mold member can be dissolved and removed by etching. A processing liquid that dissolves the mold member but does not dissolve the plurality of protrusions is used for the etching. When the mold member is aluminum oxide and the protrusion is copper, for example, NaOH (sodium hydroxide) is used as the treatment liquid.
In addition to the etching described above, for example, when the mold members are adhered with an adhesive, force may be applied to physically separate the mold members. The mold member may be peeled off after loading.
The removal of the mold member is not particularly limited as long as it can be removed without damaging the protruding portion to be formed.

[Structure]
As described above, a plurality of protrusions having conductivity are formed on the conductive surface of the conductive base material. ), a plurality of protrusions 17 are formed on the surface. The projections 17 follow the unevenness of the bonding surface even if the bonding surface with the object to be bonded has unevenness, so the above-described hybrid bonding does not require mirror finishing by CMP. Moreover, since the plurality of protruding portions 17 follow the unevenness of the bonding surface, it is possible to achieve bonding with high reliability in terms of bonding strength and conductivity.

<Protrusion>
The interval Wc of the gap between the protruding portions of the structure is appropriately determined according to the objects to be joined and the like. For example, it is 30 μm or less, preferably 5 nm to 800 nm, more preferably 10 nm to 200 nm, even more preferably 50 nm to 140 nm.
Here, the interval Wc of the gap between the protruding portions is the width w of the substrate between the adjacent through-holes (see FIG. 2) when the through-holes are formed. If formed with recesses, it is the width wt of the substrate between adjacent recesses (see FIG. 6).
The gap Wc (see FIG. 4) between the protrusions is obtained by obtaining a cross-sectional image of the protrusion using a field emission scanning electron microscope, and measuring the gap between adjacent protrusions at 10 points based on the cross-sectional image. and is the average value measured.

<Other shapes>
The protrusion is columnar. The projecting portion preferably has a columnar shape because it can increase the contact area with the joint surface. The diameter Dc of the protrusion may be 30 μm or less, preferably 5 μm or less, more preferably 20 nm to 1000 nm, and even more preferably 100 nm or less.
The height H of the protrusion is preferably 30 nm to 500 nm, and more preferably 100 nm or less as the upper limit.
The diameter Dc of the protrusion and the height H of the protrusion are obtained by obtaining a cross-sectional image of the protrusion using a field emission scanning electron microscope as described above, and determining the diameter Dc and the height H of the protrusion based on the cross-sectional image. is the average value obtained by measuring the height of each at 10 points.

Preferably, the protrusions are electrically insulated without contacting each other. The density of the protrusions is preferably 20,000/mm ² or more, more preferably 2,000,000/mm ² or more, still more preferably 10,000,000/mm ² or more, and 50,000,000. /mm ² or more is particularly preferable, and 100 million/mm ² or more is most preferable.

Further, the center-to-center distance between adjacent protrusions can be the same as the gap spacing Wc between the protrusions, for example. The center-to-center distance is preferably 5 nm to 800 nm, more preferably 10 nm to 200 nm, even more preferably 50 nm to 140 nm.

<Conductive substance>
The protruding portion is made of a conductive material that fills the above-described portion to be filled.

<Resin layer>
The projecting portion may be provided with a resin layer (not shown) that has a function of adhering to an object to be joined and a function of a protective layer for the projecting portion.
Therefore, a resin layer forming step of forming a resin layer on the projecting portion may be provided after the removing step. In the resin layer forming step, for example, a resin layer is formed on the projecting portion using an inkjet method, a transfer method, a spray method, a screen printing method, or the like.
The resin layer preferably exhibits fluidity in a temperature range of, for example, 50° C. to 200° C. and cures at 200° C. or higher in order to exhibit the above functions.
The composition of the resin agent will be described below. The resin layer contains an antioxidant material and a polymeric material.

<Antioxidant material>
Specific examples of the antioxidant material contained in the resin layer include 1,2,3,4-tetrazole, 5-amino-1,2,3,4-tetrazole, 5-methyl-1,2, 3,4-tetrazole, 1H-tetrazole-5-acetic acid, 1H-tetrazole-5-succinic acid, 1,2,3-triazole, 4-amino-1,2,3-triazole, 4,5-diamino-1 , 2,3-triazole, 4-carboxy-1H-1,2,3-triazole, 4,5-dicarboxy-1H-1,2,3-triazole, 1H-1,2,3-triazole-4- Acetic acid, 4-carboxy-5-carboxymethyl-1H-1,2,3-triazole, 1,2,4-triazole, 3-amino-1,2,4-triazole, 3,5-diamino-1,2 ,4-triazole, 3-carboxy-1,2,4-triazole, 3,5-dicarboxy-1,2,4-triazole, 1,2,4-triazole-3-acetic acid, 1H-benzotriazole, 1H -benzotriazole-5-carboxylic acid, benzofuroxane, 2,1,3-benzothiazole, o-phenylenediamine, m-phenylenediamine, catechol, o-aminophenol, 2-mercaptobenzothiazole, 2-mercaptobenzimidazole , 2-mercaptobenzoxazole, melamine, and derivatives thereof.
Of these, benzotriazole and its derivatives are preferred.
Benzotriazole derivatives include hydroxyl groups, alkoxy groups (e.g., methoxy groups, ethoxy groups, etc.), amino groups, nitro groups, alkyl groups (e.g., methyl groups, ethyl groups, butyl groups, etc.) on the benzene ring of benzotriazole. , substituted benzotriazoles having halogen atoms (eg, fluorine, chlorine, bromine, iodine, etc.) and the like. Also included are naphthalenetriazole, naphthalenebistriazole, and similarly substituted naphthalenetriazoles and substituted naphthalenebistriazoles.

Other examples of the antioxidant material contained in the resin layer include general antioxidants such as higher fatty acids, higher fatty acid copper, phenol compounds, alkanolamines, hydroquinones, copper chelating agents, organic amines, organic Ammonium salts and the like are included.

Although the content of the antioxidant material contained in the resin layer is not particularly limited, it is preferably 0.0001% by mass or more, more preferably 0.001% by mass or more, based on the total mass of the resin layer from the viewpoint of anticorrosion effect. Moreover, from the reason of obtaining suitable electrical resistance in this joining process, 5.0 mass % or less is preferable and 2.5 mass % or less is more preferable.

<Polymer material>
The polymer material contained in the resin layer is not particularly limited, but it can efficiently fill the gap between the object to be bonded such as a semiconductor chip or semiconductor wafer and the structure, and the adhesion between the structure and the semiconductor chip or semiconductor wafer can be improved. Thermosetting resins are preferred because they are more durable.
Specific examples of thermosetting resins include epoxy resins, phenol resins, polyimide resins, polyester resins, polyurethane resins, bismaleimide resins, melamine resins, and isocyanate resins.
Among them, it is preferable to use a polyimide resin and/or an epoxy resin for the reason that the insulation reliability is further improved and the chemical resistance is excellent.

<Migration prevention material>
The resin layer contains a migration-preventing material for the reason that insulation reliability is further improved by trapping metal ions, halogen ions, and metal ions derived from the semiconductor chip and semiconductor wafer that may be contained in the resin layer. is preferred.

As an anti-migration material, for example, an ion exchanger, in particular a mixture of a cation exchanger and an anion exchanger, or only a cation exchanger can be used.
Here, the cation exchanger and the anion exchanger can be appropriately selected from, for example, inorganic ion exchangers and organic ion exchangers, which will be described later.

(Inorganic ion exchanger)
Examples of inorganic ion exchangers include hydrous oxides of metals typified by hydrous zirconium oxide.
Known types of metal include, for example, zirconium, iron, aluminum, tin, titanium, antimony, magnesium, beryllium, indium, chromium, bismuth, and the like.
Among these, zirconium-based materials have an exchange ability with respect to cations Cu2+ and Al3+. Iron-based materials also have exchangeability with respect to Ag+ and Cu2+. Similarly, tin-based, titanium-based, and antimony-based are cation exchangers.
On the other hand, the bismuth-based one has an exchange ability with respect to the anion Cl-.
In addition, zirconium-based materials exhibit anion exchange ability depending on the manufacturing conditions. The same applies to aluminum-based and tin-based materials.
As other inorganic ion exchangers, acid salts of polyvalent metals typified by zirconium phosphate, heteropolyacid salts typified by ammonium molybdophosphate, and synthetic compounds such as insoluble ferrocyanides are known.
Some of these inorganic ion exchangers are already commercially available, for example, various grades under the trade name IXE of Toagosei Co., Ltd. are known.
In addition to synthetic products, natural zeolites or powders of inorganic ion exchangers such as montmorillonite can also be used.

(Organic ion exchanger)
Organic ion exchangers include crosslinked polystyrene with sulfonic acid groups as cation exchangers, as well as those with carboxylic acid, phosphonic acid or phosphinic acid groups.
In addition, crosslinked polystyrene having a quaternary ammonium group, a quaternary phosphonium group or a tertiary sulfonium group can be used as an anion exchanger.

These inorganic ion exchangers and organic ion exchangers may be appropriately selected in consideration of the types of cations and anions to be captured and the exchange capacity for the ions. Of course, it goes without saying that an inorganic ion exchanger and an organic ion exchanger may be mixed and used.
Inorganic ion exchangers are preferred because the manufacturing process of electronic devices includes a heating process.

In addition, the mixing ratio of the ion exchanger and the above-described polymer material is preferably 10% by mass or less for the ion exchanger, and 5% by mass or less for the ion exchanger, from the viewpoint of mechanical strength. More preferably, the content of the ion exchanger is 2.5% by mass or less. Moreover, from the viewpoint of suppressing migration when a semiconductor chip or semiconductor wafer and a structure are bonded, the content of the ion exchanger is preferably 0.01% by mass or more.

<Inorganic filler>
The resin layer preferably contains an inorganic filler.
The inorganic filler is not particularly limited and can be appropriately selected from known ones. , crystalline silica, fused silica, spherical silica, talc, clay, magnesium carbonate, calcium carbonate, aluminum oxide, aluminum hydroxide, mica, aluminum nitride, zirconium oxide, yttrium oxide, silicon carbide, silicon nitride and the like.

In order to prevent the inorganic filler from entering between the conducting paths and improve the conduction reliability, it is preferable that the inorganic filler have an average particle size larger than the interval between the conducting paths.
The average particle size of the inorganic filler is preferably 30 nm to 10 μm, more preferably 80 nm to 1 μm.
Here, the average particle size is defined as the primary particle size measured by a laser diffraction/scattering particle size measuring device (Microtrac MT3300 manufactured by Nikkiso Co., Ltd.).

<Curing agent>
The resin layer may contain a curing agent.
When a curing agent is contained, from the viewpoint of suppressing poor bonding with the surface shape of the semiconductor chip or semiconductor wafer to be connected, a curing agent that is solid at normal temperature is not used, and a curing agent that is liquid at normal temperature is contained. is more preferred.
Here, "solid at room temperature" refers to a substance that is solid at 25°C, for example, a substance that has a melting point higher than 25°C.

Specific examples of curing agents include aromatic amines such as diaminodiphenylmethane and diaminodiphenylsulfone, aliphatic amines, imidazole derivatives such as 4-methylimidazole, dicyandiamide, tetramethylguanidine, thiourea-added amines, methyl Carboxylic acid anhydrides such as hexahydrophthalic anhydride, carboxylic acid hydrazides, carboxylic acid amides, polyphenol compounds, novolak resins, polymercaptans, etc. can be mentioned, and from these curing agents, those which are liquid at 25° C. are appropriately selected. can be used for The curing agent may be used singly or in combination of two or more.

The resin layer may contain various additives such as dispersing agents, buffering agents, viscosity modifiers, etc., which are generally added to resin insulating films of semiconductor packages, as long as the properties are not impaired.

<Shape>
For the reason of protecting the protrusions of the structure, the thickness of the resin layer is preferably greater than the height of the protrusions and is 1 μm to 5 μm.

[Method for manufacturing structure]
The method for manufacturing the joined body will be described in more detail below.
FIG. 13 is a schematic cross-sectional view showing an example of the structure of the structure according to the embodiment of the invention. 14 and 15 are schematic cross-sectional views showing an example of the manufacturing method of the joined body according to the embodiment of the present invention in order of steps. The bonding method shown in FIGS. 14 and 15 relates to a chip-on-chip, in which the semiconductor element 30 is bonded to the semiconductor element 32 as the structural body 18 . Thereby, a joined body 39 is obtained.
Semiconductor elements 30 and 32 shown in FIG. The rewiring layer 34 and the passivation layer 36 are electrically insulated insulating layers. A surface 33a of the semiconductor layer 33 is provided with an element region (not shown) in which a circuit or the like that exhibits a specific function is formed. The element region will be explained later. The surface 33a of the semiconductor layer 33 corresponds to the surface on which the terminals of the semiconductor are provided.
A rewiring layer 34 is provided on the surface 33 a of the semiconductor layer 33 . In the rewiring layer 34, wirings 37 electrically connected to the element regions of the semiconductor layer 33 are provided. A pad 38 is provided on the wiring 37, and the wiring 37 and the pad 38 are electrically connected. The wiring 37 and the pad 38 enable the transfer of signals to and from the element region, and the supply of voltage and the like to the element region.

A passivation layer 36 is provided on the surface 34 a of the rewiring layer 34 . In the passivation layer 36 , the conductive layer 12 functioning as an extraction electrode is provided on the pad 38 provided on the wiring 37 . The conductive layer 12 is electrically connected to the semiconductor layer 33 .
Also, the rewiring layer 34 is not provided with the wiring 37 but is provided with only the pads 38 . A conductive layer 12 functioning as an electrode is provided on a pad 38 that is not provided on the wiring 37 . Conductive layer 12 is not electrically connected to semiconductor layer 33 .

The end surface 12c of the conductive layer 12 and the end surface 12c of the conductive layer 12 are both aligned with the surface 36a of the passivation layer 36, which is a so-called flush state. It does not protrude from 36a. The conductive layer 12 and the conductive layer 12 shown in FIG. 13 are made flush with the surface 36a of the passivation layer 36 by, for example, polishing. The end surface 12c of the conductive layer 12 of the semiconductor element 30 corresponds to the surface 12a of the conductive layer 12 described above, and the conductive member 19 is formed on the end surface 12c of the conductive layer 12 to form the structure 18. FIG. When two semiconductor elements 30 and 32 are to be joined, one of them may be used as the structure 18 and the conductive member 19 may be formed. Both of the two semiconductor elements 30 , 32 may be bonded together as the structure 18 . That is, the conductive members 19 may be joined together.

As shown in FIG. 14, the semiconductor element 30 and the semiconductor element 32 are arranged with the conductive layers 12 facing each other.
Conductive layer 12 of semiconductor element 30 and conductive layer 12 of semiconductor element 32 are aligned, for example, by aligning semiconductor element 30 and semiconductor element 32 using alignment marks (not shown). Note that aligning the above positions is also referred to as alignment.
In FIG. 14, a plurality of protruding portions 17 are formed on the conductive layer 12 of the semiconductor element 30 positioned below.

With the semiconductor elements 30 and 32 aligned, the semiconductor elements 30 and 32 are brought close to each other as shown in FIG. Then, the semiconductor element 30 and the semiconductor element 32 are temporarily bonded to each other. The above-mentioned temporary joining will be explained later, but it is a state in which the aligned state is maintained, and is not a state in which they are permanently fixed.

Next, as shown in FIG. 15, the semiconductor element 30 and the semiconductor element 32 are joined. Thereby, the conductive layers 12 corresponding to each other are directly connected via the conductive member 19 . As described above, the semiconductor element 30 and the semiconductor element 32 are electrically connected to each other by the conductive member 19 and the conductive layer 12, and are physically connected without being electrically connected by the conductive member 19 and the conductive layer 12. Connected.
A process of bonding at least two members such as the semiconductor element 30 and the semiconductor element 32 is called a bonding process. In the joining step, for example, at least two members are joined under predetermined joining conditions.
Note that joining means joining objects to each other in a state in which electrical continuity is ensured with each other. When joined, the objects remain permanently joined together. The bonding in the bonding step described above is also referred to as main bonding.
In the bonding step, for example, the temporary bonding may be performed under predetermined conditions, but the temporary bonding may be omitted. Note that the temporary bonding process is called a temporary bonding process, and bonding other than the temporary bonding in the bonding process is also called final bonding.

The semiconductor layer 33 is not particularly limited as long as it is a semiconductor, and is composed of silicon or the like, but is not limited thereto, and may be silicon carbide, germanium, gallium arsenide, gallium nitride, or the like. good.
The rewiring layer 34 is made of an electrically insulating material such as polyimide.
The passivation layer 36 is also made of an electrically insulating material such as silicon nitride (SiN) or polyimide.
The wiring 37 and the pads 38 are made of a conductive material such as copper, copper alloy, aluminum, or aluminum alloy.

The conductive layer 12 and the conductive layer 12 are made of a conductive material like the wiring 37 and the pad 38, and are made of metal or alloy, for example. Specifically, the conductive layer 12 and the conductive layer 12 are made of, for example, copper, a copper alloy, aluminum, an aluminum alloy, or the like. As described above, the conductive layer 12 and the conductive material filled in the structure 18 are preferably made of the same material.
It should be noted that the conductive layer 12 and the conductive layer 12 are not limited to being made of a metal or an alloy as long as they have conductivity. The materials used can be used as appropriate.

[Layered device]
Next, a laminated device will be described as an example using the structure 18. FIG.
FIG. 16 is a schematic diagram showing a first example of a laminated device using the structure of the embodiment of the invention, and FIG. 17 shows a second example of the laminated device using the structure of the embodiment of the invention. 18 is a schematic diagram showing a third example of a laminated device using the structure of the embodiment of the present invention, and FIG. 19 is a laminated device using the structure of the embodiment of the present invention. It is a schematic diagram which shows the 4th example of.

In the stacked device 40 shown in FIG. 16, one of the semiconductor element 42 and the semiconductor element 44 is used as the structural body 18 . The stacked device 40 is formed by bonding the semiconductor element 42 and the semiconductor element 44 together in the stacking direction Ds via a conductive member 19 (not shown) to electrically connect the semiconductor element 42 and the semiconductor element 44. .

In addition to the configuration shown in FIG. 16, for example, like a stacked device 40 shown in FIG. may be
In addition to the structure 18, the semiconductor element 42, the semiconductor element 44, and the semiconductor element 46 are laminated and joined in the lamination direction Ds using an interposer 45, as in the laminated device 40 shown in FIG. An electrically connected configuration may also be used.

The interposer 45 is responsible for electrical connection between semiconductor elements. It also serves as an electrical connection between the semiconductor element and the wiring board or the like. By using the interposer 45, the wiring length and wiring width can be reduced, the parasitic capacitance can be reduced, and variations in wiring length can be reduced.
The configuration of the interposer 45 is not particularly limited as long as it can achieve the above functions, and any known configuration can be used as appropriate. The interposer 45 can be configured using, for example, an organic material such as polyimide, glass, ceramics, metal, silicon, polycrystalline silicon, or the like.

Moreover, it may function as an optical sensor like the laminated device 40 shown in FIG. A stacked device 40 shown in FIG. 19 has a semiconductor element 42 and a sensor chip 47 stacked in a stacking direction Ds. In the laminated device 40 , the semiconductor element 42 and the sensor chip 47 are joined using the structure 18 . Also, the sensor chip 47 is provided with a lens 48 .
The semiconductor element 42 is formed with a logic circuit, and its configuration is not particularly limited as long as the signal obtained by the sensor chip 47 can be processed.
The sensor chip 47 has an optical sensor that detects light. The optical sensor is not particularly limited as long as it can detect light, and for example, a CCD (Charge Coupled Device) image sensor or a CMOS (Complementary Metal Oxide Semiconductor) image sensor is used.
The configuration of the lens 48 is not particularly limited as long as it can focus light on the sensor chip 47, and for example, a so-called microlens is used.

The semiconductor element 42, the semiconductor element 44, and the semiconductor element 46 described above have element regions (not shown). The element region is as described above. As described above, the device region is formed with the device configuration circuit and the like, and the semiconductor device is provided with, for example, a rewiring layer (not shown).
A stacked device can be, for example, a combination of a semiconductor element having a logic circuit and a semiconductor element having a memory circuit. Further, all of the semiconductor elements may have memory circuits, or all of them may have logic circuits. The combination of semiconductor elements in the laminated device 40 may be a combination of a sensor, an actuator, an antenna, etc., and a memory circuit and a logic circuit.

[Semiconductor device]
The semiconductor element 42, the semiconductor element 44, and the semiconductor element 46 described above are, in addition to those described above, for example, logic LSI (Large Scale Integration) (e.g., ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array), ASSP (Application Specific Standard Product), etc.), microprocessor (e.g., CPU (Central Processing Unit), GPU (Graphics Processing Unit), etc.), memory (e.g., DRAM (Dynamic Random Access Memory), HMC (Hybrid Memory Cube), MRAM (MagneticRAM), PCM (Phase-Change Memory), ReRAM (Resistive RAM), FeRAM (Ferroelectric RAM), flash memory (NAND (Not AND) flash ), etc.), LEDs (Light Emitting Diodes), (e.g., mobile terminal microflash, automotive, projector light sources, LCD backlights, general lighting, etc.), power devices, analog ICs (Integrated Circuits), (e.g., DC (Direct Current)-DC (Direct Current) converter, insulated gate bipolar transistor (IGBT), etc.), MEMS (Micro Electro Mechanical Systems), (e.g. acceleration sensor, pressure sensor, vibrator, gyro sensor, etc.), wireless (e.g. , GPS (Global Positioning System), FM (Frequency Modulation), NFC (Nearfield communication), RFEM (RF Expansion Module), MMIC (Monolithic Microwave Integrated Circuit), WLAN (Wireless Local Area Network), etc.), discrete elements, BSI (Back Side Illumination) , CIS (Contact Image Sensor), Camera module, CMOS (Complementary Metal Oxide Semiconductor), Passive device, SAW (Surface Acoustic Wave) filter, RF (Radio Frequency) filter, RFIPD (Radio Frequency Integrated Passive Devices), BB (Broadband) etc.
A semiconductor element is, for example, a single device, and a single semiconductor element exerts a specific function such as a circuit or a sensor.
The stacked device is not limited to a one-to-plural form in which a plurality of semiconductor elements are joined to one semiconductor element, but a form in which a plurality of semiconductor elements are joined to a plurality of semiconductor elements. Certain many-to-many forms are also possible.

[First Example of Method for Manufacturing Laminated Device]
Next, a first example of a method of manufacturing a laminated device using a structure will be described.
A first example of a method of manufacturing a laminated device using a structure relates to a chip-on-wafer, and shows a method of manufacturing a laminated device 40 shown in FIG.
20 to 22 are schematic diagrams showing the order of steps of a first example of a method for manufacturing a laminated device using the structure of the embodiment of the present invention.
In the first example of the method of manufacturing a stacked device using structures, the structures 18 are manufactured on the first semiconductor wafer 50 . A surface 50a of the first semiconductor wafer 50 has a plurality of element regions (not shown), and a conductive member 19 is provided for each element region.
Next, the semiconductor element 44 is arranged facing the conductive member 19 of the first semiconductor wafer 50 . Next, the alignment marks of the semiconductor element 44 and the alignment marks of the first semiconductor wafer 50 are used to align the semiconductor element 44 with respect to the first semiconductor wafer 50 .
As for alignment, if digital image data can be obtained for the image or reflected image of the alignment mark of the first semiconductor wafer 50 and the image or reflected image of the alignment mark of the semiconductor element 44, the configuration is particularly limited. A known imaging device can be used as appropriate.

Next, the semiconductor element 44 is placed on the conductive member 19 provided in the element region of the first semiconductor wafer 50, for example, a predetermined pressure is applied, heated to a predetermined temperature, and heated to a predetermined temperature. Temporary bonding is performed by holding for a specified time. This is performed for all the semiconductor elements 44, and all the semiconductor elements 44 are temporarily bonded to the element regions of the first semiconductor wafer 50 as shown in FIG.
Temporary bonding may be performed by the method described below. For example, a sealing resin or the like may be supplied onto the conductive member 19 of the first semiconductor wafer 50 by a dispenser or the like, and the semiconductor element 44 may be temporarily bonded to the element region of the first semiconductor wafer 50. The semiconductor element 44 may be temporarily bonded to the element region of the semiconductor wafer 50 by using an insulating resin film (NCF (Non-conductive Film)) supplied in advance. Alternatively, a resin layer (not shown) may be formed on the projecting portion, and the resin layer may be used for temporary bonding.

Next, in a state in which all the semiconductor elements 44 are temporarily bonded to the element regions of the first semiconductor wafer 50, the semiconductor elements 44 are applied with a predetermined pressure, heated to a predetermined temperature, and After holding for a predetermined time, all of the plurality of semiconductor elements 44 are collectively bonded to the element region of the first semiconductor wafer 50 via the conductive member 19 . This joining is called the main joining. As a result, terminals (not shown) of the semiconductor element 44 are joined to the conductive members 19 of the first semiconductor wafer 50 .
Next, as shown in FIG. 22, the first semiconductor wafer 50 to which the semiconductor elements 44 are bonded is singulated by dicing, laser scribing, or the like for each element region. Thereby, the laminated device 40 in which the semiconductor element 42 and the semiconductor element 44 are joined can be obtained.

In addition, if the temporary bonding strength is weak at the time of temporary bonding, positional deviation may occur in the transportation process and the process up to bonding, so the temporary bonding strength is important.
Moreover, the temperature conditions and pressure conditions in the temporary bonding step are not particularly limited, and the temperature conditions and pressure conditions described later are exemplified.

The temperature conditions and pressure conditions in this bonding are not particularly limited, and are exemplified by the temperature conditions and pressure conditions described later.
By performing the main bonding under appropriate conditions, the resin layer flows between the electrodes of the semiconductor element 44 and is less likely to remain at the bonding portion. As described above, in this bonding, by collectively bonding a plurality of semiconductor elements 44, the tact time can be reduced and the productivity can be increased.

[Second Example of Method for Manufacturing Laminated Device]
A second example of a method of manufacturing a laminated device using a structure will be described.
FIG. 23 is a schematic diagram showing one step of the second example of the method of manufacturing a laminated device using the structure of the embodiment of the present invention.
In the second example of the method for manufacturing a stacked device using a structure, three semiconductor elements 42, 44 and 46 are stacked in comparison with the first example of the method for manufacturing a stacked device using a structure. The method is the same as the first example of the method for manufacturing a laminated device using a structure, except for the point of bonding. Therefore, detailed description of the manufacturing method common to the second example of the manufacturing method of the laminated device will be omitted.
The semiconductor element 44 is provided with an alignment mark (not shown) on the rear surface 44b, and is provided with terminals (not shown). In addition, the semiconductor element 46 has the structure 18, and the conductive member 19 is provided on the surface 46a. The semiconductor device 46 has the structure 18 manufactured in the device region (not shown) in the same manner as the first semiconductor wafer 50, and is singulated. Therefore, the semiconductor element 46 has the conductive member 19 .

As shown in FIG. 23, in a state in which all the semiconductor elements 44 are temporarily bonded to the element regions of the first semiconductor wafer 50 via the conductive members 19, the alignment marks on the back surface 44b of the semiconductor elements 44 and the semiconductor elements 46 are aligned. The alignment marks are used to align the semiconductor element 46 with respect to the semiconductor element 44 .

Next, the semiconductor element 46 is temporarily bonded to the back surface 44 b of the semiconductor element 44 via the conductive member 19 . Next, all the semiconductor elements 44 are temporarily bonded to the element region of the first semiconductor wafer 50 via the conductive members 19, and the semiconductor elements 46 are temporarily bonded to all the semiconductor elements 44 via the conductive members 19. Then, the main bonding is performed under predetermined conditions. Thereby, the semiconductor element 44 and the semiconductor element 46 are bonded together, and the semiconductor element 44 and the first semiconductor wafer 50 are bonded together.
Next, with the semiconductor elements 44 and 46 bonded to the first semiconductor wafer 50, the semiconductor elements 44 and 46 are singulated for each element region by, for example, dicing or laser scribing. Thereby, the laminated device 40 (see FIG. 17) in which the semiconductor element 42, the semiconductor element 44, and the semiconductor element 46 are joined can be obtained.

[Third Example of Method for Manufacturing Laminated Device]
A third example of a method of manufacturing a laminated device using a structure will be described.
A third example of a method of manufacturing a laminated device using a structure relates to wafer-on-wafer, and shows a method of manufacturing a laminated device 40 shown in FIG.
24 and 25 are schematic diagrams showing, in order of steps, a third example of a method for manufacturing a laminated device using the structure of the embodiment of the present invention.
Compared to the first example of the method for manufacturing a stacked device, the third example of the method for manufacturing a stacked device using the structure uses the structure 18 to manufacture the first semiconductor wafer 50 and the second semiconductor wafer. 52 is the same as the first example of the manufacturing method of the laminated device. Therefore, detailed description of the manufacturing method common to the first example of the manufacturing method of the laminated device is omitted. Further, since the structure 18 is also as described above, detailed description thereof will be omitted.

First, a first semiconductor wafer 50 and a second semiconductor wafer 52 are prepared. One of the first semiconductor wafer 50 and the second semiconductor wafer 52 is used as the structure 18 .
Next, the surface 50a of the first semiconductor wafer 50 and the surface 52a of the second semiconductor wafer 52 are made to face each other. Then, the second semiconductor wafer 52 is aligned with the first semiconductor wafer 50 using the alignment marks of the first semiconductor wafer 50 and the alignment marks of the second semiconductor wafer 52 .
Next, the surface 50a of the first semiconductor wafer 50 and the surface 52a of the second semiconductor wafer 52 are opposed to each other, and the first semiconductor wafer 50 and the second semiconductor wafer 50 are separated by the above-described method as shown in FIG. The semiconductor wafer 52 is bonded through the conductive member 19 . In this case, the permanent bonding may be performed after the temporary bonding, or the final bonding alone may be performed.

Next, as shown in FIG. 25, in a state where the first semiconductor wafer 50 and the second semiconductor wafer 52 are bonded via the conductive member 19, each element region is individually separated by, for example, dicing or laser scribing. fragment. Thereby, the laminated device 40 in which the semiconductor element 42 and the semiconductor element 44 are joined can be obtained. Thus, the laminated device 40 can be obtained even by using wafer-on-wafer.
In addition, since it is as above-mentioned about singulation, detailed description is abbreviate|omitted.
Further, as shown in FIG. 25, it is necessary to make the first semiconductor wafer 50 and the second semiconductor wafer 52 thinner in a state where the first semiconductor wafer 50 and the second semiconductor wafer 52 are bonded. If a semiconductor wafer is available, it can be thinned, such as by chemical mechanical polishing (CMP).

In the third example of the method of manufacturing a laminated device using a structure, a two-layer structure in which the semiconductor element 42 and the semiconductor element 44 are laminated has been described as an example. Of course, three or more layers may be used. In this case, alignment marks (not shown) and terminals (not shown) are provided on the rear surface 52b of the second semiconductor wafer 52 in the same manner as in the second example of the manufacturing method of the laminated device 40 described above. A stacked device 40 with more than one layer can be obtained.

As described above, by using the structure 18 in the stacked device 40, even if the semiconductor element has unevenness, the protrusion 17 can be used as a buffer layer to absorb the unevenness. Since the protruding portion 17 functions as a buffer layer, it is possible to eliminate the need for a high surface quality for the surface of the semiconductor element having the element region. For this reason, smoothing treatment such as polishing is not required, and the production cost can be suppressed, and the production time can be shortened.
In addition, since the stacked device 40 can be manufactured using chip-on-wafer, it is possible to maintain yield and reduce manufacturing loss by bonding only non-defective semiconductor chips to non-defective portions in the semiconductor wafer. can be done.
Furthermore, for example, the resin layer has adhesiveness and can be used as a temporary bonding agent during temporary bonding, and can be permanently bonded together.

The semiconductor device 44 described above can be formed using a semiconductor wafer having a plurality of device regions (not shown). The element region is provided with alignment marks (not shown) for alignment and terminals (not shown) as described above.

Regarding the bonding of the stacked device, the mode of bonding another semiconductor element to a semiconductor element has been described, but the present invention is not limited to this, and may be a mode of bonding a plurality of semiconductor elements to one semiconductor element. A one-to-multiple form may also be used. Alternatively, a multiple-to-multiple mode, in which a plurality of semiconductor elements are bonded to each other, may be used.

The method for manufacturing the laminated device will be described in more detail below.
[Temporary bonding process]
Temporary bonding in the temporary bonding step refers to fixing onto the object to be bonded in a state of being aligned with the object to be bonded. Temporary bonds remain in alignment but are not permanently fixed. When the semiconductor element of the object to be joined is temporarily fixed, it is in a state where the semiconductor element is aligned and fixed.
The temporary joining step is carried out by bringing at least two members close together and in contact with each other. In this case, the pressurization conditions are not particularly limited, but are preferably 10 MPa or less, more preferably 5 MPa or less, and particularly preferably 1 MPa or less.
Similarly, the temperature condition in the temporary bonding step is not particularly limited, but it is preferably 0 ° C. to 300 ° C., more preferably 10 ° C. to 200 ° C., normal temperature (23 ° C.) to 100 ° C. °C is particularly preferred.
For the temporary bonding process, devices of companies such as Toray Engineering Co., Ltd., Shibuya Kogyo Co., Ltd., Shinkawa Co., Ltd., and Yamaha Motor Co., Ltd. can be used.

[Joining process]
The bonding in the bonding step as described above is also referred to as main bonding. As noted above, when joined, the objects remain permanently joined together. At the time of main bonding, the atmosphere, heating temperature, pressure (load), and processing time at the time of main bonding are listed as control factors, but conditions suitable for devices such as semiconductor elements to be used can be selected.
The temperature conditions in the main bonding are not particularly limited, but the temperature is preferably higher than the temperature of the temporary bonding, specifically, it is more preferably 150 ° C. to 350 ° C., and 200 ° C. to 300° C. is particularly preferred.
Also, the pressurizing conditions in this bonding are not particularly limited, but are preferably 30 MPa or less, and more preferably 0.1 MPa to 20 MPa. It is preferable that the maximum load of the pressurizing condition is 1 MN or less. More preferably, it is 0.1 MN or less.
The time for the main bonding is not particularly limited, but is preferably 1 second to 60 minutes, more preferably 5 seconds to 10 minutes.

Examples of equipment used for the above-mentioned main bonding include Mitsubishi Heavy Industries Machine Tool, Bondtech, PMT Co., Ltd., Ayumi Industry, Tokyo Electron (TEL), EVG, Sus Microtech Co., Ltd. (SUSS), Musashino Engineering, etc. can be used.
The atmosphere at the time of this bonding may be the air, an inert gas such as nitrogen or argon, a reducing gas such as hydrogen or carboxylic acid, or a mixed gas of these inert gases and reducing gases. gas atmosphere may be used. Also, the atmosphere during the main bonding may be a reduced-pressure atmosphere including a vacuum atmosphere. Any of the atmospheres described above can be achieved by known methods.
The heating temperature is not particularly limited to the above, and various temperatures can be selected from 100° C. to 400° C., and the heating rate is from 10° C./min to 10° C./sec. Or it can be selected according to the heating method. The same is true for cooling. Moreover, it is also possible to heat in a stepwise manner, and it is also possible to divide into several steps and raise the heating temperature one by one for bonding.
The pressure (load) is also not particularly limited to the one described above, and a rapid pressurization or a stepped pressurization can be selected according to the physical properties such as the strength of the object to be welded.

The atmosphere at the time of main bonding, the holding time for each of heating and pressurization, and the changing time can be appropriately set. Also, the order can be changed as appropriate. For example, after a vacuum state is created, the first stage of pressurization is performed, and after that, when the temperature is raised by heating, the second stage of pressurization is performed and held for a certain period of time. It is possible to set up a procedure to return to the atmosphere at the stage when it becomes unusable.
Such a procedure can be variously modified, and after pressurization in the atmosphere, heating may be performed in a vacuum state, or vacuuming, pressurization, and heating may be performed at once. Examples of these combinations are shown in FIGS. 26-32.
In addition, if a mechanism for individually controlling pressure distribution and heating distribution in the plane is used during bonding, the bonding yield can be improved.
Temporary bonding can also be changed in the same way. For example, by performing it in an inert atmosphere, oxidation of the electrode surface of the semiconductor element can be suppressed. Furthermore, it is also possible to perform bonding while applying ultrasonic waves.

26 to 32 are graphs showing first to seventh examples of main bonding conditions for laminated devices using the structure of the embodiment of the present invention. 26 to 32 show the atmosphere, heating temperature, pressure (load), and processing time during bonding, and symbol V indicates the degree of vacuum. The symbol L indicates the load and the symbol T indicates the temperature. A high degree of vacuum in FIGS. 26 to 32 indicates a low pressure. 26 to 32, the lower the degree of vacuum, the closer to the atmospheric pressure.
Regarding the atmosphere, heating temperature, and load during bonding, for example, as shown in FIGS. Also, as shown in FIGS. 29, 31 and 32, the timing of applying the load and the timing of raising the temperature may be matched. As shown in FIG. 30, the load may be applied after the temperature is raised. Also, as shown in FIGS. 29 and 30, the timing of reducing the pressure and the timing of increasing the temperature may be matched.
The temperature may be raised in steps as shown in FIGS. 26, 27 and 31, or may be heated in two stages as shown in FIG. The load may also be applied stepwise as shown in FIGS.
26, 28, 30, 31 and 32, the load may be applied after the pressure is reduced, or the pressure may be reduced as shown in FIGS. 27 and 29. and the timing of applying the load may be matched. In this case, pressure reduction and bonding are performed simultaneously.

[Other joining processes]
The joining method is not limited to the one described above. For example, the semiconductor element 42 and the semiconductor element 44 are laminated via an electrode material containing at least tin as a heat melting material. In this case, the electrode material is arranged on the projecting portion 17 shown in FIG.
Next, the hot-melt material containing tin is melted by heating to a melting point or higher in an atmosphere containing carboxylic acid vapor such as formic acid vapor at a pressure of 1×10 ⁴ Pa or higher. As a result, the electrode material is formed into an electrode on the projecting portion 17 . Next, the semiconductor element 42 and the semiconductor element 44 are brought close to each other, and after the heated and melted material is solidified, the carboxylic acid vapor is exhausted to reduce the pressure from 1×10 ⁴ Pa or more to 1×10 ² Pa or less. do. Carboxylic acid vapor is vented when the temperature of the electrode material is above 100° C. and below the melting point. After reducing the pressure, the atmosphere is replaced with an inert gas atmosphere containing no carboxylic acid. Thereby, as shown in FIG. 16, the semiconductor element 42 and the semiconductor element 44 are bonded to obtain the laminated device 40. Next, as shown in FIG. Note that the carboxylic acid acts as a reducing agent, enabling bonding at a lower temperature. Further, the electrode material containing tin is, for example, a solder material containing tin.

Also, for example, the semiconductor element 42 and the semiconductor element 44 are laminated via a composition layer. In this case, the composition layer is arranged on the projecting portion 17 shown in FIG. Then, it is heated at a temperature of 120 to 250° C. under a gas atmosphere of an inert gas, a reducing gas, or a mixed gas thereof, and a load is applied. Thereby, as shown in FIG. 16, the semiconductor element 42 and the semiconductor element 44 are bonded to obtain the laminated device 40. Next, as shown in FIG.
The gas atmosphere is a gas atmosphere containing hydrogen gas or formic acid gas.
The conductor-forming composition contains copper-containing particles, an organic acid, and a dispersion medium. The copper-containing particles have core particles containing copper and an organic substance covering at least part of the surface of the core particles. The organic matter includes alkylamines having a hydrocarbon group with 7 or less carbon atoms.
The copper-containing particles are, for example, the copper-containing particles of JP-A-2016-037627. In addition, the copper-containing particles contain at least copper, but as substances other than copper, metals such as gold, silver, platinum, tin, and nickel, compounds containing these metal elements, reducing compounds, organic substances, etc. good too.
The organic acid is, for example, an organic carboxylic acid used as a soldering flux component. The dispersion medium is an organic solvent that is generally used for manufacturing conductive ink, conductive paste, and the like.

As for the bonding atmosphere, not only a vacuum atmosphere but also an inert gas such as nitrogen or argon, a reducing gas such as hydrogen or carboxylic acid, or a mixed gas of these inert gases and reducing gases can be used. You may use a well-known method, such as introducing. In particular, it is preferable to use a gas containing a reducing gas. Techniques using these gases can be applied to solder fusion bonding techniques or bonding techniques using fine metal particles. Bonding can be performed by heating and pressurizing by introducing a chemical atmosphere gas into the chamber. It is desirable that the concentration of the carboxylic acid in the atmospheric gas is below the explosion limit and above 0.002%. Also in the case of gas containing hydrogen, it is desirable that the content is below the explosion limit and 1% or more. Bonding in a reducing atmosphere facilitates the detachment of organic matter from the surface of the copper pillar protruding from the surface of the anisotropically conductive member manufactured by the present invention, and the removal of the oxide film. The bonding with the copper electrode is promoted.
Specifically, after the objects to be bonded are introduced into the chamber, the inside of the chamber is once evacuated, and the above-mentioned reducing atmospheric gas is introduced into the chamber to maintain a constant pressure. At this time, the gas introduced into the chamber is a mixed gas of carboxylic acid vapor and carrier gas (nitrogen or the like), and the pressure inside the chamber becomes 1×10 ⁴ Pa or more by introducing the gas. The heated objects to be bonded are bonded together while the internal pressure of the chamber is constant. The object to be bonded may be heated during evacuation, or may be heated after introduction of a reducing gas. The pressure in the chamber in the heating process is not particularly limited, and by reducing the pressure, the conductivity at low temperatures tends to be further promoted, and the gas is introduced and exhausted in parallel in a "flow" state. It's okay. By setting the "flow" state, desorption gas and the like are exhausted at the same time, and contamination of the chamber is reduced.

A semiconductor package using the structure will be described below.
[Semiconductor package]
FIG. 33 is a schematic cross-sectional view showing a first example of a semiconductor package. In addition, in FIG. 33 shown below, the same components as those of the structure 18 shown in FIG. 13 described above are denoted by the same reference numerals, and detailed description thereof will be omitted.
In the semiconductor package 60 shown in FIG. 33, the structure 18 of the semiconductor element 62 is manufactured. The semiconductor element 62 is covered with a mold resin 64 . Conductive member 19 of semiconductor element 62 is electrically connected to wiring board 70 .
The wiring board 70 has a wiring layer 74 provided on an insulating base material 72 having electrical insulation. The wiring layer 74 has one side electrically connected to the conductive member 19 and the other side electrically connected to the solder ball 75 . As a result, signals and the like can be extracted from the semiconductor element 62 to the outside of the semiconductor package 60 . Also, a signal, voltage, current, or the like can be supplied to the semiconductor element 62 from the outside of the semiconductor package 60 .

Note that the present invention is not limited to the above-described embodiments, and implementation forms include, for example, SoC (System on a chip), SiP (System in Package), PoP (Package on Package), PiP (Package in Package). Package), CSP (Chip Scale Package), TSV (Through Silicon Via), and the like.

[Semiconductor device mounting process]
When mounting a structure on a semiconductor element, mounting by heating is involved. In mounting by thermocompression bonding including solder reflow and mounting by flip chip, the maximum temperature reached is 220° C. from the viewpoint of performing uniform and reliable mounting. ~350°C is preferred, 240 to 320°C is more preferred, and 260 to 300°C is particularly preferred.
From the same point of view, the time for which these maximum temperatures are maintained is preferably 2 seconds to 10 minutes, more preferably 5 seconds to 5 minutes, and particularly preferably 10 seconds to 3 minutes.
In addition, from the viewpoint of suppressing cracks that occur in the anodized film due to the difference in thermal expansion coefficient between the object to be joined and the anodized film of the structure, a desired constant temperature is applied before the maximum temperature is reached. A method of heat-treating at a temperature of 5 seconds to 10 minutes, more preferably 10 seconds to 5 minutes, particularly preferably 20 seconds to 3 minutes, can also be used. A desired constant temperature is preferably 80 to 200°C, more preferably 100 to 180°C, and particularly preferably 120 to 160°C.
The temperature during mounting by wire bonding is preferably 80 to 300.degree. C., more preferably 90 to 250.degree. C., and particularly preferably 100 to 200.degree. The heating time is preferably 2 seconds to 10 minutes, more preferably 5 seconds to 5 minutes, particularly preferably 10 seconds to 3 minutes.

[Coaxial structure]
In addition, as shown in FIGS. 34 and 35, for example, the wiring described above may be arranged in a plurality of lines connected to a ground wiring 93 at predetermined intervals around a plurality of linear conductors 90 through which signal currents flow. A shaped conductor 90 can also be arranged. Since this structure is equivalent to a coaxial line, a shielding effect can be obtained. Further, a plurality of linear conductors 90 connected to the ground wiring 93 are arranged between the plurality of linear conductors 90 arranged adjacent to each other and through which different signal currents flow. Therefore, it is possible to reduce the electrical coupling (capacitive coupling) that occurs between the plurality of linear conductors 90 that are arranged adjacent to each other and carry different signal currents. You can suppress it from becoming a source. In FIG. 34 , a plurality of linear conductors 90 through which signal currents flow are formed on an insulating base material 91 and electrically insulated from each other, and are electrically connected to signal wiring 92 . The signal wiring 92 and the ground wiring 93 are electrically connected to a wiring layer 95 electrically insulated by an insulating layer 94, respectively.

Also, FIG. 36 is a schematic cross-sectional view showing a second example of the semiconductor package.
The structure can also be used for electrical connection between the semiconductor package 60 and the printed wiring board 80, as shown in FIG. The printed wiring board 80 has the semiconductor package 60 manufactured from the structure 18 . The printed wiring board 80 has a wiring layer 84 provided on an insulating base material 82 made of resin, for example. The wiring layer 84 is electrically connected to the conductive member 19 .

The structure of the present invention can also be used for connection between two or more semiconductor packages (PoP: Package on Package). A mode in which it is connected to a package via predetermined wiring can be mentioned.
The structure can also be used for a multi-chip package in which two or more semiconductor elements are stacked or laid flat on a substrate. are laminated and connected via predetermined wiring.

[Electronic device]
The electronic device is not limited to a one-to-plural form in which a plurality of semiconductor elements are joined to one semiconductor element, but is a form in which a plurality of semiconductor elements are joined to a plurality of semiconductor elements. It may also be in the form of multiple pairs.
FIG. 37 is a schematic diagram showing a first example of an electronic device using the structure of the embodiment of the invention, and FIG. 38 shows a second example of an electronic device using the structure of the embodiment of the invention. 39 is a schematic diagram showing a third example of an electronic device using the structure of the embodiment of the present invention, and FIG. 40 is an electronic device using the structure of the embodiment of the present invention. It is a schematic diagram which shows the 4th example of.

As a multiple-to-multiple mode, for example, as shown in FIG. The electronic device 100a in the form of being connected and electrically connected is exemplified. The semiconductor element 104 may have an interposer function.
Also, for example, it is possible to stack a plurality of devices such as a logic chip having a logic circuit and a memory chip on a device having an interposer function. Moreover, in this case, even if the electrode size is different for each device, it can be joined.
In the electronic device 100b shown in FIG. 38, the electrodes 118 are not of the same size, and electrodes 118 of different sizes are mixed. 19 are used to bond and electrically connect the semiconductor element 106 and the semiconductor element 108 . Furthermore, semiconductor element 106 and semiconductor element 108 also form structure 18 , and semiconductor element 116 is joined and electrically connected to semiconductor element 106 using conductive member 19 of structure 18 . A semiconductor element 117 is joined and electrically connected across the semiconductor elements 106 and 108 using the conductive member 19 of the structure 18 .

Moreover, as in an electronic device 100c shown in FIG. properly connected. Furthermore, a structure 18 is formed on the semiconductor element 106 and the semiconductor element 108, the semiconductor element 116 and the semiconductor element 117 are joined to the semiconductor element 106 using the conductive member 19 of the structure 18, and the semiconductor element 121 is attached to the semiconductor element 108. A configuration in which they are joined and electrically connected using the conductive member 19 of the structure 18 can also be used.

In the case of the above configuration, a light emitting element such as a VCSEL (Vertical Cavity Surface Emitting Laser) and a light receiving element such as a CMOS (Complementary Metal Oxide Semiconductor) image sensor are stacked on the device surface including the optical waveguide. This makes it possible to handle silicon photonics assuming high frequencies.
For example, as in an electronic device 100d shown in FIG. properly connected. Furthermore, a structure 18 is formed on the semiconductor element 106 and the semiconductor element 108, the semiconductor element 116 and the semiconductor element 117 are joined to the semiconductor element 106 using the conductive member 19 of the structure 18, and the semiconductor element 121 is attached to the semiconductor element 108. They are joined and electrically connected using the conductive member 19 of the structure 18 .
An optical waveguide 123 is provided in the semiconductor element 104 . A light emitting element 125 is provided on the semiconductor element 108 and a light receiving element 126 is provided on the semiconductor element 106 . Light Lo output from the light emitting element 125 of the semiconductor element 108 passes through the optical waveguide 123 of the semiconductor element 104 and is emitted to the light receiving element 126 of the semiconductor element 106 as output light Ld. This makes it possible to deal with the silicon photonics described above.
In addition, in the structure 18 of the semiconductor element 104, the conductive member 19 is formed so as to avoid the region 122 corresponding to the optical paths of the light Lo and the emitted light Ld.

The present invention is basically configured as described above. Although the method for manufacturing a structure and the method for manufacturing a joined body according to the present invention have been described in detail above, the present invention is not limited to the above-described embodiments, and various improvements and modifications can be made without departing from the gist of the present invention. It is of course possible to

The features of the present invention will be described more specifically with reference to examples below. The materials, reagents, amounts and ratios of substances, operations, etc. shown in the following examples can be changed as appropriate without departing from the gist of the present invention. Accordingly, the scope of the invention is not limited to the following examples.
In this example, structures were produced by the structure manufacturing methods of Examples 1 to 4 and Comparative Example 1. FIG. Bonding and conductivity were evaluated for each of the fabricated structures. The results are shown in Table 1 below. Bonding and conductivity will be described below.

<Evaluation of Joining>
A TEG chip (Test Element Group chip) was prepared for bonding evaluation. The TEG chip was provided with a joint having a size of 100 μm on one side. Also, the TEG chip has extraction electrodes at both ends.
The structures fabricated in Examples 1 to 4 and Comparative Example 1 and the TEG chips were stacked and placed in a chamber of a wafer bonder. After the inside of the chamber was once evacuated to 10 ⁻³ Pa, nitrogen gas containing 5% hydrogen was introduced into the chamber, and the pressure inside the chamber was stabilized at 5 KPa. After that, it was pressurized and heated under the conditions of a temperature of 250° C. and a pressure of 100 MPa, and this heating and pressurizing state was maintained for 30 minutes to try to produce a joined body. Bondtech WB-1000 was used as a wafer bonder.
Bonding was evaluated based on the presence or absence of peeling when the bonded body was turned upside down. The presence or absence of peeling was visually evaluated. Those with no peeling were evaluated as "no peeling", and those with peeling were evaluated as "with peeling".

<Evaluation of conductivity>
Continuity test was carried out on the joined body obtained by the above-described joining evaluation using lead electrodes at both ends of the TEG chip, and the electric resistance value was measured and evaluated.
Continuity was evaluated as "conducting" when the electrical resistance value was 1 kΩ or less, and as "impossible to measure" when the electrical resistance value could not be measured.

Examples 1 to 4 and Comparative Example 1 are described below. Note that the diameter and height of the protrusions in Examples 1 to 4 were obtained by obtaining a cross-sectional image of the protrusion using a field emission scanning electron microscope, and based on the cross-sectional image, the diameter and height of the protrusion were determined. The height was measured at 10 points, and the measured average value was used.

(Example 1)
In Example 1, a TEG chip was prepared. A conductive layer having a side of 100 μm was formed on the TEG chip. A plurality of protrusions were formed on the surface of this conductive layer.
A quartz glass plate having through holes with a hole diameter of 20 μm was used as the mold member. A quartz glass plate was glued to the conductive surface using PEG (polyethylene glycol).
Next, electroless plating was performed to fill the through holes of the quartz glass plate with copper as a conductive material.
After filling, the quartz glass plate was physically peeled off. After that, the conductive surface was washed with pure water. As a result, a plurality of protrusions having a diameter of 20 μm and a height of 100 nm were formed on the conductive surface.
Electroless plating was carried out at a temperature of 60° C. for 10 minutes using an electroless plating solution having the composition shown below.
(Electroless plating solution composition)
・Copper sulfate pentahydrate ( _CuSO4.5H2O ) 0.032 mol _/ ^dm3
· Sodium citrate dihydrate (C ₆ H ₅ Na ₃ O ₇ 2H ₂ O) 0.052 mol/dm ³
・Sodium dihydrogen phosphate dihydrate (NaH ₂ PO _{4.2H 2} O) 0.54 mol/dm ³
・Boric acid (H ₃ BO ₃ ) 0.50 mol/dm ³

(Example 2)
Example 2 was the same as Example 1 except for the configuration of the mold member, the method of removing the mold member, and the size of the projecting portion.
In Example 2, a fine porous alumina plate having an average pore size of 5 μm was used as the mold member.
As a method for removing the mold member, the mold member was immersed in a 10% NaOH solution for 10 minutes to dissolve the mold member, and then washed with pure water. The protrusions were 5 μm in diameter and 100 nm in height.
(Example 3)
Example 3 was the same as Example 1 except for the structure of the mold member, the method of removing the mold member, and the size of the projecting portion.
In Example 3, an anodized film with a pore size of 60 nm and a thickness of 40 μm was used for the mold member. The anodized film was produced using aluminum. The mold member is made of aluminum oxide with a plurality of through holes.
As a method for removing the mold member, the mold member was immersed in a 10% NaOH solution for 10 minutes to dissolve the mold member, and then washed with pure water. The protrusions were 60 nm in diameter and 100 nm in height.

(Example 4)
Compared with the first embodiment, the fourth embodiment has a configuration of the mold member, a method of filling the mold member, a method of applying the mold member, a method of removing the mold member, a method of manufacturing the projection, and the projection. , but otherwise the same as in Example 1. In Example 4, the protrusions were formed by etching.
In Example 4, an anodic oxide film with a thickness of 40 μm and having recesses with a hole diameter of 60 nm was used for the mold member. The anodized film was produced using an aluminum plate. The mold member is composed of aluminum oxide formed continuously on an aluminum plate.
After the mold member was immersed in nitric acid (15% aqueous solution), the mold member was pressed against the conductive surface and held there for 2 minutes while the nitric acid aqueous solution was wiped off from the surface of the mold member. After peeling the mold member from the conductive surface, the conductive surface was washed with pure water. As a result, protrusions were formed on the conductive surface. The protrusions were honeycomb-shaped with a thickness of 40 nm.

(Comparative example 1)
Comparative Example 1 is different from Example 1 except that a TEG chip having a conductive layer with a side of 100 μm is used. in Comparative Example 1; No protrusions were formed on the conductive surface. Therefore, in Table 1 below, "-" is indicated in the columns of "constitution of mold member", "filling method", "removing method of mold member", and "shape of protrusion".

As shown in Table 1, Examples 1 to 4 were better than Comparative Example 1 in terms of bonding and conductivity. In this way, it was possible to easily achieve highly reliable bonding with the object to be bonded.

REFERENCE SIGNS LIST 10 semiconductor element 10a surface 12 conductive layer 12a surface 12c end surface 14 mold member 15 filling portion 15a substrate 15b through hole 15c surface 16a treatment liquid 17 projecting portion 17a gap 18 structure 19 conductive member 20 mold member 21 recess 22 substrate 23 Bottom 30, 32 Semiconductor element 33 Semiconductor layer 33a, 34a, 36a, 46a Surface 34 Rewiring layer 36 Passivation layer 37 Wiring 38 Pad 39 Junction 40 Laminated device 42, 44, 46, 62 Semiconductor element 44b Back 45 Interposer 47 Sensor Chip 48 Lens 50 First Semiconductor Wafer 50a Surface 52 Second Semiconductor Wafer 60 Semiconductor Package 64 Mold Resin 70 Wiring Board 72 Insulating Base Material 74 Wiring Layer 75 Solder Ball 80 Printed Wiring Board 82 Insulating Base Material 84 Wiring Layer 90 Linear conductor 91 Insulating substrate 92 Signal wiring 93 Ground wiring 94 Insulating layer 95 Wiring layer 100a, 100b, 100c, 100d Electronic device 104, 106, 108, 116, 117, 121 Semiconductor element 118 Electrode 122 Region 123 Optical waveguide 125 Light-emitting element 126 Light-receiving element d Diameter of through hole dt Diameter of recess Dc Diameter of protrusion Ds Lamination direction Dt Thickness direction H Height of protrusion h Thickness of shaped member ht Length of recess Ld Emitted light Lo Light p Distance between centers x direction w substrate width wt substrate width Wc gap distance

Claims (8)

a preparation step of preparing a conductive substrate having a conductive surface having conductivity, and a mold member having a portion to be filled composed of a plurality of recesses or a plurality of through holes;
an applying step of bringing the filled portion of the mold member into contact with at least the conductive surface;
and a removing step of removing the mold member,
Between the preparing step and the removing step, a first filling step of filling the portion to be filled with a conductive material, or a second filling step of filling the portion to be filled with a treatment liquid that dissolves the conductive base material. has a filling process of
The mold member is removed by the removing step to form a plurality of conductive protrusions on the conductive surface ,
A method of manufacturing a structure, wherein the first filling step or the second filling step is performed between the applying step and the removing step. 2. The method of manufacturing a structure according to claim 1, wherein said conductive material filled in said first filling step is the same as the conductive material contained in said conductive surface of said conductive substrate. The applying step is a step of bringing the plurality of through holes of the mold member into contact with the conductive surface,
The first filling step is a step of filling the plurality of through holes of the mold member with the conductive material while the plurality of through holes of the mold member are in contact with the conductive surface. Item 1. A method for manufacturing the structure according to item 1 . The method of manufacturing a structure according to any one of claims 1 to 3, wherein the mold member is composed of an anodized valve metal film having a plurality of micropores. 5. The method of manufacturing a structure according to claim 4, wherein said valve metal is aluminum. 6. The method of manufacturing a structure according to claim 1, wherein said removing step removes said mold member by etching. preparing at least one structure manufactured by the structure manufacturing method according to any one of claims 1 to 6;
A joined body, comprising: a joining step of arranging the plurality of conductive projections formed on the conductive surface of the structure toward an object to be joined, and joining the structure and the object to be joined. manufacturing method. preparing a plurality of the structures,
8. The bonding step according to claim 7, wherein said joining step is a step of joining one said structure out of a plurality of said structures and said joining object comprising another said structure out of said plurality of said structures. A method for producing a conjugate of

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