CN115003864B

CN115003864B - Method for manufacturing metal-filled microstructure

Info

Publication number: CN115003864B
Application number: CN202080094351.7A
Authority: CN
Inventors: 糟谷雄一
Original assignee: Fujifilm Corp
Current assignee: Fujifilm Corp
Priority date: 2020-01-31
Filing date: 2020-12-23
Publication date: 2024-08-16
Anticipated expiration: 2040-12-23
Also published as: JP7369797B2; TW202130861A; CN115003864A; WO2021153112A1; JPWO2021153112A1

Abstract

The present invention provides a method for manufacturing a metal-filled microstructure, which suppresses metal filling defects into a plurality of pores when filling metal into the plurality of pores. The method for producing a metal-filled microstructure comprises: providing an insulating film having a plurality of pores on the surface of the metal member, thereby obtaining a structure having the metal member and the insulating film; and a plating step of plating the surface of the structure on at least the side having the insulating film in a supercritical state or a subcritical state with a metal, wherein the plurality of pores are filled with a metal. At the beginning of the plating process, a metal layer other than the valve metal is present at the bottom of the pores of the structure, and a metal layer other than the valve metal is formed in the bottom of the pores in a region of 80% or more of the area.

Description

Method for manufacturing metal-filled microstructure

Technical Field

The present invention relates to a method for producing a metal-filled microstructure in which a metal is filled in a plurality of pores in an oxide film having a plurality of pores, and more particularly, to a method for producing a metal-filled microstructure in which a metal is filled in a plurality of pores by metal plating in a supercritical state or subcritical state.

Background

A metal-filled microstructure in which a plurality of through holes penetrating an insulating substrate such as an oxide film in the thickness direction are filled with a metal is one of fields in which nanotechnology has been attracting attention in recent years. The metal-filled microstructure is expected to be used for, for example, electrodes for batteries, breathable films, sensors, anisotropic conductive members, and the like.

Since an anisotropic conductive member is interposed between an electronic component such as a semiconductor element and a circuit board and an electrical connection between the electronic component and the circuit board is obtained only by pressing, the anisotropic conductive member is widely used as an electrical connection member for the electronic component such as the semiconductor element and an inspection connector for performing a functional inspection.

In particular, miniaturization of electronic parts such as semiconductor devices is remarkable. In the conventional method of directly connecting a wiring board such as wire bonding, flip chip bonding, thermocompression bonding, and the like, since the stability of electrical connection of electronic parts cannot be sufficiently ensured, an anisotropic conductive member has been attracting attention as an electronic connection member.

In the above method for producing a metal-filled microstructure, a plating method is used when filling a plurality of through holes with a metal. As the plating method, electroplating or electroless plating is used. Further, for example, as described in patent document 1, the following plating method is described: a plating solution containing at least one of carbon dioxide and an inert gas, and a surfactant dispersed by adding a metal powder to an insoluble metal powder in an amount of at least one of the above, wherein the metal powder is plated by an induced eutectoid phenomenon in a supercritical state or a subcritical state. The metal powder is the same kind of metal as at least one of the metal base and the metal coating film obtained by the plating treatment.

As described in patent document 2, there is also a method of: when the magnetic material is filled in the pores, the supercritical fluid or subcritical fluid containing the magnetic material particles is used, and the supercritical fluid or subcritical fluid is caused to flow into the pores, thereby filling the pores with the magnetic material.

Technical literature of the prior art

Patent literature

Patent document 1: japanese patent No. 4163728

Patent document 2: japanese patent laid-open No. 2008-305143

Disclosure of Invention

Technical problem to be solved by the invention

In the metal-filled microstructure, it is necessary to consider the possibility that filling defects may occur in all pores, such as insufficient filling of metal. In both patent document 1 and patent document 2, the supercritical state and the subcritical state are used, but it may not be possible to sufficiently fill all the pores with the metal by using only the supercritical state and the subcritical state.

The purpose of the present invention is to provide a method for producing a metal-filled microstructure, wherein metal filling defects into a plurality of pores are suppressed when metal is filled into the plurality of pores.

Means for solving the technical problems

In order to achieve the above object, the 1 st aspect of the present invention provides a method for producing a metal-filled microstructure, comprising: providing an insulating film having a plurality of pores on the surface of the metal member, thereby obtaining a structure having the metal member and the insulating film; and a plating step of plating the surface of the structure on at least the side having the insulating film in a supercritical state or a subcritical state, and filling a metal into the plurality of pores, wherein at the start of the plating step, a metal layer other than the valve metal is present at the bottom of the pores of the structure, and a metal layer other than the valve metal is formed in a region of 80% or more of the area in the bottom of the pores.

The step of forming a metal layer other than the valve metal at the bottom of the pores is preferably provided between the step of obtaining the structure and the plating step, and the plating step is preferably performed in a state where a metal layer other than the valve metal is formed in 80% or more of the area of the bottom of the pores at the start of the plating step.

Preferably, the metal member is made of a metal other than the valve metal, and the metal member is exposed at the bottom of the pore.

The average diameter of the plurality of pores is preferably 1 μm or less.

Preferably, the insulating film is an oxide film. Preferably, the oxide film is an anodic oxide film of aluminum.

Preferably, the metal layer other than the valve metal is composed of a metal more noble than aluminum. Preferably, the metal component is composed of a noble metal or a valve metal.

Effects of the invention

According to the present invention, when the metal is filled in the plurality of pores, the metal filling defect into the plurality of pores can be suppressed.

Drawings

Fig. 1 is a schematic cross-sectional view showing a step of embodiment 1 of a method for producing a metal-filled microstructure according to an embodiment of the present invention.

Fig. 2 is a schematic cross-sectional view showing a step of embodiment 1 of the method for producing a metal-filled microstructure according to the embodiment of the present invention.

Fig. 3 is a schematic cross-sectional view showing a step of embodiment 1 of the method for producing a metal-filled microstructure according to the embodiment of the present invention.

Fig. 4 is a schematic cross-sectional view showing a step of embodiment 1 of the method for producing a metal-filled microstructure according to the embodiment of the present invention.

Fig. 5 is a schematic cross-sectional view showing a step of embodiment 1 of the method for producing a metal-filled microstructure according to the embodiment of the present invention.

Fig. 6 is a schematic cross-sectional view showing an enlarged view of a step of embodiment 1 of the method for producing a metal-filled microstructure according to the embodiment of the invention.

Fig. 7 is a schematic cross-sectional view showing a step of embodiment 2 of the method for producing a metal-filled microstructure according to the embodiment of the invention.

Fig. 8 is a schematic cross-sectional view showing a step of embodiment 2 of the method for producing a metal-filled microstructure according to the embodiment of the invention.

Fig. 9 is a schematic cross-sectional view showing a step of embodiment 2 of the method for producing a metal-filled microstructure according to the embodiment of the invention.

Fig. 10 is a schematic cross-sectional view showing a step of embodiment 2 of the method for producing a metal-filled microstructure according to the embodiment of the invention.

Fig. 11 is a schematic cross-sectional view showing an enlarged view of a step of embodiment 2 of the method for producing a metal-filled microstructure according to the embodiment of the invention.

Fig. 12 is a schematic view showing an electroplating apparatus used in a plating process in the method for manufacturing a metal-filled microstructure according to the embodiment of the present invention.

Fig. 13 is a plan view showing an example of a metal-filled microstructure according to an embodiment of the present invention.

Fig. 14 is a schematic cross-sectional view showing an example of a metal-filled microstructure according to an embodiment of the present invention.

Fig. 15 is a schematic cross-sectional view showing an example of a structure of an anisotropic conductive material using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 16 is a schematic view showing example 1 of a stacked device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 17 is a schematic diagram showing example 2 of a stacked device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 18 is a schematic diagram showing example 3 of a stacked device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 19 is a schematic view showing a 4 th example of a stacked device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 20 is a schematic view showing a step of example 1 of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 21 is a schematic view showing a step of example 1 of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 22 is a schematic view showing a step of example 1 of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 23 is a schematic view showing a step of example 2 of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 24 is a schematic view showing a step of example 2 of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 25 is a schematic view showing a step of example 2 of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 26 is a schematic view showing a step of example 3 of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 27 is a schematic view showing a step of example 3 of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 28 is a schematic diagram showing a 5 th example of a stacked device according to an embodiment of the present invention.

Fig. 29 is a schematic view showing a 6 th example of a stacked device according to an embodiment of the present invention.

Fig. 30 is a schematic diagram showing a 7 th example of a stacked device according to an embodiment of the present invention.

Fig. 31 is a schematic view showing an 8 th example of a stacked device according to an embodiment of the present invention.

Fig. 32 is a schematic diagram showing example 9 of a stacked device according to an embodiment of the present invention.

Fig. 33 is a schematic view showing a step of example 4 of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 34 is a schematic view showing a step of example 4 of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 35 is a schematic view showing a step of example 4 of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 36 is a schematic view showing a step of example 4 of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 37 is a schematic view showing a step of example 4 of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 38 is a schematic view showing a step of example 4 of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 39 is a schematic diagram showing a step of example 4 of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 40 is a schematic view showing a step of example 4 of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 41 is a schematic view showing a step of example 4 of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 42 is a schematic view showing a step of example 4 of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 43 is a schematic view showing a step of example 4 of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 44 is a schematic view showing a step of a method for manufacturing a laminated body used in example 4 of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 45 is a schematic view showing a step of a method for manufacturing a laminated body used in example 4 of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 46 is a schematic diagram showing a step of a method for manufacturing a laminated body used in example 4 of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 47 is a schematic view showing a step of a method for manufacturing a laminated body used in example 4 of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 48 is a schematic diagram showing a step of a method for manufacturing a laminated body used in example 4 of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 49 is a schematic view showing a step of example 5 of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 50 is a schematic view showing a step of the 5 th example of the method for manufacturing a laminated device using a metal-filled microstructure according to the embodiment of the present invention.

Fig. 51 is a schematic view showing a step of the 5 th example of the method for manufacturing a laminated device using a metal-filled microstructure according to the embodiment of the present invention.

Fig. 52 is a schematic view showing a step of the 5 th example of the method for manufacturing a laminated device using the metal-filled microstructure according to the embodiment of the present invention.

Fig. 53 is a schematic view showing a step of example 5 of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 54 is a schematic view showing a step of the 5 th example of the method for manufacturing a laminated device using the metal-filled microstructure according to the embodiment of the present invention.

Fig. 55 is a schematic view showing a step of example 5 of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 56 is a schematic view showing a step of the 5 th example of the method for manufacturing a laminated device using the metal-filled microstructure according to the embodiment of the present invention.

Fig. 57 is a schematic view showing a step of example 5 of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 58 is a schematic view showing a step of the 5 th example of the method for manufacturing a laminated device using the metal-filled microstructure according to the embodiment of the present invention.

Fig. 59 is a schematic view showing a step of example 5 of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 60 is a schematic view showing a step of the 5 th example of the method for manufacturing a laminated device using the metal-filled microstructure according to the embodiment of the present invention.

Fig. 61 is a schematic view showing a step of example 5 of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 62 is a schematic view showing a step of example 6 of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 63 is a schematic view showing a step of example 6 of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 64 is a schematic view showing a step of example 6 of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 65 is a schematic view showing a step of example 6 of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 66 is a schematic view showing a step of example 6 of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 67 is a graph showing example 1 of the main joint condition.

Fig. 68 is a graph showing example 2 of the main joint condition.

Fig. 69 is a graph showing example 3 of the main joint condition.

Fig. 70 is a graph showing the 4 th example of the main joint condition.

Fig. 71 is a graph showing the 5 th example of the main joint condition.

Fig. 72 is a graph showing example 6 of the main joint condition.

Fig. 73 is a graph showing the 7 th example of the main joint condition.

Detailed Description

The method for producing the metal-filled microstructure according to the present invention will be described in detail below with reference to preferred embodiments shown in the drawings.

The drawings described below are illustrative drawings for explaining the present invention, and the present invention is not limited to the drawings described below.

The term "to" representing the numerical range "as used hereinafter means that the numerical values described on both sides are included. For example, epsilon is a numerical value alpha to a numerical value beta means that epsilon ranges from the numerical value alpha to the numerical value beta, and alpha is equal to or less than epsilon and equal to or less than beta when expressed by mathematical symbols.

Unless otherwise specified, angles such as "orthogonal" and the like, temperatures and pressures include the error ranges generally allowable in the corresponding technical fields.

Also, "identical" is meant to include the range of errors that are generally accepted in the corresponding art. Also, "the entire surface" and the like include an error range generally allowable in the corresponding technical field.

There is a great need for filling plated metal into through holes of an insulating substrate such as an anodic oxide film of aluminum having very fine through holes. But may create local filling defects. If the filling defect is used for experiments, it does not become a problem, but if the area of the metal-filled microstructure is increased for use in a battery electrode, a gas permeable film, a sensor, or the like, an effect such as poor bonding occurs due to the filling defect.

Hereinafter, a method for manufacturing a metal-filled microstructure will be described in detail. The metal-filled microstructure produced has an insulating base material composed of an insulating film. The insulating film is made of an oxide film, for example. The oxide film is not particularly limited, and is composed of an anodic oxide film of aluminum. The oxide film is formed of an anodic oxide film of aluminum. In this case, an aluminum member is used as the metal member.

< Mode 1>

Fig. 1 to 5 are schematic cross-sectional views showing, in order of steps, embodiment 1 of a method for producing a metal-filled microstructure according to the embodiment of the invention. Fig. 6 is a schematic cross-sectional view showing an enlarged view of a step of embodiment 1 of the method for producing a metal-filled microstructure according to the embodiment of the invention.

First, as a metal member, for example, an aluminum member 10 shown in fig. 1 is prepared.

The aluminum member 10 is appropriately sized and has a thickness according to the thickness of the anodized film 14 of aluminum of the metal-filled microstructure 20 (see fig. 5) to be finally obtained, that is, the thickness of the insulating base material, the device to be processed, and the like. The aluminum member 10 is, for example, a rectangular plate material.

Next, the surface 10a (see fig. 1) of one side of the aluminum member 10 is anodized. As a result, the surface 10a (see fig. 1) of the aluminum member 10 is anodized, and as shown in fig. 2, an anodized film 14 having a barrier layer 13 is formed, and the barrier layer 13 is present at the bottom of the plurality of through holes 12 extending in the thickness direction Dt of the aluminum member 10. The step of performing the above-described anodic oxidation is referred to as an anodic oxidation treatment step. For example, an oxide film having a plurality of pores is provided on the surface of a metal member by anodic oxidation treatment, thereby obtaining a structure having the metal member and the oxide film. That is, the surface 10a of one side of the aluminum member 10 is anodized, and the anodized film 14 of aluminum having the plurality of through holes 12 is provided on the surface 10a of the aluminum member 10, thereby obtaining the structure 17 having the aluminum member 10 and the anodized film 14.

The structure 17 is not limited to the structure obtained by anodizing the aluminum member 10. As will be described later, the structure 17 can also be obtained by a method of providing a metal member on an oxide film.

In the anodized film 14 having the plurality of through holes 12, the barrier layer 13 is present at the bottom of the through holes 12 as described above, but the barrier layer 13 is removed as shown in fig. 3. The step of removing the barrier layer 13 is referred to as a barrier layer removal step.

In the barrier removal step, the barrier layer 13 of the anodized film 14 is removed by using an alkaline aqueous solution containing ions of the metal M1 having a higher hydrogen overvoltage than aluminum, and for example, a metal layer 15a composed of a metal other than a valve metal (metal M1) is formed on the bottom 12c of the through hole 12 of the structure 17. Thereby, the metal layer 15a other than the valve metal is exposed at the bottom 12c of the through hole 12 of the structure 17.

Specifically, as shown in fig. 6, a metal layer 15a is formed on the surface 10a of the aluminum member 10 at the bottom 12c of the through hole 12 of the structure 17. In this case, the bottom 12c of the through hole 12 in the structure 17 is formed of the metal layer 15a other than the valve metal over 80% of the area. The ratio of forming a metal layer other than the valve metal in the bottom region of the pores is referred to as an area ratio. In the bottom 12c of the through hole 12 in the structure 17, when the metal layer 15a is formed in a region of 80% or more of the area, the area ratio of the metal layer 15a is 80%.

The metal layer 15a is preferably formed in the bottom 12c of the through hole 12 in a region of 80% or more of the area, more preferably in the surface 12d of the bottom 12c of the through hole 12 in a region of 95% or more of the area, and most preferably in the bottom 12c of the through hole 12 in a region of 100%.

The barrier layer removing step also serves as a step of forming a metal layer made of a metal other than the valve metal at the bottom of the pores. The step of forming the metal layer is performed between the step of obtaining the structure and the plating step.

In the plating step, at the start of the plating step, a metal layer other than the valve metal is present at the bottom 12c of the through hole 12, and a metal layer 15a or the like is formed in a region of 80% or more of the surface 10a of the aluminum member 10 located at the bottom 12c of the through hole 12. Thus, when the metal is filled in the through-holes 12 by metal plating, plating is easy, and insufficient filling of the metal can be suppressed, and the metal can be suppressed from being not filled in the through-holes 12 or the like.

In addition, in the surface 10a of the aluminum member 10 in the structure 17, the ratio covered by the metal layer 15a is calculated as follows: the anodized film was cut in the thickness direction by FIB (Focused Ion Beam), a surface photograph (magnification 5 ten thousand times) of 10 fields was taken by FE-SEM in a cross section thereof, and the area ratio of the metal layer formed on the surface of the member in which the fine holes in each field were exposed was measured as an average value thereof.

The bottom 12c of the through hole 12 of the structure 17 is not limited to a structure in which an area of 80% or more of the surface 10a of the aluminum member 10 in the structure 17 is covered with the metal layer 15a as shown in fig. 6, as long as a metal layer other than the valve metal is formed in an area of 80% or more.

Next, in the structure 17, a plating step of plating the surface of the surface having at least the oxide film, that is, the surface having the anodized film 14, with metal is performed in a supercritical state or subcritical state, whereby the metal 15b is filled in the through-hole 12 of the anodized film 14, as shown in fig. 4. By filling the metal 15b in the through hole 12, a conductive via 16 is formed. In this case, the metal layer 15a composed of metal (metal M1) can be used as an electrode at the time of metal plating. The plating step of filling the metal 15b in the through-hole 12 will be described in detail later. In addition, the metal layer 15a and the metal layer 15b are collectively referred to as the filled metal 15.

After the plating process, as shown in fig. 5, the aluminum member 10 is removed. Thus, the metal-filled microstructure 20 is obtained. The step of removing the aluminum member 10 is referred to as a substrate removal step.

In the barrier removal step before the plating step, the barrier layer is removed by using an alkaline aqueous solution containing ions of the metal M1 having a higher hydrogen overvoltage than that of the metal member (for example, aluminum), and thereby, not only the barrier layer 13 but also the metal layer 15a of the metal M1 which is less likely to generate hydrogen than aluminum is formed on the aluminum member 10 exposed at the bottom 12c of the through hole 12. As a result, the in-plane uniformity of the metal filling becomes good. It is considered that the generation of hydrogen gas caused by the plating solution is suppressed and that the metal filling by the plating is easily performed.

The detailed mechanism is not clear, but it is considered that the reason for this is that, in the barrier layer removal step, the metal M1 layer is formed under the barrier layer by using an alkaline aqueous solution containing ions of the metal M1, so that the interface between the aluminum member and the anodized film is prevented from being damaged, and the uniformity of dissolution of the barrier layer is improved. In this case, the metal layer 15a covers 80% or more of the area of the surface 10a of the aluminum member 10 in the structure 17.

In the barrier removal step, the metal layer 15a made of metal (metal M1) is formed on the bottom 12c of the through hole 12, but the present invention is not limited thereto, and only the barrier layer 13 is removed to expose the aluminum member 10 on the bottom of the through hole 12. On the surface 10a of the aluminum member 10 exposed at the bottom of the through hole 12, a metal layer 15a is formed as a coating material by, for example, vapor deposition or plating.

In the above aspect 1, the metal protrusion step or the resin layer formation step may be included. The metal protrusion step and the resin layer forming step will be described later.

< Mode 2>

Fig. 7 to 10 are schematic cross-sectional views showing the mode 2 of the method for producing a metal-filled microstructure according to the embodiment of the invention in the sequence of steps. Fig. 11 is a schematic cross-sectional view showing an enlarged view of a step of embodiment 2 of the method for producing a metal-filled microstructure according to the embodiment of the invention. In fig. 7 to 11, the same reference numerals are given to the same structural objects as those shown in fig. 1 to 5, and detailed description thereof will be omitted.

The difference of the 2 nd embodiment from the 1 st embodiment is that the metal member 24 (see fig. 9 and 11) is used instead of the aluminum member 10.

The following steps are different from those in the above-described 1 st aspect in the 2 nd aspect. In the structure 17 having the aluminum member 10 and the anodized film 14 shown in fig. 2 in the embodiment 1, the aluminum member 10 is removed in the embodiment 2 to obtain the anodized film 14 shown in fig. 7. Since the aluminum member 10 can be removed by the substrate removal process, a detailed description thereof will be omitted.

Next, the through-holes 12 of the anodized film 14 shown in fig. 7 are expanded in diameter and the barrier layer 13 is removed, whereby, as shown in fig. 8, a plurality of through-holes 12 penetrating in the thickness direction Dt are formed in the anodized film 14.

For example, a reaming process is used to enlarge the through-hole 12 (fine hole). The pore expansion treatment is a treatment of expanding the diameter of the through-hole 12 (pore) by immersing the anodic oxide film in an acidic aqueous solution or an alkaline aqueous solution to dissolve the anodic oxide film. In the reaming treatment, an aqueous solution of an inorganic acid such as sulfuric acid, phosphoric acid, nitric acid, hydrochloric acid, or a mixture thereof, or an aqueous solution of sodium hydroxide, potassium hydroxide, lithium hydroxide, or the like can be used.

Next, the metal member 24 is formed on the entire surface of the rear surface 14b of the anodized film 14 shown in fig. 8, for example, as shown in fig. 9. Thus, the structure 17 is obtained, and the structure 17 is provided with the anodic oxide film 14 having the plurality of through holes 12 on the surface 24a of the metal member 24, and has the metal member 24 and the anodic oxide film 14. The step of forming the metal member 24 is referred to as a metal member forming step.

In the metal member forming step, for example, vapor deposition, sputtering, electroless plating, or the like is used to form the metal member 24. The metal member 24 is preferably made of a metal other than a valve metal, for example, a noble metal such as Au (gold). The metal member 24 may be the same as the metal layer 15a described above.

As shown in fig. 11, a metal member 24 is provided on the rear surface 14b side of the anodic oxidation film 14. The metal member 24 covers all openings on the rear surface 14b side of the anodic oxide film 14 of the through hole 12. The metal member 24 is made of Au, for example, and 100% of the surface 24a of the metal member 24 is made of a metal other than the valve metal. By providing the metal member 24 on the rear surface 14b of the anodic oxidation film 14, a metal layer other than the valve metal is exposed on the surface 12d of the bottom 12c of the through-hole 12 of the structure 17. Further, 100% of the surface 12d of the bottom 12c of the through hole 12 can be made of a non-valve metal. Thus, when the metal is filled in the through-holes 12 by metal plating, plating is easy, and insufficient filling of the metal can be suppressed, and the metal can be suppressed from being not filled in the through-holes 12 or the like.

Next, as shown in fig. 10, in the state where the metal member 24 is formed in the anodized film 14, the metal 15b is filled in the plurality of through holes 12 by a plating step of performing metal plating in a supercritical state or a subcritical state in the interior of the through holes 12 of the anodized film 14, as in embodiment 1, thereby forming the conductive paths 16.

Next, the metal member 24 is removed to obtain the metal-filled microstructure 20 shown in fig. 5. The method for removing the metal member 24 is not particularly limited as long as the metal member 24 can be removed, and etching or polishing is exemplified.

< Other modes >

As the manufacturing method, for example, the above-described anodizing treatment step, holding step, barrier layer removal step, plating step, front metal projection step, resin layer formation step, substrate removal step, and back metal projection step may be performed in combination.

Further, a part of the surface of the aluminum member may be anodized using a mask layer having a desired shape.

In the above method for producing a metal-filled microstructure, it is possible to obtain a metal-filled microstructure having few filling defects into the through holes 12 while suppressing occurrence of local filling defects in the plurality of through holes 12 (pores). Therefore, when an anisotropic conductive member is manufactured using a metal-filled microstructure, the density of the conductive path can be significantly increased, and the structure can be used as an electrical connection member for electronic parts such as semiconductor elements, an inspection connector, and the like in the present process, in which the integration is further advanced.

[ Insulating substrate ]

The insulating base material is not particularly limited as long as it is made of an inorganic material and has a resistivity (about 10 ¹⁴ Ω·cm) of the same level as that of an insulating base material constituting a conventionally known anisotropic conductive film or the like.

The term "composed of an inorganic material" means a specification for distinguishing from a polymer material constituting a resin layer described later, and is not limited to a specification of an insulating base material composed of only an inorganic material, but a specification of an inorganic material as a main component (50 mass% or more).

As described above, the insulating base material is constituted by an oxide film. The oxide film is more preferably an anodic oxide film of a valve metal, from the viewpoint of forming a through hole having a desired average diameter and facilitating formation of a conductive path to be described later. For example, as described above, the oxide film is an anodic oxide film of aluminum. Therefore, the metal member is preferably a valve metal.

Specific examples of the valve metal include aluminum, tantalum, niobium, titanium, hafnium, zirconium, zinc, tungsten, bismuth, and antimony. Among them, an anodic oxide film of aluminum is preferable in terms of good dimensional stability and relatively low cost. Therefore, it is preferable to manufacture the metal-filled microstructure using an aluminum member.

[ Metal parts ]

The metal member is preferably formed of the valve metal, and is preferably capable of forming an anodic oxide film as described above for producing the metal-filled microstructure. As described above, an aluminum member is used as the metal member.

In addition, as in claim 2, when a metal member is provided on the anodic oxide film, a noble metal may be used in addition to the valve metal, for example. Examples of the noble metal include Au (gold), ag (silver), and platinum group (Ru, rh, pd, os, ir, pt).

< Aluminum Member >

The aluminum member is not particularly limited, and specific examples thereof include: a pure aluminum plate; an alloy sheet containing aluminum as a main component and a trace amount of a hetero element; a substrate on which low purity aluminum (for example, recycled material) is vapor-deposited with high purity aluminum; a substrate coated with high-purity aluminum on the surfaces of a silicon wafer, quartz, glass and the like by vapor deposition, sputtering and other methods; an aluminum-laminated resin substrate; etc.

In the aluminum member, the purity of aluminum on the surface on which the anodized film is provided in the anodizing treatment step is preferably 99.5 mass% or more, more preferably 99.9 mass% or more, and still more preferably 99.99 mass% or more. When the purity of aluminum is within the above range, the regularity of the arrangement of the through holes becomes sufficient.

The surface of the aluminum member on the side to which the anodic oxidation treatment step is performed is preferably subjected to a heat treatment, degreasing treatment, and mirror finishing treatment in advance.

Here, the heat treatment, degreasing treatment, and mirror finishing treatment can be performed in the same manner as the treatments described in paragraphs [0044] to [0054] of jp 2008-270158 a.

[ Anodic oxidation treatment Process ]

The anodic oxidation process comprises the following steps: and a step of forming an anodized film having a through hole penetrating in the thickness direction and a barrier layer existing at the bottom of the through hole on one surface of the aluminum member by performing an anodizing treatment on the one surface of the aluminum member.

The anodic oxidation treatment can be performed by a conventionally known method, but from the viewpoint of improving the regularity of the arrangement of the through holes and ensuring the anisotropic conductivity of the metal-filled microstructure, a self-regularization method or a constant pressure treatment is preferably used.

Here, the self-regularization method and constant pressure treatment of the anodic oxidation treatment can be performed in the same manner as the treatments described in paragraphs [0056] to [0108] and [ fig. 3] of japanese patent application laid-open No. 2008-270158.

< Anodic oxidation treatment >

The average flow rate of the electrolyte in the anodic oxidation treatment is preferably 0.5 to 20.0m/min, more preferably 1.0 to 15.0m/min, and even more preferably 2.0 to 10.0m/min.

The method of flowing the electrolyte under the above conditions is not particularly limited, and for example, a method using a general stirring device such as a stirrer may be used. In particular, if a stirrer capable of controlling the stirring speed by digital display is used, the average flow rate can be controlled, which is preferable. Examples of such stirring devices include "magnetic stirrer HS-50D (manufactured by AS ONE CORPORATION)".

For example, the anodic oxidation treatment may be performed by a method in which an aluminum member is electrified as an anode in a solution having an acid concentration of 1 to 10 mass%.

The solution used in the anodic oxidation treatment is preferably an acid solution, more preferably sulfuric acid, phosphoric acid, chromic acid, oxalic acid, benzenesulfonic acid, sulfamic acid, glycolic acid, tartaric acid, malic acid, citric acid, and the like, and among these, sulfuric acid, phosphoric acid, and oxalic acid are particularly preferred. These acids can be used singly or in combination of 2 or more.

The conditions of the anodizing treatment vary variously depending on the electrolyte used, and therefore cannot be said to be generalized, but it is generally preferable that the electrolyte concentration is 0.1 to 20 mass%, the liquid temperature is-10 to 30 ℃, the current density is 0.01 to 20A/dm ², the voltage is 3 to 300V, the electrolysis time is 0.5 to 30 hours, more preferably the electrolyte concentration is 0.5 to 15 mass%, the liquid temperature is-5 to 25 ℃, the current density is 0.05 to 15A/dm ², the voltage is 5 to 250V, the electrolysis time is 1 to 25 hours, still more preferably the electrolyte concentration is 1 to 10 mass%, the liquid temperature is 0 to 20 ℃, the current density is 0.1 to 10A/dm ², the voltage is 10 to 200V, and the electrolysis time is 2 to 20 hours.

In the above-described anodizing treatment step, the average thickness of the anodized film formed by the anodizing treatment is preferably 30 μm or less, more preferably 5 to 20 μm, from the viewpoint of supplying the metal-filled microstructure 20 in a shape wound around a winding core. In addition, regarding the average thickness, the following is calculated: the anodized film was cut in the thickness direction by a Focused Ion Beam (FIB), and a surface photograph (magnification: 5 ten thousand times) was taken of a cross section thereof by a field emission scanning electron microscope (Field Emission Scanning Electron Microscope: FE-SEM) as an average value of measurement at 10 points.

[ Holding step ]

The method for producing the metal-filled microstructure may include a holding step. The holding step is as follows: after the anodizing step, the substrate is held at a voltage of 95% or more and 105% or less in a range selected from 1V or more and less than 30% of the voltage in the anodizing step for a total of 5 minutes or more. In other words, the holding step is the following step: after the anodizing step, an electrolytic treatment is performed for a total of 5 minutes or more at a voltage of 95% or more and 105% or less of a holding voltage selected from the range of 1V or more and less than 30% of the voltage in the anodizing step. By the holding step, the uniformity of metal filling at the time of plating treatment is greatly improved.

Here, the "voltage in the anodic oxidation treatment" is a voltage applied between aluminum and the counter electrode, and is an average value of voltages held during 30 minutes when the electrolysis time by the anodic oxidation treatment is 30 minutes, for example.

The voltage in the holding step is preferably 5% to 25% of the voltage in the anodic oxidation treatment, more preferably 5% to 20% from the viewpoint of controlling the thickness of the barrier layer to an appropriate thickness with respect to the sidewall thickness of the anodic oxide film, that is, the depth of the through hole.

Further, the total holding time in the holding step is preferably 5 minutes to 20 minutes, more preferably 5 minutes to 15 minutes, and even more preferably 5 minutes to 10 minutes, from the viewpoint of further improving the in-plane uniformity.

The holding time in the holding step may be a total of 5 minutes or more, and preferably 5 minutes or more.

The voltage in the holding step may be set to be continuously or stepwise (stepwise) lower from the voltage in the anodizing step to the voltage in the holding step, but is preferably set to be 95% to 105% of the holding voltage within 1 second after the end of the anodizing step for the reason of further improving the in-plane uniformity.

The holding step may be performed continuously with the anodizing step by, for example, lowering the electrolytic potential at the end of the anodizing step.

The holding step may use the same electrolytic solution and the same treatment conditions as those of the conventional known anodic oxidation treatment, except for the electrolytic potential.

In particular, it is preferable to perform the treatment using the same electrolyte when the holding step and the anodizing step are performed continuously.

[ Barrier removal Process ]

The barrier layer removal step is a step of removing the barrier layer of the anodized film using, for example, an alkaline aqueous solution containing ions of the metal M1 having a higher hydrogen overvoltage than aluminum.

Through the above-described barrier removal process, the barrier is removed, and as also shown in fig. 3, a metal layer 15a composed of the metal M1 is formed on the bottom 12c of the through hole 12.

Here, the hydrogen overvoltage (hydrogen overvoltage) means a voltage required for generating hydrogen, for example, the hydrogen overvoltage of aluminum (Al) is-1.66V (J.J.Chem.1982, (8), p 1305-1313). In addition, examples of the metal M1 having a higher hydrogen overvoltage than aluminum and hydrogen overvoltage values thereof are shown below.

< Metal M1 and Hydrogen (1N H ₂SO₄) overvoltage >

Platinum (Pt): 0.00V

Gold (Au): 0.02V

Silver (Ag): 0.08V

Nickel (Ni): 0.21V

Copper (Cu): 0.23V

Tin (Sn): 0.53V

Zinc (Zn): 0.70V

The metal M1 used in the barrier removal step is preferably a metal having a higher ionization tendency than the metal M2 used in the plating step, from the viewpoint of reducing the influence on the electrical characteristics of the metal filled in the through-holes due to substitution reaction with the metal M2 filled in the anodic oxidation step described later.

Specifically, in the case where copper (Cu) is used as the metal M2 in the plating step, the metal M1 used in the barrier layer removing step is preferably a metal other than a valve metal, which is more noble than aluminum.

In addition, a metal more noble than aluminum refers to a metal less susceptible to ionization than aluminum. A more noble metal than aluminum is, for example Zn, cr, fe, co, ni, sn, pb, cu, ag, au.

Examples of the metal M1 include Zn, fe, ni, sn, among which Zn and Ni are preferably used, and Zn is more preferably used.

In the case where Ni is used as the metal M2 in the plating step, examples of the metal M1 used in the barrier layer removing step include Zn and Fe, and among them, zn is preferably used.

The method for removing the barrier layer using the alkaline aqueous solution containing the ions of the metal M1 is not particularly limited, and examples thereof include the same method as conventionally known chemical etching treatment.

< Chemical etching treatment >

The removal of the barrier layer by chemical etching treatment can be performed, for example, by immersing the structure after the anodic oxidation treatment step in an alkaline aqueous solution, filling the interior of the through-hole with the alkaline aqueous solution, and then bringing the surface of the anodic oxide film on the opening side of the through-hole into contact with a pH (hydrogen ion index) buffer solution, or the like, whereby only the barrier layer can be selectively dissolved.

Here, as the alkaline aqueous solution containing ions of the metal M1, an aqueous solution of at least one alkali selected from the group consisting of sodium hydroxide, potassium hydroxide, and lithium hydroxide is preferably used. The concentration of the alkaline aqueous solution is preferably 0.1 to 5 mass%. The temperature of the alkaline aqueous solution is preferably 10 to 60 ℃, more preferably 15 to 45 ℃, and even more preferably 20 to 35 ℃.

Specifically, for example, 50g/L of an aqueous phosphoric acid solution at 40℃or 0.5g/L of an aqueous sodium hydroxide solution at 30℃or 0.5g/L of an aqueous potassium hydroxide solution at 30℃is preferably used.

As the pH buffer, a buffer corresponding to the above-mentioned alkaline aqueous solution can be suitably used.

The time for immersing the aqueous alkaline solution is preferably 5 to 120 minutes, more preferably 8 to 120 minutes, still more preferably 8 to 90 minutes, and particularly preferably 10 to 90 minutes. Among them, it is preferably 10 to 60 minutes, more preferably 15 to 60 minutes.

[ Other examples of Barrier removal Process ]

In addition to the above, the barrier layer removal step may be a step of removing the barrier layer of the anodized film and exposing a part of the aluminum member at the bottom of the through hole.

In this case, the method of removing the barrier layer is not particularly limited, and examples thereof include: a method of electrochemically dissolving the barrier layer at a potential lower than that in the anodic oxidation treatment step (hereinafter, also referred to as "electrolytic removal treatment"); a method of removing the barrier layer by etching (hereinafter, also referred to as "etching removal process"); and a method of combining these (in particular, a method of removing a residual barrier layer by an etching removal process after performing an electrolytic removal process).

< Electrolytic removal treatment >

The electrolytic removal process is not particularly limited as long as it is an electrolytic process performed at a potential lower than the potential (electrolytic potential) in the anodic oxidation process.

The electrolytic dissolution treatment can be performed continuously with the anodic oxidation treatment by, for example, lowering the electrolytic potential at the end of the anodic oxidation treatment step.

The electrolytic removal treatment may be performed under conditions other than the electrolytic potential, using the same electrolytic solution and the same treatment conditions as those used in the conventional known anodic oxidation treatment.

In particular, as described above, in the case where the electrolytic removal treatment and the anodic oxidation treatment are continuously performed, it is preferable to perform the treatment using the same electrolytic solution.

(Electrolytic potential)

The electrolytic potential in the electrolytic removal process is preferably continuously or stepwise (stepwise) lowered to a potential lower than the electrolytic potential in the anodic oxidation process.

Here, from the viewpoint of the withstand voltage of the barrier layer, the reduction width (step width) when the electrolytic potential is reduced stepwise is preferably 10V or less, more preferably 5V or less, and further preferably 2V or less.

In addition, from the viewpoint of productivity and the like, the voltage drop rate when the electrolysis potential is continuously or stepwise reduced is preferably 1V/sec or less, more preferably 0.5V/sec or less, and further preferably 0.2V/sec or less.

< Etching removal treatment >

The etching removal treatment is not particularly limited, and may be a chemical etching treatment in which dissolution is performed using an acidic aqueous solution or an alkaline aqueous solution, or may be a chemical etching treatment.

(Chemical etching treatment)

The removal of the barrier layer by chemical etching treatment can be performed, for example, by immersing the structure after the anodic oxidation treatment step in an acidic aqueous solution or an alkaline aqueous solution, filling the interior of the pores with the acidic aqueous solution or the alkaline aqueous solution, and then bringing the surface of the anodic oxide film on the opening side of the pores into contact with a pH (hydrogen ion index) buffer solution, or the like, whereby only the barrier layer can be selectively dissolved.

In the case of using an acidic aqueous solution, an aqueous solution of an inorganic acid such as sulfuric acid, phosphoric acid, nitric acid, hydrochloric acid, or the like, or a mixture of these is preferably used. The concentration of the acidic aqueous solution is preferably 1 to 10 mass%. The temperature of the acidic aqueous solution is preferably 15 to 80 ℃, more preferably 20 to 60 ℃, still more preferably 30 to 50 ℃.

On the other hand, in the case of using an alkaline aqueous solution, it is preferable to use an aqueous solution of at least one alkali selected from the group consisting of sodium hydroxide, potassium hydroxide and lithium hydroxide. The concentration of the alkaline aqueous solution is preferably 0.1 to 5 mass%. The temperature of the alkaline aqueous solution is preferably 10 to 60 ℃, more preferably 15 to 45 ℃, and even more preferably 20 to 35 ℃. In addition, the alkaline aqueous solution may contain zinc and other metals.

As the pH buffer, a buffer corresponding to the acidic aqueous solution or the alkaline aqueous solution can be suitably used.

The immersion time in the acidic aqueous solution or the alkaline aqueous solution is preferably 8 minutes to 120 minutes, more preferably 10 minutes to 90 minutes, and even more preferably 15 minutes to 60 minutes.

(Dry etching treatment)

For example, a gas species such as a Cl ₂/Ar mixed gas is preferably used for the dry etching treatment.

[ Plating Process ]

The plating step is as follows: after the barrier removal step, metal plating is performed in a supercritical state or subcritical state, and the inside of the plurality of through holes (pores) of the anodized film is filled with the metal M2. As described above, at the beginning of the plating step, a metal layer other than the valve metal is present at the bottom of the pores of the structure, and a metal layer other than the valve metal is formed in the bottom of the pores in a region of 80% or more of the area. In the plating step, the metal plating may be either electroplating or electroless plating, but electroplating is preferable because it can be performed in a short time.

The plating apparatus 28 shown in fig. 12 includes a plating tank 29, an oven 30 surrounding the plating tank 29, a counter electrode 31, a power supply unit 32, and a control unit 33. In the plating tank 29, the structure 17 is disposed to face the counter electrode 31. Plating bath 29 is filled with plating solution AQ, and structure 17 and counter electrode 31 are immersed therein. As described above, the structure 17 has the metal member and the anodic oxide film 14 having the plurality of through holes 12.

The power supply portion 32 is electrically connected to the structure 17 and the counter electrode 31, and applies current to the structure 17. When metal plating is performed, an electric current is applied to the metal layer or the metal member of the structure 17.

The control unit 33 is connected to the power supply unit 32, and controls the power supply unit 32. The control unit 33 controls the current value, time, and period of the current applied by the power supply unit 32. For example, a plurality of current patterns of applied currents are stored in the control unit 33, and a current is applied from the power supply unit 32 to the structure 17 in an arbitrary current pattern.

In addition, the power supply unit 32 may be provided with the function of the control unit 33, and in this case, the control unit 33 is not required. The current mode of the applied current is also referred to as a current control mode.

Oven 30 adjusts the temperature of plating solution AQ in plating bath 29. The temperature of the plating solution AQ in the plating tank 29 can be adjusted by the oven 30, and a known heater or the like can be used without any particular limitation. The temperature of plating solution AQ is maintained by oven 30 at a desired temperature, either supercritical or subcritical.

The plating device 28 includes a supply portion 34, a pump 35, and a valve 36, and a supply pipe 37 is provided in the lid 29a of the plating tank 29, and high-pressure carbon dioxide, for example, is supplied into the plating tank 29. The pressure adjusting portion 38 is connected to the plating tank 29 via a discharge pipe 39 provided in the lid 29a of the plating tank 29. The pressure in the plating tank 29 is maintained at a pressure required for supercritical or subcritical operation by the pressure adjusting section 38.

The supply unit 34 stores a substance that becomes supercritical or subcritical. In the case where the substance to be supercritical is carbon dioxide, the supply unit 34 is a carbon dioxide bottle.

The pump 35 pressurizes the substance to be supercritical or subcritical and supplies the substance to the plating tank 29, and a known pressurizing pump is used.

Valve 36 controls the supply of the substance to be supercritical or subcritical into plating tank 29.

As described above, the pressure adjusting portion 38 reduces or releases the pressure in the plating tank 29 while maintaining the pressure in the plating tank 29. The pressure adjusting portion 38 uses a valve, for example.

The supercritical medium is, for example, carbon dioxide. The critical point (point at which carbon dioxide becomes supercritical) is a temperature of 31.0 ℃ and a pressure of 7.38MPa, and carbon dioxide becomes supercritical at a temperature and a pressure equal to or higher than the critical point. Therefore, the temperature in the plating tank 29 is set to 31.0 ℃ or higher, and the pressure is set to 7.38MPa or higher. In this case, if the supercritical medium is stirred at the same time, plating can be effectively performed. Therefore, a stirrer (not shown) for stirring is preferably provided in the plating tank 29.

The sub-supercritical medium can be the same as the above-described supercritical medium.

In the plating tank 29 shown in fig. 12, the structure 17 is disposed so as to face the counter electrode 31. Then, the plating bath 29 is filled with the plating solution AQ.

The temperature of the plating solution AQ in the plating tank 29 is set to, for example, 40 ℃ by the oven 30. Next, for example, carbon dioxide is supplied from the supply unit 34 to the pump 35, pressurized by the pump 35 to pass through the valve 36, supplied into the plating tank 29 via the supply pipe 37, and pressurized so that the pressure in the plating tank 29 becomes, for example, 10MPa. In this case, the plating solution AQ is preferably stirred.

As described above, carbon dioxide is in a supercritical state in an environment of a temperature of 31.0 ℃ and a pressure of 7.38MPa, and thus the inside of the plating tank 29 is in a substantially supercritical state, and the plating solution AQ is in a substantially emulsion state. The plating treatment is performed with the plating solution AQ in the emulsion state, and the inside of the through-hole in the anodized film is filled with the metal M2, thereby forming the conductive via 16. In the plating step, metal plating is performed in a supercritical state using a supercritical medium. The pressure and temperature may be adjusted, for example, to bring carbon dioxide into a subcritical state, so that metal plating may be performed in a subcritical state using a subcritical medium.

< Supercritical Medium >

As the supercritical medium, for example, a forming gas such as oxygen, argon, krypton, xenon, ammonia, methane, ethane, methanol, ethanol, isopropanol, dimethyl ketone, sulfur hexafluoride, carbon monoxide, dinitrogen monoxide, a mixed gas of 95% nitrogen and 5% hydrogen, and a mixture of 2 or more thereof can be used in addition to carbon dioxide. Also, water can be used. Among them, carbon dioxide is preferable.

In addition, water becomes a supercritical medium in an environment where the temperature is 374.2 ℃ or higher and the pressure is 22.1MPa or higher. Methanol becomes a supercritical medium in an environment with a temperature of 239.4 ℃ or higher and a pressure of 8.1MPa or higher. Ethanol becomes a supercritical medium in an environment with a temperature of 243 ℃ or higher and a pressure of 6.4MPa or higher.

< Sub-supercritical Medium >

Here, the supercritical state refers to a state in which the temperature is equal to or higher than the temperature at the critical point (critical temperature) and the pressure is equal to or higher than the pressure at the critical point (critical pressure). The subcritical state is a state in which the temperature near the critical point is slightly lower than the critical temperature or a state in which the temperature is slightly lower than the critical pressure.

The subcritical medium may utilize the same medium as the supercritical medium. As described above, the subcritical medium is a state in which the temperature is slightly lower than that in the critical state or a state in which the pressure is slightly lower than that in the supercritical medium.

< Metal M2>

The metal M2 is preferably a material having a resistivity of 10 ³ Ω·cm or less, and specific examples thereof include gold (Au), silver (Ag), copper (Cu), aluminum (Al), magnesium (Mg), nickel (Ni), zinc (Zn), and the like.

Among them, cu, au, al, and Ni are preferable, cu and Au are more preferable, and Cu is further preferable from the viewpoint of conductivity.

< Filling method >

As a method of plating for filling the metal M2 into the through-hole, an electroplating method is used. In addition, in the electroless plating method, a long time is required to completely fill the holes consisting of the through holes having a high aspect ratio with the metal.

Here, in a conventionally known plating method used for coloring or the like, it is difficult to selectively deposit (grow) a metal in a hole with a high aspect ratio. The reason is considered that the plating layer does not grow even if the deposited metal is consumed in the hole and subjected to electrolysis for a predetermined time or longer.

Therefore, in the case of filling metal by the plating method, it is necessary to set a stop time at the time of pulse electrolysis or constant potential electrolysis. The suspension time is 10 seconds or longer, preferably 30 to 60 seconds.

In order to promote stirring of the electrolyte, it is also preferable to apply ultrasonic waves.

Further, the electrolysis voltage is usually 20V or less, preferably 10V or less, but it is preferable to measure the precipitation potential of the target metal in the electrolyte to be used in advance and perform constant potential electrolysis within +1v of the potential. In addition, when constant potential electrolysis is performed, it is desirable to use cyclic voltammetry at the same time, and potentiostat devices such as Solartron corporation, BAS inc., HOKUTO DENKO corp., IVIUM corporation, etc. can be used.

(Plating solution)

The plating solution contains metal ions, and a conventionally known plating solution corresponding to the filled metal is used. As the plating solution, copper sulfate is preferable as a main component of the solid component, and for example, a mixed aqueous solution of copper sulfate, sulfuric acid, and hydrochloric acid is used. Specifically, in the case of precipitating copper, an aqueous copper sulfate solution is generally used, but the concentration of copper sulfate is preferably 1 to 300g/L, more preferably 100 to 200g/L. Further, if hydrochloric acid is added to the plating solution, precipitation can be promoted. In this case, the hydrochloric acid concentration is preferably 10 to 20g/L.

The main component of the solid content is that the proportion of the solid content in the electrolyte is 20% by mass or more, and for example, copper sulfate is 20% by mass or more in the solid content in the electrolyte.

In the case of depositing gold, it is preferable to use a sulfuric acid solution of tetrachlorogold and perform plating by ac electrolysis.

The plating solution preferably contains a surfactant.

As the surfactant, a known surfactant can be used. Sodium lauryl sulfate, which is known as a surfactant added to conventional plating solutions, can also be used as it is. The hydrophilic portion may be any of an ionic (cationic, anionic, or amphoteric) active agent and a nonionic (nonionic) active agent, but a cationic linear active agent is preferable from the viewpoint of avoiding the generation of bubbles on the surface of the plating object. The concentration of the surfactant in the plating solution composition is preferably 1 mass% or less.

< Reaming treatment >

The reaming process is as follows: the anodic oxide film is dissolved by immersing the aluminum member in an acidic aqueous solution or an alkaline aqueous solution, and the diameter of the through hole 12 is enlarged.

This facilitates control of the arrangement regularity and diameter variation of the through holes 12. Further, by dissolving the barrier coating at the bottom portions of the plurality of through holes 12 of the anodic oxide film, the surface area as an electrode can be remarkably increased by selectively electrodepositing the barrier coating inside the through holes 12 and enlarging the diameter.

In the case of using an acidic aqueous solution for the reaming treatment, an aqueous solution of an inorganic acid such as sulfuric acid, phosphoric acid, nitric acid, hydrochloric acid, or the like, or a mixture of these is preferably used. The concentration of the acidic aqueous solution is preferably 1 to 10 mass%. The temperature of the acidic aqueous solution is preferably 25 to 40 ℃.

When an alkaline aqueous solution is used for the reaming treatment, an aqueous solution of at least one alkali selected from the group consisting of sodium hydroxide, potassium hydroxide and lithium hydroxide is preferably used. The concentration of the alkaline aqueous solution is preferably 0.1 to 5 mass%. The temperature of the alkaline aqueous solution is preferably 20 to 35 ℃.

The immersion time for the acidic aqueous solution or the alkaline aqueous solution is preferably 8 to 60 minutes, more preferably 10 to 50 minutes, and even more preferably 15 to 30 minutes.

[ Substrate removal Process ]

The substrate removal step is a step of removing the aluminum member after the plating step. The method for removing the aluminum member is not particularly limited, and for example, a method for removing by dissolution is preferably used.

< Dissolution of aluminum Member >

In the dissolution of the aluminum member, a treatment liquid which is less likely to dissolve the anodic oxide film and is more likely to dissolve aluminum is preferably used.

The dissolution rate of the treatment liquid in aluminum is preferably 1 μm/min or more, more preferably 3 μm/min or more, and still more preferably 5 μm/min or more. Similarly, the dissolution rate of the anodic oxide film is preferably 0.1 nm/min or less, more preferably 0.05 nm/min or less, and still more preferably 0.01 nm/min or less.

Specifically, a treatment liquid containing at least 1 metal compound having a lower ionization tendency than aluminum and having a pH of 4 or less or 8 or more is preferable, and the pH is more preferably 3 or less or 9 or more, and still more preferably 2 or less or 10 or more.

As the treatment liquid for dissolving aluminum, a treatment liquid obtained by blending, for example, compounds of manganese, zinc, chromium, iron, cadmium, cobalt, nickel, tin, lead, antimony, bismuth, copper, mercury, silver, palladium, platinum, gold (for example, chloroplatinic acid), fluorides of these, chlorides of these, or the like with an acid or alkali aqueous solution as a base is preferable.

Among these, an acidic aqueous solution base is preferable, and mixed chlorides are preferable.

In particular, from the viewpoint of the treatment range, a treatment solution in which mercury chloride is mixed with an aqueous hydrochloric acid solution (hydrochloric acid/mercury chloride) and a treatment solution in which copper chloride is mixed with an aqueous hydrochloric acid solution (hydrochloric acid/copper chloride) are preferable.

The composition of the treatment liquid for dissolving aluminum is not particularly limited, and for example, a bromine/methanol mixture, a bromine/ethanol mixture, aqua regia, and the like can be used.

The concentration of the acid or alkali in the treatment solution for dissolving aluminum is preferably 0.01 to 10mol/L, more preferably 0.05 to 5mol/L.

The treatment temperature of the treatment solution in which the dissolved aluminum is used is preferably-10 to 80 ℃, and more preferably 0 to 60 ℃.

The dissolution of the aluminum member is performed by bringing the aluminum member after the plating step into contact with the treatment liquid. The contact method is not particularly limited, and examples thereof include an immersion method and a spray method. Among them, the impregnation method is preferable. The contact time in this case is preferably 10 seconds to 5 hours, more preferably 1 minute to 3 hours.

[ Metal protrusion Process ]

For the reason of improving the metal bondability of the produced metal-filled microstructure, at least 1 of the front metal projecting step and the rear metal projecting step may be provided.

The surface metal protrusion step is as follows: after the plating step and before the substrate removal step, a part of the surface of the anodized film on the side where the aluminum member is not provided is removed in the thickness direction so that the metal M2 filled in the plating step protrudes from the surface of the anodized film.

The back metal projection step is as follows: after the substrate removal step, a part of the surface of the anodized film on the side where the aluminum member is provided is removed in the thickness direction so that the metal M2 filled in the plating step protrudes from the surface of the anodized film.

The removal of a part of the anodic oxide film in the metal protrusion step can be performed, for example, as follows: the metal M1 and the metal M2 (particularly the metal M2) are not dissolved, but the anodic oxide film, that is, the anodic oxide film having the through holes filled with the metal is brought into contact with an acidic aqueous solution or an alkaline aqueous solution in which alumina is dissolved. The contact method is not particularly limited, and examples thereof include an immersion method and a spray method. Among them, the impregnation method is preferable.

In the case of using an acidic aqueous solution, an aqueous solution of an inorganic acid such as sulfuric acid, phosphoric acid, nitric acid, hydrochloric acid, or a mixture of these is preferably used. Among them, an aqueous solution containing no chromic acid is preferable from the viewpoint of excellent safety. The concentration of the acidic aqueous solution is preferably 1 to 10 mass%. The temperature of the acidic aqueous solution is preferably 25 to 60 ℃.

In the case of using an alkaline aqueous solution, it is preferable to use an aqueous solution of at least one alkali selected from the group consisting of sodium hydroxide, potassium hydroxide and lithium hydroxide. The concentration of the alkaline aqueous solution is preferably 0.1 to 5 mass%. The temperature of the alkaline aqueous solution is preferably 20 to 35 ℃.

The immersion time for the acidic aqueous solution or the alkaline aqueous solution is preferably 8 to 120 minutes, more preferably 10 to 90 minutes, and even more preferably 15 to 60 minutes. Here, the term "impregnation time" refers to the total of the impregnation times when the impregnation treatment is repeated for a short period of time. In addition, a cleaning process may be performed between the dipping processes.

When the produced metal-filled microstructure is used as an anisotropic conductive member, at least one of the front metal projection step and the back metal projection step is preferably a step of projecting the metal M2 from the surface of the anodic oxide film by 10 to 1000nm, and more preferably a step of projecting the metal M2 by 50 to 500nm, from the viewpoint of improving the pressure-bonding property with an adherend such as a wiring board.

In addition, when the metal-filled microstructure produced by the method of pressure bonding or the like is connected (bonded) to the electrode, the aspect ratio of the protruding portion (height of the protruding portion/diameter of the protruding portion) formed by at least 1 of the front surface metal protruding step and the back surface metal protruding step is preferably 0.01 or more and less than 20, and preferably 6 to 20, from the reason that the insulation properties in the plane direction when the protruding portion is flattened can be sufficiently ensured.

The conductive path formed of a metal formed by the plating step, the substrate removal step, and any metal protruding step is preferably columnar. The diameter of the via is substantially the same as the diameter of the metal-filled through hole. The average diameter of the conductive path is preferably 1 μm or less, more preferably 5 to 500nm, still more preferably 20 to 400nm, still more preferably 40 to 200nm, and most preferably 50 to 100nm.

The conductive paths are conductive paths which exist in a state of being insulated from each other by an anodic oxide film of an aluminum member, and the density thereof is preferably 2 ten thousand/mm ² or more, more preferably 200 ten thousand/mm ² or more, still more preferably 1000 ten thousand/mm ² or more, particularly preferably 5000 ten thousand/mm ² or more, and most preferably 1 hundred million/mm ² or more.

The center-to-center distance between adjacent conductive paths is preferably 20nm to 500nm, more preferably 40nm to 200nm, and even more preferably 50nm to 140nm.

[ Resin layer Forming Process ]

For the reason of improving the conveyability of the metal-filled microstructure thus produced, the resin layer forming step may be provided as described above.

Here, the resin layer forming step is a step of: a resin layer is provided on the surface of the anodized film on the side where the aluminum member is not provided, after the plating step (after the surface metal protrusion step in the case of having the surface metal protrusion step) and before the substrate removal step.

Specific examples of the resin material constituting the resin layer include ethylene copolymer, polyamide resin, polyester resin, polyurethane resin, polyolefin resin, acrylic resin, cellulose resin, and the like, but from the viewpoint of transportation and ease of use as an anisotropic conductive member, the resin layer is preferably a film with an adhesive layer that is peelable, and more preferably a film with an adhesive layer that is peelable due to reduction in adhesion by heat treatment or ultraviolet exposure treatment.

The film with an adhesive layer is not particularly limited, and examples thereof include a heat-peelable resin layer and an ultraviolet (ultrayiolet: UV) peelable resin layer.

Here, the heat-peelable resin layer has adhesive strength at normal temperature and can be easily peeled off by heating alone, so that mainly foamable microcapsules and the like are used.

Specific examples of the adhesive constituting the adhesive layer include rubber-based adhesives, acrylic adhesives, vinyl alkyl ether-based adhesives, silicone-based adhesives, polyester-based adhesives, polyamide-based adhesives, urethane-based adhesives, and styrene-diene block copolymer-based adhesives.

The UV-releasable resin layer has a UV-curable adhesive layer, and is releasable by curing to lose adhesive force.

Examples of the UV curable adhesive layer include a polymer in which a carbon-carbon double bond is introduced into a side chain or a main chain of a polymer or a terminal of the main chain in a base polymer. As the base polymer having a carbon-carbon double bond, an acrylic polymer is preferably used as a basic skeleton.

The acrylic polymer may contain a polyfunctional monomer or the like as a comonomer component, if necessary, for crosslinking.

The base polymer having carbon-carbon double bonds can be used alone, but UV curable monomers or oligomers can also be blended.

For curing the UV-curable adhesive layer by UV irradiation, it is preferable to use a photopolymerization initiator simultaneously. Examples of the photopolymerization initiator include benzoin ether compounds; ketal compounds; aromatic sulfonyl chloride compounds; photosensitive oximes; benzophenone compounds; thioxanthones; camphorquinone; halogenated ketones; acyl phosphine oxides; acyl phosphonates and the like.

Examples of the commercial products of the heat-peelable resin layer include INTELLIMER (registered trademark) tapes (manufactured by NITTA Corporation) such as WS5130C02 and WS5130C 10; somatac (registered trademark) TE series (manufactured by SOMAR, inc. );No.3198、No.3198LS、No.3198M、No.3198MS、No.3198H、No.3195、No.3196、No.3195M、No.3195MS、No.3195H、No.3195HS、No.3195V、No.3195VS、No.319Y-4L、No.319Y-4LS、No.319Y-4M、No.319Y-4MS、No.319Y-4H、No.319Y-4HS、No.319Y-4LSC、No.31935MS、No.31935HS、No.3193M、No.3193MS et al RIVA ALPHA (registered trademark) series (manufactured by NITTO DENKO CORPORATION).

As a commercially available product of the UV-releasable resin layer, for example, ELEPH HOLDER (registered trademark) (manufactured by NITTO DENKO CORPORATION. Co., ltd.) such as ELP DU-300, ELP DU-2385KS, ELP DU-2187G, ELP NBD-3190K, ELP UE-2091J, etc. can be used; adwill D-210, adwill D-203, adwill D-202, adwill D-175, adwill D-675 (all manufactured by Lintec corporation); SUMILITE (registered trademark) FLS, N8000 series (Sumitomo Bakelite co., ltd.); UC353EP-110 (FURUKAWA ELECTRIC CO., LTD.); an equal cutting band, ELP RF-7232DB, ELP UB-5133D (all manufactured by NITTO DENKO CORPORATION); SP-575B-150, SP-541B-205, SP-537T-160, SP-537T-230 (both FURUKAWA ELECTRIC CO., LTD.); and (5) grinding the belt at the back.

The method of attaching the film with an adhesive layer is not particularly limited, and the film can be attached using a conventionally known surface protective tape attaching device and laminator.

[ Winding Process ]

For the reason of further improving the conveyability of the produced metal-filled microstructure, a winding step of winding the metal-filled microstructure into a roll with the resin layer may be provided after the arbitrary resin layer forming step.

The winding method in the winding step is not particularly limited, and examples thereof include a method of winding a core having a predetermined diameter and a predetermined width.

The average thickness of the metal-filled microstructure other than the resin layer (not shown) is preferably 30 μm or less, more preferably 5 to 20 μm, from the viewpoint of ease of winding in the winding step. In addition, regarding the average thickness, it can be calculated as follows: the metal-filled microstructure other than the resin layer was subjected to cutting processing in the thickness direction by FIB, and a surface photograph (magnification 50000 times) was taken of a section thereof by FE-SEM as an average value of 10 points or the like.

[ Other treatment Process ]

The production method of the present invention may include, in addition to the above-described steps, a polishing step, a surface smoothing step, a protective film formation treatment, and a water washing treatment described in paragraphs [0049] to [0057] of International publication No. 2015/029881.

In addition, from the viewpoints of manufacturability and use of the metal-filled microstructure as an anisotropic conductive member, various processes and forms as shown below can be applied.

< Example of Process Using temporary Adhesives >

The method may comprise the steps of: after the metal-filled microstructure is obtained in the substrate removal step, the metal-filled microstructure is fixed to a silicon wafer using a temporary adhesive (Temporary Bonding Materials), and thinned by polishing.

Then, after the thin layer process and after the surface is sufficiently cleaned, the above-described surface metal protrusion process can be performed.

Then, after the metal-protruded surface is fixed to the silicon wafer by applying a temporary adhesive having a stronger adhesive force than the previous temporary adhesive, the silicon wafer bonded by the previous temporary adhesive can be peeled off, and the back metal-protruded step can be performed on the peeled-off metal-filled microstructure-side surface.

< Example of Process Using Paraffin >

The method may comprise the steps of: after the metal-filled microstructure is obtained in the substrate removal step, the metal-filled microstructure is fixed to a silicon wafer using paraffin, and thinned by polishing.

Then, after the metal-protruded surface is fixed to the silicon wafer by applying a temporary adhesive, the silicon wafer can be peeled by dissolving the paraffin by heating, and the back metal-protruded step is performed on the peeled metal-filled microstructure-side surface.

Although solid paraffin may be used, if liquid paraffin such as SKYCOAT (NIKKA SEIKO co., ltd. Manufactured) is used, the uniformity of the coating thickness can be improved.

< Example of Process for substrate removal treatment after that >

The method may comprise the steps of: after the plating step and before the substrate removal step, the aluminum member is fixed to a rigid substrate (for example, a silicon wafer, a glass substrate, or the like) using a temporary adhesive, paraffin, or a functional adsorption film, and then the surface of the anodized film on the side where the aluminum member is not provided is polished to make the aluminum member thinner.

Next, after a resin material (for example, epoxy resin, polyimide resin, or the like) as an insulating material is applied to the surface where the metal is protruded, a rigid substrate can be attached to the surface by the same method as described above. The attachment based on the resin material can be performed as follows: the method comprises selecting a resin material having an adhesive force greater than that of a temporary adhesive or the like, peeling the rigid substrate to be attached first after the adhesion by the resin material, and sequentially performing the substrate removing step, the polishing step, and the back metal projecting step.

As the functional adsorption film, Q-chuck (registered trademark) (MARUISHI SANGYO co., ltd., manufactured) and the like can be used.

The metal-filled microstructure is preferably provided as a product in a state of being attached to a rigid substrate (e.g., a silicon wafer, a glass substrate, or the like) through a releasable layer.

In this supply method, when a metal-filled microstructure is used as a joining member, the surface of the metal-filled microstructure is temporarily adhered to the device surface, and after the rigid substrate is peeled off, the device to be joined is set in an appropriate position and subjected to thermocompression bonding, whereby the upper and lower devices can be joined by the metal-filled microstructure.

The releasable layer may be a thermal release layer, or a combination with a glass substrate may be a photo release layer.

Further, the above-described steps may be performed on a single sheet, or the aluminum roll may be continuously processed as a web (web).

In the case of continuous treatment, it is preferable to provide an appropriate cleaning step and drying step between the steps.

The metal-filled microstructure obtained by filling the inside of the through-holes derived from the through-holes provided in the insulating base material composed of the anodized film of the aluminum member with the metal by the manufacturing method having the above-described respective processing steps.

Specifically, the above-described manufacturing method can provide an anisotropic conductive member described in, for example, japanese patent application laid-open No. 2008-270158, that is, an anisotropic conductive member provided in the following state: in an insulating base material (an anodic oxide film of an aluminum member having a through hole), a plurality of conductive paths made of a conductive member (metal) are formed so as to penetrate the insulating base material in a thickness direction while being insulated from each other, one end of each of the conductive paths is exposed on one surface of the insulating base material, and the other end of each of the conductive paths is exposed on the other surface of the insulating base material.

An example of the metal-filled microstructure 20 manufactured by the above-described manufacturing method will be described below. Fig. 13 is a plan view showing an example of a metal-filled microstructure according to an embodiment of the invention, and fig. 14 is a schematic cross-sectional view showing an example of a metal-filled microstructure according to an embodiment of the invention. Fig. 14 is a cross-sectional view taken along section line IB-IB of fig. 13. Fig. 15 is a schematic cross-sectional view showing an example of a structure of an anisotropic conductive material using a metal-filled microstructure according to an embodiment of the present invention.

As shown in fig. 13 and 14, the metal-filled microstructure 20 manufactured as described above is a member including, for example, an insulating base material 40 and a plurality of conductive vias 16, the insulating base material 40 being composed of an anodized film 14 of aluminum (see fig. 5), the plurality of vias 16 penetrating in a thickness direction Dt (see fig. 14) of the insulating base material 40 and being provided in an electrically insulated state from each other. The metal-filled microstructure 20 further includes a resin layer 44 provided on the front surface 40a and the back surface 40b of the insulating base material 40.

Here, the "state of being electrically insulated from each other" means a state in which the conduction between the conduction paths existing inside the insulating base material is sufficiently low inside the insulating base material.

The metal-filled microstructure 20 is the following: the conductive vias 16 are electrically insulated from each other, have sufficiently low conductivity in the direction x orthogonal to the thickness direction Dt (see fig. 14) of the insulating base material 40, and have conductivity in the thickness direction Dt (see fig. 14). Thus, the metal-filled microstructure 20 is a member exhibiting anisotropic conductivity. For example, the metal-filled microstructure 20 is arranged so that the thickness direction Dt (see fig. 14) coincides with the stacking direction Ds of the stacked device 60.

As shown in fig. 13 and 14, the conductive paths 16 are provided so as to penetrate the insulating base material 40 in the thickness direction Dt while being electrically insulated from each other.

As shown in fig. 14, the conductive path 16 may have a protruding portion 16a and a protruding portion 16b protruding from the front surface 40a and the back surface 40b of the insulating base material 40. The metal-filled microstructure 20 may further include a resin layer 44 provided on the front surface 40a and the back surface 40b of the insulating base material 40. The resin layer 44 has adhesion and also imparts bondability. The length of the protruding portion 16a and the protruding portion 16b is preferably 6nm or more, more preferably 30nm to 500nm.

In fig. 15 and 14, the resin layer 44 is provided on the front surface 40a and the back surface 40b of the insulating base material 40, but the present invention is not limited to this, and the resin layer 44 may be provided on at least one surface of the insulating base material 40.

Similarly, the conductive path 16 in fig. 15 and 14 has the protruding portions 16a and 16b at both ends, but the present invention is not limited thereto, and the insulating base material 40 may have protruding portions on at least the surface on the side having the resin layer 44.

The thickness h of the metal-filled microstructure 20 shown in fig. 14 is, for example, 30 μm or less. The TTV (Total Thickness Variation: total thickness variation) of the metal-filled microstructure 20 is preferably 10 μm or less.

Here, the thickness h of the metal-filled microstructure 20 is an average value of 10 points measured for a region corresponding to the thickness h by observing the metal-filled microstructure 20 with an electrolytic emission scanning electron microscope at a magnification of 20 ten thousand times to obtain a wheel Guo Xingzhuang of the metal-filled microstructure 20.

Also, TTV (Total Thickness Variation) of the metal-filled microstructure 20 is the following value: the metal-filled microstructure 20 is cut together with the support 46 by dicing, and the cross-sectional shape of the metal-filled microstructure 20 is observed to obtain a value.

For transportation, conveyance, transportation, storage, and the like, as shown in fig. 15, the metal-filled microstructure 20 is provided on a support 46. A release layer 47 is provided between the support 46 and the metal-filled microstructure 20. The support 46 and the metal-filled microstructure 20 are bonded to each other by a release layer 47 so as to be separable. As described above, the material of the metal-filled microstructure 20 provided on the support 46 via the release layer 47 is referred to as an anisotropic conductive material 50.

The support 46 supports the metal-filled microstructure 20 and is made of, for example, a silicon substrate. As the support 46, for example, a ceramic substrate such as SiC, siN, gaN or alumina (Al ₂O₃), a glass substrate, a fiber-reinforced plastic substrate, or a metal substrate can be used in addition to a silicon substrate. The fiber reinforced plastic substrate also includes an FR-4 (FLAME RETARDANT TYPE (flame retardant) 4) substrate as a printed circuit board, and the like.

Further, as the support 46, a support having flexibility and transparency can be used. Examples of the flexible and transparent support 46 include plastic films such as PET (polyethylene terephthalate), polycycloolefin, polycarbonate, acrylic resin, PEN (polyethylene naphthalate), PE (polyethylene), PP (polypropylene), polystyrene, polyvinyl chloride, polyvinylidene chloride, and TAC (cellulose triacetate).

Here, transparent means that the transmittance of light of a wavelength used for alignment is 80% or more. Therefore, the transmittance may be low in the entire visible light range of 400 to 800nm, but the transmittance is preferably 80% or more in the entire visible light range of 400 to 800 nm. The transmittance was measured by a spectrophotometer.

The release layer 47 is preferably a layer obtained by laminating a support layer 48 and a release agent 49. The release agent 49 contacts the metal-filled microstructure 20, and the support 46 and the metal-filled microstructure 20 are separated from each other with the release layer 47 as a starting point. In the anisotropic conductive material 50, for example, by heating to a predetermined temperature, the adhesion force of the peeling agent 49 is weakened, and the support 46 is removed from the metal-filled microstructure 20.

As the release agent 49, for example, REVALPHA (registered trademark) manufactured by Nitto Denko Corporation, SOMATAC (registered trademark) manufactured by SOMAR Corporation, and the like can be used.

A protective layer (not shown) may be provided on the resin layer 44. The protective layer is preferably an easily releasable adhesive tape because it is used for protecting the surface of the structure from damage or the like. As the protective layer, for example, a film with an adhesive layer can be used.

As the film with an adhesive layer, for example, commercially available products sold under the following serial names can be used: SUNYTECT (registered trademark) having an adhesive layer formed on the surface of a polyethylene resin film (Sun a. Kaken co., LTD., manufactured), E-MASK (registered trademark) having an adhesive layer formed on the surface of a polyethylene terephthalate resin film (manufactured) Nitto Denko Corporation, MASTACK (registered trademark) having an adhesive layer formed on the surface of a polyethylene terephthalate resin film (FUJIMORI KOGYO co., LTD), and the like.

The method of attaching the film with the adhesive layer is not particularly limited, and the film can be attached using a conventionally known surface protective tape attaching device and laminator.

Hereinafter, the structure of the metal-filled microstructure 20 will be described in more detail.

[ Insulating substrate ]

The physical properties and composition of the insulating base material are as described above.

The thickness ht of the insulating base material 40 is preferably in the range of 1 to 1000. Mu.m, more preferably in the range of 5 to 500. Mu.m, and even more preferably in the range of 10 to 300. Mu.m. When the thickness of the insulating base material is within this range, the operability of the insulating base material becomes good.

The thickness ht of the insulating base material 40 is obtained by cutting the insulating base material 40 in the thickness direction Dt with a Focused Ion Beam (FIB), observing the cross section of the insulating base material 40 with an electron emission scanning electron microscope at a magnification of 20 ten thousand times to obtain a wheel Guo Xingzhuang of the insulating base material 40, and measuring an average value of 10 points in a region corresponding to the thickness ht.

The distance between the through holes in the insulating base material is preferably 5nm to 800nm, more preferably 10nm to 200nm, and even more preferably 50nm to 140nm. When the interval between the through holes in the insulating base material is within this range, the insulating base material sufficiently functions as an insulating partition wall. The interval of the through holes is the same as the interval of the conduction paths.

Here, the interval of the through holes, that is, the interval of the via holes refers to the width w (see fig. 14) between adjacent via holes, and refers to the average value of the width between adjacent via holes measured at 10 points by observing the cross section of the anisotropic conductive member at 20 ten thousand times by an electric field emission scanning electron microscope.

< Average diameter of pores >

The average diameter of the micropores, that is, the average diameter d (see FIG. 14) of the through holes 12 is preferably 1 μm or less, more preferably 5 to 500nm, further preferably 20 to 400nm, still more preferably 40 to 200nm, and most preferably 50 to 100nm. When the average diameter d of the through hole 12 is 1 μm or less, a sufficient response can be obtained when an electric signal flows through the obtained conductive path 16, and therefore, the connector can be more preferably used as a connector for inspection of electronic parts.

The average diameter d of the through holes 12 was measured by taking a photographic image of the surface of the anodic oxide film 14 from directly above at a magnification of 100 to 10000 times using a scanning electron microscope, extracting at least 20 through holes connected in a ring shape around the photographic image, and calculating the average value of the opening diameters as the average diameter of the through holes.

The magnification can be appropriately selected in the above range to obtain a photographic image in which 20 or more through holes can be extracted. The maximum value of the distance between the ends of the through-hole portions was measured with respect to the opening diameter. That is, since the shape of the opening of the through-hole is not limited to a substantially circular shape, when the shape of the opening is non-circular, the maximum value of the distance between the ends of the through-hole is defined as the opening diameter. Therefore, for example, in the case of a through hole having a shape in which 2 or more through holes are integrated, the through hole is regarded as 1 through hole, and the maximum value of the distance between the ends of the through hole portion is set as the opening diameter.

[ Conduction path ]

The conductive path is made of metal. Specific examples of the metal include gold (Au), silver (Ag), copper (Cu), aluminum (Al), magnesium (Mg), and nickel (Ni). Copper, gold, aluminum, and nickel are preferable from the viewpoint of conductivity, and copper and gold are more preferable.

< Protruding portion >

When the anisotropic conductive member is electrically or physically bonded to the electrode by pressure bonding or the like, the aspect ratio of the protruding portion of the conductive path (height of the protruding portion/diameter of the protruding portion) is preferably 0.5 or more and less than 50, more preferably 0.8 to 20, and even more preferably 1 to 10, from the viewpoint that the insulation properties in the plane direction when the protruding portion is crushed can be sufficiently ensured.

Further, from the viewpoint of following the surface shape of the semiconductor component to be connected, the height of the protruding portion of the conductive path is preferably 20nm or more, more preferably 100nm to 500nm, as described above.

The height of the protruding portion of the conductive path is an average value of the height of the protruding portion of the conductive path measured at 10 points by observing the cross section of the metal-filled microstructure with a 2-ten thousand times magnification by an electron emission scanning electron microscope.

The diameter of the protruding portion of the conductive path is an average value of the diameters of the protruding portion of the conductive path measured at 10 points by observing the cross section of the metal-filled microstructure with an electron emission scanning electron microscope.

As described above, the conductive paths 16 are electrically insulated from each other by the insulating base material 40, but the density thereof is preferably 2 ten thousand/mm ² or more, more preferably 200 ten thousand/mm ² or more, still more preferably 1000 ten thousand/mm ² or more, particularly preferably 5000 ten thousand/mm ² or more, and most preferably 1 hundred million/mm ² or more.

The distance p (see FIG. 13) between centers of adjacent passages 16 is preferably 20nm to 500nm, more preferably 40nm to 200nm, and even more preferably 50nm to 140nm.

[ Resin layer ]

As described above, the resin layer is provided on the front and rear surfaces of the insulating base material, and the protruding portion of the conductive path is embedded as described above. That is, the resin layer covers the end of the conductive path protruding from the insulating base material and protects the protruding portion.

The resin layer is formed by the resin layer forming step. The resin layer preferably exhibits fluidity in a temperature range of 50 to 200 ℃ and cures at a temperature of 200 ℃ or higher, for example.

The resin layer is formed by the resin layer forming step, but the composition of the resin agent shown below may be used. Hereinafter, the composition of the resin layer will be described. The resin layer contains a polymer material. The resin layer may contain an antioxidant material.

< Polymer Material >

The polymer material contained in the resin layer is not particularly limited, and is preferably a thermosetting resin from the viewpoint of being able to efficiently fill in the gap between the semiconductor chip or the semiconductor wafer and the anisotropic conductive member and further improving the adhesion with the semiconductor chip or the semiconductor wafer.

Specific examples of the thermosetting resin include epoxy resins, phenolic resins, polyimide resins, polyester resins, polyurethane resins, bismaleimide resins, melamine resins, and isocyanate resins.

Among them, polyimide resin and/or epoxy resin are preferably used for the reason of further improving insulation reliability and excellent chemical resistance.

< Antioxidant Material >

As the antioxidant material contained in the resin layer, specifically, examples thereof include 1,2,3, 4-tetrazole, 5-amino-1, 2,3, 4-tetrazole, 5-methyl-1, 2,3, 4-tetrazole, 1H-tetrazole-5-acetic acid, 1H-tetrazole-5-succinic acid, 1,2, 3-triazole, 4-amino-1, 2, 3-triazole, 4, 5-diamino-1, 2, 3-triazole, 4-carboxy-1H-1, 2, 3-triazole, 4, 5-dicarboxy-1H-1, 2, 3-triazole, 1H-1,2, 3-triazole-4-acetic acid, 4-carboxy-5-carboxymethyl-1H-1, 2, 3-triazole, 1,2, 4-triazole 3-amino-1, 2, 4-triazole, 3, 5-diamino-1, 2, 4-triazole, 3-carboxy-1, 2, 4-triazole, 3, 5-dicarboxy-1, 2, 4-triazole, 1,2, 4-triazole-3-acetic acid, 1H-benzotriazole-5-carboxylic acid, benzofuran, 2,1, 3-benzothiazole, o-phenylenediamine, m-phenylenediamine, catechol, o-aminophenol, 2-mercaptobenzothiazole, 2-mercaptobenzimidazole, 2-mercaptobenzoxazole, melamine, and derivatives thereof.

Among them, benzotriazole and its derivatives are preferable.

Examples of the benzotriazole derivatives include substituted benzotriazoles having a benzene ring of the benzotriazole with a hydroxyl group, an alkoxy group (for example, methoxy group, ethoxy group, etc.), an amino group, a nitro group, an alkyl group (for example, methyl group, ethyl group, butyl group, etc.), a halogen atom (for example, fluorine, chlorine, bromine, iodine, etc.), etc. Examples of the compound include naphthalene triazole, naphthalene bistriazole, substituted naphthalene triazole substituted in the same manner, and substituted naphthalene bistriazole.

Further, examples of the antioxidant material contained in the resin layer include higher fatty acids, copper higher fatty acids, phenol compounds, alkanolamines, hydroquinones, copper chelators, organic amines, and organic ammonium salts, which are general antioxidants.

The content of the antioxidant material contained in the resin layer is not particularly limited, but is preferably 0.0001 mass% or more, more preferably 0.001 mass% or more, based on the total mass of the resin layer, from the viewpoint of the anticorrosive effect. Further, the amount of the additive is preferably 5.0 mass% or less, more preferably 2.5 mass% or less, from the viewpoint of obtaining an appropriate electrical resistance in the main bonding process.

< Migration preventing Material >

The resin layer preferably contains a migration preventing material for the reason that the insulating reliability is further improved by trapping metal ions, halogen ions, and metal ions originating from semiconductor chips and semiconductor wafers that can be contained in the resin layer.

As the migration preventing material, for example, an ion exchanger, specifically, a mixture of a cation exchanger and an anion exchanger or only a cation exchanger can be used.

Here, the cation exchanger and the anion exchanger can be appropriately selected from, for example, an inorganic ion exchanger and an organic ion exchanger, which will be described later.

(Inorganic ion exchanger)

Examples of the inorganic ion exchanger include hydroxides of metals typified by zirconium hydroxide.

As the type of metal, for example, iron, aluminum, tin, titanium, antimony, magnesium, beryllium, indium, chromium, bismuth, and the like are known in addition to zirconium.

Wherein, the zirconium metal has the exchange capacity of the cation Cu ²⁺、Al³⁺. Furthermore, ferrous metals also have the exchange capacity of Ag ⁺、Cu²⁺. Similarly, tin-based, titanium-based, and antimony-based metals are cation exchangers.

Bismuth-based metals, on the other hand, have the exchange capacity of the anion Cl ^-.

The zirconium-based metal exhibits anion exchange ability according to the production conditions. Aluminum and tin metals are the same.

As other inorganic ion exchangers, there are known compositions such as acidic salts of polyvalent metals typified by zirconium phosphate, heteropolyacid salts typified by ammonium molybdenum phosphate, and insoluble ferrocyanide.

Some of these inorganic ion exchangers are commercially available, and various grades of the trade name "IXE" are known, for example, from TOAGOSEI co.

In addition, besides the synthesized product, an inorganic ion exchanger powder such as zeolite or montmorillonite which is a natural product can be used.

(Organic ion exchanger)

The organic ion exchanger may be a crosslinked polystyrene having sulfonic acid groups as a cation exchanger, or may be a crosslinked polystyrene having carboxylic acid groups, phosphonic acid groups, or phosphinic acid groups.

Further, as the anion exchanger, crosslinked polystyrene having quaternary ammonium groups, quaternary phosphonium groups or tertiary sulfonium groups can be mentioned.

These inorganic ion exchangers and organic ion exchangers may be appropriately selected in consideration of the type of cations and anions to be trapped and the exchange capacity for the ions. Of course, an inorganic ion exchanger and an organic ion exchanger may be mixed and used.

The process for producing an electronic component includes a heating process, and therefore, an inorganic ion exchanger is preferable.

Further, for example, from the viewpoint of mechanical strength, the mixing ratio of the migration preventing material and the polymer material is preferably 10 mass% or less, more preferably 5 mass% or less, and still more preferably 2.5 mass% or less. In addition, from the viewpoint of suppressing migration when bonding a semiconductor chip or a semiconductor wafer and an anisotropic conductive member, it is preferable that the migration preventing material is 0.01 mass% or more.

< Inorganic filler >

The resin layer preferably contains an inorganic filler.

The inorganic filler is not particularly limited and may be appropriately selected from known inorganic fillers, and examples thereof include kaolin, barium sulfate, barium titanate, silicon oxide powder, fine powder silicon oxide, fumed silica, amorphous silica, crystalline silica, fused silica, spherical silica, talc, clay, magnesium carbonate, calcium carbonate, alumina, aluminum hydroxide, mica, aluminum nitride, zirconium oxide, yttrium oxide, silicon carbide, and silicon nitride.

For the reason of preventing the inorganic filler from entering between the conduction paths and further improving the conduction reliability, it is preferable that the average particle diameter of the inorganic filler is larger than the interval between the conduction paths.

The average particle diameter of the inorganic filler is preferably 30nm to 10. Mu.m, more preferably 80nm to 1. Mu.m.

Here, regarding the average particle diameter, the primary particle diameter measured by a laser diffraction scattering particle diameter measuring device (NIKKISO co., ltd. Microtrac MT 3300) is set as the average particle diameter.

< Curing agent >

The resin layer may contain a curing agent.

In the case of containing a curing agent, it is more preferable to contain a curing agent that is liquid at ordinary temperature without using a curing agent that is solid at ordinary temperature, from the viewpoint of suppressing bonding failure with the surface shape of the semiconductor chip or semiconductor wafer to be connected.

Herein, "solid at normal temperature" means a substance that is solid at 25 ℃, for example, a substance having a melting point higher than 25 ℃.

Specific examples of the curing agent include aromatic amines such as diaminodiphenylmethane and diaminodiphenyl sulfone, imidazole derivatives such as aliphatic amines and 4-methylimidazole, carboxylic anhydrides such as dicyandiamide, tetramethylguanidine, thiourea addition amines and methyl hexahydrophthalic anhydride, carboxylic hydrazides, carboxylic acid amides, polyphenol compounds, novolak resins, polythiols and the like, and curing agents which are liquid at 25 ℃ can be appropriately selected from these curing agents. In addition, 1 kind of curing agent may be used alone, or 2 or more kinds may be used simultaneously.

The resin layer may contain various additives such as a dispersant, a buffer, and a viscosity adjuster, which are generally widely added to the resin insulating film of the semiconductor package, within a range that does not impair the characteristics thereof.

< Shape >

The thickness of the resin layer is preferably 1 μm to 5 μm, which is larger than the height of the protruding portion of the via-hole, from the reason of protecting the via-hole.

Hereinafter, as an application example of the metal-filled microstructure 20, an example in which the metal-filled microstructure 20 is used for the anisotropic conductive member 22 (see fig. 16 and the like) will be described.

Fig. 16 is a schematic view showing example 1 of a laminated device using a metal-filled microstructure according to an embodiment of the present invention, fig. 17 is a schematic view showing example 2 of a laminated device using a metal-filled microstructure according to an embodiment of the present invention, fig. 18 is a schematic view showing example 3 of a laminated device using a metal-filled microstructure according to an embodiment of the present invention, and fig. 19 is a schematic view showing example 4 of a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

Further, as in the stacked device 60 shown in fig. 16, the semiconductor element 62 and the semiconductor element 64 may be bonded in the stacking direction Ds via the anisotropic conductive member 22 exhibiting anisotropic conductivity, so that the semiconductor element 62 and the semiconductor element 64 may be electrically connected. The anisotropic conductive member 22 has the same structure as the metal-filled microstructure 20 described above, and has a via 16 (see fig. 5) that is conductive in the stacking direction Ds, and functions as a TSV (Through Silicon Via: through-silicon via). In addition, the anisotropic conductive member 22 can also be used as an interposer (interposer).

In addition to the configuration shown in fig. 16, the following configuration may be adopted, for example: as in the stacked device 60 shown in fig. 17, the semiconductor element 62, the semiconductor element 64, and the semiconductor element 66 are stacked and bonded in the stacking direction Ds via the anisotropic conductive member 22, and are electrically connected.

The following structure may be used: as in the stacked device 60 shown in fig. 18, the interposer 23 and the anisotropic conductive member 22 are used to stack and bond the semiconductor element 62, the semiconductor element 64, and the semiconductor element 66 in the stacking direction Ds, and are electrically connected.

The stacked device 60 shown in fig. 19 can also function as an optical sensor. The stacked device 60 shown in fig. 19 is stacked with the semiconductor element 72 and the sensor chip 74 in the stacking direction Ds via the anisotropic conductive member 22. A lens 76 is provided on the sensor chip 74.

The semiconductor element 72 is not particularly limited in configuration as long as it can process a signal obtained from the sensor chip 74.

The sensor chip 74 has a photosensor that detects light. The photosensor is not particularly limited as long as it can detect light, and for example, a CCD (Charge Coupled Device: charge coupled device) image sensor or a CMOS (Complementary Metal Oxide Semiconductor: complementary metal oxide semiconductor) image sensor can be used.

In the stacked device 60 shown in fig. 19, the semiconductor element 72 and the sensor chip 74 are connected via the anisotropic conductive member 22, but the present invention is not limited to this, and the semiconductor element 72 and the sensor chip 74 may be directly bonded.

The configuration of the lens 76 is not particularly limited as long as it can collect light to the sensor chip 74, and a lens called a microlens, for example, may be used.

The semiconductor elements 62, 64, and 66 have element regions (not shown).

The element region is a region in which various elements such as a capacitor, a resistor, and a coil, which function as electronic elements, are formed to constitute a circuit or the like. In the element region, for example, there are the following regions: a region in which a memory circuit such as a flash memory, a logic circuit such as a microprocessor and an FPGA (field-programmable gate array) and the like are formed, and a region in which a communication module such as a wireless tag and wiring are formed. In addition to this, a transmission circuit or a MEMS (Micro Electro MECHANICAL SYSTEMS: microelectromechanical system) may be formed in the element region. MEMS are for example sensors, actuators, antennas etc. The sensor includes, for example, various sensors such as an acceleration sensor, a sound sensor, and a light sensor.

As described above, the element region is formed with an element constituting circuit or the like, and the semiconductor element is provided with a rewiring layer (not shown), for example.

The stacked device can be configured as a combination of a semiconductor element having a logic circuit and a semiconductor element having a memory circuit, for example. The semiconductor elements may all have a memory circuit, and may all have a logic circuit. The combination of the semiconductor elements in the stacked device 60 may be a combination of a sensor, an actuator, an antenna, and the like, and a memory circuit and a logic circuit, and may be appropriately determined according to the purpose of the stacked device 60, and the like.

The semiconductor elements 62, 64, and 66 include, in addition to the above, logic integrated circuits such as an ASIC (Application SPECIFIC INTEGRATED Circuit), an FPGA (Field Programmable GATE ARRAY), and an ASSP (Application SPECIFIC STANDARD Product). Further, examples thereof include microprocessors such as a CPU (Central Processing Unit: central processing unit) and a GPU (Graphics Processing Unit: graphics processor). Examples of the Memory include a DRAM (Dynamic Random Access Memory: dynamic random access Memory), HMC (Hybrid Memory Cube: hybrid Memory cube), MRAM (Magnetoresistive Random Access Memory: magnetoresistive random access Memory), PCM (Phase-Change Memory), reRAM (RESISTANCE RANDOM ACCESS MEMORY: variable resistance Memory), feRAM (Ferroelectric Random Access Memory: ferroelectric random access Memory), and flash Memory. Examples of the integrated circuit include an analog integrated circuit such as an LED (LIGHT EMITTING Diode), a power device, a DC (Direct Current) -DC (Direct Current) converter, and an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor IGBT).

Examples of the semiconductor device include a wireless device such as GPS (Global Positioning System: global positioning system), FM (Frequency Modulation: frequency modulation), NFC (NEAR FIELD Communication: near field Communication), RFEM (RF Expansion Module: radio Frequency expansion module), MMIC (Monolithic Microwave Integrated Circuit: monolithic microwave integrated circuit), WLAN (Wireless Local Area Network: wireless local area network), a discrete device, a Passive device, SAW (Surface Acoustic Wave: surface acoustic wave) filter, RF (Radio Frequency) filter, IPD (INTEGRATED PASSIVE DEVICES: integrated Passive device), and the like.

Next, a description will be given of example 1 of a method for manufacturing a laminated device using a metal-filled microstructure.

The 1 st example of the method of manufacturing a stacked device using a metal-filled microstructure relates to a chip-on-wafer (chip) and shows a method of manufacturing a stacked device 60 shown in fig. 16.

Fig. 20 to 22 are schematic views showing, in order of steps, example 1 of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

In example 1 of the method for manufacturing a laminated device using a metal-filled microstructure, first, a semiconductor element 64 having an anisotropic conductive member 22 provided on a surface 64a is prepared.

Next, the semiconductor element 64 is arranged so that the anisotropic conductive member 22 faces the 1 st semiconductor wafer 80. Next, the alignment mark of the semiconductor device 64 and the alignment mark of the 1 st semiconductor wafer 80 are used to align the semiconductor device 64 with respect to the 1 st semiconductor wafer 80.

In addition, in the alignment, the configuration is not particularly limited as long as digital image data can be obtained with respect to the image or the reflection image of the alignment mark of the 1 st semiconductor wafer 80 and the image or the reflection image of the alignment mark of the semiconductor element 64, and a known image pickup device can be appropriately used.

Next, the semiconductor device 64 is placed on the device region of the 1 st semiconductor wafer 80 via the anisotropic conductive member 22, and is heated to a predetermined temperature and held for a predetermined time by applying a predetermined pressure, for example, and is temporarily bonded using the resin layer 44 (see fig. 14). The above-described processing is performed for all the semiconductor elements 64, and as shown in fig. 21, all the semiconductor elements 64 are temporarily bonded to the element region of the 1 st semiconductor wafer 80.

The resin layer 44 is used for temporary bonding, and may be one of the methods described below. For example, the semiconductor device 64 may be temporarily bonded to the device region of the 1 st semiconductor wafer 80 by supplying a sealing resin or the like to the 1 st semiconductor wafer 80 by a dispenser (or the like), or the semiconductor device 64 may be temporarily bonded to the device region on the 1 st semiconductor wafer 80 using a previously supplied insulating resin Film (NCF (Non-conductive Film)).

Next, in a state where all the semiconductor elements 64 are temporarily bonded to the element region of the 1 st semiconductor wafer 80, a predetermined pressure is applied to the semiconductor elements 64, and the semiconductor elements 64 are heated to a predetermined temperature and held for a predetermined time, so that all the plurality of semiconductor elements 64 are bonded to the element region of the 1 st semiconductor wafer 80 at once. This engagement is called formal engagement. Thus, the terminal (not shown) of the semiconductor element 64 is bonded to the anisotropic conductive member 22, and the terminal (not shown) of the 1 st semiconductor wafer 80 is bonded to the anisotropic conductive member 22.

Next, as shown in fig. 22, the 1 st semiconductor wafer 80, to which the semiconductor elements 64 are bonded via the anisotropic conductive members 22, is singulated by dicing, laser scribing, or the like for each element region. Thus, the stacked device 60 in which the semiconductor element 62, the anisotropic glycerin component 22, and the semiconductor element 64 are bonded can be obtained.

In addition, when the temporary joining is performed, if the temporary joining strength is weak, positional deviation occurs in the conveying process or the like and the processes up to the joining, and therefore the temporary joining strength becomes important.

The temperature condition in the temporary bonding process is not particularly limited, but is preferably 0 to 300 ℃, more preferably 10 to 200 ℃, and particularly preferably normal temperature (23 ℃) to 100 ℃.

Similarly, the pressurizing condition in the temporary bonding process is not particularly limited, and is preferably 10MPa or less, more preferably 5MPa or less, and particularly preferably 1MPa or less.

The temperature condition in the primary bonding is not particularly limited, but is preferably a temperature higher than the temperature of the temporary bonding, specifically, 150 to 350 ℃, and particularly preferably 200 to 300 ℃.

The pressurizing condition in the main joint is not particularly limited, but is preferably 30MPa or less, and more preferably 0.1MPa to 20MPa.

The time for the primary bonding is not particularly limited, but is preferably 1 second to 60 minutes, more preferably 5 seconds to 10 minutes.

By performing the main bonding under the above conditions, the resin layer flows between the electrodes of the semiconductor element 64, and is less likely to remain in the bonding portion.

As described above, in the main bonding, the bonding of the plurality of semiconductor elements 64 is performed at once, whereby the tact time can be shortened and the productivity can be improved.

A description will be given of example 2 of a method for manufacturing a stacked device using a metal-filled microstructure.

Fig. 23 to 25 are schematic views showing, in order of steps, the 2 nd example of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

In example 2 of the method of manufacturing a laminated device using a metal-filled microstructure, 3 semiconductor elements 62, 64, 66 are laminated and bonded via the anisotropic conductive member 22, as compared with example 1 of the method of manufacturing a laminated device using a metal-filled microstructure, except that the method is the same as example 1 of the method of manufacturing a laminated device using a metal-filled microstructure. Therefore, a detailed description of the same manufacturing method as example 2 of the manufacturing method of the laminated device will be omitted.

The semiconductor element 64 is provided with an alignment mark (not shown) on the back surface 64b and a terminal (not shown). The anisotropic conductive member 22 is provided on the surface 64a of the semiconductor element 64. The semiconductor element 66 is also provided with the anisotropic conductive member 22 on the surface 66 a.

As shown in fig. 23, in a state where all the semiconductor elements 64 are temporarily bonded to the element region of the 1 st semiconductor wafer 80 via the anisotropic conductive member 22, the alignment marks of the back surface 64b of the semiconductor elements 64 and the alignment marks of the semiconductor elements 66 are used to align the semiconductor elements 64 with the semiconductor elements 66.

Next, as shown in fig. 24, the semiconductor element 66 is temporarily bonded to the back surface 64b of the semiconductor element 64 via the anisotropic conductive member 22. Next, all the semiconductor elements 64 are temporarily bonded to the element region of the 1 st semiconductor wafer 80 via the anisotropic conductive member 22, and the semiconductor elements 66 are temporarily bonded to all the semiconductor elements 64 via the anisotropic conductive member 22, and the main bonding is performed under predetermined conditions. Thus, the semiconductor element 64 and the semiconductor element 66 are bonded via the anisotropic conductive member 22, and the semiconductor element 64 and the 1 st semiconductor wafer 80 are bonded via the anisotropic conductive member 22. Terminals (not shown) of the semiconductor element 64, the semiconductor element 66, and the 1 st semiconductor wafer 80 are bonded to the anisotropic conductive member 22.

Next, as shown in fig. 25, the 1 st semiconductor wafer 80, in which the semiconductor element 64 and the semiconductor element 66 are bonded via the anisotropic conductive member 22, is singulated by dicing, laser scribing, or the like, for each element region. Thus, the stacked device 60 in which the semiconductor element 62, the semiconductor element 64, and the semiconductor element 66 are bonded via the anisotropic conductive member 22 can be obtained.

A description will be given of example 3 of a method for manufacturing a stacked device using a metal-filled microstructure.

A 3 rd example of a method of manufacturing a stacked device using a metal-filled microstructure relates to wafer-on-wafer (wafer), and shows a method of manufacturing a stacked device 60 shown in fig. 16.

Fig. 26 and 27 are schematic views showing, in order of steps, the 3 rd example of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

In example 3 of the method for manufacturing a laminated device using the metal-filled microstructure, the 1 st semiconductor wafer 80 and the 2 nd semiconductor wafer 82 are bonded via the anisotropic conductive member 22, as compared with example 1 of the method for manufacturing a laminated device, except that the method is the same as example 3 of the method for manufacturing a laminated device. Therefore, a detailed description of the same manufacturing method as example 1 of the manufacturing method of the laminated device is omitted. The anisotropic conductive member 22 is also described above, and thus a detailed description thereof is omitted.

First, the 1 st semiconductor wafer 80 and the 2 nd semiconductor wafer 82 are prepared. The anisotropic conductive member 22 is provided on either the surface 80a of the 1 st semiconductor wafer 80 or the surface 82a of the 2 nd semiconductor wafer 82.

Next, the surface 80a of the 1 st semiconductor wafer 80 and the surface 82a of the 2 nd semiconductor wafer 82 are opposed to each other. Then, the 1 st semiconductor wafer 80 is aligned with the 2 nd semiconductor wafer 82 by using the alignment mark of the 1 st semiconductor wafer 80 and the alignment mark of the 2 nd semiconductor wafer 82.

Next, the surface 80a of the 1 st semiconductor wafer 80 and the surface 82a of the 2 nd semiconductor wafer 82 are opposed to each other, and the 1 st semiconductor wafer 80 and the 2 nd semiconductor wafer 82 are bonded via the anisotropic conductive member 22 by the above-described method, as shown in fig. 26. In this case, the temporary joining may be followed by the final joining, or the final joining may be performed only.

Next, as shown in fig. 27, the 1 st semiconductor wafer 80 and the 2 nd semiconductor wafer 82 are singulated by dicing, laser scribing, or the like, for example, in a state where they are bonded via the anisotropic conductive member 22, for each element region. Thus, the stacked device 60 in which the semiconductor element 62 and the semiconductor element 64 are bonded via the anisotropic conductive member 22 can be obtained. In this way, even if a wafer on a wafer is used, the stacked device 60 can be obtained.

In addition, since the singulation is performed as described above, a detailed description thereof is omitted.

As shown in fig. 27, in a state where the 1 st semiconductor wafer 80 and the 2 nd semiconductor wafer 82 are bonded, if there is a semiconductor wafer that needs to be thinned in the 1 st semiconductor wafer 80 and the 2 nd semiconductor wafer 82, the thinning can be performed by Chemical Mechanical Polishing (CMP) or the like.

In example 3 of the method for manufacturing a stacked device using a metal-filled microstructure, the two-layer structure in which the semiconductor element 62 and the semiconductor element 64 are stacked has been described as an example, but the present invention is not limited to this, and it is needless to say that the number of layers may be 3 or more as described above. In this case, as in the case of example 2 of the method for manufacturing the stacked device 60, the stacked device 60 having 3 or more layers can be obtained by providing the alignment marks (not shown) and the terminals (not shown) on the back surface 82b of the 2 nd semiconductor wafer 82.

As described above, by providing the anisotropic conductive member 22 in the stacked device 60, even if irregularities are present in the semiconductor element, the irregularities can be absorbed by using the protruding portions 16a and 16b as buffer layers. Since the protruding portions 16a and 16b function as buffer layers, a high surface quality is not required for the surface where the element region exists in the semiconductor element. Therefore, smoothing processing such as grinding is not required, the production cost can be suppressed, and the production time can be shortened.

Further, since the stacked device 60 can be manufactured using the chips on the wafer, the yield can be maintained and the manufacturing loss can be reduced by bonding only the qualified semiconductor chips to the qualified portion in the semiconductor wafer.

As described above, the resin layer 44 has adhesion, and can be used as a temporary bonding agent in temporary bonding, and can be bonded together in a main form.

The semiconductor element 64 provided with the anisotropic conductive member 22 can be formed using the anisotropic conductive member 22 and a semiconductor wafer having a plurality of element regions (not shown). The element region is provided with the alignment mark (not shown) and the terminal (not shown) for alignment as described above. In the anisotropic conductive material 50 (refer to fig. 15), the anisotropic conductive member 22 is formed in a pattern matching the element region.

First, a predetermined pressure is applied, heated to a predetermined temperature and held for a predetermined time, and the anisotropic conductive member 22 of the anisotropic conductive material 50 is bonded to the element region of the semiconductor wafer.

Then, the support 46 of the anisotropic conductive material 50 is removed, and only the anisotropic conductive member 22 is bonded to the semiconductor wafer. In this case, the anisotropic conductive material 50 is heated to a predetermined temperature, and the adhesive force of the release agent 49 of the release layer 47 is reduced, so that the support 46 is removed starting from the release layer 47 of the anisotropic conductive material 50. Next, the semiconductor wafer is singulated for each device region, to obtain a plurality of semiconductor devices 64.

Further, the explanation has been made taking the semiconductor element 64 provided with the anisotropic conductive member 22 as an example, but the anisotropic conductive member 22 may be provided in the same manner as the semiconductor element 64 provided with the anisotropic conductive member 22 with respect to the semiconductor element 66 provided with the anisotropic conductive member 22 and the 2 nd semiconductor wafer 82 provided with the anisotropic conductive member 22.

The semiconductor device is bonded to the semiconductor element by bonding the other semiconductor element, but the present invention is not limited to this, and a plurality of semiconductor elements may be bonded to one semiconductor element, that is, one-to-many semiconductor elements may be bonded to one semiconductor element. Further, a plurality of semiconductor elements and a plurality of semiconductor elements may be bonded, that is, a many-to-many method.

Fig. 28 is a schematic view showing a5 th example of a laminated device according to an embodiment of the present invention, fig. 29 is a schematic view showing a 6 th example of a laminated device according to an embodiment of the present invention, fig. 30 is a schematic view showing a 7 th example of a laminated device according to an embodiment of the present invention, fig. 31 is a schematic view showing a 8 th example of a laminated device according to an embodiment of the present invention, and fig. 32 is a schematic view showing a 9 th example of a laminated device according to an embodiment of the present invention.

As one-to-many method, as shown in fig. 28, for example, a stacked device 83 is illustrated in which a semiconductor element 62, a semiconductor element 64, and a semiconductor element 66 are bonded and electrically connected by using an anisotropic conductive member 22, respectively. In addition, the semiconductor element 62 may have an interposer function. In the stacked device 83, the semiconductor element 62, the semiconductor element 64, and the semiconductor element 66 may be replaced with a semiconductor element wafer.

As a many-to-many method, for example, as shown in fig. 29, a stacked device 84 is illustrated in which the semiconductor element 64 and the semiconductor element 66 are bonded to and electrically connected to one semiconductor element 62 using the anisotropic conductive member 22. The semiconductor element 62 may have an interposer function.

For example, a plurality of devices such as a logic chip and a memory chip having a logic circuit may be stacked on a device having an interposer function. In this case, the electrodes of the devices can be bonded even if the electrodes are different in size.

In the stacked device 85 shown in fig. 30, the electrodes 88 are different in size, and although electrodes different in size are mixed, the semiconductor element 64 and the semiconductor element 66 are bonded and electrically connected to one semiconductor element 62 using the anisotropic conductive member 22. The semiconductor element 86 is bonded to and electrically connected to the semiconductor element 64 using the anisotropic conductive member 22. The semiconductor element 87 is bonded and electrically connected to the semiconductor element 64 and the semiconductor element 66 using the anisotropic conductive member 22.

As shown in fig. 31, the stacked device 89 includes the semiconductor element 64 and the semiconductor element 66 bonded to each other by the anisotropic conductive member 22 and electrically connected to one semiconductor element 62. The following structure is also possible: semiconductor element 86 and semiconductor element 87 are bonded to semiconductor element 64 using anisotropic conductive member 22, and semiconductor element 91 is bonded to and electrically connected to semiconductor element 66 using anisotropic conductive member 22.

In the case of the above-described structure, silicon photons assuming a high frequency can be handled by stacking a light emitting element such as a VCSEL (VERTICAL CAVITY Surface EMITTING LASER: vertical cavity Surface emitting laser) and a light receiving element such as a CMOS (Complementary Metal Oxide Semiconductor) image sensor on a device Surface including an optical waveguide.

For example, as shown in fig. 32, the stacked device 89a, the semiconductor element 64 and the semiconductor element 66 are bonded and electrically connected to one semiconductor element 62 using the anisotropic conductive member 22. The semiconductor element 86 and the semiconductor element 87 are bonded to the semiconductor element 64 using the anisotropic conductive member 22, and the semiconductor element 91 is bonded to and electrically connected to the semiconductor element 66 using the anisotropic conductive member 22. An optical waveguide 81 is provided on the semiconductor element 62. A light emitting element 95 is provided on the semiconductor element 66, and a light receiving element 96 is provided on the semiconductor element 64. The light Lo output from the light emitting element 95 of the semiconductor element 66 passes through the optical waveguide 81 of the semiconductor element 62 and is emitted as the emitted light Ld to the light receiving element 96 of the semiconductor element 64. This can cope with the silicon photons.

Further, holes 27 are formed in the anisotropic conductive member 22 at positions corresponding to the optical paths of the light Lo and the emitted light Ld.

A specific assembly process in three-dimensional lamination using a laminate will be described.

In order to realize three-dimensional lamination, it is necessary to form, in the laminated device, a wiring that takes charge of electrical connection in the lamination direction, which is called a TSV (Through Silicon Via: through silicon via). Devices with TSVs are classified into three types, pre-drilled (Via-first), mid-drilled (Via-middle), and post-drilled (Via-last), depending on which stage the TSV is formed. The formation of TSVs prior to the formation of the transistors of the device is referred to as pre-drilling. The formation after the transistor is formed and before the formation of the rewiring layer is referred to as a middle-drilled hole. The formation of the wiring layer after the formation of the rewiring layer is called post-drilling. The formation of TSVs by any method requires thinning of the silicon substrate for the penetration process.

The method of bonding the semiconductor chip or wafer to which the TSV is applied will be described together with an example of the mode of use of the laminate.

As a representative example of the pre-drilling or mid-drilling, a stacked memory chip called HBM (High Bandwidth Memory: high bandwidth memory) or HMC (Hybrid Memory Cube) is given. In these examples, the memory region is formed in the same mold shape, the TSV region is formed, the substrate wafer is thinned, the TSV is formed, and an electrode called a microbump is formed on the surface of the via hole and laminated and bonded.

As an example of the post-drilling, the following steps may be mentioned: the semiconductor chip or wafer without the metal bump is bonded by an insulating adhesive or insulating oxide, and then the TSV is formed.

Conventionally, after interlayer bonding is formed, holes are formed by a BOSCH method, a laser drilling method, or the like, plated cores are formed on the wall surfaces by sputtering or the like, and metal is filled by plating, so that the holes are electrically bonded to wiring portions of the respective layers.

However, the filler metal is formed by growth of the plating nuclei, and therefore, the bonding between the filler metal and the wiring portion is not necessarily ensured. In contrast, in the case where the anisotropic conductive member is used to connect the bumps, the conductive path of the anisotropic conductive member is directly formed to be bonded to the bumps, so that the electrical connection is enhanced, and the signal connection is further improved. In this case, the electrodes which do not contribute to signal transmission are provided on the surface of the semiconductor chip or the surface of the wafer, whereby the area of the joint portion is increased and the resistance per shear stress can be improved. Further, heat conduction between layers is good, and therefore, heat is easily diffused to the entire laminate. According to these mechanisms, the connection strength and heat dissipation performance are further improved.

Examples of bonding methods applicable to any of the preceding, intermediate, and subsequent holes include metal diffusion bonding, oxide film direct bonding, metal bump bonding, and eutectic bonding.

The metal diffusion bonding or the oxide film direct bonding is excellent in bonding property under low pressure and low temperature conditions. On the other hand, as the high cleanliness of the joint surface, for example, a level equivalent to that immediately after surface cleaning by Ar etching is required. Further, since flatness is required to have an arithmetic average roughness Ra of 1nm or less, strict environmental control and parallelism control are required at the time of bonding, and the types of semiconductor devices and wiring rules may be different in different companies or in product groups of semiconductor devices manufactured in different factories even though the companies are the same, and in the case of three-dimensionally stacking such product groups of semiconductor devices, the most strict precision or control is required.

On the other hand, in the case where some defects exist, or in the case of process redundancy, the bondability of the metal bump bonding or eutectic bonding is also good. Also, due to deformation or flow of the bump or solder, the cleanliness or flatness of the device surface when bonding different kinds of devices may sometimes be lower than metal diffusion bonding or oxide film direct bonding.

Among these joining methods, the following are given as the subject: the bonding strength is lower than that of the metal diffusion bonding and the oxide film direct bonding; and a device failure may be caused by reheating the bonded portion each time lamination is repeated. The following method is proposed in the literature (National Institute of Advanced Industrial SCIENCE AND Technology (AIST) research results report 2013, 3, 8 days: "research and development of evaluation analysis technology of multifunctional high-density three-dimensional integration technology (2) next generation three-dimensional integration" < (2) -B heat/lamination bonding technology > "): the temporary fixation is performed by the organic resin when laminating, and after all layers are laminated, the layers are heated and bonded together, thereby avoiding the influence of the temperature history. Since the heat dissipation is improved by forming an electrode that does not contribute to signal transmission, it is particularly useful to apply the laminate to a system using an organic resin layer having low thermal conductivity.

Next, a case will be described in which an anisotropic conductive member constituting the laminate is used for the above-described bonding.

The anisotropic conductive member used in the laminate is preferably formed with a resin layer on at least one surface, more preferably on both surfaces.

The resin layer 44 of the anisotropic conductive member preferably contains a thermosetting resin. The resin layer thus formed serves as a temporary bonding layer to suppress misalignment after lamination. Since temporary bonding can be performed at a low temperature and in a short time, adverse effects on the device can be reduced. The thickness of the resin layer is preferably 100nm to 1000nm, the thermal conductivity of the anisotropic conductive member is preferably 20 to 100W/(m·k) in the thickness direction, and the thermal expansion number (CTE) of the anisotropic conductive member is preferably 5ppm to 10ppm, from the viewpoint of suppressing misalignment caused by heat during the process.

The anisotropic conductive member is preferably supplied in a form held to the support via a releasable adhesive layer. The material of the support is not particularly limited, but is preferably silicon, glass, or the like, from the viewpoint of being not flexible and ensuring a certain flatness.

The releasable adhesive layer may be an adhesive layer having low adhesion, and preferably an adhesive layer having reduced adhesion due to heat or light irradiation. Examples of the adhesive layer having reduced adhesiveness by heating include revapha (registered trademark) manufactured by Nitto Denko Corporation and SOMATAC (registered trademark) manufactured by SOMAR Corporation. As an adhesive layer having reduced adhesiveness due to light irradiation, a material used as a general dicing tape can be used, and examples thereof include a light release layer manufactured by 3M Company.

In the anisotropic conductive member, a pattern may be formed at a stage of holding the support. Examples of patterning include, for example, embossing, singulation, and hydrophilic-hydrophobic patterning, preferably hydrophilic-hydrophobic patterning, and more preferably hydrophilic-hydrophobic patterning is singulated.

Since the anisotropic conductive member contains a conductive material, no special technique is required, for example, a special metal bump such as a fine conical gold bump, or MONSTER PAC Core technique according to CONNECTEC JAPAN, tohoku MicroTec co., ltd. And National Institute of Advanced Industrial SCIENCE AND Technology (AIST) green Liu Changhong, which are the research groups, is required as long as an electrode is formed on the surface of the object to be bonded for bonding. In particular, in order to enable bonding even when the surface flatness of the bonding object is low, it is preferable that the anisotropic conductive member has a protrusion on the surface, and as described above, it is more preferable that the protruding portion 16a, i.e., the protrusion, includes a protrusion composed of a conductive material.

Further, the laminate provided with the terminal having the area ratio of the present invention has excellent heat conduction between layers, and therefore heat is easily diffused to the entire laminate, and therefore heat dissipation is particularly excellent.

Next, a lamination method of the laminated device will be described.

Examples of the method of stacking different semiconductor chips include a COC (Chip on Chip) method, a COW (Chip on Wafer) method, and a WOW (Wafer on Wafer) method. The COC method is a method of stacking semiconductor chips on a semiconductor chip fixed to a substrate, and has advantages such as being capable of stacking semiconductor chips of different sizes, being capable of screening qualified semiconductor chips before bonding, and being high in cost because alignment is required every time a plurality of semiconductor chips are stacked. The COW method is a method of stacking semiconductor chips on a substrate wafer, and when stacking a plurality of semiconductor chips, the cost is high because alignment is required every time as in the COC method. The WOW method is a method of bonding wafers to each other, and has advantages such as shortening bonding time and easy alignment, but since a qualified semiconductor chip cannot be screened, the yield of a multilayer laminate is easily lowered.

For the purpose of shortening the alignment time, a method called self-alignment has been studied in which a collective alignment is performed on a wafer, and techniques are disclosed in, for example, japanese patent application laid-open publication No. 2005-150085 or japanese patent application laid-open publication No. 2014-57019. However, these documents disclose only a technique of aligning the positions of the semiconductor chips to be fixed, and any one of the above bonding methods needs to be further performed in order to electrically bond the layers to each other. In order to apply the metal diffusion bonding or the oxide film direct bonding, it is necessary to precisely control the heights of all the semiconductor chips arranged, and thus it is costly. On the other hand, in the case of applying the metal bump bonding or the eutectic bonding, it is necessary to take measures to reheat the bonded portion each time the bonding is performed by heating, and in the case of performing bonding by heating all layers together after lamination, it is necessary to take measures to prevent the semiconductor chip from being deviated and radiating heat at the time of lamination.

For the above-described problems, three-dimensional lamination using anisotropic conductive members is useful.

Therefore, it is preferable to use an anisotropic conductive member for each bonding of the laminate, but the laminate may include bonding by a conventional method. Examples of the bonding include a method in which a laminate having bonding by an anisotropic conductive member has hybrid bonding between an optical semiconductor and an ASIC (Application SPECIFIC INTEGRATED Circuit) and a method in which a laminate has surface-active bonding between a memory and an ASIC. Bonding based on the conventional method has an advantage that devices manufactured by different rules are easily stacked on each other.

Examples of the three-dimensional laminate using the anisotropic conductive member include the following.

First, the 1 st semiconductor chip set is inspected and singulated, and the 1 st qualified semiconductor chip set is screened.

The 1 st qualified semiconductor chip set is arranged on the 1 st substrate via the 1 st anisotropic conductive member and temporarily bonded. The temporary bonding can be performed by a flip-chip bonder or the like. The 1 st substrate is not particularly limited, and examples thereof include a device having a transistor, or a substrate having a wiring layer and a through electrode.

After inspection of the stacked semiconductor chip sets, singulation is performed and the stacked good semiconductor chip sets are screened. The stacked semiconductor chip set is not particularly limited, and examples thereof include a system having a through electrode and a system in which the back surface of a semiconductor chip having a buried through hole is removed. Examples of the method for removing the back surface include a back grinding method, a CMP method, and a chemical etching method. In particular, a removal method such as chemical etching with little lateral stress is preferable.

The stacked qualified semiconductor chip sets are arranged at positions of the 2 nd substrate corresponding to the arrangement of the 1 st qualified semiconductor chip sets on the 1 st substrate.

After the 1 st substrate and the 2 nd substrate are aligned, the 1 st non-defective semiconductor chip set and the stacked non-defective semiconductor chip set are temporarily bonded via the 2 nd anisotropic conductive member with the 2 nd anisotropic conductive member interposed between the 1 st substrate and the 2 nd substrate. Then, the 2 nd base is peeled off from the laminated acceptable semiconductor chip set and removed.

The structure composed of the 1 st qualified semiconductor chip set, the 2 nd anisotropic conductive member and the laminated qualified semiconductor chip set is set as a new 1 st qualified semiconductor chip set, and the 2 nd anisotropic conductive member and the laminated semiconductor chip set are repeatedly laminated until a predetermined level structure is formed.

After a predetermined hierarchical structure is formed, the hierarchical layers are subjected to primary bonding by heating and pressurizing together, thereby obtaining a three-dimensional bonded structure.

The obtained three-dimensional bonded structure is sealed by compression bonding or the like, and singulated, thereby obtaining a target element. In addition, before singulation, processes such as thinning, rewiring, electrode formation, and the like may be performed.

As other examples, the following embodiments are given: after bonding to the 1 st acceptable semiconductor chip set via the 2 nd anisotropic conductive member, a method of singulating the stacked semiconductor chip sets is performed; a mode in which the patterned anisotropic conductive member is used as the 1 st anisotropic conductive member or the 2 nd anisotropic conductive member; and a method in which the patterned anisotropic conductive member is used as an adhesive for arranging the stacked semiconductor chip sets on the 2 nd substrate, and peeling is performed at the interface between the 2 nd substrate and the anisotropic conductive member.

Further, as other examples, the following modes can be given.

First, the 1 st anisotropic conductive member is provided on the surface of the 1 st substrate. The 1 st base may be a Metal Oxide Semiconductor (MOS) or a metal oxide semiconductor (Metal Oxide Semiconductor) which is not MOS.

The 1 st semiconductor chip set is inspected and singulated, and the 1 st qualified semiconductor chip set is screened.

The 2 nd anisotropic conductive member is provided on the surface of the support via the temporary bonding layer whose adhesiveness is reduced by the treatment. The material of the support is not particularly limited, and is preferably silicon or glass. The temporary bonding layer having reduced adhesiveness by the treatment is preferably a temporary bonding layer having reduced adhesiveness by heating or a temporary bonding layer having reduced adhesiveness by light irradiation.

A pattern is provided on the 2 nd anisotropic conductive member. As the pattern, a hydrophilic and hydrophobic pattern which is singulated is more preferable. When the hydrophilic and hydrophobic patterns are singulated, the anisotropic conductive member is easily transferred to the 1 st acceptable semiconductor chip set in a subsequent process. The singulation method is not particularly limited, and examples thereof include a dicing method, a laser irradiation method, a stealth dicing method, a wet etching method, a dry etching method, and the like.

The 1 st-qualified semiconductor chip set is arranged on the support via the 2 nd anisotropic conductive member by a self-assembly technique using a pattern, and temporarily bonded. Examples of the self-assembly technique include the following methods: a droplet containing an active agent is formed on a mounting region of a substrate, a semiconductor chip set is placed on the droplet, a component is positioned on the mounting region, the droplet is dried, the component and the mounting substrate are bonded via a curable resin layer, and the active agent is rinsed. Such techniques are disclosed in Japanese patent application laid-open No. 2005-150085 or Japanese patent application laid-open No. 2014-57019. The electrodes may also be used as alignment marks when self-assembly is performed.

The 1 st base body and the 1 st acceptable semiconductor chip set are temporarily bonded via the 1 st anisotropic conductive member. Then, the temporary bonding layer is subjected to a treatment for reducing the adhesiveness, and the interface between the 2 nd anisotropic conductive member and the support is peeled off.

The 1 st substrate, the 1 st anisotropic conductive member, and the 1 st acceptable semiconductor chip set are set as new 1 st substrate, the 2 nd anisotropic conductive member is set as new 1 st anisotropic conductive member, and the 1 st acceptable semiconductor chip set and the 2 nd anisotropic conductive member are repeatedly laminated until a predetermined level structure is formed.

After the formation of the structure of the predetermined hierarchy, the three-dimensional bonded structure is obtained by performing the collective treatment under the conditions of higher pressure and higher temperature than those used in the temporary bonding, and then performing the formal bonding between the hierarchies. Since the temporary bonding layer remains in the laminate, a material that undergoes a curing reaction under the main bonding conditions is preferably used as the temporary bonding layer.

The obtained three-dimensional bonded structure is sealed by compression bonding or the like, and singulated, thereby obtaining the target laminated device. Further, before singulation, processes such as thinning, rewiring, electrode formation, and the like may be performed.

As described above, since the temporary bonding and the main bonding can be separated by using the anisotropic conductive member, there is no need to perform a high-temperature process such as reflow soldering a plurality of times, and the risk of occurrence of device failure can be reduced. In addition, as described above, in the case of using an anisotropic conductive member having a resin layer on the surface, the resin layer can alleviate the influence of the process conditions on the bonded portion. In addition, in the embodiment using an anisotropic conductive member having protrusions on the surface, even when the surface flatness of the bonding object is low, the planarization process can be simplified.

Hereinafter, three-dimensional stacking using a stacked body will be described more specifically with reference to fig. 33 to 48.

Fig. 33 to 43 are schematic views showing, in order of steps, the 4 th example of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 44 to 46 are schematic views showing, in order of steps, a method for manufacturing a laminate used in example 4 of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

Fig. 47 and 48 are schematic views showing, in order of steps, a method for manufacturing a laminate used in example 4 of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention.

The 4 th example of the method for manufacturing a laminated device using a metal-filled microstructure relates to three-dimensional lamination, and an anisotropic conductive member is used in the same manner as the 2 nd example of the method for manufacturing a laminated device using a metal-filled microstructure. Therefore, a detailed description of the same manufacturing method as example 2 of the manufacturing method of the laminated device using the metal-filled microstructure is omitted.

First, as shown in fig. 33, a1 st laminated substrate 90 having an anisotropic conductive member 22 provided on the entire surface 92a of a semiconductor wafer 92 is prepared. The semiconductor wafer 92 may have the same structure as the 1 st semiconductor wafer 80 having a plurality of device regions (not shown), for example. The semiconductor wafer 92 may be the interposer 23.

As shown in fig. 34, a2 nd laminated substrate 100 provided with a plurality of semiconductor elements 64 is prepared. The 2 nd laminated substrate 100 has a peeling functional layer 104 and an anisotropic conductive member 22 laminated on a surface 102a of the 2 nd substrate 102. A plurality of semiconductor elements 64 are provided on the anisotropic conductive member 22. The anisotropic conductive member 22 is provided with a hydrophilic film 105 in a region where the semiconductor element 64 is not provided.

In the 2 nd laminated substrate 100, the back surface 64b of the semiconductor element 64 is the 2 nd substrate 102 side surface, and the front surface 64a is the opposite side surface. For example, the semiconductor element 64 is a qualified semiconductor element that is inspected and screened.

The peeling functional layer 104 is constituted by an adhesive layer having reduced adhesiveness due to heat or light irradiation, for example. Examples of the adhesive layer having reduced adhesiveness by heating include revapha (registered trademark) manufactured by Nitto Denko Corporation and SOMATAC (registered trademark) manufactured by SOMAR Corporation. As an adhesive layer having reduced adhesiveness due to light irradiation, a material used as a general dicing tape can be used, and examples thereof include a light release layer manufactured by 3M Company.

Next, as shown in fig. 35, the 1 st laminated substrate 90 and the 2 nd laminated substrate 100 are temporarily bonded. In addition, the method of temporary bonding is as described above. In addition, a flip-chip bonding machine or other device can be used for temporary bonding.

Next, as shown in fig. 36, the 2 nd base 102 of the 2 nd laminated base 100 is removed. In this case, the semiconductor element 64 is temporarily bonded to the anisotropic conductive member 22 of the semiconductor wafer 92, and the anisotropic conductive member 22 is transferred to the surface 64a of the semiconductor element 64.

The 2 nd base 102 is removed by reducing the adhesiveness of the peeling functional layer 104 by, for example, heating or light irradiation.

Next, as shown in fig. 37, another 2 nd laminated substrate 100 is temporarily bonded to the anisotropic conductive member 22 on the surface 64a side of the semiconductor element 64 in alignment with the position of the semiconductor elements 64. In this case, the back surface 64b of the semiconductor element 64 of the other 2 nd laminated body 100 and the anisotropic conductive member 22 on the front surface 64a side of the semiconductor element 64 temporarily bonded to the semiconductor wafer 92 are temporarily bonded. The method of temporary bonding is as described above.

Next, as shown in fig. 38, the 2 nd base 102 of the other 2 nd laminated base 100 is removed. The removal method of the 2 nd substrate 102 is as described above.

As shown in fig. 38, the semiconductor element 64 is temporarily bonded to the anisotropic conductive member 22 of the semiconductor element 64 on the semiconductor wafer 92 side, and the anisotropic conductive member 22 is transferred to the surface 64a of the semiconductor element 64. Fig. 38 shows a structure in which two layers of semiconductor elements 64 are provided. In this way, by repeating the temporary bonding of the 2 nd laminated substrate 100, the number of layers of the semiconductor element 64 can be controlled.

Here, a3 rd composite laminate 106 shown in fig. 39 is prepared. The 3 rd composite laminate 106 has a3 rd substrate 108, and a hydrophilic-hydrophobic film 109 is formed on a surface 108a thereof in a specific pattern. The semiconductor element 64 is provided on the surface 108a of the 3 rd substrate 108, that is, in a region where the hydrophilic-hydrophobic film 109 is not provided. In this case, for example, the semiconductor element 64 is a qualified semiconductor element that is inspected and screened.

The hydrophilic-hydrophobic film 109 is coated with a hydrophobic material, for example, through a mask, and is set to a desired pattern, thereby obtaining a specific pattern. As the hydrophobic material, a compound such as alkylsilane or fluoroalkylsilane can be used. As the hydrophobic material, a material exhibiting a shape-based hydrophobic effect, for example, a phase separation structure of isotactic polypropylene (i-PP) or the like can be used.

Next, as shown in fig. 40, the 3 rd composite laminate 106 is temporarily bonded to the 1 st laminate substrate 90 provided with the two layers of semiconductor elements 64, on the anisotropic conductive member 22 on the surface 64a side of the semiconductor elements 64, in alignment with the positions of the semiconductor elements 64. This results in a structure in which the 3-layer semiconductor element 64 is provided.

Next, as shown in fig. 41, the 3 rd matrix 108 of the 3 rd composite laminate 106 is removed. The method of removing the 3 rd substrate 108 is the same as the method of removing the 2 nd substrate 102 described above.

Next, the semiconductor element 64, the anisotropic conductive member 22, and the semiconductor wafer 92 are bonded together by performing a collective process under conditions of higher pressure and higher temperature than those used for temporary bonding, thereby obtaining a three-dimensional bonded structure 94 shown in fig. 42. The three-dimensional joint structure 94 may be thinned, re-wired, and electrode-formed.

Next, the semiconductor wafer 92 and the anisotropic conductive member 22 of the three-dimensional bonded structure 94 are cut, and singulated as shown in fig. 43. Thus, the stacked device 60 in which 3 semiconductor elements 64 are bonded via the anisotropic conductive member 22 can be obtained. The singulation method can suitably utilize the above method.

As shown in fig. 44, the 2 nd laminated substrate 100 shown in fig. 34 is formed by laminating the peeling functional layer 104 and the anisotropic conductive member 22 on the surface 102a of the 2 nd substrate 102.

Next, as shown in fig. 45, a hydrophilic-hydrophobic film 105 is formed in a specific pattern on the anisotropic conductive member 22.

The hydrophilic-hydrophobic film 105 is patterned on the anisotropic conductive member 22 by, for example, photolithography or self-assembly. In the hydrophilic-hydrophobic membrane 105, as an example of a hydrophilic material forming a hydrophilic pattern, a hydrophilic polymer such as polyvinyl alcohol is given.

The hydrophilic-hydrophobic film 105 may be formed of a material used for the hydrophilic-hydrophobic film 109. The hydrophilic and hydrophobic film 105 can be formed into a specific pattern by exposure and development using, for example, a photoresist material containing a fluorine compound.

Next, as shown in fig. 46, the semiconductor element 64 is provided in a region where the hydrophilic-hydrophobic film 105 is not provided. Thus, the 2 nd laminated substrate 100 shown in fig. 34 was obtained.

As a method of providing the semiconductor element 64, for example, the following method can be used: a droplet containing an active agent is formed in a region where the hydrophilic-hydrophobic film 105 is not provided, the semiconductor element 64 is placed on the droplet, the droplet is positioned and dried, the semiconductor element 64 and the 2 nd base 102 are bonded via the curable resin layer, and the active agent is rinsed.

As shown in fig. 47, with respect to the 3 rd composite laminate 106 shown in fig. 39, a3 rd substrate 108 is prepared. Next, as shown in fig. 48, a hydrophilic-hydrophobic film 109 is formed in a specific pattern on the surface 108a of the 3 rd substrate 108. The hydrophilic membrane 109 has the same structure as the hydrophilic membrane 105 described above, and can be formed in the same manner.

Next, the semiconductor element 64 is provided in a region where the hydrophilic-hydrophobic film 109 is not provided. As a method of providing the semiconductor element 64, for example, the following method can be used: a droplet containing an active agent is formed in a region where the hydrophilic-hydrophobic film 109 is not provided, the semiconductor element 64 is placed on the droplet, the droplet is positioned and dried, the semiconductor element 64 and the 3 rd base 108 are bonded via the curable resin layer, and the active agent is rinsed. Thus, the 3 rd composite laminate 106 shown in fig. 39 was obtained.

In addition, a new method that does not use TSVs can also be handled. In three-dimensional mounting, as described above, one-to-many or many-to-many joining is sometimes required. In this case, it is generally necessary to provide an interposer function to any device in advance. However, in consideration of heterogeneous bonding environments, it is not preferable to design each device in advance.

As a method for solving such a problem, a method of using a rewiring layer (RDL: re-Distribution Layer: redistribution layer) alone has been proposed. By bonding and incorporating a rewiring layer having an interposer function for connecting various devices into an anisotropic conductive film, it is possible to realize a thin and TSV-free structure without being limited by the design of each device.

A stack (stack) in which a plurality of devices are stacked can be provided in the organic substrate with the same structure.

Examples of these assemblies are shown in fig. 49 to 66. The specific assembly method is not limited to the method shown in fig. 49 to 66.

Fig. 49 to 61 are schematic views showing, in order of steps, the 5 th example of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention, and fig. 62 to 66 are schematic views showing, in order of steps, the 6 th example of a method for manufacturing a laminated device using a metal-filled microstructure according to an embodiment of the present invention. In fig. 49 to 66, the same components as those of the anisotropic conductive material 50 shown in fig. 13 and the stacked device 60 shown in fig. 13 are denoted by the same reference numerals, and detailed description thereof is omitted.

First, an anisotropic conductive material 50 having a support 46 and an anisotropic conductive member 22, and a wafer 112 provided with a rewiring layer 110 are prepared. The rewiring layer 110 has the above-described interposer function.

As shown in fig. 49, the rewiring layer 110 is disposed opposite the anisotropic conductive member 22, and as shown in fig. 50, the anisotropic conductive member 22 and the rewiring layer 110 are bonded and electrically connected.

Next, as shown in fig. 51, the wafer 112 is separated from the rewiring layer 110.

Next, as shown in fig. 52, an anisotropic conductive material 50 is disposed on the rewiring layer 110 so as to face the anisotropic conductive member 22.

Next, as shown in fig. 53, the rewiring layer 110 and the anisotropic conductive member 22 are bonded, and as shown in fig. 54, one support 46 is separated.

Next, as shown in fig. 55, the semiconductor element 62 is disposed so as to face the anisotropic conductive member 22 from which one support 46 is separated. Next, as shown in fig. 56, the anisotropic conductive member 22 and the semiconductor element 62 are bonded and electrically connected. Next, as shown in fig. 57, the remaining support 46 is separated.

Next, as shown in fig. 58, the semiconductor element 64 is disposed so as to face the anisotropic conductive member 22 from which the remaining support 46 is separated on the side where the semiconductor element 62 is not disposed.

Next, as shown in fig. 59, the anisotropic conductive member 22 and the semiconductor element 64 are bonded and electrically connected. Thus, the semiconductor element 62 and the semiconductor element 64 can be stacked without using TSVs.

In fig. 58, the semiconductor element 64 is arranged, but the present invention is not limited thereto, and as shown in fig. 60, the semiconductor element 64 and the semiconductor element 66 may be arranged in one semiconductor element 62. In this case, as shown in fig. 61, a plurality of semiconductor elements 64 and 66 are arranged on one semiconductor element 62. In this case, the semiconductor element 64 and the semiconductor element 66 can be stacked over the semiconductor element 62 without using the TSV.

The rewiring layer 110 is not limited to a single use, and may be embedded in an organic substrate.

In this case, as shown in fig. 62, the organic substrate 120 is disposed so as to face the rewiring layer 110 with respect to the anisotropic conductive material 50 provided with the rewiring layer 110. The organic substrate 120 functions as an interposer, for example.

Next, as shown in fig. 63, the organic substrate 120 is electrically connected to the rewiring layer 110 by soldering, for example. In this case, the rewiring layer 110 may be embedded in the organic substrate 120.

Next, as shown in fig. 64, the supporting body 46 is separated. Next, as shown in fig. 65, the semiconductor element 62 is disposed so as to face the anisotropic conductive member 22.

Next, as shown in fig. 66, the semiconductor element 62 is bonded and electrically connected to the anisotropic conductive member 22. This enables a structure in which the rewiring layer 110 and the semiconductor element 62 are stacked.

In the above description, the semiconductor device is exemplified, but the present invention is not limited to this, and a semiconductor wafer may be used instead of the semiconductor device.

The structure of the semiconductor element is not particularly limited, and the above-described exemplary structure can be used appropriately.

Here, temporary bonding refers to fixing a semiconductor device or a half-sweet wafer to an object to be bonded while being aligned with the object to be bonded.

The primary bonding means bonding under predetermined conditions in a state of temporary bonding and bonding objects to each other. The main joint means a state in which the joint state is not permanently released unless a special external force or the like acts.

The main bonding is performed as described above, whereby the tact time can be shortened and productivity can be improved.

The bonding method is not particularly limited to the above method, but DBI (Direct Bond Interconnect: direct bond interconnect) and SAB (Surface Activated Bond: surface activated bond) can be used.

For example, in the case of bonding an anisotropic conductive member and a semiconductor wafer, the DBI is obtained by laminating a silicon oxide film on the anisotropic conductive member and the semiconductor wafer, and performing chemical mechanical polishing. Then, the silicon oxide film interface is activated by plasma treatment, and the anisotropic conductive member is brought into contact with the semiconductor wafer to bond the two.

For example, in the case of bonding an anisotropic conductive member and a semiconductor wafer, the SAB is activated by surface-treating each bonding surface of the anisotropic conductive member and the semiconductor wafer in vacuum. In this state, the anisotropic conductive member and the semiconductor wafer are brought into contact with each other in a normal temperature environment, thereby bonding the both. In the surface treatment, ion irradiation of an inert gas such as argon or neutral atomic beam irradiation is used.

When the anisotropic conductive member and the semiconductor wafer are bonded to each other during temporary bonding, the semiconductor wafer and the semiconductor device are inspected to separate the non-defective product and the non-defective product in advance, and only the non-defective product of the semiconductor device is bonded to the non-defective product portion in the semiconductor wafer via the anisotropic conductive member, whereby manufacturing loss can be reduced. The semiconductor device that is a qualified product for quality assurance is called KGD (Known Good Die: high-quality chip).

In the step of bonding the semiconductor element to the element region, all of the semiconductor elements are bonded together after the plurality of semiconductor elements are temporarily bonded, but the present invention is not limited thereto. Depending on the bonding method, temporary bonding may not be possible. In this case, temporary bonding of the semiconductor element may be omitted. In addition, the semiconductor elements may be bonded to the element region of the semiconductor wafer one by one.

The transportation, pickup, and the like of the semiconductor element and the semiconductor wafer, and the temporary bonding and the main bonding can be realized by using a known semiconductor manufacturing apparatus.

In the case of the above-described temporary bonding, TORAY ENGINEERING co., ltd, SHIBUYA CORPORATION, SHINKAWA Ltd, and Yamaha Motor co., ltd, etc., devices of respective companies can be used.

As the device for the above-mentioned main bonding, for example, wafer bonding devices of various companies such as MITSUBISHI HEAVY INDUSTR IES MACHINE TOOL CO.,LTD.、Bondtech Co.,Ltd.、PMT CORPORATION、AYUMI INDUSTRY Co.,Ltd.、Tokyo Electron Limited.(TEL)、EVG、SUSS MICROT EC SE.(SUSS)、MUSASHINO ENGINEERING CO.,LTD. are used.

When performing each bonding such as temporary bonding and main bonding, the environment, heating temperature, pressurizing force (load), and processing time at the time of bonding may be given as control factors, but conditions suitable for the devices such as semiconductor elements used may be selected.

The atmosphere at the time of bonding may be selected from inactive environments such as nitrogen atmosphere and vacuum conditions.

The heating temperature may be selected from various temperatures of 100 to 400 ℃, and the heating rate may be selected from 10 to 10 ℃/min depending on the performance of the heating stage or the heating mode. The same applies to cooling. The heating may be performed stepwise, or the heating temperature may be sequentially increased in a plurality of stages to perform bonding.

The pressure (load) may be selected from rapid pressurization and stepwise pressurization depending on the characteristics of the resin sealing agent.

The holding time and the changing time of the environment, the heating, and the pressurization at the time of bonding can be appropriately set. The procedure can be changed as appropriate. For example, the following steps can be combined: when the pressure in the 1 st stage is applied after the vacuum state is established, and then the temperature is raised by heating, the pressure in the 2 nd stage is applied for a constant time, the pressure is cooled while the pressure is being discharged, and the pressure is returned to the atmosphere at a temperature equal to or lower than the constant temperature.

This step can be performed by various recombination, and may be performed by heating in a vacuum state after pressurizing under the atmosphere, or by performing vacuum, pressurizing, and heating all together. Examples of these combinations are shown in fig. 67 to 73.

Further, by using a mechanism for individually controlling the in-plane pressure distribution and the heating distribution at the time of bonding, the yield of bonding is improved.

The temporary bonding may be similarly modified, and oxidation of the electrode surface of the semiconductor element can be suppressed by performing the bonding in an inert atmosphere, for example. Further, the bonding may be performed while applying ultrasonic waves.

Fig. 67 to 73 are graphs showing the 1 st to 7 th examples of the main joint conditions. Fig. 67 to 73 show the environment, heating temperature, pressurizing force (load), and processing time at the time of joining, where V denotes a vacuum degree, L denotes a load, and T denotes a temperature. In fig. 67 to 73, a high vacuum degree indicates a low pressure. In fig. 67 to 73, the lower the vacuum degree is, the closer to the atmospheric pressure is.

As to the environment, heating temperature, and load at the time of joining, for example, as shown in fig. 67 to 69, the temperature may be raised after the load is applied in a state of reduced pressure. As shown in fig. 70, 72, and 73, the time of applying the load and the time of raising the temperature can be matched. As shown in fig. 71, the load may be applied after the temperature is raised. As shown in fig. 70 and 71, the time of pressure decrease and the time of temperature increase can be matched.

As shown in fig. 67, 68 and 72, the temperature rise may be stepwise, or may be heated in two stages as shown in fig. 73. As shown in fig. 69 and 72, the load may be applied in a stepwise manner.

The time of pressure reduction may be performed by applying a load after the pressure reduction as shown in fig. 67, 69, 71, 72, and 73, or may be performed by matching the time of pressure reduction with the time of applying a load as shown in fig. 68 and 70. In this case, the depressurization and the joining are performed simultaneously.

The present invention is basically constructed as described above. Although the method for producing the metal-filled microstructure according to the present invention has been described in detail above, the present invention is not limited to the above-described embodiment, and various modifications and alterations can be made without departing from the gist of the present invention.

Examples

Hereinafter, the features of the present invention will be described more specifically with reference to examples. The materials, reagents, mass, proportions thereof, operations and the like shown in the following examples can be appropriately modified without departing from the gist of the present invention. Accordingly, the scope of the present invention is not limited to the following examples.

In this example, metal-filled microstructures of example 1 and example 2 and metal-filled microstructures of comparative examples 1 to 3 were produced. The metal-filled microstructure of example 1 and example 2 and the metal-filled microstructures of comparative examples 1 to 3 were evaluated for the number of microdefects and the rate of nano-defects. The evaluation results of the number of microdefects and the rate of nano-defects are shown in table 2 below.

The number of micro defects and the nano defect rate will be described below.

The evaluation of the number of microdefects will be described.

< Evaluation of the amount of micro defects >

After polishing one side of the manufactured metal-filled microstructure, the polished surface was observed by an optical microscope to attempt to find defects. Then, the number of defects was counted, and the number of defects per unit area was determined, and the number of defects was evaluated based on the evaluation criteria shown in table 1 below. In the evaluation, it is necessary to satisfy both of an evaluation criterion having a diameter of 20 to 50 μm and an evaluation criterion having a diameter exceeding 50 μm. For example, the AA was evaluated to be 20 to 50 μm in diameter satisfying 0.001 to 0.1 and no defect exceeding 50 μm in diameter was detected.

The single-sided polishing was performed as follows. First, the manufactured metal-filled microstructure was attached to a 4-inch wafer by Q-chuck (registered trademark) (MARUISHI SANGYO co., ltd. Manufactured), and the manufactured polishing apparatus was used to polish the metal-filled microstructure until the arithmetic average roughness (JIS (japanese industrial standard) B0601:2001) became 0.02 μm. Abrasive grains containing alumina were used for polishing.

TABLE 1

The evaluation of the nano defect rate will be described.

< Evaluation of Nano Defect Rate >

Regarding the produced metal-filled microstructure, an image of FE-SEM (Field Emission Scanning Electron Microscope) of 1 ten thousand times of 10 fields of view was taken for observation, and the total number of pores and the number of unfilled pores in each field of view image were counted. Using an average of the total number of pores of 10 fields and an average of the number of unfilled pores of 10 fields,

Let the nano defect rate (%) = ((average of number of unfilled pores)/(average of total number of pores)) ×100 (%). The results are shown in table 2 below.

The cross section is obtained by cutting with a Focused Ion Beam (FIB).

Hereinafter, examples 1,2 and comparative examples 1 to 3 will be described.

Example 1

The metal-filled microstructure of example 1 will be described.

[ Metal-filled microstructure ]

< Production of aluminum Member >

The method comprises the following steps: 0.06 mass%, fe:0.30 mass%, cu:0.005 mass%, mn:0.001 mass%, mg:0.001 mass%, zn:0.001 mass%, ti:0.03 mass% of an aluminum alloy having Al and unavoidable impurities as the remainder, and an ingot having a thickness of 500mm and a width of 1200mm was produced by DC (DIRECT CHILL: direct chill) casting method, after the molten metal was treated and filtered.

Then, after cutting the surface with a face cutter at an average thickness of 10mm, soaking was maintained at 550℃for about 5 hours, and when the temperature was lowered to 400℃a rolled sheet having a thickness of 2.7mm was produced using a hot rolling mill.

Further, after heat treatment at 500℃using a continuous annealing machine, the aluminum member was finished to a thickness of 1.0mm by cold rolling to obtain an aluminum member of JIS (Japanese Industrial Standard) 1050 material.

After forming the aluminum member into a wafer shape having a diameter of 200mm (8 inches), the following treatments were performed.

< Electrolytic polishing treatment >

The aluminum member was subjected to electrolytic polishing treatment using an electrolytic polishing liquid having the following composition under the conditions of a voltage of 25V, a liquid temperature of 65℃and a liquid flow rate of 3.0 m/min.

The cathode was a carbon electrode, and GP0110-30R (TAKASAGO LTD. Manufactured) was used as a power supply. And, the flow rate of the electrolyte was measured using a vortex flow monitor FLM22-10PCW (manufactured by AS ONE corporation).

(Composition of electrolytic polishing liquid)

660ML of 85% by mass phosphoric acid (Wako Pure Chemical, ltd. Reagent)

160ML of pure water

Sulfuric acid 150mL

Ethylene glycol 30mL

< Anodizing Process >

Next, according to the procedure described in japanese patent application laid-open No. 2007-204802, the aluminum member after the electrolytic polishing treatment is subjected to an anodic oxidation treatment by a self-regularization method.

The aluminum parts after the electrolytic polishing treatment were subjected to pre-anodic oxidation treatment with 0.50mol/L oxalic acid electrolyte for 5 hours at a voltage of 40V, a liquid temperature of 16℃and a liquid flow rate of 3.0 m/min.

Then, the aluminum part after the pre-anodic oxidation treatment was subjected to a stripping treatment by immersing it in a mixed aqueous solution of 0.2mol/L chromic anhydride and 0.6mol/L phosphoric acid (liquid temperature: 50 ℃ C.) for 12 hours.

Then, re-anodizing treatment was performed with 0.50mol/L of oxalic acid in an electrolyte at a voltage of 40V at a liquid temperature of 16℃and a liquid flow rate of 3.0 m/min for 3 hours and 45 minutes to obtain an anodized film having a film thickness of 30. Mu.m.

In the pre-anodic oxidation treatment and the re-anodic oxidation treatment, the cathodes were each stainless steel electrodes, and GP0110-30R (TAKASAGO LTD. Manufactured) was used as a power supply. Also, neoCool BD (Yamato Scientific CO., ltd.) was used as the cooling device, and a pair of stirrers PS-100 (EYELATOKYO RIKAKIKAI CO., ltd.) was used as the stirring and heating device. In addition, the flow rate of the electrolyte was measured using a vortex flow monitor FLM22-10PCW (manufactured by AS ONE corporation).

< Barrier removal Process >

Then, under the same treatment liquid and treatment conditions as those of the above-mentioned anodic oxidation treatment, electrolytic treatment (electrolytic removal treatment) was performed while continuously decreasing the voltage from 40V to 0V at a voltage decreasing rate of 0.2V/sec.

Then, an etching treatment (etching removal treatment) was performed by immersing the aluminum member in a 5 mass% phosphoric acid aqueous solution at 30 ℃ for 30 minutes, and the barrier layer existing at the bottom of the pores of the anodic oxide film was removed to expose the aluminum member through the pores.

Here, the average diameter of the through-holes, i.e., the pores, present in the anodized film after the barrier layer removal step was 60nm. In addition, regarding the average diameter, the following was calculated: a photograph of the surface (magnification of 5 ten thousand times) was taken by FE-SEM (Field emission-Scanning Electron Microscope: field emission scanning electron microscope) as an average value of 50 points.

The average thickness of the anodized film after the barrier layer removal step was 80. Mu.m. In addition, regarding the average thickness, the following is calculated: the anodized film was cut in the thickness direction by FIB (Focused Ion Beam) and a surface photograph (5 ten thousand times magnification) was taken by FE-SEM as an average value at 10 points.

And the density of the through holes present in the anodized film is about 1 hundred million/mm ². The density of the through holes was measured and calculated by the method described in paragraphs [0168] and [0169] of Japanese patent application laid-open No. 2008-270158.

The degree of regularity of the through holes in the anodized film was 92%. The regularity was measured and calculated by the method described in paragraphs [0024] to [0027] of JP-A2008-270158 by taking a surface photograph (magnification of 20000) by FE-SEM.

Next, a metal layer was formed on the exposed aluminum member using Zn (zinc) at the bottom of the pores. In the barrier layer removal step, a metal layer composed of Zn is formed at the bottom of the pores while removing the barrier layer by using an alkaline aqueous solution containing Zn ions. In example 1, a metal layer other than the valve metal was formed in a region of 80% or more of the area of the metal layer composed of Zn, i.e., in the bottom of the pores. The area ratio of the metal layer other than the valve metal is referred to as "area ratio other than the valve metal" in table 2.

The area ratio other than the valve metal is calculated as follows: as described above, the anodized film was cut in the thickness direction by FIB (Focused Ion Beam), and a surface photograph (magnification 5 ten thousand times) of 10 fields of view was taken by FE-SEM as a cross section, and the area ratio of the Zn layer formed on the surface of the aluminum member with the exposed pores in each field of view was measured as an average value.

< Metal filling Process >

Next, the aluminum member on which the anodic oxide film was formed was used as a cathode, platinum (Pt) was used as a positive electrode, and metal plating was performed in a supercritical state.

The following copper plating solution was used for the metal plating. The supercritical state was set by using carbon dioxide at a temperature of 35℃and a pressure of 15 MPa. Metal plating is performed in a supercritical state. The plating apparatus shown in fig. 12 was used for metal plating.

(Copper plating bath composition and conditions)

Copper sulfate 100g/L

Sulfuric acid 10g/L

Hydrochloric acid 5g/L

Nonionic surfactant 1% by mass

Current density 3A/dm ²

The temperature of the plating solution is 35 DEG C

Pressure 15Mpa

Counter electrode (positive electrode) Pt

< Substrate removal Process >

Next, the aluminum member was dissolved and removed by immersing in a 20 mass% aqueous mercury chloride solution (mercuric chloride) at 20 ℃ for 3 hours, thereby producing a metal-filled microstructure.

Example 2

In example 2, the aluminum member (metal portion) was removed after the anodic oxide film was formed, as compared with example 1. Then, pore expansion and removal of the barrier layer are performed. Thereby, the anodic oxide film 14 alone (refer to fig. 8).

The pores were enlarged and the barrier layer was removed, and immersed in a 50g/L aqueous phosphorus solution at 40℃for 15 minutes.

Next, an Au (gold) film is formed on the rear surface 14b of the anodized film 14 by electroless plating, and a metal member 24 is provided on the rear surface 14b of the anodized film 14 (see fig. 10). The metal member covers the entire opening of the pore, and the metal member 24 other than the valve metal is exposed at the bottom of the pore (see fig. 10). In example 2, the region of 100% area in the bottom of the pore was constituted by the metal member 24 (refer to fig. 10) other than the valve metal, and the area ratio other than the valve metal was 100%.

Next, metal plating was performed on the anodized film 14 provided with the metal member 24 under the same conditions as in example 1 in a supercritical state.

After the metal plating, the metal member is polished and removed, thereby producing a metal-filled microstructure.

In example 2, the average diameter of the pores was 60nm and the regularity of the pores was 92% in the same manner as in example 1.

Comparative example 1

Comparative example 1 is identical to example 1 except that the plating reaction field is set to a liquid phase and metal plating is performed at atmospheric pressure in the plating step as compared with example 1. Comparative example 1 was not subjected to metal plating in the supercritical state.

Comparative example 2

Comparative example 2 is identical to example 2 except that the plating reaction field is set to a liquid phase and metal plating is performed at atmospheric pressure in the plating step as compared with example 2. Comparative example 2 was not subjected to metal plating in the supercritical state.

Comparative example 3

Comparative example 3 was the same as example 1 except that the area ratio of the metal layer composed of Zn was set to 50% as compared with example 1. In comparative example 3, the etching treatment time in the barrier layer removal step was shortened to adjust the area ratio.

TABLE 2

As shown in table 2, the examples 1 and 2 were excellent in that the number of micro defects was small and the nano defect rate was also small, compared with the comparative examples 1 to 3.

In comparative examples 1 and 2, since metal plating was not performed in a supercritical state, the metal did not sufficiently fill the pores, and the number of micro defects was large and the nano defect rate was also large.

In comparative example 3, the area ratio of the material other than the valve metal was small, the metal did not sufficiently fill the pores, the number of micro defects was large, and the nano defect ratio was also large.

Symbol description

10 A-surface, 12-through hole, 12 c-bottom, 12 d-surface, 13-barrier, 14-anodic oxide film, 15-metal, 15 a-metal layer, 15 b-metal, 16-conductive via, 17-structure, 20-metal filled microstructure, 22-anisotropic conductive member, 23-interposer, 27-hole, 28-plating apparatus, 29-plating bath, 30-oven, 31-counter electrode, 32-power supply, 33-control part, 34-supply part, 35-pump, 36-valve, 37-supply pipe, 38-pressure regulator, 39-discharge pipe, 40-insulating substrate, 40 a-surface, 40 b-back, 16a, 16 b-protruding part, 44-resin layer, 46-support, 47-release layer, 48-layer, 49-release agent, 50-anisotropic conductive material, 60-laminated device, 62-semiconductor element, 64a, 66a, 80 a-surface, 64b, 82 b-back surface, 66, 72, 86, 87-semiconductor element, 74-sensor chip, 76-lens, 80-1 st semiconductor wafer, 81-optical waveguide, 82-2 nd semiconductor wafer, 83, 84, 85, 89 a-laminated device, 88-electrode, 90-1 st laminated substrate, 91-semiconductor element, 92-semiconductor wafer, 92a, 102a, 108 a-surface, 94-three-dimensional bonded structure, 95-light emitting element, 96-light receiving element, 100-2 nd laminated substrate, 102-2 nd substrate, 104-peeling functional layer, 105-hydrophilic-hydrophobic film, 106-3 rd composite laminated body, 108-3 rd substrate, 109-hydrophilic-hydrophobic film, 110-rewiring layer, 112-wafer, 120-organic substrate, AQ-plating solution, ds-lamination direction, dt-thickness direction, d-average diameter, ld-emergent light, lo-light, h, ht-thickness, x-direction.

Claims

1. A method for producing a metal-filled microstructure, comprising:

Providing an insulating film having a plurality of fine holes on a surface of a metal member, thereby obtaining a structure having the metal member and the insulating film; and

A plating step of plating at least a surface of the structure having one side of the insulating film with a metal in a supercritical state or subcritical state, and filling the plurality of pores with a metal, the metal being gold, silver, copper, aluminum, magnesium, nickel, or zinc,

At the beginning of the plating step, a metal layer of a metal having a higher hydrogen overvoltage than aluminum is present at the bottom of the pores of the structure,

The metal layer of the metal having the higher hydrogen overvoltage than aluminum is formed in a region of 80% or more of the area of the bottom of the pore.

2. The method for producing a metal-filled microstructure according to claim 1, wherein,

A step of forming the metal layer of the metal having a higher hydrogen overvoltage than aluminum at the bottom of the pores between the step of obtaining the structure and the plating step,

The plating step is performed in a state in which the metal layer of the metal having the higher hydrogen overvoltage than aluminum is formed in 80% or more of the area of the bottom portion of the pore at the start of the plating step.

3. The method for producing a metal-filled microstructure according to claim 1, wherein,

The metal member is made of the metal having a higher hydrogen overvoltage than aluminum, and the metal member is exposed at the bottom of the pore.

4. The method for producing a metal-filled microstructure according to claim 1 or 2, wherein the average diameter of the plurality of pores is 1 μm or less.

5. The method for manufacturing a metal-filled microstructure according to claim 1 or 2, wherein the insulating film is an oxide film.

6. The method for producing a metal-filled microstructure according to claim 5, wherein the oxide film is an anodic oxide film of aluminum.

7. The method for producing a metal-filled microstructure according to claim 1 or 2, wherein the metal layer of the metal having a higher hydrogen overvoltage than aluminum is composed of a metal less susceptible to ionization than aluminum.

8. The method for producing a metal-filled microstructure according to claim 1 or 2, wherein the metal member is composed of a noble metal, aluminum, tantalum, niobium, titanium, hafnium, zirconium, zinc, tungsten, bismuth, or antimony.