TW201939689A - Method of manufacturing bonded body, temporary-fixing member, and stacked body - Google Patents

Abstract

Provided are a method of manufacturing a bonded body in which positional error between electrically conductive members is suppressed and inhibition to bonding of the electrically conductive members is suppressed, a temporary-fixing member for use in the manufacture of the bonded body, and a stacked body. The method of manufacturing a bonded body comprises: a temporary-fixing step of providing a temporary-fixing member between at least two electrically conductive members having electrical conductivity to thereby temporarily fix the at least two electrically conductive members to each other; a removing step of removing the temporary-fixing member; and a bonding step of bonding the at least two electrically conductive members to each other. The temporary-fixing member is used for the method of manufacturing a bonded body. The stacked body comprises a stack in which a temporary-fixing member is provided between at least two electrically conductive members having electrical conductivity.

Description

Manufacturing method of joint body, temporary fixing member and laminated body

The present invention relates to a method for manufacturing a joint body that joins at least two conductive members as a connection object, a temporary fixing member for manufacturing the joint body, and a laminated body that laminates at least two conductive members, and particularly relates to the manufacture of a joint Method, temporary fixing member and laminated body.

A structural system formed by filling a plurality of through-holes provided on an insulating substrate with a conductive substance such as metal is one of the fields that have attracted attention in nanotechnology in recent years. use.
Anisotropic conductive members can be electrically connected between electronic components and circuit substrates only by being inserted between an electronic component such as a semiconductor element and a circuit substrate and pressurized. Therefore, they are widely used as electronic components such as semiconductor components. Electrical connection members and inspection connectors when performing functional inspections.
In particular, miniaturization of electronic components such as semiconductor elements is remarkable. In the method of directly connecting a wiring substrate such as wire bonding, flip chip bonding, and autoclave bonding, etc., the stability of the electrical connection of electronic components cannot be sufficiently ensured. Therefore, an anisotropic conductive member is received as an electronic connection member. attention.

Patent Document 1 describes an anisotropic conductive member. The anisotropic conductive member is provided with a plurality of conductive paths penetrating in a thickness direction of an insulating base material, and the conductive members are provided in a state of being insulated from each other. Structure; an adhesive layer is provided on the surface of the insulating base material, each of the conductive paths has a protruding portion protruding from the surface of the insulating base material, and an end portion of the protruding portion of each conductive path is exposed or protruded from the surface of the adhesive layer. In Patent Document 1, it is assumed that an adhesive layer provided on the surface of an insulating base material of an anisotropic conductive member may be temporarily fixed on a wafer, and then the anisotropic conductive member may be heated and press-bonded with a wafer welding machine. To formally join.
[Prior technical literature]
[Patent Literature]

[Patent Document 1] International Publication No. 2016/006660

In the above-mentioned Patent Document 1, as described above, when an adhesive layer provided on the surface of an insulating base material of an anisotropic conductive member is used to temporarily fix the wafer and then formally bonded, the There is room for improvement in joining. For example, if the adhesive layer remains between the electrode to be connected and the anisotropic conductive member, the bonding of the metals to each other is hindered, thereby increasing the resistance. As described above, the residual of the adhesive layer for temporary fixation causes the increase in conduction resistance.
When an adhesive layer is present during bonding, the adhesive layer flows in accordance with the bonding conditions of the actual bonding, and there is a possibility that the temporarily fixed state may deviate and position deviation may occur.

An object of the present invention is to provide a method for manufacturing a bonded body that suppresses the positional deviation of conductive members from each other and suppresses the resistance of the conductive members from joining with each other, a temporary fixing member for manufacturing the bonded body, and a laminated body.

In order to achieve the above-mentioned object, the present invention provides a method for manufacturing a bonded body. The method for manufacturing the bonded body includes a temporary fixing step of providing at least two temporary fixing members between at least two conductive members having conductivity. The conductive members are temporarily fixed to each other; a removing step to remove the temporarily fixed members; and a joining step to join at least two conductive members.

It is preferable to perform the removal step and the bonding step simultaneously.
The removing step preferably includes at least one of a gasification step of the temporary fixing member and a replacement step of replacing the temporary fixing member with a gas or a filler.
The temporary fixing member is preferably a liquid at a temperature of 23 ° C, and the boiling point of the liquid is more preferably 50 ° C to 250 ° C.
The conductive member is preferably a member having an electrode or an anisotropic conductive member.

The present invention provides a temporary fixing member for use in a method of manufacturing a bonded body.
The present invention provides a laminated body in which the temporary fixing member of the present invention is provided and laminated between at least two conductive members having conductivity.
[Inventive effect]

According to the present invention, it is possible to obtain a method of manufacturing a bonded body that suppresses the positional deviation of conductive members from each other and suppresses the resistance of the conductive members from joining with each other, a temporary fixing member for manufacturing a bonded body, and a laminated body.

Hereinafter, a method for manufacturing a bonded body, a temporary fixing member, and a laminated body according to the preferred embodiment shown in the drawings will be described in detail.
The diagrams described below are illustrative diagrams for explaining the present invention, and the present invention is not limited to the diagrams shown below.
In addition, "-" which shows a numerical range below means the numerical value included in both sides. For example, the ε ₁ coefficient value α ₁ to the numerical value β ₁ refers to a range of ε ₁ including a numerical value α ₁ and a numerical value β _{1. When} expressed by a mathematical symbol, α ₁ ≦ ε ₁ ≦ β ₁ .
If the angles such as "orthogonal" are not specifically described, they include the error range generally allowed in the technical field. The temperature is also included in an error range generally allowed in the technical field. The temperature is 23 ° C in the specification unless otherwise specified.
In addition, "same" includes the range of error generally allowed in the technical field. In addition, "all" and "whole surface" are included in the error range generally allowed in the technical field.

(Joint body)
A bonding system in which at least two conductive members can be electrically connected to each other. The bonded body can be obtained by a method for manufacturing a bonded body described later.
The conductive member is a member having an electrode or an anisotropic conductive member. As a member having an electrode, for example, a single semiconductor element that performs a specific function can be exemplified, but a combination of a plurality of elements to perform a specific function is also included in a member having an electrode. In addition, members having electrodes also include those who transmit electrical signals such as wiring members.
The anisotropically conductive member will be described in detail later, but has an electrically conductive member only in a specific direction.
Hereinafter, the bonded body will be described using a semiconductor element as an example of a conductive member, and a laminated device as an example of the bonded body will be described as an example.
In addition, bonding refers to a state in which objects are connected to each other to ensure electrical conduction. In the case of joining, the objects are permanently joined to each other. The joining in the joining step is also referred to as a formal joining.

[Laminated Device]
FIG. 1 is a schematic diagram of a first example of a multilayer device showing an example of a bonded body according to an embodiment of the present invention, and FIG. 2 is a schematic diagram of a second example of a multilayer device that is an example of a bonded body according to an embodiment of the present invention.
The multilayer device has at least two conductive members, for example, a member including an electrode or an anisotropic conductive member. A multilayer device is, for example, a person who completes, and a person who performs a predetermined function by a single unit. As described above, the laminated device is a bonded body.

The multilayer device 10 shown in FIG. 1 is, for example, a semiconductor element 12 and a semiconductor element 14 which are laminated in the stacking direction Ds and bonded, and directly connects the semiconductor element 12 and the semiconductor element 14. For example, the dimensions of the semiconductor element 12 and the semiconductor element 14 are the same. The laminated semiconductor element 12 and the semiconductor element 14 constitute a junction body 17 for electrically connecting a plurality of semiconductors. The two semiconductor elements 12 and 14 may each have the same structure or different structures.
The laminated device 10 is not limited to that shown in FIG. 1. Like the laminated device 10 shown in FIG. 2, for example, the semiconductor element 12, the semiconductor element 14, and the semiconductor element 16 may be laminated and laminated in the lamination direction Ds. 12. A structure in which the semiconductor element 14 and the semiconductor element 16 are directly electrically connected. The junction body 17 is constituted by three semiconductor elements 12, 14, and 16. The three semiconductor elements 12, 14, and 16 may each have the same structure or different structures.

For example, as shown in FIG. 3, each of the semiconductor elements 12 and 14 has a plurality of terminals 30. Although the semiconductor element 16 is not described, for example, the semiconductor element 16 has the same structure as the semiconductor elements 12 and 14.
As shown in FIG. 3, the semiconductor elements 12 and 14 include a semiconductor layer 32, a redistribution layer 34, and a passivation layer 36. The redistribution layer 34 and the passivation layer 36 are electrically insulating layers. A surface 32 a of the semiconductor layer 32 is provided with an element region (not shown) in which a circuit or the like which performs a specific function is formed. The element area will be described later. The surface 32 a of the semiconductor layer 32 corresponds to a surface of a semiconductor on which the terminal 30 is provided.
A redistribution layer 34 is provided on a surface 32 a of the semiconductor layer 32. The redistribution layer 34 is provided with a wiring 37 electrically connected to the element region of the semiconductor layer 32. A pad 38 is provided on the wiring 37, and the wiring 37 is electrically connected to the pad 38. The wiring 37 and the bonding pad 38 can receive signals from the device region, and can supply a voltage or the like to the device region.

A surface 34 a of the redistribution layer 34 is provided with a passivation layer 36. In the passivation layer 36, a terminal 30 a is provided on a pad 38 provided on the wiring 37. The terminal 30 a is electrically connected to the semiconductor layer 32.
Although the wiring 37 is not provided on the redistribution layer 34, only the pads 38 are provided. A terminal 30b is provided on the pad 38 on which the wiring 37 is not provided. The terminal 30 b is not electrically connected to the semiconductor layer 32.

Both the end surface 30c of the terminal 30a and the end surface 30c of the terminal 30b coincide with the surface 36a of the passivation layer 36, which is a so-called same plane state. The terminals 30a and 30b do not protrude from the surface 36a of the passivation layer 36. The terminal 30a and the terminal 30b shown in FIG. 3 are, for example, polished to become the same plane as the surface 36a of the passivation layer 36.
For example, when the semiconductor element 12 and the semiconductor element 14 having the structure shown in FIG. 3 are bonded, as shown in FIG. 6, the terminals 30 a corresponding to each other are directly connected to each other, and the terminals 30 b corresponding to each other are directly connected to each other. As described above, the semiconductor element 12 and the semiconductor element 14 are electrically connected to each other through the terminal 30a, and are not electrically connected through the terminal 30b, but are physically connected.

[Manufacturing method of multilayer device]
Next, a method of manufacturing the multilayer device 10 shown in FIG. 1 will be described by taking the bonding of the semiconductor element 12 and the semiconductor element 14 shown in FIG. 3 as an example. The manufacturing method of the multilayer device 10 is an example of the manufacturing method of a junction body.
4 to 6 are schematic cross-sectional views showing a first example of a method of manufacturing a multilayer device as an example of a bonded body according to an embodiment of the present invention in steps. In FIGS. 4 to 6, the same reference numerals are given to the same structures as those of the multilayer device 10 and the semiconductor elements 12 and 14 shown in FIGS. 1 to 3, and detailed descriptions thereof are omitted.
In addition, the manufacturing method of the multilayer device 10 shown in FIGS. 4 to 6 relates to a chip-on-chip.

As shown in FIG. 4, each of the semiconductor element 12 and the semiconductor element 14 is disposed to face the terminal 30.
For example, the positions of the terminals 30 a and 30 b of the semiconductor element 12 and the semiconductor element 14 are aligned by aligning the semiconductor element 12 and the semiconductor element 14 with an alignment mark (not shown). In addition, aligning the above positions is also referred to as alignment.
In FIG. 4, since the semiconductor element 12 is located below, a temporary fixing member 13 is provided on the surface 36 a of the passivation layer 36 of the semiconductor element 12.

As shown in FIG. 5, in a state where the semiconductor element 12 and the semiconductor element 14 are aligned, the semiconductor element 12 and the semiconductor element 14 are brought close to and brought into contact, and the semiconductor element 12 and the semiconductor element 14 are temporarily fixed to each other by a temporary fixing member 13. The temporarily fixed state is the laminated body 19.
In the temporary fixing based on the temporary fixing member 13 described above, the surface tension of the temporary fixing member 13 is used. Temporary fixation keeps alignment, but not permanent fixation. As described later, for example, the temporary fixing member 13 is used as a liquid at a temperature of 23 ° C. If the temporary fixing member 13 is a liquid, for example, it is easy to supply to the surface 36 a of the passivation layer 36 of the semiconductor element 12. Therefore, it is preferable.
In addition, the step of providing a temporary fixing member 13 between the semiconductor element 12 and the semiconductor element 14 and temporarily fixing the semiconductor element 12 and the semiconductor element 14 to each other by the temporary fixing member 13 shown in FIG. 4 is equivalent to having at least two A temporary fixing step in which a temporary fixing member is provided between the conductive conductive members to temporarily fix at least two conductive members to each other. The temporary fixing member 13 will be described in detail later.

Next, the temporary fixing member 13 is removed. The step of removing the temporary fixing member 13 is a removal step. The removal procedure of the temporary fixing member 13 will be described in detail later.

Next, as shown in FIG. 6, the semiconductor element 12 and the semiconductor element 14 are bonded. Thereby, the multilayer device 10 shown in FIG. 1 can be obtained. Like the semiconductor element 12 and the semiconductor element 14, a step of bonding at least two conductive members is referred to as a bonding step. In the bonding step, for example, at least two conductive members are bonded under a predetermined bonding condition.

The temporary fixing member 13 is a remover after bonding, and the temporary fixing member 13 does not exist between the semiconductor element 12 and the semiconductor element 14 after bonding. Therefore, the temporary fixing member 13 does not exist in the multilayer device 10 shown in FIGS. 1 and 2, and the temporary fixing member 13 does not exist between the semiconductor element 12 and the semiconductor element 14. With this structure, the terminals are in direct contact with each other and the resistance becomes small. In addition, since the temporary fixing member 13 is bonded in a temporarily fixed state, the positional deviation of the semiconductor element 12 and the semiconductor element 14 is suppressed during the above bonding, and the alignment accuracy of the semiconductor element 12 and the semiconductor element 14 is increased.

In addition, the semiconductor element is not limited to the terminal 30a and the terminal 30b shown in FIG. 3 and the surface 36a of the passivation layer 36, and may protrude from the surface 36a of the passivation layer 36 as shown in FIG. In this case, the protrusion amount, that is, the depression amount δ of the passivation layer 36 with respect to the terminal 30a and the terminal 30b of the surface 36a is, for example, 200 nm or more and 1 μm or less.
When the depression amount δ is less than 200 nm, it is approximately the same as the unprotruded structure shown in FIG. 3 and needs to be polished with high precision. On the other hand, if the depression amount δ exceeds 1 μm, it is the same as the conventional structure in which the pad electrode is provided, and it is necessary to use a solder ball or the like for bonding.
In the structure shown in FIG. 7, the terminals 30 a and 30 b protrude from the surface 36 a of the passivation layer 36. Therefore, a resin layer 39 for protecting the terminals 30 a and 30 b may be provided on the surface 36 a of the passivation layer 36.

Regarding the above-mentioned depression amount δ, images of the cross section including the terminal 30a and the terminal 30b are obtained in the semiconductor elements 12, 14; the image of the terminal 30a and the terminal of the terminal 30b are obtained by image analysis; and the end surface 30c and the terminal of the terminal 30a are detected The end face 30c of 30b. The distance from the surface 36a of the passivation layer 36 to the end surface 30c of the terminal 30a and the distance between the end surface of the terminal 30b and 30c can be obtained.
The end surface 30c of the terminal 30a and the end surface 30c of the terminal 30b are both surfaces located farthest from the surface 36a of the passivation layer 36, and are generally surfaces referred to as upper surfaces.

The semiconductor layer 32 is not particularly limited as long as it is a semiconductor, and is composed of silicon or the like, but it is not limited thereto, and may be silicon carbide, germanium, gallium arsenide, gallium nitride, or the like.
The redistribution layer 34 is made of a material having electrical insulation, for example, polyimide.
The passivation layer 36 is also made of a material having electrical insulation, for example, silicon nitride (SiN) or polyimide.
The wirings 37 and the pads 38 are made of a conductive material, for example, copper, a copper alloy, aluminum, or an aluminum alloy.

The terminals 30a and 30b are made of a conductive material, like the wiring 37 and the pad 38, and are made of, for example, a metal or an alloy. Specifically, the terminals 30a and 30b are made of, for example, copper, copper alloy, aluminum, or aluminum alloy.
In addition, the terminals 30a and 30b may be conductive as long as they are not limited to a metal or an alloy, and a material called a terminal or an electrode pad in the field of semiconductor devices can be appropriately used.

[Laminated device with anisotropic conductive member]
Next, a second example of the multilayer device will be described. The second example of the multilayer device is one having an anisotropic conductive member as a conductive member.
FIG. 8 is a schematic diagram showing a second example of a laminated device which is an example of a bonded body according to an embodiment of the present invention, and FIG. 9 is a schematic diagram showing a second example of a laminated device which is an example of a bonded body according to an embodiment of the present invention. In addition, in FIGS. 8 and 9, the same structures as those of the multilayer device 10 and the semiconductor elements 12 and 14 shown in FIGS. 1 to 3 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The multilayer device 10 shown in FIG. 8 is, for example, a semiconductor element 12, an anisotropic conductive member 15, and a semiconductor element 14 that are sequentially connected and electrically connected. The bonded body 17 includes a laminated semiconductor element 12, an anisotropic conductive member 15, and a semiconductor element 14.
The multilayer device 10 is a form in which one semiconductor element 14 is bonded to one semiconductor element 12, but it is not limited thereto. The multilayer device 10 shown in FIG. 9 may have a form in which three semiconductor elements 12, 14, and 16 are bonded via an anisotropic conductive member 15. The multilayer device 10 includes three semiconductor elements 12, 14, 16, and two anisotropic conductive members 15. The bonded body 17 includes a laminated semiconductor element 12, an anisotropic conductive member 15, a semiconductor element 14, an anisotropic conductive member 15, and a semiconductor element 16.

[Manufacturing method of a multilayer device having an anisotropic conductive member]
Next, a method for manufacturing the multilayer device 10 having the anisotropic conductive member 15 shown in FIG. 8 will be described.
10 to 12 are schematic cross-sectional views showing a second example of a method of manufacturing a multilayer device, which is an example of a bonded body according to an embodiment of the present invention. FIG. 13 is a schematic cross-sectional view showing a step of a second example of a method of manufacturing a multilayer device as an example of a bonded body according to an embodiment of the present invention.
In FIGS. 10 to 13, the same structures as those of the multilayer device 10 and the semiconductor elements 12 and 14 shown in FIGS. 1 to 6 are denoted by the same reference numerals, and detailed description thereof will be omitted.
The second example of the method of manufacturing the multilayer device 10 shown in FIGS. 10 to 13 relates to a chip-on-chip.

When manufacturing the multilayer device 10 having the anisotropic conductive member 15 shown in FIG. 8, first, the semiconductor element 12, the semiconductor element 14, and the anisotropic conductive member 15 shown in FIG. 10 are prepared. The semiconductor element 12 is, for example, a plurality of electrodes 22 provided in the semiconductor element section 20 for exchanging signals with the outside or transmitting and receiving voltage or current. Each electrode 22 is electrically insulated by an insulating layer 24. The electrode 22 is more prominent than the surface 24 a of the insulating layer 24, for example.

The semiconductor element 14 has the same structure as the semiconductor element 12. The semiconductor element 14 is, for example, an interposer substrate 21 provided with a plurality of electrodes 23 for exchanging signals with the outside or transmitting and receiving voltages or currents. Each electrode 23 is electrically insulated by an insulating layer 25. The electrode 23 protrudes more than the surface 25 a of the insulating layer 25, for example. The interposer substrate 21 has, for example, a lead-out wiring layer, and the multilayer device 10 is electrically connected to the outside through an electrode 23.

The anisotropic conductive member 15 includes a plurality of conductive paths 42 (see FIGS. 10 and 13). For example, the anisotropic conductive member 15 does not include a member having a subsequent function such as an adhesive layer. The anisotropic conductive member 15 will be described in detail later.

As shown in FIG. 10, the semiconductor element 12 and the semiconductor element 14 are arranged to face the electrode 23 and the electrode 22 with the anisotropic conductive member 15 interposed therebetween. A temporary fixing member 13 is disposed between the semiconductor element 12 and the anisotropic conductive member 15, and a temporary fixing member 13 is disposed between the anisotropic conductive member 15 and the semiconductor element 14.
At this time, alignment is performed using alignment marks (not shown) provided on the semiconductor elements 12 and 14 and the anisotropic conductive member 15 respectively.
Furthermore, the alignment using the alignment mark is not particularly limited as long as an image of the alignment mark or a reflection image can be obtained to obtain the position information of the alignment mark, and a known alignment mechanism can be appropriately used. .

Next, as shown in FIG. 11, the semiconductor element 12, the anisotropic conductive member 15, and the semiconductor element 14 are located close to the semiconductor element 12, the anisotropic conductive member 15, and the semiconductor element 14. The anisotropic conductive member 15 and the semiconductor element 14 are temporarily fixed by a temporary fixing member 13 in a state. The temporarily fixed state is the laminated body 19.
Next, the temporary fixing member 13 is removed from the temporarily fixed state shown in FIG. 11. The method of removing the temporary fixing member 13 will be described later.

Next, the semiconductor element 12, the anisotropic conductive member 15, and the semiconductor element 14 are bonded. Thereby, as shown in FIG. 12 and FIG. 13, the semiconductor device 12, the anisotropic conductive member 15, and the semiconductor element 14 are bonded in a state where the temporary fixing member 13 is not present, and the multilayer device 10 can be obtained.
As shown in FIG. 13, in the multilayer device 10 manufactured in the above-mentioned bonding step, there is no member between the electrode 22 and the conductive path 42 of the anisotropic conductive member 15. With this structure, the electrode 22 is in direct contact with the conduction path 42 and the resistance is reduced.
In addition, since the bonding is performed in a state of being temporarily fixed by the temporary fixing member 13, the positional deviation of the semiconductor element 12 and the anisotropic conductive member 15 is suppressed when the above-mentioned bonding is performed, and the alignment of the semiconductor element 12 and the anisotropic conductive member 15 is suppressed. The accuracy becomes higher.
In addition, the semiconductor element 14 and the anisotropic conductive member 15 are bonded to the semiconductor element 12 and the anisotropic conductive member 15 in the same manner. The electrode 22 and the conductive path 42 are in direct contact with each other to reduce resistance, and the semiconductor is suppressed during the bonding The deviation of the position of the element 14 from the anisotropic conductive member 15 increases the accuracy of alignment between the semiconductor element 12 and the anisotropic conductive member 15.

[Anisotropic conductive member]
Next, an anisotropic conductive member is demonstrated.
14 is a schematic plan view showing an example of an anisotropic conductive member used in a bonded body according to an embodiment of the present invention, and FIG. 15 is a diagram showing an anisotropic conductive member used in a bonded body according to an embodiment of the present invention. A schematic cross-sectional view of an example of a member.

As shown in FIGS. 14 and 15, the anisotropic conductive member 15 includes: an insulating base material 40 including an inorganic material; and a plurality of conductive paths 42 in a thickness direction D of the insulating base material 40 (see FIG. 15). They are connected through and electrically insulated from each other. The via 42 is formed by filling a conductive material in the through-hole 41 formed in the insulating base material 40 and extending in the thickness direction D, and has conductivity.
Here, the “state electrically insulated from each other” refers to a state in which each of the conductive paths existing inside the insulating base material is sufficiently low in the conductivity between the conductive paths inside the insulating base material.
The conductive paths 42 of the anisotropic conductive member 15 are electrically insulated from each other, have extremely low conductivity in a direction x orthogonal to the thickness direction D (see FIG. 15) of the insulating base material 40, and have conductivity in the thickness direction D. . As described above, the anisotropic conductive member 15 is a member that exhibits anisotropic conductivity.

As shown in FIG. 15, in the state where the conductive paths 42 are electrically insulated from each other, the insulating base material 40 is provided penetrating in the thickness direction D.
Further, as shown in FIG. 15, the via 42 has a protruding portion 42 a protruding from the surface 40 a of the insulating substrate 40 in the thickness direction D, and a protruding portion 42 b protruding from the back surface 40 b in the thickness direction D. The anisotropic conductive member 15 may further include a resin layer 43 provided on the front surface 40 a and the back surface 40 b of the insulating base material 40. It is preferable that the resin layer 43 does not contact the front end portion of the protruding portion 42a and the front end portion of the protruding portion 42b.
The height Hd of the protruding portion 42a and the height Hd of the protruding portion 42b are preferably 6 nm or more, and more preferably 30 nm to 500 nm.
The height Hd of the protruding portion 42 a is a length from the surface 40 a of the insulating base material 40. The height Hd of the protruding portion 42 b is a length from the back surface 40 b of the insulating base material 40.

In FIG. 15, the resin substrate 43 is shown on the front surface 40 a and the back surface 40 b of the insulating base material 40, but the invention is not limited to this. The resin layer 43 may be provided on at least one surface of the insulating base material 40. The structure may be a structure in which the resin layer 43 is not provided on both surfaces of the insulating base material 40. The anisotropic conductive member 15 shown in FIG. 10 described above has a structure without the resin layer 43.
Similarly, the guide path 42 in FIG. 15 has protruding portions 42a and 42b at both ends, but it is not limited to this. The insulating substrate 40 may have a protruding portion on the surface of at least one side of the resin layer 43. structure.

The thickness h of the anisotropic conductive member 15 shown in FIG. 15 is, for example, 30 μm or less. The TTV (Total Thickness Variation) of the anisotropic conductive member 15 is preferably 10 μm or less. Furthermore, TTV (Total Thickness Variation) = T _Max -T _Min . T _Max is the maximum distance (thickness) from the back reference in the flatness application area. T _Min is the minimum value of the distance (thickness) from the back reference in the flatness application area.
The thickness h of the anisotropic conductive member 15 is an average value of 10 points measured in a region corresponding to the thickness h.
As a preferable method for measuring the thickness h of the anisotropic conductive member 15, an observation by an electric field emission scanning electron microscope at a magnification of 200,000 times can be used to obtain the outline shape of the anisotropic conductive member 15 and A method of measuring an average value of the measured values of the 10 points in the area corresponding to the thickness h of the anisotropic conductive member 15 in the outline shape.
The TTV (Total Thickness Variation) of the anisotropic conductive member 15 is obtained by cutting the anisotropic conductive member 15 for each support 47 with a slice, and observing the cross-sectional shape of the anisotropic conductive member 15 to obtain it. Value.

The anisotropic conductive member 15 is provided on a support body 47 as shown in FIG. 15 for transportation, transportation, transportation, storage, and the like. A release layer 44 is provided between the support body 47 and the anisotropic conductive member 15. The support body 47 and the anisotropic conductive member 15 are detachably bonded by the release layer 44. As described above, the one in which the anisotropic conductive member 15 is provided on the support 47 via the release layer 44 is referred to as an anisotropic conductive material 49.
The support 47 supports an anisotropic conductive member 15 and is made of, for example, a silicon substrate. As the support body 47, in addition to a silicon substrate, for example, a ceramic substrate such as SiC, SiN, GaN, and alumina (Al ₂ O ₃ ), a glass substrate, a fiber-reinforced plastic substrate, and a metal substrate can be used. Fiber-reinforced plastic substrates also include FR-4 (Flame Retardant Type 4) substrates as printed wiring boards.

Moreover, as the support body 47, a flexible and transparent one can be used. Examples of the flexible and transparent support 47 include PET (polyethylene terephthalate), polycycloolefin, polycarbonate, acrylic resin, PEN (polyethylene naphthalate), and PE (Polyethylene), PP (polypropylene), polystyrene, polyvinyl chloride, polyvinylidene chloride and TAC (cellulose triacetate) and other plastic films.
Here, the term “transparency” refers to a light transmittance of 80% or more based on light having a wavelength used for alignment. Therefore, the transmittance may be low in the entire region of visible light having a wavelength of 400 to 800 nm, but the transmittance is preferably 80% or more in the entire region of visible light having a wavelength of 400 to 800 nm. The transmittance was measured by a spectrophotometer.

It is preferable that the release layer 44 is a laminated layer having a support layer 45 and a release agent 46. The release agent 46 is in contact with the anisotropic conductive member 15, and the support body 47 and the anisotropic conductive member 15 are separated with the release layer 44 as a starting point. For example, by heating to a predetermined temperature, the adhesive force of the release agent 46 is weakened, and the support body 47 is removed from the anisotropic conductive member 15.
As the release agent 46, for example, REVALPHA (registered trademark) manufactured by NITTO DENKO CORPORATION. And SOMATAC (registered trademark) manufactured by SOMAR CORPORATION.

The anisotropic conductive member 15 will be described in more detail below.
[Insulating substrate]
The insulating substrate is made of an inorganic material, and is not particularly limited as long as it has a resistivity (approximately 10 ¹⁴ Ω ･ cm) equivalent to that of an insulating substrate constituting a conventionally known anisotropic conductive film or the like.
In addition, "consisting of an inorganic material" means a rule for distinguishing from a polymer material constituting a resin layer described later, and is not limited to a rule for an insulating base material consisting only of an inorganic material. The material is specified as the main component (50% by mass or more).

Examples of the insulating substrate include metal oxide substrates, metal nitride substrates, glass substrates, ceramic substrates such as silicon carbide and silicon nitride, carbon substrates such as diamond-like carbon, and polyimide groups. Materials and these composite materials. As the insulating base material, for example, it is also possible to form a film from an inorganic material containing a ceramic material or a carbon material in an amount of 50% by mass or more on an organic raw material having through holes.

As the insulating base material, a metal oxide base material is preferable, and an anodized film of a valve metal is more preferable for the reason that micropores having a desired average pore diameter are formed as through holes, and a conductive path described later is easily formed. .
Among them, specific examples of the valve metal include aluminum, tantalum, niobium, titanium, hafnium, zirconium, zinc, tungsten, bismuth, and antimony. Among these, from the viewpoint of good dimensional stability and relatively low cost, an anodized film (base material) of aluminum is preferred.

The interval between the conductive paths in the insulating substrate is preferably 5 nm to 800 nm, more preferably 10 nm to 200 nm, and even more preferably 50 nm to 140 nm. When the distance between the conductive paths in the insulating substrate is within this range, the insulating substrate sufficiently functions as an insulating partition wall.
Here, the interval between each conductive path means that the width between adjacent conductive paths is called w, and the cross section of the anisotropic conductive member is observed at a magnification of 200,000 times with an electric field emission scanning electron microscope, and the phase The width between adjacent channels was measured by an average of 10 points.

[Guideway]
The plurality of conductive paths are made of a conductive material.
＜ Conductive material ＞
The conductive material constituting the conduction path is not particularly limited as long as it has a resistivity of 10 ³ Ω ･ cm or less. As specific examples thereof, gold (Au), silver (Ag), and copper (Cu) are preferably exemplified. , Aluminum (Al), magnesium (Mg), nickel (Ni), indium-doped tin oxide (ITO), and the like.
Among them, copper, gold, aluminum, and nickel are preferred, and copper and gold are more preferred from the viewpoint of conductivity.

＜ Highlighting ＞
When the anisotropic conductive member and the electrode are electrically connected or physically joined by a method such as crimping, the vertical and horizontal directions of the protruding portion of the conductive path are sufficient to ensure the planar insulation of the protruding portion when the protruding portion collapses. The ratio (height of the protruding portion / diameter of the protruding portion) is preferably 0.5 or more and less than 50, more preferably 0.8 to 20, and even more preferably 1 to 10.

From the viewpoint of following the surface shape of the semiconductor member to be connected, the height of the protruding portion of the via is as described above, preferably 20 nm or more, and more preferably 100 nm to 500 nm.
The height of the protruding portion of the conductive path refers to an electric field emission scanning electron microscope to observe the cross section of the anisotropic conductive member at a magnification of 20,000 times, and an average of 10 points was measured for the height of the protruding portion of the conductive path.
The diameter of the protruding portion of the conductive path refers to an electric field emission type scanning electron microscope to observe the cross section of the anisotropic conductive member, and the average value of 10 points is measured for the diameter of the protruding portion of the conductive path.

＜ Other shapes ＞
The conducting path is columnar. The diameter d of the conducting path is the same as the diameter of the protruding part, and it is more preferable that it is more than 5 nm and less than 10 μm, more preferably 20 nm to 1000 nm, and more preferably less than 100 nm.

In addition, the conductive paths exist in a state of being electrically insulated from each other by an insulating substrate, but the density is preferably 20,000 pieces / mm ² or more, more preferably 2 million pieces / mm ² or more, and 10 million pieces. / mm ² or more is further preferred, 50,000,000 / mm ² or more is particularly preferably, 100 million / mm ² or more is preferred.

Furthermore, the distance p between the centers of adjacent conductive paths is preferably 20 nm to 500 nm, more preferably 40 nm to 200 nm, and 50 nm to 140 nm is even more preferred.

[Resin layer]
The resin layer may be provided, for example, on the front surface and the back surface of the insulating base material, and the above-mentioned conductive path may be buried. The resin layer can be the same as NCP (Non Conductive Paste). The resin layer may be a member having a bonding function.
<Shape>
For reasons of protecting the via, the thickness of the resin layer is greater than the height of the protruding portion of the via, and 1 μm to 5 μm is preferred.

[Other manufacturing method of multilayer device]
Next, as a method for manufacturing a multilayer device, a method based on Chip-on-Wafer will be described.
In the Chip-on-Wafer manufacturing method, a semiconductor element and a semiconductor wafer are used as conductive members. First, a semiconductor element and a semiconductor wafer will be described.
16 is a schematic perspective view showing an example of an alignment mark of a semiconductor element used in a bonded body according to an embodiment of the present invention.
As shown in FIG. 16, an alignment mark 52 is provided on the surface 14 a of the semiconductor element 14, for example, at each corner of the element region 50 and the element region 50. Four alignment marks 52 are provided on the surface 14 a of the semiconductor element 14. Further, a terminal 30 shown in FIG. 3 is provided on the surface 14a. The surface 14a faces the surface 60a (see FIG. 17) of the first semiconductor wafer 60 (see FIG. 17).
In addition, at least two alignment marks 52 may be provided. As described later, for example, when the anisotropic conductive member 15 is provided in the element region 50, in order to easily identify the alignment mark 52, the alignment mark 52 is preferably provided outside the element region 50.

FIG. 17 is a schematic diagram showing an example of an alignment mark of a first semiconductor wafer used in a bonded body according to an embodiment of the present invention.
As shown in FIG. 17, the first semiconductor wafer 60 includes a plurality of element regions 62. The four corners of the element region 62 are provided with alignment marks 64, respectively. A total of four alignment marks 64 are provided in the element region 62. The element region 62 is a region where the semiconductor element 14 is bonded. The element region 50 of the semiconductor element 14 is bonded to the element region 62 to constitute the multilayer device 10. The alignment mark 64 has the same structure as the alignment mark 52 described above. It is sufficient to provide at least two alignment marks 64.

18 to 21 are schematic views showing a third example of a method of manufacturing a multilayer device as an example of a bonded body according to an embodiment of the present invention. In FIGS. 18 to 21, the same reference numerals are given to the same structures as those of the multilayer device 10 and the semiconductor elements 12 and 14 shown in FIGS. 1 to 6, and detailed descriptions thereof are omitted.
The alignment of the first semiconductor wafer 60 and the semiconductor element 14 is performed using the alignment mark 64 (see FIG. 17) of the first semiconductor wafer 60 and the alignment mark 52 (see FIG. 16) of the semiconductor element 14.
Regarding the alignment using the alignment mark, for example, the alignment mark 64 (see FIG. 17) of the first semiconductor wafer 60 and the alignment mark 52 (see FIG. 16) of the semiconductor element 14 are captured at the same time, based on the first semiconductor wafer. An image of the alignment mark 64 (see FIG. 17) of 60 and an image of the alignment mark 52 (see FIG. 16) of the semiconductor element 14, and the alignment mark 64 (see FIG. 17) of the first semiconductor wafer 60 is obtained. And the position information of the alignment mark 52 (see FIG. 16) of the semiconductor element 14 for alignment.
Regarding the alignment, the image or reflection image of the alignment mark 64 (see FIG. 17) of the first semiconductor wafer 60 and the image or reflection image of the alignment mark 52 (see FIG. 16) of the semiconductor element 14 can be used. The structure of the digital image data is not particularly limited, and a known imaging device can be appropriately used.

As shown in FIG. 18, after the first semiconductor wafer 60 and the semiconductor element 14 are aligned, a temporary fixing member 13 is provided between the first semiconductor wafer 60 and the semiconductor element 14, for example, a surface 60 a of the first semiconductor wafer 60.
The temporary fixing member 13 may be provided in each semiconductor element 14, but is not limited thereto. For example, the temporary fixing member 13 may be provided on the entire surface 60 a of the first semiconductor wafer 60.

As shown in FIG. 19, the semiconductor element 14 is brought into close contact with the surface 60a of the first semiconductor wafer 60, and all of the semiconductor elements are aligned with the temporary fixing member 13 while the first semiconductor wafer 60 and the semiconductor element 14 are aligned. 14 Perform temporary fixation. The temporarily fixed state is the laminated body 19.
Next, the temporary fixing member 13 is removed. The method of removing the temporary fixing member 13 will be described later.
Next, the temporary fixing member 13 does not exist, and all the semiconductor elements 14 are bonded to the first semiconductor wafer 60 together in a temporarily fixed state, for example, under a predetermined bonding condition. Thereby, the element region 50 (see FIG. 16) of the semiconductor element 14 and the element region (not shown) of the first semiconductor wafer 60 are joined, and the semiconductor element 14 and the first semiconductor wafer 60 are in a state of ensuring electrical conduction with each other. As shown in FIG. 20, a bonded body 17 of the semiconductor element 14 and the first semiconductor wafer 60 is configured.

Next, for example, by dicing or laser scribing, the first semiconductor wafer 60 bonded to the semiconductor element 14 shown in FIG. 20 is sliced for each element region as shown in FIG. 21. Thereby, the laminated device 10 which joins the semiconductor element 12 and the semiconductor element 14 can be obtained.
The slicing is not limited to cutting, and laser scribing may be used.
In the step of bonding the semiconductor element 12 to the first semiconductor wafer 60, a plurality of semiconductor elements 14 are temporarily fixed and then all are bonded together, but the invention is not limited to this, and the semiconductor elements 14 may be individually bonded to the first semiconductor crystal one by one. Circle 60 joins.
Conveyance, selection, and the like of the semiconductor element 14 and the first semiconductor wafer 60 as well as temporary fixation and formal bonding can be achieved by using a known semiconductor manufacturing apparatus.

In addition, joining together as described above can reduce the tact time and improve productivity.
The bonding method is not particularly limited to the above method, and DBI (Direct Bond Interconnect) and SAB (Surface Activated Bond) can be used.
In the above-mentioned DBI, a silicon oxide film is laminated on the semiconductor element 14 and the first semiconductor wafer 60, and chemical mechanical polishing is performed. Thereafter, the silicon oxide film interface is activated by a plasma treatment, and the semiconductor element 14 and the first semiconductor wafer 60 are brought into contact with each other to bond the two.
In the SAB described above, the bonding surfaces of the semiconductor element 14 and the first semiconductor wafer 60 are surface-treated in a vacuum to be activated. In this state, the semiconductor element 14 and the first semiconductor wafer 60 are brought into contact with each other in a normal temperature environment to bond the two. In the surface treatment, ion irradiation with an inert gas such as argon or neutral atom beam irradiation is used.
During temporary fixing, the first semiconductor wafer 60 and the semiconductor element 14 are inspected to separate the good and the defective products in advance, and only the good of the semiconductor element 14 is bonded to the good part of the first semiconductor wafer 60, thereby reducing the Manufacturing losses. The semiconductor device with good quality is called KGD (Known Good Die).

In addition, the timing of the provision of the temporary fixing member 13 is explained after the alignment of the first semiconductor wafer 60 and the semiconductor element 14, but as long as the temporary fixing member 13 does not hinder the detection of the alignment mark, the alignment may be performed. The temporary fixing member 13 is previously provided. In the manufacturing method of the multilayer device 10 described below, the timing of setting the temporary fixing member 13 may be before or after the alignment.
In addition, as a method of providing the temporary fixing member 13, the temporary fixing member 13 can be provided at a predetermined position, but the method is not particularly limited. For example, if the temporary fixing member 13 is liquid or fixed, the temporary fixing member 13 is supplied at a predetermined place in the atmospheric environment. In order to improve productivity, considering the ease of supply of the temporary fixing member 13, it is preferable that the temporary fixing member 13 is a liquid at a temperature of 23 ° C.

In addition, as described above, the multilayer device 10 has a structure including three semiconductor elements 12, 14, and 16. In this case, the semiconductor element 14 is configured to have a terminal (not shown) and an alignment mark (not shown) on the back surface 14b. The semiconductor element 16 bonded to the semiconductor element 14 has a structure having an element region (not shown) and an alignment mark (not shown) on the surface 16 a.
22 to 25 are schematic views showing a fourth example of a method of manufacturing a multilayer device, which is an example of a bonded body according to an embodiment of the present invention in steps. In FIGS. 22 to 25, the same components as those in FIGS. 18 to 21 are denoted by the same reference numerals, and detailed descriptions thereof are omitted.

As shown in FIG. 19, in a state where all the semiconductor elements 14 are temporarily fixed to the element region of the first semiconductor wafer 60, as shown in FIG. 22, an alignment mark (not shown) on the back surface 14b of the semiconductor element 14 is used. And an alignment mark (not shown) of the semiconductor element 16 with respect to the semiconductor element 14. A temporary fixing member 13 is disposed between the semiconductor element 14 and the semiconductor element 16, for example, the back surface 14 b of the semiconductor element 14. The semiconductor element 16 and the semiconductor element 14 are brought into close contact with each other, and the semiconductor element 14 and the semiconductor element 16 are temporarily fixed by a temporary fixing member 13. Thereby, the first semiconductor wafer 60, the semiconductor element 14, and the semiconductor element 16 are temporarily fixed by the temporary fixing member 13 while being aligned. This temporarily fixed state is a laminated body (not shown).
Next, the temporary fixing member 13 is removed. The method of removing the temporary fixing member 13 will be described later. The temporary fixing using the temporary fixing member 13 is not limited to the state shown in FIG. 19.

For example, the first semiconductor wafer 60, the semiconductor element 14, and the semiconductor element 16 are prepared, and as shown in FIG. 23, the alignment of the first semiconductor wafer 60, the semiconductor element 14, and the semiconductor element 16 is performed using an alignment mark. After the alignment, a temporary fixing member 13 is provided between the first semiconductor wafer 60 and the semiconductor element 14, for example, the surface 60 a of the first semiconductor wafer 60. A temporary fixing member 13 is provided between the semiconductor element 14 and the semiconductor element 16, for example, the back surface 14 b of the semiconductor element 14.
For example, the first semiconductor wafer 60 is brought into close contact with the semiconductor element 14 and the semiconductor element 16, and is temporarily fixed by the temporary fixing member 13 while the first semiconductor wafer 60, the semiconductor element 14, and the semiconductor element 16 are aligned.

As described above, after the temporary fixing member 13 is removed, the first semiconductor wafer 60, the semiconductor element 14, and the semiconductor element 16 are bonded in a state where they are aligned and temporarily fixed. Thereby, the first semiconductor wafer 60, the semiconductor element 14, and the semiconductor element 16 are in a state of ensuring electrical conduction with each other. As shown in FIG. 24, the joint body 17 of the first semiconductor wafer 60, the semiconductor element 14, and the semiconductor element 16 is configured. .
Next, for example, by dicing or laser scribing, as shown in FIG. 25, the first semiconductor wafer 60 shown in FIG. 24 to which the semiconductor element 14 and the semiconductor element 16 are bonded is sliced for each element region. Thereby, the laminated device 10 which joins the semiconductor element 12 and the semiconductor element 14 can be obtained. The slicing can use the above.

Next, a manufacturing method of the multilayer device 10 using the anisotropic conductive member 15 based on Chip-on-Wafer will be described.
The manufacturing method of the multilayer device 10 using the anisotropic conductive member 15 uses the semiconductor element 14 shown in FIG. 26, for example.
FIG. 26 is a schematic perspective view showing another example of an alignment mark of a semiconductor element used in a bonded body according to an embodiment of the present invention.
In the semiconductor element 14 shown in FIG. 26, an anisotropic conductive member 15 is provided on an element region (not shown) of the surface 14a. Similarly to the semiconductor element 14 shown in FIG. 16, on the surface 14 a of the semiconductor element 14, alignment marks 52 are provided at four corners, and a total of four alignment marks 52 are provided. It is sufficient to provide at least two alignment marks 52. Further, a terminal 30 shown in FIG. 3 is provided on the surface 14a.

27 to 30 are schematic views showing a fifth example of a method of manufacturing a multilayer device as an example of a bonded body according to an embodiment of the present invention. In FIGS. 27 to 30, the same reference numerals are given to the same structures as those in FIGS. 18 to 21, and detailed descriptions thereof are omitted.
Compared with the third example of the method of manufacturing the multilayer device 10 shown in FIGS. 18 to 21 described above, the difference is that the fifth example of the method of manufacturing the multilayer device 10 using the anisotropic conductive member 15 is in the semiconductor element 14 The steps other than the step of providing the anisotropic conductive member 15 are the same as those of the method of manufacturing the multilayer device 10 using the anisotropic conductive member 15.

As shown in FIG. 27, a semiconductor element 14 is arranged on the surface 60a of the first semiconductor wafer 60 toward the anisotropic conductive member 15, and alignment is performed using an alignment mark. In this state, the temporary fixing member 13 is provided on the first The surface 60 a of the semiconductor wafer 60. The temporary fixing member 13 may be provided on the entire surface 60 a of the first semiconductor wafer 60 as described above.
Next, as shown in FIG. 28, the first semiconductor wafer 60 and the semiconductor element 14 provided with the anisotropic conductive member 15 are aligned, and temporarily fixed by the temporary fixing member 13. This temporarily fixed state is a laminated body (not shown).

Next, the temporary fixing member 13 is removed. The method of removing the temporary fixing member 13 will be described later.
Next, the first semiconductor wafer 60 and the semiconductor element 14 are bonded via the anisotropic conductive member 15 under a predetermined bonding condition in a state where the temporary fixing member 13 is not present. Thereby, the semiconductor element 14, the anisotropic conductive member 15, and the first semiconductor wafer 60 are in a state of ensuring electrical conduction with each other. As shown in FIG. 29, the semiconductor element 14, the anisotropic conductive member 15, and the first semiconductor wafer are constituted. Bonded body 17 of semiconductor wafer 60. In this case, since the bonding is performed in a state where the temporary fixing member 13 is not present, there is no resistance to the conductor and the resistance becomes small.
Next, for example, by dicing or laser scribing, as shown in FIG. 30, the first semiconductor wafer 60 to which the semiconductor element 14 and the anisotropic conductive member 15 are bonded as shown in FIG. Slicing. Thereby, the laminated device 10 which joined the semiconductor element 12, the anisotropic conductive member 15, and the semiconductor element 14 can be obtained. The slicing can use the above.

In addition, in the step of bonding the semiconductor element 12 to the element region, a plurality of semiconductor elements 14 are temporarily fixed and then all are bonded together, but it is not limited to this, and the semiconductor elements 14 may be individually connected to the elements of the first semiconductor wafer 60 one by one. Area junction. By joining together as described above, the cycle time can be reduced, and productivity can be improved.

Further, as shown in FIG. 27, the semiconductor element 14 and the first semiconductor wafer 60 provided with the anisotropic conductive member 15 are not limited to use, and the first semiconductor wafer 60 and the anisotropic conductive member 15 are used. A temporary fixing member 13 is provided in between, and the semiconductor element 14 may have a structure in which the anisotropic conductive member 15 is not provided.
FIG. 31 is a schematic diagram showing one step of a first modification of the fifth example of the method for manufacturing a laminated device as an example of a bonded body according to an embodiment of the present invention, and FIG. 32 is a diagram showing an example of a bonded body according to an embodiment of the present invention It is a schematic diagram of one step of the 2nd modification of the 5th example of the manufacturing method of a laminated device. In FIGS. 31 and 32, the same components as those of the temporary fixing member 13, the semiconductor element 14, the anisotropic conductive member 15, and the first semiconductor wafer 60 shown in FIGS. 26 to 30 are denoted by the same reference numerals, and are omitted. A detailed description of it.

As shown in FIG. 31, the semiconductor element 14 and the anisotropic conductive member 15 are provided separately. The anisotropic conductive member 15 is interposed and the semiconductor element 14 and the first semiconductor wafer 60 are opposed to each other. A temporary fixing member 13 is disposed between the semiconductor element 14 and the anisotropic conductive member 15, and a temporary fixing member 13 is disposed before the anisotropic conductive member 15 and the first semiconductor wafer 60. At this time, the semiconductor element 14, the anisotropic conductive member 15, and the first semiconductor wafer 60 are aligned.
In this case, the first semiconductor wafer 60, the anisotropic conductive member 15 and the semiconductor element 14 are then temporarily fixed by the temporary fixing member 13 while being aligned. This temporarily fixed state is a laminated body (not shown). As described above, the temporary fixing member 13 is removed. Next, the first semiconductor wafer 60 and the semiconductor element 14 are bonded via the anisotropic conductive member 15 under a predetermined bonding condition in a state where the temporary fixing member 13 is not present. As shown in FIG. 29 described above, the bonded body 17 of the semiconductor element 14, the anisotropic conductive member 15, and the first semiconductor wafer 60 is configured. Next, as shown in FIG. 30, by slicing, a laminated device 10 in which the semiconductor element 12, the anisotropic conductive member 15, and the semiconductor element 14 are bonded can be obtained.

The anisotropic conductive member 15 is sandwiched, the semiconductor element 14 and the first semiconductor wafer 60 are opposed to each other, and after being aligned, a temporary fixing member 13 is disposed between the semiconductor element 14 and the anisotropic conductive member 15, A temporary fixing member 13 is disposed between the anisotropic conductive member 15 and the first semiconductor wafer 60. At this time, as shown in FIG. 32, the temporary fixing member 13 may be provided on the entire surface 60 a of the first semiconductor wafer 60. In this case, as described above, the temporary fixing member 13 is removed after being temporarily fixed by the temporary fixing member 13 in the aligned state. Next, the first semiconductor wafer 60 and the semiconductor element 14 are bonded via the anisotropic conductive member 15 under a predetermined bonding condition in a state where the temporary fixing member 13 is not present. As shown in FIG. 29 described above, the bonded body 17 of the semiconductor element 14, the anisotropic conductive member 15, and the first semiconductor wafer 60 is configured. Next, as shown in FIG. 30, by slicing, a laminated device 10 in which the semiconductor element 12, the anisotropic conductive member 15, and the semiconductor element 14 are bonded can be obtained.

As described above, when the multilayer device 10 having a structure of three semiconductor elements 12, 14, 16 is manufactured, as described above, the semiconductor element 14 is provided with a terminal (not shown) and an alignment mark (not shown) on the back surface 14b. (Not shown). The semiconductor element 16 bonded to the semiconductor element 14 has a structure having an element region (not shown) and an alignment mark (not shown) on the surface 16 a. The semiconductor element 16 is provided with an anisotropic conductive member 15 in advance similarly to the semiconductor element 14.
33 to 36 are schematic diagrams showing a sixth example of a method of manufacturing a multilayer device as an example of a bonded body according to an embodiment of the present invention. In FIGS. 33 to 36, the same reference numerals are given to the same structures as those in FIGS. 22 to 25, and detailed descriptions thereof are omitted.

As shown in FIG. 28, in a state where all the semiconductor elements 14 and the element regions of the first semiconductor wafer 60 are temporarily fixed, as shown in FIG. 33, an alignment mark (not shown) on the back surface 14b of the semiconductor element 14 is used. And an alignment mark (not shown) of the semiconductor element 16 with respect to the semiconductor element 14. A temporary fixing member 13 is arranged on the back surface 14 b of the semiconductor element 14. The semiconductor element 16 is brought into close contact with the semiconductor element 14, and the semiconductor element 14 and the semiconductor element 16 provided with the anisotropic conductive member 15 are temporarily fixed by a temporary fixing member 13. Thereby, in a state where the first semiconductor wafer 60, the semiconductor element 14 provided with the anisotropic conductive member 15 and the semiconductor element 16 provided with the anisotropic conductive member 15 are aligned, the temporary fixing member 13 is temporarily used. fixed. This temporarily fixed state is a laminated body (not shown).
Next, the temporary fixing member 13 is removed. The method of removing the temporary fixing member 13 will be described later. The temporary fixing using the temporary fixing member 13 is not limited to the state shown in FIG. 29.

For example, as shown in FIG. 34, the first semiconductor wafer 60, the semiconductor element 14 provided with the anisotropic conductive member 15, and the semiconductor element 16 provided with the anisotropic conductive member 15 are prepared. 1 Alignment of the semiconductor wafer 60, the semiconductor element 14, and the semiconductor element 16. After the alignment, a temporary fixing member 13 is provided between the first semiconductor wafer 60 and the semiconductor element 14 on which the anisotropic conductive member 15 is provided, for example, on the surface 60 a of the first semiconductor wafer 60. A temporary fixing member 13 is provided between the semiconductor element 14 provided with the anisotropic conductive member 15 and the semiconductor element 16 provided with the anisotropic conductive member 15, for example, on the back surface 14 b of the semiconductor element 14.
For example, the semiconductor element 14 provided with the anisotropic conductive member 15 and the semiconductor element 16 provided with the anisotropic conductive member 15 are brought into contact with each other near the first semiconductor wafer 60 and aligned with the first semiconductor wafer 60, The semiconductor element 14 provided with the anisotropic conductive member 15 and the semiconductor element 16 provided with the anisotropic conductive member 15 are temporarily fixed by the temporary fixing member 13 in a state.

As described above, after the temporary fixing member 13 is removed, the first semiconductor wafer 60, the semiconductor element 14 provided with the anisotropic conductive member 15 and the semiconductor element 16 provided with the anisotropic conductive member 15 are temporarily aligned. Join in a fixed state. Thereby, the first semiconductor wafer 60, the anisotropic conductive member 15, the semiconductor element 14, the anisotropic conductive member 15, and the semiconductor element 16 are in a state of ensuring electrical conduction with each other, as shown in FIG. 35, constituting the first The semiconductor wafer 60, the anisotropic conductive member 15, the semiconductor element 14, the anisotropic conductive member 15, and the bonded body 17 of the semiconductor element 16.
Next, for example, by dicing or laser scribing, as shown in FIG. 36, the first semiconductor wafer 60 shown in FIG. 35 to which the semiconductor element 14 and the semiconductor element 16 are bonded is sliced for each element region. Thereby, the laminated device 10 which joins the semiconductor element 12 and the semiconductor element 14 can be obtained. The slicing can use the above.

As shown in FIG. 34, the use of the semiconductor element 14 and the first semiconductor wafer 60 provided with the anisotropic conductive member 15 is not limited to the provision of a temporary space between the anisotropic conductive member 15 and the semiconductor element 14. The fixing member 13 is provided with a temporary fixing member 13 between the first semiconductor wafer 60 and the anisotropic conductive member 15. The semiconductor element 14 may have a structure in which the anisotropic conductive member 15 is not provided.
FIG. 37 is a schematic diagram showing one step of a first modification of the sixth example of the method of manufacturing a laminated device as an example of a bonded body according to an embodiment of the present invention, and FIG. 38 is a diagram showing an example of a bonded body according to an embodiment of the present invention. It is a schematic diagram of one step of the 2nd modification of the 6th example of the manufacturing method of a laminated device. In FIGS. 37 and 38, the same structures as those of the temporary fixing member 13, the semiconductor element 14, the anisotropic conductive member 15, the semiconductor element 16, and the first semiconductor wafer 60 shown in FIGS. 31 to 36 are denoted by the same Symbols and detailed descriptions thereof are omitted.

As shown in FIG. 37, the semiconductor element 14 and the anisotropic conductive member 15 are provided separately. The semiconductor element 14 and the first semiconductor wafer 60 are disposed to face each other with the anisotropic conductive member 15 interposed therebetween, and the anisotropic conductive member 15, the semiconductor element 14, and the semiconductor element 16 are disposed to face each other.
Temporary arrangements are respectively provided between the semiconductor element 16 and the anisotropic conductive member 15, between the semiconductor element 14 and the anisotropic conductive member 15, and between the anisotropic conductive member 15 and the first semiconductor wafer 60. Fixed member 13. At this time, the first semiconductor wafer 60, the anisotropic conductive member 15, the semiconductor element 14, the anisotropic conductive member 15, and the semiconductor element 16 are aligned.
In this case, the first semiconductor wafer 60, the anisotropic conductive member 15, the semiconductor element 14, the anisotropic conductive member 15, and the semiconductor element 16 are then temporarily aligned by the temporary fixing member 13 while being aligned. fixed. This temporarily fixed state is a laminated body (not shown). As described above, the temporary fixing member 13 is removed. Next, the first semiconductor wafer 60, the semiconductor element 14, and the semiconductor element 16 are bonded through the anisotropic conductive member 15 under a predetermined bonding condition in a state where the temporary fixing member 13 is not present. As shown in FIG. 35 described above, the semiconductor element 16, the anisotropic conductive member 15, the semiconductor element 14, the anisotropic conductive member 15, and the bonded body 17 of the first semiconductor wafer 60 are configured. Next, as shown in FIG. 36, by slicing, a laminated device 10 in which the semiconductor element 12, the anisotropic conductive member 15, the semiconductor element 14, the anisotropic conductive member 15 and the semiconductor element 16 are bonded can be obtained.

The semiconductor element 14 and the first semiconductor wafer 60 are disposed to face each other with the anisotropic conductive member 15 interposed therebetween, and the semiconductor element 14 and the semiconductor element 16 are disposed to face each other with the anisotropic conductive member 15 interposed and aligned. Next, between the semiconductor element 16 and the anisotropic conductive member 15, between the semiconductor element 14 and the anisotropic conductive member 15, between the anisotropic conductive member 15 and the first semiconductor wafer 60, respectively. Configure the temporary fixing member 13. At this time, as shown in FIG. 38, the temporary fixing member 13 may be provided on the entire surface 60 a of the first semiconductor wafer 60. In this case, as described above, the temporary fixing member 13 is removed after being temporarily fixed by the temporary fixing member 13 in the aligned state. Next, the first semiconductor wafer 60, the semiconductor element 14, and the semiconductor element 16 are bonded through the anisotropic conductive member 15 under a predetermined bonding condition in a state where the temporary fixing member 13 is not present. As shown in FIG. 35 described above, the semiconductor element 16, the anisotropic conductive member 15, the semiconductor element 14, the anisotropic conductive member 15, and the bonded body 17 of the first semiconductor wafer 60 are configured. Next, as shown in FIG. 36, by slicing, a laminated device 10 in which the semiconductor element 12, the anisotropic conductive member 15, the semiconductor element 14, the anisotropic conductive member 15, and the semiconductor element 16 are bonded can be obtained.

Next, a manufacturing method of the Wafer-on-Wafer multilayer device 10 will be described.
39 to 41 are schematic views showing a seventh example of a method of manufacturing a multilayer device as an example of a bonded body according to an embodiment of the present invention. In FIGS. 39 to 41, the same components as those in FIGS. 18 to 21 are denoted by the same reference numerals, and detailed descriptions thereof are omitted.

The seventh example of the manufacturing method of the multilayer device is a manufacturing method of the multilayer device 10 shown in FIG.
The seventh example of the method of manufacturing the multilayer device 10 is the same as the third example of the method of manufacturing the multilayer device 10 shown in FIGS. 18 to 21 except that a second semiconductor wafer 70 is used instead of the semiconductor element 14. Therefore, a detailed description of the manufacturing method common to the first example of the manufacturing method of the multilayer device is omitted.

First, a first semiconductor wafer 60 and a second semiconductor wafer 70 including a plurality of element regions (not shown) and alignment marks (not shown) are prepared. The element region is provided on a surface 70 a of the second semiconductor wafer 70.
Next, as shown in FIG. 39, the surface 60a of the first semiconductor wafer 60 and the surface 70a of the second semiconductor wafer 70 are opposed to each other. Then, using the alignment mark of the first semiconductor wafer 60 and the alignment mark of the second semiconductor wafer 70, the second semiconductor wafer 70 is aligned with respect to the first semiconductor wafer 60.
Next, a temporary fixing member 13 is arranged between the first semiconductor wafer 60 and the second semiconductor wafer 70, for example, on the surface 60 a of the first semiconductor wafer 60.
Next, the first semiconductor wafer 60 and the second semiconductor wafer 70 are aligned and temporarily fixed by a temporary fixing member 13 in a state of being aligned.

Next, the temporary fixing member 13 is removed. The method of removing the temporary fixing member 13 will be described later.
Next, the first semiconductor wafer 60 and the second semiconductor wafer 70 are bonded under a predetermined bonding condition in a state where the temporary fixing member 13 does not exist. Thereby, the first semiconductor wafer 60 and the second semiconductor wafer 70 are in a state of ensuring electrical conduction with each other, and a joint body 17 of the first semiconductor wafer 60 and the second semiconductor wafer 70 shown in FIG. 40 is configured. In this case, since the bonding is performed in a state where the temporary fixing member 13 is not present, there is no resistance to the conductor and the resistance becomes small.

Next, as shown in FIG. 40, in a state where the first semiconductor wafer 60 and the second semiconductor wafer 70 are bonded, for example, dicing is performed for each element region by dicing or laser scribing. Thereby, as shown in FIG. 41, the laminated device 10 which joins the semiconductor element 12 and the semiconductor element 14 can be obtained. As described above, the laminated device 10 can also be obtained using Wafer-on-Wafer. The slicing can use the above.
As shown in FIG. 40, in a state where the first semiconductor wafer 60 and the second semiconductor wafer 70 are bonded, if the first semiconductor wafer 60 and the second semiconductor wafer 70 have a semiconductor wafer to be thinned, , It can be thinned by chemical mechanical polishing (CMP).

In the seventh example of the method of manufacturing a multilayer device, the two-layer structure of the base semiconductor element 12 and the semiconductor element 14 is described as an example, but it is not limited to this, and it may of course be three or more layers. In this case, an alignment mark (not shown) and an element region (not shown) are provided on the back surface 70 b of the second semiconductor wafer 70. A terminal (not shown) on the back surface 70b is electrically connected to the element region of the front surface 70a. By setting the second semiconductor wafer 70 as described above, after the third semiconductor wafer (not shown) is aligned, between the second semiconductor wafer 70 and the third semiconductor wafer, for example, the second semiconductor wafer The back surface 70b of 70 is provided with a temporary fixing member 13, and is temporarily fixed using the temporary fixing member 13. In addition, by bonding the third semiconductor wafer by removing the temporary fixing member 13, the multilayer device 10 having three or more layers can be obtained.

Next, a method for manufacturing a multilayer device 10 having an anisotropic conductive member 15 based on Wafer-on-Wafer will be described.
42 to 44 are schematic diagrams showing an eighth example of a method of manufacturing a laminated device as an example of a bonded body according to an embodiment of the present invention. In FIGS. 42 to 44, the same components as those in FIGS. 39 to 41 are denoted by the same reference numerals, and detailed descriptions thereof are omitted.
An eighth example of the manufacturing method of the multilayer device is a manufacturing method of the multilayer device 10 shown in FIG.
Compared with the seventh example of the method of manufacturing the multilayer device 10 shown in FIGS. 39 to 41, in the eighth example of the method of manufacturing the multilayer device, the first semiconductor wafer 60 and the first semiconductor wafer 60 are bonded to each other via the anisotropic conductive member 15. Except for this, the second semiconductor wafer 70 is the same as the seventh example of the manufacturing method of the multilayer device. Therefore, a detailed description of the manufacturing method common to the third example of the manufacturing method of the multilayer device is omitted. The anisotropic conductive member 15 is as described above, and therefore detailed description thereof is omitted.

First, as in the seventh example of the method of manufacturing the multilayer device 10, a first semiconductor wafer 60 and a second semiconductor wafer 70 including a plurality of element regions (not shown) and alignment marks (not shown) are prepared. . The anisotropic conductive member 15 may be provided on either the surface 60 a of the first semiconductor wafer 60 or the surface 70 a of the second semiconductor wafer 70. However, in FIG. 42, the surface of the second semiconductor wafer 70 is provided. 70a is provided with an anisotropic conductive member 15.
Next, as shown in FIG. 42, the surface 60 a of the first semiconductor wafer 60 and the surface 70 a of the second semiconductor wafer 70 are opposed to each other. Then, using the alignment mark of the first semiconductor wafer 60 and the alignment mark of the second semiconductor wafer 70, the second semiconductor wafer 70 is aligned with respect to the first semiconductor wafer 60.
Next, a temporary fixing member 13 is arranged between the first semiconductor wafer 60 and the second semiconductor wafer 70, for example, on the surface 60 a of the first semiconductor wafer 60.
Next, the first semiconductor wafer 60 and the second semiconductor wafer 70 provided with the anisotropic conductive member 15 are temporarily fixed by the temporary fixing member 13 while being aligned.

Next, the temporary fixing member 13 is removed. The method of removing the temporary fixing member 13 will be described later.
Next, the first semiconductor wafer 60, the anisotropic conductive member 15, and the second semiconductor wafer 70 are bonded under a predetermined bonding condition in a state where the temporary fixing member 13 does not exist. Thereby, the first semiconductor wafer 60, the anisotropic conductive member 15, and the second semiconductor wafer 70 are in a state of ensuring electrical conduction with each other, and the first semiconductor wafer 60 and the anisotropic conductivity shown in FIG. 43 are configured. The member 15 and the bonded body 17 of the second semiconductor wafer 70. In this case, since the bonding is performed in a state where the temporary fixing member 13 is not present, there is no resistance to the conductor and the resistance becomes small.

Next, as shown in FIG. 44, in a state where the first semiconductor wafer 60 and the second semiconductor wafer 70 provided with the anisotropic conductive member 15 are bonded, for example, by cutting or laser scribing, the The component area is sliced. Thereby, the laminated device 10 in which the semiconductor element 12 and the semiconductor element 14 are joined via the anisotropic conductive member 15 shown in FIG. 44 can be obtained. As described above, the laminated device 10 can also be obtained using Wafer-on-Wafer. The slicing can use the above.
As shown in FIG. 44, in a state where the first semiconductor wafer 60 and the second semiconductor wafer 70 are bonded, if there is a semiconductor crystal to be thinned among the first semiconductor wafer 60 and the second semiconductor wafer 70. If it is round, it can be thinned by chemical mechanical polishing (CMP).

In the eighth example of the method for manufacturing a laminated device, the two-layer structure of the laminated semiconductor element 12 and the semiconductor element 14 has been described as an example, but it is not limited thereto, and as described above, it may of course be three or more layers. In this case, an alignment mark (not shown) and an element region (not shown) are provided on the back surface 70 b of the second semiconductor wafer 70. A terminal (not shown) on the back surface 70b is electrically connected to the element region of the front surface 70a. By setting the second semiconductor wafer 70 as described above, after the third semiconductor wafer (not shown) is aligned, between the second semiconductor wafer 70 and the third semiconductor wafer, for example, the second semiconductor wafer The back surface 70b of 70 is provided with a temporary fixing member 13, and is temporarily fixed using the temporary fixing member 13. In addition, by bonding the third semiconductor wafer by removing the temporary fixing member 13, the multilayer device 10 having three or more layers can be obtained.

As described above, by temporarily fixing using the temporarily fixed member 13 that is finally removed, it is possible to prevent poor joining due to the temporarily fixed member 13.
In addition, as described above, with the multilayer device 10 having the structure in which the anisotropic conductive member 15 is provided, even if there is unevenness in the semiconductor element, the unevenness can be absorbed by using the protruding portion 42a and the protruding portion 42b as a buffer layer. . Since the protruding portion 42a and the protruding portion 42b function as a buffer layer, a surface having an element region in a semiconductor element does not need a high surface quality. Therefore, smoothing processing such as grinding is not required, production costs can be suppressed, and production time can be shortened.
In addition, since the multilayer device 10 can be manufactured using Chip-on-Wafer, only good products of a semiconductor wafer are bonded to good products in the semiconductor wafer, thereby maintaining yield and reducing manufacturing losses.

Next, the semiconductor element 14 provided with the anisotropic conductive member 15 is demonstrated.
The semiconductor element 14 provided with the anisotropic conductive member 15 can use the anisotropic conductive member 15 of the anisotropic conductive material 49 shown in FIG. 15 and a semiconductor wafer having a plurality of element regions (not shown). To form. As described above, the element region is provided with an alignment mark (not shown) and a terminal (not shown) for alignment. In the anisotropic conductive material 49, the anisotropic conductive member 15 is formed in a pattern aligned with the element region.

First, a predetermined pressure is applied, heating is performed to a predetermined temperature, and the predetermined time is maintained to join the anisotropic conductive member 15 of the anisotropic conductive material 49 to a device region of a semiconductor wafer.
Next, the support body 47 of the anisotropic conductive material 49 is removed, and only the anisotropic conductive member 15 is bonded to the semiconductor wafer. In this case, the anisotropic conductive material 49 is heated to a predetermined temperature, the adhesive force of the release agent 46 of the release layer 44 is reduced, and the support 47 is removed using the release layer 44 of the anisotropic conductive material 49 as a starting point. Next, the semiconductor wafer is sliced for each element region to obtain a plurality of semiconductor elements 14.
Although the semiconductor element 14 provided with the anisotropic conductive member 15 has been described as an example, the semiconductor device 16 provided with the anisotropic conductive member 15 and the second semiconductor device 16 provided with the anisotropic conductive member 15 are described. The semiconductor wafer 70 can be provided with the anisotropic conductive member 15 similarly to the semiconductor element 14 provided with the anisotropic conductive member 15.
The semiconductor element 14 provided with the anisotropic conductive member 15 in advance, the first semiconductor wafer 60 provided with the anisotropic conductive member 15 in advance, and the second semiconductor crystal provided with the anisotropic conductive member 15 in advance The circle 70 is not limited to this, and the anisotropic conductive member 15 can be separately arranged to manufacture the multilayer device 10.

Hereinafter, the manufacturing method of a bonded body is demonstrated more concretely.
[Provisional Fixing Step]
Temporary fixation in the temporary fixation step refers to fixing to the joined object in a state of being aligned with the joined object. Temporary fixation keeps alignment, but not permanent fixation. For temporary fixing, a temporary fixing member is used, and the surface tension of the temporary fixing member is used to temporarily fix at least two conductive members to each other.
In the temporary fixing step, at least two conductive members are brought into close contact with each other, thereby being implemented. In this case, the pressing condition of the conductive member is not particularly limited, but is preferably 10 MPa or less, more preferably 5 MPa or less, and particularly preferably 1 MPa.
Similarly, the temperature conditions in the temporary fixing step are not particularly limited, but 0 ° C to 300 ° C is preferred, 10 ° C to 200 ° C is more preferred, and normal temperature (23 ° C) to 100 ° C is particularly preferred. When the temperature of the temporary fixing step is higher than the boiling point of the temporary fixing member, the temporary fixing member is removed in the temporary fixing step, and the temporary fixing step and the removing step are performed at the same time.
For example, in the temporary fixing step of temporarily fixing the respective semiconductor elements including the semiconductor element 14, the semiconductor element 16, and the first semiconductor wafer 60, Toray Engineering Co., Ltd., SHIBUYA KOGYO CO., LTD., Devices from companies such as SHINKAWA LTD. And Yamaha Motor Co., Ltd.

[Temporary fixing member]
The temporary fixing member is a person who uses a surface tension to temporarily fix at least two conductive members to each other, and is a final remover. Therefore, the temporary fixing member 13 does not exist in the bonded body such as the multilayer device 10. As described above, the temporary fixing member is the final remover. Therefore, when it is removed by vaporization, for example, it is preferable that no component remains.
The temporary fixing member is preferably a liquid at a temperature of 23 ° C. In this case, the boiling point of the liquid is preferably 50 ° C or higher and 250 ° C or lower. When the temporary fixing member is liquid or solid, it is not limited to a single composition, and may be a mixture.
A liquid system at a temperature of 23 ° C refers to a person who is based on physical property data.
Since the temporary fixing member is a liquid at a temperature of 23 ° C., it is easy to supply the temporary fixing member to a predetermined place under the atmospheric pressure, so it is preferable. However, as a device for supplying a temporary fixing member, a known one that supplies droplets can be used, and for example, the temporary fixing member can be supplied using an inkjet method. In the case of Wafer-on-Chip, by using multi-head inkjet, a temporary fixing member can be satisfactorily arranged in the element region on the surface of the semiconductor wafer.

When the temporary fixing member is a liquid at a temperature of 23 ° C., the electrical resistance after bonding is reduced. On the other hand, if the temporary fixing member is a solid at a temperature of 23 ° C., the electrical resistance after the joining is increased.
In addition, if the boiling point of the liquid is less than 50 ° C, it is possible to remove the temporary fixing member even in the removal step. When the boiling point of the liquid exceeds 250 ° C., the temporary fixing member is vaporized and removed. Therefore, a high temperature is required, and sometimes the joining step and the removing step cannot be performed simultaneously under the joining conditions. In addition, if the boiling point is high, the temporary fixing member tends to remain, and the electrical resistance after the joining is increased. Regarding the temporary fixing member, it is preferable to perform the joining step and the removal step at the same time. From the viewpoint of the electrical conductivity after joining, the temperature of the liquid is preferably 60 ° C or higher and 180 ° C or lower.

As the temporary fixing member, for example, acetone (boiling point 56 ° C), isopropanol (boiling point 82 ° C), ethyl lactate (boiling point 154 ° C), ethanol (boiling point 78 ° C), water (boiling point 100 ° C), propylene glycol monomethyl can be used. Ether acetate (boiling point 146 ° C), ethylene glycol (boiling point 197 ° C), diethylene glycol monobutyl ether acetate (boiling point 245 ° C), diethylene glycol dibutyl ether (boiling point 256 ° C), and Third butanol (boiling point 82 ° C).
In the example of the temporary fixing member described above, the third butanol is a solid at a temperature of 23 ° C, but other than that, it is a liquid at a temperature of 23 ° C.
In addition, in the case of a liquid at a temperature of 23 ° C, the boiling point is 250 ° C or lower, except for diethylene glycol dibutyl ether (boiling point: 256 ° C). In addition, the boiling points are all catalog values.

[Removal steps]
As described above, the temporary fixing member is preferably a liquid at a temperature of 23 ° C, and a boiling point of the liquid is preferably 50 ° C or higher and 250 ° C or lower.
The temporary fixing member 13 is a liquid. As a method for removing the temporary fixing member 13, a method of vaporizing the temporary fixing member 13 may be mentioned.
When the temporary fixing member is vaporized, for example, in a state where the semiconductor element 12 and the semiconductor element 14 are temporarily fixed by the temporary fixing member 13, the temporary fixing member 13 is disposed in a temperature environment of evaporation or a reduced pressure environment.
In the case where the temporary fixing member is disposed in a temperature environment in which evaporation is performed, and the bonding step in the subsequent step is performed in the case where the temperature fixing device in which the temporary fixing member is vaporized is implemented, the temporary fixing member is removed in the process of performing the bonding step. In this case, the removal step and the bonding step are performed simultaneously.
Moreover, when it arrange | positions in a pressure-reduced environment, and when the joining process of a subsequent step is implemented in a pressure-reduced environment, a temporary fixing member is removed in the process of performing a joining process. In this case, the removal step and the bonding step are performed simultaneously. As described above, the simultaneous execution of the removal step and the bonding step means that the two steps of the removal step and the bonding step are performed in the execution of one step.
By performing the removal step and the bonding step at the same time, the positional deviation can be more suppressed, and the alignment accuracy of the conductive member such as the semiconductor element 12 and the semiconductor element 14 can be further improved.
Moreover, by simultaneously performing the removal step and the bonding step, the manufacturing method can be simplified, the manufacturing equipment can be simplified, and the cycle time can be reduced.

As a method of removing the temporary fixing member 13, the temporary fixing member may be replaced with a gas or a filler. When the temporary fixing member is replaced with a gas, for example, in a state where the semiconductor element 12 and the semiconductor element 14 are temporarily fixed by the temporary fixing member 13, the temporary fixing member is placed in a decompressed environment and the temporary fixing member is discharged. Thereby, the temporary fixing member is replaced with a gas in a reduced pressure environment. If the gas system air in the reduced pressure environment is used, the temporary fixing member is replaced with air, and if the gas system air in the reduced pressure environment is replaced with an inert gas such as argon or nitrogen, the temporarily fixed member is replaced with an inert gas.
When the temporary fixing member 13 is replaced with a filler, when the temporary fixing member 13 is discharged, the filler is filled in place of the temporary fixing member, whereby the temporary fixing member can be replaced with a filler.
As the step of removing the temporary fixing member, at least one of the step of vaporizing the temporary fixing member, the step of replacing the temporary fixing member with a gas, or the step of replacing with a filler is sufficient.
The gas replacing the temporary fixing member 13 is, for example, air or an inert gas such as argon or nitrogen.
The filler for replacing the temporary fixing member 13 is, for example, NCP (Non Conductive Paste), or underfill. The filler will be described in detail below.

As the filler, those containing a polymer material, a hardener, and an inorganic filler can be used.
Examples of the polymer material include bisphenol A epoxy resin, bisphenol F epoxy resin, phenol novolac epoxy resin, alicyclic epoxy resin, siloxane epoxy resin, and epoxy resin. Xylylene type epoxy resin, propylene oxide (based) ester type epoxy resin, propylene oxide (based) amine type epoxy resin, hydantoin type epoxy resin and naphthalene ring-containing epoxy resin Epoxy. In the epoxy resin composition, the compounds exemplified herein may be used alone or as a mixture of two or more. (A) It is more preferable that it is 5-30 mass% with respect to the total weight of an epoxy resin composition, and it is further more preferable that it is 12-26 mass%.
Examples of the curing agent include a chain aliphatic amine, a cyclic aliphatic amine, a fatty aromatic amine, and an aromatic amine. In the epoxy resin composition, the compounds exemplified herein may be used alone or as a mixture of two or more. The amine group of the component (B) is preferably contained at a ratio of 0.7 to 1.5 equivalents with respect to 1 equivalent of the epoxy group of the component (A), and further preferably contained at a ratio of 0.8 to 1.2 equivalents.

Examples of the inorganic filler include silica, alumina, aluminum nitride, magnesium oxide, silicon nitride, zinc oxide, and boron nitride. Among them, silicon dioxide, aluminum oxide, and aluminum nitride are preferred. In the epoxy resin composition, the compounds exemplified herein may be used alone or as a mixture of two or more. (C) The component is more preferably contained in an amount of 40 to 85% by mass based on the total weight of the epoxy resin composition, and more preferably contained in an amount of 60 to 80% by mass. The material and content of the component (C) are adjusted to obtain a desired thermal conductivity (for example, 0.3 W / m ° C or higher, preferably 1.0 W / m ° C or higher, and more preferably 1.5 W / ° C or higher).
The filler may further include an alkylene oxide adduct, a silane coupling agent, and the like as additives.

＜ NCP ＞
NCP is an example of a filler that replaces the temporary fixing member 13.
The NCP system, for example, exhibits fluidity in a temperature range of 50 ° C to 200 ° C and is preferably hardened at 200 ° C or higher.
Hereinafter, the composition of NCP will be described. NCP is one containing polymer materials. NCP can also contain antioxidant materials.

＜ Polymer Materials ＞＞
The polymer material included in the NCP is not particularly limited, but considering the reason that the gaps between conductive members such as semiconductor elements and anisotropic conductive members can be efficiently buried and the adhesion between the conductive members is further improved, the thermosetting property is considered. Resin is preferred.
Specific examples of the thermosetting resin include epoxy resin, phenol resin, polyimide resin, polyester resin, polyurethane resin, bismaleimide resin, melamine resin, and isocyanate-based resin. Resin, etc.
Among them, it is preferable to use a polyimide resin and / or an epoxy resin for reasons of better insulation reliability and excellent chemical resistance.

＜〈 Antioxidant material 〉＞
Specific examples of the antioxidant material contained in NCP include 1,2,3,4-tetrazole, 5-amino-1,2,3,4-tetrazole, and 5-methyl-1. , 2,3,4-tetrazole, 1H-tetrazol-5-acetic acid, 1H-tetrazol-5-succinic acid, 1,2,3-triazole, 4-amino-1,2,3-triazole Azole, 4,5-diamino-1,2,3-triazole, 4-carboxy-1H-1,2,3-triazole, 4,5-dicarboxy-1H-1,2,3-triazole Azole, 1H-1,2,3-triazole-4-acetic acid, 4-carboxy-5-carboxymethyl-1H-1,2,3-triazole, 1,2,4-triazole, 3-amine -1,2,4-triazole, 3,5-diamino-1,2,4-triazole, 3-carboxy-1,2,4-triazole, 3,5-dicarboxy-1, 2,4-triazole, 1,2,4-triazole-3-acetic acid, 1H-benzotriazole, 1H-benzotriazole-5-carboxylic acid, benzofuran, 2,1,3-benzene Benzothiazole, o-phenylenediamine, m-phenylenediamine, catechol, o-aminophenol, 2-mercaptobenzothiazole, 2-mercaptobenzimidazole, 2-mercaptobenzoxazole, melamine and the like derivative.
Of these, benzotriazole and its derivatives are preferred.
Examples of the benzotriazole derivative include a hydroxyl group, an alkoxy group (for example, a methoxy group, an ethoxy group, etc.), an amine group, a nitro group, and an alkyl group (for example, a methyl group) on the benzene ring of the benzotriazole. Group, ethyl, butyl, etc.), halogen atoms (for example, fluorine, chlorine, bromine, iodine, etc.) and the like. In addition, naphthalenetriazole, naphthalenebistriazole, and substituted naphthalenetriazole and substituted naphthalenebistriazole, which are similarly substituted, can also be mentioned.

In addition, as other examples of the antioxidant material included in NCP, general antioxidants, higher fatty acids, higher fatty acid copper, phenol compounds, alkanolamines, hydroquinones, copper chelating agents, and organic amines are mentioned. , Organic ammonium salts, etc.

The content of the antioxidant material contained in the NCP is not particularly limited, but from the viewpoint of the anticorrosive effect, it is preferably 0.0001 mass% or more with respect to the total mass of the NCP, and more preferably 0.001 mass% or more. In addition, from the reason that an appropriate resistance is obtained in a formal bonding process, 5.0% by mass or less is more preferable, and 2.5% by mass or less is more preferable.

＜＜ Migration prevention material ＞＞
In the NCP, it is preferable to include a migration prevention material for the reason that the metal ions, halogen ions, and metal ions originating from a semiconductor element and a semiconductor wafer can be contained in the NCP to improve insulation reliability.

As the migration preventing material, for example, an ion exchanger can be used, and specifically, a mixture of a cation exchanger and an anion exchanger can be used or only a cation exchanger can be used.
Among them, the cation exchanger and the anion exchanger can be appropriately selected from, for example, an inorganic ion exchanger and an organic ion exchanger described later.

((Inorganic ion exchanger))
Examples of the inorganic ion exchanger include hydrous oxides of metals typified by hydrous zirconia.
Examples of the metal include iron, aluminum, tin, titanium, antimony, magnesium, beryllium, indium, chromium, and bismuth, in addition to zirconium.
Among them, zirconium-based ^compounds have an exchange capacity for cations Cu ²⁺ and Al ³⁺ . In addition, iron-based persons also have exchange capabilities for Ag ⁺ and Cu ²⁺ .
Similarly, tin-based, titanium-based, and antimony-based cation exchangers are used.
The other hand, those based on bismuth, Cl to anion ^- exchange having capability.
Moreover, a zirconium-based person shows anion exchange capacity depending on conditions. The same applies to aluminum and tin.
As other inorganic ion exchangers, composites such as acid salts of polyvalent metals represented by zirconium phosphate, heteropoly acid salts represented by ammonium phosphomolybdate, and insoluble ferrocyanide are known.
Some of these inorganic ion exchangers are commercially available. For example, various grades of the product name of TOAGOSEI CO., LTD. Are known as "IXE".
Furthermore, in addition to synthetic products, powders of inorganic ion exchangers such as natural zeolites and montmorillonite can be used.

((Organic Ion Exchanger))
Among the organic ion exchangers, crosslinked polystyrene having a sulfonic acid group can be mentioned as the cation exchanger, and those having a carboxylic acid group, a phosphonic acid group or a phosphinic acid group can also be mentioned.
Examples of the anion exchanger include a crosslinked polystyrene having a quaternary ammonium group, a quaternary fluorenyl group, or a tertiary fluorenyl group.

These inorganic ion exchangers and organic ion exchangers may be appropriately selected in consideration of the types of cations and anions to be captured and the exchange capacity for the ions. Of course, it is needless to say that an inorganic ion exchanger and an organic ion exchanger can be used in combination.
The manufacturing process of electronic components includes a heating process, so an inorganic ion exchanger is preferred.

Regarding the mixing ratio of the migration preventing material and the above-mentioned polymer material, for example, from the viewpoint of mechanical strength, it is preferable that the migration preventing material is 10% by mass or less, and the migration preventing material is 5% by mass or less. More preferably, it is more preferable that the migration preventing material is 2.5 mass% or less. From the viewpoint of suppressing migration when a semiconductor element or a semiconductor wafer is bonded to the anisotropic conductive member, the migration prevention material is preferably 0.01% by mass or more.

<< Inorganic Filler >>
The NCP preferably contains an inorganic filler.
The inorganic filler is not particularly limited and can be appropriately selected from known ones, and examples thereof include kaolin, barium sulfate, barium titanate, silicon oxide powder, finely powdered silicon oxide, fumed silica, and amorphous two. Silica, crystalline silica, fused silica, spherical silica, talc, clay, magnesium carbonate, calcium carbonate, aluminum oxide, aluminum hydroxide, mica, aluminum nitride, zirconia, yttrium oxide, carbonization Silicon, silicon nitride, etc.

At the time of joining, for the reason that the inorganic filler is prevented from entering between the conductive paths and the conduction reliability is further improved, the average particle diameter of the inorganic filler is preferably larger than the interval between the conductive paths.
The average particle diameter of the inorganic filler is preferably 30 nm to 10 μm, and more preferably 80 nm to 1 μm.
The average particle diameter is a primary particle diameter measured by a laser diffraction scattering particle diameter measuring device (Microtrac MT3300 manufactured by NIKKISO CO., LTD.).

＜＜ Hardener ＞＞
NCP may also contain a hardener.
When a hardener is contained, from the viewpoint of suppressing poor bonding with the surface shape of the anisotropic conductive member to be connected, it is not used as a hardener which is solid at normal temperature, but is contained as a liquid at normal temperature. Is better.
Here, "a solid at normal temperature" means a substance which is solid at 25 ° C, for example, a melting point higher than 25 ° C.

Specific examples of the hardening agent include aromatic amines such as diaminodiphenylmethane and diaminodiphenylhydrazone, aliphatic amines, imidazole derivatives such as 4-methylimidazole, dicyandiamine, and tetramine. Carboxylic anhydrides such as methylguanidine, thiourea addition amine, methylhexahydrophthalic anhydride, hydrazine carboxylic acid, hydrazine carboxylic acid, polyphenol compounds, novolac resins, polythiols, etc. The agent can be appropriately selected and used as a liquid at 25 ° C. The hardener may be used alone or in combination of two or more.

The NCP may contain various additives such as a dispersant, a buffering agent, and a viscosity modifier, which are widely added to a resin insulating film of a semiconductor package, as long as the characteristics are not impaired.

[Joining procedure]
As described above, the joining in the joining step is also referred to as a formal joining. At the time of formal bonding, the environment, heating temperature, pressure (load), and processing time at the time of formal bonding are cited as control factors, but the conditions applicable to the device such as the used semiconductor element can be selected.
The temperature conditions in the formal bonding are not particularly limited, but a temperature higher than the temporarily fixed temperature is preferable, and specifically, 150 ° C to 350 ° C is more preferable, and 200 ° C to 300 ° C is particularly preferable.
In addition, the pressurizing conditions in the formal joining are not particularly limited, but 30 MPa or less is preferable, and 0.1 MPa to 20 MPa is more preferable.
In addition, the time for formal joining is not particularly limited, but it is preferably from 1 second to 60 minutes, and more preferably from 5 seconds to 10 minutes.
In addition, as the device used in the above-mentioned formal bonding, for example, MITSUBISHI HEAVY INDUSTRIES MACHINE TOOL CO., LTD., Bondtech Co., Ltd., PMT CORPORATION, AYUMI INDUSTRY Co., Ltd., Tokyo Electron Limited (TEL) can be used. , EVG, SUSS MicroTec AG (SUSS), MUSASHINO ENGINEERING CO., LTD.
As the environment at the time of the actual bonding, the atmosphere can be selected from an inert environment such as a nitrogen environment and a reduced-pressure environment including a vacuum environment.
The heating temperature is not particularly limited to the above, and various selections can be made up to a temperature of 100 ° C to 400 ° C. Regarding the heating rate, it can also be based on the performance of the heating stage or heating from 10 ° C / minute to 10 ° C / second. Way to choose. The same applies to cooling. In addition, it can be heated in a stepped shape and divided into several sections, and it can also be sequentially joined by increasing the heating temperature.
Regarding the pressure (load), it is not particularly limited to the above, and it is possible to select rapid pressurization or pressurization in a stepped manner depending on the physical characteristics and the like of the joining target.

The environment at the time of the actual joining, the holding time and the changing time of heating and pressing can be appropriately set. The order can be changed as appropriate. For example, the first stage of pressurization in a vacuum state is performed. After heating and heating, the second stage of pressurization is performed for a certain period of time, cooling is performed while unloading, and the combination can return to the stage below a certain temperature The order in the atmosphere.
This sequence can replace various combinations. After pressing in the atmosphere, it can be heated to a vacuum state, or it can be vacuumed, pressed, and heated together. Examples of these combinations are shown in FIGS. 45 to 51.
In addition, in the case of pressure distribution and heating distribution in the joint surface, if a mechanism for individual control is used, the yield of the joint can be improved.
The temporary fixation can also be changed in the same manner. For example, by performing it in an inert environment, oxidation of the electrode surface of the semiconductor element can be suppressed. In addition, it is possible to perform bonding while adding ultrasonic waves.

45 to 51 are graphs showing the first to seventh examples of the actual joining conditions of the joined body according to the embodiment. 45 to 51 show the environment, heating temperature, pressure (load), and processing time during joining. The symbol V represents the degree of vacuum, the symbol L represents the load, and the symbol T represents the temperature. The high degree of vacuum in FIGS. 45 to 51 indicates that the pressure becomes low.
Regarding the environment, the heating temperature, and the load at the time of joining, for example, as shown in FIG. 45 to FIG. 47, the temperature can be increased after the load is applied while the pressure is reduced. Moreover, as shown in FIG. 48, FIG. 50, and FIG. 51, the time at which a load is applied and the time at which temperature is raised may be combined. As shown in FIG. 49, a load may be applied after the temperature is increased. Moreover, as shown in FIG. 48 and FIG. 49, the time of pressure reduction and the time of temperature increase may be combined.
The temperature rise is also shown in FIG. 45, FIG. 46, and FIG. 50, and it can rise to a step shape, as shown in FIG. 51, and it can also be heated in two steps. As shown in Fig. 47 and Fig. 50, the load can be applied in a step shape.
In addition, as shown in FIGS. 45, 47, 49, 50, and 51, a load can be applied after decompression at the time of decompression pressure, and as shown in FIGS. 46 and 48, the decompression time can also be combined And when the load is applied. In this case, pressure reduction and joining are performed simultaneously.

(Laminated Device)
Hereinafter, a multi-layered device having an anisotropic conductive member in a multi-layered device as an example of a bonded body according to an embodiment of the present invention will be further described.
FIG. 52 is a schematic view showing a fifth example of a multilayer device as an example of a bonded body according to an embodiment of the present invention, and FIG. 53 is a schematic view showing a sixth example of a multilayer device as an example of a bonded body according to an embodiment of the present invention.
Moreover, a bonded body is a thing which comprises a laminated device and a part of laminated device. The semiconductor element described later is, for example, a member having a conductive region of a bonded body and bonded to an anisotropic conductive member. The conductive region corresponds to a terminal or the like which bears the conductivity of the semiconductor element.

The laminated device 10 is not limited to the above-mentioned structure. As shown in the laminated device 80 shown in FIG. 52, it is also possible to use an interposer 87 and an anisotropic conductive member 82 to laminate and bond the semiconductor elements 84, A structure in which the semiconductor element 86 and the semiconductor element 88 are electrically connected. The anisotropic conductive member 82 has the same structure as the anisotropic conductive member 15 described above, for example.
Moreover, like the multilayer device 80 shown in FIG. 53, it can also function as an optical sensor. The laminated device 80 shown in FIG. 53 laminates the semiconductor element 110 and the sensor wafer 112 along the laminated direction Ds via the anisotropic conductive member 82. A lens 114 is provided on the sensor wafer 112.
The semiconductor element 110 is a person formed with a logic circuit, and the structure of the semiconductor element 110 is not particularly limited as long as the signal can be processed by the sensor chip 112.
The sensor chip 112 is a light sensor having a detection light. The light sensor is not particularly limited as long as it can detect light. For example, a CCD (Charge Coupled Device) image sensor or a CMOS (Complementary Metal Oxide Semiconductor) image sensor can be used.
As long as the lens 114 is capable of condensing light on the sensor wafer 112, its structure is not particularly limited, and for example, a microlens can be used.

The semiconductor element 84, the semiconductor element 86, and the semiconductor element 88 have element regions (not shown). Including the semiconductor elements 12, 14, 16, the first semiconductor wafer 60, the second semiconductor wafer 70, and the third semiconductor wafer, the element area is formed by capacitors, resistors, and coils that function as electronic components. There are areas of various element structure circuits and the like. The element area includes, for example, an area where a storage circuit such as a flash memory is formed, a logic circuit such as a microprocessor and an FPGA (field-programmable gate array), and a communication module such as a wireless tag is formed. And wiring area. In addition to the element region, a transmission circuit or a MEMS (Micro Electro Mechanical Systems) may be formed. MEMS are, for example, sensors, actuators, and antennas. The sensors include various sensors such as acceleration, sound, and light.

As described above, an element structure circuit and the like are formed in the element region. For example, a redistribution layer (not shown) is provided in a semiconductor element.
The multilayer device can be, for example, a combination of a semiconductor element having a logic circuit and a semiconductor element having a storage circuit. In addition, the semiconductor device may be a device having all the storage circuits, or may be a device having all the logic circuits. The combination of the semiconductor elements in the multilayer device 80 may be a combination of a sensor, an actuator, an antenna, and the like, a storage circuit and a logic circuit, and may be appropriately determined according to the purpose of the multilayer device 80 and the like.

[Semiconductor element]
Semiconductor components are used in the above-mentioned semiconductor packages and multilayer devices. The semiconductor device is not particularly limited. In addition to the above, for example, a logic LSI (Large Scale Integration) (for example, ASIC (Application Specific Integrated Circuit), or FPGA (Field Programmable Gate Array)) Program Gate Array), ASSP (Application Specific Standard Product, etc.), microprocessor (such as CPU (Central Processing Unit, Central Processing Unit), GPU (Graphics Processing Unit, Graphics Processing Unit, etc.)), storage Devices (such as DRAM (Dynamic Random Access Memory), HMC (Hybrid Memory Cube, hybrid memory cube), MRAM (MagneticRAM: magnetic storage device) and PCM (Phase-Change Memory: phase change storage device), ReRAM (Resistive RAM: variable resistance storage device), FeRAM (Ferroelectric RAM: ferroelectric storage device), flash memory (NAND (Not AND) flash, etc.), LED (Light Emitting Diode, light emitting diode), (E.g. portable micro-flash, automotive, projector light source, LCD backlight, general lighting, etc.), power / device Analog IC (Integrated Circuit), (for example, DC (Direct Current) -DC (Direct Current) converter, Insulation mold inlet bipolar transistor (IGBT), etc.), MEMS (Micro Electro Mechanical Systems, Microelectronics Mechanical system), (e.g. acceleration sensor, pressure sensor, vibrator, gyro sensor, etc.), wireless (e.g. GPS (Global Positioning System), FM (Frequency Modulation), NFC (Frequency Modulation) Nearfield communication), RFEM (RF Expansion Module), MMIC (Monolithic Microwave Integrated Circuit), WLAN (WirelessLocalAreaNetwork, wireless local area network, etc.), discrete components, BSI (Back Side Illumination (backlighting), CIS (Contact Image Sensor), camera module, CMOS (Complementary Metal Oxide Semiconductor), Passive (Passive) device, SAW (Surface Acoustic Wave, surface (Sonic) filter, RF (Radio Frequency) filter, RFIPD (Radio Frequency Integrated Passive De vices, RF integrated passive devices), BB (Broadband, Broadband), etc.
The semiconductor element is, for example, a single finisher, and a single semiconductor element that performs a specific function such as a circuit or a sensor.

As a multilayer device, it is not limited to a form in which a plurality of semiconductor elements are bonded to one semiconductor element, that is, a pair of forms, and a form in which a plurality of semiconductor elements and a plurality of semiconductor elements are joined, that is, a plurality of pairs Shape.
FIG. 54 is a schematic view of a seventh example of a multilayer device showing an example of a bonded body according to an embodiment of the present invention, FIG. 55 is a schematic view of an eighth example of a multilayer device that is an example of a bonded body according to an embodiment of the present invention, FIG. 56 FIG. 57 is a schematic diagram of a ninth example of a multilayer device showing an example of a bonded body according to an embodiment of the present invention, and FIG. 57 is a schematic diagram of a tenth example of a laminated device that is an example of a bonded body according to an embodiment of the present invention.

As a form of plural to plural, as shown in FIG. 54, for example, a laminated layer in which an anisotropic conductive member 82 is used, and a semiconductor element 86 and a semiconductor element 88 are bonded to one semiconductor element 84 and electrically connected is exemplified. Device 80a. The semiconductor element 84 may be an interposer function.
For example, a plurality of devices such as a logic chip having a logic circuit and a memory chip can be stacked on a device having an interposer function. In this case, the bonding can be performed even if the electrode size differs for each device.
In the multilayer device 80b shown in FIG. 55, the sizes of the electrodes 118 are not the same, and different sizes are mixed. However, using an anisotropic conductive member 82, the semiconductor element 86 and the semiconductor element 88 are bonded to one semiconductor element 84. And electrically connected. Furthermore, the anisotropic conductive member 82 is used to join the semiconductor element 116 and the semiconductor element 86 and to electrically connect them. Using the anisotropic conductive member 82, the semiconductor element 117 is bonded and electrically connected across the semiconductor element 86 and the semiconductor element 88.

Also, as in the multilayer device 80 c shown in FIG. 56, the semiconductor element 86 and the semiconductor element 88 are bonded to one semiconductor element 84 using an anisotropic conductive member 82 and are electrically connected. Furthermore, the semiconductor element 116 and the semiconductor element 117 may be bonded to the semiconductor element 86 using the anisotropic conductive member 82, and the semiconductor element 121 and the semiconductor element 88 may be bonded using the anisotropic conductive member 82. Electrical connection.

In the case of the structure described above, a light emitting element such as a VCSEL (Vertical Cavity Surface Emitting Laser) and a complementary metal oxide such as a CMOS (Complementary Metal Oxide Semiconductor) The light-receiving element of a semiconductor) image sensor can also correspond to silicon photonics assuming a high frequency.
For example, as in the multilayer device 80 d shown in FIG. 57, the semiconductor element 86 and the semiconductor element 88 are bonded to one semiconductor element 84 using an anisotropic conductive member 82 and are electrically connected. Furthermore, the semiconductor element 116 and the semiconductor element 117 are bonded to the semiconductor element 86 using the anisotropic conductive member 82, and the semiconductor element 121 and the semiconductor element 88 are bonded to each other using the anisotropic conductive member 82 and electrically connected. The semiconductor element 84 is provided with an optical waveguide 123. A light emitting element 125 is provided on the semiconductor element 88, and a light receiving element 126 is provided on the semiconductor element 86. The light Lo output from the light emitting element 125 of the semiconductor element 88 passes through the optical waveguide 123 of the semiconductor element 84, and is emitted as the emitted light Ld to the light receiving element 126 of the semiconductor element 86. This can correspond to the above-mentioned silicon photonics.
In the anisotropic conductive member 82, a hole 122 is formed in a portion corresponding to the optical path of the light Lo and the emitted light Ld.

The present invention is basically constituted as described above. The manufacturing method of the bonded body, the temporary fixing member, and the laminated body according to the present invention have been described in detail above. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the present invention. Or change.
[Example]

Hereinafter, the features of the present invention will be described in more detail with examples. The materials, reagents, substance amounts, ratios, operations, etc. shown in the following examples can be changed as appropriate without departing from the spirit of the present invention. Therefore, the scope of the present invention is not limited to the following examples.
In this example, an anisotropic conductive member and a semiconductor member shown below were bonded as a conductive member, and joints of Examples 1 to 11 and Comparative Examples 1 and 2 described below were produced and evaluated. Resistance and position deviation. The results of resistance and position deviation are shown in Table 1 below.

Hereinafter, the resistance as an evaluation item will be described.
The resistance was evaluated using conduction resistance. The on-resistance will be described.
＜ Evaluation of resistance ＞
The probe was brought into contact with the lead pad of the daisy chain pattern portion of the interposer, and the continuity evaluation was performed in the atmosphere. As a measuring device, SourceMeter from KEITHLEY was used to measure the impedance value.
Based on the results of the impedance values, evaluation was performed using the evaluation criteria shown below. The evaluation results are shown in the resistance column of Table 1 below.
"A": The impedance value is less than 10 times the design impedance. "B": The impedance value is more than 10 times and less than 100 times the design impedance. "C": The impedance value is more than 100 times and less than 1000 times the design impedance. " D ”: The impedance value is more than 1000 times the design impedance

Hereinafter, the position deviation as an evaluation item will be described.
Regarding the position deviation, the deviation of the alignment mark was evaluated by observation with an infrared microscope.
<Position deviation>
Using an IR microscope, it was evaluated whether or not the scale marks on the four sides of the alignment marks located on the two places of the wafer and the interposer deviated from each other. Based on the results of microscopic observation, evaluation was performed based on the criteria shown below. The evaluation results are shown in the column of misalignment in Table 1 below.
"A": Position deviation less than 5 μm
"B": Position deviation is 5 μm or more and less than 10 μm
"C": Position deviation is 10 μm or more

A TEG wafer (Test Element Group chip) is used in the semiconductor component.
＜ TEG Wafer ＞
TEG chips and interposers with Cu pads were prepared. These include a daisy chain pattern for measuring the on-resistance and a comb tooth pattern for measuring the insulation resistance. The insulating layers are made of SiN. A TEG wafer was prepared with a wafer size of 8 mm square and a ratio of electrode area (copper pillars) to wafer area of 25%. The diameter of the electrode was set to 5 μm, the height was set to 7 μm, and the thickness of the insulating layer existing between the electrodes was set to 2 μm. The TEG wafer corresponds to a semiconductor component. The interposer contains extraction wiring around it, so a square with a wafer size of 10 mm is prepared.
In addition, during bonding, a TEG wafer, an anisotropic conductive member, and an interposer were sequentially laminated, and a wafer bonder (DB250, manufactured by Shibuya Kogyo Co., Ltd.) was used at a bonding temperature of 270 ° C for 10 minutes. Joined. At this time, the alignment marks formed on the corners of the wafer are used for alignment and bonding, so as to prevent the position of the TEG wafer and the Cu pad of the interposer from deviating. In addition, prior to joining, there is also a case for temporarily fixing using a temporary fixing member as described later.

The anisotropic conductive member will be described below.
[Anisotropic conductive member]
＜ Production of aluminum substrate ＞
Using Si: 0.06% by mass, Fe: 0.30% by mass, Cu: 0.005% by mass, Mn: 0.001% by mass, Mg: 0.001% by mass, Zn: 0.001% by mass, Ti: 0.03% by mass, and the remaining portions are Al and Aluminum alloys with unavoidable impurities are prepared as molten metals. Next, the molten metal was processed and filtered, and an ingot having a thickness of 500 mm and a width of 1200 mm was produced by a DC (Direct Chill) casting method.
Next, the surface of the ingot was cut by a surface cutting machine with an average thickness of 10 mm, and then held at 550 ° C for 5 hours. After the temperature was lowered to 400 ° C, a 2.7 mm-thick rolled plate was produced using a hot rolling mill. .
In addition, after performing a heat treatment at 500 ° C. using a continuous annealing machine, a thickness of 1.0 mm was completed by cold rolling, and an aluminum substrate of JIS (Japanese Industrial Standard) 1050 material was obtained.
After forming the aluminum substrate into a wafer shape with a diameter of 200 mm (8 feet), each of the processes described below was performed.

＜ Electrolytic polishing treatment ＞
An electrolytic polishing liquid having the following composition was used for the above-mentioned aluminum substrate, and electrolytic polishing was performed under conditions of a voltage of 25 V, a liquid temperature of 65 ° C., and a liquid flow rate of 3.0 m / min.
The cathode was a carbon electrode, and GP0110-30R (manufactured by Takasago, Ltd.) was used as a power source. The flow rate of the electrolytic solution was detected using a vortex flow monitor FLM22-10PCW (manufactured by As One Corporation).
(Composition of electrolytic polishing liquid)
･ 85% by mass phosphoric acid (reagent manufactured by Wako Pure Chemical Industries, Ltd.) 660 mL
･ Pure water 160 mL
Sulfuric acid 150 mL
･ Glycol ester 30 mL

＜ Anodizing process ＞
Next, an anodizing process based on a self-regularization method was performed on the aluminum substrate after electrolytic polishing treatment in accordance with the procedure described in Japanese Patent Application Laid-Open No. 2007-204802.
A 0.50 mol / L oxalic acid electrolyte was applied to the aluminum substrate after the electrolytic polishing treatment, and a pre-anodization treatment was performed for 5 hours at a voltage of 40 V, a liquid temperature of 16 ° C, and a liquid flow rate of 3.0 m / min.
After that, the aluminum substrate after the pre-anodization treatment was subjected to a stripping treatment for 12 hours in a mixed aqueous solution (liquid temperature: 50 ° C.) of 0.2 mol / L chromic anhydride and 0.6 mol / L phosphoric acid.
Then, a 0.50 mol / L oxalic acid electrolyte was used to perform an anodization treatment at a voltage of 40 V, a liquid temperature of 16 ° C., and a liquid flow rate of 3.0 m / min for 3 hours and 45 minutes, thereby obtaining an anodization film having a thickness of 30 μm. membrane.
In addition, in the pre-anodizing treatment and the re-anodizing treatment, the cathode was a stainless steel electrode, and GP0110-30R (manufactured by Takasago, Ltd.) was used as a power source. Moreover, NeoCool BD36 (made by Yamato Scientific Co., Ltd.) was used as a cooling device, and Pairstirrer PS-100 (made by TOKYO RIKAKIKAI CO., LTD.) Was used as a stirring and heating device. The flow rate of the electrolytic solution was detected using a vortex flow monitor FLM22-10PCW (manufactured by As One Corporation).

＜ Removal process of barrier layer ＞
Next, under the same treatment liquid and treatment conditions as the above-mentioned anodizing treatment, the voltage was continuously decreased from 40 V to 0 V at a voltage drop rate of 0.2 V / sec, and an electrolytic treatment (electrolytic removal treatment) was performed.
Thereafter, an etching treatment (etching removal treatment) was performed by immersing in 5 mass% phosphoric acid at 30 ° C for 30 minutes to remove the barrier layer on the bottom of the micropores of the anodized film, and aluminum was exposed through the micropores.

The average pore diameter of the micropores of the anodic oxide film existing in the barrier layer removal process is 60 nm. In addition, the average pore diameter is calculated by taking a photograph of the surface (magnification of 50,000 times) by using a field emission-scanning electron microscope (FE-SEM) and measuring it as an average of 50 points.
The average thickness of the anodized film after the barrier layer removal process was 80 μm. In addition, the average thickness is cut with FIB (Focused Ion Beam) with respect to the thickness direction, and the surface of the cross-section is taken by FE-SEM (50,000 times magnification) and measured as 10 points. The average value is calculated.
The density of micropores existing in the anodized film was about 100 million pieces / mm ² . The density of micropores is measured and calculated by the methods described in paragraphs <0168> and <0169> of Japanese Patent Application Laid-Open No. 2008-270158.
The degree of regularity of the micropores existing in the anodized film was 92%. In addition, the degree of regularity was measured and calculated by taking a photograph of the surface (magnification 20,000 times) by FE-SEM, and measuring the method described in paragraphs <0024> to <0027> of JP-A-2008-270158.

＜ Metal Filling Process ＞
Next, an electrolytic plating process was performed using an aluminum substrate as a cathode and platinum as a positive electrode.
Specifically, a copper-plated metal having the composition shown below was used and constant-current electrolysis was performed to produce a metal-filled microstructure with copper filled inside the micropores.
Here, for constant current electrolysis, a plating device manufactured by Yamamoto-MS Co., Ltd was used, and a power source (HZ-3000) manufactured by HOKUTO DENKO CORPORATION was used. Cyclic voltammetry was performed in the plating solution to confirm the precipitation potential. Perform the treatment under the conditions indicated.
(Composition and conditions of copper plating bath)
铜 Copper sulfate 100 g / L
Sulfuric acid 50 g / L
･ Hydrochloric acid 15 g / L
･ Temperature 25 ℃
･ Current density 10 A / dm ²

The surface of the anodic oxide film after the metal is filled in the micropores is observed by FE-SEM, and whether or not the sealing caused by the metal in 1000 micropores is observed is used to calculate the sealing rate (the number of sealing micropores / 1000) , Which is 96%.
In addition, FIB was used to cut the anodic oxide film after filling the micropores with metal in the thickness direction, and the surface of the cross section was taken by FE-SEM (50,000 times magnification) to confirm the inside of the micropores. The sealed micropores are completely filled with metal inside.

＜ Substrate removal process ＞
Next, the aluminum substrate was dissolved and removed by immersing in a 20% by mass mercury chloride aqueous mercury solution (liter of mercury) at 20 ° C. for 3 hours to prepare a metal-filled fine structure.

＜ Trimming process ＞
The metal-filled microstructures after the substrate removal process are immersed in an aqueous sodium hydroxide solution (concentration: 5 mass%, liquid temperature: 20 ° C), and the immersion time is adjusted so that the height of the protruding portion becomes 500 nm and the aluminum is selectively dissolved The surface of the anodized film was then washed with water and dried to produce an anisotropic conductive member having a copper cylinder, which is a conductive path, protruding.

(Example 1)
In Example 1, after the interposer, the anisotropic conductive member, and the TEG chip are aligned, between the interposer and the anisotropic conductive member, and between the anisotropic conductive member and the TEG chip, Isopropyl alcohol (boiling point: 82 ° C) was provided as a temporary fixing member, and isopropyl alcohol was temporarily fixed, and then isopropyl alcohol was removed and bonded at the same time to produce a bonded body. In addition, in Example 1, the temporary fixing member was replaced with a gas during joining.
In Example 1, isopropyl alcohol was used as a temporary fixing member, and after temporarily fixing at a temperature of 50 ° C. for 1 minute, bonding was performed under a bonding condition of temperature of 270 ° C. for 10 minutes. Isopropanol is vaporized and removed.

(Example 2)
The second embodiment differs from the first embodiment in that the temporary fixing member removal step and the joining step, and the temporary fixing member removal step are the steps of replacing the temporary fixing member with a gas. It is the same as that of Example 1.
In Example 2, during temporary fixation, temporary fixation was performed at a temperature of 150 ° C. for 1 minute, and isopropyl alcohol was vaporized and removed, and then bonded.
(Example 3)
The third embodiment is different from the first embodiment in that the temporary fixing member removal step and the joining step and the temporary fixing member removal step are not gasification steps, and are different from the first embodiment. the same.
In Example 3, during temporary fixation, temporary fixation was performed under the conditions of a temperature of 100 ° C. for 1 minute, and isopropyl alcohol was vaporized and removed, and then a filler was filled, followed by bonding.
As for the filler, U8410-73CF3 (Product No.) manufactured by NAMICS CORPORATION was used. 10 g of filler was added to the dispenser, and a vacuum dispenser (manufactured by Toray Engineering Co., Ltd.) was set at a pressure of 130 Pa and a temperature of 100 ° C. Model: FS2500).

(Example 4)
Example 4 is different from Example 1 in that the temporary fixing member removal step and the joining step, and the temporary fixing member removal step are the steps of replacing the temporary fixing member with a filler. Is the same as that of the first embodiment.
Regarding the filler, U8443-14 (Product No.) manufactured by NAMICS CORPORATION was used, and 10 g of filler was added to the dispenser, and the vacuum dispenser (manufactured by Toray Engineering Co., Ltd.) was set to a pressure of 130 Pa and a temperature of 50 ° C. Model: FS2500).
(Example 5)
The fifth embodiment is the same as the first embodiment except that the third butanol (boiling point: 82 ° C.) is used in the temporary fixing member. The third butanol was solid at a temperature of 23 ° C.
(Example 6)
Example 6 is the same as Example 1 except that diethylene glycol dibutyl ether (boiling point: 256 ° C) was used in the temporary fixing member, as compared with Example 1. In addition, diethylene glycol dibutyl ether is liquid at a temperature of 23 ° C.

(Example 7)
Example 7 is the same as Example 1 except that acetone (boiling point: 56 ° C) is used in the temporary fixing member, as compared with Example 1. In addition, acetone was liquid at a temperature of 23 ° C. (Example 8) (Example 8)
Example 8 is the same as Example 1 except that ethyl lactate (boiling point: 154 ° C) was used in the temporary fixing member, as compared with Example 1. In addition, ethyl lactate was liquid at a temperature of 23 ° C.
(Example 9)
Example 9 is the same as Example 1 except that propylene glycol monomethyl ether acetate (boiling point: 146 ° C) was used in the temporary fixing member, as compared with Example 1. The propylene glycol monomethyl ether acetate was liquid at a temperature of 23 ° C.

(Example 10)
Example 10 is the same as Example 1 except that ethylene glycol (boiling point: 197 ° C) was used in the temporary fixing member, as compared with Example 1. In addition, ethylene glycol is liquid at a temperature of 23 ° C.
(Example 11)
Example 11 is the same as Example 1 except that diethylene glycol monobutyl ether acetate (boiling point: 245 ° C.) was used in the temporary fixing member. In addition, diethylene glycol monobutyl ether acetate was liquid at a temperature of 23 ° C.

(Comparative Example 1)
In Comparative Example 1, a TEG wafer, an anisotropic conductive member, and an interposer were bonded without using a temporary fixing member.
(Comparative Example 2)
In Comparative Example 2, joining was performed, but the difference from Example 1 was that NCP (Non Conductive Paste) was used as the temporary fixing member, and the temporary fixing member was not removed. Other than that, it was set to Example 1 the same.

[Table 1]

As shown in Table 1, the results of the resistors of Examples 1 to 11 were better than those of Comparative Example 1 and Comparative Example 2. Moreover, compared with the comparative example 1 which did not use a temporary fixing member, the position deviation of Examples 1-11 was small.
In Example 1, the removal step and the joining step of the temporary fixing member were simultaneously performed, and the evaluation of resistance and position deviation was good.
In Example 2, the temporary fixing member was replaced with a gas, and the removal step and the joining step of the temporary fixing member were not performed simultaneously. Therefore, the resistance evaluation was lower than that in Example 1.
In Example 3, the temporary fixing member was vaporized and removed, and the removal step and the joining step of the temporary fixing member were not performed at the same time. Therefore, the resistance evaluation was slightly lower than that in Example 1.
In Example 4, the temporary fixing member was replaced with a filler, and the removal step and the joining step of the temporary fixing member were not performed at the same time. Therefore, the resistance evaluation was slightly lower than that in Example 1.

In Example 5, since the temporary fixing member was solid at a temperature of 23 ° C, the resistance evaluation was lower than that in Example 1.
In Example 6, since a temporary fixing member having a boiling point exceeding 250 ° C. was used, the evaluation of resistance and position deviation was lower than that of Example 1.
In Example 7, the temporary fixing member was liquid at a temperature of 23 ° C, but the boiling point of the liquid was close to 50 ° C, and the resistance evaluation was slightly lower than in Example 1.
In Examples 8 and 9, the temporary fixing member was liquid at a temperature of 23 ° C., and the liquid had a boiling point of 140 ° C. to 160 ° C., and the resistance evaluation was the same as in Example 1.
In Example 10 and Example 11, the temporary fixing member was liquid at a temperature of 23 ° C, but the boiling point of the liquid exceeded 190 ° C, and the resistance evaluation was slightly lower than in Example 1.
In Examples 6, 8, and 9 to 11, the boiling point of the temporary fixing member exceeds 140 ° C, which is higher than the boiling points of the temporary fixing members of Examples 1 to 5 and 7. If the boiling point of the temporary fixing member is high, the evaluation of the positional deviation is slightly lower.

10, 80, 80a, 80b, 80c, 80d

12, 14, 16, 84, 86, 88, 110, 116, 117, 121‧‧‧ semiconductor devices

13‧‧‧Temporary fixing members

14a, 16a, 22a, 24a, 25a, 32a, 34a, 36a, 40a, 60a, 70a

14b, 40b, 70b ‧‧‧ back

15, 82‧‧‧Anisotropic conductive member

17‧‧‧ Joint

19‧‧‧Laminated body

20‧‧‧Semiconductor Element Division

21‧‧‧Interposer substrate

22, 23, 118‧‧‧ electrodes

24, 25‧‧‧ Insulation

30, 30a, 30b‧‧‧ terminal

30c‧‧‧face

32‧‧‧ semiconductor layer

34‧‧‧ redistribution layer

36‧‧‧ passivation layer

37‧‧‧Wiring

38‧‧‧pad

39, 43‧‧‧ resin layer

40‧‧‧ insulating substrate

41‧‧‧through hole

42‧‧‧ channel

42a, 42b ‧‧‧ protruding parts

44‧‧‧ peeling layer

45‧‧‧ support layer

46‧‧‧ peeling agent

47‧‧‧ support

49‧‧‧Anisotropic conductive material

50, 62‧‧‧ component area

52, 64‧‧‧ alignment marks

60‧‧‧1st semiconductor wafer

70‧‧‧Second semiconductor wafer

87‧‧‧Interposer

112‧‧‧Sensor Chip

114‧‧‧ lens

122‧‧‧hole

123‧‧‧Optical waveguide

125‧‧‧Light-emitting element

126‧‧‧ light receiving element

D‧‧‧thickness direction

Ds‧‧‧layer direction

Ld‧‧‧ emits light

Lo‧‧‧ Light

h, t‧‧‧ thickness

Hd‧‧‧height

p‧‧‧center distance

w‧‧‧ width between conductors

x‧‧‧ direction

δ‧‧‧ Depression

V‧‧‧Vacuum degree

L‧‧‧Load

T‧‧‧Temperature

FIG. 1 is a schematic view showing a first example of a multilayer device as an example of a bonded body according to an embodiment of the present invention.

FIG. 2 is a schematic view showing a second example of a multilayer device as an example of a bonded body according to an embodiment of the present invention.

3 is a schematic cross-sectional view showing an example of a structure of a terminal of a semiconductor element of a multilayer device as an example of a bonded body according to an embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view showing one step of a first example of a method of manufacturing a multilayer device as an example of a bonded body according to an embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view showing one step of a first example of a method of manufacturing a multilayer device as an example of a bonded body according to an embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view showing one step of a first example of a method of manufacturing a multilayer device as an example of a bonded body according to an embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view showing another example of a structure of a terminal of a semiconductor element of a multilayer device as an example of a bonded body according to an embodiment of the present invention.

FIG. 8 is a schematic view showing a third example of a multilayer device as an example of a bonded body according to an embodiment of the present invention.

FIG. 9 is a schematic diagram of a fourth example of a multilayer device showing an example of a bonded body according to an embodiment of the present invention.

FIG. 10 is a schematic cross-sectional view showing one step of a second example of a method of manufacturing a multilayer device as an example of a bonded body according to an embodiment of the present invention.

11 is a schematic cross-sectional view showing one step of a second example of a method of manufacturing a multilayer device as an example of a bonded body according to an embodiment of the present invention.

FIG. 12 is a schematic cross-sectional view showing one step of a second example of a method of manufacturing a multilayer device as an example of a bonded body according to an embodiment of the present invention.

FIG. 13 is a schematic cross-sectional view showing one step of a second example of a method of manufacturing a multilayer device as an example of a bonded body according to an embodiment of the present invention.

14 is a schematic plan view showing an example of an anisotropic conductive member used in a bonded body according to an embodiment of the present invention.

15 is a schematic cross-sectional view showing an example of an anisotropic conductive member used in a bonded body according to an embodiment of the present invention.

16 is a schematic perspective view showing an example of an alignment mark of a semiconductor element used in a bonded body according to an embodiment of the present invention.

FIG. 17 is a schematic diagram showing an example of an alignment mark of a first semiconductor wafer used in a bonded body according to an embodiment of the present invention.

FIG. 18 is a schematic diagram showing one step of a third example of a method of manufacturing a multilayer device as an example of a bonded body according to an embodiment of the present invention.

FIG. 19 is a schematic diagram showing a step of a third example of a method of manufacturing a multilayer device as an example of a bonded body according to an embodiment of the present invention.

FIG. 20 is a schematic diagram showing a step of a third example of a method of manufacturing a multilayer device as an example of a bonded body according to an embodiment of the present invention.

FIG. 21 is a schematic diagram showing a step of a third example of a method of manufacturing a multilayer device as an example of a bonded body according to an embodiment of the present invention.

22 is a schematic diagram showing a step of a fourth example of a method of manufacturing a multilayer device as an example of a bonded body according to an embodiment of the present invention.

FIG. 23 is a schematic diagram showing one step of a fourth example of a method of manufacturing a multilayer device as an example of a bonded body according to an embodiment of the present invention.

FIG. 24 is a schematic diagram showing a step of a fourth example of a method of manufacturing a multilayer device as an example of a bonded body according to an embodiment of the present invention.

FIG. 25 is a schematic diagram showing a step of a fourth example of a method of manufacturing a multilayer device as an example of a bonded body according to an embodiment of the present invention.

FIG. 26 is a schematic perspective view showing another example of an alignment mark of a semiconductor element used in a bonded body according to an embodiment of the present invention.

FIG. 27 is a schematic diagram showing a step in a fifth example of a method of manufacturing a multilayer device as an example of a bonded body according to an embodiment of the present invention.

FIG. 28 is a schematic diagram showing a step of a fifth example of a method of manufacturing a multilayer device as an example of a bonded body according to an embodiment of the present invention.

FIG. 29 is a schematic diagram showing one step of a fifth example of a method of manufacturing a multilayer device as an example of a bonded body according to an embodiment of the present invention.

FIG. 30 is a schematic diagram showing a step of a fifth example of a method of manufacturing a multilayer device as an example of a bonded body according to an embodiment of the present invention.

FIG. 31 is a schematic diagram showing a step in a first modification of the fifth example of the method of manufacturing a multilayer device as an example of a bonded body according to an embodiment of the present invention.

FIG. 32 is a schematic diagram showing one step of a second modification of the fifth example of the method of manufacturing a multilayer device as an example of a bonded body according to the embodiment of the present invention.

FIG. 33 is a schematic diagram showing a step of a sixth example of a method of manufacturing a multilayer device as an example of a bonded body according to an embodiment of the present invention.

FIG. 34 is a schematic diagram showing one step of a sixth example of a method of manufacturing a multilayer device as an example of a bonded body according to an embodiment of the present invention.

FIG. 35 is a schematic diagram showing a step in a sixth example of a method of manufacturing a multilayer device as an example of a bonded body according to an embodiment of the present invention.

FIG. 36 is a schematic diagram showing a step in a sixth example of a method of manufacturing a multilayer device as an example of a bonded body according to an embodiment of the present invention.

FIG. 37 is a schematic diagram showing one step of a first modification of the sixth example of the method of manufacturing a multilayer device as an example of a bonded body according to the embodiment of the present invention.

FIG. 38 is a schematic diagram showing one step of a second modification of the sixth example of the method of manufacturing a multilayer device as an example of the bonded body according to the embodiment of the present invention.

FIG. 39 is a schematic diagram showing one step of a seventh example of a method of manufacturing a multilayer device as an example of a bonded body according to an embodiment of the present invention.

FIG. 40 is a schematic diagram showing one step of a seventh example of a method of manufacturing a multilayer device as an example of a bonded body according to an embodiment of the present invention.

41 is a schematic diagram showing a step in a seventh example of a method of manufacturing a multilayer device as an example of a bonded body according to an embodiment of the present invention.

FIG. 42 is a schematic diagram showing one step of an eighth example of a method of manufacturing a multilayer device as an example of a bonded body according to an embodiment of the present invention.

FIG. 43 is a schematic diagram showing one step of an eighth example of a method of manufacturing a multilayer device as an example of a bonded body according to an embodiment of the present invention.

FIG. 44 is a schematic diagram showing one step of an eighth example of a method of manufacturing a multilayer device as an example of a bonded body according to an embodiment of the present invention.

FIG. 45 is a diagram showing a first example of a formal joining condition of a joined body according to an embodiment of the present invention.

FIG. 46 is a diagram showing a second example of the formal joining conditions of the joined body according to the embodiment of the present invention.

Fig. 47 is a diagram showing a third example of the actual joining conditions of the joined body according to the embodiment of the present invention.

FIG. 48 is a diagram showing a fourth example of the actual joining conditions of the joined body according to the embodiment of the present invention.

Fig. 49 is a diagram showing a fifth example of the formal joining conditions of the joined body according to the embodiment of the present invention.

Fig. 50 is a diagram showing a sixth example of the actual joining conditions of the joined body according to the embodiment of the present invention.

Fig. 51 is a diagram showing a seventh example of the actual joining conditions of the joined body according to the embodiment of the present invention.

FIG. 52 is a schematic view showing a fifth example of a multilayer device as an example of a bonded body according to an embodiment of the present invention.

FIG. 53 is a schematic view showing a sixth example of a multilayer device as an example of a bonded body according to an embodiment of the present invention.

FIG. 54 is a schematic view showing a seventh example of a multilayer device as an example of a bonded body according to an embodiment of the present invention.

Fig. 55 is a schematic view showing an eighth example of a multilayer device as an example of a bonded body according to an embodiment of the present invention.

FIG. 56 is a schematic diagram showing a ninth example of a multilayer device as an example of a bonded body according to an embodiment of the present invention.

FIG. 57 is a schematic view showing a tenth example of a multilayer device as an example of a bonded body according to an embodiment of the present invention.

Claims (9)

A method for manufacturing a joint body includes: A temporary fixing step of temporarily fixing the at least two conductive members to each other by providing a temporary fixing member between the at least two conductive members having conductivity; A removing step to remove the temporary fixing member; and The joining step joins the at least two conductive members. The manufacturing method of the joint body according to item 1 of the patent application scope, wherein The removal step and the joining step are performed simultaneously. The manufacturing method of the joint body according to item 1 of the patent application scope, wherein The removing step includes at least one of a gasification step of the temporary fixing member and a replacement step of replacing the temporary fixing member with a gas or a filler. The method for manufacturing a joint according to any one of claims 1 to 3, wherein The temporary fixing member was liquid at a temperature of 23 ° C. The method for manufacturing a joint according to item 4 of the scope of patent application, wherein This liquid has a boiling point of 50 ° C or higher and 250 ° C or lower. The method for manufacturing a joint according to any one of claims 1 to 3, wherein The conductive member is a member having an electrode or an anisotropic conductive member. A temporary fixing member for use in a method for manufacturing a joint according to any one of claims 1 to 6 of the scope of patent application. A laminated body is provided with a temporary fixing member as described in item 7 of the scope of patent application for lamination between at least two conductive members having conductivity. The laminated body described in item 8 of the scope of patent application, wherein The conductive member is a member having an electrode or an anisotropic conductive member.