JP6886261B2 - Manufacturing method of semiconductor light emitting device - Google Patents

Description

The present invention relates to a semiconductor light emitting device including a current block layer and a method for manufacturing the same.

A double hetero type light emitting diode in which a Zn-doped GaAs layer is sandwiched between AlGaAs layers is used as an element for outputting light in the infrared wavelength region (infrared region having a wavelength of 920 nm or less) having high light receiving sensitivity of a photodiode using silicon. Are known. This double heterostructure is usually formed on a GaAs substrate. Most of the light emitted by the GaAs light emitting layer is absorbed by the GaAs substrate. Therefore, when light is taken out to the substrate side, the light loss is large.

Patent Document 1 discloses a technique in which a support layer containing AlGaAs is formed on a GaAs temporary substrate by a liquid phase epitaxial growth method, and then the GaAs temporary substrate is removed by etching or the like to leave a support layer. By forming an AlGaAs clad layer, an InGaAs active layer (light emitting layer), or the like on the support layer (growth substrate), light can be effectively extracted to the support layer side.

In general, it is desired that the light emitting diode has high external quantum efficiency (= intensity of light taken out of the device / intensity of light emitted inside the light emitting layer). In order to improve the external quantum efficiency, a current block layer that partially limits the current injected into the light emitting layer may be provided (for example, Patent Documents 2 to 5).

JP-A-2002-33509 JP-A-2002-016287 Japanese Unexamined Patent Publication No. 2013-093412 JP-A-2009-158550 JP 2015-005551

An object of the present invention is to provide a semiconductor light emitting device having a novel structure, particularly a semiconductor light emitting device including a current block layer having a novel structure, and a method for manufacturing the same.

According to the main aspect of the present invention, step a) high Al composition layer Al composition ratio is mainly a high AlGaAs than 30%, and a low Al the Al composition ratio is mainly a lower AlGaAs than 30% A step of preparing a support layer formed by laminating the composition layer, and a step b) forming a light-emitting optical semiconductor laminate and a first electrode on the surface of the support layer on the low Al composition layer side. The step c) includes a step of forming a second electrode on the surface of the support layer on the high Al composition layer side, and the step c) is a sub-step c1) the height of the support layer. A sub-step of patterning the Al composition layer to expose the low Al composition layer to the region from which the high Al composition layer has been removed, and a sub step c2) a sub step of spontaneously oxidizing the surface of the patterned high Al composition layer. After the sub-step c3) and the sub-step c2), at least a part of the low Al composition layer is exposed on the surface of the patterned high Al composition layer and the exposed surface of the low Al composition layer. , A method for manufacturing a semiconductor light emitting element, which includes a sub-step of forming the second electrode.

A semiconductor light emitting device including a current block layer having a novel structure is provided.

1A and 1B are cross-sectional views showing how a support layer is prepared. It is sectional drawing which shows the appearance of forming the optical semiconductor laminate and the 1st electrode on one surface of a support layer. 3A and 3B are cross-sectional views showing how a second electrode is formed on the other surface of the support layer. It is a top view which shows the shape of a current block layer, a 2nd electrode, and the like. It is sectional drawing which shows the state of mounting and packaging the manufactured semiconductor light emitting element.

A method of manufacturing a semiconductor light emitting device (LED chip) according to an embodiment will be described with reference to FIGS. 1 to 3. In the LED chip according to the embodiment, a support layer is prepared (FIG. 1), an optical semiconductor laminate and a first electrode are formed on one surface of the support layer (FIG. 2), and a second electrode is formed on the other surface of the support layer. It is produced by forming an electrode (Fig. 3).

1A and 1B are cross-sectional views showing how a support layer is produced.

As shown in FIG. 1A, a temporary substrate 1 made of GaAs is prepared. The main surface of the temporary substrate 1 is the (100) surface of GaAs. Further, the temporary substrate 1 is doped with Si to impart n-type conductivity, and its concentration is about 1 × 10 ¹⁸ cm ^-3 .

_{Al 0.6} Ga _{0.4 As layer 2 having a thickness of 10 μm and Al 0.3} Ga _0.7 As layer having a thickness of 250 μm are formed on the main surface of the temporary substrate 1 by liquid phase epitaxial growth (LPE). 3 is grown in order. These two layers will be referred to as a support layer (support substrate) 4.

The composition ratio of Al in the group III element of the AlGaAs layer 2 is higher than that of the AlGaAs layer 3. The AlGaAs layer 2 having a relatively high Al composition ratio may be referred to as a high Al composition layer. Further, the AlGaAs layer 3 having a relatively low Al composition ratio may be referred to as a low Al composition layer. It is desirable that the Al composition ratio of the high Al composition layer 2 is higher than 30% and the Al composition ratio of the low Al composition layer 3 is 30% or less.

LPE mainly includes a temperature difference method and a slow cooling method. Here, as will be described later, the temperature difference method is adopted. As the growth device, for example, a slide boat type device can be used. The AlGaAs layers 2 and ³ are doped with Te during growth so that the ^{Te concentrations are 10 17} cm ^-3 and 10 ¹⁸ cm -3, respectively.

The growth solution used was a solution of GaAs, Al and Te in a Ga solvent. The vertical temperature gradient of the growth solution filled in the melt tank is about 5 ° C./cm, and the temperature of the lower part of the growth solution in contact with the seed crystal is 850 to 950 ° C. The temperature and temperature gradient of the lower part of the growth solution are kept substantially constant during the growth.

As shown in FIG. 1B, a temporary substrate 1 made of GaAs is etched and removed. As a result, only the support layer 4 remains.

The temporary substrate 1 made of GaAs can be etched with an etching solution in which aqueous ammonia and aqueous hydrogen peroxide are mixed at a volume ratio of 1:20. At this time, the AlGaAs layer 2 having a high Al composition ratio functions as an etch stopper.

Next, the surface of the AlGaAs layer 3 is ground to reduce unevenness. Further, after polishing the ground surface to remove processing damage, the final finish is performed by chemical mechanical polishing (CMP). In general, a semiconductor layer grown by a temperature difference method has a poorer surface flatness than a semiconductor grown by a slow cooling method. The flatness of the surface can be improved by performing the final finish by CMP.

As described above, the support layer (support substrate, growth substrate) 4 is completed. The AlGaAs layer 2 having a high Al composition ratio (higher than 30%) is easily oxidized in an oxygen atmosphere. When the AlGaAs layer 2 is exposed to the atmosphere, its surface is instantly oxidized (natural oxidation).

FIG. 2 is a cross-sectional view showing a state in which an optical semiconductor laminate and a first electrode (p-side electrode) are formed on a surface of the support layer on the AlGaAs layer side having a relatively low Al composition ratio.

An active layer having an n-type current diffusion layer 5, an n-type clad layer 6, a first carrier confinement layer 7, and a multiple quantum well structure by metalorganic chemical vapor deposition (MOCVD) on the low Al composition layer 3. 8. The second carrier confinement layer 9, the p-type clad layer 10, the p-type current diffusion layer 11, and the p-type contact layer 12 are grown in this order. The laminated structure from the n-type current diffusion layer 5 to the p-type contact layer 12 is referred to as an optical semiconductor laminate 13. The optical semiconductor laminate has a structure in which at least a semiconductor layer imparted with n-type conductivity, an active layer having light emission (light emitting layer), and a semiconductor layer imparted with p-type conductivity are laminated.

The n-type current diffusion layer 5 is formed of Te-doped n-type Al _0.2 Ga _0.8 As, its thickness is about 2 μm, and its Te concentration is about 2 × 10 ¹⁸ cm ^-3 . .. The n-type clad layer 6 is formed of Te-doped n-type Al _0.4 Ga _0.6 As, its thickness is about 0.5 μm, and its Te concentration is about 2 × 10 ¹⁸ cm ^-3 . is there.

_{The first carrier confinement layer 7 is formed of Al 0.2} Ga _0.8 As which is not intentionally doped with impurities, and has a thickness of 500 nm. The background concentration of Te in the first carrier confinement layer 7 is 2 × 10 ¹⁶ cm ^-3 or less.

The active layer 8 has a multiple quantum well structure in which InGaAs is a well layer and AlGaAs is a barrier layer. Assuming that the structure in which the barrier layer sandwiches the well layer is one cycle, it is configured by stacking , for example, two cycles. The thickness of the well layer is about 11 nm, and the thickness of the barrier layer is about 11 nm.

_{The second carrier confinement layer 9 is formed of Al 0.2} Ga _0.8 As which is not intentionally doped with impurities, and has a thickness of 500 nm. The background concentration of C in the second carrier confinement layer 9 is 2 × 10 ¹⁶ cm ^-3 or less.

The p-type clad layer 10 is formed of C-doped p-type Al _0.4 Ga _0.6 As, has a thickness of about 1 μm, and has a C concentration of about 2 × 10 ¹⁸ cm ^-3 . The p-type current diffusion layer 11 is formed of C-doped p-type Al _0.2 Ga _0.8 As, its thickness is about 1 μm, and its C concentration is about 2 × 10 ¹⁸ cm ^-3 . .. The p-type contact layer 12 is formed of C-doped p-type GaAs, and its thickness is about 0.1 μm, and its C concentration is about 4 × 10 ¹⁸ cm ^-3 .

An indium tin oxide (ITO) layer / Ag layer / TiW layer / Ti layer / Au layer is laminated on the contact layer 12 in this order from the bottom to form a p-side electrode 15. The p-side electrode 15 is formed on almost the entire surface of the contact layer 12, for example, by wet etching and lift-off method.

As described above, the optical semiconductor laminate and the first electrode are formed on the surface of the AlGaAs layer (low Al composition layer) having a relatively low Al composition ratio.

3A and 3B are cross-sectional views showing how a second electrode (n-side electrode) is formed on the surface of the support layer on the AlGaAs layer side having a relatively high Al composition ratio. Hereinafter, the arrangement (lamination) relationship of the high Al composition layer 2 to the p-side electrode 15 is shown upside down.

As shown in FIG. 3A, a part of the high Al composition layer 2 composed of _{Al 0.6} Ga _{0.4 As is etched and removed.} As a result, a part of the low Al composition layer 3 is exposed, and a part 2a of the high Al composition layer patterned in a desired shape remains.

The high Al composition layer 2 has a shape (FIG. 4) described later by wet etching using a resist pattern as a mask. The _{high Al composition layer 2 composed of Al 0.6} Ga _0.4 As can be etched with an etching solution having a phosphoric acid: hydrogen peroxide solution of 1: 1.

The high Al composition layer 2 is easily oxidized in an oxygen atmosphere. When the patterned high Al composition layer 2a is exposed to the atmosphere, its surface (particularly the side surface exposed by patterning) is instantly oxidized (naturally oxidized). The high Al composition layer 2a whose surfaces (upper surface and side surfaces) are oxidized electrically functions as an insulator.

Here, for convenience, in the optical semiconductor laminate 13, the region corresponding to the patterned high Al composition layer 2a is referred to as the first region 13a. Further, the surrounding area excluding the first area 13a is referred to as a second area 13b.

As shown in FIG. 3B, an n-side electrode 16 in which a Ni layer, a Ge layer, and an Au layer are laminated in this order from the bottom is formed on the high Al composition layer 2a and the low Al composition layer 3. The n-side electrode 16 has a shape (FIG. 4) described later by the lift-off method.

As described above, the second electrode is formed on the surface of the AlGaAs layer (high Al composition layer) having a relatively high Al composition ratio. Then, the LED chip according to the embodiment is completed.

FIG. 4 is a plan view showing the shapes of the high Al composition layer 2a and the n-side electrode 16. The planar shape of the LED chip (or low Al composition layer 3) according to the examples is, for example, a square having a side of 1 mm.

The patterned high Al composition layer 2a is provided, for example, substantially in the center of the low Al composition layer 3. The planar shape of the high Al composition layer 2a is, for example, circular. The patterned high Al composition layer may be rectangular or may be composed of a plurality of patterns that are separated from each other.

The n-side electrode 16 is formed so as to straddle the high Al composition layer 2a and the low Al composition layer 3, and is continuous with, for example, the main portion 16a arranged on the high Al composition layer 2 and the main portion 16a. , A branch portion 16b extending radially, and the like. The n-side electrode 16 is formed by exposing at least a part of the low Al composition layer 3.

FIG. 5 is a cross-sectional view showing how the LED chip according to the embodiment is mounted and packaged.

The p-side electrode 15 of the LED chip is die-bonded to the fixed electrode (mounting substrate) 18. By this die bonding, the fixed electrode 18 and the p-side electrode 15 are electrically and mechanically bonded.

Further, an electrode (not shown) and an electrode 16 on the n-side of the LED chip are wire-bonded with a bonding wire 19 to electrically connect them to each other. The bonding wire 19 is bonded to the position of the n-side electrode 16 corresponding to the high Al composition layer 2a (main portion 16a of the n-side electrode in FIG. 4).

A forward bias is applied between the p-side electrode 15 and the n-side electrode 16 via the fixed electrode 18 and the bonding wire 19 (an electrode (not shown) connected to the fixed electrode 18), and the carrier is injected into the active layer 8 (current). Is generated to emit light in the infrared region (wavelength 950 nm). The light emitted from the active layer (light emitting layer) 8 is mainly emitted from the region of the low Al composition layer 3 where the n-side electrode 16 is not formed (the region where the low Al composition layer 3 is exposed). (See Fig. 4).

The surface of the high Al composition layer 2a is oxidized, and it electrically functions as an insulator. Here, the high Al composition layer 2a functions as a current block layer. That is, the high Al composition layer 2a suppresses the concentrated flow of current to the optical semiconductor laminate 13 (first region 13a in FIG. 3A) located below the bonding wire 19, and is located around the optical semiconductor stacking 13 (1st region 13a in FIG. 3A). The optical semiconductor stack 13 (second region 13b in FIG. 3A) is attracted so that a more current flows.

Generally, the bonding wire has a light-shielding property (absorbency). Light emission is suppressed in the light emitting layer (active layer 8 included in the first region 13a in FIG. 3A) located below the bonding wire, and the light emitting layer located around the light emitting layer (second in FIG. 3A). By promoting the light emission of the active layer 8) included in the region 13b, more light generated in the light emitting layer can be emitted to the outside of the element without being absorbed by the bonding wire. That is, the external quantum efficiency (light extraction efficiency) of the LED chip can be improved.

The high Al composition layer functions as an etch stopper when the temporary substrate made of GaAl is etched and removed (see FIG. 1B). Further, after patterning into a desired shape, the surface is naturally oxidized to function as a current block layer. In the LED chip according to the embodiment, it is not necessary to separately form an insulating layer, a conductive layer (Schottky barrier layer), or the like in order to provide the current block layer.

Although the present invention has been described above based on Examples, the present invention is not limited thereto. It will be obvious to those skilled in the art that various changes, improvements, combinations, etc. are possible.

1 ... Temporary substrate, 2 ... High Al composition layer, 3 ... Low Al composition layer, 4 ... Support layer (support substrate), 5 ... n-type current diffusion layer, 6 ... n-type clad layer, 7 ... First carrier closure Embedded layer, 8 ... active layer (quantum well structure layer), 9 ... second carrier confining layer, 10 ... p-type clad layer, 11 ... p-type current diffusion layer, 12 ... p-type contact layer, 13 ... optical semiconductor Lamination, 15 ... p side electrode, 16 ... n side electrode, 18 ... fixed electrode (mounting substrate), 19 ... bonding wire.

Claims (4)

High Al composition layer step a) the Al composition ratio is mainly a high AlGaAs than 30%, and a support layer low Al composition layer Al composition ratio is mainly a lower AlGaAs than 30%, it is formed by stacking And the process of preparing
Step b) A step of forming a light-emitting optical semiconductor laminate and a first electrode on the surface of the support layer on the low Al composition layer side.
Step c) A step of forming a second electrode on the surface of the support layer on the high Al composition layer side, and
Have,
In step c),
Sub-step c1) In the support layer, a sub-step of patterning the high Al composition layer to expose the low Al composition layer to a region from which the high Al composition layer has been removed.
Sub-step c2) A sub-step that naturally oxidizes the surface of the patterned high Al composition layer,
Sub-step c3) After the sub-step c2), at least a part of the low Al composition layer is exposed on the surface of the patterned high Al composition layer and the exposed surface of the low Al composition layer. The sub-process of forming the second electrode and
including,
A method for manufacturing a semiconductor light emitting device. In step a),
Sub-step a1) A sub-step in which the high Al composition layer and the low Al composition layer are sequentially laminated on the surface of a temporary substrate mainly composed of GaAs.
Sub-step a2) A sub-step of etching and removing the temporary substrate using the high Al composition layer as an etch stopper.
The method for manufacturing a semiconductor light emitting device according to claim 1. In the step b), the optical semiconductor laminate has a structure in which at least an n-type AlGaAs layer, an InGaAs layer as a well layer, a quantum well layer having an AlGaAs layer as a barrier layer, and a p-type AlGaAs layer are laminated. The method for manufacturing a semiconductor light emitting device according to claim 1 or 2. Step d) The method for manufacturing a semiconductor light emitting device according to any one of claims 1 to 3, further comprising a step of connecting wiring to a position corresponding to the patterned high Al composition layer of the second electrode. ..

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