JP6884688B2 - Capacitor charger - Google Patents

Description

According to the present invention, a high-power main charger and a low-power auxiliary charger are used in combination to charge a capacitor. Especially in the first half of the charging period, the capacitor is charged only by the output voltage of the main charger. In the latter half of the charging period, the capacitor is charged only by the output voltage of the auxiliary charger, and when switching from charging with the former main charger to charging with the latter auxiliary charger, charging with the main charger and charging with the auxiliary charger The present invention relates to a charging type condenser charger that overlaps with.

Conventionally, the capacitor is charged by both the output voltage of the main charger and the output voltage of the auxiliary charger in the first half of the charging period, and the capacitor is charged only by the output voltage of the auxiliary charger in the latter half of the charging period. Capacitor chargers are known (see, for example, Patent Document 1).

However, in the case of the above-mentioned conventional technique, since the capacitor is charged by both the output voltage of the main charger and the output voltage of the auxiliary charger in the first half of the charging period, the capacitor charging voltage is the target charging voltage from the base level. It is difficult to obtain the lamp (tilt) characteristics of the desired boost pattern in the process of rising to, and in the process of switching from the charging mode of both the main charger and the auxiliary charger to the charging mode of the auxiliary charger alone, the capacitor is charged. There is a problem that the desired high stability cannot be obtained for the voltage.

Therefore, in order to solve such a problem, the capacitor is charged only by the output voltage of the main charger in the first half of the charging period, and the capacitor is charged only by the output voltage of the auxiliary charger in the latter half of the charging period. When switching from charging with the former main charger to charging with the latter auxiliary charger, a charging method in which charging by the main charger and charging by the auxiliary charger overlap is conceivable. This switching-time overlap type capacitor charging device will be described below as a comparative example.

FIG. 6 is a circuit diagram showing a configuration of an overlapping type capacitor charging device at the time of switching of a comparative example, and FIG. 7 is a waveform diagram illustrating the operation of the capacitor charging device.

(1) Operation in period T1 (timing t1 to t2) In period T1, the capacitor C1 is charged only by the main charger J1, and the first determination device H1 outputs a closing signal (on signal). , The first gate circuit G1 is in the closed state (on state). The second determination device H2 outputs an open signal (off signal), and the second gate circuit G2 is in the open state (off state). The first regulator B1 configured by the differential amplifier OP1 takes the difference between the pattern voltage Vp and the capacitor charging voltage Vc, and sets the difference voltage ΔVp-c (= Vp −Vc) as the first control amount V _c1. Output to the first gate circuit G1. The first control amount V _c1 is given to the main charger J1 via the first gate circuit G1 in the closed state. Similarly, the second regulator B2 configured by the differential amplifier OP2 also outputs the difference voltage ΔVp-c to the second gate circuit G2 as the second _{control amount V c2.} However, since the second gate circuit G2 is in the open state, the second control amount V _c2 is not given to the auxiliary charger J2.

In this comparative example, the second control amount V _{c2 with} respect to the auxiliary charger J2 is a fixed value at an excessively high level without adjusting the control amount as shown in FIG. 7 (c). This second control amount V _c2 is an output as a preparatory step that is immediately given to the auxiliary charger J2 when the second gate circuit G2 is switched to the closed state by the second determination device H2. It is in a standby state.

The main charger J1 is in the driving state because the first gate circuit G1 is in the closed state, while the auxiliary charger J2 is in the stopped state because the second gate circuit G2 is in the open state. _{The main charger J1 given the first control amount V c1} from the first gate circuit G1 in the closed state outputs the output voltage V _J1 corresponding to the first control amount V _c1 . The current due to the output voltage V _J1 charges the capacitor C1 via the resistance element R1 for current limiting, the diode D1 for preventing backflow, and the resistance element R3 for current limiting.

The capacitor charging voltage Vc gradually rises with the passage of time, and the output voltage V _J1 also gradually rises accordingly. The main charger J1 _{raises the output voltage V J1} to be output under a constant boost coefficient with the passage of time. As the output voltage V _J1 of the main charger J1 rises, the capacitor charging voltage Vc also rises under a constant boost coefficient. At each timing, the capacitor charging voltage Vc changes at a _{level lower than the output voltage V J1} output by the main charger J1 by a small voltage that is almost constant. The reason why the small voltage is almost constant and the low level is due to the voltage drop in the resistance elements R1 and R3 for current limiting.

(2) Operation in period T2 (timing t2 to t3) At timing t2, when the auxiliary charger J2 charges the capacitor C1 in addition to the main charger J1, the state of the second determination device H2 is reversed. Then, a closing signal is output to the second gate circuit G2, and the second gate circuit G2 is switched to the closed state. At this time, the second regulator B2 has already _{output the second control amount V c2} , and the second control amount V _c2 is switched to the closed state via the second gate circuit G2 with low power consumption. It is given to the auxiliary charger J2.

During the period T2, both the high-power main charger J1 and the low-power auxiliary charger J2 are in the driving state. The main charger J1 supplies the output voltage V _J1 under the first control amount V _c1 , and the auxiliary charger J2 simultaneously supplies the output voltage V _{J2 under the second control amount V c2.} To do. This period T2 has a sufficiently shorter time width than the previous period T1 and the later period T3.

During the period T2 in which the auxiliary charger J2 is driven from the stopped state and the main charger J1 and the auxiliary charger J2 are both driven, the output voltage V _J2 of the auxiliary charger J2 rises sharply, and the first and first _{The target charging voltage V T} , which is the flat top level of the pattern voltage Vp given to the regulators B1 and B2 of 2, may be exceeded.

(3) Operation at the final timing t3 of the period T2 When the charging by the main charger J1 is stopped at the timing t3, the state of the first determination device H1 is reversed with respect to the first gate circuit G1. The opening signal is output, and the first gate circuit G1 is switched to the opening state. As a result, the main charger J1 stops the output. After that, the capacitor C1 is charged only by _{the output voltage V J2 of the auxiliary charger J2.}

To summarize the above transition period by only the output voltage V _J1 of the T1 primary charger J1 is done charging of the capacitor C1, the output voltage of the output voltage V _J1 and auxiliary charger J2 period in T2 primary charger J1 The capacitor C1 is charged in cooperation with _{V J2, and the output voltage V J1} of the main charger J1 is stopped at the timing t3. Therefore, during the period T3, the capacitor C1 is _{charged only by the output voltage V J2 of the auxiliary charger J2.} Is charged. The period T2 is a very short time width, but in this period T2, the charging with high power by the main charger J1 and the charging with low power by the auxiliary charger J2 are performed in parallel (overlap) (hereinafter, "" At the end of the parallel drive period (referred to as "parallel drive period") and the parallel drive period T2, the charging state is switched only by the auxiliary charger J2.

JP-A-2007-124807

When applied to an electromagnet power supply, the stability of the capacitor charging voltage may be required to be about 1% before the capacitor is fully charged, and about 0.01% when the capacitor is fully charged. .. The voltage waveform leading to full charge is indicated by a pattern command, and the charger must control according to that pattern. In a highly stable control state (when fully charged), the capacitor is discharged by closing a switch such as a thyristor, and charging is restarted. The charge / discharge cycle is 1 to 3 seconds.

However, in the above comparative example, at the timing t2 at the beginning of the parallel drive period T2, _{the level of the second control amount V c2 to} be given to the auxiliary charger J2 is excessively high as shown in FIG. 7 (c). It is a fixed value at the level. It has a higher than necessary as compared with the optimum level corresponding to the target charge voltage V _T is a flat top level for the capacitor charging voltage Vc. This is because the auxiliary charger J2 was directly controlled via the second gate circuit G2 based on _{the second controlled variable} V c2 from the second regulator B2. In this way, the auxiliary charger J2 is provided with _{the second control amount V c2} which remains at a fixed value at an excessively high level without adjusting the control amount. As shown in the parallel drive period T2, there is a problem that the feedback control amount V _FB with respect to the capacitor charge voltage Vc runs out of control, and the stability is impaired due to the large distortion of the charge voltage waveform even in the period T3.

Note that I ₁ is the charging current of the main charger J _{1 and I 2} is the charging current of the auxiliary charger J 2.

The present invention has been made in view of such circumstances, and it is possible to obtain a lamp characteristic of a desired boost pattern in the process of increasing the capacitor charging voltage from the base level to the target charging voltage, and in the process of switching. The purpose is to suppress / avoid runaway of the feedback control amount with respect to the capacitor charging voltage, and to obtain the desired high stability with respect to the capacitor charging voltage.

The present invention solves the above problems by taking the following measures.

The capacitor charging device according to the present invention
A first charging circuit with a high power main charger and a second charging circuit with a low power auxiliary charger connected in parallel to the capacitors to be charged, and
For controlling the output voltage of the main charger in the first charging circuit, input the difference voltage between the pattern voltage that rises from the base level and transitions to the target charging voltage level and the capacitor charging voltage detected for the capacitor. The first adjustment control amount of the result calculated by the predetermined increase / decrease rate is generated, and the first adjuster in which the increase / decrease rate can be changed, and the first adjuster.
A first gate circuit inserted between the output side of the first regulator and the control terminal of the main charger, and
The capacitor charging voltage is compared with the first threshold voltage, and when it is equal to or less than the first threshold voltage, a closing signal is output to the first gate circuit, and when it exceeds the first threshold voltage, the first threshold voltage is output. The first judgment device that outputs the opening signal to the gate circuit of 1 and
For controlling the output voltage of the auxiliary charger in the second charging circuit, a second adjustment control amount as a result of inputting the difference voltage and calculating with a predetermined increase / decrease rate is generated, and the increase / decrease rate is generated. With a second adjuster that can be changed,
A second gate circuit inserted between the output side of the second regulator and the control terminal of the auxiliary charger, and
The capacitor charging voltage is compared with the second threshold voltage set lower than the first threshold voltage, and when it is equal to or less than the second threshold voltage, an opening signal is output to the second gate circuit. When the second threshold voltage is exceeded, a second determination device that outputs a closing signal to the second gate circuit is provided.

According to the above configuration of the present invention, the following actions are exhibited.

In the first half of the charging period, the capacitor is charged only by the output voltage of the main charger without using the output voltage of the auxiliary charger, and in the second half of the charging period, the output of the auxiliary charger is not used. The capacitor is charged only by the voltage, and in the parallel drive period from charging by the former main charger to charging by the latter auxiliary charger, it is premised on a charging method that overlaps charging by the main charger and charging by the auxiliary charger. There is.

In such a charging method, without using the above-mentioned regulator, the difference voltage (control amount) between the pattern voltage and the capacitor charging voltage is not adjusted, and the output is output to the gate circuit while maintaining an excessively high level. In this case, the control amount changes abnormally in the switching process, and the desired high stability of the capacitor charging voltage cannot be obtained (in the case of lack of the second regulator related to the auxiliary charger). At the same time, in the process of increasing the capacitor charging voltage from the base level to the target charging voltage, the lamp-like characteristics of the ideal desired boost pattern cannot be obtained (in the case of lack of the first regulator related to the main charger). ..

On the other hand, in the case of the present invention, a first regulator and a second regulator whose increase / decrease rate can be changed are provided. Therefore, if the rate of increase / decrease corresponding to the desired pattern voltage for the capacitor charging voltage is set in the first and second regulators and prepared so as to be the first and second adjustment control amounts, respectively, the capacitor is charged. Obtain the ramp-like characteristics of the desired boost pattern in the process of the voltage rising from the base level to the target charging voltage, and obtain the voltage characteristics that match the target charging voltage (flat top level of the pattern voltage) with high accuracy. It becomes possible. At the same time, in the process of switching, the runaway of the feedback control amount with respect to the capacitor charging voltage is suppressed / avoided, and it becomes possible to obtain a desired high stability with respect to the capacitor charging voltage.

The capacitor charging device of the present invention having the above configuration has some preferable modes or variations / modifications as follows.

[1] As the means for generating the differential voltage, a first differential amplifier for controlling the output voltage of the main charger and a second differential amplifier for controlling the output voltage of the auxiliary charger are provided. There is an aspect that it is.

[2] Further, as the means for generating the difference voltage, it is said that a single differential amplifier that also controls the output voltage of the main charger and the output voltage of the auxiliary charger is provided. There is an aspect.

[3] Further, there is an embodiment in which the pattern voltage is set to a waveform that rises in a lamp shape from the base level and changes so as to converge from the lamp apex to a target charging voltage level of a certain level. With this configuration, it has a ramp-like characteristic that gradually increases linearly from the base level, and by using a pattern voltage with variable adjustment of the rate of increase / decrease, the maximum value of the tilt apex is the desired optimum. It is possible to adjust to the value (target charging voltage) with high accuracy.

[4] Further, in the first adjuster and the second adjuster, the increase / decrease rate of either one of the variable increase / decrease rates is preferentially fixed to a predetermined value, and the increase / decrease rate of the other is fixed. There is an aspect that it is configured to be adjusted.

[5] Further, of the first regulator and the second regulator, the regulator whose increase / decrease rate is preferentially fixed to a predetermined value is the second regulator, and is described above. There is an aspect that the adjuster whose increase / decrease rate is adjusted is the first adjuster. When the increase / decrease rate of the second adjuster is preferentially fixed to a predetermined value and then the increase / decrease rate of the first adjuster is adjusted, the target charging voltage is set with respect to the flat top level of the pattern voltage. It is possible to approach the accuracy sufficiently.

According to the present invention, since the first regulator and the second regulator are provided, the lamp characteristics of a desired boost pattern can be obtained in the process of the capacitor charging voltage rising from the base level to the target charging voltage. At the same time, it is possible to obtain voltage characteristics that match the target charging voltage with high accuracy. That is, it is possible to suppress / avoid runaway of the feedback control amount with respect to the capacitor charging voltage in the process of switching, and obtain a desired high stability with respect to the capacitor charging voltage.

A circuit diagram showing a configuration of a capacitor charging device according to a first embodiment of the present invention. Waveform diagram showing the operation of the capacitor charging device according to the first embodiment of the present invention. A timing chart showing the transition of the capacitor charging voltage and the operating state of the first and second gate circuits in the capacitor charging device according to the first embodiment of the present invention. In the first embodiment, a circuit diagram showing a specific configuration example of the first regulator and the second regulator. A circuit diagram showing a configuration of a capacitor charging device according to a second embodiment of the present invention. A circuit diagram showing the configuration of an overlapping type capacitor charging device when switching a comparative example. Waveform diagram explaining the operation of the capacitor charging device of the comparative example

Hereinafter, embodiments of the capacitor charging device of the present invention having the above configuration will be described in detail at the level of specific examples.

[First Example]
FIG. 1 is a circuit diagram showing a configuration of a capacitor charging device according to a first embodiment of the present invention. In FIG. 1, 10 is a first charging circuit, 20 is a second charging circuit, 30 is a load circuit, J1 is a high-power main charger, J2 is a low-power auxiliary charger, and C1 is a capacitor to be charged. R1, R2, R3 are current limiting resistor elements, D1 and D2 are backflow prevention diodes, A1 is the first regulator, A2 is the second regulator, G1 is the first gate circuit, and G2 is the first. The gate circuit of 2, H1 is a first determination device, H2 is a second determination device, and S1 is a switch element for discharge.

The positive electrode terminal of the capacitor C1 is connected to the positive electrode terminal of the main charger J1 via the current limiting resistance element R1, the backflow prevention diode D1 and the current limiting resistance element R3, and the negative electrode terminal of the capacitor C1 is the main charger J1. It is connected to the negative electrode terminal of. Similarly, the positive electrode terminal of the capacitor C1 is connected to the positive electrode terminal of the auxiliary charger J2 via the current limiting resistance element R2, the backflow prevention diode D2, and the current limiting resistance element R3, and the negative electrode terminal of the capacitor C1. Is connected to the negative electrode terminal of the auxiliary charger J2. A load circuit 30 is connected between the bipolar terminals of the capacitor C1 via a switch element S1 such as a thyristor.

The first regulator A1 inputs the difference voltage between the preset pattern voltage Vp and the detected capacitor charging voltage Vc for controlling the output voltage of the main charger J1 in the first charging circuit 10. _{The first adjustment control amount V c1} ′, which is the result calculated by the predetermined increase / decrease rate K1, is generated, and the increase / decrease rate K1 is variably configured. The pattern voltage Vp is a pattern that rises from the base level and changes to the level of the target charging voltage _VT (see FIG. 3).

The output terminal of the first regulator A1 is connected to the input terminal of the first gate circuit G1. The first determination device H1 compares the detected capacitor charging voltage Vc with the first threshold voltage V _tH, and controls the opening and closing of the first gate circuit G1 according to the comparison result, and its output terminal is the first. It is connected to the control terminal of the gate circuit G1 of. The output terminal of the first gate circuit G1 is connected to the control terminal of the main charger J1. When the capacitor charging voltage Vc is _{equal to or lower than the first threshold voltage V tH} , the first determining device H1 outputs a closing signal (on signal) as a control signal for the first gate circuit G1, and the capacitor charging voltage Vc becomes When the first threshold voltage V _tH is exceeded, an opening signal (off signal) is output as a control signal for the first gate circuit G1.

Similar to the above, the second regulator A2 inputs the difference voltage between the pattern voltage Vp and the detected capacitor charging voltage Vc to control the output voltage of the auxiliary charger J2 in the second charging circuit 20. _{The second adjustment control amount V c2} ′, which is the result calculated by the increase / decrease rate K2 of, is generated, and the increase / decrease rate K2 is variably configured.

The output terminal of the second regulator A2 is connected to the input terminal of the second gate circuit G2. The second determination device H2 compares the detected capacitor charging voltage Vc with the second threshold voltage V _tL, and controls the opening and closing of the second gate circuit G2 according to the comparison result, and its output terminal is the second. It is connected to the control terminal of the gate circuit G2 of. The output terminal of the second gate circuit G2 is connected to the control terminal of the auxiliary charger J2. When the capacitor charging voltage Vc is _{equal to or less than the second threshold voltage V tL} , the second determining device H2 outputs an opening signal (off signal) as a control signal for the second gate circuit G2, and the capacitor charging voltage Vc is the second. When the threshold voltage V _tL of 2 is exceeded, a closing signal (on signal) is output as a control signal for the second gate circuit G2.

The first threshold voltage V _{t H} is set to a voltage level that is lower than the _{target charging voltage V T,} which is the flat top level of the pattern _{voltage V p, and is extremely close to the target charging voltage V T.} The second threshold voltage V _tL is lower than the first threshold voltage V _tH, and to a lesser extent the first threshold voltage V _tH, is set fairly close voltage level to the target charging voltage V _T. For example, the first threshold voltage V _tH is set to 99.9% level of the target charging voltage V _T, the second threshold voltage V _tL is set to 99.0% level of the target charging voltage V _T. For example, when the target charging voltage V _T is 6,000 [V], the first threshold voltage V _tH is 5,994 [V] and the second threshold voltage V _tL is 5,940 [V]. .. The operation logic of the second determination device H2 is the reverse of the operation logic of the first determination device H1.

Figure 2 is a waveform diagram for explaining the operation of the capacitor charger, it detected relationship between the output voltage V _J2 from the output voltage V _J1 and the auxiliary charger J2 from the capacitor charged voltage Vc and the main charger J1 (Fig. 2 (a)), _{the transition of the charging current I 1} by the main charger J1, the transition of the charging current I ₂ by the auxiliary charger J2 (FIG. 2 (b)), and the transition of the second adjustment control amount V _c2 ′ (FIG. 2 (Fig. 2)). c)) is shown. FIG. 3 is a timing chart showing the transition of the capacitor charging voltage Vc and the operating states of the first and second gate circuits G1 and G2.

The boosting of the capacitor charging voltage Vc is started at the timing t1. The timing t2 is the timing when the second threshold voltage V _tL where the capacitor charging voltage Vc is lower is reached, and the timing t3 is the timing when the first threshold voltage V _tH where the capacitor charging voltage Vc is higher is reached. The timing t4 is the timing at which the capacitor C1 is discharged and the capacitor charging voltage Vc drops rapidly. The timings t1 to t2 are defined as the period T1, the timings t2 to t3 are defined as the period T2, the timings t3 to t4 are defined as the period T3, and the period from the timing t4 to the equivalent of the timing t1 in the next cycle is defined as the period T4.

Next, the operation will be described in chronological order.

At the timing t1, the main charger J1 is in the driving state and the auxiliary charger J2 is in the stopped state. At the timing t2, the auxiliary charger J2 is in the driving state, and at the timing t3, the main charger J1 is in the stopped state. At the timing t4, the auxiliary charger J2 is also stopped.

That is, first, during the period T1 of the timings t1 to t2, the main charger J1 is in the driving state and the auxiliary charger J2 is in the stopped state. During the period T2 of the timings t2 to t3, the main charger J1 is continuously in the driving state, and the auxiliary charger J2 is in the driving state. During the period T3 of the timings t3 to t4, the main charger J1 is in the stopped state, and the auxiliary charger J2 is subsequently in the driven state. In the period T4 from the timing t4 to the timing corresponding to the timing t1 in the next cycle, both the main charger J1 and the auxiliary charger J2 are in the stopped state.

Here, the state change of each component in each of the above periods T1, T2, T3, T3, and T4 will be described.

(1) Operation in period T1 (timing t1 to t2) In period T1, the capacitor charging voltage Vc is equal to or less than _{the second threshold voltage V tL} (of course, lower than _{the first threshold voltage V tH).} The first determination device H1 outputs a closing signal, and the first gate circuit G1 is in a closed state (on state). The second determination device H2 outputs an open signal, and the second gate circuit G2 is in the open state (off state).

The first regulator A1 _{outputs the first adjustment control amount V c1} ′ to the first gate circuit G1. The first adjustment control amount V _c1 ′ is given to the main charger J1 via the first gate circuit G1 in the closed state. The second regulator A2 _{outputs the second adjustment control amount V c2} ′ to the second gate circuit G2. However, since the second gate circuit G2 is in the open state, the second adjustment control amount V _c2 ′ is not given to the auxiliary charger J2.

The main charger J1 is in the driving state because the first gate circuit G1 is in the closed state, while the auxiliary charger J2 is in the stopped state because the second gate circuit G2 is in the open state. _{The main charger J1 given the first adjustment control amount V c1} ′ from the first gate circuit G1 in the closed state outputs the output voltage V _J1 corresponding to the first adjustment control amount V _{c1 ′.} .. The current due to the output voltage V _J1 charges the capacitor C1 via the resistance element R1 for current limiting, the diode D1 for preventing backflow, and the resistance element R3 for current limiting. The capacitor charging voltage Vc gradually rises with the passage of time, and the output voltage V _J1 also gradually rises accordingly. The main charger J1 _{raises the output voltage V J1} to be output under a constant boost coefficient with the passage of time. As the output voltage V _J1 of the main charger J1 rises, the capacitor charging voltage Vc also rises under a constant boost coefficient. At each timing, the capacitor charging voltage Vc changes at a _{level lower than the output voltage V J1} output by the main charger J1 by a small voltage that is almost constant. The low level by a substantially constant small voltage is due to the voltage drop in the resistance elements R1 and R3 for current limiting and the diode D1 for preventing backflow.

The output voltage V _J1 of the main charger J1 gradually increased under certain boost coefficient following the first adjustment control quantity V _c1 ', which is adjusted by the first regulator A1, the first adjustment The control amount V _c1 ′ is adjusted by varying the increase / decrease rate K1.

(2) Operation in period T2 (timing t2 to t3) At timing t2, when the rising capacitor charging voltage Vc reaches the second threshold voltage V _tL , the state of the second determination device H2 is inverted. A closing signal is output to the second gate circuit G2, and the second gate circuit G2 is switched to the closed state. At this time, the second regulator A2 'and outputs, the second adjustment control quantity V _c2' already second adjustment control quantity V _c2 and the second gate circuit G2 that is switched to a closed state It is given to the low power auxiliary charger J2 via.

During the period T2, both the high-power main charger J1 and the low-power auxiliary charger J2 are in the driving state. The main charger J1 supplies the output voltage V _J1 under the first adjustment control amount V _c1 ′, and the auxiliary charger J2 simultaneously supplies the _{output voltage under the second adjustment control amount V c2} ′. Supply V _J2. This period T2 has a sufficiently shorter time width than the previous period T1 and the later period T3.

The operation during the period T2 in which the auxiliary charger J2 is changed from the stopped state to the drive state and the main charger J1 and the auxiliary charger J2 are both driven has the following characteristics.

_{The first adjustment control amount V c1} ′ output by the first regulator A1 to the main charger J1 via the first gate circuit G1 is the increase / decrease rate K1 in the first regulator A1, the pattern voltage Vp, and the capacitor. Using the charging voltage Vc,
V _c1 ′ = (Vp −Vc) ・ K1 = ΔVp-c ・ K1
Will be.

By adjusting the change ratio K1 of the first regulator A1 in this way, based on the desired boost factor in the process of capacitor charging voltage Vc rises from the ground level of the pattern voltage Vp to the target charge voltage V _T It is possible to obtain the ramp-like characteristics of the step-up pattern in.

_{Further, the second adjustment control amount V c2} ′ output by the second regulator A2 to the auxiliary charger J2 via the second gate circuit G2 is the increase / decrease rate K2 in the second regulator A2 and the pattern voltage Vp. And using the capacitor charging voltage Vc,
V _c2 ′ = (Vp −Vc) ・ K2 = ΔVp-c ・ K2
Will be.

By adjusting the increase / decrease rate K2 in the second regulator A2 in this way, the capacitor charging voltage Vc is finally matched with high accuracy to the _{target charging voltage V T which is the flat top level of the pattern voltage Vp.} It becomes possible.

In the above equation, the values of the increase / decrease rates K1 and K2 are K1> 1 and K2> 1 when the increase rate is used, and K1 <1, K2 <1 when the decrease rate is used.

In the period T2, the output voltage V _J2 of the auxiliary charger J2 rises sharply and may exceed the _{target charging voltage V T} , which is the flat top level of the pattern voltage Vp. _{In this case, the output voltage V J1} of the main charger J1 drops a little in order to compensate for the capacitor charging voltage Vc.

(3) Operation at the final timing t3 of the period T2 When the rising capacitor charging voltage Vc reaches the first threshold voltage V _tH at the timing t3, the state of the first determination device H1 is reversed and the first An open signal is output to the gate circuit G1 of the above, and the first gate circuit G1 is switched to the open state. As a result, the main charger J1 stops the output. After that, the capacitor C1 is charged only by _{the output voltage V J2 of the auxiliary charger J2.}

To summarize the transition up to this point, in the period T1, the _{capacitor C1 is charged only by the output voltage V J1 of the} main charger J1, and in the period T2, the output voltage V _J1 of the main charger J1 and the output of the auxiliary charger J2 are used. The capacitor C1 is charged in cooperation with the voltage V _{J2, and the output voltage V J1} of the main charger J1 is stopped at the timing t3. Therefore, during the period T3, the capacitor is _{charged only by the output voltage V J2 of the auxiliary charger J2.} The C1 is charged. The period T2 is a very short time width, but at the end of the period (timing t3) after the main charger J1 charges with high power and the auxiliary charger J2 charges with low power during this period T2. Switching to the charging state with low power is performed only by the auxiliary charger J2. At the beginning timing t2 of the parallel drive period T2, _{the level of the second adjustment control amount V c2} ′ to be given to the auxiliary charger J2 is adjusted by the increase / decrease rate K2, and is a flat top level for the capacitor charging voltage Vc. Since the optimum level corresponding to the charging voltage V _{T can be obtained, the runaway of the feedback control amount V FB with} respect to the capacitor charging voltage V c as in the comparative example does not occur, and it is possible to avoid this.

_{Incidentally, in the comparative example shown in FIGS. 6 and 7, the second control amount V c2} is at an excessively high level without being adjusted from the timing t1 at the beginning of the period T1 to the timing t3 at the beginning of the period T3. _Therefore, there is a problem that the feedback control amount V FB with respect to the capacitor charging voltage Vc causes a runaway during the parallel drive period T2. On the other hand, in the case of the embodiment of the present invention, with respect to the transition pattern of the capacitor charging voltage Vc, a lamp (inclination) characteristic (boost) that linearly increases from the base level through variable adjustment of the increase / decrease rate K1 in the first regulator A1. the boost factor) in the process in the desired optimum properties and that the target charge voltage V _T is the highest value of the slope vertexes through the variable adjustment of the percentage change K2 in the second regulator A2 Komu accordance with a desired optimum value it can. That is, it is possible to prevent the inconvenience of runaway of the _{feedback control amount V FB with} respect to the capacitor charging voltage Vc in the parallel drive period T2 assumed in the comparative example.

(4) Operation in period T3 (timing t3 to t4) In period T3, charging by the high-power main charger J1 is completed, and charging is performed only by the low-power auxiliary charger J2. Capacitor charging voltage Vc has reached almost up to the target charge voltage V _T, yet because of the low power charge, the amplitude of the differential voltage? Vp-c is sufficiently small. Therefore, the capacitor charge voltage Vc is at the very vicinity of the target charge voltage V _T, repeated vertical movement transition in a very short period.

Change ratio K1 of the first regulator A1 is related to the boost coefficient in ramp form characteristic pattern voltage Vp of the capacitor charging voltage Vc slide into linearly increases from the base level to the target charge voltage V _T. That is, the smaller the increase / decrease rate K1 is, the smaller the boosting coefficient is, and the larger the increase / decrease rate K1 is, the larger the boosting coefficient is.

On the other hand, the increase / decrease rate K2 in the second regulator A2 is related to the _{target charging voltage V T, which is the flat top level of the pattern voltage Vp for the capacitor charging voltage Vc.} That is, change ratio K2 becomes larger difference between the higher target charging voltage V _T is small, the difference between the larger change ratio K2 target charge voltage V _T decreases.

Then, the adjustment of the increase / decrease rate K1 in the first regulator A1 and the adjustment of the increase / decrease rate K2 in the second adjuster A2 can be arbitrarily performed in a state of being independent of each other. Therefore, the level of adjustment of the adjustment and the target charge voltage V _T of the step-up factor in the lamp-shaped characteristic of the capacitor charging voltage Vc, can be carried out optionally in a state independent from each other. Therefore, it is possible to reliably prevent the _{feedback control amount V FB} from running out of control in the process of switching from the charging period T1 of the capacitor C1 to the parallel driving period T2 only by the main charger J1.

In the above, the adjustment of the increase / decrease rate K1 (adjustment of the boosting coefficient in the lamp-like characteristic of the capacitor charging voltage Vc) and the adjustment of the increase / decrease rate K2 (adjustment of the difference amount with respect to the _{target charging voltage V T) are arbitrarily independent of each other.} Although it has been explained that this can be performed, as for the procedure for adjusting the increase / decrease rate K1 and the increase / decrease rate K2, a method of preferentially fixing the increase / decrease rate K2 to a predetermined value and then adjusting the increase / decrease rate K1 is preferable. That is, the change ratio K2 is a factor in determining the level of the target charging voltage V _T, the target charge voltage V _T are those corresponding to the flat top-level pattern voltage Vp. Since this flat top level is the most important factor for adjusting the level of the capacitor charging voltage Vc to be controlled, it is desirable to prioritize the determination of the _{target charging voltage V T.} If the target charging voltage V _T is determined first, and then the boosting coefficient in the lamp-like characteristic is adjusted by adjusting the increase / decrease rate K1 so as to be closest to _{the determined target charging voltage V T at a desired timing.} Good. According to the adjustment procedure described here, the target charging voltage can be brought close to the flat top level of the pattern voltage with sufficiently high accuracy.

FIG. 4 is a circuit diagram showing a specific configuration example of the first regulator A1 and the second regulator A2 in the first embodiment.

The first regulator A1 is composed of a first differential amplifier OP1 having a variable rate of increase / decrease K1 composed of an operational amplifier (operational amplifier). R4 is a resistance element connected to the inverting input terminal (−) of the first differential amplifier OP1, and R5 ′ is a variable resistance element connected between the inverting input terminal (−) and the output terminal. The increase / decrease rate K1 of the first regulator A1 is adjusted by adjusting the variable resistance element R5'.

The second regulator A2 is composed of a second differential amplifier OP2 which is composed of an operational amplifier (operational amplifier) and can change the increase / decrease rate K2. R6 is a resistance element connected to the inverting input terminal (−) of the second differential amplifier OP2, and R7 ′ is a variable resistance element connected between the inverting input terminal (−) and the output terminal. The increase / decrease rate K2 of the second adjuster A2 is adjusted by adjusting the variable resistance element R7'.

[Second Example]
FIG. 5 is a circuit diagram showing a configuration of a capacitor charging device according to a second embodiment of the present invention. In FIG. 5, the same reference numerals as those used in FIG. 4 of the first embodiment refer to the same components, and detailed description thereof will be omitted.

In FIG. 4, the first differential amplifier OP1 and the second differential amplifier OP2 are used as means for generating the difference voltage ΔVp-c (= Vp −Vc) between the pattern voltage Vp and the detected capacitor charging voltage Vc. Although it is provided, in the second embodiment, it is changed to a single differential amplifier OP3 which has both the function of the first differential amplifier OP1 and the function of the second differential amplifier OP2.

R8 is a resistance element connected to the inverting input terminal (−) of the dual-purpose differential amplifier OP3, and R9 is a resistance element connected between the inverting input terminal (−) and the output terminal. A variable resistance element R10 is connected between the output terminal of the dual-purpose differential amplifier OP3 and the input terminal of the first gate circuit G1 to form the first regulator A1. The increase / decrease rate K1 of the first regulator A1 is adjusted by adjusting the variable resistance element R10.

Further, a variable resistance element R11 is connected between the output terminal of the dual-purpose differential amplifier OP3 and the input terminal of the second gate circuit G2 to form the second regulator A2. The increase / decrease rate K2 of the second adjuster A2 is adjusted by adjusting the variable resistance element R11.

In the case of this embodiment, since the differential amplifier OP3 that is also used is adopted, the number of circuit components is reduced, which is advantageous in terms of cost and space. Other configurations are the same as in the case of the first embodiment, and the operation and action / effect are also the same.

In the above embodiment, the case of _{6,000 [V] per the target charging voltage V T} has been illustrated, but of course, the case is not limited to this, and an arbitrary voltage value can be set. Then, the optimum values may be selected for the increase / decrease rate K1 and the increase / decrease rate K2 according to the setting change.

In the above, regarding the procedure for adjusting the increase / decrease rate K1 and the increase / decrease rate K2, it has been described that the method of preferentially fixing the increase / decrease rate K2 to a predetermined value and then adjusting the increase / decrease rate K1 is preferable. On the contrary, a method may be adopted in which the increase / decrease rate K1 is preferentially fixed to a predetermined value and then the increase / decrease rate K2 is adjusted. When adjusting the rate of change K1 related to the boost coefficient in ramp form characteristic preferentially, the timing to reach the target charging voltage V _T changes, it is necessary to consider in this respect. Shifted arrival timing to the target charging voltage V _T is backward when the boost coefficient decreases, the arrival timing of the target charging voltage V _T when the boosting factor is large is shifted forward.

Further, in order to carry out fine adjustment with high accuracy, a method may be adopted in which the adjustment of the increase / decrease rate K1 and the adjustment of the increase / decrease rate K2 are alternately repeated. In this case, whichever comes first.

In the above example, the first regulator A1 and the second regulator A2 are configured in an analog system using a differential amplifier, but the present invention is not necessarily limited to that system, but is configured in a digital system. May be good. That is, the first regulator A1 and the second regulator A2 are used by a CPU (central processing unit) as a control means for executing a program or calculating / processing data, and a program for calculation / control by the CPU. ROM (read-only memory) as a non-volatile storage unit for storing data, RAM (random access memory) as a working area for temporarily storing data while assisting CPU calculation and control, data with the outside It may be configured by a microcomputer provided with an input / output interface for inputting / outputting control signals.

The present invention relates to an overlap charging type capacitor charging device, in which a lamp characteristic of a desired boost pattern is obtained in the process of the capacitor charging voltage rising to a target charging voltage, and a feedback control amount with respect to the capacitor charging voltage is obtained in the switching process. It is useful as a technique for suppressing / avoiding runaway and obtaining the desired high stability of the capacitor charging voltage.

10 1st charging circuit 20 2nd charging circuit A1 1st regulator A2 2nd regulator C1 Capacitor OP1 1st differential amplifier OP2 2nd differential amplifier OP3 Combined differential amplifier G1 1st Gate circuit G2 2nd gate circuit H1 1st judgment device H2 2nd judgment device J1 High power main charger J2 Low power auxiliary charger

Claims (6)

A first charging circuit with a high power main charger and a second charging circuit with a low power auxiliary charger connected in parallel to the capacitors to be charged, and
For controlling the output voltage of the main charger in the first charging circuit, input the difference voltage between the pattern voltage that rises from the base level and transitions to the target charging voltage level and the capacitor charging voltage detected for the capacitor. The first adjustment control amount of the result calculated by the predetermined increase / decrease rate is generated, and the first adjuster in which the increase / decrease rate can be changed, and the first adjuster.
A first gate circuit inserted between the output side of the first regulator and the control terminal of the main charger, and
The capacitor charging voltage is compared with the first threshold voltage, and when it is equal to or less than the first threshold voltage, a closing signal is output to the first gate circuit, and when it exceeds the first threshold voltage, the first threshold voltage is output. The first judgment device that outputs the opening signal to the gate circuit of 1 and
For controlling the output voltage of the auxiliary charger in the second charging circuit, a second adjustment control amount as a result of inputting the difference voltage and calculating with a predetermined increase / decrease rate is generated, and the increase / decrease rate is generated. With a second adjuster that can be changed,
A second gate circuit inserted between the output side of the second regulator and the control terminal of the auxiliary charger, and
The capacitor charging voltage is compared with a second threshold voltage set lower than the first threshold voltage, and when it is equal to or lower than the second threshold voltage, an opening signal is output to the second gate circuit. A capacitor charging device including a second determination device that outputs a closing signal to the second gate circuit when the second threshold voltage is exceeded. A claim including a first differential amplifier for controlling the output voltage of the main charger and a second differential amplifier for controlling the output voltage of the auxiliary charger as means for generating the differential voltage. Item 1. The capacitor charging device according to item 1. The capacitor according to claim 1, further comprising a single differential amplifier for controlling the output voltage of the main charger and controlling the output voltage of the auxiliary charger as the means for generating the differential voltage. Charging device. Any one of claims 1 to 3 is set in a waveform in which the pattern voltage rises like a lamp from the base level and converges from the top of the lamp to a target charging voltage level of a certain level. The capacitor charging device described in. In the first adjuster and the second adjuster, one of the variable increase / decrease rates is preferentially fixed to a predetermined value, and the other increase / decrease rate is adjusted. The capacitor charging device according to any one of claims 1 to 4, which is configured. Of the first regulator and the second regulator, the regulator whose increase / decrease rate is preferentially fixed to a predetermined value is the second adjuster, and the increase / decrease rate is adjusted. The condenser charging device according to claim 5, wherein the regulator is the first regulator.

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