CN102386771B - Controller, current control method and DC-DC converter - Google Patents
Controller, current control method and DC-DC converter Download PDFInfo
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- CN102386771B CN102386771B CN201110240114.XA CN201110240114A CN102386771B CN 102386771 B CN102386771 B CN 102386771B CN 201110240114 A CN201110240114 A CN 201110240114A CN 102386771 B CN102386771 B CN 102386771B
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Abstract
The invention discloses a controller, a current control method and a DC-DC converter. The controller includes a ramp signal generator and control circuitry coupled to the ramp signal generator. The ramp signal generator provides a control current through a resistive component to control energy stored in a first energy storage component. The ramp signal generator further generates a ramp signal based on the energy stored in the first energy storage component. The control circuitry adjusts a voltage at one end of the resistive component thereby controlling the control current to indicate a voltage across a second energy storage component. The control circuitry further controls a current through the second energy storage component within a predetermined range based on the ramp signal. The controller can control the output current amplitude of the DC-DC converter to be constant and increase the accuracy for DC-DC converter output control. Moreover, high power power consumption oscillator, large-sized capacitor and operational transconductance amplifier with narrow bandwidth in the prior art are eliminated in the invention.
Description
Technical field
Present invention relates in general to DC to DC converter and controller thereof and control method.
Background technology
Direct current direct current (Direct-Current to Direct-Current, referred to as DC/DC) transducer comprises that controller is for generation of pulse-width modulation (Pulse-Width Modulation, referred to as PWM) signal is with driving switch circuit, thus control the output voltage of this DC/DC transducer.As, controller increases output voltage by increasing the duty ratio of pwm signal, or reduces output voltage by reducing the duty ratio of pwm signal.
Figure 1A has described a kind of traditional controller 150 in DC/DC transducer.Controller 150 comprises oscillator 152 (being designated OSC), comparator 154 (being designated CMP), operation transconductance amplifier 156 (being designated OTA), and capacitor 158.Oscillator 152 provides the in-phase input end of concussion voltage 160 to comparator 154.Reference voltage 162 on capacitor 158 offers the inverting input of comparator 154.Comparator 154 will shake voltage 160 and reference voltage 162 compares, and according to comparative result output pwm signal 168.In the maximum and the scope between minimum value of reference voltage 162 earthquake voltages 160.If reference voltage 162 increases, the duty ratio of pwm signal 168 will reduce, and the output voltage of DC/DC transducer also will reduce so.If reference voltage 162 reduces, the duty ratio of pwm signal 168 will increase, and the output voltage of DC/DC transducer also will increase so.
Operation transconductance amplifier 156 receives the feedback voltage 164 of predeterminated voltage 166 and indication DC/DC converter output voltage, and the control electric current I COMP of the difference that is proportional to predeterminated voltage 166 and feedback voltage 164 is provided.The output of operation transconductance amplifier 156 is connected with capacitor 158, makes to control the reference voltage 162 of electric current I COMP on can control capacitor 158.As, if feedback voltage 164 is greater than predeterminated voltage 166, operation transconductance amplifier 156 outputs are controlled electric current I COMP to capacitor 158 chargings, thereby increase reference voltage 162.Output voltage thereby reduce.If feedback voltage 164 is less than predeterminated voltage 166, operation transconductance amplifier 156 absorbs and controls electric current I COMP from capacitor 158, thereby reduces reference voltage 162.Output voltage thereby increase.As a result, the output voltage of DC/DC transducer is adjusted to the determined desired value of predeterminated voltage 166.
Yet in this traditional controller 150, the power consumption of oscillator 152 is relatively high.In addition,, because the volume of capacitor 158 is large, capacitor 158 can not be integrated in one chip with comparator 154 together with operation transconductance amplifier 156.Also has the narrow response time delay that makes operation transconductance amplifier 156 of bandwidth of operation transconductance amplifier 156.Therefore, controller 150 can not be controlled output voltage exactly.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of controller, current control method and DC/DC transducer, its the output current wave amplitude that can control DC/DC transducer is constant, thereby increase the accuracy of controlling this DC/DC transducer output, and omitted high power consumption oscillator, the large volume electric capacity in conventional art, and the narrower operation transconductance amplifier of bandwidth.
For solving the problems of the technologies described above, the invention provides a kind of controller, it comprises: ramp signal generator, for control electric current that the resistance element of flowing through is provided with control store the energy in the first energy storage elements, and based on the described power generation ramp signal being stored in the first energy storage elements; And the control circuit that is connected to described ramp signal generator, for regulating described resistance element one terminal voltage to control described control electric current indication across the voltage of the second energy storage elements, and the electric current of controlling described the second energy storage elements of flowing through based on described ramp signal is in preset range, wherein, described control circuit comprises: the first comparator, for by described resistance element one terminal voltage and the first reference voltage comparison; And second comparator, be used for described resistance element one terminal voltage and the second reference voltage comparison, wherein, described the first reference voltage equals described the second energy storage elements one terminal voltage and adds the first predeterminated voltage, and described the second reference voltage equals described the second energy storage elements one terminal voltage and deducts the second predeterminated voltage.
The present invention also provides a kind of controller, comprise: ramp signal generator, for control electric current that the resistance element of flowing through is provided with control store the energy in the first energy storage elements, and based on the described power generation ramp signal being stored in the first energy storage elements, and the control circuit that is connected to described ramp signal generator, for regulating described resistance element one terminal voltage to control described control electric current indication across the voltage of the second energy storage elements, and the electric current of controlling described the second energy storage elements of flowing through based on described ramp signal is in preset range, wherein, described control circuit comprises the first comparator, be used for described resistance element one terminal voltage and reference voltage comparison, according to the switch of described relatively control connection between described resistance element one end and described second energy storage elements one end, wherein said reference voltage equals described the second energy storage elements one terminal voltage and deducts predeterminated voltage.The present invention also provides a kind of current control method, and the flow through electric current of the first energy storage elements of its control, comprising: the control electric current that the resistance element of flowing through is provided is the energy in the second energy storage elements with control store; Regulate described resistance element one terminal voltage; Based on controlling the voltage of electric current indication across described the first energy storage elements described in the voltage control of described resistance element one end; Based on the described power generation ramp signal that is stored in the second energy storage elements; And the electric current of first energy storage elements of flowing through described in controlling based on described ramp signal is in preset range, wherein, the step of described resistance element one terminal voltage of described adjusting comprises that controlling described resistance element one terminal voltage is tending towards described the first energy storage elements one terminal voltage, wherein, described resistance element one terminal voltage and the first reference voltage are compared; And described resistance element one terminal voltage and the second reference voltage are compared, wherein, described the first reference voltage equals described the first energy storage elements one terminal voltage and adds the first predeterminated voltage, and described the second reference voltage equals described the first energy storage elements one terminal voltage and deducts the second predeterminated voltage.
The present invention also provides a kind of current control method, for controlling the electric current of first energy storage elements of flowing through, it is characterized in that, described current control method comprises: the control electric current that the resistance element of flowing through is provided is the energy in the second energy storage elements with control store, regulate described resistance element one terminal voltage, based on controlling the voltage of electric current indication across described the first energy storage elements described in the voltage control of described resistance element one end, based on the described power generation ramp signal that is stored in the second energy storage elements, and the electric current of first energy storage elements of flowing through described in controlling based on described ramp signal is in preset range, wherein, the step of described resistance element one terminal voltage of described adjusting comprises that controlling described resistance element one terminal voltage is tending towards described the first energy storage elements one terminal voltage, wherein, by described resistance element one terminal voltage and reference voltage comparison, according to the switch of described relatively control connection between described resistance element one end and described first energy storage elements one end, wherein said reference voltage equals described the first energy storage elements one terminal voltage and deducts predeterminated voltage.
The present invention also provides DC/DC transducer, and it comprises: for the first energy storage elements of described DC to DC converter output voltage is provided, be connected to the pair of switches of described the first energy storage elements, and the controller that is connected to described the first energy storage elements and described pair of switches, for control electric current that the resistance element of flowing through is provided with control store the energy in the second energy storage elements, based on the described power generation ramp signal being stored in the second energy storage elements, by regulating described resistance element one terminal voltage to control described control electric current indication across the voltage of described the first energy storage elements, and control described pair of switches to control described output voltage and the electric current of described the first energy storage elements of flowing through based on described ramp signal, wherein, described controller comprises: the first comparator, be used for described resistance element one terminal voltage and the first reference voltage comparison, and second comparator, be used for described resistance element one terminal voltage and the second reference voltage comparison, wherein, described the first reference voltage equals described the first energy storage elements one terminal voltage and adds the first predeterminated voltage, and described the second reference voltage equals described the first energy storage elements one terminal voltage and deducts the second predeterminated voltage.The present invention also provides a kind of DC to DC converter, comprising: for the first energy storage elements of described DC to DC converter output voltage is provided, be connected to the pair of switches of described the first energy storage elements, and the controller that is connected to described the first energy storage elements and described pair of switches, for control electric current that the resistance element of flowing through is provided with control store the energy in the second energy storage elements, based on the described power generation ramp signal being stored in the second energy storage elements, by regulating described resistance element one terminal voltage to control described control electric current indication across the voltage of described the first energy storage elements, and control described pair of switches to control described output voltage and the electric current of described the first energy storage elements of flowing through based on described ramp signal, wherein, described controller comprises the first comparator, be used for described resistance element one terminal voltage and reference voltage comparison, according to the switch of described relatively control connection between described resistance element one end and described first energy storage elements one end, wherein said reference voltage equals described the first energy storage elements one terminal voltage and deducts predeterminated voltage.
Compared with prior art, controller of the present invention, current control method and the brand-new structure of DC/DC transducer utilization, for example: resistance element, inductive element (a kind of energy storage elements), capacitive element (a kind of energy storage elements) etc., the output voltage wave amplitude of controlling DC/DC transducer is constant, the output stability of DC/DC transducer is increased, power consumption reduces, volume reduces, and response speed increases.
Below in conjunction with the drawings and specific embodiments, technical scheme of the present invention is described in detail, so that characteristic of the present invention and advantage are more obvious.
Accompanying drawing explanation
Figure 1A is a kind of traditional controller in DC/DC transducer;
Fig. 1 is the example block diagram of DC/DC transducer according to an embodiment of the invention;
Fig. 2 is the example table of on off state according to an embodiment of the invention;
Fig. 3 is the exemplary circuit diagram of DC/DC transducer according to an embodiment of the invention;
Fig. 4 is the exemplary sequential chart of the signal that controller according to an embodiment of the invention and in Fig. 3 is relevant;
Fig. 5 is the exemplary circuit diagram of DC/DC transducer according to an embodiment of the invention;
Fig. 6 is the exemplary sequential chart of relevant to controller in Fig. 5 according to one embodiment of present invention signal;
Fig. 7 is the exemplary circuit diagram of DC/DC transducer according to an embodiment of the invention;
Fig. 8 is the exemplary sequential chart of relevant to controller in Fig. 7 according to one embodiment of present invention signal;
Fig. 9 is the exemplary method flowchart of Current Control according to an embodiment of the invention;
Figure 10 A is the example block diagram of DC/DC transducer according to an embodiment of the invention;
Figure 10 B is the example block diagram of DC/DC transducer according to an embodiment of the invention;
Figure 11 is the example table of having described in response to high-side switch state and the low side switch state of two control signals according to an embodiment of the invention;
Figure 12 is the exemplary circuit diagram of DC/DC transducer according to an embodiment of the invention;
Figure 13 is the exemplary sequential chart of the signal relevant to the DC/DC transducer of Figure 12 according to an embodiment of the invention;
Figure 14 is the exemplary circuit diagram of DC/DC transducer according to an embodiment of the invention;
Figure 15 is the exemplary sequential chart of the signal relevant to the DC/DC transducer of Figure 14 according to an embodiment of the invention; And
Figure 16 is the exemplary method flowchart of Current Control according to an embodiment of the invention.
Embodiment
To embodiments of the invention be provided to detailed explanation below.Although the present invention sets forth in connection with embodiment, should understand this and not mean to limit the invention to these embodiment.On the contrary, the invention is intended to contain defined various options in the spirit and scope of the invention being defined by claims item, can modification item and be equal to item.
In addition,, in following detailed description of the present invention, in order to provide one to understand completely for of the present invention, illustrated a large amount of details.Yet, it will be understood by those skilled in the art that and there is no these details, the present invention can implement equally.In some other examples, the scheme of knowing for everybody, flow process, element and circuit are not described in detail, so that highlight the present invention's purport.
The invention provides a kind of DC/DC transducer (as: step-down controller, boost converter etc.), and the controller of controlling described DC/DC transducer.Advantageously, the output current wave amplitude of DC/DC transducer is constant, makes the output current of DC/DC transducer and output voltage relatively stable.Described controller is controlled the output voltage of DC/DC transducer more accurately.In addition, the present invention has omitted the oscillator 152 of higher power dissipation, the capacitor 158 of larger volume, and the narrower operation transconductance amplifier of bandwidth.
Fig. 1 is the example block diagram of DC/DC transducer 100 according to an embodiment of the invention.DC/DC transducer 100 comprises controller 102, drive circuit 104, switching circuit 106, and output circuit 108 (or being called energy storage circuit, filter circuit etc.).Controller 102 produces one or more control signals to drive circuit 104.As, controller 102 produces pwm signal, with control switch circuit 106.Switching circuit 106 comprises pair of switches.Specifically, high-side switch 110 and low side switch 112 receive respectively the control signal from drive circuit 104, and provide signal to output circuit 108 to produce output voltage VO UT.Drive circuit 104 is controlled high-side switch 110 and low side switch 112, makes high-side switch 110 and low side switch 112 separately in conducting or cut-off state.Specifically, controller 102 provides one or more pwm signals, controls the state of high-side switch 110 and low side switch 112 by changing the mode of described pwm signal duty ratio.
In the present embodiment, if pwm signal is high level, high-side switch 110 conductings so, low side switch 112 cut-offs.This state is called " switch ON " state or " TON_BUCK " state.Under this state, the inductor 114 in output circuit 108 is through high-side switch 110 and be designated V
iNinput voltage connect.Flow through electric current thereby the increase of inductor 114, and by charge storage to the capacitor 116 in output circuit 108.In the embodiment in figure 1, DC/DC transducer 100 is a kind of step-down controllers.Therefore, input voltage V
iNbe greater than output voltage V
oUT, across the voltage of inductor 114 for just.The inductive current I of inductor 114 flows through
l1increase, and magnetic field energy is stored in inductor 114.If pwm signal is low level, high-side switch 110 cut-offs so, low side switch 112 conductings.This state is called " switch OFF " state or " TOFF_BUCK " state.Under this state, across the voltage of inductor 114 for negative.Therefore, inductor 114 discharges and is stored in magnetic field energy wherein, and output voltage V is provided
oUTgive capacitor 116.So the duty of the pwm signal that controller 102 provides based on it recently provides output voltage V
oUT.Controller 102 also provides enable signal (as: low side switch enable signal, or LDR_EN signal) to drive circuit 104.In the present embodiment, LDR_EN signal is provided by the port that is designated " EN ", and controls the state of high-side switch 110 and low side switch 112.
In the present embodiment, controller 102 receives two voltage feedback signals to produce pwm signal and LDR_EN signal.Specifically, the port that is designated " VFB " receives output voltage V through path 120
oUT.In addition the port that, is designated " LX " on controller 102 is through another paths 118 receiving inductance device 114 1 terminal voltages.The feedback voltage being provided by path 118 is for determining the state of high-side switch 110 and low side switch 112.Controller 102 comprises that some elements are for arranging relative parameter.Illustrate, resistor 128, resistor 124 and capacitor 126 are connected with controller 102, for reference voltage, reference current are set, with reference to parameters such as slew rates.
Fig. 2 is the example table 200 of on off state according to an embodiment of the invention.Form 200 has been described corresponding to the high-side switch 110 of LDR_EN signal and pwm signal level value and the state of low side switch 112.In addition, the conducting situation of high-side switch 110 and low side switch 112 is determined a kind of state.Illustrate, if for example, high-side switch 110 conductings and low side switch 112 cut-offs (: LDR_EN=1 and PWM=1), this state is defined as " TON_BUCK " state or " switch ON " state.Under TON_BUCK state, inductor 114 and input voltage V
iNconnect.If for example, high-side switch 110 cut-off and low side switch 112 conductings (: LDR_EN=1 and PWM=0), this state is defined as " TOFF_BUCK " state or " switch OFF " state.Under TOFF_BUCK state, inductor 114 is connected with earth potential.For example, if high-side switch 110 and low side switch 112 all end (: LDR_EN=0 and PWM=0), this state is defined as " SKIP " state.Under SKIP state, because high-side switch 110 and low side switch 112 all end, inductor 114 was not in vacant state (as: both connect voltage source and there is no ground connection yet).Therefore, inductor 114 under TON_BUCK state with input voltage V
iNconnect, under TOFF_BUCK state, be connected with earth potential, unsettled under SKIP state.
Under TON_BUCK state, across the voltage of inductor 114, approximate V
iN-V
oUT.For step-down controller, input voltage V
iNbe greater than output voltage V
oUT, across the clean voltage of inductor 114 for just.Therefore, the flow through inductive current I of inductor 114
l1according to following equation, increase:
dI
L1/dt＝(V
IN-V
OUT)/L＝ΔI
L1/T
ON. (1)
V in equation (1)
iNthe input voltage that represents DC/DC transducer 100, V
oUTthe output voltage that represents DC/DC transducer 100, T
oNrepresent high-side switch 110 and the time of low side switch 112 in TON_BUCK state, L represents the inductance value of inductor 114, Δ I
l1represent inductive current I
l1variable quantity during TON_BUCK state.
Under TOFF_BUCK state, across the voltage of inductor 114, equal output voltage V
oUT.Yet, across the voltage of inductor 114, be reverse polarity, inductive current I
l1according to following equation, reduce:
dI
L1/dt＝-(V
OUT)/L＝ΔI
L1/T
OFF. (2)
T in equation (2)
oFFrepresent high-side switch 110 and the time of low side switch 112 in TOFF_BUCK state, Δ I
l1represent inductive current I
l1variable quantity during TOFF_BUCK state.
Fig. 3 is the example block diagram of DC/DC transducer 100A according to an embodiment of the invention.DC/DC transducer 100A is that in Fig. 1, a kind of of DC/DC transducer 100 illustrates.Fig. 1 and Fig. 3 get the bid sensible with element there is similar function.DC/DC transducer 100A comprises controller 102A.Controller 102A can be used in various DC/DC transducer 100A.Illustrate, DC/DC transducer 100A is a kind of synchronous buck converter that comprises controller 102A, drive circuit 104, the switching circuit 106 that comprises high-side switch 110 and low side switch 112 and output circuit 108.Output circuit 108 comprises inductor 114 and capacitor 116.High-side switch 110 is connected to input voltage V
iNand between switching node 122.Low side switch 112 is connected between switching node 122 and ground.Switching node 122 is also connected with output circuit 108.
Controller 102A comprises the pulse-width modulation circuit 352 that produces pwm signal and LDR_EN signal.In response to pwm signal and LDR_EN signal, drive circuit 104 is controlled the state of high-side switch 110 and low side switch 112.
Controller 102A receives the input signal of indication switching node 122 voltages.Controller 102A also comprises that target input SLEW is for arranging expection output voltage V
sET.Illustrating, in the embodiment in figure 1, is that resistor 124 based in resitstance voltage divider and the resistance of resistor 128 and the value of reference voltage REF realize to the charging of capacitor 126.Those skilled in the art know various methods capacitor 126 are charged to produce target voltage signal.In addition, the VFB termination of controller 102A is received indication DC/DC transducer 100A output voltage V
oUTfeedback signal.
The controller 102A describing in Fig. 3 comprises the resistor 320 that is connected to DC/DC transducer 100A switching node 122.For example flow through the current response of resistor 320, in the state of high-side switch 110 and low side switch 112: TON_BUCK state, TOFF_BUCK state, or SKIP state.Controller 102A also comprises that the electric current in response to the resistor 320 of flowing through provides the oblique wave generating circuit 350 of ramp signal 312.Pulse-width modulation circuit 352 at least produces pwm signal in response to ramp signal 312.
Under TON_BUCK state, as: when 112 cut-off of high-side switch 110 conductings and low side switch, due to high-side switch 110 conductings, switching node 122 and input voltage V
iNconnect, so switching node 122 voltages equal input voltage V
iN.So flow through, the electric current of resistor 320 equals the input voltage V of DC/DC transducer 100A
iNdeduct the output voltage V of DC/DC transducer 100A
oUTagain divided by the resistance of resistor 320.In response to the electric current of the resistor 320 of flowing through, oblique wave generating circuit 350 by a part for the ramp signal of describing in Fig. 4 312 (for example: rising part) produces.
Under TOFF_BUCK state, as: when high-side switch 110 cut-off and low side switch 112 conducting, because switching node 122 is via low side switch 112 ground connection, switching node 122 voltages equal zero.So flow through, the electric current of resistor 320 equals zero and deducts the output voltage V of DC/DC transducer 100A
oUTagain divided by the resistance of resistor 320.In response to the electric current of the resistor 320 of flowing through, oblique wave generating circuit 350 by another part of the ramp signal of describing in Fig. 4 312 (for example: sloping portion) produces.
Under SKIP state, when high-side switch 110 and low side switch 112 all end, switching node 122 voltages equal the output voltage V of DC/DC transducer 100A
oUT.Because switching node 122 voltages deduct output voltage V
oUTresistance divided by resistor 320 equals zero again, and the electric current of the resistor 320 of flowing through equals zero under SKIP state.In response to the electric current of this resistor 320 of flowing through, oblique wave generating circuit 350 for example produces, by another part of the ramp signal of describing in Fig. 4 312 (: be tending towards constant portion).
Oblique wave generating circuit 350 comprises buffer 351 (being designated BUF) and current-controlled current source 324.The reverse input of buffer 351 is connected to provide negative feedback with the output of buffer 351.The in-phase input end of buffer 351 receives indication DC/DC transducer 100A output voltage (as: expection output voltage V
sETor output voltage V
oUT) voltage.The output voltage of buffer 351 thereby follow tightly expection output voltage V
sETor output voltage V
oUTand change.Current-controlled current source 324 is in response to the electric current I _ in of the resistor 320 of flowing through, and electric current I _ in depends on the state of high-side switch 110 and low side switch 112 and changes.Current-controlled current source 324 provides the electric current I _ out with electric current I _ in mirror image.In one embodiment, current-controlled current source 324 includes but not limited to mirror current source.Electric current I _ out discharges and recharges slope capacitor 308, to provide ramp signal 312 to the comparator 301 (being designated CMP1) in pulse-width modulation circuit 352 and comparator 302 (being designated CMP2).
Comparator 301 is by ramp signal 312 and nominal voltage V2 comparison.In one embodiment, nominal voltage V2 value is 20 millivolts.Comparator 301 provides signal RAW_LDR_EN to NAND gate 311 (being designated G1).NAND gate 311 also receives SKIP signal and provides LDR_EN signal to drive circuit 104.Comparator 302 is ramp signal 312 and reference voltage REF comparison, and the reset terminal " R " that outputs signal to trigger 342 is provided.The in-phase output end of trigger 342 " Q " provides pwm signal to drive circuit 104.
The duty ratio of pwm signal and input voltage V
iNand output voltage V
oUT(or expection output voltage V
sET) difference be inversely proportional to.In other words, along with this difference increases, thereby the duty ratio of pwm signal reduces to shorten the TON_BUCK time of high-side switch 110 and low side switch 112.On the contrary, along with this difference reduces, thereby the duty ratio of pwm signal increases the TOFF_BUCK time that shortens high-side switch 110 and low side switch 112.In the present embodiment, the TON_BUCK time of high-side switch 110 and low side switch 112 (for example: time T
oN) and input voltage V
iNand output voltage V
oUTpoor (as: V
iN-V
oUT) or with input voltage V
iNwith expection output voltage V
sETpoor (as: V
iN-V
sET) be inversely proportional to.Therefore, the current change quantity Δ I in each TON_BUCK period of state
l1invariable.In addition, the TOFF_BUCK time of high-side switch 110 and low side switch 112 (for example: time T
oFF) and output voltage V
oUTor expection output voltage V
sETbe inversely proportional to.Therefore, the current change quantity Δ I in each TOFF_BUCK period of state
l1invariable.In one embodiment, the current change quantity Δ I in each TON_BUCK period of state
l1with the current change quantity Δ I in each TOFF_BUCK period of state
l1equate.In other words, controller 102A is a kind of constant ripple current (Constant-ripple-current, referred to as CRC) controller, controls inductive current I
l1there is constant wave amplitude.
Fig. 4 is exemplary sequential chart 400 according to an embodiment of the invention.Below with reference to Fig. 1, Fig. 3 and Fig. 4, set forth the certain operations of the controller 102A in Fig. 3, comprise the production process of ramp signal 312.When controller 102A starts, the SLEW voltage on the target input SLEW shown in Fig. 1 and Fig. 3 starts to increase.This moment, indication output voltage V
oUTfeedback voltage V FB be zero.Comparator 303 in Fig. 3 senses that SLEW voltage is greater than feedback voltage V FB, and provide high level to door 322 (being designated G2).This moment, the output of comparator 301 (as: signal RAW_LDR_EN) is also high level.So, be high level with the input of door 322, so export high level by trigger 342 set with door 322.This moment, pwm signal is high level.High-side switch 110 conductings, so output voltage V
oUTstart to increase with feedback voltage V FB.In the present embodiment, when SLEW voltage is increased to preset value (as: expection output voltage V
sET) time, SLEW voltage remains unchanged.
During t1 arrives the t2 moment, the pwm signal shown in 403 in Fig. 4 is high level; LDR_EN signal shown in Fig. 4 404 is high level.So high-side switch 110 and low side switch 112 be in TON_BUCK state, i.e. high-side switch 110 conductings, low side switch 112 cut-offs.Due to the input voltage V of switching node 122 with DC/DC transducer 100A
iNconnect, thus in Fig. 4 405 shown in t1 to during the t2 moment, switching node 122 voltage LX equal input voltage V
iN.
During t1 arrives the t2 moment, the electric current I _ in of the resistor 320 of flowing through is provided by following formula:
I_in＝(V
IN-V
OUT)/R1。(3)
Wherein, V
iNthe input voltage that represents DC/DC transducer 100A, V
oUTthe output voltage that represents DC/DC transducer 100A, R1 represents the resistance of resistor 320.If K=1/R1, rewrites so equation (3) and obtains:
I_in＝K＊(V
IN-V
OUT)。(4)
Due to electric current I _ out image current I_in, so electric current I _ out equals electric current I _ in and can be by equation (3) and equation (4), and provide by 406 examples in Fig. 4.During t1 arrives the t2 moment, the ramp signal 312 shown in 407 in Fig. 4 increases to be proportional to the speed of electric current I _ out.Ramp signal 312 increases until equal to be input to the reference voltage REF of comparator 302 inverting inputs.When ramp signal 312 is when t2 is increased to reference voltage REF constantly, the output of comparator 302 resets trigger 342.
When trigger 342 is when t2 resets constantly, the Q of trigger 342 (homophase) is output as low level, so the pwm signal shown in 403 in Fig. 4 is low level.Signal RAW_LDR_EN (signal as shown in 402 in Fig. 4) from comparator 301 is low level, and the output (as: the LDR_EN signal shown in 404 in Fig. 4) that makes NAND gate 311 is high level.Therefore, high-side switch 110 and low side switch 112 are in TOFF_BUCK state during t2 arrives the t3 moment, and high-side switch 110 ends, low side switch 112 conductings.When high-side switch 110 and low side switch 112 are under TOFF_BUCK state, because switching node 122 is via low side switch 112 ground connection, the switching node 122 voltage LX shown in 405 in Fig. 4 equal zero.
During t2 arrives the t3 moment, the electric current I _ in shown in 406 in Fig. 4 is provided by following formula:
I_in＝(0-V
OUT)/R1。(5)
If K=1/R1, rewrites so equation (5) and obtains:
I_in＝-K＊V
OUT。(6)
Due to electric current I _ out image current I_in, so electric current I _ out equals electric current I _ in and can be by equation (5) and equation (6), and provide by 406 examples in Fig. 4.During t2 arrives the t3 moment, the ramp signal 312 shown in 407 in Fig. 4 reduces to be proportional to the speed of electric current I _ out.Ramp signal 312 reduces until equal to be input to the nominal voltage V2 of comparator 301 in-phase input ends.When ramp signal 312 is when t3 is decreased to nominal voltage V2 constantly, the output of comparator 301 (as: signal RAW_LDR_EN) becomes high level.When ramp signal 312 is when t3 is decreased to nominal voltage V2 constantly, the inductive current I shown in 408 in Fig. 4
l1in zero crossing (zero-crossing) state.Therefore, the not direct inductance measuring electric current I of controller 102A
l1, and be to provide zero crossing estimation device estimation inductive current I
l1.
For example, if SKIP signal be also constantly high level (: thereby activation SKIP state) at t3, the output of NAND gate 311 so (as: the LDR_EN signal shown in 404 in Fig. 4) is low level.Therefore,, during t3 arrives the t4 moment, controller 102A is in SKIP state.In response to the low level LDR_EN signal shown in 404 in the low level pwm signal shown in 403 in Fig. 4 and Fig. 4, high-side switch 110 and low side switch 112 all end and in SKIP state.In one embodiment, SKIP state occurs in following situation: when ramp signal 312 is decreased to nominal voltage V2, feedback voltage V FB is greater than SLEW voltage.Yet, if feedback voltage V FB is less than or equal to SLEW voltage when ramp signal 312 is decreased to nominal voltage V2, with door 322 by trigger 342 set with output high level pwm signal.In other words, if feedback voltage V FB is less than or equal to SLEW voltage when ramp signal 312 is decreased to nominal voltage V2, SKIP state will there will not be.
Therefore,, under SKIP state (when high-side switch 110 and low side switch 112 all end), the switching node 122 voltage LX shown in 405 in Fig. 4 equal the output voltage V of DC/DC transducer 100A
oUT.In addition, as shown in 406 in Fig. 4, under SKIP state, because switching node 122 voltages deduct output voltage V
oUTresistance divided by resistor 320 equals zero again, and electric current I _ in and the electric current I _ out of the resistor 320 of flowing through equal zero.
After SKIP state starts, controller 102A keeps high-side switch 110 and low side switch 112 in SKIP state, until the output voltage V of the DC/DC transducer 100A of feedback voltage V FB indication
oUTdrop to predeterminated voltage value, as: SLEW voltage.
T1 to t2 constantly during, high-side switch 110 conductings, low side switch 112 cut-offs, feedback voltage V FB increases, slope be on the occasion of.During t2 arrives the t3 moment, high-side switch 110 cut-offs, low side switch 112 conductings, feedback voltage V FB reduces, until constantly equal SLEW voltage at t4.At t3, arrive t4 between the moment, high-side switch 110 and low side switch 112 all end.The speed that the speed ratio that feedback voltage V FB now reduces reduces constantly to t3 at t2 is fast.At t4 constantly, comparator 303 (being designated CMP3) is output as high level.High level from comparator 303 and comparator 301 makes and door 322 output high level, thereby by trigger 342 set, so the pwm signal shown in 403 in Fig. 4 transfers high level to.During t4 arrives the t6 moment, will repeat said process.Feedback voltage V FB shown in Fig. 4 401 t3 to t4 constantly during reduction rate depend on load current.For example, the reduction rate of feedback voltage V FB under little load current condition is lower than the reduction rate compared with in large load current situation.Therefore, and compared with comparing in large load current situation, the controller 102A under little load current condition keeps the time of SKIP state longer.
Return in Fig. 3, t2 to t3 constantly during or t5 to t6 constantly during, can actuating switch 372 to affect the slope of ramp signal 312, thereby the shortening TOFF_BUCK time.With the output control switch 372 of door 323 (being designated G3), and when the input with door 323 is high level actuating switch 372.This situation is less than SLEW voltage at feedback voltage V FB and makes comparator 303 be output as high level, and the QB of trigger 342 (anti-phase) output occurs while being high level.In other words, if before ramp signal 312 is decreased to nominal voltage V2, feedback voltage V FB is decreased to SLEW voltage, and switch 372 is switched on.In the situation of ending with switch 372, compare, the TOFF_BUCK state time shorten in switch 372 conducting situations.This is because compare with in the situation of switch 372 cut-off, and at the situation downslope signal 312 of switch 372 conductings, under TOFF_BUCK state, the negative value slope of (as: t2 to the t3 moment during) can reduce further.More particularly, during TOFF_BUCK state, if switch 372 conductings will have extracurrent to flow to ground through resistor 373, the electric current I _ in flowing out from buffer 351 outputs so increases.Therefore, discharging current I_out increases, and ramp signal 312 is decreased to nominal voltage V2 institute's time spent from reference voltage REF and shortens.In other words, the time shorten of TOFF_BUCK state.Can be by selecting resistor 373 to determine the accelerated ratio of TOFF_BUCK state.If this accelerated TOFF_BUCK state is undesirable, controller 102A can not comprise switch 372, resistor 373, and with door 323.
According to the embodiment of Fig. 3, during TON_BUCK state, obtain following equation:
dV
312/dt＝I_out/C1＝ΔV
312/T
ON。(7a)
V wherein
312the voltage level that represents ramp signal 312, C1 represents the capacitance of slope capacitor 308, Δ V
312represent voltage level V
312variable quantity during TON_BUCK state.Because electric current I _ in equals electric current I _ out, rewrite equation (7a) and obtain:
I_in/C1＝ΔV
312/T
ON。(7b)
Based on equation (1), (4) and (7b), obtain following equation:
ΔI
L1＝(ΔV
312＊C1)/(K＊L)。(8)
During each TON_BUCK state, the voltage variety Δ V in equation (8)
312can be steady state value (as: equal reference voltage REF and deduct nominal voltage V2).Therefore, Δ I
l1also can be steady state value.
In like manner, during TOFF_BUCK state, obtain following equation:
dV
312/dt＝I_out/C1＝ΔV
312/T
OFF。(9a)
Δ V in equation (9a)
312represent voltage level V
312variable quantity during TOFF_BUCK state.Rewriteeing equation (9a) obtains:
I_in/C1＝ΔV
312/T
OFF. (9b)
Based on equation (2), (6) and (9b), obtain following equation 3
ΔI
L1＝(ΔV
312＊C1)/(K＊L). (10)
During each TOFF_BUCK state, the voltage variety Δ V in equation (10)
312can be steady state value (as: equal nominal voltage V2 and deduct reference voltage REF).Therefore, current change quantity Δ I
l1also can be steady state value.Due to the voltage variety Δ V during each TON_BUCK state
312with the voltage variety Δ V during each TOFF_BUCK state
312its value equates, so the current change quantity Δ I during each TON_BUCK state
l1with the current change quantity Δ I during each TOFF_BUCK state
l1its value equates.In other words, controller 102A controls inductive current I
l1a kind of CRC controller with constant wave amplitude.
In the present embodiment, by utilize comparator 303, with door 322, with door 323, trigger 342, switch 372, and resistor 373, controller 102A regulation output voltage V
oUTaverage voltage V
aVEto the expection output voltage V on target input SLEW
sET.Specifically, during TOFF_BUCK state, when ramp signal 312 is decreased to nominal voltage V2, if feedback voltage V FB is greater than SLEW voltage, average voltage V so
aVEbe greater than expection output voltage V
sET.In the case, comparator 303 output low levels are low level through keeping pwm signal with door 322 and trigger 342, until feedback voltage V FB is decreased to SLEW voltage.Therefore, the time of TOFF_BUCK state increases, thereby reduces the duty ratio of pwm signal.Average voltage V
aVEthereby reduce.If before ramp signal 312 is decreased to nominal voltage V2, feedback voltage V FB is decreased to SLEW voltage, so average voltage V
aVEbe less than expection output voltage V
sET.In the case, comparator 303 output high level are given with door 323 with actuating switch 372.The time shorten of TOFF_BUCK state, thereby the duty ratio of increase pwm signal.Average voltage V
aVEthereby increase.As a result, average voltage V
aVEbe adjusted to expection output voltage V
sET.
Fig. 5 is the example block diagram of DC/DC transducer 100B according to an embodiment of the invention.DC/DC transducer 100B is that in Fig. 1, a kind of of DC/DC transducer 100 illustrates.Fig. 1, Fig. 3 and Fig. 5 get the bid sensible with element there is similar function.DC/DC transducer 100B comprises controller 102B.Controller 102B comprises the resistor 520 that is connected to DC/DC transducer 100B switching node 122.Controller 102B comprises the oblique wave generating circuit 550 that ramp signal 512 is provided in response to the electric current that flows through resistor 520.Controller 102B also comprises the pulse-width modulation circuit 552 that at least produces pwm signal in response to ramp signal 512.
Oblique wave generating circuit 550 comprises the slope capacitor 508 of connecting with resistor 520 through path 509.Operational amplifier 551 (being designated OA1) has an inverting input that is connected to node 506, and for receiving indication DC/DC transducer 100B output voltage (as: expection output voltage V
sETor output voltage V
oUT) the in-phase input end of feedback voltage.Operational amplifier 551 is as integrator.If described in-phase input end receives output voltage V
oUT, resistor 520 one end (node 506) voltage equals output voltage V
oUT.The electric current that flows through resistor 520 also flows through slope capacitor 508, to slope capacitor 508 chargings or electric discharge, thereby controls ramp signal 512.
Ramp signal 512 is provided for the in-phase input end of comparator 501 (being designated CMP1) and the inverting input of comparator 502 (being designated CMP2).Nominal voltage V2 is provided for the inverting input of comparator 501.Reference voltage REF is provided for the in-phase input end of comparator 502.In one embodiment, reference voltage REF equals 0.01 volt, and nominal voltage V2 equals 2.5 volts.
Fig. 6 is exemplary sequential chart 600 according to an embodiment of the invention.Below with reference to Fig. 5, set forth the certain operations of the controller 102B in Fig. 6, comprise the production process of ramp signal 512.During t1 arrives the t2 moment, the pwm signal shown in 601 in Fig. 6 is high level, and the LDR_EN signal shown in 602 is also high level.Therefore, high-side switch 110 conductings, low side switch 112 cut-offs.T1 to t2 constantly during, due to switching node 122 and the input voltage V of DC/DC transducer 100B
iNconnect, the switching node 122 voltage LX shown in 603 in Fig. 6 equal input voltage V
iN.T1 to t2 constantly during, the electric current I _ in (or I (C1)) that flows through resistor 520 and flow through slope capacitor 508 shown in 604 in Fig. 6 is provided by equation (3) and (4).In response to the electric current that flows through slope capacitor 508, the ramp signal 512 shown in 605 in Fig. 6 reduces constantly to t2 at t1.During t1 arrives the t2 moment, because the electric current I _ in shown in 604 in Fig. 6 flows through slope capacitor 508 via operational amplifier 551, the slope of ramp signal 512 is negative value.Ramp signal 512 thereby anti-phase with the ramp signal 312 in Fig. 4.In addition, provide ramp signal 512 slope capacitor 508 polarity arrangement with provide the polarity arrangement of slope capacitor 308 of the ramp signal 312 shown in Fig. 4 contrary.
Ramp signal 512 reduces until equal to be input to the reference voltage REF of the in-phase input end of comparator 502.When ramp signal 512 is when t2 is decreased to reference voltage REF constantly, the output of comparator 502 resets trigger 542.When trigger 542 is at t2 constantly during position, the Q of trigger 542 (homophase) is output as low level, the pwm signal shown in 601 in Fig. 6 thereby be low level.As shown in 606 in Fig. 6, the signal RAW_LDR_EN of comparator 501 outputs is low level to t3 at t2 constantly, so the output of NAND gate 511 (being designated G1) (as: the LDR_EN signal shown in 602 in Fig. 6) is high level.Therefore, high-side switch 110 and low side switch 112 t2 to t3 constantly during in TOFF_BUCK state (high-side switch 110 cut-offs, low side switch 112 conductings).When high-side switch 110 and low side switch 112 are during at TOFF_BUCK state, because switching node 122 is through low side switch 112 ground connection, the switching node 122 voltage LX shown in 603 in Fig. 6 equal zero.
T2 to t3 constantly during, the electric current I _ in (or I (C1)) that flows through resistor 520 and flow through slope capacitor 508 shown in 604 in Fig. 6 is provided by equation (5) and (6).So, ramp signal 512 increases to be proportional to the speed of electric current I _ in and I (C1), until constantly equal nominal voltage V2 at t3.At t3 constantly, the output of comparator 501 (as: the signal RAW_LDR_EN shown in 606 in Fig. 6) transfers high level to.If SKIP signal is also high level (as: SKIP state is activated) at t3 constantly, the output of NAND gate 511 (as: the LDR_EN signal shown in 602 in Fig. 6) is low level.At t3 constantly, if feedback voltage V FB is greater than SLEW, receive from the low level of comparator 503 (being designated CMP3) and output low level to trigger 542 with door 522 (being designated G2), take and keep pwm signal as low level.Therefore,, during t3 arrives the t4 moment, controller 102B is in SKIP state.In response to the low level LDR_EN signal shown in 602 in the low level pwm signal shown in 601 in Fig. 6 and Fig. 6, high-side switch 110 and low side switch 112 all end.Yet if feedback voltage V FB is less than or equal to SLEW voltage when ramp signal 512 is increased to nominal voltage V2, SKIP state does not occur but directly enters TON_BUCK state.
Therefore,, under SKIP state (when high-side switch 110 and low side switch 112 all end), the switching node 122 voltage LX shown in 603 in Fig. 6 equal the output voltage V of DC/DC transducer 100B
oUT.In addition the electric current that, flows through resistor 520 and slope capacitor 508 is zero under SKIP state.Controller 102B keeps high-side switch 110 and low side switch 112 in SKIP state until the output voltage V of the indicated DC/DC transducer 100B of the feedback voltage V FB shown in 607 in Fig. 6
oUTdrop to predeterminated voltage value (as: SLEW voltage).When this situation is when t4 occurs constantly, the output of the comparator 503 of Fig. 5 transfers high level to.From the high level of comparator 503 and comparator 501 make in Fig. 5 with door 522 output high level, by trigger 542 set, thereby make the pwm signal shown in 601 in Fig. 6 transfer high level to.During t4 arrives the t6 moment, will repeat said process.
Controller 102B controls inductive current I
l1a kind of CRC controller with constant wave amplitude.Specifically, under TON_BUCK state, obtain following equation:
I_in＝C1＊(dV
508/dt)＝C1＊(-dV
512/dt)＝C1＊(-ΔV
512/T
ON)。(11)
V in equation (11)
508expression is across the voltage of slope capacitor 508, V
512the voltage level that represents ramp signal 512, C1 represents the capacitance of slope capacitor 508, Δ V
512represent voltage level V
512variable quantity during TON_BUCK state.Based on equation (1), (4) and (11), obtain following equation:
ΔI
L1＝-(ΔV
512＊C1)/(K＊L)。(12)
Δ I in equation (12)
l1represent inductive current I
l1variable quantity during TON_BUCK state.In like manner, under TOFF_BUCK state, obtain following equation:
I_in＝C1＊(dV
508/dt)＝C1＊(-dV
512/dt)＝C1＊(-ΔV
512/T
OFF)。(13)
Δ V in equation (13)
512represent voltage level V
512variable quantity during TOFF_BUCK state.Based on equation (2), (6) and (13), obtain following equation:
ΔI
L1＝-(ΔV
512＊C1)/(K＊L)。(14)
Δ I in equation (14)
l1represent inductive current I
l1variable quantity during TOFF_BUCK state.Due to the voltage variety Δ V during each TON_BUCK state
512with the voltage variety Δ V during each TOFF_BUCK state
512its value equates, so the current change quantity Δ I during each TON_BUCK state
l1with the current change quantity Δ I during each TOFF_BUCK state
l1its value equates.
In addition, be similar to the controller 102A in Fig. 3, in Fig. 5, work as output voltage V
oUTaverage voltage V
aVEbe less than the expection output voltage V on SLEW end
sETtime, controller 102B increases the duty ratio of pwm signal.As average voltage V
aVEbe greater than the expection output voltage V on SLEW end
sETtime, controller 102B reduces the duty ratio of pwm signal.As a result, controller 102B regulation output voltage V
oUTaverage voltage V
aVEto expecting output voltage V
sET.
Fig. 7 is the example block diagram of DC/DC transducer 100C according to an embodiment of the invention.DC/DC transducer 100C in Fig. 7 embodiment is a kind of boost converter.High-side switch 110 and low side switch 112 that DC/DC transducer 100C comprises controller 102C, drive circuit 704 and is connected to inductor 714.Controller 102C for generation of control signal to drive circuit 704, to drive high-side switch 110 and low side switch 112.Controller 102C regulates the duty ratio of DC/DC transducer 100C to control high-side switch 110 and low side switch 112, thereby controls the inductive current I that flows through inductor 714
l7and the output voltage V of DC/DC transducer 100C
oUT.Controller 102C, by changing the mode of pwm signal duty ratio, utilizes pwm signal to control the state of high-side switch 110 and low side switch 112.
In one embodiment, if pwm signal is high level, low side switch 112 conductings so, high-side switch 110 cut-offs.This state of high-side switch 110 and low side switch 112 is called as " switch ON " state or " TON_BOOST " state.Inductor 714 under this state is through switching node 122 ground connection.Therefore, inductive current I
l7from input (as input voltage V Fig. 7
iNthat end) flow through inductor 714 and flow to ground, and increase.If pwm signal is low level and HDR_EN signal is high level, low side switch 112 cut-offs so, high-side switch 110 conductings.This state of high-side switch 110 and low side switch 112 is called as " switch OFF " state or " TOFF_BOOST " state.In DC/DC transducer 100C (boost converter), the clean voltage across inductor 714 under this state is for negative.So, inductive current I
l7under TOFF_BOOST state, reduce.Therefore, the duty ratio of pwm signal is determined the time T of TON_BOOST state
oNand the time T of TOFF_BOOST state
oFF.Be similar to step-down controller, controller 102C utilizes the auxiliary pwm signal that produces of ramp signal 712.
Controller 102C comprises pulse-width modulation circuit 752 and oblique wave generating circuit 750.Pulse-width modulation circuit 752 comprise comparator 701 (being designated CMP1), comparator 702 (being designated CMP2), comparator 703 (being designated CMP3), with door 722 (being designated G2), NAND gate 723 (being designated G1), and latch 742.Comparator 701 provides and inputs to and door 722 and NAND gate 723.Output with door 722 reception comparators 703, then produces one and inputs to latch 742.Latch 742 provide and input to (may in pulse-width modulation circuit 752 peripheries) drive circuit 704 and with door 725 (being designated G3).The ramp signal 712 that pulse-width modulation circuit 752 receives from oblique wave generating circuit 750, and produce pwm signal in response to ramp signal 712.Oblique wave generating circuit 750 comprises operational amplifier 751 (being designated OA1) and slope capacitor 708, and to flowing through the electric current of resistor 720 and resistor 771, responds as described below.
Controller 102C also comprise switch 713 and with door 725, be connected with the output of comparator 703 in pulse-width modulation circuit 752 and the anti-phase output of latch 742 respectively with the input of door 725.Controller 102C also comprises resistor 720 and the resistor 771 of connecting with the switching node 122 of DC/DC transducer 100C.
Resistor 720 is connected with resistor 771 and can be regarded an equivalent resistor as and have the resistance value R that equals R1+R2.In one embodiment, R1 can equal R/6, and R2 equals 5*R/6.Oblique wave generating circuit 750 also comprises the slope capacitor 708 of connecting with resistor 720 and resistor 771.The inverting input of operational amplifier 751 is connected to the node 706 relevant with resistor 771 to the resistor 720 of connecting, and the in-phase input end of operational amplifier 751 receives the input voltage V of indication DC/DC transducer 100C
iNfeedback signal.Operational amplifier 751 is as integrator.The electric current that flows through resistor 720 and resistor 771 also flows through 708 chargings of 708 pairs of slope capacitors of slope capacitor or electric discharge, thereby controls ramp signal 712.
Ramp signal 712 is provided for the inverting input of comparator 701 and the in-phase input end of comparator 702.Nominal voltage V2 is provided for comparator 701 in-phase input ends.Reference voltage REF is provided for the inverting input of comparator 702.In one embodiment, reference voltage REF equals 2.5 volts, and nominal voltage V2 equals 0.01 volt.
Under TOFF_BOOST state, PWMB signal is high level, if output voltage V
oUTbe less than VSLEW voltage, with door 725 output high level.So switch 713 conductings, reduce resistance value R.Ramp signal 712 is decreased to nominal voltage V2 rapidly, makes the output of comparator 701 become high level, thereby by latch 742 set.PWMB signal becomes low level, thus cutoff switch 713.
Fig. 8 is for describing according to one embodiment of present invention the exemplary sequential chart 800 of the operating process of the controller 102C in Fig. 7.In the present embodiment, during t1 arrives the t2 moment, the HDR_EN signal shown in 802 in the pwm signal shown in 801 in Fig. 8 and Fig. 8 is high level.Therefore, low side switch 112 conductings, high-side switch 110 cut-offs.During t1 arrives the t2 moment, the switching node 122 voltage LX shown in 803 in Fig. 8 are zero.As shown in 804 in Fig. 8, during t1 arrives the t2 moment, the electric current I (C) that flows through resistor 720, resistor 771 and slope capacitor 708 is provided by following formula:
I(C)＝-V
IN/R＝-V
IN＊K。(15)
In response to the electric current I (C) that flows through slope capacitor 708, the ramp signal 712 shown in 805 in Fig. 8 increases constantly to t2 at t1.T1 to t2 constantly during, for example, because the electric current I (C) shown in 804 in Fig. 8 flows through slope capacitor 708 via operational amplifier 751: flow to slope capacitor 708 from the output of operational amplifier 751, the slope of ramp signal 712 is for just.
Once constantly latch 742 be resetted at t2, the Q of latch 742 (homophase) output becomes low level, so the pwm signal shown in 801 in Fig. 8 is low level.When high-side switch 110 and low side switch 112 are during in TOFF_BOOST state, the switching node 122 voltage LX shown in 803 in Fig. 8 equal output voltage V
oUT.This is via high-side switch 110 and output voltage V because of switching node 122
oUTconnect.
During t2 arrives the t3 moment, the electric current I (C) that flows through resistor 720 and resistor 771 shown in 804 in Fig. 8 is provided by following formula:
I(C)＝(V
OUT-V
IN)/R＝(V
OUT-V
IN)＊K。(16)
During t2 arrives the t3 moment, ramp signal 712 reduces to be proportional to the speed of electric current I (C).Ramp signal 712 reduces until equal to be input to the nominal voltage V2 of the in-phase input end of comparator 701.When ramp signal 712 is when t3 is decreased to nominal voltage V2 constantly, comparator 701 is output as high level.Be similar to ramp signal 512 and inductive current I in Fig. 5
l1, the ramp signal 712 in Fig. 7 when t3 is decreased to nominal voltage V2 constantly, inductive current I
l7in zero crossing (zero-crossing) state.Therefore, the not direct inductance measuring electric current I of controller 102C
l7, and be to provide zero crossing estimation device estimation inductive current I
l7.
Controller 102C controls inductive current I
l7a kind of CRC controller with constant wave amplitude.Specifically, under TON_BOOST state, obtain following equation:
dI
L7/dt＝V
IN/L＝ΔI
L7/T
ON。(17)
Δ I in equation (17)
l7represent inductive current I
l7variable quantity during TON_BOOST state.In addition, also obtain following equation:
I(C)＝C＊(dV
708/dt)＝C＊(-dV
712/dt)＝C＊(-ΔV
712/T
ON)。(18)
V in equation (18)
708expression is across the voltage of slope capacitor 708, V
712the voltage level that represents ramp signal 712, C represents the capacitance of slope capacitor 708, Δ V
712represent V
712variable quantity during TON_BOOST state.Based on equation (15), (17) and (18), obtain following equation:
ΔI
L7＝(ΔV
712＊C)/(K＊L)。(19)
In like manner, under TOFF_BOOST state, obtain following equation:
dI
L7/dt＝(V
IN-V
OUT)/L＝ΔI
L7I/T
OFF。(20)
Δ I in equation (20)
l7represent inductive current I
l7variable quantity during TOFF_BOOST state.In addition, also obtain following equation:
I(C)＝C＊(dV
708/dt)＝C＊(-dV
712/dt)＝C＊(-ΔV
712/T
OFF)。(21)
Δ V in equation (21)
712represent V
712variable quantity during TOFF_BOOST state.Based on equation (16), (20) and (21), obtain following equation:
ΔI
L7＝(ΔV
712＊C)/(K＊L)。(22)
Due to the Δ V during each TON_BOOST state
712with the Δ V during each TOFF_BOOST state
712its value equates, so the current change quantity Δ I during each TON_BOOST state
l7with the current change quantity Δ I during each TOFF_BOOST state
l7its value equates.
In addition, be similar to controller 102A in Fig. 3 and the controller 102B in Fig. 5, the controller 102C in Fig. 7 is in output voltage V
oUTaverage voltage V
aVEbe less than the expection output voltage V on target input SLEW
sETthe duty ratio of Shi Zengjia pwm signal.Controller 102C is in output voltage V
oUTaverage voltage V
aVEbe greater than the expection output voltage V on target input SLEW
sETtime reduce the duty ratio of pwm signal.As a result, controller 102C is by output voltage V
oUTaverage voltage V
aVEbe adjusted to expection output voltage V
sET.
Specifically, under TOFF_BOOST state, if when ramp signal 712 is decreased to nominal voltage V2, output voltage V
oUTstill be greater than VSLEW voltage, comparator 703 output low levels, are low level through keeping PWM with door 722 and latch 742, until output voltage V
oUTbe decreased to VSLEW voltage.So the time of TOFF_BOOST state increases, thereby reduce the duty ratio of pwm signal.If before ramp signal 712 is decreased to nominal voltage V2, output voltage V
oUTbe decreased to VSLEW voltage, comparator 703 output high level via with door 725 actuating switchs 713, thereby reduce the resistance value in path between node 706 and switching node 122.The electric current I (C) that flows through slope capacitor 708 increases, thereby has shortened the time of TOFF_BOOST state.So the duty ratio of pwm signal increases.As a result, output voltage V
oUTaverage voltage V
aVEbe adjusted to VSLEW voltage.
Fig. 9 is the exemplary method flowchart 900 of Current Control according to an embodiment of the invention.As shown in flow chart 900, comprising:
Step 902, produces ramp signal in response to the electric current that flows through the resistance of the switching node that is connected to DC/DC transducer, and wherein, described switching node is connected with low side switch with the high-side switch of described DC/DC transducer.
Step 904, produces pwm signal in response to described ramp signal.
The invention provides a kind of DC/DC transducer (as: step-down controller, boost converter) for by input voltage V
iNbe converted to output voltage V
oUT.Illustrate, Fig. 3 and Fig. 5 provide step-down DC/DC transducer 100A and DC/DC transducer 100B, and Fig. 7 provides the DC/DC transducer 100C that boosts.Described DC/DC transducer comprises CRC controller (as: controller 102A, controller 102B, or controller 102C), output current (as: the inductive current I for generation of ramp signal with control DC/DC transducer
l1or inductive current I
l7).Can utilize and control electric current (as: electric current I _ out or electric current I (C)) to slope capacitor (as: slope capacitor 308, slope capacitor 508, or slope capacitor 708) charging or electric discharge, to produce ramp signal, make ramp signal to be proportional to the velocity variations of described control electric current.In addition inductive current (as: inductive current I,
l1or inductive current I
l7) to be proportional to the velocity variations across the voltage of inductor (as: inductor 114 or inductor 714).Because described control electric current is proportional to the voltage across described inductor; See equation (4), (6), (15) and (16), so ramp signal is proportional to inductive current.Therefore, advantageously, can be constant by the wave amplitude of inductive current described in the wave amplitude constant control of the described ramp signal of control.In addition, the narrower operation transconductance amplifier 156 of bandwidth in Figure 1A has been removed, and makes CRC controller control more accurately the output of DC/DC transducer.Secondly, the capacitor 158 with higher capacitance value and larger volume has also been removed.CRC controller 102A, controller 102B, or all elements in controller 102C can be integrated in one chip.In addition, the oscillator in traditional controller has also been removed, thereby reduces power consumption.
For regulating, control electric current and be proportional to method across the voltage of inductor and comprise that the voltage of controlling across resistor (as: resistor 320, resistor 520, or resistor 720-771) equals or is proportional to the voltage across inductor.Illustrate, resistor has first end and the second end, and inductor has first end and the second end.The first end of resistor and the first end of inductor are connected to (as: switching node 122) on same node.The second terminal voltage of resistor is controlled to the second terminal voltage that approximates inductor.In the embodiment of Fig. 3, Fig. 5 and Fig. 7, DC/DC transducer 100A, DC/DC transducer 100B and DC/DC transducer 100C comprise respectively buffer 351, operational amplifier 551, and operational amplifier 751.Operational amplifier is transferred to the second terminal voltage of inductor on the second end of resistor.Yet, can utilize the second terminal voltage of the whole bag of tricks or means control resistor to approximate the second terminal voltage of inductor.
Figure 10 A is the example block diagram of DC/DC transducer 1000 according to an embodiment of the invention.In the embodiment of Figure 10 A, DC/DC transducer 1000 is a kind of boost converters, for by the input voltage V on low side 1088
iNconvert the output voltage V on high side 1086 to
oUT.As shown in Figure 10 A, DC/DC transducer 1000 comprises controller 1002, driver 1004, comprises the switching circuit of high-side switch 1010 and low side switch 1012, and energy storage elements (for example: inductor 1014).
In the embodiment of Figure 10 A, the high side path between inductor 1014 and high side 1086 comprises high-side switch 1010, and the low side path between inductor 1014 and ground comprises low side switch 1012.Yet in an interchangeable embodiment, high-side switch 1010 is replaced by diode.Described energy storage elements can be but not limit a kind of inductor 1014.Inductor 1014 comprises the first end 1013 that is connected to the switching node 1022 between high-side switch 1010 and low side switch 1012, and the second end 1015 that is connected to low side 1088.Inductor 1014 is for providing the output voltage V of DC/DC transducer 1000
oUT.
Controller 1002 comprises and enables output EN for providing high-side switch to enable (referred to as HDR_EN) signal 1082, and control output end PWM is used for providing pwm signal 1084.Controller 1002 also comprises that input LX is for the voltage on the first end 1013 of receiving inductance device 1014, input VFB1 is for the feedback voltage on the second end 1015 of receiving inductance device 1014, and first input end VFB2 is for receiving the output voltage V on high side 1086
oUT.Controller 1002 also comprises that whether effectively input SKIP controls HDR_EN signal 1082 SKIP signal for receiving.In addition, controller 1002 can also comprise output VREF and input SLEW.In one embodiment, input SLEW arranges output voltage V
oUTexpected value or desired value.In the embodiment of Figure 10 A, the resistance ratios of the capacitor 1026 that is connected to input SLEW based on resitstance voltage divider (resistor 1024 as shown in figure 10 and resistor 1028) and the voltage of output VREF are recharged, thereby predeterminated voltage V is provided
pREgive input SLEW.Yet the present invention is not limited to this; Other interchangeable methods also can be used for to capacitor 1026 chargings, to produce predeterminated voltage V
pREgive input SLEW.
In one embodiment, when 1012 conducting of high-side switch 1010 cut-off low side switch, the first end 1013 of inductor 1014 is via low side switch 1012 ground connection, and across the clean voltage of inductor 1014 for example, for just (: equal V
iN).The inductive current I of inductor 1014 flows through
l10for example, across the voltage of inductor 1014 (: equal V to be proportional to
iN) speed increase.Obtain following equation:
dI
L10/dt＝V
IN/L。(23)
Wherein, L represents the inductance value of inductor 1014.When high-side switch 1010 conducting low side switch 1012 cut-off, the first end 1013 of inductor 1014 is connected with high side 1086 via high-side switch 1010, and is (for example: equal V to bear across the clean voltage of inductor 1014
iN-V
oUT).Inductive current I
l10for example, across the voltage of inductor 1014 (: equal V to be proportional to
iN-V
oUT) speed reduce.Obtain following equation:
dI
L10/dt＝(V
IN-V
OUT)/L。(24)
In the present embodiment, inductive current I
l10for ripple current.When high-side switch 1010 conducting low side switch 1012 cut-off, inductive current I
l10flow into high side 1086.Be connected to energy storage units (as: output capacitance 1016) between high side 1086 and ground by inductive current I
l10charging, and output voltage V is provided
oUT.By alternately conducting and cut-off high-side switch 1010 and low side switch 1012, controller 1002 regulation output voltage V
oUTor output voltage V
oUTaverage voltage V
aVEto target voltage V
tARGET.In addition, controller 1002 is controlled inductive current I
l10there is the wave amplitude that is tending towards constant.Therefore, the output voltage V of DC/DC transducer 1000
oUTmore stable.
The control signal of controller 1002 generation such as HDR_EN signal 1082 and pwm signals 1084 is to driver 1004, to control/to drive high-side switch 1010 and low side switch 1012.Illustrate, high-side switch 1010 can be by high level signal conducting, low level signal cut-off.In like manner, low side switch 1012 can be by high level signal conducting, low level signal cut-off.By controlling the logic level of HDR_EN signal 1082 and pwm signal 1084, can control the state of high-side switch 1010 and low side switch 1012.
Form 1100 in Figure 11 has been described in response to HDR_EN signal 1082 and pwm signal 1084, the state variation of high-side switch 1010 and low side switch 1012.Below with reference to Figure 10 A, form 1100 is described.
As shown in form 1100, when HDR_EN signal and pwm signal are high level (that is: HDR_EN=1 and PWM=1), high-side switch 1010 cut-off low side switch 1012 conductings.This state is called TON_BOOST state.When HDR_EN signal is low level pwm signal while being high level (that is: HDR_EN=0 and PWM=1), high-side switch 1010 cut-off low side switch 1012 conductings.Therefore, high-side switch 1010 and low side switch 1012 are still in TON_BOOST state.Under TON_BOOST state, first end 1013 ground connection of inductor 1014, equal V across the voltage of inductor 1014
iN, and inductive current I
l10increase.When HDR_EN signal is high level pwm signal while being low level (that is: HDR_EN=1 and PWM=0), high-side switch 1010 conducting low side switch 1012 cut-offs.This state is called TOFF_BOOST state.Under TOFF_BOOST state, the first end 1013 of inductor 1014 is connected with high side 1086, across the voltage of inductor 1014, equals V
iN-V
oUT, and inductive current I
l10reduce.When HDR_EN signal and pwm signal are low level (that is: HDR_EN=0 and PWM=0), high-side switch 1010 and low side switch 1012 cut-offs.This state is called SKIP state.Under SKIP state, the first end 1013 of inductor 1014 unsettled (for example: not connecing high side 1086 does not have ground connection yet), and be zero across the voltage of inductor 1014.Inductive current I
l10also be zero.
Figure 10 B is the example block diagram of DC/DC transducer 1000 ' according to an embodiment of the invention.Figure 10 A has similar function with the sensible same element of 10B acceptance of the bid.As described in Figure 10 B, controller 1002 comprises ramp signal generator 1030, pwm signal generator 1040, and feedback circuit 1070.Ramp signal generator 1030 comprises energy storage units (as: slope capacitor 1008) and resistance I element (as: resistor 1020).Slope capacitor 1008 be connected to and pwm signal generator 1040 between.The first end 1023 of resistor 1020 is connected with the first end 1013 of inductor 1014, and second end 1025 process method/circuit 1018 of resistor 1020 are connected with slope capacitor 1008.
Ramp signal generator 1030 provides the control electric current I that flows through resistor 1020
c10electric energy with control store in slope capacitor 1008.The ramp signal generator 1030 also electric energy based on being stored in slope capacitor 1008 produces ramp signal 1032 (for example: across the voltage of slope capacitor 1008).The control circuit that comprises pwm signal generator 1040 and method/circuit 1018 is controlled electric current I by regulating resistor 1020 one end voltage control
c10make its indication (for example: linearity is proportional to) across the voltage of inductor 1014.Described control circuit is also controlled the inductive current I of the inductor 1014 of flowing through based on ramp signal 1032
l10in preset range.
More particularly, in the present embodiment, the first end 1023 voltage V of resistor 1020
1023equal the first end 1013 voltage V of inductor 1014
1013.The second end 1025 voltage V of method/circuit 1018 control resistors 1020
1025equal the second end 1015 voltage V of inductor 1014
1015.Therefore, the voltage across resistor 1020 approximates the voltage across inductor 1014.So, the control electric current I of the resistor 1020 of flowing through
c10linearity is proportional to the voltage V across inductor 1014
1013-V
1015, and provided by following formula: I
c10=(V
1013-V
1015)/R
rP.R
rPthe resistance that represents resistor 1020.Method/circuit 1018 can install in pwm signal generator 1040 the insides, or ramp signal generator 1030 the insides, or the built-up circuit of pwm signal generator 1040 and ramp signal generator 1030 the inside, or device is in the outside of pwm signal generator 1040 and ramp signal generator 1030.
Control electric current I
c10the electric energy of control store in slope capacitor 1008 for example, to regulate ramp signal 1032 (: across the voltage of slope capacitor 1008).Illustrate, under TON_BOOST state, control electric current I
c10by following formula, provided:
I
C10＝(V
1013-V
1015)/R
RP＝(0-V
IN)/R
RP。(25)
So obtain following equation:
I
C10＝C
RP＊dV
RP/dt＝-V
IN/R
RP。(26)
Wherein, C
rPthe capacitance that represents slope capacitor 1008, V
rPthe voltage level that represents ramp signal 1032.Therefore,, under TON_BOOST state, control electric current I
c10slope capacitor 1008 is discharged to reduce ramp signal 1032.In like manner, under TOFF_BOOST state, control electric current I
c10by following formula, provided:
I
C10＝(V
1013-V
1015)/R
RP＝(V
OUT-V
IN)/R
RP。(27)
So obtain following equation:
I
C10＝C
RP＊dV
RP/dt＝(V
OUT-V
IN)/R
RP。(28)
Therefore,, under TOFF_BOOST state, control electric current I
c10slope capacitor 1008 is charged to increase ramp signal 1032.
Based on equation (23) and (26), obtain following equation:
Δ I
l10/ T
oN=V
iN/ L; (29a)
C
RP＊ΔV
RP/T
ON＝-V
IN/R
RP。(29b)
Equation (29a) and (29b) in Δ I
l10represent inductive current I
l10variable quantity during TON_BOOST state, Δ V
rPrepresent voltage level V
rPvariable quantity during TON_BOOST state, T
oNthe time that represents TON_BOOST state.Based on equation (29a) and (29b), obtain following equation:
ΔI
L10＝-C
RP＊ΔV
RP＊R
RP/L。(30)
In like manner, based on equation (24) and (28), obtain following equation:
Δ I
l10/ T
oFF=(V
iN-V
oUT)/L; (31a)
C
RP＊ΔV
RP/T
OFF＝(V
OUT-V
IN)/R
RP。(31b)
Equation (31a) and (31b) in Δ I
l10represent inductive current I
l10variable quantity during TOFF_BOOST state, Δ V
rPrepresent voltage level V
rPvariable quantity during TOFF_BOOST state, T
oFFthe time that represents TOFF_BOOST state.Based on equation (31a) and (31b), obtain following equation:
ΔI
L10＝-C
RP＊ΔV
RP＊R
RP/L。(32)
Pwm signal generator 1040 is controlled high-side switch 1010 and low side switch 1012 these pair of switches based on ramp signal 1032, thereby controls the inductive current I of the inductor 1014 of flowing through
l10.Specifically, pwm signal generator 1040 produces pwm signal 1084 to control high-side switch 1010 and low side switch 1012.Pwm signal generator 1040 is also controlled the state of pwm signal 1084, makes ramp signal 1032 have the wave amplitude that is tending towards constant.Based on equation (30) and (32_), controller 1002 is by controlling the voltage variety Δ V of ramp signal 1032
rPbe tending towards constant in to control inductive current I
l10current change quantity Δ I
l10be tending towards constant.Therefore, controller 1002 is a kind of CRC controllers.
In addition, pwm signal generator 1040 is controlled high-side switch 1010 and low side switch 1012 these pair of switches based on ramp signal 1032, thereby controls the output voltage V of DC/DC transducer 1000 '
oUT.Specifically, feedback circuit 1070 receives output voltage V via first input end VFB2
oUT, and produce indication output voltage V
oUTfeedback signal (as: feedback voltage V
fB) to pwm signal generator 1040.Pwm signal generator 1040 is also based on feedback voltage V
fBcontrol the duty ratio of pwm signal 1084.Illustrate, pwm signal generator 1040 is in output voltage V
oUTaverage voltage V
aVEbe less than target voltage V
tARGETthe duty ratio of Shi Zengjia pwm signal 1084, at average voltage V
aVEbe greater than target voltage V
tARGETtime reduce the duty ratio of pwm signal 1084.Output voltage V
oUTaverage voltage V
aVEthereby be adjusted to target voltage V
tARGET.
Figure 12 is DC/DC transducer 1000A exemplary circuit diagram according to an embodiment of the invention.Figure 10 A, Figure 10 B and Figure 12 get the bid sensible with element there is similar function.As shown in figure 12, controller 1002A comprises ramp signal generator 1030A, pwm signal generator 1040A, and feedback circuit 1070.
Ramp signal generator 1030A comprises resistor 1020, slope capacitor 1008, switch 1232 and switch 1234.The first end 1023 of resistor 1020 is connected with the first end 1013 of inductor 1014, and the second end 1025 of resistor 1020 is connected with slope capacitor 1008 via switch 1234.Resistor 1020 in Figure 12 embodiment comprises inferior resistor 1220 (inferior resistor 1220 can be thought the second resistance element of the embodiment of the present invention) and time resistor 1221 (inferior resistor 1221 can be thought the first resistance element of the embodiment of the present invention) of mutual series connection.Switch 1232 is connected with the two ends of time resistor 1221.The resistance R of resistor 1020
rPequal the resistance R of time resistor 1220
rP0add resistor 1221 resistance R last time
rP1.
Pwm signal generator 1040A comprises the second comparator 1201 (being designated CMP1), the first comparator 1202 (being designated CMP2), off-centre circuit 1242, off-centre circuit 1252, set-reset flip-floop 1248, set-reset flip-floop 1258, logical AND gate 1262 (being designated G1), logical AND gate 1264 (being designated G2), and the 3rd comparator 1203 (being designated CMP3).As shown in figure 12, the in-phase input end of the inverting input of the second comparator 1201 and the first comparator 1202 is connected with slope capacitor 1008, and is connected with the second end 1025 of resistor 1020 via switch 1234.The in-phase input end of the second comparator 1201 is connected with the second end 1015 of inductor 1014 via off-centre circuit 1242.The inverting input of the first comparator 1202 is connected with the second end 1015 of inductor 1014 via off-centre circuit 1252.The 3rd comparator 1203 comprises the inverting input being connected with feedback circuit 1070, and provides the 3rd predeterminated voltage V
pREthe in-phase input end that connects of voltage source (not being presented in Figure 12), and the output being connected with logical AND gate 1264 with logical AND gate 1262.The reset terminal R of set-reset flip-floop 1248 is connected with the second comparator 1201 outputs, set end S is connected with logical AND gate 1262 outputs, in-phase output end Q is connected with controller 1002A control output end PWM, and reversed-phase output QB is connected with logical AND gate 1264 inputs.The reset terminal R of set-reset flip-floop 1258 is connected with set-reset flip-floop 1248 in-phase output end Q, set end S is connected with the first comparator 1202 outputs, in-phase output end Q is connected with logical AND gate 1262 inputs, and reversed-phase output QB is connected with the output EN that enables of controller 1002A.The input of logical AND gate 1262 is connected with the output of the 3rd comparator 1203 with the in-phase output end Q of set-reset flip-floop 1258, and output is connected with the set end S of set-reset flip-floop 1248.The reversed-phase output QB of the input of logical AND gate 1264 and set-reset flip-floop 1248 and the 3rd comparator 1203 output be connected, output is connected with the control end of switch 1232.In addition, the reversed-phase output QB of set-reset flip-floop 1258 is connected with the control end of switch 1234.
In the present embodiment, the second reference voltage V that the second comparator 1201 receives from off-centre circuit 1242
l, and pass through ramp signal 1032 and the second reference voltage V
lcomparison output signal is to set-reset flip-floop 1248.The second comparator 1201 is not more than the second reference voltage V at ramp signal 1032
ltime export high level signal, at ramp signal 1032, be greater than the second reference voltage V
ltime output low level signal.The first comparator 1202 receives from off-centre circuit 1,252 first reference voltage V
h(V
h> V
l), and pass through ramp signal 1032 and the first reference voltage V
hcomparison output signal is to set-reset flip-floop 1258.The first comparator 1202 is not less than the first reference voltage V at ramp signal 1032
htime export high level signal, at ramp signal 1032, be less than the first reference voltage V
htime output low level signal.
Set-reset flip-floop 1248 in the present embodiment can be triggered by the rising edge of input signal (as: asserts signal or reset signal).Illustrate, if there is the rising edge of asserts signal on the set end S of set-reset flip-floop 1248, the in-phase output end Q of set-reset flip-floop 1248 is set to high level and reversed-phase output QB is set to low level.If there is the rising edge of reset signal on the reset terminal R of set-reset flip-floop 1248, the in-phase output end Q of set-reset flip-floop 1248 is set to low level and reversed-phase output QB is set to high level.If set end S and reset terminal R are low level, the in-phase output end Q of set-reset flip-floop 1248 and the logic level of reversed-phase output QB remain unchanged until the appearance of set-reset flip-floop 1248 input signal rising edges so.
Controller 1002A passes through ramp signal 1032 and the second reference voltage V
land ramp signal 1032 and the first reference voltage V
hrelatively control wave amplitude and the inductive current I of ramp signal 1032
l10wave amplitude be tending towards constant.More particularly, pwm signal generator 1040A is according to ramp signal 1032 and the second reference voltage V
land ramp signal 1032 and the first reference voltage V
hrelatively control pwm signal 1084 duty ratios.When ramp signal 1032 is decreased to the second reference voltage V
ltime, the second comparator 1201 output high level reset set-reset flip-floop 1248, make its output low level pwm signal 1084.So ramp signal 1032 increases.The first reference voltage V when ramp signal 1032 is increased to
h, the first comparator 1202 output high level signals, are set to high level via set-reset flip-floop 1258, logical AND gate 1262 and set-reset flip-floop 1248 by pwm signal 1084.So ramp signal 1032 reduces.So, ramp signal 1032 has and equals the first reference voltage V
hmaximum and equal the second reference voltage V
lminimum value.So inductive current I
l10also there are maximum and minimum value (for example: inductive current I
l10be in the preset range based on ramp signal 1032).The wave amplitude of ramp signal 1032 equals the second reference voltage V
lwith the first reference voltage V
hpoor.Difference V
h-V
lfor constant, make the wave amplitude of ramp signal 1032 constant.Result inductive current I
l10wave amplitude also constant.
In the embodiment of Figure 12, for the second end 1025 voltage V of control resistor 1020
1025the the second end 1015 voltage V that are tending towards inductor 1014
1015method/circuit comprise: the second comparator 1201, the first comparator 1202, off-centre circuit 1242, and off-centre circuit 1252.Specifically, the second comparator 1201 is by voltage V
1025with the second reference voltage V
lcompare, thereby control voltage V
1025be not less than the second reference voltage V
l.The first comparator 1202 is by voltage V
1025with the first reference voltage V
hcompare, thereby control voltage V
1025be not more than the first reference voltage V
h.The second predeterminated voltage across off-centre circuit 1242 is V
s1, across the first predeterminated voltage of off-centre circuit 1252, be V
s2.So, offer the second reference voltage V of the second comparator 1201
lequal voltage V
1015deduct the second predeterminated voltage V
s1(as: V
l=V
1015-V
s1), offer the first reference voltage V of the first comparator 1202
hequal voltage V
1015add the first predeterminated voltage V
s2(as: V
h=V
1015+ V
s2).In one embodiment, across the second predeterminated voltage V of off-centre circuit 1242
s1with the first predeterminated voltage V across off-centre circuit 1252
s2substantially constant.In one embodiment, the second predeterminated voltage V
s1with the first predeterminated voltage V
s2can equate (as: V
s1=V
s2), make voltage V
1015be in the second reference voltage V
lwith the first reference voltage V
hcentre.In addition, with voltage V
1015compare the second predeterminated voltage V
s1with the first predeterminated voltage V
s2relatively little and can omit and disregard, make at the second reference voltage V
l(as: V
l=V
1015-V
s1) to the first reference voltage V
h(as: V
h=V
1015+ V
s2) the interior voltage V changing of scope
1025be considered to approximate voltage V
1015.
Off-centre circuit 1242 in Figure 12 embodiment comprises that resistance is R
s1resistor 1246.Off-centre circuit 1242 also comprises the predetermined current I that the resistor 1246 of flowing through is provided
s1current source 1244, making has the second predeterminated voltage V on resistor 1246
s1(as: V
s1=I
s1* R
s1).In like manner, off-centre circuit 1252 comprises that resistance is R
s2resistor 1256.Off-centre circuit 1252 also comprises the predetermined current I that the resistor 1256 of flowing through is provided
s2current source 1254, making has the first predeterminated voltage V on resistor 1256
s2(as: V
s2=I
s2* R
s2).Yet the present invention is not limited to this; Other interchangeable methods also can be used for producing the predeterminated voltage across off-centre circuit 1242 and off-centre circuit 1252.
In the embodiment of Figure 12, the second comparator 1201 and the first comparator 1202 are controlled ramp signal 1032 and are had constant wave amplitude, and control voltage V
1025be tending towards voltage V
1015.Yet, in another embodiment, ramp signal 1032 and voltage V
1025by different comparators, controlled.As, one or more comparators are controlled ramp signal 1032 and are had constant wave amplitude.Other one or more comparators are controlled voltage V
1025be tending towards voltage V
1015.In such enforcement, the scope of ramp signal 1032 and voltage V
1025scope can be identical or different.In such enforcement, can utilize current-controlled current source (as: circuit 324 in Fig. 3) to produce to equal the control electric current of electric current of resistor 1020 of flowing through, to control slope capacitor 1008.
Feedback circuit 1070 comprises the resitstance voltage divider (resistor 1272 as shown in Figure 12 and resistor 1274) being connected between high side 1086 and ground.Output voltage V
oUTand the resistance of resistor 1272 and resistor 1274 is determined feedback voltage V
fB.Yet the present invention is not limited to this; Other interchangeable methods also can be used for producing indication output voltage V
oUTfeedback signal.
As shown in figure 12, the 3rd comparator 1203 passes through feedback voltage V
fBwith the 3rd predeterminated voltage V
pREcomparison output signal 1260 is given logical AND gate 1262 and logical AND gate 1264.Signal 1260 is called " PULSE " signal.Logical AND gate 1264 output signals 1236 are the switch 1232 to time resistor 1221 with control connection.Signal 1236 is called signal for "faster" of water ski signaling or " ACCEL " signal.Switch 1232 is called " acceleration " switch.In addition the switch 1234 being connected between resistor 1020 and slope capacitor 1008, is called " time delay " switch.By utilizing comparator the 3 1203, logical AND gate 1262, logical AND gate 1264, acceleration switch 1232, delay switch 1234, set-reset flip-floop 1248, and set-reset flip-floop 1258, output voltage V
oUTaverage voltage V
aVEbe adjusted to target voltage V
tARGET.More particularly, on the one hand, if average voltage V
aVEbe less than target voltage V
tARGET, the 3rd comparator 1203 output high level PULSE signals 1260, are set to high level via logical AND gate 1264 by ACCEL signal 1236.Therefore, thus acceleration switch 1232 is switched on to increase the duty ratio of pwm signal 1084 increases average voltage V
aVE.On the other hand, if average voltage V
aVEbe greater than target voltage V
tARGET, the 3rd comparator 1203 output low level PULSE signals 1260.Low level PULSE signal 1260 remains low level via logical AND gate 1262 and set-reset flip-floop 1248 by pwm signal 1084, and keeps delay switch 1234 cut-offs, thereby makes the duty ratio of pwm signal 1084 reduce average voltage V
aVE.Below with reference to Figure 13, describe about output voltage V
oUTaverage voltage V
aVEadjustment process.
Figure 13 is relevant signal (as: the inductive current I of DC/DC transducer 1000A according to an embodiment of the invention and Figure 12
l10, output voltage V
oUT, ramp signal 1032, PULSE signal 1260, HDR_EN signal 1082, ACCEL signal 1236, and pwm signal 1084) exemplary sequential chart 1300.In the embodiment of Figure 13, the operation of controller 1002A comprises different mode, and for example: duty ratio reduces pattern, duty ratio normal mode, and duty ratio increases pattern.Illustrate the output voltage V in Figure 13
oUTwith predetermined level V '
tARGETfor reference level fluctuates up and down.(as: t under duty ratio normal mode
jto t
j+4constantly), when ramp signal 1032 is increased to the first reference voltage V
htime (as: at t
j+2constantly), output voltage V
oUTbe decreased to predetermined level V '
tARGET.Output voltage V
oUTaverage voltage V
aVEequal target voltage V
tARGET.In the present embodiment, target voltage V
tARGETapproximate predetermined level V'
tARGET.In duty ratio, reduce (as: t under pattern
ito t
i+4constantly), when ramp signal 1032 is increased to the first reference voltage V
htime (as: at t
i+2constantly), output voltage V
oUTbe greater than predetermined level V '
tARGET.Average voltage V
aVEbe greater than target voltage V
tARGET.So, the duty ratio that controller 1002A reduces pwm signal 1084 is to reduce average voltage V
aVE.(as: t under duty ratio increase pattern
kto t
k+3constantly), at ramp signal 1032, be increased to the first reference voltage V
houtput voltage V before
oUTbe decreased to predetermined level V'
tARGET(as: at t
k+2constantly).Average voltage V
aVEbe less than target voltage V
tARGET.So, the duty ratio that controller 1002A increases pwm signal 1084 is to increase average voltage V
aVE.
In embodiment as shown in figure 13, (as: t under duty ratio normal mode
jto t
j+4constantly), ACCEL signal 1236 is low level, HDR_EN signal 1082 is high level.PULSE signal 1260 and pwm signal 1084 homophases.For example, PULSE signal 1260 is high level at pwm signal 1084 during for high level, at pwm signal 1084, is low level during for low level.Ramp signal 1032 and inductive current I
l10there is sawtooth waveform.Because the wave amplitude of ramp signal 1032 is constant, inductive current I
l10wave amplitude constant.Output voltage V
oUTwith predetermined level V '
tARGETfor reference level fluctuates up and down, but output voltage V
oUTaverage voltage V
aVEequal target voltage V
tARGET.
More particularly, (as: t under the TON_BOOST of duty ratio normal mode state
jto t
j+1constantly), inductive current I
l10according to equation (23), increase, ramp signal 1032 reduces according to equation (26).In addition output voltage V,
oUTreduce.In response to the rising edge of pwm signal 1084 (as: at t
jconstantly), set-reset flip-floop 1258 is set to high level by HDR_EN signal 1082.During TON_BOOST state, because ramp signal 1032 is less than the first reference voltage V
h, the first comparator 1202 output low level signals are to set-reset flip-floop 1258, and HDR_EN signal 1082 keeps high level.Be connected to delay switch 1234 conductings between resistor 1020 and slope capacitor 1008.In addition, the reversed-phase output QB of set-reset flip-floop 1248 is low level, and ACCEL signal 1236 is ended for low level will speed up switch 1232.When ramp signal 1032 is decreased to the second reference voltage V
ltime (as: at t
j+1constantly), the second comparator 1201 output high level signals reset set-reset flip-floop 1248, make its output low level pwm signal 1084.At t
j+1constantly, HDR_EN signal 1082 is still high level.Therefore, DC/DC transducer 1000A enters TOFF_BOOST state.
(as: t under the TOFF_BOOST of duty ratio normal mode state
j+1to t
j+2constantly), inductive current I
l10according to equation (24), reduce, ramp signal 1032 increases according to equation (28).In addition output voltage V,
oUTreduce.Output capacitance 1016 has an equivalent series impedance (equivalent series resistance, referred to as ESR).Therefore, when high-side switch 1010 conducting low side switch 1012 cut-off (as: at t
j+1constantly), output voltage V
oUTcan be increased to relatively rapidly one and equal input voltage V
iNadd the level across the voltage of inductor 1014.At t
j+1constantly, output voltage V
oUTbe greater than predetermined level V '
tARGET(as: feedback voltage V
fBbe greater than the 3rd predeterminated voltage V
pRE).So, the low level PULSE signal 1260 that logical AND gate 1264 receives from the 3rd comparator 1203, and output low level ACCEL signal 1236 is to keep acceleration switch 1232 cut-offs.In addition, HDR_EN signal 1082 is high level and keeps delay switch 1234 conductings.
Under duty ratio normal mode, when ramp signal 1032 is increased to the first reference voltage V
htime (as: at t
j+2constantly), output voltage V
oUTbe decreased to predetermined level V '
tARGET.The first comparator 1202 output high level signals, to set-reset flip-floop 1258, are set to high level by the in-phase output end Q of set-reset flip-floop 1258.Secondly, the 3rd comparator 1203 output high level PULSE signals 1260.So logical AND gate 1262 output high level signals are set to high level to set-reset flip-floop 1248 by pwm signal 1084.In one embodiment, when receiving from moment of the high level signal of the first comparator 1202 and as the reset terminal R of set-reset flip-floop 1258, the set end S of set-reset flip-floop 1258 receives life period interval delta T between moment of high level pwm signal 1084
1.Time interval Δ T
1relatively short.In other words, HDR_EN signal 1082 is at time interval Δ T
1interior (as the t in figure
j, t
j+2, t
j+4constantly) in low level, and the duration of this state is relatively short.With time T
oNand time T
oFFcompare time interval Δ T
1can ignore.In one embodiment, logical AND gate 1264 is at time interval Δ T
2interior reception is from the high level signal of the reversed-phase output QB of set-reset flip-floop 1248 with from the high level PULSE signal 1260 of the 3rd comparator 1203.Time interval Δ T
2relatively short.In other words, ACCEL signal 1236 is at time interval Δ T
2interior (as the t in Figure 13
j, t
j+2, t
j+4constantly) in high level, and the duration of this state is relatively short.With time T
oNand time T
oFFcompare time interval Δ T
2can ignore.
In duty ratio, reduce (as: t under pattern
ito t
i+4constantly), ACCEL signal 1236 is low level, HDR_EN signal 1082 can be high level or low level.In duty ratio, reduce (as: t under the TON_BOOST state of pattern
ito t
i+1constantly), inductive current I
l10, output voltage V
oUT, ramp signal 1032, PULSE signal 1260, HDR_EN signal 1082, ACCEL signal 1236, and the TON_BOOST state (as: t of the state of pwm signal 1084 and duty ratio normal mode
ito t
i+1constantly) under situation similar.Yet, in duty ratio, reduce (as: t under the TOFF_BOOST state of pattern
i+1to t
i+2constantly), when ramp signal 1032 is increased to the first reference voltage V
htime (as: at t
i+2constantly), output voltage V
oUTbe greater than predetermined level V'
tARGET.Therefore, as at t
i+2constantly, PULSE signal 1260 is low level, makes logical AND gate 1262 output low level signals to set-reset flip-floop 1248, and pwm signal 1084 is remained to low level.Meanwhile, the first comparator 1202 output high level signals, by set-reset flip-floop 1258 set, make its output low level HDR_EN signal 1082.Therefore, DC/DC transducer 1000A enters SKIP state (as: at t
i+2to t
i+3constantly).
Under SKIP state, HDR_EN signal 1082, by delay switch 1234 cut-offs that are connected between resistor 1020 and slope capacitor 1008, remains unchanged ramp signal 1032.In addition, because output capacitance 1016 electric discharges are to load (not showing in Figure 12), output voltage V
oUTcontinue to reduce.Work as output voltage V
oUTbe decreased to predetermined level V '
tARGETtime (as: at t
i+3constantly), the 3rd comparator 1203 output high level PULSE signals 1260 are given logical AND gate 1262.Because the in-phase output end Q of set-reset flip-floop 1258 is also high level, logical AND gate 1262 output high level signals are set to high level to set-reset flip-floop 1248 by pwm signal 1084.In response to this pwm signal 1084, set-reset flip-floop 1258 is set to high level by HDR_EN signal 1082, and conducting delay switch 1234.In other words, at t
i+3constantly, DC/DC transducer 1000A enters new TON_BOOST state.As a result, under duty ratio reduces pattern, the duty ratio of pwm signal 1084 reduces.
(as: t under duty ratio increase pattern
kto t
k+3constantly), ACCEL signal 1236 can be high level or low level, and HDR_EN signal 1082 is high level.(as: t under the TON_BOOST state of duty ratio increase pattern
kto t
k+1constantly), inductive current I
l10, output voltage V
oUT, ramp signal 1032, PULSE signal 1260, HDR_EN signal 1082, ACCEL signal 1236, and (as: t under the TON_BOOST state of the state of pwm signal 1084 and duty ratio normal mode
ito t
i+1constantly) situation similar.Yet, (as: t under the TOFF_BOOST state of duty ratio increase pattern
k+1to t
k+2constantly), at ramp signal 1032, be increased to the first reference voltage V
hbefore, output voltage V
oUTbe decreased to predetermined level V '
tARGET(as: at t
k+2constantly).Therefore, as at t
k+2constantly, PULSE signal 1260 is high level.In addition, the reversed-phase output QB of set-reset flip-floop 1248 is high level.Therefore, logical AND gate 1264 output high level ACCEL signals 1236 are with conducting acceleration switch 1232.The resistance R of resistor 1020
rP(for example: from R reduce
rP0+ R
rP1be decreased to R
rP0), and control electric current I
c10increase.So ramp signal 1032 is from the second reference voltage V
lbe increased to the first reference voltage V
hneeded time shorten.When ramp signal 1032 is increased to the first reference voltage V
htime (as: at t
k+3constantly), the first comparator 1202 output high level signals are via set-reset flip-floop 1258, logical AND gate 1262, and set-reset flip-floop 1248 is set to high level by pwm signal 1084.Therefore, at t
k+3constantly, DC/DC transducer 1000A enters new TON_BOOST state.As a result, under duty ratio increase pattern, the duty ratio of pwm signal 1084 increases.
Controller 1002A is according to output voltage V
oUTstate automatically select to be operated in duty ratio and reduce pattern, duty ratio normal mode, or under duty ratio increase pattern.As a result, output voltage V
oUTaverage voltage V
aVEbe adjusted to target voltage V
tARGET.Output voltage V
oUTfluctuating range relatively little, can ignore.Therefore, output voltage V
oUTapproximate target voltage V
tARGET.
Figure 14 is the exemplary circuit diagram of DC/DC transducer 1000B according to an embodiment of the invention.Figure 10 A, Figure 10 B, Figure 12 and Figure 14 get the bid sensible with element there is similar function.As shown in figure 14, controller 1002B comprises ramp signal generator 1030B, pwm signal generator 1040B, and feedback circuit 1070.
Ramp signal generator 1030B comprises resistor 1020, slope capacitor 1008, and switch 1436.The first end 1023 of resistor 1020 is connected with the first end 1013 of inductor 1014, and the second end 1025 of resistor 1020 is connected with the second end 1015 of inductor 1014 via switch 1436.Slope capacitor 1008 is connected between second end 1025 and ground of resistor 1020.
Pwm signal generator 1040B comprises off-centre circuit 1442, the 4th comparator 1401 (being designated CMP1), the 5th comparator 1402 (being designated CMP2), comparator 1403 (being designated CMP3), set-reset flip-floop 1448, and logical AND gate 1462 (being designated G1).The in-phase input end of the 4th comparator 1401 is connected with the second end 1015 of inductor 1014 via off-centre circuit 1442, and inverting input is connected with the second end 1025 of resistor 1020, and output is connected with the reset terminal R of set-reset flip-floop 1448.The in-phase input end of the 5th comparator 1402 is connected with the first end (switching node 1022 as shown in FIG.) of high-side switch 1010, inverting input is connected with second end (high side 1086 as shown in Figure 14) of high-side switch 1010, and output is connected with the output EN that enables of controller 1002B.The in-phase input end of comparator 1403 with predeterminated voltage V is provided
pREvoltage source (in Figure 14 do not show) connect, inverting input is connected with feedback circuit 1070, output is connected with logical AND gate 1462.The input of logical AND gate 1462 is connected with the reversed-phase output QB of comparator 1403 and set-reset flip-floop 1448, and output is connected with the set end S of set-reset flip-floop 1448.The reversed-phase output QB of set-reset flip-floop 1448 is also connected with the control end of switch 1436.In addition, the in-phase output end Q of set-reset flip-floop 1448 and the control output end PWM of controller 1002B are connected.
In the present embodiment, the 3rd reference voltage V ' that the 4th comparator 1401 receives from off-centre circuit 1442
l, and pass through ramp signal 1032 and the 3rd reference voltage V '
lcomparison output signal is to set-reset flip-floop 1448.The 4th comparator 1401 is not more than the 3rd reference voltage V ' at ramp signal 1032
ltime export high level signal, at ramp signal 1032, be greater than the 3rd reference voltage V'
ltime output low level signal.The 5th comparator 1402 receives high-side switch 1010 first end voltage V
sWH(as: V
sWH=V
1013) and high-side switch 1,010 second terminal voltage V
sWL(as: V
sWL=V
oUT), and pass through first end voltage V
sWHwith the second terminal voltage V
sWLcomparison output signal enables output EN to controller 1002B's.The 5th comparator 1402 is at first end voltage V
sWHbe greater than the second terminal voltage V
sWLtime export high level, at first end voltage V
sWHbe not more than the second terminal voltage V
sWLtime output low level.In addition, be similar to the mode of describing in Figure 12, set-reset flip-floop 1448 is triggered by the rising edge of input signal.
In the present embodiment, controller 1002B passes through ramp signal 1032 and the 3rd reference voltage V '
lcompare, and by first end voltage V
sWHwith the second terminal voltage V
sWLrelatively, control wave amplitude and the inductive current I of ramp signal 1032
l10wave amplitude constant.More particularly, pwm signal generator 1040B is according to ramp signal 1032 and the 3rd reference voltage V'
lthe state of relatively controlling pwm signal 1084, and control according to first end voltage V
sWHwith the second terminal voltage V
sWLthe state of relatively controlling HDR_EN signal 1082.
When pwm signal 1084 is high level, inductive current I
l10increase, and ramp signal 1032 reduces.As inductive current I
l10while being increased to particular value (for example: when ramp signal 1032 is decreased to the 3rd reference voltage V'
ltime), the 4th comparator 1401 output high level signals reset set-reset flip-floop 1448.So set-reset flip-floop 1448 is set to low level to reduce inductive current I by pwm signal 1084
l10.Meanwhile, the reversed-phase output QB of set-reset flip-floop 1448 is high level, by switch 1436 conductings, makes ramp signal 1032 by control, be equaled the second end 1015 voltage V of inductor 1014
1015.High-side switch 1010 in this example has conducting resistance (on-resistance), if make inductive current I
l10(for example: zero ampere) first end voltage V be greater than preset value
sWHbe greater than the second terminal voltage V
sWL.As inductive current I
l10for example, while being decreased to described preset value (: zero ampere), first end voltage V
sWHbe decreased to the second terminal voltage V
sWLso the 5th comparator 1402 is set to low level with cut-off high-side switch 1010 by HDR_EN signal 1082.Therefore, inductive current I
l10(for example: zero ampere) be not less than described preset value.Comparator 1403 is according to output voltage V
oUTcan again pwm signal 1084 be set to high level.As a result, ramp signal 1032 has one to equal voltage V
1015maximum and one equal the 3rd reference voltage V '
lminimum value.Inductive current I
l10also there are maximum and minimum value (for example: inductive current I
l10be in the preset range based on ramp signal 1032).The wave amplitude of ramp signal 1032 equals voltage V
1015with the 3rd reference voltage V '
lpoor.Difference V
1015-V '
lconstant, make the wave amplitude of ramp signal 1032 constant.Result inductive current I
l10wave amplitude constant.
In the embodiment of Figure 14, switching circuit comprises high-side switch 1010 and low side switch 1012.Yet in an interchangeable embodiment, diode has replaced high-side switch 1010, and the 5th comparator 1402 has been removed.Specifically, the negative electrode of described diode is connected with high side 1086, and positive pole is connected with switching node 1022.Therefore, when low side switch 1012 conducting, described diode reverse biased.As low side switch 1012 cut-off and inductive current I
l10be greater than zero ampere-hour, described diode forward biasing.As inductive current I
l10be decreased to zero ampere-hour, described diode cut-off.
In the embodiment of Figure 14, for the second end 1025 voltage V of control resistor 1020
1025the the second end 1015 voltage V that are tending towards inductor 1014
1015method/circuit comprise: off-centre circuit 1442, the 4th comparator 1401, set-reset flip-floop 1448, and switch 1436.Specifically, the 4th comparator 1401 is by voltage V
1025with the 3rd reference voltage V '
lrelatively with according to described relatively control switch 1436.As voltage V
1025be decreased to the 3rd reference voltage V '
ltime, switch 1436 conductings make voltage V
1025controlled and equaled voltage V
1015.Therefore, voltage V
1025be in the 3rd reference voltage V'
lto voltage V
1015scope in.Predeterminated voltage across off-centre circuit 1442 is V
s3, and offer the 3rd reference voltage V ' of the 4th comparator 1401
lequal voltage V
1015deduct predeterminated voltage V
s3, for example: V '
l=V
1015-V
s3.The predeterminated voltage V across off-centre circuit 1442 in the present embodiment
s3for steady state value.In addition, with voltage V
1015compare predeterminated voltage V
s3relatively little, can ignore, make at the 3rd reference voltage V '
lto voltage V
1015the voltage V changing in scope
1025be considered to approximate voltage V
1015.
In the embodiment of Figure 14, the 4th comparator 1401 is controlled ramp signal 1032 and is had constant wave amplitude, and controls voltage V
1025be tending towards voltage V
1015.Yet, in another embodiment, ramp signal 1032 and voltage V
1025by different comparators, controlled.In such enforcement, the scope of ramp signal 1032 and voltage V
1025scope can be identical or different.In such enforcement, can utilize current-controlled current source (as: circuit 324 in Fig. 3) to produce to equal the control electric current of electric current of resistor 1020 of flowing through, to control slope capacitor 1008.
In the present embodiment, by utilizing comparator 1403, logical AND gate 1462 and set-reset flip-floop 1448, output voltage V
oUTaverage voltage V
aVEbe adjusted to target voltage V
tARGET.Below with reference to Figure 15, describe about output voltage V
oUTaverage voltage V
aVEadjustment process.
Figure 15 is relevant signal (as: the inductive current I of DC/DC transducer 1000B according to an embodiment of the invention and Figure 14
l10, output voltage V
oUT, ramp signal 1032, PULSE signal 1460, HDR_EN signal 1082, and pwm signal 1084) exemplary sequential chart 1500.
As shown in figure 15, the operation of controller 1002B comprises different mode, and for example: duty ratio reduces pattern, duty ratio normal mode, and duty ratio increases pattern.(as: t under duty ratio normal mode
nto t
n+4constantly), as inductive current I
l10be decreased to preset value I
pREtime (as: at t
n+2constantly), output voltage V
oUTbe decreased to predetermined level V'
tARGET.Output voltage V
oUTaverage voltage V
aVEequal target voltage V
tARGET.In the present embodiment, preset value I
pREampere equals zero.In duty ratio, reduce (as: t under pattern
mto t
m+4constantly), work as I
l10be decreased to preset value I
pREtime (as: at t
m+2constantly), output voltage V
oUTbe greater than predetermined level V'
tARGET.Average voltage V
aVEbe greater than target voltage V
tARGET.So, the duty ratio that controller 1002B reduces pwm signal 1084 is to reduce average voltage V
aVE.(as: t under duty ratio increase pattern
sto t
s+3constantly), at inductive current I
l10be decreased to preset value I
pREoutput voltage V before
oUTbe decreased to predetermined level V'
tARGET(as: at t
s+2constantly).Average voltage V
aVEbe less than target voltage V
tARGET.So, the duty ratio that controller 1002B increases pwm signal 1084 is to increase average voltage V
aVE.
In embodiment as shown in figure 15, under duty ratio normal mode, HDR_EN signal 1082 is anti-phase with pwm signal 1084.As, HDR_EN signal 1082 is low level when PWM is high level, is high level when PWM is low level.PULSE signal 1460 and pwm signal 1084 homophases.If, PULSE signal 1460 is high level at pwm signal 1084 during for high level, at pwm signal 1084, be low level during for low level.Ramp signal 1032 is (as: t when TON_BOOST state
nto t
n+1constantly) reduce (as: t when TOFF_BOOST state
n+1to t
n+2constantly) equal voltage V
1015.Inductive current I
l10there is sawtooth waveform.Because the wave amplitude of ramp signal 1032 is constant, inductive current I
l10wave amplitude constant.Output voltage V
oUTwith predetermined level V'
tARGETfor reference level fluctuates up and down, but output voltage V
oUTaverage voltage V
aVEequal target voltage V
tARGET.As described above, predetermined level V '
tARGETapproximate target voltage V
tARGET.
More particularly, (as: t under the TON_BOOST of duty ratio normal mode state
nto t
n+1constantly), inductive current I
l10according to equation (23), increase, ramp signal 1032 reduces according to equation (26), and output voltage V
oUTreduce.Pwm signal 1084 is high level.Because high-side switch 1010 cut-offs, low side switch 1012 conductings, so switching node 1022 ground connection.Therefore, the first end voltage V of high-side switch 1010
sWHbe less than the second terminal voltage V of high-side switch 1010
sWL, the 5th comparator 1402 is set to low level by HDR_EN signal 1082.In addition output voltage V,
oUTbe less than predetermined level V '
tARGET(for example: feedback voltage V
fBbe less than predeterminated voltage V
pRE), so comparator 1403 is set to high level by PULSE signal 1460.
When ramp signal 1032 is decreased to the 3rd reference voltage V '
ltime (as: at t
n+1constantly), the 4th comparator 1401 output high level signals reset set-reset flip-floop 1448, make its output low level pwm signal 1084.So low side switch 1012 cut-offs.Secondly, the reversed-phase output QB of set-reset flip-floop 1448 is set to high level with actuating switch 1436.At t
n+1constantly, inductor 1014, resistor 1020 and switch 1436 form current circuit.Inductor 1014 releases energy (for example: magnetic field energy is converted to electric energy) via described current circuit, so voltage V
1013be greater than voltage V
1015.T in the present embodiment
n+1constantly, first end voltage V
sWH(for example: V
sWH=V
1013) be greater than the second terminal voltage V
sWL(for example: V
sWL=V
oUT), make the 5th comparator 1402 that HDR_EN signal 1082 is set to high level with conducting high-side switch 1010.Therefore, DC/DC transducer 1000B enters TOFF_BOOST state.
(as: t under TOFF_BOOST state
n+1to t
n+2constantly), high-side switch 1010 conductings, output voltage V
oUTbe greater than predetermined level V '
tARGET.So, comparator 1403 output low level PULSE signals 1460.Inductive current I
l10via high-side switch 1010, flow into high side 1086.Along with inductive current I
l10reduce, across the voltage of high-side switch 1010 (for example: V
sWH-V
sWL) reduce.As inductive current I
l10be decreased to zero ampere-hour, first end voltage V
sWHbe decreased to the second terminal voltage V
sWL.Therefore, as t
n+2constantly, the 5th comparator 1402 is set to low level with cut-off high-side switch 1010 by HDR_EN signal 1082.In addition, under duty ratio normal mode, as inductive current I
l10be decreased to zero ampere-hour, output voltage V
oUTbe decreased to predetermined level V '
tARGET.Therefore, at t
n+2constantly, comparator 1403 output high level PULSE signals 1460 are set to high level via logical AND gate 1462 and set-reset flip-floop 1448 by pwm signal 1084.DC/DC transducer 1000B is at t
n+2constantly enter new TON_BOOST state.
In duty ratio, reduce (as: t under the TON_BOOST state of pattern
mto t
m+1constantly), inductive current I
l10, output voltage V
oUT, ramp signal 1032, PULSE signal 1460, HDR_EN signal 1082, and (as: t under the TON_BOOST state of the state of pwm signal 1084 and duty ratio normal mode
nto t
n+1constantly) situation similar.Yet, in duty ratio, reduce (as: t under the TOFF_BOOST state of pattern
m+1to t
m+2constantly), as inductive current I
l10be decreased to preset value I
pRE(for example: in the time of zero ampere), output voltage V
oUTbe greater than predetermined level V '
tARGET.Therefore, as at t
m+2to t
m+3, during the moment, comparator 1403 output low level PULSE signals 1460 remain low level via G1 and set-reset flip-floop 1448 by pwm signal 1084.Meanwhile, HDR_EN signal 1082 is low level.Therefore, DC/DC transducer 1000B enters SKIP state (as: at t
m+2to t
m+3constantly).
Under SKIP state, inductive current I
l10be zero ampere, ramp signal 1032 remains on voltage V
1015, output voltage V
oUTreduce.Work as output voltage V
oUTbe decreased to predetermined level V '
tARGETtime (as: at t
m+3constantly), comparator 1403 output high level PULSE signals 1460 are set to high level via logical AND gate 1462 and set-reset flip-floop 1448 by pwm signal 1084.Therefore, DC/DC transducer 1000B is at t
m+3constantly enter new TON_BOOST state.As a result, under duty ratio reduces pattern, the duty ratio of pwm signal 1084 reduces.
(as: t under the TON_BOOST state of duty ratio increase pattern
sto t
s+1constantly), inductive current I
l10, output voltage V
oUT, ramp signal 1032, PULSE signal 1460, HDR_EN signal 1082, and (as: t under the TON_BOOST state of the state of pwm signal 1084 and duty ratio normal mode
nto t
n+1constantly) situation similar.Yet, (as: t under the TOFF_BOOST state of duty ratio increase pattern
s+1to t
s+2constantly), at inductive current I
l10be decreased to preset value I
pRE(for example: zero ampere) before, output voltage V
oUTbe decreased to predetermined level V'
tARGET(as: at t
s+2constantly).Therefore, as at t
s+2constantly, comparator 1403 output high level PULSE signals 1460 are set to high level by pwm signal 1084.In other words, DC/DC transducer 1000B is at inductive current I
l10be decreased to preset value I
pREenter new TON_BOOST state before.As a result, under duty ratio increase pattern, the duty ratio of pwm signal 1084 increases.
Controller 1002B is according to output voltage V
oUTstate automatically select to be operated in duty ratio and reduce pattern, duty ratio normal mode, or under duty ratio increase pattern.As a result, output voltage V
oUTbe adjusted to target voltage V
tARGET.
Figure 16 is the exemplary method flowchart 1600 of Current Control according to an embodiment of the invention.Below with reference to Figure 10 A, Figure 10 B, Figure 12, and Figure 14 is described Figure 16.
In step 1602, controller 1002, controller 1002A or controller 1002B provide the control electric current I of the resistor 1020 of flowing through
c10electric energy with control store in slope capacitor 1008;
In step 1604, the second end 1025 voltage V of controller 1002, controller 1002A or controller 1002B regulating resistor 1020
1025the the second end 1015 voltage V that are tending towards inductor 1014
1015;
In step 1606, controller 1002, controller 1002A or controller 1002B the second end 1025 voltage V based on resistor 1020
1025control electric current I
c10indication (for example: linearity is proportional to) is across the voltage of inductor 1014;
In step 1608, controller 1002, controller 1002A or the controller 1002B electric energy based on being stored in slope capacitor 1008 produces ramp signal 1032;
In step 1610, controller 1002, controller 1002A or controller 1002B control the inductive current I of the inductor 1014 of flowing through based on ramp signal 1032
l10in preset range.
In the present embodiment, controller 1002, controller 1002A or controller 1002B are by controlling the wave amplitude constant control inductive current I of ramp signal 1032
l10wave amplitude constant.
To sum up, the invention provides the DC/DC transducer (for example: step-down controller, boost converter etc.) with CRC controller.CRC controller regulates the output voltage of DC/DC transducer to target level.In addition, CRC controller utilizes resistance element, inductive element, capacitive element, and the output current that the element such as comparator or circuit are controlled DC/DC transducer has constant wave amplitude.Therefore, the output voltage of DC/DC transducer and electric current are more stable.This kind of DC/DC transducer can be widely used in integrated circuit, diode, and in the power system of display system etc.
Although explanation and accompanying drawing have before been described embodiments of the invention, be to be understood that and variously augment, revise and replace not departing from can have under the spirit of the principle of the invention that appended claim book defines and the prerequisite of invention scope.It should be appreciated by those skilled in the art that the present invention can change to some extent in form, structure, layout, ratio, material, element, assembly and other side according to concrete environment and job requirement in actual applications under the prerequisite that does not deviate from invention criterion.Therefore, at the embodiment of this disclosure, be only illustrative rather than definitive thereof, the present invention's scope is defined by appended claim and legal equivalents thereof, and is not limited to description before this.
Claims (45)
1. a controller, is characterized in that, described controller comprises:
Ramp signal generator, for control electric current that the resistance element of flowing through is provided with control store the energy in the first energy storage elements, and based on the described power generation ramp signal being stored in the first energy storage elements; And
Be connected to the control circuit of described ramp signal generator, for regulating described resistance element one terminal voltage to control described control electric current indication across the voltage of the second energy storage elements, and the electric current of controlling described the second energy storage elements of flowing through based on described ramp signal is in preset range
Wherein, described control circuit comprises:
The first comparator, for by described resistance element one terminal voltage and the first reference voltage comparison; And
The second comparator, for by described resistance element one terminal voltage and the second reference voltage comparison,
Wherein, described the first reference voltage equals described the second energy storage elements one terminal voltage and adds the first predeterminated voltage, and described the second reference voltage equals described the second energy storage elements one terminal voltage and deducts the second predeterminated voltage.
2. controller according to claim 1, is characterized in that, described the first energy storage elements comprises capacitor.
3. controller according to claim 1, is characterized in that, described the second energy storage elements comprises inductor.
4. controller according to claim 1, is characterized in that, described resistance element comprises resistor.
5. controller according to claim 1, is characterized in that, described control circuit regulates described resistance element one terminal voltage to be tending towards described the second energy storage elements one terminal voltage.
6. controller according to claim 1, is characterized in that, described control circuit also comprises:
The 3rd comparator, for indicating feedback voltage and the 3rd predeterminated voltage comparison of described controller first input end voltage, with output pulse signal, thereby control acceleration switch and delay switch, wherein, described acceleration switch is connected with the two ends of the first resistance element in described resistance element, described the first resistance element and the second resistance element that described resistance element comprises series connection, in addition, described delay switch is connected between described resistance element and described the first energy storage elements.
7. controller according to claim 1, is characterized in that, described control circuit is controlled described control electric current linearity and is proportional to the described voltage across the second energy storage elements.
8. controller according to claim 1, is characterized in that, described control circuit comprises:
Be connected to the pulse-duration modulation signal generator of described the first energy storage elements, for generation of pulse-width signal, to control the conduction of high side path and low side path, wherein said high side path is connected with described the second energy storage elements via switching node with low side path.
9. controller according to claim 8, is characterized in that, described control circuit is described ramp signal and described the first reference voltage and described the second reference voltage comparison, according to described, relatively controls described pulse-width signal.
10. controller according to claim 1, is characterized in that, described control circuit is constant by controlling the electric current wave amplitude of second energy storage elements of flowing through described in described ramp signal wave amplitude constant control.
11. 1 kinds of controllers, is characterized in that, described controller comprises:
Ramp signal generator, for control electric current that the resistance element of flowing through is provided with control store the energy in the first energy storage elements, and based on the described power generation ramp signal being stored in the first energy storage elements; And
Be connected to the control circuit of described ramp signal generator, for regulating described resistance element one terminal voltage to control described control electric current indication across the voltage of the second energy storage elements, and the electric current of controlling described the second energy storage elements of flowing through based on described ramp signal is in preset range
Wherein, described control circuit comprises the first comparator, be used for described resistance element one terminal voltage and reference voltage comparison, according to the switch of described relatively control connection between described resistance element one end and described second energy storage elements one end, wherein said reference voltage equals described the second energy storage elements one terminal voltage and deducts predeterminated voltage.
12. controllers according to claim 11, is characterized in that, described control circuit also comprises:
The second comparator, for by the voltage ratio of the voltage of described controller first input end and the described second energy storage elements other end, with output enable signal.
13. controllers according to claim 11, is characterized in that, described the first energy storage elements comprises capacitor.
14. controllers according to claim 11, is characterized in that, described the second energy storage elements comprises inductor.
15. controllers according to claim 11, is characterized in that, described resistance element comprises resistor.
16. controllers according to claim 11, is characterized in that, described control circuit regulates described resistance element one terminal voltage to be tending towards described the second energy storage elements one terminal voltage.
17. controllers according to claim 11, is characterized in that, described control circuit is controlled described control electric current linearity and is proportional to the described voltage across the second energy storage elements.
18. controllers according to claim 11, is characterized in that, described control circuit comprises:
Be connected to the pulse-duration modulation signal generator of described the first energy storage elements, for generation of pulse-width signal, to control the conduction of high side path and low side path, wherein said high side path is connected with described the second energy storage elements via switching node with low side path.
19. controllers according to claim 18, is characterized in that, described control circuit is by described ramp signal and described reference voltage comparison, to control described pulse-width signal.
20. controllers according to claim 11, is characterized in that, described control circuit is constant by controlling the electric current wave amplitude of second energy storage elements of flowing through described in described ramp signal wave amplitude constant control.
21. 1 kinds of current control methods, for controlling the electric current of first energy storage elements of flowing through, is characterized in that, described current control method comprises:
The control electric current that the resistance element of flowing through is provided is the energy in the second energy storage elements with control store;
Regulate described resistance element one terminal voltage;
Based on controlling the voltage of electric current indication across described the first energy storage elements described in the voltage control of described resistance element one end;
Based on the described power generation ramp signal that is stored in the second energy storage elements; And
The electric current of first energy storage elements of flowing through described in controlling based on described ramp signal in preset range,
Wherein, the step of described resistance element one terminal voltage of described adjusting comprises that controlling described resistance element one terminal voltage is tending towards described the first energy storage elements one terminal voltage, wherein,
Described resistance element one terminal voltage and the first reference voltage are compared; And
Described resistance element one terminal voltage and the second reference voltage are compared,
Wherein, described the first reference voltage equals described the first energy storage elements one terminal voltage and adds the first predeterminated voltage, and described the second reference voltage equals described the first energy storage elements one terminal voltage and deducts the second predeterminated voltage.
22. current control methods according to claim 21, is characterized in that, describedly based on controlling the electric current indication step across the voltage of described the first energy storage elements described in the voltage control of described resistance element one end, comprise:
Control described control electric current linearity and be proportional to the described voltage across the first energy storage elements.
23. current control methods according to claim 21, is characterized in that, the step of the described electric current based on first energy storage elements of flowing through described in described ramp signal control in preset range comprises:
Constant by controlling the electric current wave amplitude of first energy storage elements of flowing through described in described ramp signal wave amplitude constant control.
24. 1 kinds of current control methods, for controlling the electric current of first energy storage elements of flowing through, is characterized in that, described current control method comprises:
The control electric current that the resistance element of flowing through is provided is the energy in the second energy storage elements with control store;
Regulate described resistance element one terminal voltage;
Based on controlling the voltage of electric current indication across described the first energy storage elements described in the voltage control of described resistance element one end;
Based on the described power generation ramp signal that is stored in the second energy storage elements; And
The electric current of first energy storage elements of flowing through described in controlling based on described ramp signal in preset range,
Wherein, the step of described resistance element one terminal voltage of described adjusting comprises that controlling described resistance element one terminal voltage is tending towards described the first energy storage elements one terminal voltage, wherein, by described resistance element one terminal voltage and reference voltage comparison, according to the switch of described relatively control connection between described resistance element one end and described first energy storage elements one end, wherein said reference voltage equals described the first energy storage elements one terminal voltage and deducts predeterminated voltage.
25. current control methods according to claim 24, is characterized in that, describedly based on controlling the electric current indication step across the voltage of described the first energy storage elements described in the voltage control of described resistance element one end, comprise:
Control described control electric current linearity and be proportional to the described voltage across the first energy storage elements.
26. current control methods according to claim 24, is characterized in that, the step of the described electric current based on first energy storage elements of flowing through described in described ramp signal control in preset range comprises:
Constant by controlling the electric current wave amplitude of first energy storage elements of flowing through described in described ramp signal wave amplitude constant control.
27. 1 kinds of DC to DC converters, is characterized in that, described DC to DC converter comprises:
For the first energy storage elements of described DC to DC converter output voltage is provided;
Be connected to the pair of switches of described the first energy storage elements; And
Be connected to the controller of described the first energy storage elements and described pair of switches, for control electric current that the resistance element of flowing through is provided with control store the energy in the second energy storage elements, based on the described power generation ramp signal being stored in the second energy storage elements, by regulating described resistance element one terminal voltage to control described control electric current indication across the voltage of described the first energy storage elements, and control described pair of switches to control described output voltage and the electric current of described the first energy storage elements of flowing through based on described ramp signal
Wherein, described controller comprises:
The first comparator, for by described resistance element one terminal voltage and the first reference voltage comparison; And
The second comparator, for by described resistance element one terminal voltage and the second reference voltage comparison,
Wherein, described the first reference voltage equals described the first energy storage elements one terminal voltage and adds the first predeterminated voltage, and described the second reference voltage equals described the first energy storage elements one terminal voltage and deducts the second predeterminated voltage.
28. DC to DC converters according to claim 27, is characterized in that, described the first energy storage elements comprises inductor.
29. DC to DC converters according to claim 27, is characterized in that, described the second energy storage elements comprises capacitor.
30. DC to DC converters according to claim 27, is characterized in that, described resistance element comprises resistor.
31. DC to DC converters according to claim 27, is characterized in that, described controller regulates described resistance element one terminal voltage to be tending towards described the first energy storage elements one terminal voltage.
32. DC to DC converters according to claim 27, is characterized in that, described controller is controlled described control electric current linearity and is proportional to the described voltage across the first energy storage elements.
33. DC to DC converters according to claim 27, is characterized in that, described controller also comprises:
Be connected to the pulse-duration modulation signal generator of described pair of switches, for generation of pulse-width signal to control described pair of switches.
34. DC to DC converters according to claim 33, it is characterized in that, described controller is by described ramp signal and described the first reference voltage and described the second reference voltage comparison, according to described, relatively control described pulse-width signal, thus the wave amplitude of the electric current of first energy storage elements of flowing through described in controlling.
35. DC to DC converters according to claim 33, is characterized in that, described controller also comprises:
The 3rd comparator, for by feedback voltage and the 3rd predeterminated voltage comparison of the described output voltage of indication, relatively controls described pulse-width signal according to described, thereby controls described output voltage.
36. DC to DC converters according to claim 27, is characterized in that, described controller is constant by controlling the electric current wave amplitude of first energy storage elements of flowing through described in described ramp signal wave amplitude constant control.
37. 1 kinds of DC to DC converters, is characterized in that, described DC to DC converter comprises:
For the first energy storage elements of described DC to DC converter output voltage is provided;
Be connected to the pair of switches of described the first energy storage elements; And
Be connected to the controller of described the first energy storage elements and described pair of switches, for control electric current that the resistance element of flowing through is provided with control store the energy in the second energy storage elements, based on the described power generation ramp signal being stored in the second energy storage elements, by regulating described resistance element one terminal voltage to control described control electric current indication across the voltage of described the first energy storage elements, and control described pair of switches to control described output voltage and the electric current of described the first energy storage elements of flowing through based on described ramp signal
Wherein, described controller comprises the first comparator, be used for described resistance element one terminal voltage and reference voltage comparison, according to the switch of described relatively control connection between described resistance element one end and described first energy storage elements one end, wherein said reference voltage equals described the first energy storage elements one terminal voltage and deducts predeterminated voltage.
38. according to the DC to DC converter described in claim 37, it is characterized in that, described the first energy storage elements comprises inductor.
39. according to the DC to DC converter described in claim 37, it is characterized in that, described the second energy storage elements comprises capacitor.
40. according to the DC to DC converter described in claim 37, it is characterized in that, described resistance element comprises resistor.
41. according to the DC to DC converter described in claim 37, it is characterized in that, described controller regulates described resistance element one terminal voltage to be tending towards described the first energy storage elements one terminal voltage.
42. according to the DC to DC converter described in claim 37, it is characterized in that, described controller is controlled described control electric current linearity and is proportional to the described voltage across the first energy storage elements.
43. according to the DC to DC converter described in claim 37, it is characterized in that, described controller also comprises:
Be connected to the pulse-duration modulation signal generator of described pair of switches, for generation of pulse-width signal to control described pair of switches.
44. according to the DC to DC converter described in claim 43, it is characterized in that, described controller is described ramp signal and described reference voltage comparison, to control described pulse-width signal, thus the wave amplitude of the electric current of first energy storage elements of flowing through described in controlling.
45. according to the DC to DC converter described in claim 37, it is characterized in that, described controller is constant by controlling the electric current wave amplitude of first energy storage elements of flowing through described in described ramp signal wave amplitude constant control.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/874,438 US9059632B2 (en) | 2008-03-24 | 2010-09-02 | Controllers for DC to DC converters |
| US12/874,438 | 2010-09-02 |
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| Publication Number | Publication Date |
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| CN102386771A CN102386771A (en) | 2012-03-21 |
| CN102386771B true CN102386771B (en) | 2014-10-01 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI487233B (en) * | 2012-11-09 | 2015-06-01 | Alchip Technologies Ltd | High voltage tolerant input/output circuit |
| CN104079171B (en) * | 2014-07-17 | 2017-01-18 | 电子科技大学 | DC-DC converter with quick response characteristic |
| TWI681613B (en) | 2018-02-02 | 2020-01-01 | 茂達電子股份有限公司 | Voltage converter for simulating inductor current control |
| US10931201B2 (en) | 2019-02-04 | 2021-02-23 | Analog Devices International Unlimited Company | Dead-time supply voltage compensation |
| CN112015093B (en) * | 2019-05-31 | 2022-02-11 | 广东美的制冷设备有限公司 | Drive control method, device, household appliance and computer readable storage medium |
| WO2021196081A1 (en) * | 2020-04-01 | 2021-10-07 | Texas Instruments Incorporated | Constant ripple injection circuit for switching converter |
| TWI777531B (en) * | 2021-04-28 | 2022-09-11 | 力林科技股份有限公司 | Llc converter circuit |
| CN114142861B (en) * | 2022-01-30 | 2022-04-26 | 钰泰半导体股份有限公司 | Integral accumulation storage circuit |
| CN116540823B (en) * | 2023-07-07 | 2023-08-25 | 深圳安森德半导体有限公司 | DCDC voltage stabilizer intelligent control system |
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| US5949226A (en) * | 1995-04-10 | 1999-09-07 | Kabushiki Kaisha Toyoda Jidoshokki Seisakush | DC/DC converter with reduced power consumpton and improved efficiency |
| CN101546957A (en) * | 2008-03-24 | 2009-09-30 | 凹凸电子（武汉）有限公司 | DC to DC converter having controller and control method thereof |
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| US6791306B2 (en) * | 2002-01-29 | 2004-09-14 | Intersil Americas Inc. | Synthetic ripple regulator |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5949226A (en) * | 1995-04-10 | 1999-09-07 | Kabushiki Kaisha Toyoda Jidoshokki Seisakush | DC/DC converter with reduced power consumpton and improved efficiency |
| CN101546957A (en) * | 2008-03-24 | 2009-09-30 | 凹凸电子（武汉）有限公司 | DC to DC converter having controller and control method thereof |
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| CN102386771A (en) | 2012-03-21 |
| TW201223088A (en) | 2012-06-01 |
| TWI431906B (en) | 2014-03-21 |
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