TWI431906B - Dc/dc converter, controller and control method thereof - Google Patents

Description

DC/DC converter and its controller and current control method

The present invention relates to a control circuit, and more particularly to a control circuit having a constant chopping amplitude.

The DC/DC converter can include a controller for generating a pulse width modulation (PWM) signal to drive a switching circuit to control the output voltage of the DC/DC converter. For example, the controller increases the output voltage by increasing the duty cycle of the PWM signal, or reduces the output voltage by reducing the duty cycle of the PWM signal.

Figure 1A shows the controller 150 in a conventional DC/DC converter. Controller 150 includes an oscillator 152, a comparator 154, an operational transconductance amplifier 156, and a capacitor 158. Oscillator 152 provides an oscillating voltage 160 to the non-inverting input of comparator 154. A reference voltage 162 on capacitor 158 is provided to the inverting input of comparator 154. The comparator 154 compares the oscillating voltage 160 with the reference voltage 162 and outputs a PWM signal 168 based on the comparison result. The reference voltage 162 is within a range between the maximum and minimum values of the oscillating voltage 160. If the reference voltage 162 increases and the duty cycle of the PWM signal 168 decreases, then the output voltage of the DC/DC converter will also decrease. If the reference voltage 162 decreases and the duty cycle of the PWM signal 168 will increase, then the output voltage of the DC/DC converter will also increase.

The operational transconductance amplifier 156 receives a predetermined voltage 166 and a feedback voltage 164 indicative of the output voltage of the DC/DC converter, and provides a control current I that is proportional to the difference between the preset voltage 166 and the feedback voltage 164. _COMP . The output of operational transduction amplifier 156 is coupled to capacitor 158 such that control current I _COMP can control reference voltage 162 on capacitor 158. For example, if the feedback voltage 164 is greater than the predetermined voltage 166, the operational transconductance amplifier 156 outputs a control current I _COMP to charge the capacitor 158, thereby increasing the reference voltage 162. The output voltage is therefore reduced. If the feedback voltage 164 is less than the predetermined voltage 166, the operational transconductance amplifier 156 sinks the control current I _COMP from the capacitor 158, thereby reducing the reference voltage 162. The output voltage is thus increased. As a result, the output voltage of the DC/DC converter can be adjusted to the preset voltage 166.

However, in such a conventional controller 150, the power consumption of the oscillator 152 is relatively high. Moreover, since capacitor 158 is bulky, it cannot be integrated into a single wafer with comparator 154 and operational transconductance amplifier 156. Moreover, the bandwidth of the operational transconductance amplifier 156 is too narrow to allow the operational transduction amplifier 156 to respond to delays. Therefore, the controller 150 cannot accurately control the output voltage.

It is an object of the present invention to provide a controller comprising: a ramp signal generator providing a control current flowing through a resistive element to control energy stored in a first energy storage element and based on being stored in the first The energy in the energy storage element generates a ramp signal; and a control circuit coupled to the ramp signal generator to adjust a voltage at one end of the resistive element to control the control current indicative across a second energy storage element a voltage, and controlling a current flowing through the second energy storage element to be within a predetermined range based on the ramp signal.

The present invention also provides a method of controlling current flow through an energy storage element, comprising: providing a control current flowing through a resistive element to control energy stored in a second energy storage element; adjusting one end of the resistive element a voltage; controlling the control current based on the voltage at one end of the resistive element to indicate a voltage across a first energy storage element; generating a ramp signal based on the energy stored in the second energy storage element; The ramp signal controls a current flowing through the first energy storage element within a predetermined range.

The present invention also provides a DC/DC converter comprising: a first energy storage component providing the DC/DC converter output an output voltage; a pair of switches coupled to the first energy storage component; and a controller Connecting to the first energy storage element and the pair of switches, providing a control current flowing through a resistive element to control an energy stored in a second energy storage element based on being stored in the second energy storage element The energy generates a ramp signal, and the voltage of one end of the resistive element is controlled to control the control current to indicate a voltage across the first energy storage element, and the pair of switches are controlled based on the ramp signal to control the output voltage and A current flowing through the first energy storage element.

A detailed description of the embodiments of the present invention will be given below. While the invention will be described in conjunction with the embodiments, it is understood that the invention is not limited to the embodiments. Rather, the invention is to cover various modifications, equivalents, and equivalents of the invention as defined by the scope of the appended claims.

In addition, in the following detailed description of the embodiments of the invention However, it will be understood by those of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail in order to facilitate the invention.

The present invention provides a DC/DC converter (e.g., a buck converter, a boost converter, etc.), and a controller that controls the DC/DC converter. Advantageously, the output current of the DC/DC converter has a constant chopping amplitude such that the output current and output voltage of the DC/DC converter are relatively stable. The controller more accurately controls the output voltage of the DC/DC converter. In addition, the present invention omits higher power consumption oscillators, larger volume capacitors, and narrower operational transconductance amplifiers.

1 is a schematic diagram of a DC/DC converter 100 in accordance with an embodiment of the present invention. The DC/DC converter 100 includes a control circuit 102, a drive circuit 104, a switch circuit 106, and an output circuit 108 (also referred to as an energy storage circuit, a filter circuit). Control circuit 102 generates one or more control signals to drive circuit 104. For example, control circuit 102 generates a PWM signal to control switching circuit 106. Switching circuit 106 includes a pair of switches. In particular, high side switch 110 and low side switch 112 receive control signals from drive circuit 104, respectively, and provide signals to output circuit 108 to produce output voltage _VOUT . The drive circuit 104 controls the high side switch 110 and the low side switch 112 such that the high side switch 110 and the low side switch 112 are each in an on or off state. More specifically, the control circuit 102 provides one or more PWM signals to control the conduction states of the high side switch 110 and the low side switch 112 by changing the duty cycle of the PWM signal.

In one embodiment, if the PWM signal is high, the high side switch 110 is turned "on" and the low side switch 112 is turned "off". This state is called the "switch ON" state or the "TON_BUCK" state. In this state, the inductor 114 in the output circuit 108 is coupled through the high side switch 110 to the input voltage identified as V _IN . The current flowing through the inductor 114 thus increases and stores the charge onto the capacitor 116 in the output circuit 108. In the embodiment of Figure 1, the DC/DC converter 100 is a buck converter. Therefore, the input voltage V _{IN is} greater than the output voltage V _OUT and the voltage across the inductor 114 is positive. The inductor current I _L1 flowing through the inductor 114 is increased and the magnetic field energy is stored into the inductor 114. If the PWM signal is low, the high side switch 110 is off and the low side switch 112 is on. This state is called the "switch OFF" state or the "TOFF_BUCK" state. In this state, the voltage across the inductor 114 is negative. Thus, the inductor 114 releases the magnetic field energy stored therein and provides an output voltage _VOUT to the capacitor 116. Therefore, control circuit 102 provides an output voltage V _OUT based on the duty cycle of the PWM signal it provides. Control circuit 102 also provides a consistent energy signal (eg, a low side switch enable signal, or an LDR_EN signal) to drive circuit 104. In the present embodiment, the LDR_EN signal is provided by 埠 identified as "EN" and controls the state of the high side switch 110 and the low side switch 112.

In the present embodiment, control circuit 102 receives two voltage feedback signals to generate a PWM signal and an LDR_EN signal. Specifically, the 埠 transmission path 120 identified as "VFB" receives the output voltage V _OUT . In addition, the NMOS identified as "LX" on control circuit 102 receives the voltage at one end of inductor 114 through another path 118. The feedback voltage provided by path 118 is used to determine the state of high side switch 110 and low side switch 112. Control circuit 102 includes some components for setting parameters associated therewith. For example, the resistor 128, the resistor 124, and the capacitor 126 are connected to the control circuit 102 for setting parameters such as a reference voltage, a reference current, a reference voltage swing rate, and the like.

2 shows an exemplary table 200 of switch states in accordance with an embodiment of the present invention. Table 200 describes the states of high side switch 110 and low side switch 112 corresponding to the LDR_EN signal and the PWM signal potential value. Further, the conduction of the high side switch 110 and the low side switch 112 determines a state. For example, if the high side switch 110 is on and the low side switch 112 is off (eg, LDR_EN = 1 and PWM = 1), this state is determined to be a "TON_BUCK" state or a "switch ON" state. In the TON_BUCK state, the inductor 114 is coupled to the input voltage V _IN . If the high side switch 110 is off and the low side switch 112 is on (eg, LDR_EN = 1 and PWM = 0), this state is determined to be a "TOFF_BUCK" state or a "switch OFF" state. In the TOFF_BUCK state, the inductor 114 is connected to ground potential. If both the high side switch 110 and the low side switch 112 are off (eg, LDR_EN = 0 and PWM = 0), this state is determined to be the "SKIP" state. In the SKIP state, since both the high side switch 110 and the low side switch 112 are off, the inductor 114 is in a floating state (eg, neither a voltage source nor a ground is connected). Therefore, the inductor 114 is connected to the input voltage V _IN in the TON_BUCK state, connected to the ground potential in the TOFF_BUCK state, and suspended in the SKIP state.

In the TON_BUCK state, the voltage across the inductor 114 is approximately equal to V _IN -V _OUT . For a buck converter, the input voltage V _{IN is} greater than the output voltage V _OUT and the net voltage across the inductor 114 is positive. Therefore, the inductor current I _L1 flowing through the inductor 114 is increased according to the following equation: dI _L1 /dt=(V _IN -V _OUT )=ΔI _L1 /T _ON (1)

V _IN in equation (1) represents the input voltage of the DC/DC converter 100, V _OUT represents the output voltage of the DC/DC converter 100, and T _ON represents the time when the high side switch 110 and the low side switch 112 are in the TON_BUCK state, L represents the inductance value of the inductor 114, and ΔI _L1 represents the amount of change of the inductor current I _L1 during the TON_BUCK state.

In the TOFF_BUCK state, the voltage across the inductor 114 is equal to the output voltage V _OUT . However, the voltage across the inductor 114 is in opposite polarity, and the inductor current I _{L1 is} reduced according to the following equation: dI _L1 /dt=-(V _OUT )/L=ΔI _L1 /T _OFF (2)

T _OFF in the equation (2) indicates the time when the high-side switch 110 and the low-side switch 112 are in the TOFF_BUCK state, and ΔI _L1 represents the amount of change in the inductor current I _L1 during the TOFF_BUCK state.

3 is a schematic diagram of a DC/DC converter 100A in accordance with an embodiment of the present invention. The DC/DC converter 100A is an illustration of the DC/DC converter 100 of FIG. The same elements are identified in Figures 1 and 3 to have similar functions. The DC/DC converter 100A includes a control circuit 102A. Control circuit 102A can be used in a wide variety of DC/DC converters 100A. By way of example, DC/DC converter 100A is a synchronous buck converter that includes control circuit 102A, drive circuit 104, switch circuit 106 including high side switch 110 and low side switch 112, and output circuit 108. Output circuit 108 includes an inductor 114 and a capacitor 116. The high side switch 110 is connected between the input voltage V _IN and the switching node 122. The low side switch 112 is connected between the switching node 122 and ground. Switching node 122 is also coupled to output circuit 108.

Control circuit 102A includes a pulse width modulation circuit 352 that generates a PWM signal and an LDR_EN signal. In response to the PWM signal and the LDR_EN signal, the drive circuit 104 controls the states of the high side switch 110 and the low side switch 112.

Control circuit 102A receives an input signal indicative of the voltage at switching node 122. Control circuit 102A also includes a target input 埠SLEW for setting the expected output voltage V _SET . By way of example, in the embodiment of FIG. 1, charging of capacitor 126 is accomplished based on the resistance of resistor 124 and resistor 128 in the resistor divider and the value of reference voltage REF. A variety of methods are known to those skilled in the art to charge capacitor 126 to produce a target voltage signal. Further, the VFB of the control circuit 102A receives a feedback signal indicating the output voltage V _OUT of the DC/DC converter 100A.

The control circuit 102A shown in FIG. 3 includes a resistor 320 coupled to the switching node 122 of the DC/DC converter 100A. The current flowing through resistor 320 is responsive to the state of high side switch 110 and low side switch 112 (eg, TON_BUCK state, TOFF_BUCK state, or SKIP state). Control circuit 102A also includes a ramp generation circuit 350 that generates ramp signal 312 in response to current flowing through resistor 320. Pulse width modulation circuit 352 generates a PWM signal in response to at least ramp signal 312.

In the TON_BUCK state, for example, when the high-side switch 110 is turned on and the low-side switch 112 is turned off, since the high-side switch 110 is turned on, the switching node 122 is connected to the input voltage V _IN , so the voltage on the switching node 122 is equal to the input voltage V _IN . Thus, the current flowing through the resistor 320 is equal to the input voltage V _{IN of the} DC/DC converter 100A minus the output voltage V _{OUT of the} DC/DC converter 100A, divided by the resistance of the resistor 320. In response to the current flowing through resistor 320, ramp generation circuit 350 generates a portion (eg, a rising portion) of ramp signal 312, which will be described in detail in FIG.

In the TOFF_BUCK state, for example, when the high side switch 110 is off and the low side switch 112 is on, since the switching node 122 is grounded via the low side switch 112, the voltage on the switching node 122 is equal to zero. Thus, the current flowing through resistor 320 is equal to zero minus the output voltage V _{OUT of} DC/DC converter 100A divided by the resistance of resistor 320. In response to the current flowing through resistor 320, ramp generation circuit 350 produces another portion (e.g., a falling portion) of ramp signal 312, which will be described in detail in FIG.

In the SKIP state, when both the high side switch 110 and the low side switch 112 are off, the voltage on the switching node 122 is equal to the output voltage V _{OUT of the} DC/DC converter 100A. Since the voltage on the switching node 122 minus the output voltage _VOUT divided by the resistance of the resistor 320 is equal to zero, the current flowing through the resistor 320 is equal to zero in the SKIP state. In response to this current flowing through resistor 320, ramp generation circuit 350 produces another portion of ramp signal 312 (e.g., tends to a constant portion), which will be described in detail in FIG.

The ramp generation circuit 350 includes a buffer 351 and a current control current source 324. The reverse input of buffer 351 is coupled to the output of buffer 351 to provide negative feedback. The non-inverting input of the buffer 351 receives an output voltage indicative of the DC/DC converter 100A (eg, an expected output voltage V _SET or an output voltage V _OUT ). The output voltage of the buffer 351 thus varies closely following the expected output voltage V _SET or the output voltage V _OUT . The current controlled current source 324 is responsive to the current I_in flowing through the resistor 320, which varies depending on the state of the high side switch 110 and the low side switch 112. Current controlled current source 324 provides current I_out that is mirrored by current I_in. In an embodiment, the current control current source 324 includes a current mirror, but is not limited thereto. Current I_out charges and discharges ramp capacitor 308 to provide ramp signal 312 to first comparator 301 and second comparator 302 in pulse width modulation circuit 352.

The first comparator 301 compares the ramp signal 312 with the nominal voltage V2. In one embodiment, the nominal voltage V2 is 20 millivolts. The first comparator 301 provides a signal RAW_LDR_EN to the inverse gate 311, which also receives the SKIP signal and provides an LDR_EN signal to the driver circuit 104. The second comparator 302 compares the ramp signal 312 with the reference voltage REF and provides an output signal to the reset terminal "R" of the flip flop 342. The non-inverting output "Q" of the flip-flop 342 provides a PWM signal to the driver circuit 104.

The duty cycle of the PWM signal is inversely proportional to the difference between the input voltage V _IN and the output voltage V _OUT (or the expected output voltage V _SET ). In other words, as the difference increases, the duty cycle of the PWM signal decreases to shorten the TON_BUCK time of the high side switch 110 and the low side switch 112. Conversely, as the difference decreases, the duty cycle of the PWM signal increases to further shorten the TOFF_BUCK time of the high side switch 110 and the low side switch 112. In one embodiment, the difference between the TON_BUCK time (eg, time T _ON ) of the high side switch 110 and the low side switch 112 and the input voltage V _IN and the output voltage V _OUT (eg, V _IN -V _OUT ) or It is inversely proportional to the difference between the input voltage V _IN and the expected output voltage V _SET (eg, V _IN -V _SET ). Therefore, the amount of current change ΔI _L1 in each TON_BUCK state period is constant. Further, the high-side switch and the low side switch 110 TOFF_BUCK time (e.g., time T _OFF) 112 and the output voltage V _OUT or inversely proportional to the expected output voltage V _SET. Therefore, the amount of current change ΔI _L1 in each TOFF_BUCK state period is constant. In one embodiment, the current change amount per cycle [Delta] TON_BUCK state equal to _L1 and the current change amount per cycle state TOFF_BUCK ΔI _L1. In other words, the control circuit 102A is a constant chopping-current (CRC) controller that causes the control inductor current I _{L1 to} have a constant chopping.

FIG. 4 shows an exemplary timing diagram 400 in accordance with an embodiment of the present invention. Some of the operations of control circuit 102A of FIG. 3, including the generation of ramp signal 312, will be described below in conjunction with FIGS. 1, 3, and 4. When the control circuit 102A is activated, the SLEW voltage on the target input 埠SLEW shown in FIGS. 1 and 3 starts to increase. At this point, the feedback voltage VFB indicating the output voltage V _OUT is zero. The second comparator 302 of FIG. 3 senses that the SLEW voltage is greater than the feedback voltage VFB and provides a high potential to the gate 322. At this point, the output of the first comparator 301 (eg, signal RAW_LDR_EN) is also high. Then, the input of the AND gate 322 is high, and the gate 322 outputs a high potential to set the flip-flop 342. At this moment, the PWM signal is high. The high side switch 110 is turned on, and then the output voltage V _OUT and the feedback voltage VFB start to increase. In the present embodiment, when the SLEW voltage is increased to a predetermined value (for example, the expected output voltage V _SET ), the SLEW voltage remains unchanged.

During the time t1 to t2, the PWM signal in FIG. 403 is at a high potential, and the LDR_EN signal in the waveform 404 is at a high potential. The high side switch 110 and the low side switch 112 are then in the TON_BUCK state, ie the high side switch 110 is turned on and the low side switch 112 is turned off. Since the switching node 122 is connected to the input voltage V _{IN of the} DC/DC converter 100A, the switching node 122 voltage LX is equal to the input voltage V _IN during the time t1 to t2 shown in the waveform 405.

During the time t1 to t2, the current I_in flowing through the resistor 320 is given by the following equation:

I_in=(V _IN -V _OUT )/R ₁ (3)

Here, V _IN represents the input voltage of the DC/DC converter 100A, V _OUT represents the output voltage of the DC/DC converter 100A, and R1 represents the resistance of the resistor 320. If K=1/R1, then equation (3) can be rewritten as:

I_in=K*(V _IN -V _OUT ) (4)

Since the current I_out mirrors the current I_in, the current I_out is equal to the current I_in and can be given by equation (3) and equation (4). During the time t1 to t2, the ramp signal 312 in waveform 407 increases at a rate proportional to the current I_out. The ramp signal 312 is incremented until equal to the reference voltage REF input to the inverting input of the second comparator 302. When the ramp signal 312 is incremented to the reference voltage REF at time t2, the output of the second comparator 302 resets the flip flop 342.

When the flip-flop 342 is reset at time t2, the Q (non-inverting output) of the flip-flop 342 is at a low potential, and thus the PWM signal in the waveform 403 is at a low potential. The signal RAW_LDR_EN (e.g., waveform 402) from the first comparator 301 is low, such that the output of the inverse gate 311 (e.g., the LDR_EN signal of waveform 404) is high. Therefore, the high side switch 110 and the low side switch 112 are in the TOFF_BUCK state during the time t2 to t3, that is, the high side switch 110 is turned off, and the low side switch 112 is turned on. When the high side switch 110 and the low side switch 112 are in the TOFF_BUCK state, since the switching node 122 is grounded via the low side switch 112, the switching node 122 voltage LX shown by the waveform 405 is equal to zero.

During the time t2 to t3, the current I_in in the waveform 406 is given by the following equation:

I_in=(0-V _OUT )/R ₁ (5)

If the constant K is 1/R ₁ , then equation (5) can be rewritten as:

I_in=-K*V _OUT (6)

Since the current I_out mirrors the current I_in, the current I_out is equal to the current I_in and can be given by equations (5) and (6). During the time t2 to t3, the ramp signal 312 in waveform 407 decreases at a speed proportional to the current I_out. The ramp signal 312 is reduced until it is equal to the nominal voltage V2 input to the non-inverting input of the first comparator 301. When ramp signal 312 decreases to nominal voltage V2 at time t3, the output of first comparator 301 (eg, signal RAW_LDR_EN) goes high. When ramp signal 312 decreases to nominal voltage V2 at time t3, inductor current I _L1 shown by waveform 408 is in a zero crossing state. Therefore, the control circuit 102A does not directly measure the inductor current I _L1 , but provides a zero-cross estimator to estimate the inductor current I _L1 .

If the SKIP signal is also high at time t3 (eg, to initiate the SKIP state), then the output of the inverse gate 311 (eg, the LDR_EN signal in waveform 404) is low. Therefore, during the time t3 to t4, the control circuit 102A is in the SKIP state. In response to the low potential PWM signal shown by waveform 403 and the low potential LDR_EN signal shown by waveform 404, both high side switch 110 and low side switch 112 are off and in the SKIP state. In one embodiment, the SKIP state occurs when the feedback signal VFB is greater than the SLEW voltage when the ramp signal 312 is reduced to the nominal voltage V2. However, if the feedback voltage VFB is less than or equal to the SLEW voltage when the ramp signal 312 is reduced to the nominal voltage V2, the gate 322 sets the flip-flop 342 to output a high-potential PWM signal. In other words, if the feedback voltage VFB is less than or equal to the SLEW voltage when the ramp signal 312 is reduced to the nominal voltage V2, the SKIP state will not occur.

Therefore, in the SKIP state (when both the high side switch 110 and the low side switch 112 are off), the switching node 122 voltage LX shown by the waveform 405 is equal to the output voltage V _{OUT of the} DC/DC converter 100A. Furthermore, as shown by waveform 406, in the SKIP state, current I_in flowing through resistor 320 and current I_out are equal to zero due to the voltage of switching node 122 minus the output voltage _VOUT divided by the resistance of resistor 320 equal to zero.

After the start of the SKIP state, the control circuit 102A keeps the high side switch 110 and the low side switch 112 in the SKIP state until the output voltage V _OUT of the DC/DC converter 100A indicated by the feedback voltage VFB drops to a preset voltage value (eg, SLEW) Voltage).

During the period from t1 to t2, the high side switch 110 is turned on, the low side switch 112 is turned off, the feedback voltage VFB is increased, and the slope is positive. During the time t2 to t3, the high side switch 110 is turned off, the low side switch 112 is turned on, and the feedback voltage VFB is decreased until it is equal to the SLEW voltage at time t4. The high side switch 110 and the low side switch 112 are both turned off between time t3 and time t4. The feedback voltage VFB is reduced at this time faster than the speed reduced during the time t2 to t3. At time t4, the output of the third comparator 303 is at a high potential. The high potential from the third comparator 303 and the first comparator 301 causes the AND gate 322 to output a high potential, thereby setting the flip-flop 342, and the PWM signal in the waveform 403 is turned to a high potential. The above process will be repeated during the time t4 to t6. The rate of decrease of the feedback voltage VFB in the waveform 401 during the time t3 to t4 depends on the load current. For example, the rate of decrease of the feedback voltage VFB at the case of a small load current is lower than that at the case of a large load current. Therefore, the control circuit 102A in the case of a small load current maintains the SKIP state for a longer period of time than in the case of a larger load current.

Returning to FIG. 3, during the time t2 to t3 or during the time t5 to t6, the switch 372 can be turned on to affect the slope of the ramp signal 312, thereby shortening the TOFF_BUCK time. The output of the AND gate 323 controls the switch 372, and turns on the switch 372 when the input of the AND gate 323 is high. This occurs when the feedback voltage VFB is less than the SLEW voltage such that the output of the third comparator 303 is high and the QB (inverting output) of the flip-flop 342 is high. In other words, if the feedback voltage VFB is reduced to the SLEW voltage before the ramp signal 312 is reduced to the nominal voltage V2, the switch 372 is turned "on". Compared with the case where the switch 372 is turned off, the TOFF_BUCK state time when the switch 372 is turned on is shortened. This is because the slope of the negative value of the ramp signal 312 in the TOFF_BUCK state (eg, during the time t2 to t3) is further reduced when the switch 372 is turned on, as compared with the case where the switch 372 is turned off. More specifically, during the TOFF_BUCK state, if the switch 372 is turned on, an additional current will flow through the resistor 373 to ground, and the current I_in flowing from the output of the buffer 351 is increased. Therefore, the discharge current I_out increases, and the time taken for the ramp signal 312 to decrease from the reference voltage REF to the nominal voltage V2 is shortened. In other words, the time of the TOFF_BUCK state is shortened. The ratio at which the TOFF_BUCK state is accelerated can be determined by selecting the resistor 373. If such an accelerated TOFF_BUCK state does not meet the requirements, control circuit 102A may not include switch 372, resistor 373, and AND gate 323.

According to the embodiment of Figure 3, during the TON_BUCK state, the following equation is obtained:

dV ₃₁₂ /dt=I_out/C1=ΔV ₃₁₂ /T _ON (7a)

Wherein, V ₃₁₂ represents the voltage potential of the ramp signal 312, C1 represents the capacitance value of the ramp capacitor 308, and ΔV ₃₁₂ represents the amount of change of the voltage V ₃₁₂ during the TON_BUCK state. Since the current I_in is equal to the current I_out, rewriting equation (7a) yields:

I_in/C1=ΔV ₃₁₂ /T _ON (7b)

According to equations (1), (4), and (7b), the following program can be obtained:

ΔI _L1 =(ΔV ₃₁₂ *C1)/(K*L) (8)

During each TON_BUCK state, the amount of voltage change ΔV ₃₁₂ in equation (8) may be a constant value (eg, equal to the reference voltage REF minus the nominal voltage V2). Therefore, ΔI _L1 can also be a constant value.

Similarly, during the TOFF_BUCK state, the following equation is obtained:

dV ₃₁₂ /dt=I_out/C1=ΔV ₃₁₂ /T _OFF (9a)

ΔV ₃₁₂ in equation (9a) represents the amount of change in voltage V ₃₁₂ during the TOFF_BUCK state. Rewriting equation (9a) yields:

I_in/C1=ΔV ₃₁₂ /T _OFF (9b)

According to equations (2), (6), and (9b), the following program can be obtained:

ΔI _L1 = (ΔV ₃₁₂ *C1) / (K*L) (10)

During each TOFF_BUCK state, the amount of voltage change ΔV ₃₁₂ in equation (10) may be a constant value (eg, equal to the nominal voltage V2 minus the reference voltage REF). Therefore, the current change amount ΔI _L1 can also be a constant value. Since the voltage change amount ΔV ₃₁₂ during each TON_BUCK state and the voltage change amount ΔV ₃₁₂ during each TOFF_BUCK state are equal in magnitude, the current change amount ΔI _L1 during each TON_BUCK state and the current change during each TOFF_BUCK state The quantity ΔI _L1 is equal in magnitude. In other words, control circuit 102A is a CRC controller that controls inductor current I _{L1 to} have a constant chopping amplitude.

In the present embodiment, by using the third comparator 303, the gate 322, the gate 323, the flip-flop 342, the switch 372, and the resistor 373, the control circuit 102A adjusts the average voltage V _{AVE of the} output voltage V _OUT to the target input.预期 The expected output voltage V _SET on SLEW. Specifically, during the TOFF_BUCK state, when the ramp signal 312 is reduced to the nominal voltage V2, if the feedback voltage VFB is greater than the SLEW voltage, then the average voltage V _{AVE is} greater than the expected output voltage V _SET . In this case, the third comparator 303 outputs a low potential, and the AND gate 322 and the flip-flop 342 keep the PWM signal low until the feedback voltage VFB decreases to the SLEW voltage. Therefore, the time of the TOFF_BUCK state is increased, thereby reducing the duty cycle of the PWM signal. The average voltage V _{AVE is} thus reduced. If the feedback voltage VFB is reduced to the SLEW voltage before the ramp signal 312 is reduced to the nominal voltage V2, then the average voltage V _{AVE is} less than the expected output voltage V _SET . In this case, the third comparator 303 outputs a high potential to the gate 323 to turn on the switch 372. The time in the TOFF_BUCK state is shortened, which in turn increases the duty cycle of the PWM signal. The average voltage V _{AVE is} thus increased. As a result, the average voltage V _AVE is adjusted to the expected output voltage V _SET .

FIG. 5 is a schematic diagram of a DC/DC converter 100B in accordance with an embodiment of the present invention. The DC/DC converter 100B is an illustration of the DC/DC converter 100 of FIG. The same elements are identified in Figures 1, 3 and 5 to have similar functions. The DC/DC converter 100B includes a control circuit 102B. Control circuit 102B includes a resistor 520 that is coupled to DC/DC converter 100B switching node 122. Control circuit 102B includes ramp generation circuit 550 that provides ramp signal 512 in response to current flowing through resistor 520. Control circuit 102B also includes pulse width modulation circuit 552 that generates a PWM signal to respond at least to ramp signal 512.

The ramp generation circuit 550 includes a ramp capacitor 508 that is coupled in series with the resistor 520 via a path 509. Operational amplifier 551 has an inverting input coupled to node 506 and a non-inverting phase for receiving a feedback voltage indicative of a DC/DC converter 100B output voltage (eg, expected output voltage V _SET or output voltage V _OUT ) Input. The operational amplifier 551 is used as an integrator. If the non-inverting input receives the output voltage V _OUT , the voltage at one end of resistor 520 (node 506) is equal to the output voltage V _OUT . Current flowing through resistor 520 also flows through ramp capacitor 508, charging or discharging ramp capacitor 508, thereby controlling ramp signal 512.

The ramp signal 512 is provided to the non-inverting input of the first comparator 501 and the inverting input of the second comparator 502. The nominal voltage V2 is provided to the inverting input of the first comparator 501. The reference voltage REF is provided to the non-inverting input of the second comparator 502. In one embodiment, the reference voltage REF is equal to 0.01 volts and the nominal voltage V2 is equal to 2.5 volts.

FIG. 6 shows an exemplary timing waveform 600 in accordance with an embodiment of the present invention. Some of the operations of control circuit 102B of FIG. 6 including the generation of ramp signal 512 will be described below in conjunction with FIG. During the time t1 to t2, the PWM signal in waveform 601 is at a high potential, and the LDR_EN signal in waveform 602 is also at a high potential. Therefore, the high side switch 110 is turned on and the low side switch 112 is turned off. During the time t1 to t2, since the switching node 122 is connected to the input voltage V _IN of the DC/DC converter 100B, the switching node 122 voltage LX shown by the waveform 603 is equal to the input voltage V _IN . During the time t1 to t2, the current I_in (or I(C1)) flowing through the resistor 520 in the waveform 604 and flowing through the ramp capacitor 508 is given by equations (3) and (4). In response to the current flowing through the ramp capacitor 508, the ramp signal 512 of the waveform 605 decreases during the time t1 to t2. During the time t1 to t2, since the current I_in in the waveform 604 flows through the ramp capacitor 508 via the operational amplifier 551, the slope of the ramp signal 512 is a negative value. The ramp signal 512 is thus inverted from the ramp signal 312 in FIG. Moreover, the polarity arrangement of the ramp capacitance 508 providing the ramp signal 512 is opposite to the polarity arrangement of the ramp capacitance 308 providing the ramp signal 312 shown in FIG.

The ramp signal 512 is reduced until equal to the reference voltage REF input to the non-inverting input of the second comparator 502. When the ramp signal 512 is reduced to the reference voltage REF at time t2, the output of the second comparator 502 resets the flip flop 542. When the flip-flop 542 is at the time t2, the Q (non-inverting output) of the flip-flop 542 is at a low potential, and the PWM signal in the waveform 601 is thus at a low potential. As shown by the waveform 606, the signal RAW_LDR_EN outputted by the first comparator 501 is low during the time t2 to t3, so the output of the opposite gate 511 (for example, the LDR_EN signal in the waveform 602) is high. Therefore, the high side switch 110 and the low side switch 112 are in the TOFF_BUCK state during the time t2 to t3 (the high side switch 110 is turned off, and the low side switch 112 is turned on). When the high side switch 110 and the low side switch 112 are in the TOFF_BUCK state, since the switching node 122 is grounded via the low side switch 112, the switching node 122 voltage LX shown by the waveform 603 is equal to zero.

During the time t2 to t3, the current I_in (or I(C1)) flowing through the resistor 520 in the waveform 604 and flowing through the ramp capacitor 508 is given by equations (5) and (6). Then, the ramp signal 512 is increased at a rate proportional to the currents I_in and I(C1) until it is equal to the nominal voltage V2 at time t3. At time t3, the output of the first comparator 501 (eg, the signal RAW_LDR_EN of the waveform 606) is turned to a high potential. If the SKIP signal is also high at time t3 (eg, the SKIP state is enabled), the output of the inverse gate 511 (eg, the LDR_EN signal in waveform 602) is low. At time t3, if the feedback voltage VFB is greater than SLEW, the AND gate 522 receives the low potential from the third comparator 503 and outputs a low potential to the flip-flop 542 to keep the PWM signal low. Therefore, during the time t3 to t4, the control circuit 102B is in the SKIP state. In response to the low potential PWM signal in waveform 601 and the low potential LDR_EN signal in waveform 602, both high side switch 110 and low side switch 112 are off. However, if the feedback voltage VFB is less than or equal to the SLEW voltage when the ramp signal 512 is increased to the nominal voltage V2, the SKIP state does not occur but directly enters the TON_BUCK state.

Therefore, in the SKIP state (when both the high side switch 110 and the low side switch 112 are off), the switching node 122 voltage LX shown by the waveform 603 is equal to the output voltage V _{OUT of the} DC/DC converter 100B. In addition, the current flowing through resistor 520 and ramp capacitor 508 is zero in the SKIP state. The control circuit 102B keeps the high side switch 110 and the low side switch 112 in the SKIP state until the output voltage V _OUT of the DC/DC converter 100B indicated by the feedback voltage VFB in the waveform 607 drops to a preset voltage value (eg, SLEW voltage) ). When this happens at time t4, the output of the third comparator 503 of Fig. 5 turns to a high potential. The high potential from the third comparator 503 and the first comparator 501 causes the AND gate 522 of FIG. 5 to output a high potential, and the flip-flop 542 is set, thereby causing the PWM signal in the waveform 601 to go high. The above process will be repeated during the time t4 to t6.

Control circuit 102B is a CRC controller that controls inductor current I _{L1 to} have a constant chopping amplitude. Specifically, in the TON_BUCK state, the following equation is obtained:

I_in=C1*(dV ₅₀₈ /dt)=C1*(-dV ₅₁₂ /dt)=C1/(−ΔV ₅₁₂ /T _ON ) (11)

V ₅₀₈ in equation (11) represents the voltage across the ramp capacitor 508, V ₅₁₂ represents the voltage potential of the ramp signal 512, C1 represents the capacitance value of the ramp capacitor 508, and ΔV ₅₁₂ represents the amount of change of the voltage potential V ₅₁₂ during the TON_BUCK state. . Based on equations (1), (4), and (11), the following equation is obtained:

ΔI _L1 =-(ΔV ₅₁₂ *C1)/(K*L) (12)

ΔI _L1 in equation (12) represents the amount of change in inductor current I _L1 during the TON_BUCK state. Similarly, in the TOFF_BUCK state, the following equation is obtained:

I_in=C1*(dV ₅₀₈ /dt)=C1*(-dV ₅₁₂ /dt)=C1/(−ΔV ₅₁₂ /T _OFF ) (13)

ΔV ₅₁₂ in equation (13) represents the amount of change in voltage potential V ₅₁₂ during the TOFF_BUCK state. Based on equations (2), (6), and (13), the following equation is obtained:

ΔI _L1 =-(ΔV ₅₁₂ *C1)/(K*L) (14)

ΔI _L1 in the equation (14) represents the amount of change of the inductor current I _L1 during the TOFF_BUCK state. Since the amount of change ΔV ₅₁₂ during each TON_BUCK state and the amount of change ΔV ₅₁₂ during each TOFF_BUCK state are equal, the amount of current change ΔI _L1 during each TON_BUCK state and the current during each TOFF_BUCK state The quantity ΔI _L1 is equal in magnitude.

Further, similar to the control circuit 102A in FIG. 3, in FIG. 5, when the average voltage V _{AVE of the} output voltage V _OUT is smaller than the expected output voltage V _SET at the SLEW terminal, the control circuit 102B increases the duty cycle of the PWM signal. When the average voltage V _{AVE is} greater than the expected output voltage V _SET at the SLEW terminal, the control circuit 102B reduces the duty cycle of the PWM signal. As a result, the control circuit 102B adjusts the average voltage V _{AVE of the} output voltage V _OUT to the expected output voltage V _SET .

FIG. 7 is a schematic diagram of a DC/DC converter 100C in accordance with an embodiment of the present invention. The DC/DC converter 100C in the embodiment of Fig. 7 is a boost converter. The DC/DC converter 100C includes a control circuit 102C, a drive circuit 704, and a high side switch 110 and a low side switch 112 connected to the inductor 714. Control circuit 102C is operative to generate a control signal to drive circuit 704 to drive high side switch 110 and low side switch 112. The control circuit 102C regulates the duty cycle of the DC/DC converter 100C to control the high side switch 110 and the low side switch 112, thereby controlling the inductor current I _L7 flowing through the inductor 714 and the output voltage V _{OUT of the} DC/DC converter 100C. The control circuit 102C controls the states of the high side switch 110 and the low side switch 112 by means of the PWM signal by changing the duty cycle of the PWM signal.

In one embodiment, if the PWM signal is high, the low side switch 112 is turned on and the high side switch 110 is turned off. This state of the high side switch 110 and the low side switch 112 is referred to as a "switch ON" state or a "TON_BOOST" state. The inductor 714 in this state is grounded through the switching node 122. Therefore, the inductor current I _L7 flows from the input terminal (such as the input voltage V _IN in FIG. 7) through the inductor 714 to the ground and increases. If the PWM signal is low and the HDR_EN signal is high, the low side switch 112 is turned off and the high side switch 110 is turned on. This state of the high side switch 110 and the low side switch 112 is referred to as a "switch OFF" state or a "TOFF_BOOST" state. In the DC/DC converter 100C (boost converter), the net voltage across the inductor 714 in this state is negative. Then, the inductor current I _L7 is reduced in the TOFF_BOOST state. Therefore, the duty cycle of the PWM signal determines the time T _ON of the TON_BOOST state and the time T _{OFF of the} TOFF_BOOST state. Similar to the buck converter, control circuit 102C utilizes ramp signal 712 to assist in generating the PWM signal.

Control circuit 102C includes pulse width modulation circuit 752 and ramp generation circuit 750. The pulse width modulation circuit 752 includes a first comparator 701, a second comparator 702, a third comparator 703, and a gate 722, an inverse gate 723, and a latch 742. The first comparator 701 provides an input to the gate 722 and the inverse gate 723. Gate 722 receives the output of third comparator 703 and then produces an input to latch 742. Latch 742 provides input to driver circuit 704 and AND gate 725 at the periphery of pulse width modulation circuit 752. Pulse width modulation circuit 752 receives ramp signal 712 from ramp generation circuit 750 and generates a PWM signal in response to ramp signal 712. The ramp generation circuit 750 includes an operational amplifier 751 and a ramp capacitor 708 and responds to current flowing through the resistor 720 and the resistor 771 as described below.

The control circuit 102C further includes a switch 713 and a AND gate 725, and the inputs of the gate 725 are coupled to the output of the third comparator 703 and the inverted output terminal QB of the latch 742, respectively, in the pulse width modulation circuit 752. Control circuit 102C also includes a resistor 720 and a resistor 771 in series with switching node 122 of DC/DC converter 100C.

The resistor 720 in series with the resistor 771 can be regarded as an equivalent resistor having a resistance value R equal to R1 + R2. In one embodiment, R1 may be equal to R/6 and R2 is equal to 5*R/6. The ramp generation circuit 750 also includes a ramp capacitor 708 in series with a resistor 720 and a resistor 771. The inverting input of operational amplifier 751 is coupled to node 706 associated with series connected resistor 720 and resistor 771, and the non-inverting input of operational amplifier 751 receives a feedback signal indicative of input voltage V _IN of DC/DC converter 100C. The operational amplifier 751 is used as an integrator. Current flowing through resistor 720 and resistor 771 also flows through ramp capacitor 708 to charge or discharge ramp capacitor 708, thereby controlling ramp signal 712.

The ramp signal 712 is provided to the inverting input of the first comparator 701 and the non-inverting input of the second comparator 702. The nominal voltage V2 is provided to the non-inverting input of the first comparator 701. The reference voltage REF is supplied to the inverting input of the second comparator 702. In one embodiment, the reference voltage REF is equal to 2.5 volts and the nominal voltage V2 is equal to 0.01 volts.

In the TOFF_BOOST state, the PWMB signal is high, if the output voltage V _{OUT is} less than the VSLEW voltage, and the gate 725 outputs a high potential. Thus, the switch 713 is turned on to reduce the resistance value R. The ramp signal 712 is rapidly reduced to the nominal voltage V2 such that the output of the first comparator 701 goes high, which in turn sets the latch 742. The PWMB signal goes low and turns off the switch 713.

FIG. 8 illustrates an exemplary timing waveform 800 depicting the operation of the control circuit 102C of FIG. 7 in accordance with an embodiment of the present invention. In the present embodiment, during the time t1 to t2, the PWM signal in the waveform 801 and the HDR_EN signal in the waveform 802 are at a high potential. Therefore, the low side switch 112 is turned on and the high side switch 110 is turned off. During the time t1 to t2, the switching node 122 voltage LX in the waveform 803 is zero. As shown by waveform 804, during the time t1 to t2, the current I(C) flowing through resistor 720, resistor 771, and ramp capacitor 708 is given by the following equation:

I(C)=-V _IN /R=-V _IN *K (15)

In response to current I(C) flowing through ramp capacitor 708, ramp signal 712 in waveform 805 increases during the time t1 to t2. During the time t1 to t2, since the current I(C) in the waveform 804 flows through the ramp capacitor 708 via the operational amplifier 751, for example, from the output of the operational amplifier 751 to the ramp capacitor 708, the slope of the ramp signal 712 is positive.

Once latch 742 is reset at time t2, the Q (in-phase output) of latch 742 goes low, so the PWM signal in waveform 801 is low. When the high side switch 110 and the low side switch 112 are in the TOFF_BOOST state, the switching node 122 voltage LX in the waveform 803 is equal to the output voltage V _OUT . This is because the switching node 122 is connected to the output voltage V _OUT via the high side switch 110.

During the time t2 to t3, the current I(C) flowing through the resistor 720 and the resistor 771 in the waveform 804 is given by the following equation:

I(C)=(V _OUT -V _IN )/R=(V _OUT -V _IN )*K (16)

During the time t2 to t3, the ramp signal 712 decreases at a speed proportional to the current I(C). The ramp signal 712 is reduced until it is equal to the nominal voltage V2 input to the non-inverting input of the first comparator 701. When ramp signal 712 decreases to nominal voltage V2 at time t3, the output of first comparator 701 is high. Similar to the ramp signal 512 and the inductor current I _L1 in FIG. 5, when the ramp signal 712 in FIG. 7 is reduced to the nominal voltage V2 at time t3, the inductor current I _L7 is in a zero-crossing state. Therefore, the control circuit 102C does not directly measure the inductor current I _L7 , but provides a zero-cross estimator to estimate the inductor current I _L7 .

Control circuit 102C is a CRC controller that controls inductor current I _{L7 to} have a constant chopping amplitude. Specifically, in the TON_BOOST state, the following equation is obtained:

dI _L7 /dt=V _IN /L=ΔI _L7 /T _ON (17)

ΔI _L7 in equation (17) represents the amount of change in inductor current I _L7 during the TON_BOOST state. In addition, the following equation can be obtained:

I(C)=C*(dV ₇₀₈ /dt)=C*(-dV ₇₁₂ /dt)=C*(-ΔV ₇₁₂ /T _ON )(18)

V ₇₀₈ in equation (18) represents the voltage across ramp capacitor 708, V ₇₁₂ represents the voltage of ramp signal 712, C represents the capacitance of ramp capacitor 708, and ΔV ₇₁₂ represents the amount of change of V ₇₁₂ during the TON_BOOST state. Based on equations (15), (17), and (18), the following equation is obtained:

ΔI _L7 = (ΔV ₇₁₂ *C) / (K*L) (19)

Similarly, in the TOFF_BOOST state, the following equation is obtained:

dI _L7 /dt=(V _IN -V _OUT )/L=ΔI _L7 /T _OFF (20)

ΔI _L7 in equation (20) represents the amount of change in inductor current I _L7 during the TOFF_BOOST state. In addition, the following equation is obtained:

I(C)=C*(dV ₇₀₈ /dt)=C*(-dV ₇₁₂ /dt)=C*(-ΔV ₇₁₂ /T _OFF )(21)

ΔV ₇₁₂ in equation (21) represents the amount of change of V ₇₁₂ during the TOFF_BOOST state. Based on equations (16), (20), and (21), the following equation is obtained:

ΔI _L7 = (ΔV ₇₁₂ *C) / (K*L) (22)

Since the period is equal to ΔV ΔV during each TON_BOOST state ₇₁₂ and state ₇₁₂ of each TOFF_BOOST its magnitude, so that the current amount of change during each TON_BOOST state and the current change amount [Delta] I _L7 each TOFF_BOOST state during which the magnitude of [Delta] I _L7 equal.

Further, similar to the control circuit 102A in FIG. 3 and the control circuit 102B in FIG. 5, the control circuit 102C in FIG. 7 when the average voltage V _{AVE of the} output voltage V _OUT is smaller than the expected output voltage V _SET at the target input terminal SLEW Increase the duty cycle of the PWM signal. The control circuit 102C reduces the duty cycle of the PWM signal when the average voltage V _{AVE of the} output voltage V _OUT is greater than the expected output voltage V _SET at the target input terminal SLEW. As a result, the control circuit 102C adjusts the average voltage V _{AVE of the} output voltage V _OUT to the expected output voltage V _SET .

Specifically, in the TOFF_BOOST state, if the output voltage V _OUT is still greater than the VSLEW voltage when the ramp signal 712 is decreased to the nominal voltage V2, the third comparator 703 outputs a low potential, passing through the AND gate 722 and the latch 742. Keep the PWM signal low until the output voltage V _OUT decreases to the VSLEW voltage. Thus, the time of the TOFF_BOOST state is increased, thereby reducing the duty cycle of the PWM signal. If the output voltage V _OUT decreases to the VSLEW voltage before the ramp signal 712 decreases to the nominal voltage V2, the third comparator 703 outputs a high potential to turn on the switch 713 via the AND gate 725, thereby reducing the node 706 and the switching node 122. The resistance value of the path. The current I(C) flowing through the ramp capacitor 708 increases, which in turn shortens the TOFF_BOOST state. The duty cycle of the PWM signal is then increased. As a result, the average voltage V _{AVE of the} output voltage V _OUT is adjusted to the VSLEW voltage.

9 is a flow chart 900 of an exemplary method of current control in accordance with an embodiment of the present invention. Step 902 generates a ramp signal in response to current flowing through the resistance of the switching node coupled to the DC/DC converter. The switching node is connected to the high side switch and the low side switch of the DC/DC converter. Step 904 includes generating a PWM signal in response to the ramp signal.

The present invention provides a DC/DC converter (eg, a buck converter, a boost converter) for converting an input voltage V _IN to an output voltage V _OUT . By way of example, Figures 3 and 5 provide a step-down DC/DC converter 100A and a DC/DC converter 100B, and Figure 7 provides a step-up DC/DC converter 100C. The DC/DC converter includes a CRC controller (eg, control circuit 102A, control circuit 102B, or control circuit 102C) for generating a ramp signal to control the output current of the DC/DC converter (eg, inductor current I _L1 or inductor) Current I _L7 ). The ramp capacitance (eg, ramp capacitor 308, ramp capacitor 508, or ramp capacitor 708) may be charged or discharged using a control current (eg, current I_out or current I(C)) to generate a ramp signal such that the ramp signal is proportional to Controls the speed of the current. In addition, the inductor current (eg, inductor current I _L1 or inductor current I _L7 ) varies in proportion to the speed across the voltage across the inductor (eg, inductor 114 or inductor 714). Since the control current is proportional to the voltage across the inductor, see equations (4), (6), (15), and (16), the ramp signal is proportional to the inductor current. Therefore, it is advantageous to constantly control the chopping of the inductor current through the chopping of the control ramp signal. In addition, the narrower operational transconductance amplifier 156 of FIG. 1A is omitted, allowing the CRC controller to more accurately control the output of the DC/DC converter. Secondly, a capacitor 158 having a higher capacitance value and a larger volume is also omitted. All of the elements in CRC control circuit 102A, control circuit 102B, or control circuit 102C can be integrated into a single wafer. In addition, the oscillator in the traditional controller is also eliminated, thereby reducing power consumption.

A method for adjusting the control current proportional to the voltage across the inductor includes controlling the voltage across the across resistor (eg, resistor 320, resistor 520, or resistor 720-771) to be equal to or proportional to the voltage across the inductor. For example, the resistor has a first end and a second end, and the inductor has a first end and a second end. The first end of the resistor is coupled to the first end of the inductor at the same node (eg, switching node 122). The second terminal voltage of the resistor is controlled to be approximately equal to the second terminal voltage of the inductor. In the embodiments of FIGS. 3, 5, and 7, the DC/DC converter 100A, the DC/DC converter 100B, and the DC/DC converter 100C include a buffer 351, an operational amplifier 551, and an operational amplifier 751, respectively. The operational amplifier transfers the second terminal voltage of the inductor to the second terminal of the resistor. However, various methods or means can be used to control the second terminal voltage of the resistor to be approximately equal to the second terminal voltage of the inductor.

FIG. 10A is a schematic diagram of a DC/DC converter 1000 in accordance with an embodiment of the present invention. In the embodiment of FIG. 10A, DC/DC converter 1000 is a boost converter for converting input voltage V _IN on low side terminal 1088 to output voltage V _OUT on high side terminal 1086. As shown in FIG. 10A, the DC/DC converter 1000 includes a controller 1002, a driver 1004, a switching circuit including a high side switch 1010 and a low side switch 1012, and an energy storage element (eg, an inductor 1014).

In the embodiment of FIG. 10A, the high side path between inductor 1014 and high side end 1086 includes high side switch 1010, while the low side path between inductor 1014 and ground includes low side switch 1012. However, in an alternate embodiment, the high side switch 1010 is replaced by a diode. The energy storage component can be the inductor 1014, but is not limited thereto. The inductor 1014 includes a first end 1013 coupled to the switching node 1022 between the high side switch 1010 and the low side switch 1012, and a second end 1015 coupled to the low side end 1088. Inductor 1014 is used to provide an output voltage V _{OUT of} DC/DC converter 1000.

The controller 1002 includes an enable output EN for providing a high side switch enable signal (HDR_EN) 1082, and a control output PWM for providing a PWM signal 1084. The controller 1002 further includes an input terminal LX for receiving a voltage on the first terminal 1013 of the inductor 1014, an input terminal VFB1 for receiving the feedback voltage on the second terminal 1015 of the inductor 1014, and an input terminal VFB2 for receiving the high side. The output voltage V _OUT on terminal 1086. The controller 1002 also includes an input SRIP for receiving an SRIP signal that controls whether the enable signal 1082 is valid. In addition, the controller 1002 further includes an output terminal VREF and an input terminal SLEW. In an embodiment, the input terminal SLEW sets an expected or target value of the output voltage V _OUT . In the embodiment of FIG. 10A, the capacitor 1026 connected to the input terminal SLEW is charged based on the resistance ratio of the resistor divider (such as the resistor 1024 and the resistor 1028 shown in the figure) and the voltage of the output terminal VREF, thereby providing a preset. The voltage V _{PRE is} given to the input SLEW. However, the invention is not limited in this regard; other alternative methods can be used to charge capacitor 1026 to generate a predetermined voltage V _PRE to input SLEW.

In one embodiment, when the high side switch 1010 is turned off and the low side switch 1012 is turned on, the first end 1013 of the inductor 1014 is grounded via the low side switch 1012 and the net voltage across the inductor 1014 is positive (eg, equal to V _IN ). The inductor current I _L10 flowing through the inductor 1014 increases in proportion to the voltage across the voltage across the inductor 1014 (eg, equal to V _IN ). Get the following equation:

dIL ₁₀ /dt=V _I N/L (23)

Where L represents the inductance value of the inductor 1014. When the high side switch 1010 is turned on and the low side switch 1012 is turned off, the first end 1013 of the inductor 1014 is coupled to the high side terminal 1086 via the high side switch 1010 and the net voltage across the inductor 1014 is negative (eg, equal to V _IN -V _OUT ). The inductor current I _L10 decreases in proportion to the voltage across the inductor 1014 (eg, equal to V _IN -V _OUT ). Get the following equation:

dI _L10 /dt=(V _IN -V _OUT )/L (24)

In this embodiment, the inductor current I _L10 is a chopping current. When the high side switch 1010 is turned on and the low side switch 1012 is turned off, the inductor current I _L10 flows into the high side terminal 1086. An energy storage unit (eg, output capacitor 1016) coupled between the high side terminal 1086 and ground is charged by the inductor current I _L10 and provides an output voltage V _OUT . By alternately turning on and off the high side switch 1010 and the low side switch 1012, the controller 1002 adjusts the output voltage V _OUT or the average voltage V _{AVE of the} output voltage V _OUT to the target voltage V _TARGET . Further, the controller 1002 controls the inductor current I _{L10 to} have a chopping amplitude that tends to be constant. Therefore, the output voltage V _{OUT of the} DC/DC converter 1000 is more stable.

The controller 1002 generates control signals such as an enable signal (HDR_EN) 1082 and a PWM signal 1084 to the driver 1004 to control/drive the high side switch 1010 and the low side switch 1012. For example, the high side switch 1010 can be turned on by a high potential signal and turned off by a low potential signal. Similarly, the low side switch 1012 can be turned on by the high potential signal and turned off by the low potential signal. The state of the high side switch 1010 and the low side switch 1012 can be controlled by the logic potentials of the control enable signal (HDR_EN) 1082 and the PWM signal 1084.

Figure 11 shows a state change table for the high side switch 1010 and the low side switch 1012 in response to the enable signal (HDR_EN) 1082 and the PWM signal 1084. Table 1100 will be described below in conjunction with FIG. 10A.

As shown in table 1100, when enable signal (HDR_EN) 1082 and PWM signal 1084 are high (ie, HDR_EN = 1 and PWM = 1), high side switch 1010 is off and low side switch 1012 is on. This state is called the TON_BOOST state. When the enable signal (HDR_EN) 1082 is low and the PWM signal 1084 is high (ie, HDR_EN = 0 and PWM = 1), the high side switch 1010 is turned off and the low side switch 1012 is turned on. Therefore, the high side switch 1010 and the low side switch 1012 are still in the TON_BOOST state. In the TON_BOOST state, the first terminal 1013 of the inductor 1014 is grounded, the voltage across the inductor 1014 is equal to V _IN , and the inductor current I _{L10 is} increased. When the enable signal (HDR_EN) 1082 is high and the PWM signal 1084 is low (ie, HDR_EN = 1 and PWM = 0), the high side switch 1010 is turned on and the low side switch 1012 is turned off. This state is called the TOFF_BOOST state. In the TOFF_BOOST state, the first terminal 1013 of the inductor 1014 is coupled to the high side terminal 1086, the voltage across the inductor 1014 is equal to V _IN -V _oUT , and the inductor current I _{L10 is} decreased. When the enable signal (HDR_EN) 1082 and the PWM signal 1084 are low (ie, HDR_EN = 0 and PWM = 0), the high side switch 1010 and the low side switch 1012 are turned off. This state is called the SKIP state. In the SKIP state, the first end 1013 of the inductor 1014 is floating (eg, no high side terminal 1086 is also connected to ground) and the voltage across the inductor 1014 is zero. The inductor current I _L10 is also zero.

Figure 10B is a schematic diagram of a DC/DC converter 1000' in accordance with another embodiment of the present invention. Elements identified the same in Figures 10A and 10B have similar functions. As illustrated in FIG. 10B, the controller 1002 includes a ramp signal generator 1030, a PWM signal generator 1040, and a feedback circuit 1070. The ramp signal generator 1030 includes an energy storage unit (eg, a ramp capacitor 1008) and a resistive element (eg, resistor 1020). Ramp capacitor 1008 is coupled between ground and PWM signal generator 1040. The first end 1023 of the resistor 1020 is coupled to the first end 1013 of the inductor 1014, and the second end 1025 of the resistor 1020 is coupled to the ramp capacitor 1008 via a circuit 1018.

Ramp signal generator 1030 provides control current I _C10 flowing through resistor 1020 to control the electrical energy stored in ramp capacitor 1008. The ramp signal generator 1030 also generates a ramp signal 1032 (eg, a voltage across the ramp capacitor 1008) based on the electrical energy stored in the ramp capacitor 1008. The control circuit includes a PWM signal generator 1040 and a circuit 1018 that regulates the control current I _C10 by adjusting the voltage at one end of the resistor 1020 to indicate (eg, linearly proportional to) the voltage across the inductor 1014. The control circuit also controls the inductor current I _L10 flowing through the inductor 1014 based on the ramp signal 1032 to be controlled within a predetermined range.

More specifically, in the present embodiment, the voltage V ₁₀₂₃ of the first terminal 1023 of the resistor 1020 is equal to the voltage V ₁₀₁₃ of the first terminal 1013 of the inductor 1014. The circuit 1018 controls the voltage V ₁₀₂₅ of the second terminal 1025 of the resistor 1020 to be equal to the voltage V ₁₀₁₅ of the second terminal 1015 of the inductor 1014. Thus, the voltage across resistor 1020 is approximately equal to the voltage across across inductor 1014. Thus, the control current I _C10 flowing through the resistor 1020 is linearly proportional to the voltage across the inductor 1014, V ₁₀₁₃ - V ₁₀₁₅ , and is given by: I _C10 = (V ₁₀₁₃ - V ₁₀₁₅ ) / R _RP . R _RP represents the resistance of the resistor 1020. The circuit 1018 can be disposed within the PWM signal generator 1040 or the ramp signal generator 1030, or within the integrated circuit of the PWM signal generator 1040 and the ramp signal generator 1030, or in the PWM signal generator 1040 and the ramp signal generator 1030. The outside.

Control current I _C10 controls the electrical energy stored in ramp capacitor 1008 to adjust ramp signal 1032 (eg, across voltage across ramp capacitor 1008). For example, in the TON_BOOST state, the control current I _C10 is given by the following equation:

I _C10 =(V ₁₀₁₃ -V ₁₀₁₅ )/R _RP =(0-V _IN )/R _RP (25)

Therefore, the following equation can be obtained:

I _C10 =C _RP *dV _RP /dt=-V _IN /R _RP (26)

Where C _RP represents the capacitance value of the ramp capacitor 1008 and V _RP represents the voltage of the ramp signal 1032. Thus, in the TON_BOOST state, control current I _C10 discharges ramp capacitor 1008 to reduce ramp signal 1032. Similarly, in the TOFF_BOOST state, the control current I _C10 is given by the following equation:

I _C10 = (V ₁₀₁₃ - V ₁₀₁₅ ) / R _RP = (V _OUT - V _IN ) / R _RP (27)

Therefore, the following equation can be obtained:

I _C10 =C _RP *dV _RP /dt=(V _OUT -V _IN )/R _RP (28)

Thus, in the TOFF_BOOST state, control current I _C10 charges ramp capacitor 1008 to increase ramp signal 1032.

Based on equations (23) and (26), the following equation is obtained:

ΔI _L10 /T _ON =V _IN /L (29a)

C _RP *ΔV _RP /T _ON =-V _IN /R _RP (29b)

ΔI _L10 in the equations (29a) and (29b) represents the amount of change of the inductor current I _L10 during the TON_BOOST state, ΔV _RP represents the amount of change of the voltage V _RP during the TON_BOOST state, and T _ON represents the time of the TON_BOOST state. Based on equations (29a) and (29b), the following equation is obtained:

ΔI _L10 =-C _RP *ΔV _RP *R _RP /L (30)

Similarly, based on equations (24) and (28), the following equation can be obtained:

ΔI _L10 /T _OFF =(V _IN -V _OUT )/L (31a)

C _RP *ΔV _RP /T _OFF =(V _OUT -V _IN )/R _RP (31b)

ΔI _L10 in the equations (31a) and (31b) represents the amount of change of the inductor current I _L10 during the TOFF_BOOST state, ΔV _RP represents the amount of change of the voltage V _RP during the TOFF_BOOST state, and T _OFF represents the time of the TOFF_BOOST state. Based on equations (31a) and (31b), the following equation is obtained:

ΔI _L10 =-C _RP *ΔV _RP *R _RP /L (32)

The PWM signal generator 1040 controls the high side switch 1010 and the low side switch 1012 based on the ramp signal 1032 to control the inductor current I _L10 flowing through the inductor 1014. In particular, PWM signal generator 1040 generates PWM signal 1084 to control high side switch 1010 and low side switch 1012. The PWM signal generator 1040 also controls the state of the PWM signal 1084 such that the ramp signal 1032 has a chopping amplitude that tends to be constant. Based on equations (30) and (32), the controller 1002 tends to constant by controlling the amount of change ΔI _{L10 of the} inductor current I _L10 by the voltage change amount ΔV _{RP of the} control ramp signal 1032. Therefore, the controller 1002 is a CRC controller.

Further, the PWM signal generator 1040 controls the high side switch 1010 and the low side switch 1012 based on the ramp signal 1032 to thereby control the output voltage V _{OUT of the} DC/DC converter 1000'. Specifically, the feedback circuit 1070 receives the output voltage V _OUT via the input terminal VFB2 and generates a feedback signal (eg, feedback voltage V _FB ) indicative of the output voltage V _OUT to the PWM signal generator 1040. The PWM signal generator 1040 also controls the duty cycle of the PWM signal 1084 based on the feedback voltage V _FB . Illustration, the PWM signal generator 1040 when the output voltage V _OUT of the average voltage V _AVE is less than the target voltage V _TARGET, increasing the duty cycle of the PWM signal 1084, 1084 of the PWM signal is reduced when the average voltage V _AVE is larger than the target voltage V _TARGET Cycle of responsibility. The average voltage V _{AVE of the} output voltage V _OUT is thus adjusted to the target voltage V _TARGET .

Figure 12 is a schematic diagram of a DC/DC converter 1000A in accordance with an embodiment of the present invention. The same elements are identified in Figures 10A, 10B and 12 to have similar functions. As shown in FIG. 12, the controller 1002A includes a ramp signal generator 1030A, a PWM signal generator 1040A, and a feedback circuit 1070.

The ramp signal generator 1030A includes a resistor 1020, a ramp capacitor 1008, a switch 1232, and a switch 1234. The first end 1023 of the resistor 1020 is coupled to the first end 1013 of the inductor 1014, and the second end 1025 of the resistor 1020 is coupled to the ramp capacitor 1008 via the switch 1234. The resistor 1020 in the embodiment shown in FIG. 12 includes a secondary resistor 1220 and a secondary resistor 1221 connected in series with each other. The switch 1232 is connected to both ends of the secondary resistor 1221. The resistance R _{RP of the} resistor 1020 is equal to the resistance R _{RP0 of the} secondary resistor 1220 plus the resistance R _{RP1 of the} secondary resistor 1221.

The PWM signal generator 1040A includes a comparator 1201, a comparator 1202, an offset circuit 1242, an offset circuit 1252, an SR flip-flop 1248, an SR flip-flop 1258, and a gate 1262, a gate 1264, and a comparator 1203. As shown in FIG. 12, the inverting input of comparator 1201 and the non-inverting input of comparator 1202 are coupled to ramp capacitor 1008 and to second terminal 1025 of resistor 1020 via switch 1234. The non-inverting input of comparator 1201 is coupled to second end 1015 of inductor 1014 via offset circuit 1242. The inverting input of comparator 1202 is coupled to second end 1015 of inductor 1014 via offset circuit 1252. The comparator 1203 includes an inverting input coupled to the feedback circuit 1070, including a non-inverting input coupled to a voltage source (not shown in FIG. 12) for providing a predetermined voltage V _PRE , and including an output terminal and Gate 1262 is connected to gate 1264. The reset terminal R of the SR flip-flop 1248 is connected to the output terminal of the comparator 1201, the set terminal S and the output of the gate 1262 are connected, the non-inverting output terminal Q is connected to the control output terminal of the controller 1002A, and the inverting output terminal QB is connected. And the gate 1264 input is connected. The reset terminal R of the SR flip-flop 1258 is connected to the non-inverting output terminal Q of the SR flip-flop 1248, the output terminal S is connected to the output terminal of the comparator 1202, the non-inverting output terminal Q is connected to the input terminal of the gate 1262, and the inverting output terminal QB is connected. Connected to the enable output EN of the controller 1002A. The input terminal of the AND gate 1262 is connected to the non-inverting output terminal Q of the SR flip-flop 1258 and the output terminal of the comparator 1203, and the output terminal is connected to the set terminal S of the SR flip-flop 1248. The input terminal of the gate 1264 is connected to the inverting output terminal QB of the SR flip-flop 1248 and the output terminal of the comparator 1203, and the output terminal is connected to the control terminal of the switch 1232. Further, the inverting output terminal QB of the SR flip-flop 1258 is connected to the control terminal of the switch 1234.

In the present embodiment, the comparator 1201 receives a reference voltage V _L from the offset circuit 1242, and outputs a signal to the SR flip-flop 1248 through 1032 compare the ramp signal and the reference voltage V _L. When the ramp signal at the comparator 1201 1032 V _L is not greater than the reference voltage output high potential signal, the ramp signal 1032 is greater than the reference voltage V _L when the low potential signal. The comparator 1202 receives the reference voltage V _H (V _H > V _L ) from the offset circuit 1252 and outputs a signal to the SR flip-flop 1258 through the comparison ramp signal 1032 and the reference voltage V _H . Comparator 1202 outputs a high level signal in the ramp signal 1032 is not less than the reference voltage V _H when the potential of the low output signal of the ramp signal is less than 1032 when the reference voltage V _H.

In this embodiment, the SR flip-flop 1248 can be triggered by a rising edge of an input signal (eg, a set bit signal or a reset signal). For example, if the rising edge of the set bit signal appears on the set terminal S of the SR flip-flop 1248, the non-inverting output terminal Q of the SR flip-flop 1248 is set to a high potential and the inverted output terminal QB is set to a low potential. If the rising edge of the reset signal occurs on the reset terminal R of the SR flip-flop 1248, the non-inverting output terminal Q of the SR flip-flop 1248 is set to a low potential and the inverted output terminal QB is set to a high potential. If both the set terminal S and the reset terminal R are low, the logic potentials of the non-inverting output terminal Q and the inverting output terminal QB of the SR flip-flop 1248 remain unchanged until the rising edge of the input signal of the SR flip-flop 1248.

The controller 1002A controls the chopping amplitude of the ramp signal 1032 and the chopping amplitude of the inductor current I _L10 to become constant by comparing the ramp signal 1032 with the reference voltage V _L and the ramp signal 1032 and the reference voltage V _H . More specifically, the PWM signal generator 1040A controls the PWM signal 1084 duty cycle based on the comparison of the ramp signal 1032 and the reference voltage V _L and the ramp signal 1032 and the reference voltage V _H . When the ramp signal 1032 is reduced to the reference voltage V _L, the comparator 1201 outputs a high voltage to SR flip-flop 1248 is reset, it outputs a low voltage PWM signal 1084. The ramp signal 1032 then increases. When the ramp signal 1032 is incremented to the reference voltage _VH , the comparator 1202 outputs a high potential signal, and the PWM signal 1084 is asserted high via the SR flip-flop 1258, the AND gate 1262, and the SR flip-flop 1248. The ramp signal 1032 is then reduced. Then, the ramp signal 1032 has a maximum value equal to the reference voltage V _H and a minimum value equal to the reference voltage V _L . Therefore, the inductor current I _L10 also has a maximum value and a minimum value (for example, the inductor current I _L10 is within a preset range based on the ramp signal 1032). The chopping amplitude of the ramp signal 1032 is equal to the difference between the reference voltage V _L and the reference voltage V _H . The difference V _H - V _L is constant such that the chopping amplitude of the ramp signal 1032 is constant. As a result, the amplitude of the chopping of the inductor current I _L10 is also constant.

In the embodiment of FIG. 12, the circuit for controlling the voltage V ₁₀₂₅ of the second terminal 1025 of the resistor 1020 to the voltage V ₁₀₁₅ of the second terminal 1015 of the inductor 1014 includes a comparator 1201, a comparator 1202, and an offset circuit. 1242, and an offset circuit 1252. Specifically, the comparator 1201 compares the voltage V ₁₀₂₅ with the reference voltage V _L , and thus the control voltage V _{1025 is} not less than the reference voltage V _L . The comparator 1202 compares the voltage V ₁₀₂₅ with the reference voltage V _H , and thus the control voltage V _{1025 is} not greater than the reference voltage V _H . The preset voltage across the offset circuit 1242 is V _S1 , and the preset voltage across the offset circuit 1252 is V _S2 . Then, the reference voltage V _L supplied to the comparator 1201 is equal to the voltage V ₁₀₁₅ minus the preset voltage V _S1 (eg, V _L =V ₁₀₁₅ -V _S1 ), and the reference voltage V _H supplied to the comparator 1202 is equal to the voltage V ₁₀₁₅ Add the preset voltage V _S2 (for example: V _H = V ₁₀₁₅ + V _S2 ). In one embodiment, the predetermined voltage V _S1 across the shift circuits 1242 and 1252 across the offset circuit voltage V _S2 of predetermined substantially constant. In an embodiment, the preset voltage V _S1 and the preset voltage V _S2 may be equal (eg, V _S1 =V _S2 ) such that the voltage V _{1015 is} intermediate between the reference voltage V _L and the reference voltage V _H . In addition, the preset voltage V _S1 and the preset voltage V _{S2 are} relatively small and can be omitted compared to the voltage V ₁₀₁₅ such that the reference voltage V _L (eg, V _L =V ₁₀₁₅ -V _S1 ) to the reference voltage V The voltage V ₁₀₂₅ that varies within the range of _H (eg, V _H = V ₁₀₁₅ + V _S2 ) is considered to be approximately equal to the voltage V ₁ 0 ₁ 5 .

In the embodiment shown in FIG. 12, offset circuit 1242 includes a resistor 1246 having a resistance of R _S1 . The offset circuit 1242 also includes a current source 1244 that provides a predetermined current I _S1 flowing through the resistor 1246 such that the resistor 1246 has a predetermined voltage V _S1 (eg, V _S1 =I _S1 *R _S1 ). Similarly, the offset circuit 1252 includes a resistor 1256 having a resistance value of R _S2 . The offset circuit 1252 also includes a current source 1254 that provides a predetermined current I _S2 flowing through the resistor 1256 such that the resistor 1256 has a predetermined voltage V _S2 (eg, V _S2 =I _S2 *R _S2 ). However, the present invention is not limited thereto; other alternative methods can also be used to generate a preset voltage across the offset circuit 1242 and the offset circuit 1252.

In the embodiment of FIG. 12, comparator 1201 and comparator 1202 control ramp signal 1032 to have a constant chopping amplitude, and control voltage _V1025 tends to voltage _V1015 . However, in another embodiment, ramp signal 1032 and voltage V _{1025 are} controlled by different comparators. For example, one or more comparator control ramp signals 1032 have a constant chopping amplitude. The other one or more comparator control voltages V ₁₀₂₅ tend to voltage V ₁₀₁₅ . In such an implementation, the range of ramp signal 1032 and the range of voltage V ₁₀₂₅ may be the same or different. In such an implementation, a current controlled current source (eg, current controlled current source 324 in FIG. 3) can be utilized to generate a control current equal to the current flowing through resistor 1020 to control ramp capacitance 1008.

The feedback circuit 1070 includes a resistor divider (eg, resistor 1272 and resistor 1274 shown) coupled between the high side terminal 1086 and ground. The output voltage V _OUT and the resistance of the resistor 1272 and the resistor 1274 determine the feedback voltage V _FB . However, the invention is not limited thereto; other alternative methods can also be used to generate a feedback signal indicative of the output voltage _VOUT .

As shown in FIG. 12, the comparator 1203 outputs a signal 1260 to the gate 1262 and the gate 1264 by comparing the feedback voltage V _FB with the preset voltage V _PRE . Signal 1260 is referred to as a "PULSE" signal. Gate 1264 outputs a signal 1236 to control switch 1232 coupled to secondary resistor 1221. Signal 1236 is referred to as an "acceleration" signal or an "ACCEL" signal. Switch 1232 may also be referred to as an "acceleration" switch. Additionally, switch 1234 coupled between resistor 1020 and ramp capacitor 1008 may also be referred to as a "delay" switch. By using the comparator 1205, the gate 1262, the gate 1264, the switch 1232, the switch 1234, the SR flip-flop 1248, and the SR flip-flop 1258, the average voltage V _{AVE of the} output voltage V _OUT is adjusted to the target voltage V _TARGET . More specifically, on the one hand, if the average voltage V _{AVE is} less than the target voltage V _TARGET , the comparator 1203 outputs a high potential signal 1260 (PULSE), and the signal 1236 (ACCEL) is set to a high potential via the AND gate 1264. Therefore, the switch 1232 is turned on to increase the duty cycle of the PWM signal 1084 and thereby increase the average voltage V _AVE . On the other hand, if the average voltage V _{AVE is} greater than the target voltage V _TARGET , the comparator 1203 outputs a low potential signal 1260 (PULSE). The low potential signal 1260 (PULSE) maintains the PWM signal 1084 at a low potential via the AND gate 1262 and the SR flip-flop 1248, and keeps the switch 1234 off, causing the duty cycle of the PWM signal 1084 to decrease and thereby reducing the average voltage V _AVE . The adjustment process with respect to the average voltage V _AVE of the output voltage V _OUT will be described below with reference to FIG.

13 is a diagram showing signals associated with the DC/DC converter 1000A of FIG. 12 (eg, inductor current I _L10 , output voltage V _OUT , ramp signal 1032, PULSE signal 1260, HDR_EN signal 1082, ACCEL, in accordance with an embodiment of the present invention). An exemplary timing diagram 1300 of signal 1236, and PWM signal 1084). In the embodiment of FIG. 13, the operations of controller 1002A include different modes, such as: duty cycle reduction mode, duty cycle normal mode, and duty cycle increase mode. For example, the output voltage V _OUT in FIG. 13 fluctuates up and down with a preset potential V' _TARGET as a reference potential. In the duty cycle normal mode (eg, during the time t _j to t _j+4 ), when the ramp signal 1032 is increased to the reference voltage V _H (eg, at time t _j+2 ), the output voltage V _{OUT is} reduced to Set the potential V' _TARGET . The average voltage V _{AVE of the} output voltage V _OUT is equal to the target voltage V _TARGET . In this embodiment, the target voltage V _{TARGET is} approximately equal to the preset potential V' _TARGET . In the duty cycle reduction mode (eg, during the time t _i to t _i+4 ), when the ramp signal 1032 is increased to the reference voltage V _H (eg, at time t _i+2 ), the output voltage V _{OUT is} greater than the preset Potential V' _TARGET . The average voltage V _{AVE is} greater than the target voltage V _TARGET . Then, the controller 1002A reduces the duty cycle of the PWM signal 1084 to reduce the average voltage V _AVE . In the duty cycle increase mode (eg, during the time t _k to t _k+3 ), the output voltage V _{OUT is} reduced to a preset potential V' _TARGET before the ramp signal 1032 is increased to the reference voltage V _H (eg, at t _{k +2} moments). The average voltage V _{AVE is} less than the target voltage V _TARGET . Then, the controller 1002A increases the duty cycle of the PWM signal 1084 to increase the average voltage V _AVE .

In the embodiment shown in FIG. 13, in the duty cycle normal mode (eg, during the time t _j to t _j+4 ), the ACCEL signal 1236 is low and the HDR_EN signal 1082 is high. The PULSE signal 1260 is in phase with the PWM signal 1084. For example, PULSE signal 1260 is high when PWM signal 1084 is high and low when PWM signal 1084 is low. The ramp signal 1032 and the inductor current I _L10 have a sawtooth waveform. Since the chopping amplitude of the ramp signal 1032 is constant, the chopping amplitude of the inductor current I _L10 is constant. The output voltage V _OUT fluctuates up and down with a preset potential V' _TARGET as a reference potential, but the average voltage V _{AVE of the} output voltage V _OUT is equal to the target voltage V _TARGET .

More specifically, in the TON_BOOST state of the duty cycle normal mode (eg, during the time t _j to t _j+1 ), the inductor current I _{L10 is} increased according to equation (23), and the ramp signal 1032 is decreased according to equation (26). In addition, the output voltage V _{OUT is} reduced. In response to the rising edge of PWM signal 1084 (eg, at time t _j ), SR flip-flop 1258 asserts HDR_EN signal 1082 to a high potential. During the TON_BOOST state, since the ramp signal 1032 is less than the reference voltage _VH , the comparator 1202 outputs a low potential signal to the SR flip-flop 1258, and the HDR_EN signal 1082 remains high. A switch 1234 connected between the resistor 1020 and the ramp capacitor 1008 is turned on. In addition, the inverting output terminal QB of the SR flip-flop 1248 is at a low potential such that the ACCEL signal 1236 is at a low potential to turn off the acceleration switch 1232. When the ramp signal 1032 is reduced to the reference voltage V _L (e.g.: t _{j + 1} at a time), the comparator 1201 outputs a high level signal to reset the SR flip-flop 1248, so that the low potential of the PWM signal 1084. At time t _j+1 , the HDR_EN signal 1082 is still high. Therefore, the DC/DC converter 1000A enters the TOFF_BOOST state.

In the TOFF_BOOST state of the duty cycle normal mode (eg, during the time t _j+1 to t _j+2 ), the inductor current I _L10 decreases according to equation (24), and the ramp signal 1032 increases according to equation (28). In addition, the output voltage V _{OUT is} reduced. The output capacitor 1016 has an equivalent series resistance value, so that when the high side switch 1010 is turned on and the low side switch 1012 is turned off (eg, at time t _j+1 ), the output voltage V _OUT can be relatively quickly increased to equal one input. The voltage V _{IN is} added to the potential across the voltage across the inductor 1014. At time t _j+1 , the output voltage V _{OUT is} greater than the preset potential V' _TARGET (eg, the feedback voltage V _{FB is} greater than the preset voltage V _PRE ). Therefore, the AND gate 1264 receives the low potential PULSE signal 1260 from the comparator 1203 and outputs a low potential ACCEL signal 1236 to keep the switch 1232 off. Additionally, HDR_EN signal 1082 is high and keep switch 1234 conductive.

In the duty cycle normal mode, when the ramp signal 1032 is increased to the reference voltage V _H (eg, at time t _j+2 ), the output voltage V _{OUT is} decreased to a preset potential V′ _TARGET . The comparator 1202 outputs a high potential signal to the SR flip-flop 1258 to set the non-inverting output terminal Q of the SR flip-flop 1258 to a high potential. Next, comparator 1203 outputs a high potential PULSE signal 1260. Thus, the AND gate 1262 outputs a high potential signal to the SR flip-flop 1248 to set the PWM signal 1084 to a high potential. In one embodiment, when the set terminal S of the SR flip-flop 1258 receives the high potential signal from the comparator 1202 and when the reset terminal R of the SR flip-flop 1258 receives the high potential PWM signal 1084, There is a time interval ΔT _{1 between} . The time interval ΔT ₁ is relatively short. In other words, the HDR_EN signal 1082 is at a low potential within the time interval ΔT ₁ (as indicated by t _j , t _j+2 , t _j+4 in the figure), and the duration of this state is relatively short. The time interval ΔT ₁ is negligible compared to the time T _ON and the time T _OFF . In one embodiment, the AND gate 1264 receives the high potential signal from the inverted output QB of the SR flip-flop 1248 and the high potential PULSE signal 1260 from the comparator 1203 during the time interval ΔT ₂ . The time interval ΔT ₂ is relatively short. In other words, the ACCEL signal 1236 is at a high potential during the time interval ΔT ₂ (e.g., at times t _j , t _j+2 , t _j+4 in the figure), and the duration of this state is relatively short. The time interval ΔT ₂ is negligible compared to the time T _ON and the time T _OFF .

In the duty cycle reduction mode (eg, during the time t _i to t _i+4 ), the ACCEL signal 1236 is low and the HDR_EN signal 1082 can be high or low. In the TON_BOOST state of the duty cycle reduction mode (eg, during the time t _j to t _j+1 ), the inductor current I _L10 , the output voltage V _OUT , the ramp signal 1032, the PULSE signal 1260, the HDR_EN signal 1082, the ACCEL signal 1236, And the state of the PWM signal 1084 is similar to the case of the TON_BOOST state of the duty cycle normal mode (for example, during the period from t _i to t _i+1 ). However, in the TOFF_BOOST state of the duty cycle reduction mode (eg, during the time t _i+1 to t _i+2 ), when the ramp signal 1032 is increased to the reference voltage V _H (eg, at time t _i+2 ), The output voltage V _{OUT is} greater than the preset potential V' _TARGET . Thus, for example, at time t _i+2 , PULSE signal 1260 is low, such that AND gate 1262 outputs a low potential signal to SR flip-flop 1248, which maintains PWM signal 1084 at a low potential. At the same time, comparator 1202 outputs a high potential signal to assert SR flip-flop 1258, which causes a low potential HDR_EN signal 1082 to be output. Therefore, the DC/DC converter 1000A enters the SKIP state (for example, during the time t _i+2 to t _i+3 ).

In the SKIP state, the HDR_EN signal 1082 turns off the delay switch 1234 connected between the resistor 1020 and the ramp capacitor 1008 such that the ramp signal 1032 remains unchanged. In addition, as the output capacitor 1016 discharges to the load (not shown in Figure 12), the output voltage _VOUT continues to decrease. When the output voltage V _OUT decreases to a preset potential V' _TARGET (eg, at time t _i+3 ), the comparator 1203 outputs a high potential PULSE signal 1260 to the gate 1262. Since the non-inverting output Q of the SR flip-flop 1258 is also high, the gate 1262 outputs a high potential signal to the SR flip-flop 1248 to set the PWM signal 1084 to a high potential. In response to this PWM signal 1084, the SR flip-flop 1258 asserts the HDR_EN signal 1082 to a high level and turns on the delay switch 1234. In other words, at time t _i+3 , the DC/DC converter 1000A enters a new TON_BOOST state. As a result, in the duty cycle reduction mode, the duty cycle of the PWM signal 1084 is reduced.

In the duty cycle increase mode (eg, during the time t _k to t _k+3 ), the ACCEL signal 1236 can be high or low and the HDR_EN signal 1082 is high. In the TON_BOOST state of the duty cycle increase mode (eg, during the time t _k to t _k+1 ), the inductor current I _L10 , the output voltage V _OUT , the ramp signal 1032, the PULSE signal 1260, the HDR_EN signal 1082, the ACCEL signal 1236, and The state of the PWM signal 1084 is similar to the case of the TON_BOOST state of the duty cycle normal mode (for example, during the period from t _i to t _i+1 ). However, in the TOFF_BOOST state of the duty cycle increase mode (eg, during the time t _k+1 to t _k+2 ), the output voltage V _{OUT is} decreased to the preset potential V before the ramp signal 1032 is increased to the reference voltage V _H ' _TARGET (for example: at time t _k+2 ). Thus, for example, at time t _k+2 , PULSE signal 1260 is at a high potential. Further, the inverted output terminal QB of the SR flip-flop 1248 is at a high potential. Therefore, the AND gate 1264 outputs a high potential ACCEL signal 1236 to turn on the acceleration switch 1232. The resistance R _{RP of the} resistor 1020 is decreased (for example, from R _RP0 + R _RP1 to R _RP0 ), and the control current I _{C10 is} increased. Therefore, the time required for the ramp signal 1032 to increase from the reference voltage V _L to the reference voltage V _H is shortened. When the ramp signal 1032 is increased to the reference voltage V _H (eg, at time t _k+3 ), the comparator 1202 outputs a high potential signal via the SR flip-flop 1258, the gate 1262, and the SR flip-flop 1248 to the PWM signal 1084. Set to high potential. Therefore, at time t _k+3 , the DC/DC converter 1000A enters a new TON_BOOST state. As a result, the duty cycle of the PWM signal 1084 increases during the duty cycle increase mode.

The controller 1002A automatically selects to operate in the duty cycle reduction mode, the duty cycle normal mode, or the duty cycle increase mode according to the state of the output voltage V _OUT . As a result, the average voltage V _{AVE of the} output voltage V _OUT is adjusted to the target voltage V _TARGET . The fluctuation amplitude of the output voltage V _OUT is relatively small and can be ignored. Therefore, the output voltage V _{OUT is} approximately equal to the target voltage V _TARGET .

Figure 14 is a schematic diagram of a DC/DC converter 1000B in accordance with an embodiment of the present invention. The same elements are identified in Figures 10A, 10B, 12 and 14 to have similar functions. As shown in FIG. 14, the controller 1002B includes a ramp signal generator 1030B, a PWM signal generator 1040B, and a feedback circuit 1070.

The ramp signal generator 1030B includes a resistor 1020, a ramp capacitor 1008, and a switch 1436. The first end 1023 of the resistor 1020 is coupled to the first end 1013 of the inductor 1014, and the second end 1025 of the resistor 1020 is coupled to the second end 1015 of the inductor 1014 via the switch 1436. A ramp capacitor 1008 is coupled between the second end 1025 of the resistor 1020 and ground.

The PWM signal generator 1040B includes an offset circuit 1442, a comparator 1401, a comparator 1402, a comparator 1403, an SR flip-flop 1448, and a AND gate 1462. The non-inverting input of the comparator 1401 is coupled to the second terminal 1015 of the inductor 1014 via the offset circuit 1442, the inverting input is coupled to the second terminal 1025 of the resistor 1020, and the output terminal is coupled to the reset terminal R of the SR flip-flop 1448. connection. The non-inverting input of the comparator 1402 is coupled to the first end of the high side switch 1010 (the switching node 1022 as shown), the inverting input and the second end of the high side switch 1010 (as shown in the figure). The high side end 1086) is connected and the output is connected to the enable output EN of the controller 1002B. The non-inverting input of comparator 1402 is coupled to a voltage source (not shown) that provides a predetermined voltage V _PRE , the inverting input is coupled to feedback circuit 1070 , and the output is coupled to AND gate 1462 . The input terminal of the AND gate 1462 is connected to the inverting output terminal QB of the comparator 1403 and the SR flip-flop 1448, and the output terminal is connected to the set terminal S of the SR flip-flop 1448. The inverting output QB of the SR flip-flop 1448 is also coupled to the control terminal of the switch 1436. In addition, the non-inverting output Q of the SR flip-flop 1448 is PWM coupled to the control output of the controller 1002B.

In the present embodiment, the comparator 1401 receives a reference voltage V from the shift circuit 1442 _^'L, and 1032 through the ramp signal and the reference voltage ^V' _L to the comparison output signal SR flip-flop 1448. The ramp signal comparator 1401 in 1032 is not greater than the reference voltage V _^'L outputs a high level signal when, in 1032 the ramp signal is greater than the reference voltage ^V' _L when the output signal of a low potential. The comparator 1402 receives the first terminal voltage V _SWH (eg, V _SWH =V ₁₀₁₃ ) of the high side switch 1010 and the second terminal voltage V _{SWL of the} high side switch 1010 (eg, V _SWL =V _OUT ), and compares the first end by comparing The voltage V _SWH and the second terminal voltage V _SWL output a signal to the enable output EN of the controller 1002B. The comparator outputs a high voltage at the first end 1402 is greater than the voltage V _SWH second terminal voltages V _SWL, low potential at the first end is not greater than a second voltage V _SWH voltage V _SWL. Moreover, similar to the manner depicted in Figure 12, the SR flip-flop 1448 is triggered by the rising edge of the input signal.

In this embodiment, the controller 1002B controls the chopping amplitude of the ramp signal 1032 and the inductor current I by comparing the ramp signal 1032 with the reference voltage V ^' _L and comparing the first terminal voltage V _SWH with the second terminal voltage V _SWL . The amplitude of the ripple of _L10 is constant. More specifically, the PWM signal generator 1040B controls the state of the PWM signal 1084 according to the comparison of the ramp signal 1032 and the reference voltage V ^' _L , and controls the control HDR_EN according to the comparison of the first terminal voltage V _SWH and the second terminal voltage V _SWL . The state of signal 1082.

When PWM signal 1084 is high, inductor current I _L10 increases and ramp signal 1032 decreases. When the inductor current I _L10 increases to a particular value (eg, when the ramp signal 1032 decreases to the reference voltage V ^' _L ), the comparator 1401 outputs a high potential signal to reset the SR flip-flop 1448. Thus, SR flip-flop 1448 sets PWM signal 1084 to a low potential to reduce inductor current I _L10 . At the same time, the inverting output QB of the SR flip-flop 1448 is high, turning the switch 1436 on, such that the ramp signal 1032 is controlled equal to the voltage V ₁₀₁₅ of the second terminal 1015 of the inductor 1014. The high side switch 1010 in this embodiment has an on-resistance such that the first terminal voltage V _SWH is greater than the second terminal voltage V _SWL if the inductor current I _{L10 is} greater than a preset value (eg, zero amps). When the inductor current I _L10 decreases to a preset value (eg, zero amps), the first terminal voltage V _SWH decreases to the second terminal voltage V _SWL , and the comparator 1402 sets the HDR_EN signal 1082 to a low potential to turn off the high voltage. Side switch 1010. Therefore, the inductor current I _{L10 is} not less than a preset value (for example, zero ampere). The comparator 1403 can again set the PWM signal 1084 to a high level according to the output voltage V _OUT . As a result, the ramp signal 1032 has a maximum value equal to the voltage V ₁₀₁₅ and a minimum value equal to the reference voltage V' _L . The inductor current I _L10 also has a maximum value and a minimum value (eg, the inductor current I _L10 is within a preset range based on the ramp signal 1032). The chopping amplitude of the ramp signal 1032 is equal to the difference between the voltage V ₁₀₁₅ and the reference voltage V' _L . The difference V ₁₀₁₅ - V' _{L is} constant such that the chopping amplitude of the ramp signal 1032 is constant. As a result, the amplitude of the chopping of the inductor current I _L10 is constant.

In the embodiment of FIG. 14, the switching circuit includes a high side switch 1010 and a low side switch 1012. However, in an alternate embodiment, the diode replaces the high side switch 1010 and the comparator 1402 is omitted. Specifically, the cathode of the diode is connected to the high side end 1086, and the anode is connected to the switching node 1022. Therefore, when the low side switch 1012 is turned on, the diode is reverse biased. When the low side switch 1012 is off and the inductor current I _{L10 is} greater than zero amps, the diode is forward biased. When the inductor current I _{L10 is} reduced to zero amps, the diode is turned off.

In the embodiment of FIG. 14, the circuit for controlling the voltage V ₁₀₂₅ of the second terminal 1025 of the resistor 1020 to the voltage V ₁₀₁₅ of the second terminal 1015 of the inductor 1014 includes: an offset circuit 1442, a comparator 1401, and a SR flip-flop 1448, and switch 1436. Specifically, the comparator 1401 compares the voltage V ₁₀₂₅ with the reference voltage V ^' _L to control the switch 1436 according to the comparison result. When the voltage V _{1025 is} decreased to the reference voltage V ^' _L , the switch 1436 is turned on such that the voltage V ₁₀₂₅ is controlled to be equal to the voltage V ₁₀₁₅ . Therefore, the voltage V _{1025 is in the} range of the reference voltage V ^' _L to the voltage V ₁₀₁₅ . The preset voltage across the offset circuit 1442 is V _S3 , and the reference voltage V ^' _L supplied to the comparator 1401 is equal to the voltage V ₁₀₁₅ minus the preset voltage V _S3 , for example: V ^' _L = V ₁₀₁₅ - V _S3 . The preset voltage V _S3 across the offset circuit 1442 in this embodiment is a constant value. Furthermore, the preset voltage V _{S3 is} relatively small compared to the voltage V ₁₀₁₅ , negligible, so that the voltage V ₁₀₂₅ varying in the range of the reference voltage V ^' _L to the voltage V ₁₀₁₅ is considered to be approximately equal to the voltage V ₁₀₁₅ .

In the embodiment of FIG. 14, comparator 1401 controls ramp signal 1032 to have a constant chopping amplitude, and control voltage _V1025 tends to voltage _V1015 . However, in another embodiment, ramp signal 1032 and voltage V _{1025 are} controlled by different comparators. In such an implementation, the range of ramp signal 1032 and the range of voltage V ₁₀₂₅ may be the same or different. In such an implementation, a current controlled current source (eg, current controlled current source 324 in FIG. 3) can be utilized to generate a control current equal to the current flowing through resistor 1020 to control ramp capacitance 1008.

In the present embodiment, by using the comparator 1403, the gate 1462, and the SR flip-flop 1448, the average voltage V _{AVE of the} output voltage V _OUT is adjusted to the target voltage V _TARGET . The adjustment process with respect to the average voltage V _AVE of the output voltage V _OUT will be described below with reference to FIG.

Figure 15 shows signals associated with the DC/DC converter 1000B of Figure 14 (e.g., inductor current I _L10 , output voltage V _OUT , ramp signal 1032, PULSE signal 1460, HDR_EN signal 1082, in accordance with an embodiment of the present invention). And an exemplary timing diagram 1500 of the PWM signal 1084).

As shown in FIG. 15, the operation of the controller 1002B includes different modes such as a duty cycle reduction mode, a duty cycle normal mode, and a duty cycle increase mode. In the duty cycle normal mode (eg, during t _n to t _n+4 ), when the inductor current I _L10 decreases to a preset value I _PRE (eg, at time t _n+2 ), the output voltage V _{OUT is} reduced. Small to preset potential V ^' _TARGET . The average voltage V _{AVE of the} output voltage V _OUT is equal to the target voltage V _TARGET . In this embodiment, the preset value I _{PRE is} equal to zero amperes. In the duty cycle reduction mode (eg, during t _m to t _m+4 ), when _L10 decreases to the preset value I _PRE (eg, at time t _m+2 ), the output voltage V _{OUT is} greater than the preset Potential V ^' _TARGET . The average voltage V _{AVE is} greater than the target voltage V _TARGET . Then, controller 1002B reduces the duty cycle of PWM signal 1084 to reduce the average voltage V _AVE . In the duty cycle increase mode (eg, during time t _s to t _s+3 ), the output voltage V _{OUT is} reduced to a preset potential V ^' _TARGET before the inductor current I _L10 decreases to a preset value I _PRE (eg: At time t _s+2 ). The average voltage V _{AVE is} less than the target voltage V _TARGET . Then, controller 1002B increases the duty cycle of PWM signal 1084 to increase the average voltage V _AVE .

In the embodiment shown in FIG. 15, in the duty cycle normal mode, the HDR_EN signal 1082 is inverted from the PWM signal 1084. For example, the HDR_EN signal 1082 is low when PWM is high and high when PWM is low. The PULSE signal 1460 is in phase with the PWM signal 1084. For example, PULSE signal 1460 is high when PWM signal 1084 is high and low when PWM signal 1084 is low. The ramp signal 1032 decreases in the TON_BOOST state (eg, during the time t _n to t _n+1 ), and is equal to the voltage V ₁₀₁₅ in the TOFF_BOOST state (eg, during the time t _n+1 to t _n+2 ). The inductor current I _L10 has a sawtooth waveform. Since the chopping amplitude of the ramp signal 1032 is constant, the chopping amplitude of the inductor current I _L10 is constant. The output voltage V _OUT fluctuates up and down with a preset potential V ^' _TARGET as a reference potential, but the average voltage V _{AVE of the} output voltage V _OUT is equal to the target voltage V _TARGET . As described above, the preset potential V ^' _{TARGET is} approximately equal to the target voltage V _TARGET .

More specifically, in the TON_BOOST state of the duty cycle normal mode (eg, during the time t _n to t _n+1 ), the inductor current I _{L10 is} increased according to equation (23), and the ramp signal 1032 is decreased according to equation (26). And the output voltage V _{OUT is} reduced. The PWM signal 1084 is high. Because the high side switch 1010 is off and the low side switch 1012 is on, the switching node 1022 is grounded. Therefore, the first terminal voltage V _{SWH of the} high side switch 1010 is less than the second terminal voltage V _{SWL of the} high side switch 1010, and the comparator 1402 sets the HDR_EN signal 1082 to a low potential. Further, the output voltage V _{OUT is} less than the preset potential V ^' _TARGET (eg, the feedback voltage V _{FB is} less than the preset voltage V _PRE ), and the comparator 1403 sets the PULSE signal 1460 to a high potential.

When the ramp signal 1032 is reduced to the reference voltage V ^' _L (eg, at time t _n+1 ), the comparator 1401 outputs a high potential signal to reset the SR flip-flop 1448 to output a low potential PWM signal 1084. The low side switch 1012 is then turned off. Second, the inverting output terminal QB of the SR flip-flop 1448 is asserted high to turn on the switch 1436. At time t _n+1 , inductor 1014, resistor 1020, and switch 1436 form a current loop. Inductor 1014 releases energy via a current loop (eg, converts magnetic field energy into electrical energy), such that voltage V _{1013 is} greater than voltage V ₁₀₁₅ . At time t _n+1 in this embodiment, the first terminal voltage V _SWH (eg, V _SWH =V ₁₀₁₃ ) is greater than the second terminal voltage V _SWL (eg, V _SWL =V _OUT ), such that the comparator 1402 will HDR_EN Signal 1082 is asserted high to turn on high side switch 1010. Therefore, the DC/DC converter 1000B enters the TOFF_BOOST state.

In the TOFF_BOOST state (eg, during the time t _n+1 to t _n+2 ), the high side switch 1010 is turned on, and the output voltage V _{OUT is} greater than the preset potential V' _TARGET . Thus, comparator 1403 outputs a low potential PULSE signal 1460. Inductor current I _L10 flows into high side end 1086 via high side switch 1010. As the inductor current I _L10 decreases, the voltage across the high side switch 1010 (eg, V _SWH -V _SWL ) decreases. When the inductor current I _{L10 is} reduced to zero amps, the first terminal voltage V _{SWH is} reduced to the second terminal voltage V _SWL . Thus, as indicated at time tn ₊₂ , comparator 1402 sets HDR_EN signal 1082 low to turn off high side switch 1010. In addition, in the duty cycle normal mode, when the inductor current I _{L10 is} reduced to zero amps, the output voltage V _{OUT is} reduced to a preset potential V' _TARGET . Therefore, at time t _n+2 , comparator 1403 outputs high potential PULSE signal 1460 to set PWM signal 1084 to high potential via AND gate 1462 and SR flip-flop 1448. The DC/DC converter 1000B enters a new TON_BOOST state at time t _n+2 .

In TON_BOOST reduction mode duty cycle state (e.g.: t _m to t _{m + 1} time period), the inductor current I _L10, the output voltage V _OUT, the ramp signal 1032, PULSE signal 1460, HDR_EN signal 1082, and the PWM signal 1084 The state is similar to the case of the duty cycle normal mode in the TON_BOOST state (for example, during t _n to t _n+1 time). However, in the TOFF_BOOST state of the duty cycle reduction mode (eg, during the time t _m+1 to t _m+2 ), when the inductor current I _L10 decreases to a preset value I _PRE (eg, zero amps), the output The voltage V _{OUT is} greater than the preset potential V' _TARGET . Thus, for example, during t _m+2 to t _m+3 , the comparator 1403 outputs a low potential PULSE signal 1460 to maintain the PWM signal 1084 at a low potential via the AND gate 1462 and the SR flip-flop 1448. At the same time, the HDR_EN signal 1082 is low. Therefore, the DC/DC converter 1000B enters the SKIP state (for example, during the time t _m+2 to t _m+3 ).

In the SKIP state, the inductor current I _L10 is zero amps, the ramp signal 1032 is held at voltage V ₁₀₁₅ , and the output voltage V _{OUT is} reduced. When the output voltage V _OUT decreases to the preset potential V ^' _TARGET (eg, at time t _m+3 ), the comparator 1403 outputs a high potential PULSE signal 1460 via the AND gate 1462 and the SR flip-flop 1448 to set the PWM signal 1084. It is high potential. Therefore, the DC/DC converter 1000B enters a new TON_BOOST state at time t _m+3 . As a result, in the duty cycle reduction mode, the duty cycle of the PWM signal 1084 is reduced.

In the TON_BOOST state of the duty cycle increase mode (eg, during the time t _s to t _s+1 ), the inductor current I _L10 , the output voltage V _OUT , the ramp signal 1032 , the PULSE signal 1460 , the HDR_EN signal 1082 , and the PWM signal 1084 The state is similar to the case of the duty cycle normal mode in the TON_BOOST state (for example, during t _n to t _n+1 ). However, in the TOFF_BOOST state of the duty cycle increase mode (eg, during t _s+1 to t _s+2 ), the output voltage is before the inductor current I _L10 decreases to a preset value I _PRE (eg, zero amps) V _{OUT is} reduced to a preset potential V ^' _TARGET (for example, at time t _{s + 2} ). Thus, for example, at time ts ₊₂ , comparator 1403 outputs a high potential PULSE signal 1460 to set PWM signal 1084 to a high potential. In other words, the DC/DC converter 1000B enters a new TON_BOOST state before the inductor current I _L10 decreases to a preset value I _PRE . As a result, the duty cycle of the PWM signal 1084 increases during the duty cycle increase mode.

The controller 1002B automatically selects to operate in the duty cycle reduction mode, the duty cycle normal mode, or the duty cycle increase mode according to the state of the output voltage V _OUT . As a result, the output voltage V _OUT is adjusted to the target voltage V _TARGET .

16 is a flow chart 1600 of a current control method in accordance with an embodiment of the present invention. FIG. 16 will be described below with reference to FIGS. 10A, 10B, 12, and 14.

In step 1602, controller 1002, controller 1002A or controller 1002B provides control current I _C10 flowing through resistor 1020 to control the electrical energy stored in ramp capacitor 1008. In step 1604, controller 1002, controller 1002A or controller 1002B adjusts voltage V ₁₀₂₅ of second terminal 1025 of resistor 1020 to voltage V ₁₀₁₅ of second terminal 1015 of inductor 1014.

In step 1606, controller 1002, controller 1002A, or controller 1002B controls control current I _{C10 to} indicate (eg, linearly proportional to) the voltage across inductor 1014 based on voltage V ₁₀₂₅ of second terminal 1025 of resistor 1020. In step 1608, controller 1002, controller 1002A, or controller 1002B generates ramp signal 1032 based on the electrical energy stored in ramp capacitor 1008. In step 1610, controller 1002, controller 1002A, or controller 1002B controls inductor current I _L10 flowing through inductor 1014 to be within a predetermined range based on ramp signal 1032. In the present embodiment, the controller 1002, the controller 1002A or the controller 1002B constantly controls the chopping amplitude of the inductor current I _L10 by controlling the chopping amplitude of the ramp signal 1032 to be constant.

Accordingly, the present invention provides a DC/DC converter with a CRC controller (eg, a buck converter, a boost converter, etc.). The CRC controller adjusts the output voltage of the DC/DC converter to the target potential. In addition, the CRC controller controls the output current of the DC/DC converter with a constant chopping amplitude using a resistive element, an inductive element, a capacitive element, and a comparator or the like. Therefore, the output voltage and current of the DC/DC converter are more stable. Such a DC/DC converter can be widely used in power supply systems of integrated circuits, diodes, and display systems and the like.

The above detailed description and the accompanying drawings are only typical embodiments of the invention. It is apparent that various additions, modifications and substitutions are possible without departing from the spirit and scope of the invention as defined by the appended claims. It should be understood by those skilled in the art that the present invention may be changed in form, structure, arrangement, ratio, material, element, element, and other aspects without departing from the scope of the invention. Therefore, the embodiments disclosed herein are intended to be illustrative and not restrictive, and the scope of the invention is defined by the appended claims

100, 100A, 100B, 100C. . . DC/DC converter

102, 102A, 102B, 102C. . . Control circuit

104. . . Drive circuit

106. . . Switch circuit

108. . . Output circuit

110. . . High side switch

112. . . Low side switch

114. . . inductance

116. . . capacitance

118. . . path

120. . . path

122. . . Switch node

124. . . resistance

126. . . capacitance

128. . . resistance

150. . . Controller

152. . . Oscillator

154. . . Comparators

156. . . Operational transconductance amplifier

158. . . capacitance

160. . . Oscillating voltage

162. . . Reference voltage

164. . . Feedback voltage

166. . . Preset voltage

168. . . PWM signal

200. . . form

301. . . First comparator

302. . . Second comparator

303. . . Third comparator

308. . . Ramp capacitor

311. . . Reverse gate

312. . . Ramp signal

320. . . resistance

322, 323. . . Gate

324. . . Current controlled current source

342. . . Positive and negative

350. . . Ramp generating circuit

351. . . buffer

352. . . Pulse width modulation circuit

372. . . switch

373. . . resistance

400. . . Timing diagram

401~408. . . Waveform

501. . . First comparator

502. . . Second comparator

503. . . Third comparator

506. . . node

508. . . Ramp capacitor

509. . . path

511. . . Reverse gate

512. . . Ramp signal

520. . . resistance

522, 523. . . Gate

542. . . Positive and negative

550. . . Ramp generating circuit

551. . . Operational Amplifier

552. . . Pulse width modulation circuit

600. . . Timing diagram

601~607. . . Waveform

701. . . First comparator

702. . . Second comparator

703. . . Third comparator

704. . . Drive circuit

708. . . Ramp capacitor

712. . . Ramp signal

713. . . switch

714. . . inductance

720. . . resistance

722. . . Gate

723. . . Reverse gate

725. . . Gate

742. . . Latches

750. . . Ramp generating circuit

751. . . Operational Amplifier

752. . . Pulse width modulation circuit

771. . . resistance

800. . . Timing diagram

801~805. . . Waveform

900. . . flow chart

902, 904. . . step

1000, 1000', 1000A, 1000B. . . DC/DC converter

1002, 1002A, 1002B. . . Controller

1004. . . driver

1008. . . Ramp capacitor

1010. . . High side switch

1012. . . Low side switch

1013. . . First end

1014. . . inductance

1015. . . Second end

1016. . . Output capacitor

1018. . . Circuit

1020. . . resistance

1022. . . Switch node

1023. . . First end

1024. . . resistance

1025. . . Second end

1026. . . capacitance

1028. . . resistance

1030, 1030A, 1030B. . . Ramp signal generator

1032. . . Ramp signal

1040, 1040A, 1040B. . . PWM signal generator

1070. . . Feedback circuit

1082. . . Enable signal

1084. . . PWM signal

1086. . . High side

1088. . . Low side

1100. . . form

1201, 1202, 1203. . . Comparators

1220, 1221. . . Secondary resistance

1232, 1234. . . switch

1236. . . signal

1242. . . Offset circuit

1244. . . Battery

1246. . . resistance

1248. . . SR flip-flop

1252. . . Offset circuit

1254. . . Battery

1256. . . resistance

1258. . . SR flip-flop

1260. . . signal

1262, 1264. . . Gate

1272, 1274. . . resistance

1300. . . Timing diagram

1401, 1402, 1403. . . Comparators

1436. . . switch

1442. . . Offset circuit

1448. . . SR flip-flop

1462. . . Gate

1500. . . Timing diagram

1600. . . flow chart

1602~1610. . . step

The technical method of the present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments to make the features and advantages of the present invention more obvious. among them:

Figure 1A shows the controller in a conventional DC/DC converter.

1 is a schematic diagram of a DC/DC converter in accordance with an embodiment of the present invention.

2 is an exemplary table of switch states in accordance with an embodiment of the present invention.

3 is a schematic diagram of a DC/DC converter in accordance with an embodiment of the present invention.

4 is an exemplary timing diagram in accordance with an embodiment of the present invention.

Figure 5 is a schematic diagram of a DC/DC converter in accordance with an embodiment of the present invention.

FIG. 6 shows an exemplary timing diagram in accordance with an embodiment of the present invention.

7 is a schematic diagram of a DC/DC converter in accordance with an embodiment of the present invention.

FIG. 8 shows an exemplary timing diagram in accordance with an embodiment of the present invention.

9 is a flow chart of an exemplary method of current control in accordance with an embodiment of the present invention.

Figure 10A is a schematic diagram of a DC/DC converter in accordance with an embodiment of the present invention.

Figure 10B is a schematic diagram of a DC/DC converter in accordance with another embodiment of the present invention.

Figure 11 shows the state change table for the high side switch and the low side switch in response to the enable signal and the PWM signal.

Figure 12 is a schematic diagram of a DC/DC converter in accordance with an embodiment of the present invention.

Figure 13 is a timing diagram of signals associated with the DC/DC converter of Figure 12, in accordance with an embodiment of the present invention.

Figure 14 is a schematic diagram of a DC/DC converter in accordance with an embodiment of the present invention.

Figure 15 is a timing diagram of signals associated with the DC/DC converter of Figure 14 in accordance with one embodiment of the present invention.

Figure 16 is a flow chart showing a current control method in accordance with an embodiment of the present invention.

100. . . DC/DC converter

102. . . Control circuit

104. . . Drive circuit

106. . . Switch circuit

108. . . Output circuit

110. . . High side switch

112. . . Low side switch

114. . . inductance

116. . . capacitance

118. . . path

120. . . path

122. . . Switch node

124. . . resistance

126. . . capacitance

128. . . resistance

Claims (19)

A controller comprising: a ramp signal generator providing a control current flowing through a resistive element to control an energy stored in a second energy storage element and based on being stored in the second energy storage element The energy generates a ramp signal; and a control circuit coupled to the ramp signal generator to adjust a voltage at one end of the resistive element to control the control current to indicate a voltage across a first energy storage element, and A current flowing through the first energy storage element is controlled to be within a predetermined range based on the ramp signal. The controller of claim 1, wherein the control circuit controls the voltage at one end of the resistive element to a voltage at one end of the first energy storage element. The controller of claim 2, wherein the control circuit comprises: a first comparator that compares the voltage at one end of the resistive element with a first reference voltage; and a second comparator that compares the resistance The voltage at one end of the element and a second reference voltage, wherein the first reference voltage is equal to the voltage at one end of the first energy storage element plus a first predetermined voltage, the second reference voltage being equal to the first energy The voltage at one end of the storage element is subtracted from a second predetermined voltage. The controller of claim 2, wherein the control circuit comprises a comparator for comparing the voltage and a reference of one end of the resistive component Testing a voltage, according to a comparison result, controlling a switch coupled between one end of the resistive element and one end of the first energy storage element, wherein the reference voltage is equal to the voltage of one end of the first energy storage element minus a pre- Set the voltage. The controller of claim 1, wherein the control circuit controls the control current to be linearly proportional to the voltage across the first energy storage element. The controller of claim 1, wherein the control circuit comprises a pulse width modulation signal generator coupled to the second energy storage element to generate a pulse width modulation signal to control a high side path. And a continuity of the low side path, wherein the high side path and the low side path are coupled to the first energy storage element via a switching node. The controller of claim 6, wherein the control circuit compares the ramp signal with a reference voltage, and controls the pulse width modulation signal according to a comparison result. The controller of claim 1, wherein the control circuit chops constant by one of the currents flowing through the first energy storage element by controlling one of the ramp signals. A method of controlling a current flowing through an energy storage element, comprising: providing a control current flowing through a resistive element to control an energy stored in a second energy storage element; and adjusting a voltage at one end of the resistive element; Controlling the control current based on the voltage at one end of the resistive element to indicate a voltage across a first energy storage element; generating an oblique based on the energy stored in the second energy storage element a slope signal; and controlling a current flowing through the first energy storage element to be within a predetermined range based on the ramp signal. The method of claim 9, wherein the step of adjusting the voltage at one end of the resistive element comprises: controlling the voltage at one end of the resistive element to a voltage at one end of the first energy storage element. The method of claim 9, wherein the step of controlling the voltage based on the voltage at one end of the resistive element to indicate the voltage across the first energy storage element comprises: controlling the linear proportionality of the control current The voltage across the first energy storage element. The method of claim 9, wherein the step of controlling the current flowing through the first energy storage element within the predetermined range based on the ramp signal comprises: chopping a constant wave by controlling one of the ramp signals, Further, one of the currents flowing through the first energy storage element is controlled to be constant. A DC/DC converter includes: a first energy storage component, the DC/DC converter outputting an output voltage; a pair of switches coupled to the first energy storage component; and a controller coupled to the first An energy storage element and the pair of switches provide a control current flowing through a resistive element to control an energy stored in a second energy storage element, based on the energy stored in the second energy storage element Ramp signal, by adjusting the resistance A voltage at one end of the component controls the control current to indicate a voltage across the first energy storage component, and the pair of switches are controlled based on the ramp signal to control the output voltage and a current flowing through the first energy storage component. A DC/DC converter according to claim 13 wherein the controller controls the voltage at one end of the resistive element to a voltage at one end of the first energy storage element. A DC/DC converter according to claim 13 wherein the controller controls the control current to be linearly proportional to the voltage across the first energy storage element. The DC/DC converter of claim 13, wherein the controller comprises a pulse width modulation signal generator coupled to the pair of switches to generate a pulse width modulation signal to control the pair of switches. The DC/DC converter of claim 16, wherein the controller further comprises: a comparator, comparing the ramp signal and a reference voltage, and controlling the pulse width modulation signal according to a comparison result, thereby controlling A chopping of the current flowing through the first energy storage element. The DC/DC converter of claim 16, wherein the controller further comprises: a comparator that compares a feedback signal indicating the output voltage with a reference voltage, and controls the pulse width according to a comparison result. The signal is modulated to control the output voltage. A DC/DC converter according to claim 13 wherein the controller controls a chopper constant control flow by controlling one of the ramp signals One of the currents through the first energy storage element is chopped constant.