JP3416219B2 - Power supply - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-output switching power supply equipped with a capacitor input type rectification converter, which prevents a power factor reduction due to distortion of an input current waveform and a generation of a high long-wave current and a generation of a reactive power. The present invention relates to a switching power supply circuit that enables effective use of electric power by preventing malfunctions of devices connected to the same commercial power supply line and suppressing inrush current to a capacitor when power is turned on. .

[0002]

2. Description of the Related Art Conventionally, a rectifier using a capacitor input type rectifying / smoothing circuit has been used as a DC power supply for various electronic devices. Generally, AC of commercial frequency is converted to DC. In this case, a rectifying circuit with a diode, a smoothing circuit with a capacitor, and a rush current consisting of a precharging circuit with a resistor to prevent a rush current into the capacitor used for the smoothing circuit and an electromagnetic contactor that short-circuits the resistance of the precharging circuit. It is composed of a prevention circuit. FIG. 23 shows a circuit configuration example of a conventional rectifying device using such a system.

In FIG. 23, 51 and 52 are input terminals, to which an AC voltage is applied. Input terminal 51
Is an AC terminal of the rectifier stack RC1 and an input terminal 52
Is connected to the other AC terminal of the rectifier stack RC1,
The positive terminal of the rectifier stack RC1 is connected to one terminal of the resistor R1 and one contact of the electromagnetic contactor MC1.
Further, the other terminal of the resistor R1 and the electromagnetic contactor MC1
The other contact of is connected to the smoothing capacitor C1 and the output terminal 53, and the negative terminal of the rectifier stack RC1 is connected to the output terminal 54.

A voltage detection circuit 55 is connected in parallel with the capacitor C1 in order to control ON / OFF of the electromagnetic contactor MC1. The voltage detection circuit 55 is composed of a voltage dividing resistance circuit, a comparator and the like, and detects the terminal voltage of the capacitor C1. The output of the voltage detection circuit 55 is connected to the drive circuit 56, and the drive circuit 56 drives the electromagnetic contactor MC1.

Next, the operation of the circuit shown in FIG. 23 will be described. When AC power is connected to the input power terminals 51, 52,
It is converted into a pulsating flow by the rectifying action of the rectifier stack RC1. At this time, the contact of the electromagnetic contactor MC1 is broken, the capacitor C1 is precharged by the resistor R1, and the voltage gradually rises. When the precharge is repeated and the voltage of the capacitor C1 rises and reaches a predetermined voltage, the voltage detection circuit 5
5 sends a signal to the drive circuit 56.

The drive circuit 56 receives a signal from the voltage detection circuit 55 and drives the electromagnetic contactor MC1 to make contacts. When the contact of the electromagnetic contactor MC1 is made, the resistor R1 is short-circuited, the pre-charging circuit is ignored, the rectifier stack RC1 and the smoothing capacitor C1 operate as a rectifying / smoothing circuit, and DC power is determined by the output terminals 53 and 54. Supplied to the load.

As described above, when the smoothing capacitor C1 is in an uncharged state, it is pre-charged by the pre-charging circuit, and when the pre-charging is completed, the pre-charging circuit is disconnected so that the inrush current at the time of turning on the power supply is reduced. Rectification and smoothing are performed while suppressing and DC power is obtained.

[0008]

[Problems to be Solved by the Invention]

(1) However, in the conventional capacitor input type rectification method as described above, as shown in FIG. 11 which is a circuit configuration diagram and FIG. 12 (a) is an input voltage / current waveform diagram thereof, The current flows only during the period when the input voltage is equal to or higher than the terminal voltage of the capacitor, not during the entire period of the AC cycle. Since the average value of the charging current i _c flowing through the capacitor is equal to the DC output current I ₀ , it can be expressed as the following equation: I ₀ = I / T · ∫i _c dt That is, the area of the charging current i _c Is equal to the output current I ₀ ,
To obtain the same output current, the smaller the conduction feedback, the larger the peak value of the charging current of the capacitor. Therefore, the effective value of the charging current expressed by the following equation becomes very large; i _crms = SquareRoot (1 / T · ∫i _c ² dt) Therefore, the ESR (equivalent series resistance) of the smoothing electrolytic capacitor There is a problem in that the temperature rises due to internal loss and the life of the power supply decreases, which improves the reliability of the power supply. Further, there is a problem in that the power factor represented by the ratio of the effective power to the apparent power decreases due to the increase in the above-mentioned effective current.

On the other hand, the other rectification method, the choke input type rectification method, is
Although the peak value is pushed by the impedance of the choke coil, the power factor that extends the conduction period is improved,
It is said that the rectified output voltage becomes an average value of the pulsating current voltage, so that it becomes lower than the actual value of the input voltage, and when the output current is small, it becomes a capacitor input type rectification operation and the output voltage rises. There is a problem that a choke coil with a large inductance is large in shape and heavy in weight, so that it is not suitable for a small device.

As a rectification method for solving the above problems, a rectification method called an active filter has been adopted. This method is shown in FIG.
In the rectifier circuit having a circuit configuration as shown in the example of the input voltage / current waveform diagram in (b), by switching the switching element at a frequency sufficiently higher than the commercial frequency over the entire cycle with respect to the input voltage, The current waveform becomes the average value of the current flowing at each switching, and the current waveform can be shaped into a sine wave.

Although the problem caused by the current waveform distortion is solved by this, a control circuit and a switching element must be prepared in addition to the power source provided in the subsequent stage in view of the circuit configuration, and the power source device is small in size. There were problems such as incorporation into the device and cost increase.

As described above, the electric power is effectively used, and
In order to prevent adverse effects such as malfunctions on electrical equipment connected to the commercial power supply line, an active filter that can control the power factor to be close to '1' is the most effective, but the circuit is almost a switching power supply. Since the circuit configurations are the same, one rectifier unit and one converter unit each have a control device, and in a power supply device having a plurality of output systems, the control circuit becomes extremely complicated. The first problem).

(2) Further, the capacitor input type rectification system as described above has a problem that a large inrush current is generated when the power is turned on because the capacitor is equal to a short circuit when the charge is zero.

As a conventional method for solving this problem,
The current value was suppressed by inserting some impedance component in the rectifier circuit. FIG. 18 shows a conventional typical inrush current limiting method. FIG. 18 (a) is a case where a power thermistor is used, in which the resistance value decreases as the temperature rises, and FIG. 18 (b) shows a case where a thyristor is used and the output of the transformer is used as a gate signal. This is the method to use.

However, when a power thermistor is used as an impedance component as shown in FIG. 18A, it takes time from turning off the power source to returning to the original resistance value due to a thermal time constant, so that it takes a short interval. When the switch is turned on / off, there is a drawback that the current limiting capability is lost and an inrush current flows. Also, when a thyristor is used as shown in FIG. By adding a signal, it is possible to make the thyristor conductive and short-circuit the resistance, so that loss in the resistance does not occur, but when the thyristor becomes conductive, the rush current to the capacitor flows again, so The time it takes for the thyristor to conduct must be long enough to match the charging time constant of the smoothing capacitor,
In addition, when the voltage remains in the capacitor to some extent when the power is turned on again, the start-up time of the control IC and the like becomes short, that is, the time until the operation of the switching element becomes short, and the start-up time of the thyristor becomes short. However, there is a drawback that an inrush current flows.

As described above, the large inrush current is a problem in that stress is applied to the capacitor itself, the rectifying diode, the contact of the power switch, and the like (second problem).

(3) Furthermore, in the conventional rectifying device as described above, the completion of the preliminary charging is set to a reference value and a capacitor which are set in advance so that the voltage difference from the input voltage is sufficiently small. Since the judgment is made by comparing the terminal voltage, if the input voltage becomes high due to the voltage fluctuation, it is judged that the precharge is completed before the voltage difference between the input voltage and the capacitor terminal voltage becomes small, and the electromagnetic I had operated the contactor. (Third problem).

The present invention has been made in view of the above problems, and an object of the present invention is to provide a power supply device of this type which can solve these problems.

[0019]

Means for Solving the Problems] was to achieve the object
Therefore, in the present invention, the power supply device is provided with the following (1) to (4)
Configure as follows. (1) Equipped with a capacitor input type rectification converter
Or a switching power supply with multiple voltage output systems
To improve the power factor by making the input current waveform sinusoidal.
Power factor correction means for single and multiple output of a given voltage
And a DC-DC converter for obtaining the power factor,
The improving means and the DC-DC converter have the same PWM control.
Means for controlling the feedback by means of a power supply
In the above arrangement, the PWM control means is an output voltage detection means.
The voltage level detected by the
Level correction means for correcting the detected value of the output means
And comparing the output value of the level correction means with a reference value
The error amplifier, the output of this error amplifier and the input voltage waveform detection
The line voltage waveform detected by the output means is multiplied by
Multiplied by the output and input current detection means detected
An analog comparator that compares the current level with this
Count up / down by output of analog comparator
Down / up counter for selecting
Of the choke coil installed in the sensor input type rectification converter.
Zero cross to detect zero cross from waveform of current detection winding
Zero-cross signal from detection circuit or own over
Output value of the up / down counter according to the unmount signal
A second counter for loading and this second cow
The first digital value that compares the digital output value with a predetermined digital value
The digital comparator and the first digital converter
The output of the parator connects and disconnects both ends of the capacitor.
A drive circuit for driving the switching element and the second cover.
The counter output is compared with a predetermined digital value, and the
Disable / permit the load operation of the second counter by the clock signal
A second digital comparator for
Before comparing the output value of the counter with the specified digital value
Inhibit count-up operation of up / down counter
/ With a third digital comparator for enabling
Source device. (2) In the power supply device according to (1) above, the PWM
With control means , CPU, ROM, RAM and these
Associated digital circuits and digital-to-analog conversion
On the same chip
A power supply device integrated on top to form an integrated circuit. (3) In the power supply device according to (2) above, the PWM
A power supply unit whose control means is digital control only. (4) In the power supply device according to (1) above, the power factor modification
The good measure and the switching element of the DC-DC converter are the same.
A power supply device configured to be covered by one element.

[0020]

[0021]

[0022]

[0023]

[0024]

[0025]

[0026]

[0027]

[0028]

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on embodiments; (First Embodiment) FIG. 1 is a circuit configuration diagram of a first embodiment of a power supply device according to the present invention, and FIG. The block diagram of the structure of the PWM control means of the embodiment is shown.

In FIG. 1, Acin is an input current detection circuit, Zs is a zero cross detection circuit for detecting the zero cross of the current flowing through the coil, Avin is an input voltage waveform detection circuit for capturing the line voltage waveform, and Acv is a capacitor C.
1 is a voltage detection circuit for detecting the voltage across 1
Output voltage detection circuit for detecting the output voltage of the secondary side, 2
Is the voltage detection circuit Acv according to the detection value of the voltage detection circuit 1.
The level correction circuit 3 for correcting the detection value of 1 is a PWM control means for performing feedback control according to the output value of the level correction circuit 2.

Reference numeral 4 designates the power MOSFET Q1 as the P
A drive circuit for driving with the output signal of the WM control means 3,
Reference numeral 5 is a drive circuit for driving the power MOSFET Q2 by using a signal obtained by dividing the pulse signal of the clock 7 by the frequency dividing circuit 6 as a control signal.

DB1 is a diode bridge for rectifying AC AC, L1 is a coil forming an active filter, D1 is a diode forming a smoothing circuit, C1 is a capacitor, T1 is a converter transformer, D2, D3.
CH1 and Co are respective diodes, coils, and capacitors that form a smoothing circuit on the secondary side.

In FIG. 2 showing the PWM control means 3 of FIG. 1, 11 is an error amplifier for amplifying the error between the level-corrected voltage detection signal Vos and the reference value Vref, 1
2 is the error amplifier 1 for the input voltage waveform signal Vwsen
1 is a multiplier for multiplying the output of 1, and 13 is a current detection signal Ise
It is an analog comparator for comparing n with the output of the multiplier 11.

Reference numeral 15 is an up / down counter for selecting a count-up / count-down by the output of the analog comparator 13, and 16 is a second counter which loads the output value of the up / down counter 15 and counts down. It is a down counter.

Reference numeral 19 denotes a first digital comparator for comparing the output value of the down counter 16 with a predetermined digital value X, and 20 compares the output value of the down counter 16 with a predetermined digital value Y, Down counter 1
6 is a third digital comparator for prohibiting / permitting the count-up operation, 14 is an up / down control circuit for controlling the count mode of the up / down counter 15, and 17 is an underflow signal of the down counter 16. load signal h to the down counter 16 by f
Flip-flop circuit for generating (hereinafter F / F)
Is. Further, 18 is a digital comparator, and 21 is a gate.

Next, the operation will be described with reference to FIG.
First, the operation of the active filter section will be described. The commercial frequency power supply connected to the input power supply terminal is the rectifier bridge D
After being rectified by B1, one end is F through coil L1.
It is connected to the drain of ET Q1 and is connected to the “+” side of electrolytic capacitor C1 through diode D1. The other end is connected to the “−” side of the electrolytic capacitor C1 connected to the source of the FET Q1.

In this circuit, the switching element Q1
, The power line is repeatedly shorted / opened, the current flowing in the coil L1 becomes a triangular wave, and the electrolytic capacitor connected via the diode D1 is discharged through the load when the FET Q1 is on, When it is off, it flows in the direction of charging by the amount of energy stored in the coil L1. By setting the drive signal of the switching element Q1 to have a pulse width as shown in the operation timing chart of FIG. 3, the average value of the current flowing through the coil L1 becomes a sine wave as shown in the figure, and the input The current waveform is sinusoidal. Further, here, when a load is connected to the capacitor Co, the amplitude of the input current waveform is varied according to the magnitude of the load current, so that the voltage across the capacitor Co can be made constant.

That is, in this embodiment, a desired voltage is obtained on the secondary side via the converter transformer T1.
This is achieved by correcting the detection value of the output voltage detection circuit Acv with a level correction circuit that corrects the detection value of the output voltage detection circuit, and detecting the error between the value Vos and the specified reference voltage Vref of the input voltage waveform detection circuit Avin. By multiplying the value Vwsen by the multiplier M1 12 and comparing the value with the detected value Isen of the current detection circuit Aci, a drive signal as shown in the figure is generated in the PWM control means 3,
It is possible to make the secondary side output a constant voltage while generating the input sine wave current according to the output current.

Next, the DC-DC converter section will be described; in FIG. 1, 1 of the converter transformer T1 is used.
One end of the next winding N1 is connected to the “+” side of the electrolytic capacitor C1, and the other end is connected to the drain of the power MOSFET Q2. When the power MOSFET Q2 is turned on and off, a voltage according to the turn ratio is generated in the secondary winding N2. In this embodiment, the clock signal input to the PWM control means 3 is divided, a constant frequency and duty are created, and switching is performed. As a result, the AC voltage generated in the secondary winding N2 is rectified and smoothed by the diodes D2 and D3 and the electrolytic capacitor Co, and is output to the outside as a power supply output. This output is detected by the output voltage detection circuit 1 according to the value detected by the voltage detection circuit Acv.
By correcting the detected value of 1 by the level correction circuit 2, the voltage across the capacitor Co is changed and the output voltage is made constant.

Next, the PWM control means 3 will be described with reference to FIG.
Of the output signal from the zero-cross detection circuit Zs which generates a zero-cross signal from the detection value of the current detection circuit Aci through the gate 21 to the down counter 16
It is connected to the preload terminal of. When a signal is input to the preload terminal, the counter 16 is configured to forcibly generate an underflow, and the underflow output is F / F1.
It is input to the load terminal of the down counter 16 via 7 and to the up / down control circuit 14.

The down counter 16 has a commercial power frequency (5
It is driven by a clock signal clk of an oscillation circuit (not shown) that generates a frequency sufficiently higher than 0 Hz, 60 Hz). The up / down counter 15 is connected to a data input terminal for setting data input when the load signal of the counter 16 is input. This counter 15
Is the output value of the level correction circuit 2 of FIG. 1 and the reference value Vre
The output of the analog comparator 13 and the output of the digital comparator 18 and the F / F 17 for comparing the value obtained by multiplying the error value with f by the detection value of the input voltage waveform detection circuit Avin and the detection value of the current detection circuit Aci. From the above, the up / down control circuit 14 for generating the up / down signal and the clock performs up or down counting. The output of the counter 16 is connected to the comparator 19 and the comparator 20.
6 is compared with the set value input X to generate a pulse signal.
With this pulse signal, the drive circuit of FIG.
Drive ET Q1.

The comparator 20 includes a down counter 16
1 is compared with the set value Y to turn on / off the gate 21 which outputs the output of the zero-cross detection circuit Zs of FIG. 1 to the preload terminal of the down counter 16. Further, the digital comparator 18 compares the output value of the up / down counter 15 with the set value input Z and inputs the result to the up / down control 14.

Further, the comparator 18 regulates the upper limit of the up / down counter 15 by comparing it with a set value Z.
This is because when the pulse period becomes extremely large, the choke coil L1 in FIG.
This is to prevent destruction due to flowing into the SFET Q1. That is, when the comparator 18 becomes active, the output d of the up / down control 14 is forcibly set to the down mode to avoid the above problem.

The operation timing will be described below with reference to FIGS. 1 to 3; the waveform indicated by Q-SIN indicates the current flowing through the coil L1 in FIG. First, when the value of the counter 16 represented by c in FIG. 2 is larger than the set value represented by X in the figure, the FET Q1 is turned on by the drive signal e of the drive circuit by the comparison of the comparator 19, whereby the line voltage is applied to the coil L1. Is applied and a current iL flows.
Next, the counter 16 counts down, and the set value X
When it gets smaller, the output of the comparator 19 is inverted, which turns off the FET Q1. This makes the coil L
The energy stored in 1 becomes the charging current of the capacitor C1 via the diode D1, and the current waveform becomes a triangular wave as shown in FIG. It is detected by the zero-cross detection circuit Zs of FIG. 1 whether or not the current flowing through the coil L1 has reached the zero level, a zero-cross signal a is generated at the time of falling, and the pre-load signal a.1 of the down counter 16 is supplied to the gate 21. Enter through.

The down counter 16 is forced to generate an underflow by the preload signal a.1. Even if the preload signal is not generated for some reason, the down counter 16 generates an underflow f when it attempts to down count below 0. When the underflow f is generated, the down counter 16 is sent via the F / F 17.
The signal h is input to, the output value of the up / down counter 15 is loaded into the down counter 16, and the FET is turned on again.
Q1 is turned on. The operation is repeated with the above as one cycle.

The digital comparator 20 also compares the down counter 16 with the set value input Y to open / close the gate 21. This functions to secure the minimum necessary off period even if the zero-cross signal a is generated at a timing other than the desired timing due to noise or the like. As a result, the current flowing through the coil becomes 0, and then the current flows again, and it is possible to make the average current waveform closer to a sine wave without causing an unnatural continuous state. Become.

On the other hand, the up / down control 1 in FIG.
Reference numeral 4 generates an up / down signal d and a clock clk from the output of the comparator 18 and the load signal h of the F / F 17, and outputs them to the up / down counter 15. This is because indefinite data that is in the process of changing may be loaded into the down counter 16 unless the up / down operation is performed at an appropriate timing synchronized with the load signal h. The up / down counter is switched and the up / down counter 15
Are driving. When the value of the up / down counter 15 increases, the ON time of the FET Q1 increases, and the maximum value i _{LP of the} current flowing through the coil increases as shown by the following equation, and decreases as it decreases.

I _LP = V / L * t _{on In other} words, in order to make the current waveform a sine wave, the up / down counter 15 is sequentially incremented if the connected load is constant until the amplitude becomes maximum. If there is a load change, the count value is increased or decreased corresponding to the load change, and then the reverse operation is performed until the zero cross, and this is repeated for each cycle of the switching frequency.

(Second Embodiment) FIG. 4 shows a circuit configuration diagram of the second embodiment. This FIG. 4 corresponds to FIG. 2 in the first embodiment.
PWM control circuit 3, CPU 30, ROM 31, RA
FIG. 7 is a simple block diagram of an embodiment example in which M32 and its associated digital circuit, a digital-analog converter and its associated analog circuit are integrated on the same chip. This integrated circuit facilitates downsizing and systemization of a power supply device that has a power factor improving effect.

(Third Embodiment) FIG. 5 shows a circuit diagram of the third embodiment (corresponding to FIG. 4). This embodiment is applied when systematized as in the second embodiment. In this case, the input voltage is changed by previously storing one cycle or half cycle of sine wave data in the ROM 31 or the RAM 32. Detection circuit Avin, voltage detection circuit A
In cv, the output voltage detection circuit 1, the level correction circuit 2, and the PWM control means 3, as shown in FIG. 6 corresponding to FIG. 2, an error amplifier and a multiplier at the input stage can be omitted, so that the cost is lower. It is possible to have a different configuration. The circuit operation is almost the same as that of the first embodiment, but the method of calculating the control value of the input current waveform is different from the case where the line synchronization circuit 33 is provided in FIG.

As shown in the timing chart for explaining the operation in FIG. 7, since the power distribution of the output system and its timing are managed by the CPU 30 by systematization, the power distribution is held in the ROM 31 in accordance with the load switching timing. The data w in which the peak value of the sine wave data is changed is generated, and the data w is detected by the input current detection circuit Acin.
The same control is performed by comparing with the analog comparator 13. Note that the sine wave data is synchronized with the line voltage and the calculation / data generation is performed.

(Fourth Embodiment) FIG. 8 shows the PWM of the fourth embodiment.
The circuit block diagram (equivalent figure of FIG. 6) of a control means is shown. This embodiment is intended to be applied to the case of performing higher precision control in the third embodiment. The third
In the embodiment, since the control system does not actually check the output voltage, it is controlled only at the voltage level according to the predetermined load, and the load is caused by the deterioration of the mechanical system accompanying the motor load and the load. If the level of changes, the control accuracy may be significantly deteriorated. In the fourth embodiment, control accuracy independent of changes in these control bodies can be obtained.

The circuit operation is almost the same as that of the third embodiment. As shown in FIG. 9 corresponding to FIG. 7, the predetermined comparison value w is corrected based on the value detected by the output voltage detection circuit. The only difference is that

In the fourth embodiment, as shown in FIG.
The detected value of the output voltage detection circuit 34 and the peak hold value of the output waveform from the CPU 30 are compared, the difference between the output voltage level in the initial state and the current state is calculated, and the value corresponding to the difference is stored in the variable gain amplifier. A level variable (correction) circuit 35 for outputting is provided to change the output level to the PWM control means 3. This enables correction even when the power level to the load changes due to deterioration as shown in FIG.

(Fifth Embodiment) FIG. 10 shows a circuit configuration diagram (corresponding to FIG. 1) of the fifth embodiment. This embodiment is applied to a case where the power factor improving effect is slightly reduced as compared with the circuit described above, but the cost is reduced and the size is reduced. That is, DC-D
It differs from the first embodiment only in that the switching element of the C converter and the switching element of the power factor improving means are combined into one. As a result, the frequency dividing circuit 6 and the driving circuit 5 shown in FIG. 1 are unnecessary, and the size can be further reduced. The other operations are almost the same.

(Sixth Embodiment) An inrush current limiting circuit according to an embodiment of the present invention will be described below with reference to the configuration diagram of FIG. 13; as shown, the inrush limiting circuit of this embodiment is The current detection circuit 41, the switching circuit SW1, the current control circuit 42, the comparison circuit 43, the OR circuit 44, the input voltage detection circuit 47, the capacitor terminal voltage detection circuit 48, and the electrolytic capacitor C1 are used. The following operation is performed by using the smoothing capacitor section of the line operated switching power supply.

The commercial frequency power source connected to the input power source terminal is rectified by the rectifying bridge (diodes D1 to D4), and then one end of the commercial frequency power source is connected to the capacitor C1 via the switching circuit SW1 and the current detection circuit 41 and the other end. Is connected to the switch element Q1 via the transformer T1.

As the operation of the switching power supply (DC-DC converter), the switching element Q1 is turned on and off to transfer power to the secondary side of the transformer T1 and rectify the AC output generated on the secondary side by the diode D5. Then, it is smoothed by a smoothing circuit composed of the choke coil L1 and the electrolytic capacitor C2 and supplied to the load. The smoothed DC output is detected by the voltage detection circuit 45, and the photo coupler PH
The constant voltage control of the output voltage is performed by inputting it to the PWM control circuit 46 via.

The operation of the control circuit of this embodiment is performed in parallel with the switching power supply control operation as follows; the current control circuit 42 is powered on as shown in the voltage / current waveform diagram of FIG. Then, by dividing the input voltage and using it as the auxiliary power supply of the current control circuit 42, the current control circuit 42 is activated at time t1. When the control circuit 42 is activated, the switching circuit S
W1 is turned on to charge the capacitor C1. SW1
When is turned on, a current flows into the capacitor C1 through the current detection circuit 41. The magnitude of this inflow current is detected by the current detection circuit 41 and sent to the current control circuit 42. As shown in FIG. 14, the current control circuit 42 has a certain width (hysteresis width) with respect to the reference value such that when the current value is 1H or more, the comparison level is 1L and when it is 1L or less, it is 1H again. The switching circuit SW1 is turned on / off so that the current flowing into the capacitor becomes constant.
Turn off control.

Thus, the capacitor C1 is charged with a constant current, and after a lapse of time t2, the terminal voltage VC1 of the capacitor C1.
However, when a certain voltage VC ₀ is reached, the voltage defined by the voltage divider circuit (not shown) connected to the positive side of the capacitor C1 reaches the power supply voltage value Vcp of the PWM control circuit 46, and the PWM
The control circuit 46 is activated and power supply to the load is started.

Further, the comparison circuit 43 causes the input voltage Vin
And the terminal voltage VC1 of the capacitor C1 are constantly monitored. When the input voltage Vin is lower than the terminal voltage VC1, the comparison circuit 43 outputs a Hi level to the OR circuit 44 to cancel the signal from the current control circuit 42. , The circuit operates so as to keep the switching circuit SW1 in the ON state, supplies power to the load, and the input voltage Vin is the terminal voltage VC.
When it is higher than 1, the comparison circuit 43 outputs a Low level to the OR circuit 44, and the switching circuit SW1 performs the constant current charging operation as described above by the signal of the current control circuit 42.

As described above, according to the present embodiment, in the capacitor input type rectifier circuit, it is possible to suppress the inrush current when the power is turned on, and by comparing the input voltage and the terminal voltage of the capacitor, the re-entry is performed. It is possible to suppress the flow of current. It is also possible to arbitrarily change the startup time by changing the reference value for current control.

The switching circuit SW1 described in the present embodiment is a bidirectional switching element or a circuit which is a combination of switching elements and is capable of bidirectional current control.

(Seventh Embodiment) Next, FIG. 15 shows a circuit diagram of a seventh embodiment. This circuit configuration is the same as that of the sixth embodiment, except that the configuration of the current control circuit 42 is a combination of a switching element such as FET and a diode.

As a result, power is supplied from the capacitor to the load if the input voltage becomes lower than the terminal voltage of the capacitor C1 without constantly comparing the terminal voltage of the capacitor C1 with the input voltage to switch the control signal. become,
While performing the same circuit operation as that of the sixth embodiment, the comparison circuit 4
3, the OR circuit 44 can be deleted, and the circuit configuration can be simplified.

(Eighth Embodiment) FIG. 16 shows a circuit configuration path of an eighth embodiment. In the circuit shown in FIG. 13 of the sixth embodiment, the inrush current is suppressed, but another drawback of the capacitor input type rectification system, that is, the reduction of the input power factor due to the current flowing only near the voltage peak. The problem of current waveform distortion cannot be solved. As an improvement measure for that, the switching circuit SW1 inserted in series with the capacitor C1 is not always operated at the time of start-up or when the capacitor terminal voltage VC1 becomes lower than the input voltage Vin, but always performs the switching operation. By doing so, the problem is solved.

The circuit configuration is almost the same as that of the seventh embodiment, and a diode Dc is added between the connection line between the transformer T1 and the switch element and the connection line between the capacitor C1 and the power supply input line to control the current control circuit 42. The difference is that the method is changed from the constant current control method to the current limiting method, and that a low-pass filter is inserted in the power supply input line.

The operation will be described below with reference to FIG. 16 and FIG. 17 of the voltage / current waveform diagram thereof. As shown in FIG. 16, the switch element Qc outputs a PWM control signal for performing constant voltage control to an inverter circuit. It is driven by inputting via 49. As a result, when the switch element Q1 is on, Qc is in an off period, and when the switch element Q1 is off, Qc is in an on period. Thus, the input current waveform is short-circuited in the switch element Q1. By repeating the opening, a current corresponding to the input voltage will flow, as shown in FIG. Further, the terminal voltage of the capacitor C1 is charged by the energy stored in the self-inductance of the transformer T1 and the input voltage when the power source is short-circuited by the switch element Q1. That is, it operates like a step-up chopper, and the voltage waveform is a superposition of the harmonic voltage on the input voltage waveform as shown in FIG.

However, since the voltage applied to the capacitor C1 is relatively larger than usual, the inrush current at the time of startup is still large. Therefore, the current control circuit 42 turns off the pulse of the inversion PWM control signal at that time when the value of the charging current detected by the current detection circuit 41 and flowing into the capacitor becomes larger than the set value, and the PWM control circuit 46 outputs the pulse. The pulse-by-pulse control is performed such that each pulse is controlled to be kept off until one triangular wave output from the triangular wave generation circuit ends.

With this control circuit, the inrush current to the capacitor at the time of startup can be suppressed to a certain constant value, and the stress on the input stage element such as the rectifying diode can be reduced.

When the capacitor C1 is sufficiently charged, the input current waveform becomes as shown in FIG. 17 (b) by the control as described above, which is due to the low-pass signal inserted in the input line. The filter makes it close to a sine wave. As described above, according to this method, the circuit configuration is simple, and it is possible to remove the harmonic component and improve the input power factor by improving the input current waveform.

(Ninth Embodiment) An embodiment of the rectifier circuit according to the present invention will be described below with reference to the circuit diagram of FIG. 19; in FIG. 19, the same (corresponding) constituent elements as those in FIG. Are denoted by the same reference numerals. Input terminals 51 and 52 are terminals to which an AC voltage is applied. The input terminal 51 is connected to the AC terminal of the rectifier stack RC1 and the AC terminal of the voltage detection circuit 57, and the input terminal 52 is connected to the other AC terminal of the rectifier stack RC1 and the other AC terminal of the voltage detection circuit 57. .

The voltage detection circuit 57 includes a rectifier stack RC.
71, CR circuit (resistors R71 to R72, capacitor C7
1), voltage dividing resistance circuit (R73 to R74), comparator Q71
Composed of a capacitor C for detecting the input AC voltage value
Compare with the terminal voltage of 1.

The positive terminal of the rectifier stack RC1 is connected to one terminal of the resistor R1 and one contact of the electromagnetic contactor MC1, and the other terminal of the resistor R1 and the electronic contactor M.
The other contact of C1 is connected to the smoothing capacitor C1 and the output terminal 53. The negative terminal of the rectifier stack RC1 is connected to the output terminal 54. The output of the voltage detection circuit 57 is connected to the drive circuit 56, and the drive circuit 56 drives the electromagnetic contactor MC1.

Next, the operation of the circuit shown in FIG. 19 will be described. When AC power is connected to the input power terminals 51, 52,
It is converted into a pulsating flow by the rectifying action of the rectifier stack RC1. At this time, the contact of the electromagnetic contactor MC1 is broken, the capacitor C1 is precharged by the resistor R1, and the voltage gradually rises. The voltage detection circuit 57 includes a capacitor C1.
Is compared with the input AC voltage, the preliminary charging is repeated and the voltage of the capacitor C1 rises, and when the voltage difference reaches a predetermined value or less, it is determined that the preliminary charging is completed and a signal is sent to the drive circuit 56. Send a signal.

The drive circuit 56 receives the signal from the voltage detection circuit 57 and drives the electromagnetic contactor MC1 to make contacts. When the contact of the electromagnetic contactor MC1 is made, the resistor R1 is short-circuited and the pre-charging circuit is ignored. Supplied to the load.

The voltage detection circuit 57 functions as a peak voltage detection and effective value voltage detection circuit by appropriately setting the constant of the CR circuit. Although the full-wave rectifier stack is used as the rectifying element, a half-wave rectifying element such as a single diode may be used.

As described above, when the smoothing capacitor is in the uncharged state, it is precharged by the precharging circuit, and when the precharging is completed, the precharging circuit is disconnected to suppress the inrush current at power-on. While rectifying and smoothing, DC power can be obtained.

(Tenth Embodiment) FIG. 20 shows a view corresponding to FIG. 19 of another embodiment of the rectifier circuit configuration. 20, the same (corresponding) constituent elements as those in FIG. 19 are designated by the same reference numerals, and 51 and 52 are input terminals and terminals to which an AC voltage is applied. The input terminal 51 is a rectifier stack RC
One AC terminal is connected to the AC terminal of the voltage detection circuit 57, and the input terminal 52 is connected to the other AC terminal of the rectifier stack RC1 and the other AC terminal of the voltage detection circuit 57.

The voltage detection circuit 57 includes a rectifier stack RC.
71, CR circuit (resistors R71 to R72, capacitor C7
1), voltage dividing resistance circuit (R73 to R74), comparator Q71
Composed of a capacitor C for detecting the input AC voltage value
Compare with the terminal voltage of 1. The output of the voltage detection circuit 57 is
It is connected to the AND circuit 58.

The positive terminal of the rectifier stack RC1 is connected to one terminal of the resistor R1 and one contact of the electromagnetic contactor MC1, and the other terminal of the resistor R1 and the electromagnetic contactor M.
The other contact of C1 is connected to the smoothing capacitor C1 and the output terminal 53. Also, the rectifier stack RC1
The negative terminal of is connected to the output terminal 54.

A voltage detection circuit 55 is connected in parallel with the capacitor C1 in order to detect the terminal voltage of the capacitor C1. The voltage detection circuit 55 is composed of a voltage dividing resistance circuit, a comparator and the like, and detects the terminal voltage of the capacitor C1. The output of the voltage detection circuit 55 is connected to the AND circuit 58, and the AND circuit 58 takes the logical product of the outputs of the voltage detection circuit 55 and the voltage detection circuit 57. The output of the AND circuit 58 is connected to the drive circuit 56, and the drive circuit 56
Drives the electromagnetic contactor MC1.

Next, the operation of the circuit of FIG. 20 will be described. When an AC power supply is connected to the input power supply terminals 51 and 52, it is converted into a pulsating flow by the rectifying action of the rectifier stack RC1. At this time, the contact of the electromagnetic contactor MC1 is broken, the capacitor C1 is precharged by the resistor R1, and the voltage gradually rises. When the precharge is repeated and the voltage of the capacitor C1 rises and reaches a predetermined voltage or more, the voltage detection circuit 5
5 determines that the preliminary charging is completed and sends a signal to the AND circuit 58.

The voltage detection circuit 57 compares the voltage of the capacitor C1 with the input AC voltage and repeats the preliminary charging. When the voltage of the capacitor C1 rises and the voltage difference reaches a predetermined value or less, the preliminary charging is performed. When it is judged to be completed, the signal is sent to the AND circuit 58. The AND circuit 58 takes the logical product of the two signals and sends the signal to the drive circuit 56.

The drive circuit 56 receives the signal from the AND circuit 58 and drives the electromagnetic contactor MC1 to make contacts. When the contact of electromagnetic contactor MC1 is made, resistance R1
Is short-circuited and the pre-charge circuit is ignored, the rectifier stack RC1 and the smoothing capacitor C1 operate as a rectifying and smoothing circuit, and DC power is supplied to a predetermined load by the output terminals 53 and 54.

Similar to the ninth embodiment, the voltage detection circuit 5
7 functions as a peak voltage detection and effective value voltage detection circuit by appropriately setting the constant of the CR circuit. Although the full-wave rectifier stack is used as the rectifying element, a half-wave rectifying element such as a single diode may be used.

(Eleventh Embodiment) Another embodiment of the rectifying device will be described. FIG. 21 shows a circuit configuration diagram (corresponding to FIGS. 19 and 20) of the eleventh embodiment. In FIG. 21, the same (corresponding) components as those in FIGS. 19 and 20 are represented by the same reference numerals, and the duplicated description will be omitted. The signal terminal 59 is connected to the drive circuit 56 via the transistor Q1. The drive circuit 56 outputs a signal synchronized with the operation of the electromagnetic contactor MC1 to the signal terminal 59. Transistor Q
Reference numeral 1 is a buffer amplification transistor that is added as necessary depending on the signal level of the circuit connected to the signal terminal 59. Other connections and operations are the same as those in the ninth embodiment.

(Twelfth Embodiment) Further, another embodiment of the rectifier will be described. FIG. 22 shows the circuit configuration diagram (equivalent to FIGS. 19 to 21). In FIG. 22, the same (corresponding) symbols as those described above are similarly omitted from redundant description.
The DC-DC converter 60 is a voltage stabilizing circuit,
A control terminal is connected to the drive circuit 56. Drive circuit 56
Is a DC-D signal synchronized with the operation of the electromagnetic contactor MC1.
Output to the C converter 60, and the DC-DC converter 60
Are controlled in synchronization with the electromagnetic contactor MC1. Other connections and operations are the same as those in the ninth embodiment.

[0089]

As described above, according to the present invention, (1) in a switching regulator using a capacitor input type rectification system, harmonic noise and input force generated by current flowing only near a voltage peak. The problem of a decrease in the rate can be improved, and a desired output voltage can be obtained as a switching regulator. Further, the control circuit can be digitized to be integrated, and the system configuration can be facilitated. Furthermore, when configured as a system, it can be changed to a simpler circuit configuration,
An inexpensive and compact power supply device can be provided.

[0090]

[0091]

[0092]

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a power supply device according to a first embodiment.

FIG. 2 is a circuit configuration diagram of the PWM control means of the first embodiment.

FIG. 3 is an operation timing chart of the first embodiment.

FIG. 4 is a circuit configuration diagram of a second embodiment.

FIG. 5 is a view corresponding to FIG. 4 of the third embodiment.

FIG. 6 is a diagram corresponding to FIG. 2 of the third embodiment.

FIG. 7 is a timing chart for explaining the operation of the third embodiment.

FIG. 8 is a view corresponding to FIG. 6 of the fourth embodiment.

FIG. 9 is a view corresponding to FIG. 7 of the fourth embodiment.

FIG. 10 is a view corresponding to FIG. 1 of the fifth embodiment.

FIG. 11 is a circuit configuration diagram of an example of a conventional power supply device.

FIG. 12: Example of input voltage / current waveform diagram by circuit method

FIG. 13 is a configuration diagram of an inrush power supply limiting circuit according to a sixth embodiment.

FIG. 14 is a voltage / current waveform diagram of the sixth embodiment.

FIG. 15 is a circuit configuration diagram of a seventh embodiment.

FIG. 16 is a circuit configuration diagram of an eighth embodiment.

FIG. 17 is a voltage / current waveform diagram of the eighth embodiment.

FIG. 18 Example of conventional inrush current prevention circuit

FIG. 19 is a circuit diagram of a rectifying device circuit according to a ninth embodiment.

FIG. 20 is a circuit configuration diagram of a tenth embodiment.

FIG. 21 is a circuit configuration diagram of an eleventh embodiment.

FIG. 22 is a circuit configuration diagram of a twelfth embodiment.

FIG. 23 shows a conventional rectifier circuit configuration example.

[Explanation of symbols]

1 output detection circuit 2 level correction circuit 3 PWM control means 4 drive circuit 5 drive circuit 6 frequency divider circuit 7 clock Acin input current detection circuit Zs zero cross detection circuit Avin input voltage waveform detection circuit Acv voltage detection circuit DC1 rectifier diode bridges D1 to D4 rectifier diodes C1, Co, C ₂ smoothing capacitor T1 transformer D3, Dc wheeling diode Q1, Q2, Qc switching element L1, CH1 choke coil 41 current detecting circuit 42 commutation control circuit 43 comparison circuit 44 OR circuit 45 a voltage detection circuit SW1 bidirectional Switch circuit D5, D6 Diode PH Photo coupler 51, 52 Input terminal 53, 54 Output terminal 55 Voltage detection circuit 56 Drive circuit 57 Voltage detection circuit 58 AND circuit 59 Signal terminal 60 DC-DC converter Q71 Comparator RC1, RC71 Rectification Stack R1, R2, R3 resistors R71, R72, R73, R74 resistors

─────────────────────────────────────────────────── --Continued from the front page (56) Reference JP 5-91731 (JP, A) JP 4-127875 (JP, A) JP 5-184141 (JP, A) JP 4- 217867 (JP, A) JP 5-111246 (JP, A) JP 5-219726 (JP, A) JP 5-70192 (JP, A) JP 1-136560 (JP, A) Actual Kaihei 5-70192 (JP, U) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H02M 3/00-3/44 H02M ^7/ 00-7/40

Claims (4)

(57) [Claims] 1. A capacitor input type rectification converter is provided.
Switching with single or multiple voltage output systems
It is a power supply and the input current waveform is sinusoidal and the power factor is
A power factor improving means for improving and a single or predetermined voltage.
And a DC-DC converter for obtaining a plurality of outputs,
The power factor improving means and the DC-DC converter have the same P
The WM control means is configured to perform feedback control.
In the power supply, the PWM control means, and level correction means for correcting the voltage level detected by the output voltage detection means by the detection value of the output voltage detection unit of the capacitor, the output value of said level correcting means An error amplifier that compares with a reference value,
An analog comparator that multiplies the output of this error amplifier and the line voltage waveform detected by the input voltage waveform detection means by a multiplier and compares the output with the current level detected by the input current detection means, and this analog comparator If you select a count up / down by the output of the br /> regulator
And A-up / down counter, the capacitor input rectifier
A second counter for loading the output value of the up / down counter by a zero-cross signal from a zero-cross detection circuit that detects a zero-cross from a waveform of a current detection winding of a choke coil provided in a converter or an own over-count signal And a first digital comparator for comparing the output value of the second counter with a predetermined digital value, and the output of the first digital comparator
Second to disable / enable the drive circuits for driving the switching element intermittently, comparing the second counter output and a predetermined digital value and the second counter load operation by the zero-cross signal both ends of the capacitor by A third digital comparator for comparing the output value of the up / down counter with a predetermined digital value to inhibit / permit the count-up operation of the up / down counter.
You characterized in that the and a digital comparator
Power supply. 2. The power supply device according to claim 1, wherein the PWM control means, CPU, ROM, RAM, digital circuits and digital-analog converters associated therewith, and analog circuits associated therewith are provided on the same chip. power supplies characterized in that integrated to the integrated circuit. 3. The power supply device according to claim 2, wherein:
PWM controller power supplies you characterized in that only a digital control. 4. A power supply device according to claim 1, wherein the power factor correction unit and the DC-DC converter to that power supplies characterized by being configured to cover the same elements switching elements.