JP6883972B2 - 半導体装置、電子部品および電子機器 - Google Patents

半導体装置、電子部品および電子機器 Download PDF

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Publication number
JP6883972B2
JP6883972B2 JP2016208295A JP2016208295A JP6883972B2 JP 6883972 B2 JP6883972 B2 JP 6883972B2 JP 2016208295 A JP2016208295 A JP 2016208295A JP 2016208295 A JP2016208295 A JP 2016208295A JP 6883972 B2 JP6883972 B2 JP 6883972B2
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transistor
oxide semiconductor
circuit
film
wiring
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JP2017085565A (ja
JP2017085565A5 (https=
Inventor
宗広 上妻
宗広 上妻
黒川 義元
義元 黒川
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90Masterslice integrated circuits
    • H10D84/903Masterslice integrated circuits comprising field effect technology
    • H10D84/907CMOS gate arrays
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748Structural details of configuration resources
    • H03K19/1776Structural details of configuration resources for memories
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003Modifications for increasing the reliability for protection
    • H03K19/00315Modifications for increasing the reliability for protection in field-effect transistor circuits
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
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    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
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    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6704Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
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    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/674Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
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    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/875Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being semiconductor metal oxide, e.g. InGaZnO
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    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H10D86/215Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI comprising FinFETs
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    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
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    • H10D86/40Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441Interconnections, e.g. scanning lines
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    • H10D86/40Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
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    • H10D86/40Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/207Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics
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    • H10D84/90Masterslice integrated circuits
    • H10D84/903Masterslice integrated circuits comprising field effect technology
    • H10D84/907CMOS gate arrays
    • H10D84/909Microarchitecture
    • H10D84/935Degree of specialisation for implementing specific functions
    • H10D84/937Implementation of digital circuits
    • H10D84/938Implementation of memory functions
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    • H10D84/90Masterslice integrated circuits
    • H10D84/903Masterslice integrated circuits comprising field effect technology
    • H10D84/907CMOS gate arrays
    • H10D84/968Macro-architecture
    • H10D84/974Layout specifications, i.e. inner core regions
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    • H10D84/90Masterslice integrated circuits
    • H10D84/903Masterslice integrated circuits comprising field effect technology
    • H10D84/907CMOS gate arrays
    • H10D84/968Macro-architecture
    • H10D84/974Layout specifications, i.e. inner core regions
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    • H10D84/90Masterslice integrated circuits
    • H10D84/903Masterslice integrated circuits comprising field effect technology
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    • H10D84/991Latch-up prevention
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    • H10W90/736Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Microelectronics & Electronic Packaging (AREA)
JP2016208295A 2015-10-30 2016-10-25 半導体装置、電子部品および電子機器 Expired - Fee Related JP6883972B2 (ja)

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Application Number Priority Date Filing Date Title
JP2015214977 2015-10-30
JP2015214977 2015-10-30

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JP2017085565A JP2017085565A (ja) 2017-05-18
JP2017085565A5 JP2017085565A5 (https=) 2019-11-28
JP6883972B2 true JP6883972B2 (ja) 2021-06-09

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US (1) US10504919B2 (https=)
JP (1) JP6883972B2 (https=)
KR (1) KR102643895B1 (https=)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8736315B2 (en) * 2011-09-30 2014-05-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US10115769B1 (en) * 2017-06-13 2018-10-30 Macronix International Co., Ltd. Resistive random access memory device and method for manufacturing the same
WO2020128713A1 (ja) * 2018-12-20 2020-06-25 株式会社半導体エネルギー研究所 単極性トランジスタを用いて構成された論理回路、および、半導体装置

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WO2011089808A1 (en) 2010-01-20 2011-07-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
KR101889383B1 (ko) 2011-05-16 2018-08-17 가부시키가이샤 한도오따이 에네루기 켄큐쇼 프로그래머블 로직 디바이스
US9673823B2 (en) 2011-05-18 2017-06-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of driving semiconductor device
US8779799B2 (en) 2011-05-19 2014-07-15 Semiconductor Energy Laboratory Co., Ltd. Logic circuit
US8581625B2 (en) 2011-05-19 2013-11-12 Semiconductor Energy Laboratory Co., Ltd. Programmable logic device
US9762246B2 (en) 2011-05-20 2017-09-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device with a storage circuit having an oxide semiconductor
JP5820336B2 (ja) 2011-05-20 2015-11-24 株式会社半導体エネルギー研究所 半導体装置
JP5892852B2 (ja) * 2011-05-20 2016-03-23 株式会社半導体エネルギー研究所 プログラマブルロジックデバイス
JP6125850B2 (ja) 2012-02-09 2017-05-10 株式会社半導体エネルギー研究所 半導体装置及び半導体装置の作製方法
US9230683B2 (en) 2012-04-25 2016-01-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and driving method thereof
US9654107B2 (en) 2012-04-27 2017-05-16 Semiconductor Energy Laboratory Co., Ltd. Programmable LSI
JP6228381B2 (ja) 2012-04-30 2017-11-08 株式会社半導体エネルギー研究所 半導体装置
US8975918B2 (en) 2012-05-01 2015-03-10 Semiconductor Energy Laboratory Co., Ltd. Lookup table and programmable logic device including lookup table
WO2013164958A1 (en) 2012-05-02 2013-11-07 Semiconductor Energy Laboratory Co., Ltd. Programmable logic device
KR102059218B1 (ko) 2012-05-25 2019-12-24 가부시키가이샤 한도오따이 에네루기 켄큐쇼 프로그래머블 로직 디바이스 및 반도체 장치
KR102112364B1 (ko) 2012-12-06 2020-05-18 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
JP6368155B2 (ja) 2013-06-18 2018-08-01 株式会社半導体エネルギー研究所 プログラマブルロジックデバイス
TWI633650B (zh) * 2013-06-21 2018-08-21 半導體能源研究所股份有限公司 半導體裝置
JP6352070B2 (ja) * 2013-07-05 2018-07-04 株式会社半導体エネルギー研究所 半導体装置
WO2015118436A1 (en) * 2014-02-07 2015-08-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, device, and electronic device

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KR20170051284A (ko) 2017-05-11
JP2017085565A (ja) 2017-05-18
US20170125440A1 (en) 2017-05-04
KR102643895B1 (ko) 2024-03-05
US10504919B2 (en) 2019-12-10

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