JP6883478B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP6883478B2
JP6883478B2 JP2017121996A JP2017121996A JP6883478B2 JP 6883478 B2 JP6883478 B2 JP 6883478B2 JP 2017121996 A JP2017121996 A JP 2017121996A JP 2017121996 A JP2017121996 A JP 2017121996A JP 6883478 B2 JP6883478 B2 JP 6883478B2
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Prior art keywords
semiconductor chip
spacer
substrate
bonding material
semiconductor
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JP2017121996A
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JP2019009208A (ja
Inventor
史朗 岡田
史朗 岡田
森　健太郎
健太郎 森
一浩 千葉
一浩 千葉
嘉国 五島
嘉国 五島
信介 鍋屋
信介 鍋屋
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Nuflare Technology Inc
Toshiba Electronic Devices and Storage Corp
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Nuflare Technology Inc
Toshiba Electronic Devices and Storage Corp
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Priority to JP2017121996A priority Critical patent/JP6883478B2/ja
Priority to TW107118619A priority patent/TWI678780B/zh
Priority to US16/009,753 priority patent/US10607908B2/en
Priority to KR1020180070280A priority patent/KR102052484B1/ko
Publication of JP2019009208A publication Critical patent/JP2019009208A/ja
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Description

本発明の実施形態は、半導体装置に関する。
複数の荷電粒子ビームを偏向するために、荷電粒子ビームを通過させる貫通孔を複数個有する半導体チップを備えた偏向器が用いられる。各々の貫通孔が１対の電極を有し、電極間に印加される電界により各々の荷電粒子ビームを独立して偏向する。
半導体チップは、例えば、貫通孔に対応する開口部を有する基板上に接合される。複数の荷電粒子ビームが貫通孔を通過するように、貫通孔を高い位置精度で配置することが要求される。
特開２００４−２８２０３８号公報
本発明が解決しようとする課題は、高い位置精度で配置された貫通孔を有する半導体チップを備えた半導体装置を提供することにある。
本発明の一態様の半導体装置は、複数の貫通孔を有する領域を含む半導体チップと、前記領域よりも大きい第１の開口部を有し、樹脂又はセラミックスを含む基板と、前記半導体チップと前記基板との間に設けられ、前記領域よりも大きい第２の開口部を有するスペーサと、前記半導体チップと前記スペーサとの間に設けられた第１の接合材と、前記スペーサと前記基板との間に設けられた第２の接合材と、を備え、前記スペーサの熱膨張係数は前記基板の熱膨張係数よりも小さい。
実施形態の半導体装置の模式図。 実施形態の半導体チップの一部の拡大模式図。 実施形態の第１の接合材の配置パターンを例示する上面図。 比較形態の半導体装置の模式図。 比較形態の半導体装置の問題点の説明図。 比較形態の半導体装置の問題点の説明図。 実施形態の半導体装置の作用及び効果の説明図。 実施形態の半導体装置の作用及び効果の説明図。
本明細書中、同一又は類似する部材については、同一の符号を付し、重複する説明を省略する場合がある。
本明細書中、部品等の位置関係を示すために、図面の上方向を「上」、図面の下方向を「下」と記述する場合がある。本明細書中、「上」、「下」の概念は、必ずしも重力の向きとの関係を示す用語ではない。
実施形態の半導体装置は、複数の貫通孔を有する領域を含む半導体チップと、上記領域よりも大きい第１の開口部を有し、樹脂又はセラミックスを含む基板と、上記半導体チップと上記基板との間に設けられ、上記領域よりも大きい第２の開口部を有するスペーサと、上記半導体チップと上記スペーサとの間に設けられた第１の接合材と、上記スペーサと上記基板との間に設けられた第２の接合材と、を備える。
図１は、実施形態の半導体装置の模式図である。図１（ａ）は断面図、図１（ｂ）は上面図である。図１（ａ）は、図１（ｂ）のＡＡ’断面図である。
実施形態の半導体装置は、マルチビーム方式の電子ビーム描画装置に用いられる偏向器１００である。マルチビーム方式の電子ビーム描画装置は、複数の電子ビームを用いて試料にパターンを描画する。
偏向器１００は、複数の電子ビームの各々を個別に偏向する機能を備える。例えば、偏向器１００と電子ビームを遮蔽するアパーチャとを組み合わせることによって、各々の電子ビームの試料への照射と非照射を独立に制御することができる。
図１に示すように、偏向器１００（半導体装置）は、半導体チップ１０、基板２０、スペーサ３０、第１の接合材４０、第２の接合材４２を備える。スペーサ３０は、半導体チップ１０と基板２０との間に設けられる。半導体チップ１０とスペーサ３０との間に、第１の接合材４０が設けられる。スペーサ３０と基板２０との間に、第２の接合材４２が設けられる。
半導体チップ１０には、中央部に複数の貫通孔１２を有する領域１４が設けられる。貫通孔１２のそれぞれを、電子ビームが通過する。図１（ｂ）では、横９個、縦９個の計８１個の貫通孔１２がアレイ状に配置される場合を例示しているが、貫通孔１２の個数及び配置の形状は、上記形態に限定されるものではない。
図２は、実施形態の半導体チップ１０の一部の拡大模式図である。図２は、領域１４の一部の拡大図である。図２（ａ）が断面図、図２（ｂ）が上面図である。図２（ａ）は、図２（ｂ）のＢＢ’断面図である。
貫通孔１２は半導体層１１を貫通する。半導体層１１は、例えば、シリコン層である
半導体層１１上に、貫通孔１２を挟んで、１対の制御電極１３ａ、１３ｂが設けられる。さらに、制御電極１３ａに電圧を印加するための電極配線層１５ａと、制御電極１３ｂに電圧を印加するための電極配線層１５ｂとが設けられる。電極配線層１５ａ、１５ｂは、半導体層１１表面に設けられても、半導体層１１を構成する内部の層として設けられてもよい。制御電極１３ａと制御電極１３ｂとの間に印加する電圧を制御することにより、貫通孔１２を通過する電子ビームを偏向制御する。
図１（ｂ）に示すように、半導体チップ１０には、制御回路１６が設けられる。制御回路１６は、例えば、１対の制御電極１３ａ、１３ｂに印加する電圧を制御する機能を備える。制御回路１６は、例えば、半導体層１１に形成された複数のトランジスタを含む回路で構成される。制御回路１６と制御電極１３ａ、１３ｂは、例えば、電極配線層１５ａ、１５ｂにより電気的に接続される。例えば、個々の制御電極１３ａ、１３ｂに制御回路を設けても構わない。
半導体チップ１０は、複数の第１の電極パッド１７を備える。第１の電極パッド１７は、半導体層１１上に設けられる。第１の電極パッド１７は、半導体チップ１０に外部から電圧を印加するために設けられる。第１の電極パッド１７は、例えば、制御回路１６や制御電極１３ａ、１３ｂに電気的に接続される。
半導体チップ１０の厚さは、所望のアスペクト比の貫通孔１２を形成可能な厚さである必要がある。半導体チップ１０の厚さは、例えば、半導体チップ１０に照明される電子ビームが縮小光学系を構成する場合に貫通孔１２を斜めに通過できるよう、非常に薄くする必要がある。半導体チップ１０の厚さは、例えば、１０μｍ以上５００μｍ以下である。なお、照射エリアが狭くなれば、より半導体チップ１０の厚さを薄くすることも可能である。
基板２０は、例えば、回路基板である。基板２０は、半導体チップ１０を支持する機能を備える。また、基板２０は、偏向器１００の外部から印加される電圧を半導体チップに伝達する機能を備える。
基板２０は、例えば、樹脂を含むプリント基板である。また、基板２０は、例えば、セラミックスを含むセラミックス基板である。
基板２０には、例えば、図示しない配線層が設けられる。基板２０の表面は、電子ビーム照射によるチャージアップを回避するため、例えば、金メッキなどの導電性物質で被覆される。
基板２０には、第１の開口部２１が設けられる。第１の開口部２１を複数の電子ビームが通過する。
図１（ｂ）に示すように、第１の開口部２１は、領域１４よりも大きい。半導体チップ１０の上面から見た場合に、第１の開口部２１は領域１４の周囲を囲むように設けられる。図１（ａ）に示すように、第１の開口部２１の径（ｄ１）は、領域１４の径（ｄ０）よりも大きい。
基板２０は、上面に複数の第２の電極パッド２２を備える。第２の電極パッド２２は、半導体チップ１０の第１の電極パッド１７とボンディングワイヤ５０により接続される。ボンディングワイヤ５０は、例えば、金ワイヤである。
スペーサ３０は、偏向器１００の製造時に半導体チップ１０に印加される応力を緩和する機能を備える。スペーサ３０は、熱膨張係数が半導体チップ１０に近く、圧縮強度が高いものが好ましい。スペーサ３０は、例えば、半導体又は絶縁体である。スペーサ３０は、例えば、シリコン、炭化珪素、又は、石英ガラスである。スペーサ３０の表面は、電子ビーム照射によるチャージアップを回避するため、例えば、金メッキなどの導電性物質で被覆される。
スペーサ３０には、第２の開口部３１が設けられる。第２の開口部３１を複数の電子ビームが通過する。
図１（ｂ）に示すように、第２の開口部３１は、領域１４よりも大きい。第２の開口部３１の面積は、領域１４の面積よりも大きい。また、例えば、第２の開口部３１は、領域１４より大きく、第１の開口部２１よりも小さい。第２の開口部３１の面積は、領域１４の面積より大きく、第１の開口部２１の面積よりも小さい。半導体チップ１０の上面から見た場合に、第２の開口部３１は領域１４の周囲を囲むように設けられる。また、第１の開口部２１は第２の開口部３１の周囲を囲むように設けられる。第２の開口部３１の端部は、領域１４の端部と第１の開口部２１の端部との間にある。
図１（ａ）に示すように、第２の開口部３１の径（ｄ２）は、領域１４の径（ｄ０）よりも大きい。また、例えば、第２の開口部３１の径（ｄ２）は、第１の開口部２１の径（ｄ１）よりも小さい。
スペーサ３０の熱膨張係数は、例えば、基板２０の熱膨張係数よりも小さい。スペーサ３０の熱膨張係数は、例えば、６ｐｐｍ／Ｋ以下である。
また、スペーサ３０の厚さは、半導体チップ１０の厚さよりも厚い。スペーサ３０の厚さは、例えば、０．２ｍｍ以上５ｍｍ以下である。スペーサ３０の外周の一辺の長さは、例えば、２０ｍｍ以上５０ｍｍ以下である。
図１（ａ）に示すように、例えば、スペーサ３０と半導体チップ１０との間の少なくとも一部に空隙６０が存在する。空隙６０の幅、すなわち、スペーサ３０と半導体チップ１０との間の距離は、例えば、２μｍ以上１００μｍ以下である。
半導体チップ１０とスペーサ３０とは、第１の接合材４０により接合される。第１の接合材４０の材料は、例えば、導電性材料である。第１の接合材４０は、例えば、銀ペースト、又は、はんだである。第１の接合材４０は、例えば、２００℃以下の硬化温度又は融点を有する材料である。第１の接合材４０の厚さは、例えば、１μｍ以上１００μｍ以下である。
図３は、実施形態の第１の接合材４０の配置パターンを例示する上面図である。第１の接合材４０は、例えば、図３（ａ）に示すように、スペーサ３０の上面に第２の開口部３１の周囲を囲むように連続して設けられる。また、第１の接合材４０は、例えば、図３（ｂ）に示すように、複数の部分に分割して設けられる。
スペーサ３０と基板２０とは、第２の接合材４２により接合される。第２の接合材４２の材料は、例えば、導電性材料である。第２の接合材４２は、例えば、銀ペースト、又は、はんだである。第２の接合材４２は、例えば、２００℃以下の硬化温度又は融点を有する材料である。第２の接合材４２の厚さは、例えば、１μｍ以上１００μｍ以下である。
次に、実施形態の半導体装置の作用及び効果について説明する。
複数の電子ビームを偏向する偏向器では、複数の電子ビームが半導体チップに設けられた貫通孔を通過するように、貫通孔を高い位置精度で配置することが要求される。特に、貫通孔の数が増大したり、偏向器のサイズが小さくなったりすると、更に高い位置精度で配置することが要求される。例えば、偏向器の製造途中の熱工程を経ることで、半導体チップが応力によって反り、貫通孔の位置精度が低下するおそれがある。
図４は、比較形態の半導体装置の模式図である。図４（ａ）は断面図、図４（ｂ）は上面図である。図４（ａ）は、図４（ｂ）のＣＣ’断面図である。
比較形態の半導体装置は、実施形態と同様、マルチビーム方式の電子ビーム描画装置に用いられる偏向器９００である。偏向器９００は、スペーサ３０を備えない点以外は、実施形態の偏向器１００と同様である。半導体チップ１０と基板２０とは、第２の接合材４２により接合される。
図５は、比較形態の半導体装置の問題点の説明図である。図５は、比較形態の半導体装置の模式断面図である。
図５（ａ）は、基板２０に半導体チップ１０を載置した後、接合及びワイヤボンディングに伴う熱工程を経る前の図である。図５（ｂ）は、接合及びワイヤボンディングに伴う熱工程を経た後の図である。
比較形態の偏向器９００では、図５（ｂ）に示すように、熱工程を経た後、応力により半導体チップ１０が大きく反る。半導体チップ１０の反りは、半導体チップ１０と基板２０との熱膨張係数との差に起因すると考えられる。半導体チップ１０の反りは、熱工程における降温時に、半導体チップ１０と基板２０との熱収縮による変位量が異なることで生ずると考えられる。
なお、図４（ａ）は、熱工程による半導体チップ１０の反りを無視した理想的な状態の断面図である。
図６は、比較形態の半導体装置の問題点の説明図である。図６に示すように、半導体チップ１０が反ることにより、貫通孔１２の横方向の位置が変位する。なお、他の貫通孔についても同様に変位する。実線が変位前の貫通孔１２、点線が変位後の貫通孔１２である。電子ビームのサイズは貫通孔１２の径より小さい。このため、例えば、半導体チップ１０の中心部では変位があっても変位が小さいため、電子ビームは貫通孔１２を通過することができる。しかし、半導体チップ１０の外周部では変位が大きいため、電子ビームが対応する貫通孔１２の外側に照射されることになり、電子ビームの一部が貫通孔を通過できなくなるという問題が生ずる。特に、上述したように半導体チップ１０に照明される電子ビームが縮小光学系を構成する場合には、電子ビームは貫通孔１２を斜めに通過するため、更に通過のマージンが小さくなる。
したがって、半導体チップ１０の熱工程に伴う反り量を低減することが要求される。例えば、半導体チップ１０の反り量を２０μｍ以下にすることが好ましく、５μｍ以下にすることがより好ましい。
図７は、実施形態の半導体装置の作用及び効果の説明図である。図７は、実施形態の半導体装置の模式断面図である。
図７（ａ）は、スペーサ３０に半導体チップ１０を載置した後、接合及びワイヤボンディングに伴う熱工程を経る前の図である。図７（ｂ）は、接合及びワイヤボンディングに伴う熱工程を経た後の図である。
実施形態の偏向器１００では、図７（ｂ）に示すように、熱工程を経た後の半導体チップ１０の反りが、比較形態の偏向器９００と比べて小さくなる。
なお、図１（ａ）は、熱工程による半導体チップ１０の反りを無視した理想的な状態の断面図である。
図８は、実施形態の半導体装置の作用及び効果の説明図である。半導体チップ１０の反り量と、スペーサ３０の厚さと半導体チップの厚さとの比（スペーサ厚／半導体チップ厚）との関係を示す。
図８のデータを取得する際、半導体チップ１０にはシリコンを用い、基板２０には樹脂を含むプリント基板を用いている。スペーサ３０にはシリコンを用いている。スペーサ厚／半導体チップ厚が「０」の点は、スペーサ３０がない比較形態の偏向器９００における半導体チップ１０の反り量を示している。
図８から明らかなように、スペーサ３０を設けることで、半導体チップ１０の反り量が激減する。スペーサ厚／半導体チップ厚が１０以上になるとスペーサ３０が無い場合（スペーサ厚／半導体チップ厚≒０）と比較して反り量は１０分の１以下になる。
実施形態の偏向器１００において、スペーサ３０を設けることにより、半導体チップ１０の反り量が激減するのは、熱工程時に基板２０の熱収縮によって半導体チップ１０に加わる応力が、スペーサ３０及び第１の接合材４０が緩衝材となることで、緩和されるからであると考えられる。
スペーサ３０の熱膨張係数は、基板２０の熱膨張係数よりも小さいことが好ましい。通常、半導体チップ１０の熱膨張係数は、樹脂又はセラミックスを含む基板２０の熱膨張係数よりも小さくなる。スペーサ３０の熱膨張係数を、基板２０の熱膨張係数よりも小さくすることで、スペーサ３０と半導体チップ１０との間の熱膨張係数の差が小さくなる。したがって、基板２０の熱収縮に起因して半導体チップ１０に加わる応力が低減され、半導体チップ１０の反り量を低減することが可能となる。
例えば、基板２０が樹脂を含むプリント基板の場合、熱膨張係数は１５ｐｐｍ／Ｋ程度である。また、例えば、基板２０がセラミック基板の場合、熱膨張係数は７ｐｐｍ／Ｋ程度である。
例えば、半導体チップ１０がシリコンの場合、熱膨張係数は３ｐｐｍ／Ｋ程度である。また、例えば、半導体チップ１０が炭化珪素の場合、熱膨張係数は４ｐｐｍ／Ｋ〜５ｐｐｍ／Ｋ程度である。
スペーサ３０と半導体チップ１０との間の熱膨張係数の差を小さくする観点から、スペーサ３０の熱膨張係数は、６ｐｐｍ／Ｋ以下であることが好ましく、５ｐｐｍ／Ｋ以下であることがより好ましい。
スペーサ３０の厚さは、半導体チップ１０の厚さよりも十分厚いことが好ましい。スペーサ３０の厚さを、半導体チップ１０の厚さよりも厚くすることで、スペーサ３０の剛性が相対的に高くなり変形しにくくなる。したがって、基板２０の熱収縮に起因して半導体チップ１０に加わる応力が低減され、半導体チップ１０の反り量を低減することが可能となる。一方厚くしすぎると、偏向器１００が厚くなりすぎ、形成プロセス上、或いは配置スペース上支障がある。好ましくはスペーサ３０の厚さと半導体チップの厚さとの比（スペーサ厚／半導体チップ厚）が、５以上５０以下である。より好ましくは８以上２０以下である。
第２の開口部３１は領域１４より大きいサイズで、可能な限り小さいことが好ましい。スペーサ３０の大きさが相対的に大きくなることで剛性が上がり、基板２０の熱収縮に起因して半導体チップ１０に加わる応力が低減する。また、変形した半導体チップ１０の下面とスペーサ３０の上面とが接触することで、半導体チップ１０の反りが抑えられることも期待できる。よって、半導体チップ１０の反り量を低減させることが可能となる。
スペーサ３０と半導体チップ１０との間の少なくとも一部に空隙６０が設けられることが好ましい。第１の接合材４０の塗布面積が小さくなり、スペーサ３０と半導体チップ１０の接合面積が小さくなる。したがって、基板２０の熱収縮に起因して半導体チップ１０に加わる応力が低減し、半導体チップ１０の反り量を低減させることが可能となる。
図３（ｂ）のように、第１の接合材４０が、複数の部分に分割して設けられることが好ましい。第１の接合材４０の塗布面積が小さくなり、スペーサ３０と半導体チップ１０の接合面積が小さくなる。したがって、基板２０の熱収縮に起因して半導体チップ１０に加わる応力が低減し、半導体チップ１０の反り量を低減させることが可能となる。
第１の接合材４０の厚さを厚くすると、第１の接合材４０の体積が増加して、半導体チップ１０に加わる応力の緩和効果が大きくなる。したがって、基板２０の熱収縮に起因して半導体チップ１０に加わる応力が低減し、半導体チップ１０の反り量を低減させることが可能となる。一方厚すぎると熱伝導上支障がある。第１の接合材４０の厚さは、５μｍ以上１００μｍ以下であることが好ましい。
第１の接合材４０、及び、第２の接合材４２の材料は、半導体チップ１０、基板２０、スペーサ３０の熱工程における変形量を低減し、応力を緩和する観点から、低温で固まることが好ましい。第１の接合材４０、及び、第２の接合材４２は、２００℃以下の硬化温度又は融点を有する材料であることが好ましく、１５０℃以下の硬化温度又は融点を有する材料であることがより好ましい。
第１の接合材４０、及び、第２の接合材４２の材料は、半導体チップ１０に加わる応力を緩和する観点から、低弾性の材料であることが好ましい。
以上、実施形態によれば、偏向器１００の製造時の熱工程において半導体チップ１０に印加される応力が緩和される。したがって、高い位置精度で配置された貫通孔１２を有する半導体チップ１０を備えた偏向器１００を提供することが可能となる。
実施形態では、半導体チップ１０が単一の半導体層１１を用いて形成されている場合を説明したが、例えば、半導体チップ１０が２個の半導体層１１に個別に形成されたパターンを、パターン形成後に貼り合わせたものであっても構わない。
実施形態では、半導体層１１がシリコン層である場合を例に説明したが、半導体層１１は炭化珪素層など、その他の半導体材料であっても構わない。
実施形態では、荷電粒子ビームが電子ビームである場合を例に説明したが、荷電粒子ビームはイオンビームなど、その他の荷電粒子ビームであっても構わない。
本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。例えば、一実施形態の構成要素を他の実施形態の構成要素と置き換え又は変更してもよい。これら実施形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。
１０ 半導体チップ
１２ 貫通孔
１３ａ 制御電極（電極）
１３ｂ 制御電極（電極）
１４ 領域
１５ａ 電極配線層（配線層）
１５ｂ 電極配線層（配線層）
２０ 基板
２１ 第１の開口部
３０ スペーサ
３１ 第２の開口部
４０ 第１の接合材
４２ 第２の接合材
６０ 空隙
１００ 偏向器（半導体装置）

Claims (6)

  1. 複数の貫通孔を有する領域を含む半導体チップと、
    前記領域よりも大きい第１の開口部を有し、樹脂又はセラミックスを含む基板と、
    前記半導体チップと前記基板との間に設けられ、前記領域よりも大きい第２の開口部を有するスペーサと、
    前記半導体チップと前記スペーサとの間に設けられた第１の接合材と、
    前記スペーサと前記基板との間に設けられた第２の接合材と、
    を備え、
    前記スペーサの熱膨張係数は前記基板の熱膨張係数よりも小さい半導体装置。
  2. 前記スペーサの厚さは前記半導体チップの厚さよりも厚い請求項１記載の半導体装置。
  3. 前記スペーサと前記半導体チップとの間の少なくとも一部に空隙が存在する請求項１又は請求項２記載の半導体装置。
  4. 前記第１の接合材が、複数の部分に分割して設けられた請求項１ないし請求項３いずれか一項記載の半導体装置。
  5. 前記第１の接合材の厚さが５μｍ以上である請求項１ないし請求項４いずれか一項記載の半導体装置。
  6. 前記半導体チップは、前記貫通孔を挟んで設けられた１対の電極と、前記１対の電極にそれぞれ接続された配線層とを有する請求項１ないし請求項５いずれか一項記載の半導体装置。
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