JP6874443B2 - Semiconductor devices and methods for manufacturing semiconductor devices - Google Patents

Description

The present invention relates to semiconductor devices and methods for manufacturing semiconductor devices.

There are great expectations for low power consumption of power semiconductor devices, which play a central role in power converters for various purposes such as industrial or electric vehicles. Among power semiconductor devices, IGBTs (Insulated Gate Bipolar Transistors) can achieve low on-voltage due to the conductivity modulation effect and are easy to control with voltage-driven gate control, so their use is suitable. It is definitely taking root. In particular, the trench gate type IGBT in which the gate electrode is formed in the trench provided on the surface of the silicon (Si) wafer can increase the density (total channel length) of the electron inversion layer (channel), so that the on-voltage is lowered. can do.

FIG. 11 is a perspective view showing the structure of a conventional trench gate type IGBT. The shape of the element of the trench gate type IGBT is called a semiconductor chip (hereinafter, chip) having a width and depth of about several mm and a thickness of several hundred μm or less, and is a structure that normally functions as an IGBT in the chip. (Hereinafter, cells) have a structure in which multiple layers are integrated in parallel. Trench gate type IGBT products include discrete IGBTs in which output terminals are connected to each of the chip gate, collector, and emitter and sealed with resin, and multiple chips are placed on an insulating substrate, and the output terminals and heat sink are used. There are IGBT modules packaged in a resin case.

FIG. 11 shows the structure of the semiconductor chip 100 of the trench gate type IGBT, and the semiconductor chip 100 has a plurality of semiconductor cells 120 integrated in multiple layers. As shown in FIG. 11, n ^- type on one surface layer of the silicon substrate with a drift layer 1 p ^- -type layer 4 is provided, n ⁺ -type buffer layer 3 is provided on the other surface layer, n ⁺ -type ^{A p +} type collector region 2 is provided on the surface layer of the buffer layer 3 ^{(hereinafter, the side on which the p-} type layer 4 is provided is provided on the front surface of the silicon substrate, and the p ⁺ type collector region 2 is provided. The side that is used is defined as the back side of the silicon substrate). From the front surface side of the silicon substrate, a plurality of trenches 6 are provided ^{which penetrate the p-} type layer 4 in the depth direction ^{and reach the n-type drift layer 1.}

The p ^- type layer 4 is ^{divided into a p-} type base region 12 and a p ^- type floating region 13 by a trench 6. The p ^- type base region 12 and the p ^- type floating region 13 are repeatedly arranged, for example, alternately in the lateral direction in which the trench 6s are lined up, and are linearly arranged parallel to the trench 6 in the longitudinal direction orthogonal to the lateral direction. It is extending. An ^{n +} type emitter region 5 is selectively provided ^{inside the p −} type base region 12. Further, ^{inside the p-} type base region 12, ^{a p +} type base region 11 is selectively provided ^{adjacent to the n +} type emitter region 5. An n-type inversion layer, which serves as a current path for the main current when in the ON state, is formed in a portion of the ^{p-type base region 12 along the side wall of the trench 6.}

^{The emitter electrode (not shown) is electrically connected to the p +} type base region 11 and the n ⁺ type emitter region 5 via a contact hole provided in the interlayer insulating film (not shown). The collector electrode 14 is conductively connected to the ^{p +} type collector region 2 on the back surface side of the silicon substrate. The gate electrode 8 is provided inside the trench 6 via the gate insulating film 7. Further, the gate electrode 8 between the semiconductor cells 120 is connected to the gate wiring 16 via the gate lead-out wiring 15, and the gate wiring 16 is connected to a gate pad (not shown).

In such an IGBT, when a forward voltage is applied to the gate while a voltage (hereinafter, Vce) is applied between the collector and the emitter, a current (hereinafter, Ic) flows from the collector to the emitter. The amount of current flowing at this time increases or decreases depending on the voltage applied to the gate (hereinafter, Vge). It should be noted that Ic changes not only with Vge but also with Vce and the magnitude of the load at the output destination.

On the other hand, when a voltage in the opposite direction is applied to the gate, the conduction between the collector and the emitter is cut off and Ic does not flow. By applying this function, the IGBT is used for power conversion of an inverter or the like. When applying the IGBT to a large-capacity device, an IGBT module in which a plurality of chips are connected in parallel is used, and when the capacity is further increased, a module in which a plurality of IGBT modules are connected in parallel is used.

As described above, Ic can be controlled by Vge, but Vge may oscillate due to the influence of specific operating conditions and peripheral circuits. This is mainly caused by the exchange of current between the gates of the modules, chips, and cells connected in parallel. For example, in an IGBT or the like, the gate electrode is covered with a gate insulating film, and has the same structure as a capacitor and has the same function as a capacitor. That is, in a chip in which a plurality of cells are connected in parallel, a plurality of capacitors are connected in parallel by low resistance wiring (the gate wiring described above). Therefore, resonance occurs between these capacitors depending on the conditions of circuit operation, which causes Vge to oscillate. In this case, the IGBT cannot be controlled (on, off) by Vge.

As a method of preventing this, for example, there is a method of connecting individual gate resistors for each IGBT module. FIG. 12 is a circuit in which individual gate resistors are connected to each module in a conventional trench gate type IGBT. FIG. 12 shows an example of an IGBT module 110 in which an FWD (Free Wheeling Diode) connected in antiparallel to the IGBT chip 100 is combined, and an external gate resistor 21 is connected to each IGBT module 110. As a result, the exchange of gate current between modules can be suppressed, and the gate resistor 21 can suppress the imbalance of current between modules.

Further, as a method of preventing the oscillation of Vge, for example, there is a method of connecting a resistance chip to the gate of each chip inside the module, or mounting a built-in gate resistor on the chip. FIG. 13 is an equivalent circuit diagram of a chip equipped with a built-in gate resistor in a conventional trench gate type IGBT. In FIG. 13, the built-in gate resistor 22 is mounted on the IGBT chip 100, and the semiconductor cell 120 is connected in series to the built-in gate resistor 22. Further, there is a method of mounting a built-in gate resistor in a cell connected to the same gate wiring by providing a space in the gate wiring that does not include metal wiring and providing a low resistance portion at this space (see, for example, Patent Document 1). ). As a result, the exchange of gate current between chips can be suppressed, and the imbalance of current between chips can be suppressed.

JP-A-2009-141007

However, in the conventional method of connecting individual gate resistors, the method of connecting a resistor chip to the gate of each chip, and the method of mounting a built-in gate resistor in the chip, the exchange of gate current between cells in the chip is not possible. I can't control it. Further, in the method of providing a low resistance portion in the gate wiring, it is possible to control the exchange of gate current for cells connected to different gate wiring, but the gate is used for cells connected to the same gate wiring. Unable to control the exchange of current.

In this invention, in order to solve the above-mentioned problems caused by the prior art, it is possible to control the exchange of gate current between cells in the chip, and it is possible to suppress the oscillation of the voltage applied to the gate and the current imbalance. It is an object of the present invention to provide a semiconductor device capable of manufacturing a semiconductor device and a method for manufacturing the semiconductor device.

In order to solve the above-mentioned problems and achieve the object of the present invention, the semiconductor device according to the present invention has the following features. A second conductive type second semiconductor layer is selectively provided on one surface layer of the first conductive type first semiconductor layer. A first conductive type third semiconductor layer is selectively provided inside the second semiconductor layer. A trench is provided that penetrates the third semiconductor layer and the second semiconductor layer and reaches the first semiconductor layer. A gate electrode is provided inside the trench via a gate insulating film. A gate lead-out wiring that electrically connects to the gate electrode is provided. A high resistance layer having a higher resistance than the gate electrode is provided between the gate electrode and the gate lead-out wiring. The high resistance layer is provided inside the trench in a striped shape in the depth direction of the trench orthogonal to the lateral direction in which the trench is lined up.

Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the resistance value of the high resistance layer is smaller than the product of the built-in resistance value of the semiconductor device and the number of cells included in the semiconductor device. To do.

In order to solve the above-mentioned problems and achieve the object of the present invention, the method for manufacturing a semiconductor device according to the present invention has the following features. First, the first step of selectively forming the second conductive type second semiconductor layer on one surface layer of the first conductive type first semiconductor layer is performed. Next, a second step of selectively forming the first conductive type third semiconductor layer inside the second semiconductor layer is performed. Next, a third step of forming a trench that penetrates the third semiconductor layer and the second semiconductor layer and reaches the first semiconductor layer is performed. Next, a fourth step of forming a gate electrode inside the trench via a gate insulating film is performed. Next, a fifth step of forming a gate lead-out wiring that is electrically connected to the gate electrode is performed. In the fifth step, a high resistance layer having a higher resistance than the gate electrode is formed between the gate electrode and the gate lead-out wiring of the trench, which is orthogonal to the lateral direction in which the trench is lined up inside the trench. Form in stripes in the depth direction.

According to the above-described invention, since the high resistance layer is provided at the portion where the gate lead-out wiring is in contact with the gate electrode, a resistor is connected to each cell. As a result, resonance between a plurality of semiconductor cells is less likely to occur, and even if resonance occurs, the resonance current can be quickly attenuated. Therefore, the exchange of gate current can be controlled even between semiconductor cells connected on the same gate lead-out wiring, and oscillation of voltage applied to the gate and current imbalance can be suppressed.

According to the semiconductor device and the method for manufacturing the semiconductor device according to the present invention, it is possible to control the exchange of the gate current between the cells in the chip, and it is possible to suppress the oscillation of the voltage applied to the gate and the current imbalance. It has the effect of being able to do it.

It is a perspective view which shows the structure of the semiconductor device which concerns on Embodiment 1. FIG. FIG. 5 is a cross-sectional view taken along the line AA'in FIG. 1 showing the structure of the semiconductor device according to the first embodiment. It is a top view which shows the structure of the semiconductor device which concerns on Embodiment 1. FIG. It is an equivalent circuit diagram of the semiconductor device which concerns on Embodiment 1. FIG. It is a perspective view which shows the state in the manufacturing process of the semiconductor device which concerns on Embodiment 1 (the 1). It is a perspective view which shows the state in the manufacturing process of the semiconductor device which concerns on Embodiment 1 (the 2). FIG. 3 is a perspective view showing a state in which the semiconductor device according to the first embodiment is being manufactured (No. 3). It is a perspective view which shows the state in the manufacturing process of the semiconductor device which concerns on Embodiment 1 (the 4). FIG. 5 is a perspective view showing a state in which the semiconductor device according to the first embodiment is being manufactured (No. 5). It is a perspective view which shows the structure of the semiconductor device which concerns on Embodiment 2. FIG. It is a perspective view which shows the structure of the conventional trench gate type IGBT. This is a circuit in which individual gate resistors are connected to each module in a conventional trench gate type IGBT. It is an equivalent circuit diagram of the chip which mounted the built-in gate resistor in the conventional trench gate type IGBT.

Hereinafter, preferred embodiments of the semiconductor device and the method for manufacturing the semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that the electrons or holes are a large number of carriers in the layers and regions marked with n or p, respectively. Further, + and-attached to n and p mean that the impurity concentration is higher and the impurity concentration is lower than that of the layer or region to which it is not attached, respectively. When the notation of n and p including + and-is the same, it means that the concentrations are close to each other, and the concentrations are not necessarily the same. In the following description of the embodiment and the accompanying drawings, the same reference numerals are given to the same configurations, and duplicate description will be omitted.

(Embodiment 1)
An IGBT will be described as an example of the semiconductor device according to the present invention. FIG. 1 is a perspective view showing the structure of the semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view taken along the line AA'of FIG. 1 showing the structure of the semiconductor device according to the first embodiment. In FIG. 1, a ^{part of the structure above the surface of the p-} type layer 4 is omitted, but in FIG. 2, it is shown without omission. FIG. 3 is a top view showing the structure of the semiconductor device according to the first embodiment. FIG. 1 is a perspective view of a portion of region S in FIG.

Further, FIGS. 1 and 2 show only one unit cell (functional unit of the element), and other unit cells adjacent thereto are not shown. ^{The semiconductor device according to the first embodiment shown in FIG. 1 has a MOS (Metal Oxide) on the front surface (plane on the p-} type layer 4 side) side of a semiconductor substrate (silicon substrate: semiconductor chip) made of silicon (Si). It is an IGBT equipped with a Semiconductor) gate.

As shown in FIGS. 1 and 2, the semiconductor device according to the first embodiment is formed on the surface layer of the main surface (front surface) of ^{the n-type drift layer (first conductive type first semiconductor layer) 1.} A p ^- type layer (second conductive type second semiconductor layer) 4 is selectively provided. An ^{n +} type buffer layer 3 is provided on the back surface side of the ^{n − type drift layer 1, and a p +} type collector region 2 is provided on the front ^{surface of the n +} type buffer layer 3.

A ^{plurality of trenches 6 are provided on the front surface side of the n-} type drift layer 1, and form a base portion 30 provided with a channel and a floating portion 31 without a channel. The base portion 30 provided with channels, p ^- -type base region 12, p ^- -type base region 12 from a high impurity concentration p ⁺ -type base region 11 and n ⁺ -type emitter region 5 (third semiconductor of the first conductivity type Layer) is provided. Therefore, when the semiconductor device is in the ON state, a channel is formed in the ^{p-type base region 12.}

n ⁺ -type emitter region 5 is disposed on the outer periphery of the p ⁺ -type base region 11, p ⁺ -type base region 11 may be deeper than the n ⁺ -type emitter region 5. In ^{the region adjacent to the n +} type emitter region 5, a ^{trench 6 is provided which penetrates the p-} type base region 12 in the depth direction (collector electrode 14 side) ^{and reaches the n-} type drift layer 1. For example, a gate electrode 8 made of polysilicon (poly-Si) is embedded in the trench 6 via a gate insulating film 7 which is a thermal oxide film.

Further, as shown in FIG. 1, a gate lead-out wiring 15 is provided on the gate electrode 8, and a gate wiring 16 is provided on the gate lead-out wiring 15. As shown in FIG. 3, the gate wiring 16 is connected to the gate pad 18. The gate wiring 16 is composed of a portion extending linearly in the lateral direction in which the trench 6 is lined up and a portion surrounding the periphery of the semiconductor chip 100. In FIG. 3, there are three portions extending in a straight line, but the number may be more or less than this.

As shown in FIG. 1, a high resistance layer 17 is provided at a portion where the gate lead-out wiring 15 is in contact with the gate electrode 8. Further, although not shown, an insulating film is provided at a portion where the gate lead-out wiring 15 is in ^{contact with a semiconductor region such as the p + type base region 11.} Here, the high resistance layer 17 is a layer having a higher resistance value than the polysilicon that constitutes the gate electrode 8. For example, the resistance value of the high resistance layer 17 is equal to or less than the product of the number of semiconductor cells 120 included in the semiconductor chip 100 and the built-in resistance. In an IGBT or the like, the built-in resistance is 2 to 4 Ω, and when the number of cells of the semiconductor cell 120 is 100, it is 200 to 400 Ω or less. The resistance value of the high resistance layer 17 is preferably smaller than the product of the built-in resistance and the number of cells. Specifically, it is preferably about 1/10 of the above product. Therefore, the resistance value of the high resistance layer 17 is a value of several tens to several hundreds of Ω, and preferably a value of several tens of Ω.

In the chip structure of the IGBT, a current is supplied from the gate pad 18 to the gate electrode 8 made of low-resistance polysilicon via the gate wiring 16. In the present invention, the high resistance layer 17 is formed on the low resistance polysilicon layer, and the gate wiring 16 is provided on the high resistance layer 17. With such a configuration, a gate resistor is individually connected to each semiconductor cell 120 in the semiconductor chip 100.

FIG. 4 is an equivalent circuit diagram of the semiconductor device according to the first embodiment. As shown in FIG. 4, the resistance formed by the high resistance layer 17 is connected to each semiconductor cell 120 in the semiconductor chip 100. As described above, in the present invention, since the high resistance layer 17 is provided at the portion where the gate lead-out wiring 15 is in contact with the gate electrode 8, the resistor is connected to each semiconductor cell 120. As a result, resonance between the plurality of semiconductor cells 120 is less likely to occur, and even if resonance occurs, the resonance current can be quickly attenuated. Therefore, the exchange of gate current can be controlled even between the semiconductor cells 120 connected on the same gate lead-out wiring 15, and the oscillation of the voltage applied to the gate and the current imbalance can be suppressed.

Further, as shown in FIG. 2, an interlayer insulating film 9 for insulating the emitter electrode 10 is provided on the gate electrode 8. ^{The emitter electrode 10 is electrically connected to the n +} type emitter region 5, the p ⁺ type base region 11, and the p ^- type base region 12 through the contact holes provided in the interlayer insulating film 9. The emitter electrode 10 may be grounded or a negative voltage may be applied. A collector electrode 14 is provided on the back side of the semiconductor device. A positive voltage is applied to the collector electrode 14.

^{A p-} type floating region 13 is provided in the floating portion 31 where no channel is provided. The p ^- type floating region 13 is electrically in a floating state. Specifically, the p ^- type floating region 13 is electrically insulated from the emitter electrode 10 by the gate insulating film 7 and the interlayer insulating film 9 that cover the surface. Further, p ^- -type floating region 13, n ^- the pn junction between the type drift layer 1 n ^- -type drift layer 1 and electrically insulated.

(Manufacturing method of semiconductor device according to the first embodiment)
Next, a method of manufacturing the semiconductor device according to the first embodiment will be described. 5 to 9 are perspective views showing a state in the middle of manufacturing the semiconductor device according to the first embodiment. First, n ^- the type drift layer 1 n ^- providing a type semiconductor substrate. The material of the n ^- type semiconductor substrate may be silicon or silicon carbide (SiC). Hereinafter, ^{a case where the n-} type semiconductor substrate is a silicon wafer will be described as an example.

^{Next, the p-} type layer 4 is formed on the front surface side of the ^n- type drift layer 1 by photolithography and ion implantation. The state up to this point is shown in FIG. ^{Next, the p +} type base region 11 is selectively formed on the surface of the ^{p −} type layer 4 by photolithography and ion implantation. ^{Next, the n +} type emitter region 5 is selectively formed on the surface of the ^p- type layer 4 by photolithography and ion implantation. The state up to this point is shown in FIG.

Next, photolithography and etching are performed to form a trench 6 that ^{penetrates the n +} type emitter region 5 and the p ^- type layer 4 and ^{reaches the n-type drift layer 1.} The p ^- type layer 4 is ^{divided into a p-} type base region 12 and a p ^- type floating region 13 by a trench 6. The trench 6 is arranged in a striped layout extending in a direction orthogonal to the direction in which the trench 6 is arranged, for example, when viewed from the front surface ^{of the n-type drift layer 1.}

Next, for example, by thermal oxidation, ^{a gate insulating film 7 is formed along the front surface of the n-} type drift layer 1 and the inner wall of the trench 6. Next, ^{a polysilicon layer is formed on the front surface of the n-} type drift layer 1 so as to embed the inside of the trench 6. Next, the polysilicon layer is etched back, for example, to leave a portion to be the gate electrode 8 inside the trench 6. At that time, the polysilicon may be etched back so as to remain inside the surface of the substrate, or the polysilicon may protrude outward from the surface of the substrate by performing patterning and etching.

A MOS gate having a trench gate structure is composed of the p ^- type base region 12, the n ⁺ type emitter region 5, the p ⁺ type base region 11, the trench 6, the gate insulating film 7, and the gate electrode 8. After forming the gate electrode 8, a p ^- type base region 12, an n ⁺ type emitter region 5, a p ⁺ type base region 11, and a p ^- type floating region 13 may be formed. The state up to this point is shown in FIG.

Next, the high resistance layer 17 is formed on the gate electrode 8 on which the gate lead-out wiring 15 is formed. For example, by implanting impurities in polysilicon by ion implantation, a high resistance layer 17 having a predetermined resistance value is formed. Further, the high resistance layer 17 may be formed by forming an n-type region or a p-type region having a low impurity concentration by epitaxial growth. The state up to this point is shown in FIG.

Next, a polysilicon layer is formed on the substrate. Next, the polysilicon layer is etched back, for example, to leave a portion to be the gate lead-out wiring 15 on the substrate. The gate lead-out wiring 15 and the gate electrode 8 may be formed at the same time. In this case, after forming the gate lead-out wiring 15, impurities are embedded by ion implantation to form a high resistance layer 17 having a predetermined resistance value.

Next, an ^{interlayer insulating film 9 is formed on the front surface of the n-} type drift layer 1 so as to cover the gate electrode 8 and the gate lead-out wiring 15. In FIG. 9, the description of the interlayer insulating film 9 is omitted. Next, the interlayer insulating film 9 is patterned to form a plurality of contact holes penetrating the interlayer insulating film 9 in the depth direction. The depth direction is the direction from the front surface to the back surface ^{of the n-type drift layer 1.} The n ⁺ type emitter region 5, the p ⁺ type base region 11, and the gate lead-out wiring 15 are exposed in the contact hole.

Next, the emitter electrode 10 is formed on the interlayer insulating film 9 so as to embed a contact hole. The emitter electrode 10 is ^{electrically connected to the p-} type base region 12, the n ⁺ type emitter region 5, and the p ⁺ type base region 11. In FIG. 9, the description of the emitter electrode 10 is omitted. Next, the gate wiring 16 is formed on the gate lead-out wiring 15. The gate wiring 16 is formed of, for example, aluminum (Al) wiring or copper (Cu) wiring. The state up to this point is shown in FIG.

Next, the n ^- type drift layer 1 is ground from the back surface side (back grind) to the position of the product thickness used as the semiconductor device. ^{Next, the n +} type buffer layer 3 is formed on the back surface side of ^{the n −} type drift layer 1 by photolithography and ion implantation. ^{Next, a p +} type collector region 2 is formed on ^{the surface of the n +} type buffer layer 3 by photolithography and ion implantation.

Next, the collector electrode 14 is formed on the entire surface of ^{the p + type collector region 2.} After that, the semiconductor wafer is cut (diced) into chips and individualized to complete the IGBT chip (semiconductor chip) shown in FIG.

In FIGS. 1 and 2 described above, the semiconductor cells 120 are connected in parallel to the gate lead-out wiring 15, but the semiconductor cells 120 are also connected in series to the gate lead-out wiring 15. Applicable. In this case, the gate lead-out wiring 15, the high resistance layer 17, and the plurality of semiconductor cells 120 are connected in series, but since there is no low resistance like the gate lead-out wiring 15 between the plurality of semiconductor cells 120, There is little exchange of gate current between each semiconductor cell 120. Therefore, even in the form in which the semiconductor cell 120 is connected in series to the gate lead-out wiring 15, oscillation of the voltage applied to the gate and current imbalance are unlikely to occur.

As described above, according to the semiconductor device according to the first embodiment, since the high resistance layer is provided at the portion where the gate lead-out wiring is in contact with the gate electrode, a resistor is connected to each cell. It becomes. As a result, resonance between a plurality of semiconductor cells is less likely to occur, and even if resonance occurs, the resonance current can be quickly attenuated. Therefore, the exchange of gate current can be controlled even between semiconductor cells connected on the same gate lead-out wiring, and oscillation of voltage applied to the gate and current imbalance can be suppressed.

(Embodiment 2)
Next, the structure of the semiconductor device according to the second embodiment will be described. FIG. 10 is a perspective view showing the structure of the semiconductor device according to the second embodiment. As shown in FIG. 10, the semiconductor device according to the second embodiment is different from the semiconductor device according to the first embodiment in that the high resistance layer 17 is provided between the gate electrodes 8.

The high resistance layer 17 is provided inside the trench 6 and is sandwiched between the gate electrodes 8. Further, the high resistance layer 17 is preferably located closer to the gate lead-out wiring 15 than the bottom of the trench 6. Also in the second embodiment, the equivalent circuit diagram of the chip of the semiconductor device is the same as that of the first embodiment, and the resistance by the high resistance layer 17 is connected to each semiconductor cell 120 in the chip.

(Manufacturing method of semiconductor device according to the second embodiment)
Next, the method of manufacturing the semiconductor device according to the second embodiment will be described. In the method for manufacturing a semiconductor device according to the second embodiment, first, the gate insulating film 7 is formed along the inner wall of the trench 6 as in the first embodiment.

Next, ^{a polysilicon layer is formed on the front surface of the n-} type drift layer 1 so as to fill the inside of the trench 6 halfway. Next, the high resistance layer 17 is formed on the polysilicon layer. For example, by implanting impurities in polysilicon by ion implantation, a high resistance layer 17 having a predetermined resistance value is formed. Next, ^{a polysilicon layer is formed on the front surface of the n-} type drift layer 1 so as to embed the inside of the trench 6. After that, the IGBT chip (semiconductor) shown in FIG. 10 is formed by forming a polysilicon layer on the substrate and leaving the portion to be the gate lead-out wiring 15 on the substrate in the same manner as in the first embodiment. Chip) is completed.

As described above, according to the semiconductor device according to the second embodiment, the resistance due to the high resistance layer is connected to each semiconductor cell in the chip as in the first embodiment. Therefore, the second embodiment has the same effect as that of the first embodiment.

Further, in the first and second embodiments, the high resistance layer 17 is provided in each semiconductor cell 120. Since the high resistance layers 17 are connected in parallel, the increase in on-resistance due to the high resistance layer 17 is negligibly small when viewed from the semiconductor chip 100 as a whole. For example, when the resistance value of one high resistance layer 17 is several tens of Ω and the trenches 6 are provided in about 100 rows, the amount of increase in the on-resistance is about 1/100 of several tens of Ω.

Further, in the first and second embodiments, the high resistance layer 17 is provided in each semiconductor cell 120, but it is also possible to connect individual gate resistors for each IGBT module. In this case, the high resistance layer 17 controls the exchange of gate currents between the semiconductor cells 120 in the semiconductor chip 100, and the individual gate resistors control the exchange of gate currents between the semiconductor modules 110.

Further, in the first and second embodiments, the resistance due to the high resistance layer 17 is connected to each semiconductor cell 120 in the semiconductor chip 100, but it may be connected to a part of the semiconductor cells 120. For example, the high resistance layer 17 may be connected only to the semiconductor cell 120 in the central portion of the semiconductor chip 100 where the current tends to be unbalanced or in the portion directly below the wire connected to the external electrode.

In the above, the present invention can be variously modified without departing from the spirit of the present invention, and in each of the above-described embodiments, for example, the dimensions of each part, the impurity concentration, and the like are set in various ways according to the required specifications and the like. Further, in each of the above-described embodiments, the trench type IGBT is described as an example, but the present invention is not limited to this, and the present invention can be applied to a planar type IGBT. Further, in each of the above-described embodiments, the IGBT is described as an example, but the present invention is not limited to this, and various semiconductor devices that conduct and cut off the current by controlling the gate drive based on a predetermined gate threshold voltage. It is also widely applicable to. For example, it can be applied to a MOSFET by using a conductive type semiconductor substrate different from the IGBT. Further, although the case where silicon is used is described as an example, it can also be applied to a wide bandgap semiconductor such as silicon carbide other than silicon. Further, in each embodiment, the first conductive type is n-type and the second conductive type is p-type, but in the present invention, the first conductive type is p-type and the second conductive type is n-type. It holds.

As described above, the semiconductor device and the method for manufacturing the semiconductor device according to the present invention are useful for high withstand voltage semiconductor devices used in power supply devices such as power conversion devices and various industrial machines.

1 n ^- type drift layer 2 p ⁺ type collector area 3 n ⁺ type buffer layer 4 p ^- type layer 5 n ⁺ type emitter area 6 trench 7 gate insulating film 8 gate electrode 9 interlayer insulating film 10 emitter electrode 11 p ⁺ type base Region 12 p ^- type base region 13 p ^- type floating region 14 Collector electrode 15 Gate lead-out wiring 16 Gate wiring 17 High resistance layer 18 Gate pad 21 External gate resistance 22 Built-in gate resistance 30 Channels are provided in the base portion 31 channels are provided. No floating part 100 Semiconductor chip (IGBT chip)
110 Semiconductor module (IGBT module)
120 semiconductor cell

Claims (3)

The first conductive type first semiconductor layer and
A second conductive type second semiconductor layer selectively provided on one surface layer of the first semiconductor layer,
A first conductive type third semiconductor layer selectively provided inside the second semiconductor layer,
A trench that penetrates the third semiconductor layer and the second semiconductor layer and reaches the first semiconductor layer,
A gate electrode provided inside the trench via a gate insulating film,
The gate lead-out wiring that electrically connects to the gate electrode and
With
A high resistance layer having a higher resistance than the gate electrode is provided between the gate electrode and the gate lead-out wiring .
The semiconductor device is characterized in that the high resistance layer is provided inside the trench in a stripe shape in the depth direction of the trench orthogonal to the lateral direction in which the trench is lined up. The semiconductor device according to claim 1, wherein the resistance value of the high resistance layer is smaller than the product of the built-in resistance value of the semiconductor device and the number of cells included in the semiconductor device. The first step of selectively forming the second conductive type second semiconductor layer on one surface layer of the first conductive type first semiconductor layer, and
A second step of selectively forming a first conductive type third semiconductor layer inside the second semiconductor layer, and
A third step of forming a trench that penetrates the third semiconductor layer and the second semiconductor layer and reaches the first semiconductor layer.
A fourth step of forming a gate electrode inside the trench via a gate insulating film, and
The fifth step of forming the gate lead-out wiring electrically connected to the gate electrode and
Including
In the fifth step, a high resistance layer having a higher resistance than the gate electrode is formed between the gate electrode and the gate lead-out wiring of the trench, which is orthogonal to the lateral direction in which the trench is lined up inside the trench. A method for manufacturing a semiconductor device, characterized in that it is formed in a stripe shape in the depth direction.

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