JP7302469B2 - semiconductor equipment - Google Patents

Description

The technology disclosed in this specification relates to a semiconductor device.

Patent Document 1 discloses a semiconductor device having a semiconductor substrate partitioned into an IGBT (insulated gate bipolar transistor) region and a diode region. In this semiconductor device, an upper electrode is provided so as to cover the upper surface of the semiconductor substrate, and a lower electrode is provided so as to cover the lower surface of the semiconductor substrate. Within the IGBT region, an IGBT is provided such that the upper electrode serves as an emitter electrode and the lower electrode serves as a collector electrode. Within the diode region, the diode is provided such that the upper electrode serves as the anode electrode and the lower electrode serves as the cathode electrode. The diode is connected anti-parallel to the IGBT and can act as a freewheeling diode.

Patent Document 1 discloses a technique for mixing active gates and dummy gates in this type of semiconductor device. The active gate is configured to be able to apply a gate voltage for controlling on/off of the IGBT. The dummy gate is configured to be electrically connected to the upper electrode.

JP 2013-021240 A

By the way, in this type of semiconductor device, there is a problem of carrier inflow from the IGBT region to the diode region in the mode in which the diode operates. Such carriers flowing from the IGBT region into the diode region reduce the forward voltage of the diode and increase the carrier density in the diode region. As a result, deterioration of reverse recovery characteristics of the diode becomes a problem. This specification provides a technique for suppressing the inflow of carriers from the IGBT region to the diode region in a semiconductor device having a semiconductor substrate partitioned into an IGBT region and a diode region.

A semiconductor device disclosed in this specification includes a semiconductor substrate partitioned into an IGBT region and a diode region, an upper electrode provided to cover the upper surface of the semiconductor substrate, and a lower surface of the semiconductor substrate. a plurality of active gates provided on the upper surface of the semiconductor substrate corresponding to the IGBT regions and electrically connected to first control terminals; and corresponding to the diode regions. a plurality of dummy gates provided on the top surface of the semiconductor substrate and electrically connected to the upper electrode; a plurality of boundary gates disposed between the active gate and the dummy gate and electrically connected to a second control terminal different from the first control terminal; , can be provided. The IGBT regions of the semiconductor substrate include a first conductivity type drift region, a second conductivity type body region provided on the drift region, and a first conductivity type body region provided on the body region. It may have an emitter region and a barrier region of a first conductivity type within the body region and separated from the drift region and the emitter region by the body region. The active gate extends from the top surface of the semiconductor substrate to the drift region. The boundary gate extends from the top surface of the semiconductor substrate to the barrier region and does not extend to the drift region.

In the above semiconductor device, the boundary gate is selectively provided at the boundary adjacent to the diode region in the IGBT region. In the semiconductor device described above, in the mode in which the diode operates, the amount of carriers flowing from the IGBT region into the diode region can be suppressed by controlling the voltage applied to the boundary gate. As a result, deterioration of reverse recovery characteristics is suppressed in the above semiconductor device. Also, the boundary gate is configured so as not to reach the drift region. Therefore, even if a voltage is applied to the boundary gate, the upper electrode and the lower electrode are not electrically connected through the channel formed on the side surface of the boundary gate. Thus, the boundary gate can suppress the amount of carriers flowing from the IGBT region into the diode region without affecting the switching operation of the IGBT in the IGBT region.

1 schematically shows a plan view of a semiconductor device of this embodiment. FIG. FIG. 2 is a cross-sectional view of the main part of the semiconductor device of the present embodiment, and schematically shows a cross-sectional view of the main part taken along the line II-II of FIG. 1; 4 shows a timing chart of the potential of each gate of the semiconductor device of this embodiment.

As shown in FIG. 1, a semiconductor device 10 has a semiconductor substrate 12 . The semiconductor substrate 12 is a silicon substrate. Hereinafter, the thickness direction of the semiconductor substrate 12 is referred to as the z direction, one direction parallel to the upper surface of the semiconductor substrate 12 is referred to as the x direction, and the direction parallel to the upper surface of the semiconductor substrate 12 and orthogonal to the x direction is referred to as the y direction. It says. As shown in FIG. 1, the semiconductor substrate 12 has two element regions 18 and a breakdown voltage region 19 arranged around the element regions 18 . Each element region 18 is partitioned into an IGBT region 20 and a diode region 40 . In each element region 18, the IGBT regions 20 and the diode regions 40 are alternately provided in the y direction. A structure for forming an IGBT is provided in the IGBT region 20 , and a structure for forming a diode is provided in the diode region 40 . A first control terminal G<b>1 and a second control terminal G<b>2 are provided on the semiconductor substrate 12 corresponding to the withstand voltage region 19 . As will be described later, the first control terminal G1 is electrically connected to the active gate and the second control terminal G2 is electrically connected to the boundary gate.

As shown in FIG. 2, semiconductor device 10 has upper electrode 14 and lower electrode 16 . The upper electrode 14 is arranged so as to cover the upper surface 12 a (surface) of the semiconductor substrate 12 . The lower electrode 16 is arranged so as to cover the lower surface 12 b (back surface) of the semiconductor substrate 12 . Thus, the semiconductor device 10 is configured as a vertical device. The upper electrode 14 serves as both the emitter electrode of the IGBT and the anode electrode of the diode. The lower electrode 16 serves as both the collector electrode of the IGBT and the cathode electrode of the diode.

A collector region 30 and a cathode region 48 are provided in the semiconductor substrate 12 . A collector region 30 and a cathode region 48 are provided at positions exposed on the lower surface 12 b of the semiconductor substrate 12 . The collector region 30 is a p-type region containing p-type impurities and is in ohmic contact with the lower electrode 16 . The cathode region 48 is an n-type region containing n-type impurities and is in ohmic contact with the lower electrode 16 . A collector region 30 is provided over the entire IGBT region 20 at a position exposed to the lower surface 12 b of the semiconductor substrate 12 , and a cathode region 48 is provided over the entire diode region 40 . In other words, when the semiconductor substrate 12 is viewed along the z direction (thickness direction of the semiconductor substrate 12), the collector region 30 is provided at a position exposed on the lower surface of the semiconductor substrate 12 corresponding to the IGBT region 20, and the diode A cathode region 48 is provided at a position exposed on the lower surface of the semiconductor substrate 12 corresponding to the region 40 . In this manner, the semiconductor substrate 12 is defined as the IGBT region 20 in the range where the collector region 30 is provided, and as the diode region 40 in the range where the cathode region 48 is provided. In the semiconductor device 10 , a range adjacent to the diode region 40 in the IGBT region 20 is particularly called a boundary portion 60 .

Semiconductor substrate 12 further includes buffer region 28 , drift region 26 , barrier region 25 , body region 24 , body contact region 23 , emitter region 22 , anode region 42 and anode contact region 41 .

Buffer region 28 is an n-type region with lower n-type impurities than cathode region 48 . The buffer region 28 is distributed over the IGBT region 20 and the diode region 40 . The buffer region 28 is arranged above the collector region 30 in the IGBT region 20 and is in contact with the collector region 30 . The buffer region 28 is located above and in contact with the cathode region 48 within the diode region 40 .

The drift region 26 is an n-type region having a lower n-type impurity concentration than the buffer region 28 . The drift region 26 is distributed over the IGBT region 20 and the diode region 40 . The drift region 26 is located above the buffer region 28 in the IGBT region 20 and the diode region 40 and contacts the buffer region 28 .

Body region 24 is a p-type region containing p-type impurities. Body region 24 is arranged within IGBT region 20 . Body region 24 is arranged above drift region 26 and is in contact with drift region 26 .

Body contact region 23 is a p-type region having a higher p-type impurity concentration than body region 24 . Body contact region 23 is arranged in IGBT region 20 . Body contact region 23 is partially disposed on top of body region 24 and contacts body region 24 . Body contact region 23 is separated from drift region 26 by body region 24 . The body contact region 23 is arranged at a position exposed on the upper surface 12 a of the semiconductor substrate 12 and is in ohmic contact with the upper electrode 14 .

The emitter region 22 is an n-type region having a higher n-type impurity concentration than the drift region 26 . The emitter region 22 is arranged within the IGBT region 20 . Emitter region 22 is partially disposed on top of body region 24 and abuts body region 24 . Emitter region 22 is separated from drift region 26 by body region 24 . The emitter region 22 is arranged at a position where the body contact region 23 does not exist and is exposed on the upper surface 12 a of the semiconductor substrate 12 . Emitter region 22 is in ohmic contact with upper electrode 14 .

Anode region 42 is a p-type region containing p-type impurities. Anode region 42 is located within diode region 40 . Anode region 42 is located above drift region 26 and is in contact with drift region 26 .

The anode contact region 41 is a p-type region having a higher p-type impurity concentration than the anode region 42 . Anode contact region 41 is located within diode region 40 . Anode contact region 41 is partially disposed on top of anode region 42 and contacts anode region 42 . Anode contact region 41 is separated from drift region 26 by anode region 42 . The anode contact region 41 is arranged in a range including the upper surface 12 a of the semiconductor substrate 12 and is in ohmic contact with the upper electrode 14 .

The barrier region 25 is an n-type region containing n-type impurities. The barrier region 25 is distributed over the IGBT region 20 and the diode region 40 . The barrier region 25 extends along the in-plane direction of the semiconductor substrate 12 (the in-plane direction parallel to the xy plane) so as to vertically separate the body region 24 in the IGBT region 20 . Barrier region 25 is separated from drift region 26 and emitter region 22 by body region 24 within IGBT region 20 . The barrier region 25 extends along the in-plane direction of the semiconductor substrate 12 so as to vertically separate the anode region 42 in the diode region 40 . Barrier region 25 is separated from drift region 26 by body region 24 within diode region 40 .

The semiconductor device 10 further includes multiple active gates 33 , multiple dummy gates 53 , and multiple boundary gates 73 .

A plurality of active gates 33 are provided on the upper surface 12 a of the semiconductor substrate 12 corresponding to the IGBT regions 20 . Each of the plurality of active gates 33 extends long in the x direction and is arranged at intervals in the y direction. Each of the plurality of active gates 33 extends from the upper surface 12 a of the semiconductor substrate 12 to a depth reaching the drift region 26 . Each of the plurality of active gates 33 has a gate electrode 34 insulated from the semiconductor substrate 12 by a gate insulating film 32 . An interlayer insulating film 36 is arranged above each gate electrode 34 . Each gate electrode 34 is insulated from the upper electrode 14 by an interlayer insulating film 36 . Each gate electrode 34 is electrically connected to the first control terminal G1 (see FIG. 1).

The sides of the active gate 33 are in contact with the emitter region 22 , the body region 24 , the barrier region 25 and the drift region 26 . Therefore, when a voltage is applied to the gate electrode 34 of the active gate 33 via the first control terminal G1 and the potential of the gate electrode 34 is made higher than the emitter potential, an n-type channel is formed in the body region 24 and the emitter region. 22, barrier region 25 and drift region 26 are electrically connected.

A plurality of dummy gates 53 are provided on the upper surface 12 a of the semiconductor substrate 12 corresponding to the diode regions 40 . Each of the plurality of dummy gates 53 extends long in the x direction and is arranged at intervals in the y direction. Each of the plurality of dummy gates 53 extends from the top surface 12 a of the semiconductor substrate 12 to a depth reaching the drift region 26 . Each of the plurality of dummy gates 53 has a dummy gate electrode 54 insulated from the semiconductor substrate 12 by a dummy gate insulating film 52 . Each dummy gate electrode 54 is in contact with the upper electrode 14 and electrically connected to the upper electrode 14 .

A plurality of boundary gates 73 are provided on the upper surface 12 a of the semiconductor substrate 12 corresponding to the boundary 60 of the IGBT region 20 . Each of the plurality of boundary gates 73 is elongated in the x direction and arranged at intervals in the y direction. A plurality of boundary gates 73 are arranged between the active gates 33 and the dummy gates 53 . In this example, four boundary gates 73 are positioned between active gates 33 and dummy gates 53 . Each of the plurality of boundary gates 73 extends from the upper surface 12 a of the semiconductor substrate 12 to a depth reaching the barrier region 25 but does not reach the drift region 26 . Specifically, the bottom surface of each of the plurality of boundary gates 73 is located within the barrier region 25 . Each of the plurality of boundary gates 73 has a boundary gate electrode 74 insulated from the semiconductor substrate 12 by a boundary gate insulating film 72 . A boundary interlayer insulating film 76 is arranged above each boundary gate electrode 74 . Each boundary gate electrode 74 is insulated from the upper electrode 14 by a boundary interlayer insulating film 76 . Each boundary gate electrode 74 is electrically connected to the second control terminal G2 (see FIG. 1).

The side surfaces of the boundary gate 73 are in contact with the emitter region 22 , the body region 24 and the barrier region 25 . Therefore, when a voltage is applied to the boundary gate electrode 74 of the boundary gate 73 via the second control terminal G2 to make the potential of the boundary gate electrode 74 higher than the emitter potential, an n-type channel is formed in the body region 24. are formed, and the emitter region 22 and the barrier region 25 are electrically connected.

FIG. 3 shows a timing chart of potentials of the gate electrode 34 of the active gate 33, the dummy gate electrode 54 of the dummy gate 53, and the boundary gate electrode 74 of the boundary gate 73. As shown in FIG. The potential at the start of each gate is the emitter potential.

In the mode in which the IGBT operates, a voltage is applied between the lower electrode 16 and the upper electrode 14 so that the potential of the lower electrode 16 is higher than that of the upper electrode 14 . As shown in FIG. 3, in the mode in which this IGBT operates, the gate electrode 34 of the active gate 33 has a higher potential than the emitter potential, and the boundary gate 73 remains at the emitter potential. The dummy gate 53 is short-circuited to the upper electrode 14 and remains at the emitter potential. In this IGBT operating mode, an n-type channel is formed in the body region 24 in contact with the side surface of the active gate 33 in the IGBT region 20, and electrons are injected from the emitter region 22 into the drift region 26 via the n-type channel. , holes are injected from the collector region 30 into the drift region 26, and the IGBTs in the IGBT region 20 are turned on. Thus, in the mode in which the IGBT operates, current flows from the lower electrode 16 of the IGBT region 20 toward the upper electrode 14 .

In the mode in which the diode operates, a voltage is applied between the lower electrode 16 and the upper electrode 14 so that the upper electrode 14 has a higher potential than the lower electrode 16 . In the mode in which this diode operates, as shown in FIG. 3, the boundary gate 73 is at a potential higher than the emitter potential and the active gate 33 is lowered to the emitter potential. The dummy gate 53 is short-circuited to the upper electrode 14 and remains at the emitter potential. In the mode in which this diode operates, in the IGBT region 20, the n-type channel on the sides of the active gate 33 disappears and the IGBT in the IGBT region 20 is turned off.

A diode is formed between the upper electrode 14 and the lower electrode 16 of the diode region 40 by the anode contact region 41 , the anode region 42 , the drift region 26 , the buffer region 28 and the cathode region 48 . Therefore, in the mode in which the diode operates, the potential of the upper electrode 14 is higher than that of the lower electrode 16, so the diode in the diode region 40 is turned on. That is, electrons flow from the lower electrode 16 toward the upper electrode 14 via the cathode region 48 , buffer region 28 , drift region 26 , anode region 42 and anode contact region 41 . At the same time, holes flow from the upper electrode 14 to the drift region 26 via the anode contact region 41 and the anode region 42 . Thus, in the diode operating mode, a return current flows from the upper electrode 14 of the diode region 40 toward the lower electrode 16 .

A parasitic diode is also formed in the boundary portion 60 by the body contact region 23 , the body region 24 , the drift region 26 , the buffer region 28 and the cathode region 48 . Therefore, in the diode operating mode, the parasitic diode at the boundary 60 is also turned on, and holes flow from the boundary 60 into the diode region 40 . When the amount of inflow of such holes is large, the forward voltage of the diode region 40 is lowered and the hole density of the diode region 40 is increased. As a result, the reverse recovery characteristics of the diode deteriorate.

In the semiconductor device 10, as shown in FIG. 3, the boundary gate electrode 74 of the boundary gate 73 is controlled to have a higher potential than the emitter potential in the diode operating mode. In the mode in which this diode operates, in the boundary portion 60, an n-type channel is formed in the body region 24 in contact with the side surface of the boundary gate 73, the emitter region 22 and the barrier region 25 are electrically connected, and the potential of the barrier region 25 is the emitter region. potential. Therefore, no electric field is generated at the pn junction surface between the body region 24 and the barrier region 25 located above the barrier region 25, and holes cannot cross the barrier of the pn junction surface. hole injection from the body region 24 located on the upper side is suppressed. Thereby, the amount of holes flowing into the diode region 40 from the boundary portion 60 of the IGBT region 20 can be suppressed. As a result, deterioration of the reverse recovery characteristic is suppressed in the semiconductor device 10 .

Also, boundary gate 73 is not configured to reach drift region 26 . Therefore, even if the potential of boundary gate electrode 74 of boundary gate 73 is higher than the emitter potential in the diode operation mode, an n-type channel is formed in body region 24 below barrier region 25 . Therefore, there is no conduction between the upper electrode 14 and the lower electrode 16. Thus, the boundary gate 73 can suppress the amount of holes flowing from the IGBT region 20 into the diode region 40 without affecting the switching operation of the IGBTs in the IGBT region 20 .

Further, in the semiconductor device 10, there is a trade-off relationship between the forward voltage of the diode in the diode region 40 and the loss during reverse recovery. As the diode forward voltage decreases, the diode reverse recovery loss increases. On the other hand, if the forward voltage of the diode increases, the reverse recovery loss of the diode will decrease. In the semiconductor device 10 , this trade-off relationship can be controlled by controlling the voltage applied to the boundary gate electrode 74 of the boundary gate 73 . When the difference between the potential of the boundary gate electrode 74 of the boundary gate 73 and the emitter potential is relatively increased, the forward voltage of the diode increases and the loss during reverse recovery decreases. On the other hand, when the difference between the boundary gate 73 and the emitter potential of the boundary gate electrode 74 is relatively small, the forward voltage of the diode is lowered and the loss during reverse recovery is increased. Thus, the semiconductor device 10 can have desired characteristics by controlling the voltage applied to the boundary gate electrode 74 of the boundary gate 73 .

In the semiconductor device 10, four boundary gates 73 are provided. The number of boundary gates 73 is appropriately set according to the range in which the inflow of holes from the IGBT region 20 to the diode region 40 poses a problem. Although not particularly limited, the number of boundary gates 73 may be, for example, four to eight.

In the semiconductor device 10 , only the active gate 33 is formed in the IGBT region 20 other than the boundary portion 60 of the IGBT region 20 , and only the boundary gate 73 is formed in the boundary portion 60 of the IGBT region 20 . For this reason, many active gates 33 are arranged in most of the IGBT region 20, current flows uniformly in the IGBT region 20, and heat generation due to current concentration is suppressed.

Although the embodiments have been described in detail above, they are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or in the drawings exhibit technical usefulness either singly or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques exemplified in this specification or drawings simultaneously achieve a plurality of purposes, and achieving one of them has technical utility in itself.

10: semiconductor device 12: semiconductor substrate 14: upper electrode 16: lower electrode 20: IGBT region 22: emitter region 23: body contact region 24: body region 25: barrier region 26: drift region 28: buffer region 30: collector region 33 : Active gate 40 : Diode region 41 : Anode contact region 42 : Anode region 48 : Cathode region 53 : Dummy gate 60 : Boundary 73 : Boundary gate

Claims (1)

a semiconductor substrate partitioned into an IGBT region and a diode region;
an upper electrode provided to cover the upper surface of the semiconductor substrate;
a lower electrode provided to cover the lower surface of the semiconductor substrate;
a plurality of active gates provided on the upper surface of the semiconductor substrate corresponding to the IGBT regions and electrically connected to a first control terminal;
a plurality of dummy gates provided on the upper surface of the semiconductor substrate corresponding to the diode region and electrically connected to the upper electrode;
provided on the upper surface of the semiconductor substrate corresponding to a boundary portion adjacent to the diode region in the IGBT region, arranged between the active gate and the dummy gate, and the first control terminal and the a plurality of boundary gates electrically connected to different second control terminals;
The IGBT region of the semiconductor substrate,
a first conductivity type drift region;
a body region of a second conductivity type provided on the drift region;
a first conductivity type emitter region provided on the body region;
a barrier region of a first conductivity type provided within the body region and separated from the drift region and the emitter region by the body region;
the active gate reaches the drift region from the upper surface of the semiconductor substrate;
The semiconductor device, wherein the boundary gate reaches the barrier region from the top surface of the semiconductor substrate and does not reach the drift region.

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