JP6868982B2 - A method for mounting a semiconductor provided with a raised portion at a substrate position on a substrate. - Google Patents

A method for mounting a semiconductor provided with a raised portion at a substrate position on a substrate. Download PDF

Info

Publication number
JP6868982B2
JP6868982B2 JP2016156305A JP2016156305A JP6868982B2 JP 6868982 B2 JP6868982 B2 JP 6868982B2 JP 2016156305 A JP2016156305 A JP 2016156305A JP 2016156305 A JP2016156305 A JP 2016156305A JP 6868982 B2 JP6868982 B2 JP 6868982B2
Authority
JP
Japan
Prior art keywords
camera
substrate
positioning
bonding head
image
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2016156305A
Other languages
Japanese (ja)
Other versions
JP2017050533A (en
JP2017050533A5 (en
Inventor
フローリアン スピア
フローリアン スピア
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Besi Switzerland AG
Original Assignee
Besi Switzerland AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Besi Switzerland AG filed Critical Besi Switzerland AG
Publication of JP2017050533A publication Critical patent/JP2017050533A/en
Publication of JP2017050533A5 publication Critical patent/JP2017050533A5/ja
Application granted granted Critical
Publication of JP6868982B2 publication Critical patent/JP6868982B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67121—Apparatus for making assemblies not otherwise provided for, e.g. package constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67144—Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67282—Marking devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67703—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations
    • H01L21/67712—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations the substrate being handled substantially vertically
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H01L21/681—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/757—Means for aligning
    • H01L2224/75702—Means for aligning in the upper part of the bonding apparatus, e.g. in the bonding head
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/757—Means for aligning
    • H01L2224/75753—Means for optical alignment, e.g. sensors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/758—Means for moving parts
    • H01L2224/75821—Upper part of the bonding apparatus, i.e. bonding head
    • H01L2224/75824—Translational mechanism
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/81132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Description

本発明は、フリップチップとして隆起部が設けられている半導体チップを基板の基板位置に取り付けるための方法に関する。 The present invention relates to a method for mounting a semiconductor chip provided with a raised portion as a flip chip at a substrate position of a substrate.

本発明は、フリップチップとしての半導体チップを基板に取り付けるための方法を開発し、それによって、一方で極めて高い配置精度と、他方で最大可能スループットとを可能にするという目的に基づく。 The present invention is based on the object of developing a method for mounting a semiconductor chip as a flip chip on a substrate, thereby enabling extremely high placement accuracy on the one hand and maximum possible throughput on the other hand.

この明細書の一部に組み込まれかつそれを構成する添付の図面は、本発明の１つまたは複数の実施形態を例示し、詳細な説明と共に、本発明の原理および実装形態を説明する役割を果たす。本図は概略的であり一定の尺度ではない。 The accompanying drawings, which are incorporated into and constitute a portion of this specification, exemplify one or more embodiments of the invention and serve to illustrate the principles and embodiments of the invention, along with a detailed description. Fulfill. This figure is schematic and not a fixed scale.

フリップチップとして隆起部が設けられている半導体チップを取り付けるための装置の側面視を概略的に示す図である。It is a figure which shows typically the side view of the apparatus for attaching the semiconductor chip which provided the raised part as a flip chip. カメラ支持部を上面視で示す図である。It is a figure which shows the camera support part in the top view. 画素座標系および機械座標系を示す図である。It is a figure which shows the pixel coordinate system and the machine coordinate system.

図１は、本発明による方法を実行するためにセットアップされる、フリップチップ３として隆起部１が設けられている半導体チップ２を取り付けるための装置の側面視を概略的に示す。該装置は、半導体チップ２を設けるためのウエハテーブル４、ピックアップヘッド６を有するフリップ装置５、移送ヘッド８を有する第１の移送システム７、ボンディングヘッド１０を有する第２の移送システム９、支持部１２上に基板１１を供給しかつ設けるための移送システム（図示せず）、半導体チップを融剤によって濡らすためのデバイス１３、第１のカメラ１４、および、第２のカメラ１５を備える。デバイス１３は、カメラ支持部１６、基部が透明である空洞１８を有するプレート１７、および、下方に開放する融剤容器１９を備える。ボンディングヘッド１０の位置付けは機械座標によって示される。装置は、図示されない制御デバイスによって制御される。 FIG. 1 schematically shows a side view of a device for mounting a semiconductor chip 2 provided with a raised portion 1 as a flip chip 3 set up to carry out the method according to the invention. The device includes a wafer table 4 for providing a semiconductor chip 2, a flip device 5 having a pickup head 6, a first transfer system 7 having a transfer head 8, a second transfer system 9 having a bonding head 10, and a support portion. A transfer system (not shown) for supplying and providing the substrate 11 on the 12 is provided, a device 13 for wetting the semiconductor chip with a flux, a first camera 14, and a second camera 15. The device 13 includes a camera support 16, a plate 17 having a cavity 18 with a transparent base, and a flux container 19 that opens downward. The positioning of the bonding head 10 is indicated by mechanical coordinates. The device is controlled by a control device (not shown).

第１の移送システム７は、移送ヘッド８を少なくとも２つの空間方向に移動させるようにセットアップされる。第２の移送システム９は、ボンディングヘッド１０を３つの空間方向に移動させるようにセットアップされる。 The first transfer system 7 is set up to move the transfer head 8 in at least two spatial directions. The second transfer system 9 is set up to move the bonding head 10 in three spatial directions.

やはり、本発明による方法を実行するのに適している別の装置では、ウエハテーブル４、およびピックアップヘッド６を有するフリップ装置５は存在しないが、フリップチップ３として直接半導体チップ２を設ける（フィーダとしても既知の）送給デバイスに置き換えられる。このような装置では、参照符号４によって図１に示される要素は、送給デバイスを表す。 Again, in another device suitable for performing the method according to the invention, there is no flip device 5 with a wafer table 4 and a pickup head 6, but a semiconductor chip 2 is provided directly as the flip chip 3 (as a feeder). Will be replaced by a known) delivery device. In such devices, the element shown in FIG. 1 by reference numeral 4 represents a feeding device.

カメラ支持部１６は、装置上に静止するように配設され、第１のカメラ１４が据えられる基部２０と、少なくとも２つの側壁２１とを備える。プレート１７は、カメラ支持部１６に取り外し可能に取り付けられる。図２は、カメラ支持部１６を上面視で示す。カメラ支持部１６は、第１の光学マーキング２２と、オプションとして、少なくとも１つのさらなる光学マーキング２３とを含む。カメラ支持部１６は、機械的剛性を有するように形成されることで、第１のカメラ１４、光学マーキング２２およびオプションとして光学マーキング２３が互いに対して動かない幾何学的関係にあるようにし、それによって、第１のカメラ１４の画像に割り当てられた画素座標系の位置付けおよび配向は、光学マーキング２２およびオプションとして光学マーキング２３の位置付けに対して固定的関係にある（すなわち、この場合変更不可能を前提とする）。 The camera support portion 16 is arranged so as to be stationary on the device, and includes a base portion 20 on which the first camera 14 is placed and at least two side walls 21. The plate 17 is removably attached to the camera support 16. FIG. 2 shows the camera support portion 16 in a top view. The camera support 16 includes a first optical marking 22 and optionally at least one additional optical marking 23. The camera support 16 is formed to have mechanical rigidity so that the first camera 14, the optical marking 22, and optionally the optical marking 23 are in a geometric relationship that does not move with respect to each other. The positioning and orientation of the pixel coordinate system assigned to the image of the first camera 14 is fixedly related to the positioning of the optical marking 22 and optionally the optical marking 23 (ie, in this case immutable). Assuming).

光学マーキング２２およびオプションとして光学マーキング２３は、好ましくは、基板１１用の支持部１２の表面に垂直に延在する方向に、実質的に基板位置の高さに等しい高さで配設される。これによって、第２のカメラ１５が、光学マーキング２２およびオプションとして光学マーキング２３の画像、または、基板位置の画像、もしくは基板の基板マーキングの画像を記録する時、実質的に同じ高さで位置するという利点がもたらされる。これは、ボンディングヘッド１０が、物体を、第２のカメラ１５の焦点面に対して撮影させるために異なる高さに持ち上げられる必要がないことを意味する。 The optical marking 22 and optionally the optical marking 23 are preferably arranged at a height substantially equal to the height of the substrate position in a direction extending perpendicular to the surface of the support 12 for the substrate 11. Thereby, when the second camera 15 records the image of the optical marking 22 and optionally the optical marking 23, the image of the substrate position, or the image of the substrate marking of the substrate, the second camera 15 is positioned at substantially the same height. The advantage is brought. This means that the bonding head 10 does not have to be lifted to different heights to allow the object to be imaged with respect to the focal plane of the second camera 15.

フリップチップ３の画素座標は、第１のカメラ１４によって記録されたフリップチップ３の画像から判断され、第１の幾何学的データによってボンディングヘッド１０の機械座標に変換される。第１の幾何学的データは、第１の光学マーキング２２の位置付け、および、固定値（ｕ、ｖ）を有するベクトルＡを含み、それらによって、第１のカメラ１４の画素座標系の基準点からの第１の光学マーキング２２の方向および距離が指定される。第１の幾何学的データは固定角Ψをさらに含み、この固定角Ψによって、第１のカメラ１４の画素座標系と、ボンディングヘッド１０の機械座標系との間のねじれが示される。光学マーキングが２つ以上ある場合、第１の幾何学的データは、それぞれのさらなる光学マーキングの位置付け、および、関連する、固定値を有するベクトルを含み、これらによって、第１のカメラ１４の画素座標系の基準点からのさらなる光学マーキングの方向および距離が指定される。 The pixel coordinates of the flip chip 3 are determined from the image of the flip chip 3 recorded by the first camera 14, and are converted into the mechanical coordinates of the bonding head 10 by the first geometric data. The first geometric data includes the positioning of the first optical marking 22 and the vector A having a fixed value (u, v), thereby from the reference point of the pixel coordinate system of the first camera 14. The direction and distance of the first optical marking 22 of the above are specified. The first geometric data further includes a fixed angle Ψ, which indicates the twist between the pixel coordinate system of the first camera 14 and the mechanical coordinate system of the bonding head 10. If there are two or more optical markings, the first geometric data contains the positioning of each additional optical marking and the associated vector with a fixed value, thereby the pixel coordinates of the first camera 14. Further optical marking directions and distances from the reference point of the system are specified.

図３は、ボンディングヘッド１０の機械座標系ＭＳ、第１のカメラ１４の画素座標系ＰＳ、第１の光学マーキング２２、ベクトルＡ、および、角度Ψを概略的に示す。ベクトルＡの値（ｕ、ｖ）は機械座標系ＭＳにおける数である。 FIG. 3 schematically shows the mechanical coordinate system MS of the bonding head 10, the pixel coordinate system PS of the first camera 14, the first optical marking 22, the vector A, and the angle Ψ. The values (u, v) of the vector A are numbers in the machine coordinate system MS.

より詳細に後に説明されるように、フリップチップ３は、本発明による方法で空洞１８に載置される。この場合、その隆起部１は、融剤に浸漬され、画像は第１のカメラ１４によって記録され、濡れ期間の終結後、フリップチップ３は空洞１８から除去され、基板１１に取り付けられる。空洞１８は、この段階中、第１のカメラ１４の上の固定位置上に位置が定められ、第１のカメラ１４の視野は空洞１８の基部へ方向づけられ、それによって、その画像は、隆起部を有するフリップチップ３の底部側を示す。 As will be described in more detail later, the flip chip 3 is placed in the cavity 18 by the method according to the invention. In this case, the ridge 1 is immersed in a flux, the image is recorded by the first camera 14, and after the end of the wetting period, the flip chip 3 is removed from the cavity 18 and attached to the substrate 11. The cavity 18 is positioned on a fixed position above the first camera 14 during this stage, and the field of view of the first camera 14 is directed to the base of the cavity 18, whereby the image is raised. The bottom side of the flip chip 3 having the

第１の実施形態において、融剤容器１９は静止するように配設される。この場合、デバイス１３は、プレート１７の往復運動のための駆動装置を備える。空洞１８に融剤を充填するために、空洞１８が融剤容器１９の下に、または、融剤容器１９の反対側に位置が定められる程度までプレート１７を移動させ、その後、空洞１８が第１のカメラ１４の上の前述の位置に位置が定められるように再び戻される。 In the first embodiment, the flux container 19 is arranged so as to stand still. In this case, the device 13 includes a drive device for the reciprocating motion of the plate 17. To fill the cavity 18 with the flux, the plate 17 is moved to such an extent that the cavity 18 is positioned under the flux container 19 or on the opposite side of the flux container 19, after which the cavity 18 becomes the first. It is returned again so that it is positioned at the above-mentioned position on the camera 14 of 1.

第２の実施形態では、プレート１７は静止するように配設され、ここで空洞１８は第１のカメラ１４の上に位置する。この場合、デバイス１３は、空洞１８のある側から空洞１８のその反対側までの融剤容器１９の運動のための駆動装置を備える。融剤容器１９はプレート１７上を摺動し、空洞１８に融剤を充填する。 In the second embodiment, the plate 17 is arranged to be stationary, where the cavity 18 is located above the first camera 14. In this case, the device 13 comprises a drive for the movement of the flux container 19 from one side of the cavity 18 to the opposite side of the cavity 18. The flux container 19 slides on the plate 17 and fills the cavity 18 with the flux.

第２のカメラ１５はボンディングヘッド１０に据えられる。カメラ１５の光軸は、ボンディングヘッド１０の把持軸に平行に延在する。第２のカメラ１５は、第２のカメラ１５の画像に割り当てられる画素座標系の配向がボンディングヘッド１０の把持軸に対して固定された幾何学的関係にあるように、ボンディングヘッド１０に機械的に据えられる。基板位置の少なくとも１つの画像によって、または、第２のカメラ１５によって記録される基板上のマーキングによって判断される基板位置の画素座標は、第２の幾何学的データによって、ボンディングヘッド１０の機械座標に変換される。 The second camera 15 is mounted on the bonding head 10. The optical axis of the camera 15 extends parallel to the gripping axis of the bonding head 10. The second camera 15 mechanically attaches to the bonding head 10 so that the orientation of the pixel coordinate system assigned to the image of the second camera 15 has a fixed geometric relationship with respect to the gripping axis of the bonding head 10. It is installed in. The pixel coordinates of the substrate position as determined by at least one image of the substrate position or by the markings on the substrate recorded by the second camera 15 are the mechanical coordinates of the bonding head 10 according to the second geometric data. Is converted to.

第２の幾何学的データは、ボンディングヘッド１０の機械座標系の基準点から第２のカメラ１５の画素座標系の基準点までの方向および距離を指定する、値（ｘ、ｙ）を有するベクトルＢを含む。第２の幾何学的データは、これら２つの座標系のねじれを示す角度ψをさらに含む。 The second geometric data is a vector having a value (x, y) that specifies the direction and distance from the reference point of the mechanical coordinate system of the bonding head 10 to the reference point of the pixel coordinate system of the second camera 15. Including B. The second geometric data further includes an angle ψ indicating the twist of these two coordinate systems.

第１および第２の幾何学的データは、対応するカメラの画素座標系における値をボンディングヘッド１０の機械座標系における値に変換できるようにするスケーリング因子をさらに含む。第１および第２の幾何学的データは、取り付け段階前に実行される較正段階において判断される。較正段階は、装置および方法の長期安定性を高めるために、異なる時点で実行できる。 The first and second geometric data further include scaling factors that allow the values in the pixel coordinate system of the corresponding camera to be converted into the values in the mechanical coordinate system of the bonding head 10. The first and second geometric data are determined in the calibration step performed before the mounting step. The calibration steps can be performed at different times to increase the long-term stability of the device and method.

記載された装置の実施形態は、基板にフリップチップとしての半導体チップを取り付けるための、本発明による方法を実行することができる。本発明による方法は、一方では、第１および第２の幾何学的データが判断される前述の較正段階、および、それぞれの半導体チップに対して以下のステップ：
ウエハテーブル４によって半導体チップ２を所定の位置に設けるステップ；
設けられた半導体チップ２をフリップ装置５のピックアップヘッド６によって除去し、かつ、半導体チップ２を１８０度ねじることでフリップチップ３として半導体チップ２を設けるステップ；または
送給デバイスによってフリップチップとしての半導体チップ２を設けるステップ、のいずれかのステップと；
移送ヘッド８によって、ピックアップヘッド６または送給デバイスからフリップチップ３を受け取るステップと；
プレート１７に配設されかつ透明基部が形成されている空洞１８に融剤を充填するステップであって、プレート１７は、静止するように配設される、または、空洞１８の充填後移動させられることによって、空洞１８は双方の場合において第１のカメラ１４の上に位置が定められるステップと；
フリップチップ３を空洞１８に載置するステップであって、隆起部１は空洞１８の基部に面するステップと；
フリップチップ３の画像を第１のカメラ１４によって記録し、かつ、該画像および第１の幾何学的データに基づいてボンディングヘッド１０の機械座標系に対するフリップチップ３の実際の位置付けを判断するステップと；
フリップチップ３をボンディングヘッド１０によって空洞１８から除去するステップと；
ボンディングヘッド１０の機械座標系に対する基板位置の実際の位置付けを：
基板位置が第２のカメラ１５の視野にある、基板位置の上の位置へボンディングヘッド１０を移動させること、
少なくとも１つの画像を第２のカメラ１５によって記録すること、および
少なくとも１つの画像および第２の幾何学的データにおける基板位置に基づいて基板位置の実際の位置付けを計算すること；または：
少なくとも２つの基板マーキングの実際の位置付けによって基板位置の実際の位置付けを計算することであって、少なくとも２つの基板マーキングのそれぞれの実際の位置付けは、新しい基板１１を支持部１２へ送給後：
基板マーキングが第２のカメラ１５の視野にある基板１１の上の位置へボンディングヘッド１０を移動させること、
画像を第２のカメラ１５によって記録すること、および
該画像および第２の幾何学的データによって基板マーキングの実際の位置付けを判断すること、
によってそれぞれ判断される、計算すること；および、
判断された、フリップチップ３の実際の位置付け、および、判断された、基板位置の実際の位置付けに基づいてボンディングヘッド１０が接近する位置付けを計算すること、
のいずれかによって判断するステップと；
ボンディングヘッド１０を計算された位置へ移動させ、かつ、フリップチップ３を基板位置に配置するステップと、
が実行される取り付け段階を含む。 Embodiments of the described apparatus can carry out the method according to the invention for attaching a semiconductor chip as a flip chip to a substrate. The method according to the invention, on the one hand, is the above-mentioned calibration step in which the first and second geometric data are determined, and the following steps for each semiconductor chip:
Step of providing the semiconductor chip 2 in a predetermined position by the wafer table 4;
The step of removing the provided semiconductor chip 2 by the pickup head 6 of the flip device 5 and providing the semiconductor chip 2 as the flip chip 3 by twisting the semiconductor chip 2 by 180 degrees; or the semiconductor as the flip chip by the feeding device. With any of the steps of providing the chip 2;
With the step of receiving the flip chip 3 from the pickup head 6 or the feeding device by the transfer head 8;
A step of filling a cavity 18 having a transparent base formed on the plate 17 with a flux, the plate 17 being arranged to stand still or being moved after filling the cavity 18. Thereby, the cavity 18 is positioned above the first camera 14 in both cases;
The step of placing the flip chip 3 in the cavity 18 and the step of the raised portion 1 facing the base of the cavity 18;
A step of recording an image of the flip chip 3 by the first camera 14 and determining the actual position of the flip chip 3 with respect to the mechanical coordinate system of the bonding head 10 based on the image and the first geometric data. ;
With the step of removing the flip chip 3 from the cavity 18 by the bonding head 10;
The actual positioning of the board position with respect to the mechanical coordinate system of the bonding head 10:
Moving the bonding head 10 to a position above the board position where the board position is in the field of view of the second camera 15.
Recording at least one image with the second camera 15 and calculating the actual position of the substrate position based on the substrate position in at least one image and the second geometric data; or:
The actual positioning of the substrate position is calculated by the actual positioning of at least two substrate markings, the actual positioning of each of the at least two substrate markings after feeding the new substrate 11 to the support part 12:
Moving the bonding head 10 to a position above the board 11 where the board marking is in the field of view of the second camera 15.
Recording an image with a second camera 15 and determining the actual positioning of the substrate marking from the image and the second geometric data.
To calculate, as judged by, respectively;
Calculating the position where the bonding head 10 approaches based on the determined actual position of the flip chip 3 and the determined actual position of the substrate position.
Steps to judge by either;
The step of moving the bonding head 10 to the calculated position and arranging the flip chip 3 at the substrate position.
Includes the installation stage where is performed.

ピックアップヘッド６または送給デバイスからフリップチップ３を受け取り、かつ、前記チップを空洞１８に配置する移送ヘッド８、および、フリップチップ３を空洞１８から除去し、かつ、前記チップを基板１１上に配置するボンディングヘッド１０を装置に装備させることによって、装置のスループットを高めることができるが、これは、移送ヘッド８およびボンディングヘッド１０が実質的に同時に、すなわち、平行に動作できるからである。制御デバイスは、移送ヘッド８およびボンディングヘッド１０の運動を、２つのヘッドが互いに衝突せずに少なくとも部分的に同時に動くように制御するようにセットアップされる。装置の最大可能スループットに関して、制御デバイスは、特に、方法の個々のステップのシーケンスを制御するようにプログラムされることで、ボンディングヘッド１０が空洞１８から取り付けられるべき次のフリップチップ３を除去すると、移送ヘッド８が、個々の工程ステップの継続時間に基づいてできるだけ迅速に、次に続くフリップチップ３を空洞１８に配置するようにする。 The transfer head 8 that receives the flip chip 3 from the pickup head 6 or the feeding device and places the chip in the cavity 18, and the flip chip 3 are removed from the cavity 18 and the chip is placed on the substrate 11. By equipping the device with the bonding head 10, the throughput of the device can be increased because the transfer head 8 and the bonding head 10 can operate substantially simultaneously, that is, in parallel. The control device is set up to control the movements of the transfer head 8 and the bonding head 10 so that the two heads move at least partially simultaneously without colliding with each other. With respect to the maximum possible throughput of the device, the control device is specifically programmed to control the sequence of individual steps of the method so that the bonding head 10 removes the next flip chip 3 to be mounted from the cavity 18. The transfer head 8 arranges the subsequent flip-chip 3 in the cavity 18 as quickly as possible based on the duration of the individual process steps.

図１は、フリップチップ装置５のピックアップヘッド６が半導体チップ２をウエハテーブル４から取り、フリップチップ３が空洞１８に配置されており、ボンディングヘッド１０が、融剤で濡らされたフリップチップ３を基板１１へ移送する時点の装置を示す。 In FIG. 1, the pickup head 6 of the flip chip device 5 takes the semiconductor chip 2 from the wafer table 4, the flip chip 3 is arranged in the cavity 18, and the bonding head 10 has the flip chip 3 wetted with a flux. The device at the time of transfer to the substrate 11 is shown.

第１のカメラ１４によって記録されるフリップチップ３の画像を使用して、フリップチップ３の実際の位置付けの判断に加えて、隆起部１全てが存在するおよび／または正確に濡らされているかどうかをチェックすることもできる。さらに、第１のカメラ１４は、フリップチップ３の画像を次々に記録することができ、画像処理ソフトウェアは画像を評価し、かつ、隆起部１全てが正確に濡らされているかどうかチェックすることができ、この時に、ボンディングヘッド１０がフリップチップ３を空洞１８から即座に除去し、かつ、該フリップチップ３を基板位置に配置しなければならないというメッセージを発することができる。 Using the image of the flip chip 3 recorded by the first camera 14, in addition to determining the actual positioning of the flip chip 3, whether the entire ridge 1 is present and / or is accurately wetted. You can also check. Further, the first camera 14 can record the images of the flip chip 3 one after another, and the image processing software can evaluate the images and check whether all the raised portions 1 are accurately wetted. At this time, the bonding head 10 can immediately remove the flip chip 3 from the cavity 18 and issue a message that the flip chip 3 must be placed at the substrate position.

第２のカメラ１５の視角が比較的小さいことによって、基板位置全体が画像内に適合しない場合、ボンディングヘッド１０は、有利には、種々の位置付けへと移動させられ、画像は、基板位置の一部を含むそれぞれの位置付けで記録される。次いで、基板位置の位置付けおよび配向はこれらの画像に基づいて判断される。 If the entire substrate position does not fit within the image due to the relatively small viewing angle of the second camera 15, the bonding head 10 is advantageously moved to various positions and the image is one of the substrate positions. It is recorded in each position including the part. The positioning and orientation of the substrate position is then determined based on these images.

第１の製造モードでは、フリップチップが位置付けられるべき基板位置の位置付けは、基板位置の少なくとも１つの画像に基づいて判断される。第２の製造モードでは、その位置付けは、新しい基板を送給後基板マーキングに基づいて一旦判断され、その後、フリップチップの個々の目標位置付けは幾何学的材料データによって計算される。このような応用は「ウエハレベルパッケージング」（ＷＬＢ）であり、この場合、基板はウエハであり、当該ウエハ上でプラスチックが成型される。ウエハは、個々の基板位置のいずれの位置付けマーキングも含まず、ウエハの縁近くに付される基板マーキングを含む。 In the first manufacturing mode, the positioning of the substrate position where the flip chip should be positioned is determined based on at least one image of the substrate position. In the second manufacturing mode, the positioning is once determined based on the board markings after feeding the new substrate, after which the individual target positioning of the flip chips is calculated by the geometric material data. Such an application is "wafer level packaging" (WLB), in which the substrate is a wafer and plastic is molded on the wafer. Wafers do not include any positioning markings for individual substrate positions, but include substrate markings that are placed near the edges of the wafer.

温度の変化によって引き起こされる基板位置上のフリップチップ３の位置付けエラーを排除するために、第１の光学マーキング２２の位置付けは、較正段階において判断され、かつ：
第１の光学マーキング２２が第２のカメラ１５の視野にある位置へボンディングヘッド１０を移動させること；
画像を第２のカメラ１５によって記録すること；
該画像および第２の幾何学的データに基づいて第１の光学マーキング２２の位置付けを判断すること；および
判断された位置付けを第１の光学マーキング２２の新しい位置付けとして記憶すること、によって、１つまたはいくつかの所定の時点で更新される。 In order to eliminate the positioning error of the flip chip 3 on the substrate position caused by the change in temperature, the positioning of the first optical marking 22 is determined in the calibration stage and:
Moving the bonding head 10 to a position where the first optical marking 22 is in the field of view of the second camera 15;
Recording images with a second camera 15;
One by determining the position of the first optical marking 22 based on the image and the second geometric data; and by storing the determined position as a new position of the first optical marking 22. Or it will be updated at some time point.

プレート１７の空洞１８の位置が第１のカメラ１４の上の位置付けに定められる時に光学マーキング（複数可）がプレート１７によって覆われる場合、方法は、光学マーキング（複数可）２２、２３の位置付け（複数可）が更新される前に、光学マーキング（複数可）２２、２３が現れる位置付けへとプレート１７を移動させることをさらに含む。 If the optical markings (s) are covered by the plate 17 when the cavity 18 of the plate 17 is positioned above the first camera 14, the method is to position the optical markings (s) 22, 23 (s). It further includes moving the plate 17 to a position where the optical markings (s) 22 and 23 appear before the (s) are updated.

よって、本発明は、第１のカメラ１４が固定されるカメラ支持部１６に付される１つまたはいくつかの光学マーキングが、現在の要件を満たすレベルまで、基板位置上のフリップチップ３の位置付け時に、第１のカメラ１４の画素座標系と、第２のカメラ１５の画素座標系と、ボンディングヘッド１０の機械座標系との間の変化の影響を低減するのに十分であるという見出された事柄を活用する。 Thus, the present invention positions the flip chip 3 on the substrate position until one or more optical markings on the camera support 16 to which the first camera 14 is fixed meet current requirements. Occasionally, it has been found to be sufficient to reduce the effects of changes between the pixel coordinate system of the first camera 14, the pixel coordinate system of the second camera 15, and the mechanical coordinate system of the bonding head 10. Take advantage of what you have done.

１つまたはいくつかのさらなる光学マーキング、例えば、光学マーキング２３が存在する場合、さらなる光学マーキング（複数可）の位置付けは、較正段階時の同様のやり方で判断され、かつ、前述の時点で更新される。 If one or some additional optical markings, such as the optical marking 23, are present, the positioning of the additional optical markings (s) are determined in a similar manner during the calibration phase and updated at the time mentioned above. The optics.

有利には、２つのピックアンドプレースシステムが設けられ、そのシステムのそれぞれは、ピックアップヘッド６を有するフリップ装置５、移送ヘッド８を有する第１の移送システム７、ボンディングヘッド１０を有する第２の移送システム９、フリップチップを融剤で濡らすためのデバイス１３、ならびに、第１のカメラ１４および第２のカメラ１５を備える。該システムは、ウエハテーブル４から半導体チップ２を交互に収集し、かつ、該半導体チップ２をフリップチップ３として、支持部１２上に設けられる基板１１に交互に取り付ける。 Advantageously, two pick-and-place systems are provided, each of which has a flip device 5 with a pickup head 6, a first transfer system 7 with a transfer head 8, and a second transfer with a bonding head 10. It includes a system 9, a device 13 for wetting the flip chip with a flux, and a first camera 14 and a second camera 15. The system alternately collects semiconductor chips 2 from the wafer table 4 and alternately attaches the semiconductor chips 2 as flip chips 3 to a substrate 11 provided on the support portion 12.

本発明による方法によって、以下の利点がもたらされる：
−空洞からのフリップチップの除去と同じ位置で空洞にフリップチップを配置することによって、第１の位置から第２の位置への空洞の運動によって空洞における融剤の分布が変更されないように、かつ、フリップチップの隆起部の濡れに悪影響を与える可能性がある、または、装置のスループットの低減につながる可能性のある、フリップチップの空洞におけるずれが生じないように徹底される。
−フリップチップの隆起部が融剤に浸漬される間の継続時間は他の工程ステップから独立して調節できる。このことは、一方でフリップチップの隆起部の最適な濡れを実現するために、他方で最大可能スループットを実現するために重要である。
−移送ヘッドおよびボンディングヘッドを装備することによって、かつ、移送ヘッドおよびボンディングヘッドを同時に平行に動作させることによって、装置のスループットが高められる。 The method according to the invention provides the following advantages:
-By placing the flip-chip in the cavity in the same position as the removal of the flip-chip from the cavity, the movement of the cavity from the first position to the second position does not change the distribution of the flux in the cavity, and Thoroughly ensure that there are no shifts in the flip-chip cavity that can adversely affect the wetting of the flip-chip ridges or reduce the throughput of the device.
-The duration during which the flip-chip ridge is immersed in the flux can be adjusted independently of the other process steps. This is important on the one hand to achieve optimal wetting of the flip-chip ridges and on the other hand to achieve maximum possible throughput.
-By equipping the transfer head and bonding head, and by operating the transfer head and bonding head in parallel at the same time, the throughput of the device is increased.

この発明の実施形態および応用を示しかつ説明したが、本明細書における発明の概念から逸脱することなく、上述されるものよりもさらに多くの修正が可能であるという利点がこの開示にあることは、当業者には明らかとなろう。従って、本発明は、添付の特許請求の範囲およびそれらの等価物の趣旨を除いて制限されるものではない。 Although the embodiments and applications of the present invention have been shown and described, the disclosure has the advantage that more modifications can be made than those described above without departing from the concept of the invention herein. , Will be obvious to those skilled in the art. Therefore, the present invention is not limited except for the scope of the appended claims and the gist of their equivalents.

Claims (4)

隆起部（１）が設けられている半導体チップ（２）を基板（１１）の基板位置に取り付けるための方法であって、較正段階では第１および第２の幾何学的データが判断され、取り付け段階ではそれぞれの半導体チップ（２）に対して以下のステップ：
ウエハテーブル（４）によって前記半導体チップ（２）を所定の位置に設け、かつ、設けられた前記半導体チップ（２）をフリップ装置（５）のピックアップヘッド（６）によって除去し、かつ、前記半導体チップ（２）を１８０度ねじることでフリップチップ（３）として前記半導体チップ（２）を設けるステップ、または
送給デバイスによってフリップチップ（３）としての前記半導体チップ（２）を設けるステップ、のいずれかのステップと、
移送ヘッド（８）によって、前記ピックアップヘッド（６）または前記送給デバイスから前記フリップチップ（３）を受け取るステップと、
プレート（１７）に配設されかつ透明基部が形成されている空洞（１８）に融剤を充填するステップであって、前記プレート（１７）は、静止するように配設される、または、前記空洞（１８）の充填後移動させられることによって、前記空洞（１８）は双方の場合において静止するように配設される第１のカメラ（１４）の上に位置が定められるステップと、
前記フリップチップ（３）を前記空洞（１８）に載置するステップであって、前記隆起部（１）は前記空洞（１８）の前記基部に面するステップと、
前記フリップチップ（３）の画像を前記第１のカメラ（１４）によって記録し、かつ、前記画像および前記第１の幾何学的データに基づいてボンディングヘッド（１０）の機械座標系に対する前記フリップチップ（３）の実際の位置付けを判断するステップと、
前記フリップチップ（３）を前記ボンディングヘッド（１０）によって前記空洞（１８）から除去するステップと、
前記ボンディングヘッド（１０）に据えられる第２のカメラ（１５）による前記ボンディングヘッド（１０）の前記機械座標系に対する前記基板位置の実際の位置付けを：
前記基板位置が前記第２のカメラ（１５）の視野にある、前記基板位置の上の位置へ前記ボンディングヘッド（１０）を移動させること、
少なくとも１つの画像を前記第２のカメラ（１５）によって記録すること、および
前記少なくとも１つの画像および前記第２の幾何学的データにおける前記基板位置の位置付けに基づいて前記基板位置の前記実際の位置付けを計算すること、または、
少なくとも２つの基板マーキングの実際の位置付けによって前記基板位置の前記実際の位置付けを計算することであって、前記少なくとも２つの基板マーキングのそれぞれの前記実際の位置付けは、新しい基板（１１）を支持部（１２）へ送給後：
前記基板マーキングが前記第２のカメラ（１５）の視野にある、前記基板の上の位置へ前記ボンディングヘッド（１０）を移動させること、
画像を前記第２のカメラ（１５）によって記録すること、および
前記画像および前記第２の幾何学的データによって前記基板マーキングの前記実際の位置付けを判断すること、
によって判断される、計算すること、
のいずれかによって判断するステップと、
判断された、前記フリップチップ（３）の実際の位置付け、および、判断された、前記基板位置の実際の位置付けに基づいて前記ボンディングヘッド（１０）が接近する位置付けを計算するステップと、
前記ボンディングヘッド（１０）を、計算された前記ボンディングヘッド（１０）が接近する前記位置付けへ移動させ、かつ、前記フリップチップ（３）を前記基板位置に配置するステップと、が実行され、
前記移送ヘッド（８）および前記ボンディングヘッド（１０）は少なくとも一部同時に動く、方法。 This is a method for mounting the semiconductor chip (2) provided with the raised portion (1) at the substrate position of the substrate (11). In the calibration stage, the first and second geometric data are determined and mounted. In the stage, the following steps for each semiconductor chip (2):
The semiconductor chip (2) is provided at a predetermined position by the wafer table (4) , the provided semiconductor chip (2) is removed by the pickup head (6) of the flip device (5), and the semiconductor. Either a step of providing the semiconductor chip (2) as a flip chip (3) by twisting the chip (2) 180 degrees, or a step of providing the semiconductor chip (2) as a flip chip (3) by a feeding device. That step and
A step of receiving the flip chip (3) from the pickup head (6) or the feeding device by the transfer head (8).
A step of filling a cavity (18) arranged in a plate (17) and having a transparent base formed with a flux, wherein the plate (17) is arranged to stand still or said. A step in which the cavity (18) is positioned above a first camera (14) that is arranged to be stationary in both cases by being moved after filling the cavity (18).
A step of placing the flip chip (3) in the cavity (18), wherein the raised portion (1) faces the base of the cavity (18).
The image of the flip chip (3) is recorded by the first camera (14), and the flip chip with respect to the mechanical coordinate system of the bonding head (10) based on the image and the first geometric data. The step of determining the actual position of (3) and
A step of removing the flip chip (3) from the cavity (18) by the bonding head (10), and
The actual positioning of the substrate position of the bonding head (10) with respect to the mechanical coordinate system by the second camera (15) mounted on the bonding head (10) is:
Moving the bonding head (10) to a position above the substrate position where the substrate position is in the field of view of the second camera (15).
The actual positioning of the substrate position based on the recording of at least one image by the second camera (15) and the positioning of the substrate position in the at least one image and the second geometric data. To calculate, or
The actual positioning of the substrate position is to calculate the actual positioning of the substrate position by the actual positioning of at least two substrate markings, the actual positioning of each of the at least two substrate markings supporting a new substrate (11). After sending to 12):
Moving the bonding head (10) to a position above the substrate where the substrate marking is in the field of view of the second camera (15).
Recording the image with the second camera (15), and determining the actual positioning of the substrate marking from the image and the second geometric data.
Judging by, calculating,
Steps to judge by either, and
A step of calculating the determined actual positioning of the flip chip (3) and the determined positioning of the bonding head (10) to approach based on the determined actual positioning of the substrate position.
The step of moving the bonding head (10) to the position where the calculated bonding head (10) approaches and arranging the flip chip (3) at the substrate position is executed.
A method in which the transfer head (8) and the bonding head (10) move at least in part at the same time. 前記第１の幾何学的データは、第１の光学マーキング（２２）の位置付けおよび第１の固定ベクトルを含み、それらによって、前記第１のカメラ（１４）の画素座標系の基準点への前記第１の光学マーキング（２２）の方向および該基準点からの距離が指定され、前記第１の光学マーキング（２２）の前記位置付けは：
前記第１の光学マーキング（２２）が前記第２のカメラ（１５）の視野にある位置へ前記ボンディングヘッド（１０）を移動させること、
画像を前記第２のカメラ（１５）によって記録すること、
前記画像および前記第２の幾何学的データに基づいて前記第１の光学マーキング（２２）の前記位置付けを判断すること、および
判断された前記位置付けを前記第１の光学マーキング（２２）の新しい位置付けとして記憶すること、によって、少なくとも１つの所定の時点で更新される、請求項１に記載の方法。 The first geometric data includes the positioning of the first optical marking (22) and the first fixed vector, thereby the said to the reference point of the pixel coordinate system of the first camera (14). The direction of the first optical marking (22) and the distance from the reference point are specified, and the positioning of the first optical marking (22) is:
Moving the bonding head (10) to a position where the first optical marking (22) is in the field of view of the second camera (15).
Recording the image with the second camera (15),
The positioning of the first optical marking (22) is determined based on the image and the second geometric data, and the determined positioning is a new positioning of the first optical marking (22). The method of claim 1, which is updated at at least one predetermined time point by storing as. 前記第１の幾何学的データは、少なくとも１つのさらなる光学マーキング（２３）の位置付けおよびさらなる固定ベクトルを含み、これらによって、前記第１のカメラ（１４）の前記画素座標系の前記基準点への前記さらなる光学マーキングの方向および該基準点からの距離が指定され、前記さらなる光学マーキング（２３）の前記位置付けは：
前記さらなる光学マーキング（２３）が前記第２のカメラ（１５）の視野にある位置へ前記ボンディングヘッド（１０）を移動させること、
画像を前記第２のカメラ（１５）によって記録すること、
前記画像および前記第２の幾何学的データに基づいて前記さらなる光学マーキング（２３）の前記位置付けを判断すること、および
判断された前記位置付けを前記さらなる光学マーキング（２３）の新しい位置付けとして記憶すること、によって更新される、請求項２に記載の方法。 The first geometric data includes the positioning of at least one additional optical marking (23) and an additional fixed vector, thereby to the reference point of the pixel coordinate system of the first camera (14). The direction of the additional optical marking and the distance from the reference point are specified, and the positioning of the additional optical marking (23) is:
Moving the bonding head (10) to a position where the additional optical marking (23) is in the field of view of the second camera (15).
Recording the image with the second camera (15),
Determining the position of the additional optical marking (23) based on the image and the second geometric data, and storing the determined position as a new position of the additional optical marking (23). The method of claim 2, which is updated by. 前記プレート（１７）の前記空洞（１８）の位置が前記第１のカメラ（１４）の上の位置付けに定められる時に前記光学マーキング（複数可）が前記プレート（１７）によって覆われる場合、前記光学マーキング（複数可）（２２、２３）の位置付け（複数可）が更新される前に、前記光学マーキング（複数可）（２２、２３）が現れる位置付けへと前記プレート（１７）を移動させることをさらに含む、請求項２または３に記載の方法。 The optics when the optical markings (s) are covered by the plate (17) when the position of the cavity (18) of the plate (17) is defined above the first camera (14). Before the positioning (s) of the markings (s) (22, 23) is updated, the plate (17) is moved to the position where the optical markings (s) (22, 23) appear. The method of claim 2 or 3, further comprising.
JP2016156305A 2015-08-31 2016-08-09 A method for mounting a semiconductor provided with a raised portion at a substrate position on a substrate. Active JP6868982B2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
CH01248/15 2015-08-31
CH12482015 2015-08-31
CH01404/15 2015-09-28
CH01404/15A CH711536B1 (en) 2015-08-31 2015-09-28 Method for mounting bumped semiconductor chips on substrate sites of a substrate.

Publications (3)

Publication Number Publication Date
JP2017050533A JP2017050533A (en) 2017-03-09
JP2017050533A5 JP2017050533A5 (en) 2019-09-05
JP6868982B2 true JP6868982B2 (en) 2021-05-12

Family

ID=58264157

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016156305A Active JP6868982B2 (en) 2015-08-31 2016-08-09 A method for mounting a semiconductor provided with a raised portion at a substrate position on a substrate.

Country Status (7)

Country Link
JP (1) JP6868982B2 (en)
KR (1) KR102597252B1 (en)
CN (1) CN106486400B (en)
CH (1) CH711536B1 (en)
MY (1) MY176667A (en)
SG (1) SG10201606167WA (en)
TW (1) TWI700767B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7164314B2 (en) * 2017-04-28 2022-11-01 ベシ スウィッツァーランド エージー APPARATUS AND METHOD FOR MOUNTING COMPONENTS ON SUBSTRATE
CN109079367B (en) * 2018-07-23 2020-07-24 中电科技（合肥）博微信息发展有限责任公司 Intelligent chip welding method

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5372294A (en) * 1994-01-27 1994-12-13 Motorola, Inc. Method of preparing a component for automated placement
JP2833996B2 (en) * 1994-05-25 1998-12-09 日本電気株式会社 Flexible film and semiconductor device having the same
JPH10209208A (en) * 1997-01-23 1998-08-07 Hitachi Ltd Method and device for manufacturing semiconductor
US7842599B2 (en) * 1997-05-27 2010-11-30 Wstp, Llc Bumping electronic components using transfer substrates
JP2001060795A (en) * 1999-08-20 2001-03-06 Matsushita Electric Ind Co Ltd Electronic parts mounting device
US7033842B2 (en) * 2002-03-25 2006-04-25 Matsushita Electric Industrial Co., Ltd. Electronic component mounting apparatus and electronic component mounting method
JP4334892B2 (en) * 2003-03-20 2009-09-30 パナソニック株式会社 Component mounting method
JP4516354B2 (en) * 2004-05-17 2010-08-04 パナソニック株式会社 Parts supply method
JP2007173801A (en) * 2005-12-22 2007-07-05 Unaxis Internatl Trading Ltd Method of fitting flip chip to substrate
JP2008168225A (en) * 2007-01-12 2008-07-24 Fujifilm Corp Slit coating method and apparatus, and method for manufacturing color filter
CH698718B1 (en) * 2007-01-31 2009-10-15 Oerlikon Assembly Equipment Ag A device for mounting a flip chip on a substrate.
CH698720B1 (en) * 2007-02-14 2009-10-15 Oerlikon Assembly Equipment Ag The method and assembly machine for the assembly of semiconductor chips as a flip chip on a substrate.
CH698334B1 (en) * 2007-10-09 2011-07-29 Esec Ag A process for the removal and installation of a wafer table provided on the semiconductor chip on a substrate.
JP5030843B2 (en) * 2008-04-14 2012-09-19 芝浦メカトロニクス株式会社 Electronic component mounting apparatus and mounting method
JP4983737B2 (en) * 2008-06-30 2012-07-25 株式会社日立プラントテクノロジー Solder ball inspection repair device and solder ball inspection repair method
JP4766144B2 (en) * 2009-04-08 2011-09-07 パナソニック株式会社 Electronic component mounting equipment
KR101120129B1 (en) * 2009-08-31 2012-03-23 (주) 에스에스피 Method of adjusting work position automatically by reference value and automatic apparatus for the same
JP2011181675A (en) * 2010-03-01 2011-09-15 Nec Corp Mounting device for circuit component
CH705802B1 (en) * 2011-11-25 2016-04-15 Esec Ag Means for the mounting of semiconductor chips.
JP6000626B2 (en) * 2012-05-01 2016-10-05 新光電気工業株式会社 Electronic device manufacturing method and electronic component mounting apparatus
JP6391225B2 (en) * 2013-09-13 2018-09-19 ファスフォードテクノロジ株式会社 Flip chip bonder and flip chip bonding method
JP6200737B2 (en) * 2013-09-17 2017-09-20 ファスフォードテクノロジ株式会社 Die bonder dipping mechanism and flip chip bonder
JP2015076411A (en) * 2013-10-04 2015-04-20 株式会社日立ハイテクインスツルメンツ Die bonder
JP6324772B2 (en) * 2014-03-14 2018-05-16 ファスフォードテクノロジ株式会社 Die bonder dipping mechanism and flip chip bonder

Also Published As

Publication number Publication date
SG10201606167WA (en) 2017-03-30
CH711536B1 (en) 2019-02-15
TW201735227A (en) 2017-10-01
CN106486400B (en) 2021-10-29
KR102597252B1 (en) 2023-11-01
CN106486400A (en) 2017-03-08
KR20170026136A (en) 2017-03-08
JP2017050533A (en) 2017-03-09
CH711536A1 (en) 2017-03-15
MY176667A (en) 2020-08-19
TWI700767B (en) 2020-08-01

Similar Documents

Publication Publication Date Title
US9721819B2 (en) Method for mounting semiconductors provided with bumps on substrate locations of a substrate
KR101901541B1 (en) Method and apparatus for automatically adjusting dispensing units of a dispenser
KR101560322B1 (en) Method and apparatus for dispensing material on a substrate
JP6584234B2 (en) Die bonder, bonding method and semiconductor device manufacturing method
JP6835808B2 (en) Use of mountable marker parts for stepwise mounting of parts on the carrier
CN105365215A (en) Correction device and correction method for three-dimensional line printing device
EP3322275B1 (en) Mounting device, photographic processing method, and photographic unit
JP6868982B2 (en) A method for mounting a semiconductor provided with a raised portion at a substrate position on a substrate.
US6976616B2 (en) Circuit board transferring apparatus and method and solder ball mounting method
US7918017B2 (en) Electronic component taking out apparatus
TW202111455A (en) Methods of positioning components in desired positions on a board
JP2008132440A (en) Method and apparatus for filling liquid material
US10784130B2 (en) Bonding apparatus
JPWO2020003384A1 (en) Flatness acquisition system and mounting machine
TWI798619B (en) Die bonding device and method for manufacturing semiconductor device
JP2013171990A (en) Cutting device
JP6851118B2 (en) Parts quality judgment device and electronic component mounting machine
JP2011181675A (en) Mounting device for circuit component
JP6892764B2 (en) Board mounting machine
CN106937525B (en) Image generation device, installation device, and image generation method
JP7095089B2 (en) Mounting machine and mounting system
JP6804905B2 (en) Board work equipment
CN110381716B (en) Mounting device and mounting method
JP6629617B2 (en) Component mounting machine, component mounting method
JP2003152396A (en) Electronic component mounting method and apparatus therefor

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20190723

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20190724

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20191105

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20200820

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20200929

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20201016

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20210330

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20210413

R150 Certificate of patent or registration of utility model

Ref document number: 6868982

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150