JP6867768B2 - Thermal print head - Google Patents

Description

The present invention relates to a thermal print head.

Conventionally known thermal printheads include a substrate, a resistor layer, and a wiring layer. Such a thermal print head is disclosed in, for example, Patent Document 1. In the thermal printhead disclosed in the same document, the resistor layer and the wiring layer are formed on the substrate. The resistor layer has a plurality of heat generating portions arranged in the main scanning direction.

In order to perform finer printing, it is necessary to reduce the pitch of a plurality of heat generating portions. Along with this, it is required to form the wiring layer more finely. Therefore, there is a problem that the fineness of printing is hindered by the degree of fine formation of the wiring layer. Further, the conduction path including the wiring layer is required to fulfill a smooth conduction function.

Japanese Unexamined Patent Publication No. 2012-51319

The present invention has been conceived under the above circumstances, and an object of the present invention is to provide a thermal print head capable of achieving finer printing and smoother conduction function. ..

The thermal printhead provided by the present invention comprises a semiconductor substrate, a resistor layer supported by the semiconductor substrate and having a plurality of heat generating portions arranged in the main scanning direction to generate heat by energization, and a resistor layer on the resistor layer. A thermal printed head including a wiring layer formed and included in a conduction path for energizing the plurality of heat generating portions, the semiconductor substrate containing Si, and the conduction path being the semiconductor substrate and the said. It is characterized by including a polyolefin layer interposed between the semiconductor substrate and the resistor layer.

In a preferred embodiment of the invention, the silicide layer comprises at least one of Ti, Ta, Co and Ni.

In a preferred embodiment of the present invention, the wiring layer is arranged on a side opposite to the plurality of individual electrodes, each of which is separately connected to the plurality of heat generating portions, and the plurality of individual electrodes with the plurality of heat generating portions interposed therebetween. It has a common electrode that has a portion and is conductive with the plurality of heat generating portions, and the common electrode and the semiconductor substrate are conductive.

In a preferred embodiment of the present invention, an insulating protective layer covering the wiring layer and the resistor layer is provided.

In a preferred embodiment of the present invention, an insulating layer provided between the semiconductor substrate, the wiring layer, and the resistor layer is provided, and the insulating layer comprises the semiconductor substrate and the common electrode. It has a first opening for a common electrode to be conductive.

In a preferred embodiment of the present invention, the silicide layer is formed in all the regions where the insulating layer and the semiconductor substrate overlap.

In a preferred embodiment of the present invention, the insulating layer and the semiconductor substrate are in contact with each other.

In a preferred embodiment of the present invention, the first opening for the common electrode has a shape extending long in the main scanning direction.

In a preferred embodiment of the present invention, the resistor layer has a resistance-side first through conduction portion located in the common electrode first opening, and the silicide layer has the resistance-side first through conduction. It has a first intervening portion on the resistance side that is interposed between the portion and the semiconductor substrate.

In a preferred embodiment of the present invention, the common electrode has a wiring-side first through conductive portion in contact with the resistance-side first through conductive portion.

In a preferred embodiment of the present invention, the insulating layer is located on the side opposite to the first opening for the common electrode in the sub-scanning direction with the plurality of heat generating portions interposed therebetween, and the semiconductor substrate and the common electrode are used. Has a second opening for a common electrode to conduct electricity.

In a preferred embodiment of the present invention, the resistor layer has a resistance-side second through conduction portion located in the second opening for the common electrode, and the silicide layer has the resistance-side second through conduction. It has a second intervening portion on the resistance side that is interposed between the portion and the semiconductor substrate.

In a preferred embodiment of the present invention, the common electrode has a wiring-side second through-conducting portion in contact with the resistance-side second through-conducting portion.

In a preferred embodiment of the present invention, a plurality of control elements that conduct the wiring layer and individually energize the plurality of heat generating portions are provided.

In a preferred embodiment of the present invention, the second opening for the common electrode overlaps the control element in the thickness direction.

In a preferred embodiment of the present invention, the insulating protective layer has an opening for a control element that exposes at least a part of each of the plurality of individual electrodes and the common electrode.

In a preferred embodiment of the present invention, a control element pad formed in the control element opening is provided.

In a preferred embodiment of the present invention, the control element is conductively bonded to the control element pad.

In a preferred embodiment of the present invention, the insulating protective layer is located on the side opposite to the plurality of heat generating portions with respect to the control element in the sub-scanning direction, and is an opening for a wiring member that exposes the wiring layer. Has.

In a preferred embodiment of the present invention, a wiring member pad formed in the wiring member opening is provided.

In a preferred embodiment of the present invention, the wiring member is joined to the wiring member pad.

In a preferred embodiment of the present invention, the wiring member is a flexible wiring board.

In a preferred embodiment of the present invention, the semiconductor substrate has a main surface and a back surface facing opposite sides in the thickness direction, and a convex portion protruding from the main surface in the thickness direction and extending long in the main scanning direction. And, the plurality of heat generating portions overlap with the convex portion in the thickness direction view.

In a preferred embodiment of the present invention, the main surface has a first region and a second region that are separated from each other in the sub-scanning direction with the convex portion interposed therebetween.

In a preferred embodiment of the present invention, the convex portion is a top surface parallel to the main surface and separated from the main surface in the thickness direction, and is interposed between the top surface and the first region. It also has a first inclined side surface that is inclined with respect to the main surface, and a second inclined side surface that is interposed between the top surface and the second region and is inclined with respect to the main surface.

In a preferred embodiment of the present invention, the plurality of heat generating portions overlap with the top surface in the thickness direction.

In a preferred embodiment of the present invention, the common electrode first opening overlaps the first region in the thickness direction.

In a preferred embodiment of the present invention, the second opening for the common electrode overlaps the second region in the thickness direction.

In a preferred embodiment of the present invention, the control element overlaps the second region in the thickness direction.

In a preferred embodiment of the present invention, a coated conductive layer covering the resistor layer at at least one of the boundary between the top surface and the first inclined side surface and the boundary between the top surface and the second inclined side surface is further provided. Be prepared.

In a preferred embodiment of the present invention, the coated conductive layer covers the resistor layer at both the boundary between the top surface and the first inclined side surface and the boundary between the top surface and the second inclined side surface.

In a preferred embodiment of the present invention, the coated conductive layer is composed of an underlying conductive layer interposed between the resistor layer and the wiring layer.

In a preferred embodiment of the present invention, the semiconductor substrate is made of a material in which Si is doped with a metal element.

In a preferred embodiment of the present invention, the resistor layer is made of TaN.

In a preferred embodiment of the present invention, the wiring layer is made of Cu.

According to the present invention, the conduction path for energizing the plurality of heat generating portions includes the semiconductor substrate. Since conduction is achieved by the semiconductor substrate, it is not necessary to form a corresponding portion as a part of the wiring layer. Thereby, it is possible to reduce the area of the wiring layer to be provided on the main surface side. As a result, it is possible to expand the area for forming the wiring layer, and to form the wiring layer more easily in response to miniaturization and narrowing of the pitch of the plurality of heat generating portions. Can be done. Therefore, the printing can be refined. Further, the silicide layer is interposed between the resistor layer and the semiconductor substrate. By interposing the silicide layer, it is possible to avoid forming an ohmic contact between the resistor layer and the semiconductor substrate and forming a Schottky contact. Thereby, the resistance characteristic between the resistor layer and the semiconductor substrate can be made a general linear characteristic. Therefore, a smoother conduction function can be realized.

Other features and advantages of the present invention will become more apparent with the detailed description given below with reference to the accompanying drawings.

It is a top view which shows the thermal print head based on 1st Embodiment of this invention. It is sectional drawing which follows the line II-II of FIG. FIG. 5 is an enlarged cross-sectional view of a main part showing the thermal print head of FIG. It is an enlarged plan view of the main part which shows the thermal print head of FIG. It is an enlarged perspective view of the main part which shows the thermal print head of FIG. It is an enlarged sectional view of the main part which shows an example of the manufacturing method of the thermal printhead of FIG. It is an enlarged sectional view of the main part which shows an example of the manufacturing method of the thermal printhead of FIG. It is an enlarged sectional view of the main part which shows an example of the manufacturing method of the thermal printhead of FIG. It is an enlarged sectional view of the main part which shows an example of the manufacturing method of the thermal printhead of FIG. It is an enlarged sectional view of the main part which shows an example of the manufacturing method of the thermal printhead of FIG. It is an enlarged sectional view of the main part which shows an example of the manufacturing method of the thermal printhead of FIG. It is an enlarged sectional view of the main part which shows an example of the manufacturing method of the thermal printhead of FIG. It is an enlarged sectional view of the main part which shows the thermal print head based on 2nd Embodiment of this invention. It is an enlarged sectional view of the main part which shows the thermal print head based on 3rd Embodiment of this invention.

Hereinafter, preferred embodiments of the present invention will be specifically described with reference to the drawings.

1 to 5 show a thermal print head based on the first embodiment of the present invention. The thermal print head A1 of the present embodiment includes a semiconductor substrate 1, an insulating layer 2, a wiring layer 3, a resistor layer 4, an insulating protective layer 5, a silicide layer 6, a surface protective layer 59, a plurality of control elements 7, and a protective resin. 8. The support member 91 and the wiring member 92 are provided. The thermal print head A1 is incorporated in a printer that prints on a print medium 992 that is sandwiched and conveyed between the platen roller 991 and the platen roller 991. Examples of such a print medium 992 include a bar code sheet and a thermal paper for producing a receipt.

FIG. 1 is a plan view showing the thermal print head A1. FIG. 2 is a cross-sectional view taken along the line II-II of FIG. FIG. 3 is an enlarged cross-sectional view of a main part showing the thermal print head A1. FIG. 4 is an enlarged plan view of a main part showing the thermal print head A1. FIG. 5 is an enlarged perspective view of a main part showing the thermal print head A1. For convenience of understanding, the support member 91 is omitted in FIG. Further, FIG. 4 shows a part of the thermal print head A1. Further, in FIG. 5, for convenience of understanding, only the semiconductor substrate 1, the wiring layer 3, the resistor layer 4, and the first opening 21 for the common electrode and the second opening 22 for the common electrode of the insulating layer 2 described later are shown. There is.

The semiconductor substrate 1 is made of a semiconductor material having a resistivity that allows energization. Examples of such a semiconductor material include a material in which Si is doped with a metal element. The semiconductor substrate 1 has a main surface 11, a back surface 12, and a convex portion 13. The semiconductor substrate 1 may have a configuration that does not have the convex portion 13.

The main surface 11 and the back surface 12 face opposite to each other in the thickness direction z. The convex portion 13 is a portion protruding from the main surface 11 in the thickness direction z. The convex portion 13 extends long in the main scanning direction x.

The main surface 11 has a first region 111 and a second region 112 that are separated from each other in the sub-scanning direction with the convex portion 13 interposed therebetween.

The convex portion 13 has a top surface 130, a first inclined side surface 131, and a second inclined side surface 132. The top surface 130 is parallel to the main surface 11 and is separated from the main surface 11 in the thickness direction. The first inclined side surface 131 is interposed between the top surface 130 and the first region 111, and is inclined with respect to the main surface 11. The second inclined side surface 132 is interposed between the top surface 130 and the second region 112, and is inclined with respect to the main surface 11.

In the present embodiment, the (100) plane is selected as the main plane 11. Further, the angles formed by the first inclined side surface 131 and the second inclined side surface 132 with the top surface 130 and the main surface 11 are the same, for example, 54.7 degrees.

The main surface 11 has a first region 111 and a second region 112. The first region 111 and the second region 112 are regions that are partitioned from each other by the convex portion 13. In the present embodiment, the second region 112 has a larger sub-scanning direction y dimension and area than the first region 111.

The size of the semiconductor substrate 1 is not particularly limited, but to give an example, the sub-scanning direction y dimension of the semiconductor substrate 1 is about 2.0 mm to 3.0 mm, and the x-direction dimension is about 100 mm to 150 mm. The z-distance in the thickness direction between the main surface 11 and the back surface 12 is about 400 μm to 500 μm, and the z-height in the thickness direction of the convex portion 13 is about 250 μm to 400 μm.

The silicide layer 6 is a layer made of a compound metal of a metal and Si, and is formed on the semiconductor substrate 1. Examples of the material of such a silicide layer 6 include a compound metal of any one of Ti, Ta, Co and Ni and Si. The thickness of the silicide layer 6 is not particularly limited, and is, for example, 0.01 μm to 0.1 μm, more preferably about 0.03 μm. In the present embodiment, the silicide layer 6 covers all of the main surface 11 and the convex portion 13 of the semiconductor substrate 1.

The insulating layer 2 is provided between the silicide layer 6, the wiring layer 3, and the resistor layer 4. The insulating layer 2 is made of an insulating material, for example, SiO ₂ , SiN or TEOS (tetraethyl orthosilicate). The thickness of the insulating layer 2 is not particularly limited, and an example thereof is, for example, 5 μm to 15 μm, preferably about 10 μm.

The insulating layer 2 has a first opening 21 for a common electrode and a second opening 22 for a common electrode. The first opening 21 for the common electrode penetrates the insulating layer 2 in the thickness direction z. In the present embodiment, the first opening 21 for the common electrode overlaps with the first region 111 in the z-view in the thickness direction. Further, the first opening 21 for the common electrode has a shape extending long in the main scanning direction x, for example, a slit shape.

The second opening 22 for the common electrode penetrates the insulating layer 2 in the thickness direction z. In the present embodiment, the second opening 22 for the common electrode overlaps with the second region 112 in the z-view in the thickness direction.

The silicide layer 6 has a resistance-side first intervening portion 61 and a resistance-side second interposing portion 62. The first intervening portion 61 on the resistance side is a portion located in the first opening 21 for the common electrode. The second intervening portion 62 on the resistance side is a portion located in the second opening 22 for the common electrode.

The resistor layer 4 is supported by the semiconductor substrate 1, and is formed on the insulating layer 2 in the present embodiment. The resistor layer 4 has a plurality of heat generating portions 41. The plurality of heat generating units 41 locally heat the print medium 992 by selectively energizing each of them. The plurality of heat generating portions 41 are arranged along the main scanning direction x. In the present embodiment, the plurality of heat generating portions 41 overlap the convex portions 13 in the thickness direction z-view, and more specifically, all of them overlap the top surface 130. The resistor layer 4 is made of, for example, TaN. The thickness of the resistor layer 4 is not particularly limited, and is, for example, 0.03 μm to 0.07 μm, preferably about 0.05 μm.

The shape of the heat generating portion 41 is not particularly limited, but in the example shown in FIG. 4, the heat generating portion 41 has a bent shape.

In the present embodiment, the resistor layer 4 has a resistance-side first through conductive portion 421 and a resistance-side second through conductive portion 422. The resistance-side first through conductive portion 421 is in contact with the resistance-side first intervening portion 61 of the silicide layer 6 through the first opening 21 for the common electrode, and is conductive to the first region 111 of the main surface 11 of the semiconductor substrate 1. There is. The second through conductive portion 422 on the resistance side is in contact with the second intervening portion 62 on the resistance side of the silicide layer 6 through the second opening 22 for the common electrode, and conducts to the second region 112 of the main surface 11 of the semiconductor substrate 1. There is.

The wiring layer 3 is for forming a conduction path for energizing the plurality of heat generating portions 41. The wiring layer 3 is supported by the semiconductor substrate 1, and in the present embodiment, the wiring layer 3 is laminated on the resistor layer 4. The wiring layer 3 is made of a metal material having a lower resistance than the resistor layer 4, and is made of, for example, Cu. Further, the wiring layer 3 may have a structure having a layer made of Cu and a layer made of Ti interposed between the layer and the resistor layer 4. The thickness of the wiring layer 3 is not particularly limited, and is, for example, 0.3 μm to 0.5 μm.

The wiring layer 3 has a plurality of individual electrodes 31 and a common electrode 32. The plurality of individual electrodes 31 are individually connected to the plurality of heat generating portions 41. In the present embodiment, the plurality of individual electrodes 31 are located on the second region 112 side in the sub-scanning direction y with respect to the plurality of heat generating portions 41.

The common electrode 32 has a portion arranged on the side opposite to the plurality of individual electrodes 31 in the sub-scanning direction y with the plurality of heat generating portions 41 interposed therebetween. Further, the common electrode 32 of the embodiment has a portion located on the second region 112 side (left side in the drawing in FIG. 3) in the sub-scanning direction y direction with respect to the plurality of individual electrodes 31. The common electrode 32 is electrically connected to all of the plurality of heat generating portions 41. Note that FIG. 3 shows a cross section crossing the common electrode 32 in the second region 112 for convenience of understanding, but in the cross section at another position in the main scanning direction x, the wiring layer 3 has a potential different from that of the common electrode 32. Has different and insulated parts.

As can be understood from FIGS. 3 and 4, in the present embodiment, the portion of the resistor layer 4 exposed from the wiring layer 3 between the plurality of individual electrodes 31 and the common electrode 32 is a plurality of heat generating portions. It is 41.

In the present embodiment, the common electrode 32 has a wiring-side first through conductive portion 321 and a wiring-side second through conductive portion 322. The wiring-side first through conductive portion 321 is in contact with the resistance-side first through conductive portion 421 of the resistor layer 4. The second through conductive portion 322 on the wiring side is in contact with the second through conductive portion 422 on the resistance side of the resistor layer 4. With such a configuration, the portion of the common electrode 32 of the wiring layer 3 that overlaps with the first region 111 in the thickness direction z is the first through conductive portion on the resistance side through the first opening 21 for the common electrode of the insulating layer 2. It is electrically connected to the semiconductor substrate 1 via the 421 and the first intervening portion 61 on the resistance side. Further, the portion of the common electrode 32 that overlaps with the second region 112 in the thickness direction z is passed through the second opening 22 for the common electrode of the insulating layer 2 to the resistance side second through conductive portion 422 and the resistance side second intervening portion 422. It is electrically connected to the semiconductor substrate 1 via 62. As a result, in the present embodiment, the conduction path for energizing the plurality of heat generating portions 41 includes the wiring layer 3, the VDD layer 6, and the semiconductor substrate 1. More specifically, the current flowing through the common electrode 32 passes through the silicide layer 6 and the semiconductor substrate 1.

The insulating protective layer 5 covers the wiring layer 3 and the resistor layer 4. The insulating protective layer 5 is made of an insulating material and protects the wiring layer 3 and the resistor layer 4. The material of the insulating protective layer 5 is, for example, SiO ₂ . The thickness of the insulating protective layer 5 is not particularly limited, and is, for example, 0.8 μm to 2.0 μm, preferably about 1.0 μm.

The insulating protective layer 5 has an opening 51 for a conductive protective layer, a plurality of openings 52 for control elements, and a plurality of openings 53 for wiring members. The opening 51 for the conductive protective layer overlaps with the first region 111 in the thickness direction z view, and exposes the common electrode 32. The conductive protective layer opening 51 has, for example, a shape that extends long in the main scanning direction x. In the illustrated example, the conductive protective layer opening 51 overlaps with the common electrode first opening 21 in the thickness direction z-view. The opening 52 for the control element overlaps with the second region 112 in the z-view in the thickness direction, and exposes the plurality of individual electrodes 31 and the common electrodes 32, respectively.

The plurality of wiring member openings 53 are provided on the side opposite to the plurality of heat generating portions 41 in the sub-scanning direction y with respect to the plurality of control element openings 52. The plurality of wiring member openings 53 expose the common electrode 32 of the wiring layer 3 and other parts of the wiring layer 3 provided at positions different from the common electrode 32 in the x direction and insulated from the common electrode 32, respectively. I'm letting you.

The surface protective layer 59 overlaps with a plurality of heat generating portions 41 and is laminated on the insulating protective layer 5 in the thickness direction z. The surface protective layer 59 is made of a conductive material, for example, AlN. The surface protective layer 59 has a portion that overlaps with the first region 111 in the thickness direction z-view, and has a protective layer penetrating conductive portion 591. The conductive portion 591 penetrating the protective layer is in contact with the common electrode 32 through the opening 51 for the conductive protective layer. The surface protective layer 59 may be formed of a material such as SiC that does not have clear conductivity. In this case, the conductive protective layer opening 51 and the protective layer penetrating conductive portion 591 may not be formed.

The plurality of control elements 7 are for conducting the wiring layer 3 and individually energizing the plurality of heat generating portions 41. The plurality of control elements 7 are arranged in the main scanning direction x. The plurality of control elements 7 overlap with the second opening 22 for the common electrode in the thickness direction z-view.

In the present embodiment, the thermal print head A1 has a control element pad 381. The control element pad 381 is made of a metal such as Cu or Ni, and is formed in the control element opening 52. The control element 7 has a plurality of control element electrodes 71. The control element electrode 71 is conductively bonded to the control element pad 381 via a conductive bonding material 79. The conductive bonding material 79 is, for example, solder.

The wiring member 92 is for conducting the wiring layer 3 with, for example, a power supply unit (not shown) of a printer. The wiring member 92 is, for example, a printed wiring board. Such a wiring member 92 has, for example, a resin layer 921, a wiring layer 922, and a protective layer 923. The resin layer 921 is made of a flexible resin. The wiring layer 922 is laminated on the resin layer 921 and is made of a metal such as Cu. The protective layer 923 is laminated on the resin layer 921 on the opposite side of the wiring layer 922, and is a layer that protects the resin layer 921 and the wiring layer 922.

The thermal print head A1 has a pad 382 for a wiring member. The wiring member pad 382 is formed in the wiring member opening 53 of the insulating protective layer 5, and is made of a metal such as Cu or Ni. The wiring layer 922 of the wiring member 92 is conductively joined to the wiring member pad 382. The thermal print head A1 has a plurality of wiring member pads 382. The wiring member pad 382 shown in FIG. 3 is conductive with the common electrode 32. Some of the plurality of wiring member pads 382 are conducting to other portions of the wiring layer 3 that are insulated from the common electrode 32 and are provided at positions different from those shown in FIG.

The support member 91 supports the semiconductor substrate 1. The support member 91 is made of a metal such as Al. The support member 91 has a recess 911. The recess 911 is a portion for accommodating the semiconductor substrate 1 and supports the semiconductor substrate 1. The semiconductor substrate 1 is bonded to the recess 911 by, for example, a bonding layer 919. It is preferable that the bonding layer 919 is capable of transferring heat from the semiconductor substrate 1 to the support member 91 and insulating the semiconductor substrate 1 and the support member 91. Examples of such a bonding layer 919 include a resin-based adhesive.

The dimensions of the support member 91 are not particularly limited, and for example, the sub-scanning direction y dimension is about 5.0 mm to 8.0 mm, and the x direction dimension is about 100 mm to 150 mm. Further, the z dimension in the thickness direction is about 2.0 to 4.0 mm.

The protective resin 8 protects the control element 7, and is made of, for example, an insulating resin. Further, the protective resin 8 overlaps with the second inclined side surface 132 of the convex portion 13 in the thickness direction z view, and exposes the top surface 130. In the present embodiment, the protective resin 8 covers a part of the wiring member 92.

Next, an example of a method for manufacturing the thermal print head A1 will be described below with reference to FIGS. 6 to 11.

First, a semiconductor substrate material is prepared. The semiconductor substrate material is made of a low-resistance semiconductor material, for example, a material in which Si is doped with a metal element. Further, this semiconductor substrate material has a (100) plane. After covering the (100) surface with a predetermined mask layer, anisotropic etching using, for example, KOH is performed. As a result, the semiconductor substrate 1 shown in FIG. 6 is obtained. The main surface 11 and the top surface 130 are (100) surfaces. The first inclined side surface 131 and the second inclined side surface 132 are inclined surfaces formed by anisotropic etching, and the angle formed with the main surface 11 is 54.7 degrees, respectively. In addition, unlike this method, the semiconductor substrate 1 may be formed by cutting or the like. Next, a metal layer covering the main surface 11 and the convex portion 13 is formed by a thin film forming process such as CVD or sputtering. This metal layer is made of, for example, any of Ti, Ta, Co and Ni. Then, the semiconductor substrate 1 and the metal layer are heated to about 800 ° C. in, for example, a diffusion furnace. As a result, the silicide layer 6 is formed by the metal layer and the Si of the semiconductor substrate 1.

Next, as shown in FIG. 7, the insulating layer 2 is formed. The insulating layer 2 is formed by depositing _{SiO 2 using, for example, CVD.} Further, the first opening 21 for the common electrode and the second opening 22 for the common electrode are formed by etching or the like. The portion of the silicide layer 6 located in the first opening 21 for the common electrode is the first intervening portion 61 on the resistance side, and the portion located in the second opening 22 for the common electrode is the second interposing portion 62 on the resistance side.

Next, as shown in FIG. 8, the resistor layer 4 is formed. The resistor layer 4 is formed, for example, by forming a thin film of TaN on the insulating layer 2 by sputtering.

Next, the wiring layer 3 that covers the resistor layer 4 is formed. The wiring layer 3 is formed by forming a layer made of Cu by, for example, plating or sputtering. Further, the Ti layer may be formed before the Cu layer is formed. Then, by performing the selective etching of the wiring layer 3 and the selective etching of the resistor layer 4, the wiring layer 3 and the resistor layer 4 shown in FIG. 9 can be obtained. The wiring layer 3 has a plurality of individual electrodes 31 and a common electrode 32. The resistor layer 4 has a plurality of heat generating portions 41. Further, the common electrode 32 has a wiring side first through conductive portion 321 and a wiring side second through conductive portion 322. The resistor layer 4 has a first through conductive portion 421 on the resistance side and a second through conductive portion 422 on the resistance side.

Next, as shown in FIG. 10, the insulating protective layer 5 is formed. _{The formation of the insulating protective layer 5 is performed, for example, by depositing SiO 2} on the insulating layer 2, the wiring layer 3, and the resistor layer 4 using CVD, and then performing etching or the like.

Next, as shown in FIG. 11, the surface protective layer 59 is formed. Further, a pad 381 for a control element and a pad 382 for a wiring member are formed. Next, as shown in FIG. 12, the wiring member 92 is joined to the wiring member pad 382. Then, the semiconductor substrate 1 is bonded to the support member 91 by using the bonding layer 919, and then the protective resin 8 is formed. By going through the above steps, the thermal print head A1 can be obtained.

Next, the operation of the thermal print head A1 will be described.

According to the present embodiment, the conduction path for energizing the plurality of heat generating portions 41 includes the semiconductor substrate 1. Since conduction is achieved by the semiconductor substrate 1, it is not necessary to form a corresponding portion as a part of the wiring layer 3. As a result, the area of the wiring layer 3 to be provided on the main surface 11 side can be reduced. As a result, it is possible to expand the area for forming the wiring layer 3, and it is possible to more easily form the wiring layer 3 in response to the miniaturization and narrowing of the pitch of the plurality of heat generating portions 41. Can be done. Therefore, the printing can be refined.

Further, in the first opening 21 for the common electrode, the first intervening portion 61 on the resistance side of the silicide layer 6 is provided between the first through conduction portion 421 on the resistance side of the resistor layer 4 and the first region 111 of the semiconductor substrate 1. It is intervening. By interposing the first intervening portion 61 on the resistance side, it is possible to avoid forming an ohmic contact between the first penetrating conductive portion 421 on the resistance side and the first region 111 and forming a Schottky contact. Is. As a result, the resistance characteristic between the first through conductive portion 421 on the resistance side and the first region 111 can be made a general linear characteristic. Therefore, a smoother conduction function can be realized.

Further, in the second opening 22 for the common electrode, the second intervening portion 62 on the resistance side of the silicide layer 6 is provided between the second through conduction portion 422 on the resistance side of the resistor layer 4 and the second region 112 of the semiconductor substrate 1. It is intervening. By interposing the second intervening portion 62 on the resistance side, it is possible to avoid forming an ohmic contact between the second penetrating conductive portion 422 on the resistance side and the second region 112 and forming a Schottky contact. Is. As a result, the resistance characteristic between the second through conductive portion 422 on the resistance side and the second region 112 can be made a general linear characteristic. Therefore, a smoother conduction function can be realized.

The silicide layer 6 is formed so as to cover all of the main surface 11 and the convex portion 13. Therefore, in forming the silicide layer 6, a step such as patterning is not required. This is suitable for improving the efficiency of the manufacturing process of the thermal print head A1.

Further, the semiconductor substrate 1 is conductive with the common electrode 32. The common electrode 32 is a portion that conducts with all of the plurality of heat generating portions 41. Therefore, the semiconductor substrate 1 is not forced to be divided into a plurality of portions insulated from each other.

The semiconductor substrate 1 is electrically connected to the wiring side first through conductive portion 321 and the wiring side second through conductive portion 322 through the common electrode first opening 21 and the common electrode second opening 22. The first opening 21 for the common electrode, the second opening 22 for the common electrode, the first through conductive portion 321 on the wiring side, and the second through conductive portion 322 on the wiring side sandwich a plurality of heat generating portions 41 in the sub-scanning direction y. With such an arrangement, the portion of the conduction path formed by the semiconductor substrate 1 bypasses the plurality of heat generating portions 41 in the thickness direction z. This is preferable for downsizing and narrowing the pitch of the plurality of heat generating portions 41.

Further, a portion of the conduction path formed by the semiconductor substrate 1 overlaps the plurality of control elements 7 in the thickness direction z-view. Thereby, it is possible to suppress the interference between the wiring layer 3 and the plurality of control elements 7.

The first opening 21 for the common electrode extends long in the main scanning direction x. As a result, the contact resistance between the wiring layer 3 and the semiconductor substrate 1 can be reduced.

The insulating protective layer 5 is conducting with the common electrode 32 of the wiring layer 3 through the protective layer penetrating conductive portion 591. The insulating protective layer 5 is a portion that rubs against the print medium 992, and is easily charged with static electricity. This charged charge can be appropriately released to the common electrode 32 of the wiring layer 3.

A convex portion 13 is formed on the semiconductor substrate 1. The plurality of heat generating portions 41 overlap with the convex portions 13 in the z-view in the thickness direction. As a result, it is possible to press the portion including the plurality of heat generating portions 41 against the print medium 992 with a higher pressure. This is preferable for fine printing.

The convex portion 13 has a top surface 130, a first inclined side surface 131, and a second inclined side surface 132. The top surface 130 is a flat surface parallel to the main surface 11, and is preferable as a portion for forming a plurality of heat generating portions 41. The configuration having the first inclined side surface 131 and the second inclined side surface 132 is suitable for forming the wiring layer 3 and the resistor layer 4 so as to straddle them.

13 and 14 show other embodiments of the present invention. In these figures, the same or similar elements as those in the above embodiment are designated by the same reference numerals as those in the above embodiment.

FIG. 13 shows a thermal printhead based on the second embodiment of the present invention. The thermal print head A2 of the present embodiment has a structure of the silicide layer 6 different from that of the thermal print head A1 described above.

In the present embodiment, the silicide layer 6 has a portion constituting the resistance-side first intervening portion 61 and the resistance-side second intervening portion 62, while covering all of the main surface 11 and the convex portion 13. Not. Therefore, most of the insulating layer 2 is in contact with the semiconductor substrate 1. The resistance-side first interposition portion 61 and the resistance-side second interposition portion 62 are located in the common electrode first opening 21 and the common electrode second opening 22. After forming the insulating layer 2 having the first opening 21 for the common electrode and the second opening 22 for the common electrode, the first intervening portion 61 on the resistance side and the second interposing portion 62 on the resistance side form Ti, Ta, Co. It can be formed by forming a pattern of a metal layer made of and Ni and passing through the above-mentioned steps using a diffusion furnace.

Even with such an embodiment, it is possible to improve the fineness of printing and realize a smoother conduction function.

FIG. 14 shows a thermal printhead based on the third embodiment of the present invention. The configuration of the wiring layer 3 of the thermal print head A3 of the present embodiment is different from that of the above-described embodiment. The structure of the silicide layer 6 may be any of the above-mentioned thermal print head A1 and thermal print head A2.

In the present embodiment, the base conductive layer 39 interposed between the wiring layer 3 and the resistor layer 4 is provided. The base conductive layer 39 is a portion that becomes a base layer in the Cu plating step for forming, for example, the wiring layer 3. The base conductive layer 39 is made of, for example, Ti, and its thickness is 0.1 μm to 0.2 μm, preferably about 0.17 μm.

The base conductive layer 39 has a first coated conductive portion 391 and a second coated conductive portion 392. The first coated conductive portion 391 is a portion that covers the resistor layer 4 at the boundary between the top surface 130 and the first inclined side surface 131. The second coated conductive portion 392 is a portion that covers the resistor layer 4 at the boundary between the top surface 130 and the second inclined side surface 132. Such a base conductive layer 39 corresponds to an example of the coated conductive layer of the present invention. In the thermal print head A1 and the thermal print head A2, a part of the wiring layer 3 functions as a coated conductive layer.

Further, in the present embodiment, the individual electrodes 31 and the common electrodes 32 of the wiring layer 3 are provided in a region recessed from the top surface 130 of the convex portion 13.

Even with such an embodiment, it is possible to improve the fineness of printing and realize a smoother conduction function. Further, the boundary between the top surface 130 and the first inclined side surface 131 and the boundary between the top surface 130 and the second inclined side surface 132 have a bent shape. The resistor layer 4 is a layer having a relatively low resistance and is often a relatively thin layer. If the resistor layer 4 is exposed from the wiring layer 3 and the underlying conductive layer 39 in such a portion, the resistor layer 4 may be damaged due to current concentration, temperature concentration, stress concentration, or the like. , Found by the inventor's test. In the present embodiment, since the resistor layer 4 is covered with the first coated conductive portion 391 and the second coated conductive portion 392 at these portions, the resistor layer 4 can be protected.

Ti constituting the base conductive layer 39 has a lower thermal conductivity than Cu constituting the wiring layer 3. Therefore, the first coated conductive portion 391 and the second coated conductive portion 392 of the base conductive layer 39 unintentionally transfer the heat generated in the heat generating portion 41 in the y direction while protecting the resistor layer 4. Can be suppressed. This is advantageous for speeding up and clarifying the printing of the thermal print head A3.

The thermal printhead according to the present invention is not limited to the above-described embodiment. The specific configuration of each part of the thermal print head according to the present invention can be freely redesigned.

A1 to A3: Thermal printhead 1: Semiconductor substrate 2: Insulation layer 3: Wiring layer 4: Resistor layer 5: Insulation protective layer 6: VDD layer 7: Control element 8: Protective resin 11: Main surface 12: Back surface 13 : Convex portion 21: First opening for common electrode 22: Second opening for common electrode 31: Individual electrode 32: Common electrode 39: Underground conductive layer 41: Heat generating portion 51: Opening for conductive protective layer 52: For control element Opening 53: Wiring member opening 59: Surface protective layer 61: Resistance side first intervening portion 62: Resistance side second intervening portion 71: Control element electrode 79: Conductive bonding material 91: Support member 92: Wiring member 111: First 1 area 112: 2nd area 130: Top surface 131: 1st inclined side surface 132: 2nd inclined side surface 321: Wiring side 1st through conducting part 322: Wiring side 2nd through conducting part 381: Control element pad 382: Wiring Member pad 391: 1st coated conductive part 392: 2nd coated conductive part 421: Resistance side 1st through conductive part 422: Resistance side 2nd through conductive part 591: Protective layer through conductive part 911: Recessed 919: Bonding layer 921 : Resin layer 922: Wiring layer 923: Protective layer 991: Platen roller 992: Print medium x: Main scanning direction y: Sub-scanning direction z: Direction

Claims (35)

With a semiconductor substrate
A resistor layer supported by the semiconductor substrate and having a plurality of heat generating portions arranged in the main scanning direction to generate heat when energized.
A thermal printhead including a wiring layer formed on the resistor layer and included in a conduction path for energizing the plurality of heat generating portions.
The semiconductor substrate contains Si and contains
The thermal printhead, characterized in that the conduction path includes a semiconductor substrate, a silicide layer interposed between the semiconductor substrate and the resistor layer. The thermal printhead according to claim 1, wherein the silicide layer contains at least one of Ti, Ta, Co and Ni. The wiring layer has a plurality of individual electrodes individually connected to the plurality of heat generating portions, and a portion arranged on the opposite side of the plurality of individual electrodes with the plurality of heat generating portions interposed therebetween. It has a common electrode that conducts with the heat generating part of
The thermal print head according to claim 1 or 2, wherein the common electrode and the semiconductor substrate are conductive. The thermal printhead according to claim 3, further comprising an insulating protective layer that covers the wiring layer and the resistor layer. It is provided with an insulating layer provided between the semiconductor substrate, the wiring layer, and the resistor layer.
The thermal print head according to claim 4, wherein the insulating layer has a first opening for a common electrode that conducts the semiconductor substrate and the common electrode. The thermal printhead according to claim 5, wherein the silicide layer is formed in all the regions where the insulating layer and the semiconductor substrate overlap. The thermal print head according to claim 5, wherein the insulating layer and the semiconductor substrate are in contact with each other. The thermal print head according to any one of claims 5 to 7, wherein the first opening for a common electrode has a shape extending long in the main scanning direction. The resistor layer has a resistance-side first through conductive portion located in the first opening for the common electrode.
The thermal print head according to any one of claims 5 to 8, wherein the silicide layer has a resistance-side first intervening portion interposed between the resistance-side first through conductive portion and the semiconductor substrate. The thermal print head according to claim 9, wherein the common electrode has a wiring-side first through conductive portion in contact with the resistance-side first through conductive portion. The insulating layer is located on the side opposite to the first opening for the common electrode in the sub-scanning direction with the plurality of heat generating portions interposed therebetween, and has a second opening for the common electrode that conducts the semiconductor substrate and the common electrode. The thermal printhead according to any one of claims 5 to 10. The resistor layer has a second through conductive portion on the resistance side located in the second opening for the common electrode.
The thermal printhead according to claim 11, wherein the silicide layer has a resistance-side second intervening portion interposed between the resistance-side second penetrating conductive portion and the semiconductor substrate. The thermal print head according to claim 12, wherein the common electrode has a wiring-side second through-conducting portion in contact with the resistance-side second through-conducting portion. The thermal print head according to claim 13, further comprising a plurality of control elements that conduct the wiring layer and individually energize the plurality of heat generating portions. The thermal print head according to claim 14, wherein the second opening for the common electrode overlaps with the control element in the thickness direction of the semiconductor substrate. The thermal printhead according to claim 14 or 15, wherein the insulating protective layer has an opening for a control element that exposes at least a part of each of the plurality of individual electrodes and the common electrode. The thermal print head according to claim 16, further comprising a control element pad formed in the control element opening. The thermal print head according to claim 17, wherein the control element is conductively bonded to the control element pad. Any of claims 14 to 18, wherein the insulating protective layer is located on the side opposite to the plurality of heat generating portions with respect to the control element in the sub-scanning direction, and has an opening for a wiring member that exposes the wiring layer. Thermal print head described in Crab. The thermal print head according to claim 19, further comprising a wiring member pad formed in the wiring member opening. The thermal print head according to claim 20, further comprising a wiring member joined to the wiring member pad. The thermal print head according to claim 21, wherein the wiring member is a flexible wiring board. The semiconductor substrate has a main surface and a back surface that face opposite sides in the thickness direction of the semiconductor substrate, and a convex portion that protrudes from the main surface in the thickness direction and extends long in the main scanning direction.
The thermal print head according to any one of claims 14 to 22, wherein the plurality of heat generating portions overlap with the convex portions in the thickness direction. 23. The thermal printhead according to claim 23, wherein the main surface has a first region and a second region that are separated from each other in the sub-scanning direction with the convex portion interposed therebetween. The convex portion is inclined with respect to the interposed and the main surface between the main surface and is parallel and top spaced above the thickness direction from the main surface, said top surface and said first region 24. The thermal print head according to claim 24, which has a first inclined side surface and a second inclined side surface that is interposed between the top surface and the second region and is inclined with respect to the main surface. The thermal print head according to claim 25, wherein the plurality of heat generating portions overlap with the top surface in the thickness direction. The thermal print head according to claim 26, wherein the first opening for the common electrode overlaps with the first region in the thickness direction. The thermal print head according to claim 27, wherein the second opening for the common electrode overlaps with the second region in the thickness direction. 28. The thermal print head according to claim 28, wherein the control element overlaps the second region in the thickness direction. Any of claims 25 to 29, further comprising a coated conductive layer covering the resistor layer at at least one of the boundary between the top surface and the first inclined side surface and the boundary between the top surface and the second inclined side surface. The thermal printhead described in. The thermal printhead according to claim 30, wherein the coated conductive layer covers the resistor layer at both the boundary between the top surface and the first inclined side surface and the boundary between the top surface and the second inclined side surface. The thermal print head according to claim 30 or 31, wherein the coated conductive layer is composed of an underlying conductive layer interposed between the resistor layer and the wiring layer. The thermal print head according to any one of claims 1 to 32, wherein the semiconductor substrate is made of a material in which Si is doped with a metal element. The thermal print head according to any one of claims 1 to 33, wherein the resistor layer is made of TaN. The thermal print head according to any one of claims 1 to 34, wherein the wiring layer is made of Cu.

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