JP6830301B2 - PLL circuit - Google Patents

Description

The present disclosure improves the linearity of the phase detection characteristics of the phase comparator and the charge pump in a PLL (Phase-Locked-Loop) circuit having a high reference signal frequency.

Recently, high-speed data processing and high-speed data communication are increasingly required, and a PLL circuit that outputs a high-speed clock signal is becoming more and more important.

The outline configuration and the detailed configuration of the PLL circuit P of the first prior art are shown in FIGS. 1 and 2. The first prior art PLL circuit P includes a phase comparator 1, a charge pump 2, a loop filter 3, an oscillator 4, and a frequency divider 5.

The oscillator 4 controls the oscillation frequency based on the voltage signal. The frequency divider 5 divides the oscillation signal output by the oscillator 4 to a frequency substantially the same as the frequency of the reference signal ref.

The phase comparator 1 is an ascending signal instructing an increase in the oscillation frequency of the oscillator 4 according to the phase difference of the feedback signal fb output by the frequency divider 5 with respect to the phase of the reference signal ref input to the PLL circuit P. The down signal dw instructing the down of the oscillation frequency of the up and the oscillator 4 is output. The phase comparator 1 includes delay flip-flop circuits 11 and 12 and an AND circuit 13.

In the delay flip-flop circuit 11, the reference signal ref is input at the CK terminal, the high signal “1” is input at the D terminal, the output signal of the AND circuit 13 described later is input at the Reset terminal, and the Q terminal is used. , Output the rising signal up.

In the delay flip-flop circuit 12, the feedback signal fb is input at the CK terminal, the High signal “1” is input at the D terminal, the output signal of the AND circuit 13 described later is input at the Reset terminal, and the Q terminal is used. , Outputs the descending signal dw.

The AND circuit 13 inputs an ascending signal up output by the delay flip-flop circuit 11 and a descending signal dw output by the delay flip-flop circuit 12 at the input terminal, and outputs a Reset signal at the output terminal.

The charge pump 2 outputs a current signal Icp according to the pulse widths of the ascending signal up and the descending signal dw output by the phase comparator 1. The charge pump 2 includes constant current sources 21, 22 and switches 23, 24.

The switch 23 is turned on when the rising signal up is the High signal “1”, and is turned OFF when the rising signal up is the Low signal “0”. The constant current source 21 supplies an electric charge to the capacitor 31 described later when the switch 23 is ON.

The switch 24 is turned on when the descending signal dw is the High signal “1”, and is turned OFF when the descending signal dw is the Low signal “0”. The constant current source 22 draws electric charge from the capacitor 31 described later when the switch 24 is ON.

The loop filter 3 has a capacitor 31 and a resistor 32, and converts the current signal Icp output by the charge pump 2 into a voltage signal input to the oscillator 4. Here, the loop filter 3 is not limited to the one in which the capacitor 31 and the resistor 32 are connected in series.

Japanese Patent No. 1744474

By Behzad Razavi, Translated by Tadahiro Kuroda, "Design and Application of Design of Analog CMOS Integrated Circuits", Maruzen Co., Ltd., p. 646.

The output waveforms of the phase comparator 1 and the charge pump 2 of the first prior art PLL circuit P are shown in FIG. Here, the output waveform shown by the solid line is the output waveform in the ideal case, and the output waveform shown by the alternate long and short dash line is the output waveform in the actual case considering the slew rate.

The time when the phase of the feedback signal fb is later than the phase of the reference signal ref is shown at the left end of FIG. The rising signal up has a pulse width corresponding to the phase delay of the feedback signal fb with respect to the phase of the reference signal ref. The descending signal dw has a narrow pulse width corresponding to the circuit delay of the phase comparator 1. The current signal Icp supplies electric charge to the capacitor 31 according to the pulse width of the rising signal up.

The time when the phase of the feedback signal fb is equal to the phase of the reference signal ref is shown in the center of FIG. The ascending signal up and the descending signal dw have a narrow pulse width corresponding to the circuit delay of the phase comparator 1. Since the pulse widths of the rising signal up and the falling signal dw are the same in the current signal Icp, the charge is not supplied to the capacitor 31 or the charge is extracted from the capacitor 31.

The time when the phase of the feedback signal fb is earlier than the phase of the reference signal ref is shown at the right end of FIG. The rising signal up has a narrow pulse width corresponding to the circuit delay of the phase comparator 1. The descending signal dw has a pulse width corresponding to the phase advance of the feedback signal fb with respect to the phase of the reference signal ref. The current signal Icp extracts the charge from the capacitor 31 according to the pulse width of the descending signal dw.

FIG. 4 shows the phase detection characteristics of the phase comparator 1 and the charge pump 2 of the first prior art PLL circuit P. Here, the characteristics shown by the solid line are the characteristics in the actual case considering the slew rate, and the characteristics shown by the broken line are the characteristics in the ideal case.

When the phase of the feedback signal fb is equal to the phase of the reference signal ref, the current signal Icp does not supply charge to the capacitor 31 or draw charge from the capacitor 31, the voltage signal input to the oscillator 4 is not changed, and the oscillator The oscillation frequency of 4 is locked.

As described in FIG. 3, the phase detection characteristics of the phase comparator 1 and the charge pump 2 are the phase difference of the feedback signal fb with respect to the phase of the reference signal ref, from -2πrad to 2πrad, and the feedback signal fb with respect to the phase of the reference signal ref. It is desirable that it is proportional to the phase difference of.

However, in the PLL circuit P in which the frequency of the reference signal ref is high, the phase detection characteristics of the phase comparator 1 and the charge pump 2 are the difference in the phase of the feedback signal fb with respect to the phase of the reference signal ref, as described in FIG. In the vicinity of 0rad, it is considered that it is not proportional to the phase difference of the feedback signal fb with respect to the phase of the reference signal ref. This is because, in the PLL circuit P having a high frequency of the reference signal ref, the rising characteristic, that is, the slew rate is low with respect to the rising signal up and the falling signal dw having a narrow pulse width corresponding to the circuit delay of the phase comparator 1. is there.

Deterioration of the linearity of the phase detection characteristics of the phase comparator 1 and the charge pump 2 is equivalent to giving an error to the frequency division code value generated by MASH (Multi-stAge noise Shapping), and is within the PLL band. This will lead to deterioration of the phase noise floor.

Here, MASH is a technique used by the frequency divider 5 not only to perform integer division but also to perform decimal division. The case where the frequency division code value is a decimal value larger than N (N is an integer value) and smaller than N + 1 will be described. For the frequency divider of the frequency divider 5, when the MASH order is M, one of the integer values of N-2 ^M + 1, ..., N + 2 ^M is randomly selected for each cycle of the reference signal ref. If averaged over time, it will be the above decimal value. By increasing the MASH order, the frequency divider 5 can increase the randomness of the integer value output, and can diffuse the fractional spurious to the high region where the suppression amount of the loop filter 3 is large.

Examples of solving the problems of the first prior art include the second and third prior arts (see Patent Document 1 and Non-Patent Document 1, respectively).

The outline configuration of the PLL circuit P of the second prior art is shown in FIG. A delay circuit 14 is added to the second prior art PLL circuit P as compared with the first prior art PLL circuit P. The delay circuit 14 receives the output signal of the AND circuit 13 at the input terminal, applies a predetermined delay inside the circuit, and outputs the Reset signal at the output terminal.

The output waveforms of the phase comparator 1 and the charge pump 2 of the second prior art PLL circuit P are shown in FIG. Here, the output waveform shown by the solid line is the output waveform in the ideal case, and the output waveform shown by the alternate long and short dash line is the output waveform in the actual case considering the slew rate.

In the second prior art, the pulse widths of the ascending signal up and the descending signal dw are widened by the phase delay α as compared with the first prior art.

FIG. 7 shows the phase detection characteristics of the phase comparator 1 and the charge pump 2 of the second prior art PLL circuit P. Here, the characteristics shown by the solid line are the characteristics in the actual case considering the slew rate, and the characteristics shown by the broken line are the characteristics in the ideal case.

In the second conventional technique, even in the PLL circuit P in which the frequency of the reference signal ref is higher than that in the first conventional technique, the phase detection characteristics of the phase comparator 1 and the charge pump 2 are the phase of the reference signal ref. It is considered that the difference in the phase of the feedback signal fb with respect to the reference signal ref is substantially proportional to the difference in the phase of the feedback signal fb with respect to the phase of the reference signal ref. However, even with the second conventional technique, low phase noise cannot be realized.

The outline configuration of the PLL circuit P of the third prior art is shown in FIG. The third prior art PLL circuit P has the delay flip-flop circuits 11 and 12 and the AND circuit 13 removed and the EXOR circuit 15 added as compared with the first prior art PLL circuit P. The EXOR circuit 15 inputs the reference signal ref and the feedback signal fb at the input terminal, and outputs the EXOR signal to the switches 23 and 24 at the output terminal. The EXOR signal locks the PLL circuit P in order to set the duty ratio to 50% when the phase of the feedback signal fb is later by π / 2 rad than the phase of the reference signal ref and when it is earlier by π / 2 rad.

FIG. 9 shows the phase detection characteristics of the phase comparator 1 and the charge pump 2 of the third prior art PLL circuit P.

When the phase of the feedback signal fb is later by π / 2 rad and earlier than the phase of the reference signal ref, the oscillation frequency of the oscillator 4 is locked. At this time, there is no problem that the rising characteristic, that is, the slew rate is low with respect to the rising signal up and the falling signal dw having a narrow pulse width corresponding to the circuit delay of the phase comparator 1.

However, the phase detection characteristics of the phase comparator 1 and the charge pump 2 have the same characteristics when the phase of the feedback signal fb is π / 2 rad later than the phase of the reference signal ref and when π / 2 rad is earlier. Become. Therefore, since the PLL circuit P does not have a frequency discrimination function, phase slip is likely to occur and the lockup time is delayed.

Therefore, in order to solve the above-mentioned problems, the present disclosure discloses a phase comparator and a charge while having a frequency discrimination function while sufficiently securing a swing width of the phase of MASH in a PLL circuit having a high reference signal frequency. The purpose is to improve the linearity of the phase detection characteristics of the pump.

In order to achieve the above object, two delay flip-flop type phase comparators are arranged in parallel, and one loop filter is arranged as in the conventional case. A 2 ⁿ (n is a natural number) divided positive phase reference signal and a 2 ⁿ divided positive phase feedback signal are input to the first phase comparator, or a 2 ⁿ divided reverse is input. The reference signal of the phase and the feedback signal of the opposite phase divided by 2 ⁿ are input. A 2 ^n- divided positive-phase reference signal and a 2- ^n- divided reverse-phase feedback signal are input to the second phase comparator, or a 2- ^n- divided reverse-phase reference signal and A positive phase feedback signal divided by 2 ⁿ is input. That is, one of the frequency dividing reference signal and the frequency dividing feedback signal may be input in the same phase to the first and second phase comparators, and the other signal may be input to the first and second phase comparators. On the other hand, it may be input in the opposite phase. Then, it was decided to integrate the ascending signal and the descending signal output by the first phase comparator and the second phase comparator into the current signal to the loop filter of one system.

Specifically, in the present disclosure, an oscillator that controls the oscillation frequency based on a voltage signal, a frequency divider that divides the oscillation signal output by the oscillator, and a reference signal input to the PLL circuit are 2 ^n. A reference signal oscillator that divides and outputs a positive-phase division reference signal and an opposite-phase division reference signal, and a feedback signal output by the oscillator are divided by 2 ^{n to} divide the positive-phase. The feedback signal oscillator outputs the feedback signal oscillator that outputs the feedback signal and the opposite-phase oscillator signal, and the feedback signal oscillator outputs the phase of the positive-phase oscillator reference signal output by the reference signal oscillator. The reverse phase output by the feedback signal oscillator according to the phase difference of the positive phase divided feedback signal or with respect to the phase of the opposite phase divided reference signal output by the reference signal oscillator. A first rising signal instructing an increase in the oscillation frequency of the oscillator and a first falling signal instructing a decrease in the oscillation frequency of the oscillator are output according to the phase difference of the frequency-divided feedback signal of the phase. , The phase of the first phase comparator of the delay flip flop type and the frequency division of the positive phase output by the reference signal oscillator, and the frequency division of the negative phase output by the feedback signal oscillator. The positive phase divided feedback signal output by the feedback signal oscillator according to the phase difference of the feedback signal or with respect to the phase of the opposite phase divided reference signal output by the reference signal oscillator. A delay flip-flop type that outputs a second rising signal instructing an increase in the oscillation frequency of the oscillator and a second falling signal instructing a decrease in the oscillation frequency of the oscillator according to the phase difference of the above. A first charge that outputs a first current signal according to the pulse widths of the second phase comparator and the first rising signal and the first falling signal output by the first phase comparator. A pump, a second charge pump that outputs a second current signal according to the pulse widths of the second rising signal and the second falling signal output by the second phase comparator, and the second charge pump. A loop having a capacitor that integrates the first current signal output by the charge pump 1 and the second current signal output by the second charge pump and converts it into the voltage signal input to the oscillator. The PLL circuit is characterized by comprising a filter.

According to this configuration, the phase difference ± Enupairad of 2 ⁿ division before the feedback signal for the 2 ⁿ division prior reference signal of the phase, the oscillation frequency of the oscillator is locked, the 2 ⁿ division prior reference signal In the vicinity of the phase difference ± nπrad of the feedback signal before 2 ⁿ division with respect to the phase, the ascending signal and the descending signal have a wide pulse width corresponding to the phase difference nπrad before 2 ⁿ division. Therefore, in a PLL circuit in which the frequency of the reference signal is high, even if the through rate is low with respect to the rising signal and the falling signal, the phase comparison is performed while having a frequency discrimination function while sufficiently securing the swing width of the MASH phase. The linearity of the phase detection characteristics of the device and the charge pump can be improved. Further, in this PLL circuit, the range in which the linearity of the phase detection characteristics of the phase comparator and the charge pump is established can be expanded as compared with the PLL circuit described below.

Further, in the present disclosure, an oscillator that controls the oscillation frequency based on a voltage signal, a frequency divider that divides the oscillation signal output by the oscillator, and a reference signal input to the PLL circuit are divided by 2 ^n. , The reference signal oscillator that outputs the positive-phase division reference signal and the negative-phase division reference signal, and the feedback signal output by the oscillator are divided by 2 ^n, and the positive-phase division feedback signal and The positive phase output by the feedback signal oscillator with respect to the phase of the feedback signal oscillator that outputs the opposite phase divided feedback signal and the positive phase divided reference signal output by the reference signal oscillator. The division of the opposite phase output by the feedback signal oscillator according to the phase difference of the divided feedback signal of the above, or with respect to the phase of the opposite phase division reference signal output by the reference signal oscillator. A delay flip floc that outputs a first rising signal instructing an increase in the oscillation frequency of the oscillator and a first falling signal instructing a decrease in the oscillation frequency of the oscillator according to the phase difference of the peripheral feedback signal. Of the first phase comparator of the type and the divided feedback signal of the opposite phase output by the feedback signal oscillator with respect to the phase of the divided reference signal of the positive phase output by the reference signal oscillator. Depending on the phase difference or the phase of the positive phase divided feedback signal output by the feedback signal oscillator with respect to the phase of the opposite phase divided reference signal output by the reference signal oscillator. A second delay flipflop type that outputs a second rising signal instructing an increase in the oscillation frequency of the oscillator and a second falling signal instructing a decrease in the oscillation frequency of the oscillator according to the difference. The logical sum of the phase comparator, the first ascending signal output by the first phase comparator, and the second ascending signal output by the second phase comparator is calculated, and the integrated ascending signal is output. The logical sum of the rising signal synthesizer, the first falling signal output by the first phase comparator, and the second falling signal output by the second phase comparator is calculated, and the integrated falling signal is calculated. A down signal integrater that outputs a current signal, and a charge pump that outputs a current signal according to the pulse width of the integrated ascending signal output by the ascending signal integrator and the integrated down signal output by the down signal integrator. The PLL circuit includes a loop filter having a capacitor that converts the current signal output by the charge pump into the voltage signal input to the oscillator.

According to this configuration, the phase difference ± Enupairad of 2 ⁿ division before the feedback signal for the 2 ⁿ division prior reference signal of the phase, the oscillation frequency of the oscillator is locked, the 2 ⁿ division prior reference signal In the vicinity of the phase difference ± nπrad of the feedback signal before 2 ⁿ division with respect to the phase, the ascending signal and the descending signal have a wide pulse width corresponding to the phase difference nπrad before 2 ⁿ division. Therefore, in a PLL circuit in which the frequency of the reference signal is high, even if the through rate is low with respect to the rising signal and the falling signal, the phase comparison is performed while having a frequency discrimination function while sufficiently securing the swing width of the MASH phase. The linearity of the phase detection characteristics of the device and the charge pump can be improved. Further, in this PLL circuit, as compared with the PLL circuit described above, since only one charge pump is arranged, the current consumption of the charge pump can be reduced.

Further, in the present disclosure, the frequency divider is a decimal point divider using MASH, the MASH order is M and the decimal point division number is N, and the MASH order M and the decimal point division number N. It is a PLL circuit characterized in that nπ ≧ 2 ^M / N × 2π is established between them.

According to this configuration, the linearity of the phase detection characteristics of the phase comparator and the charge pump can be improved over the phase swing width of 2 ^M / N × 2πrad of MASH.

Further, in the present disclosure, the reference signal divider divides the reference signal input to the PLL circuit by two, and the feedback signal divider divides the feedback signal output by the divider by 2. It is a PLL circuit characterized by dividing the frequency.

According to this configuration, the ascending signal and the descending signal have a pulse width corresponding only to the phase difference πrad before the division by two, reduce the ON time of the charge pump switch, and reduce the output noise of the charge pump. be able to.

As described above, in the present disclosure, in a PLL circuit having a high reference signal frequency, the phase detection characteristics of the phase comparator and the charge pump are described while having a frequency discrimination function while sufficiently ensuring the phase swing width of the MASH. The linearity can be improved.

It is a figure which shows the outline structure of the PLL circuit of the 1st prior art. It is a figure which shows the detailed structure of the PLL circuit of the 1st prior art. It is a figure which shows the output waveform of the phase comparator and the charge pump of the PLL circuit of the 1st prior art. It is a figure which shows the phase detection characteristic of the phase comparator and the charge pump of the PLL circuit of the 1st prior art. It is a figure which shows the detailed structure of the PLL circuit of the 2nd prior art. It is a figure which shows the output waveform of the phase comparator and the charge pump of the PLL circuit of the 2nd prior art. It is a figure which shows the phase detection characteristic of the phase comparator and the charge pump of the PLL circuit of the 2nd prior art. It is a figure which shows the detailed structure of the PLL circuit of the 3rd prior art. It is a figure which shows the phase detection characteristic of the phase comparator and the charge pump of the 3rd prior art PLL circuit. It is a figure which shows the outline structure of the PLL circuit of 1st Embodiment of this disclosure. It is a figure which shows the detailed structure of the PLL circuit of 1st Embodiment of this disclosure. It is a figure which shows the output waveform of the phase comparator and the charge pump of the PLL circuit of the 1st Embodiment of this disclosure. It is a figure which shows the output waveform of the phase comparator and the charge pump of the PLL circuit of the 1st Embodiment of this disclosure. It is a figure which shows the output waveform of the phase comparator and the charge pump of the PLL circuit of the 1st Embodiment of this disclosure. It is a figure which shows the output waveform of the phase comparator and the charge pump of the PLL circuit of the 1st Embodiment of this disclosure. It is a figure which shows the phase detection characteristic of the phase comparator and the charge pump of the PLL circuit of the 1st Embodiment of this disclosure. It is a figure which shows the outline structure of the PLL circuit of the modification of 1st Embodiment of this disclosure. It is a figure which shows the outline structure of the PLL circuit of the modification of 1st Embodiment of this disclosure. It is a figure which shows the outline structure of the PLL circuit of the modification of 1st Embodiment of this disclosure. It is a figure which shows the outline structure of the PLL circuit of the 2nd Embodiment of this disclosure. It is a figure which shows the detailed structure of the PLL circuit of the 2nd Embodiment of this disclosure. It is a figure which shows the output waveform of the phase comparator and the charge pump of the PLL circuit of the 2nd Embodiment of this disclosure. It is a figure which shows the output waveform of the phase comparator and the charge pump of the PLL circuit of the 2nd Embodiment of this disclosure. It is a figure which shows the output waveform of the phase comparator and the charge pump of the PLL circuit of the 2nd Embodiment of this disclosure. It is a figure which shows the output waveform of the phase comparator and the charge pump of the PLL circuit of the 2nd Embodiment of this disclosure. It is a figure which shows the phase detection characteristic of the phase comparator and the charge pump of the PLL circuit of the 2nd Embodiment of this disclosure. It is a figure which shows the outline structure of the PLL circuit of the modification of the 2nd Embodiment of this disclosure. It is a figure which shows the outline structure of the PLL circuit of the modification of the 2nd Embodiment of this disclosure. It is a figure which shows the outline structure of the PLL circuit of the modification of the 2nd Embodiment of this disclosure.

Embodiments of the present disclosure will be described with reference to the accompanying drawings. The embodiments described below are examples of the embodiments of the present disclosure, and the present disclosure is not limited to the following embodiments. In this specification and drawings, the components having the same reference numerals shall indicate the same components.

(First Embodiment)
The outline configuration and the detailed configuration of the PLL circuit P of the first embodiment of the present disclosure are shown in FIGS. 10 and 11. The PLL circuit P of the first embodiment of the present disclosure includes a first phase comparator 1-1, a second phase comparator 1-2, a first charge pump 2-1 and a second charge pump 2-. 2. It is composed of a loop filter 3, an oscillator 4, a divider 5, a reference signal divider 6, and a feedback signal divider 7.

The oscillator 4 controls the oscillation frequency based on the voltage signal. The frequency divider 5 divides the oscillation signal output by the oscillator 4 to a frequency substantially the same as the frequency of the reference signal ref.

The reference signal divider 6 divides the reference signal ref input to the PLL circuit P by two, and outputs a positive phase divided reference signal ref2 and a negative phase divided reference signal ref2x. The feedback signal divider 7 divides the feedback signal fb output by the divider 5 by two, and outputs a positive phase divided feedback signal fb2 and a negative phase divided feedback signal fb2x.

The first phase comparator 1-1 is a positive phase divided feedback signal fb2 output by the feedback signal divider 7 with respect to the phase of the positive phase divided reference signal ref2 output by the reference signal divider 6. The first rising signal up1 instructing the increase in the oscillation frequency of the oscillator 4 and the first falling signal dw1 instructing the decrease in the oscillation frequency of the oscillator 4 are output according to the phase difference. The first phase comparator 1-1 includes delay flip-flop circuits 11-1, 12-1, and an AND circuit 13-1.

In the delay flip-flop circuit 11-1, a positive-phase frequency division reference signal ref2 is input at the CK terminal, a High signal “1” is input at the D terminal, and the AND circuit 13-1 described later is input at the Reset terminal. The output signal is input, and the first rising signal up1 is output at the Q terminal.

In the delay flip-flop circuit 12-1, a positive phase divided feedback signal fb2 is input at the CK terminal, a high signal “1” is input at the D terminal, and the AND circuit 13-1 described later is input at the Reset terminal. The output signal is input, and the first descending signal dw1 is output at the Q terminal.

At the input terminal, the AND circuit 13-1 is input with the first rising signal up1 output by the delay flip-flop circuit 11-1 and the first falling signal dw1 output by the delay flip-flop circuit 12-1, and is input to the output terminal. , The Reset signal is output.

The second phase comparator 1-2 is a frequency dividing feedback signal fb2x of the opposite phase output by the feedback signal divider 7 with respect to the phase of the positive phase dividing reference signal ref2 output by the reference signal divider 6. A second rising signal up2 instructing an increase in the oscillation frequency of the oscillator 4 and a second falling signal dw2 instructing a decrease in the oscillation frequency of the oscillator 4 are output according to the phase difference. The second phase comparator 1-2 includes delay flip-flop circuits 11-2 and 12-2 and an AND circuit 13-2.

In the delay flip-flop circuit 11-2, the positive-phase frequency division reference signal ref2 is input at the CK terminal, the High signal “1” is input at the D terminal, and the AND circuit 13-2 described later is input at the Reset terminal. The output signal is input, and the second rising signal up2 is output at the Q terminal.

In the delay flip-flop circuit 12-2, the opposite-phase divided feedback signal fb2x is input at the CK terminal, the High signal “1” is input at the D terminal, and the AND circuit 13-2 described later is input at the Reset terminal. The output signal is input, and the second descending signal dw2 is output at the Q terminal.

At the input terminal, the AND circuit 13-2 receives the second rising signal up2 output by the delay flip-flop circuit 11-2 and the second falling signal dw2 output by the delay flip-flop circuit 12-2, and is input to the output terminal. , The Reset signal is output.

The first charge pump 2-1 outputs a first current signal Icp1 according to the pulse widths of the first rising signal up1 and the first falling signal dw1 output by the first phase comparator 1-1. To do. The first charge pump 2-1 includes constant current sources 21-1, 22-1, and switches 23-1, 24-1.

The switch 23-1 is turned on when the first rising signal up1 is the High signal “1”, and is turned off when the first rising signal up1 is the Low signal “0”. The constant current source 21-1 supplies an electric charge to the capacitor 31 described later when the switch 23-1 is ON.

The switch 24-1 is turned on when the first descending signal dw1 is the High signal “1”, and is turned OFF when the first descending signal dw1 is the Low signal “0”. The constant current source 22-1 draws an electric charge from the capacitor 31 described later when the switch 24-1 is ON.

The second charge pump 2-2 outputs a second current signal Icp2 according to the pulse widths of the second rising signal up2 and the second falling signal dw2 output by the second phase comparator 1-2. To do. The second charge pump 2-2 includes constant current sources 21-2, 22-2 and switches 23-2, 24-2.

The switch 23-2 is turned ON when the second rising signal up2 is the High signal “1”, and is turned OFF when the second rising signal up2 is the Low signal “0”. The constant current source 21-2 supplies an electric charge to the capacitor 31 described later when the switch 23-2 is ON.

The switch 24-2 is turned on when the second descending signal dw2 is the High signal “1”, and is turned OFF when the second descending signal dw2 is the Low signal “0”. The constant current source 22-2 draws an electric charge from the capacitor 31 described later when the switch 24-2 is ON.

The loop filter 3 has a capacitor 31 and a resistor 32, and receives a first current signal Icp1 output by the first charge pump 2-1 and a second current signal Icp2 output by the second charge pump 2-2. It is integrated and converted into a voltage signal input to the oscillator 4. Here, the loop filter 3 is not limited to the one in which the capacitor 31 and the resistor 32 are connected in series. Then, the first current signal Icp1 and the second current signal Icp2 are integrated to generate the current signal Icpo.

The output waveforms of the phase comparators 1-1 and 1-2 and the charge pumps 2-1 and 2-2 of the PLL circuit P of the first embodiment of the present disclosure are shown in FIGS. 12 to 15. The method of generating the first and second ascending signals up1 and up2 and the first and second descending signals dw1 and dw2 is the same as the method of generating the ascending signal up and the descending signal dw shown in FIG. For the first and second ascending signals up1 and up2 and the first and second descending signals dw1 and dw2, narrow pulses corresponding to the circuit delays of the first and second phase comparators 1-1 and 1-2 are generated. It is output and is shown on a white background. For the first and second current signals Icp1 and Icp2 and the current signals Icpo, narrow pulses corresponding to the circuit delays of the first and second phase comparators 1-1 and 1-2 are not output. During the narrow pulse period according to the circuit delay of the first and second phase comparators 1-1 and 1-2, both the switch for supplying electric charge to the capacitor and the switch for extracting the electric charge from the capacitor are used. This is because it turns on.

The time when the phase of the feedback signal fb is 90 ° earlier than the phase of the reference signal ref is shown in the upper part of FIG. The first descending signal dw1 has a pulse width corresponding to a phase advance of 90 ° (based on 2 division before) of the positive phase divided feedback signal fb2 with respect to the positive phase divided reference signal ref2. The second descending signal dw2 has a pulse width corresponding to a phase advance of 450 ° (based on 2 divisions before) of the phase division feedback signal fb2x of the opposite phase with respect to the positive phase division reference signal ref2. The first current signal Icp1 extracts charges from the capacitor 31 according to the pulse width of the first descending signal dw1. The second current signal Icp2 extracts charges from the capacitor 31 according to the pulse width of the second descending signal dw2. The current signal Icpo extracts charges from the capacitor 31 in proportion to the phase 90 ° + 450 ° = 540 ° (based on 2 divisions before).

The time when the phase of the feedback signal fb is equal to the phase of the reference signal ref is shown in the lower part of FIG. The second descending signal dw2 has a pulse width corresponding to the phase advance 360 ° (based on 2 divisions before) of the phase division feedback signal fb2x with respect to the positive phase division reference signal ref2. The second current signal Icp2 extracts charges from the capacitor 31 according to the pulse width of the second descending signal dw2. The current signal Icpo draws charge from the capacitor 31 in proportion to the phase 360 ° (with reference to two divisions before).

The upper part of FIG. 13 shows the time when the phase of the feedback signal fb is 90 ° later than the phase of the reference signal ref. The first rising signal up1 has a pulse width corresponding to a phase delay of 90 ° (based on 2 division before) of the positive phase divided feedback signal fb2 with respect to the positive phase divided reference signal ref2. The second descending signal dw2 has a pulse width corresponding to the phase advance 270 ° (based on 2 division before) of the phase division feedback signal fb2x of the opposite phase with respect to the positive phase division reference signal ref2. The first current signal Icp1 supplies electric charge to the capacitor 31 according to the pulse width of the first rising signal up1. The second current signal Icp2 extracts charges from the capacitor 31 according to the pulse width of the second descending signal dw2. The current signal Icpo extracts charges from the capacitor 31 in proportion to the phase of 270 ° -90 ° = 180 ° (based on 2 divisions before).

The time when the phase of the feedback signal fb is 180 ° later than the phase of the reference signal ref is shown in the lower part of FIG. The first rising signal up1 has a pulse width corresponding to a phase delay of 180 ° (based on 2 division before) of the positive phase divided feedback signal fb2 with respect to the positive phase divided reference signal ref2. The second descending signal dw2 has a pulse width corresponding to the phase advance 180 ° (based on 2 division before) of the phase division feedback signal fb2x of the opposite phase with respect to the positive phase division reference signal ref2. The first current signal Icp1 supplies electric charge to the capacitor 31 according to the pulse width of the first rising signal up1. The second current signal Icp2 extracts charges from the capacitor 31 according to the pulse width of the second descending signal dw2. The current signal Icpo does not supply charge to or extract charge from the capacitor 31.

That is, the oscillation frequency of the oscillator 4 is locked by the phase difference + πrad of the feedback signal fb before division by 2 with respect to the phase of the reference signal ref before division by 2 and 2 minutes with respect to the phase of the reference signal ref before division by 2. In the vicinity of the phase difference + πrad of the feedback signal fb before the lap, the first rising signal up1 and the second falling signal dw2 have a wide pulse width corresponding to the phase difference πrad before dividing by two.

The time when the phase of the feedback signal fb is 270 ° later than the phase of the reference signal ref is shown in the upper part of FIG. The first rising signal up1 has a pulse width corresponding to a phase delay of 270 ° (based on 2 division before) of the positive phase divided feedback signal fb2 with respect to the positive phase divided reference signal ref2. The second descending signal dw2 has a pulse width corresponding to a phase advance of 90 ° (based on 2 divisions before) of the phase division feedback signal fb2x of the opposite phase with respect to the positive phase division reference signal ref2. The first current signal Icp1 supplies electric charge to the capacitor 31 according to the pulse width of the first rising signal up1. The second current signal Icp2 extracts charges from the capacitor 31 according to the pulse width of the second descending signal dw2. The current signal Icpo supplies electric charge to the capacitor 31 in proportion to the phase of 270 ° -90 ° = 180 ° (based on 2 divisions before).

The time when the phase of the feedback signal fb is 360 ° later than the phase of the reference signal ref is shown in the lower part of FIG. The first rising signal up1 has a pulse width corresponding to a phase delay of 360 ° (based on 2 division before) of the positive phase divided feedback signal fb2 with respect to the positive phase divided reference signal ref2. The first current signal Icp1 supplies electric charge to the capacitor 31 according to the pulse width of the first rising signal up1. The current signal Icpo supplies electric charge to the capacitor 31 in proportion to the phase 360 ° (with reference to two divisions before).

FIG. 15 shows when the phase of the feedback signal fb is 450 ° later than the phase of the reference signal ref. The first rising signal up1 has a pulse width corresponding to a phase delay of 450 ° (based on 2 division before) of the positive phase divided feedback signal fb2 with respect to the positive phase divided reference signal ref2. The second rising signal up2 has a pulse width corresponding to a phase delay of 90 ° (based on 2 divisions before) of the phase division feedback signal fb2x with respect to the positive phase division reference signal ref2. The first current signal Icp1 supplies electric charge to the capacitor 31 according to the pulse width of the first rising signal up1. The second current signal Icp2 supplies electric charge to the capacitor 31 according to the pulse width of the second rising signal up2. The current signal Icpo supplies electric charge to the capacitor 31 in proportion to the phase 450 ° + 90 ° = 540 ° (based on 2 divisions before).

The phase detection characteristics of the first and second phase comparators 1-1 and 1-2 and the first and second charge pumps 2-1 and 2-2 of the PLL circuit P of the first embodiment of the present disclosure are shown in FIG. Shown in. The horizontal axis shows the difference in the phase of the feedback signal fb with respect to the phase of the reference signal ref with the lock point + πrad as a reference. The phase detection characteristic of the broken line is the phase detection characteristic of the first system, the phase detection characteristic of the one-point chain line is the phase detection characteristic of the second system, and the phase detection characteristic of the solid line is the phase detection characteristic of the first and second systems. It is a phase detection characteristic by the integrated system.

In the phase detection characteristics shown in FIGS. 4 and 7, the input phase difference is every 2πrad and the detection output is 0, whereas in the phase detection characteristics of the first and second systems, the input phase difference is every 4πrad. , The detection output becomes 0. The reasons why the phase detection characteristics are different in this way are that (1) the frequency division reference signal ref2 and the frequency division feedback signal fb2 are divided by two as compared with the reference signal ref and the feedback signal fb, and (2) minutes. The phase difference of the divided feedback signal fb2 with respect to the phase of the circumferential reference signal ref2 may be equal to the phase difference of the feedback signal fb with respect to the phase of the reference signal ref2. In the transition from the first and second prior art techniques to the first embodiment of the present disclosure, in order to align the specifications such as the bandwidth of the PLL, the inclinations of the phase detection characteristics shown in FIGS. 16 are shown in FIGS. It must be the same as the slope of the phase detection characteristic shown, and the current of each charge pump of the first embodiment of the present disclosure needs to be half the current of each charge pump of the first and second prior art. ..

As shown in FIG. 16, in the PLL circuit P having a high frequency of the reference signal ref, even if the through rate is low with respect to the first and second rising signals up1 and up2 and the first and second falling signals dw1 and dw2. To improve the linearity of the phase detection characteristics of the first and second phase comparators 1-1 and 1-2 and the first and second charge pumps 2-1 and 2-2 while having a frequency discrimination function. Can be done.

Here, when the frequency divider 5 uses MASH, the MASH order is M and the decimal point frequency divider is N, and the decimal point divider is a decimal point divider, the phase swing width of MASH is 2 ^M / N × 2πrad. Is. Therefore, in the input phase difference width πrad where the linearity of the phase detection characteristics of the first and second phase comparators 1-1 and 1-2 and the first and second charge pumps 2-1 and 2-2 is improved. It is desirable that the MASH phase swing width of 2 ^M / N × 2πrad is included. Then, the phases of the first and second phase comparators 1-1 and 1-2 and the first and second charge pumps 2-1 and 2-2 are spread over the swing width of 2 ^M / N × 2πrad of the phase of MASH. The linearity of the detection characteristics can be improved.

In the PLL circuit P of the first embodiment of the present disclosure, the first and second phase comparators 1-1, 1-2 and the first and second are compared with the PLL circuit P of the second embodiment of the present disclosure. The range in which the linearity of the phase detection characteristics of the charge pumps 2-1 and 2-2 of the above is established can be expanded.

In the above description, the first phase comparator 1-1 has the first rising signal up1 according to the difference in the phase of the positive phase divided feedback signal fb2 with respect to the phase of the positive phase divided reference signal ref2. And the first descending signal dw1 is output, and the second phase comparator 1-2 outputs the phase difference of the frequency dividing feedback signal fb2x of the opposite phase with respect to the phase of the frequency dividing reference signal ref2 of the positive phase. The second rising signal up2 and the second falling signal dw2 are output, and the lock point is + πrad.

Here, as a modification, as shown in FIG. 17, the first phase comparator 1-1 is the difference in the phase of the positive phase divided feedback signal fb2 with respect to the phase of the positive phase divided reference signal ref2. The first ascending signal up1 and the first descending signal dw1 may be output depending on the phase, and the second phase comparator 1-2 has a positive phase with respect to the phase of the opposite phase division reference signal ref2x. The second ascending signal up2 and the second descending signal dw2 may be output depending on the phase difference of the divided feedback signal fb2, and the lock point may be −πrad.

Alternatively, as a modified example, as shown in FIG. 18, the first phase comparator 1-1 determines the difference in the phase of the opposite-phase divided feedback signal fb2x with respect to the phase of the opposite-phase divided reference signal ref2x. Depending on the situation, the first rising signal up1 and the first falling signal dw1 may be output, and the second phase comparator 1-2 divides the phase of the positive phase division reference signal ref2 into the opposite phase. The second ascending signal up2 and the second descending signal dw2 may be output according to the phase difference of the peripheral feedback signal fb2x, and the lock point may be −πrad.

Alternatively, as a modification, as shown in FIG. 19, the first phase comparator 1-1 determines the difference in the phase of the anti-phase division feedback signal fb2x with respect to the phase of the anti-phase division reference signal ref2x. Depending on the situation, the first ascending signal up1 and the first descending signal dw1 may be output, and the second phase comparator 1-2 is a positive phase component with respect to the phase of the opposite phase frequency dividing reference signal ref2x. The second ascending signal up2 and the second descending signal dw2 may be output according to the phase difference of the peripheral feedback signal fb2, and the lock point may be + πrad.

Summarizing the above, one of the frequency dividing reference signal and the frequency dividing feedback signal may be input in phase to the first and second phase comparators 1-1 and 1-2, and the other signal may be input. May be input in opposite phase to the first and second phase comparators 1-1 and 1-2.

In the above description, the reference signal divider 6 divides the reference signal ref input to the PLL circuit P by two, and the feedback signal divider 7 divides the feedback signal fb output by the divider 5 by two. The lock point is ± π rad, and π ≧ 2 ^M / N × 2π holds.

Here, as a modification, the reference signal divider 6 may divide the reference signal ref input to the PLL circuit P by 2 ⁿ (n is a natural number), and the feedback signal divider 7 divides the frequency. The feedback signal fb output by the device 5 may be divided by 2 ⁿ , the lock point may be ± nπrad, and nπ ≧ 2 ^M / N × 2π may be established.

However, when the reference signal ref and the feedback signal fb are divided by two, the first ascending signal up1 and the second descending signal dw2 are compared with the case where the reference signal ref and the feedback signal fb are divided by 2 ^n. It has a pulse width corresponding only to the phase difference πrad before the division by two, and the switches 23-1, 23-2, 24-1, 24-2 of the first and second charge pumps 2-1 and 2-2. The ON time of the first and second charge pumps 2-1 and 2-2 can be reduced, and the output noise of the first and second charge pumps 2-1 and 2-2 can be reduced.

When the frequency of the feedback signal fb is higher than the frequency of the reference signal ref, even if the ascending signal up due to the delayed phase is initially output, once the descending signal dw due to the advancing phase is output, the descending due to the advancing phase is subsequently output. Continue to output the signal dw. On the contrary, when the frequency of the feedback signal fb is lower than the frequency of the reference signal ref, even if the descending signal dw due to the leading phase is output at the initial stage, once the rising signal up due to the delayed phase is output, it depends on the delayed phase thereafter. Continue to output the rising signal up. Therefore, the PLL circuit P does not transition to an unstable state.

(Second Embodiment)
20 and 21 show an outline configuration and a detailed configuration of the PLL circuit P of the second embodiment of the present disclosure. The PLL circuit P of the second embodiment of the present disclosure includes a first phase comparator 1-1, a second phase comparator 1-2, a charge pump 2, a loop filter 3, an oscillator 4, a frequency divider 5, and the like. It is composed of a reference signal divider 6, a feedback signal divider 7, an ascending signal integrator 8, and a descending signal integrator 9.

The oscillator 4 controls the oscillation frequency based on the voltage signal. The frequency divider 5 divides the oscillation signal output by the oscillator 4 to a frequency substantially the same as the frequency of the reference signal ref.

The reference signal divider 6 divides the reference signal ref input to the PLL circuit P by two, and outputs a positive phase divided reference signal ref2 and a negative phase divided reference signal ref2x. The feedback signal divider 7 divides the feedback signal fb output by the divider 5 by two, and outputs a positive phase divided feedback signal fb2 and a negative phase divided feedback signal fb2x.

The first phase comparator 1-1 is a positive phase divided feedback signal fb2 output by the feedback signal divider 7 with respect to the phase of the positive phase divided reference signal ref2 output by the reference signal divider 6. The first rising signal up1 instructing the increase in the oscillation frequency of the oscillator 4 and the first falling signal dw1 instructing the decrease in the oscillation frequency of the oscillator 4 are output according to the phase difference. The first phase comparator 1-1 includes delay flip-flop circuits 11-1, 12-1, and an AND circuit 13-1.

In the delay flip-flop circuit 11-1, a positive-phase frequency division reference signal ref2 is input at the CK terminal, a High signal “1” is input at the D terminal, and the AND circuit 13-1 described later is input at the Reset terminal. The output signal is input, and the first rising signal up1 is output at the Q terminal.

In the delay flip-flop circuit 12-1, a positive phase divided feedback signal fb2 is input at the CK terminal, a high signal “1” is input at the D terminal, and the AND circuit 13-1 described later is input at the Reset terminal. The output signal is input, and the first descending signal dw1 is output at the Q terminal.

At the input terminal, the AND circuit 13-1 is input with the first rising signal up1 output by the delay flip-flop circuit 11-1 and the first falling signal dw1 output by the delay flip-flop circuit 12-1, and is input to the output terminal. , The Reset signal is output.

The second phase comparator 1-2 is a frequency dividing feedback signal fb2x of the opposite phase output by the feedback signal divider 7 with respect to the phase of the positive phase dividing reference signal ref2 output by the reference signal divider 6. A second rising signal up2 instructing an increase in the oscillation frequency of the oscillator 4 and a second falling signal dw2 instructing a decrease in the oscillation frequency of the oscillator 4 are output according to the phase difference. The second phase comparator 1-2 includes delay flip-flop circuits 11-2 and 12-2 and an AND circuit 13-2.

In the delay flip-flop circuit 11-2, the positive-phase frequency division reference signal ref2 is input at the CK terminal, the High signal “1” is input at the D terminal, and the AND circuit 13-2 described later is input at the Reset terminal. The output signal is input, and the second rising signal up2 is output at the Q terminal.

In the delay flip-flop circuit 12-2, the opposite-phase divided feedback signal fb2x is input at the CK terminal, the High signal “1” is input at the D terminal, and the AND circuit 13-2 described later is input at the Reset terminal. The output signal is input, and the second descending signal dw2 is output at the Q terminal.

At the input terminal, the AND circuit 13-2 receives the second rising signal up2 output by the delay flip-flop circuit 11-2 and the second falling signal dw2 output by the delay flip-flop circuit 12-2, and is input to the output terminal. , The Reset signal is output.

The ascending signal integrater 8 calculates the logical sum of the first ascending signal up1 output by the first phase comparator 1-1 and the second ascending signal up2 output by the second phase comparator 1-2. , Outputs the integrated rising signal UP. The ascending signal integrater 8 includes NOT circuits 81 and 82 and a NAND circuit 83.

The NOT circuit 81 receives the first rising signal up1 at the input terminal and outputs the NOT signal at the output terminal. The NOT circuit 82 receives a second rising signal up2 at the input terminal and outputs a NOT signal at the output terminal. At the input terminal, the NAND circuit 83 inputs the NOT signal output by the NOT circuits 81 and 82, and outputs the NAND signal. Here, this NAND signal is an integrated rising signal UP.

The descending signal integrated unit 9 calculates the logical sum of the first descending signal dw1 output by the first phase comparator 1-1 and the second descending signal dw2 output by the second phase comparator 1-2. , Outputs the integrated descending signal DW. The descending signal integrater 9 includes NOT circuits 91 and 92 and a NAND circuit 93.

The NOT circuit 91 receives the first descending signal dw1 at the input terminal and outputs the NOT signal at the output terminal. The NOT circuit 92 receives a second descending signal dw2 at the input terminal and outputs a NOT signal at the output terminal. At the input terminal, the NAND circuit 93 inputs the NOT signal output by the NOT circuits 91 and 92, and outputs the NAND signal. Here, this NAND signal is an integrated descending signal DW.

The charge pump 2 outputs the current signal Icpo according to the pulse width of the integrated rising signal UP output by the rising signal integrating device 8 and the integrated falling signal DW output by the falling signal integrating device 9. The charge pump 2 includes constant current sources 21, 22 and switches 23, 24.

The switch 23 is turned on when the integrated rising signal UP is the High signal “1”, and is turned OFF when the integrated rising signal UP is the Low signal “0”. The constant current source 21 supplies an electric charge to the capacitor 31 described later when the switch 23 is ON.

The switch 24 is turned on when the integrated descending signal DW is the High signal “1”, and is turned OFF when the integrated descending signal DW is the Low signal “0”. The constant current source 22 draws electric charge from the capacitor 31 described later when the switch 24 is ON.

The loop filter 3 has a capacitor 31 and a resistor 32, and converts the current signal Icpo output by the charge pump 2 into a voltage signal input to the oscillator 4. Here, the loop filter 3 is not limited to the one in which the capacitor 31 and the resistor 32 are connected in series.

The output waveforms of the phase comparators 1-1 and 1-2 and the charge pump 2 of the PLL circuit P of the second embodiment of the present disclosure are shown in FIGS. 22 to 25. The method of generating the first and second ascending signals up1 and up2 and the first and second descending signals dw1 and dw2 is the same as the method of generating the ascending signal up and the descending signal dw shown in FIG. For the first and second ascending signals up1 and up2 and the first and second descending signals dw1 and dw2, narrow pulses corresponding to the circuit delays of the first and second phase comparators 1-1 and 1-2 are generated. It is output and is shown on a white background. Narrow pulses corresponding to the circuit delays of the first and second phase comparators 1-1 and 1-2 are not output to the integrated ascending signal UP, the integrated descending signal DW, and the current signal Icpo. During the narrow pulse period according to the circuit delay of the first and second phase comparators 1-1 and 1-2, both the switch for supplying electric charge to the capacitor and the switch for extracting the electric charge from the capacitor are used. This is because it turns on.

The upper part of FIG. 22 shows the time when the phase of the feedback signal fb is 90 ° earlier than the phase of the reference signal ref. The first descending signal dw1 has a pulse width corresponding to a phase advance of 90 ° (based on 2 division before) of the positive phase divided feedback signal fb2 with respect to the positive phase divided reference signal ref2. The second descending signal dw2 has a pulse width corresponding to a phase advance of 450 ° (based on 2 divisions before) of the phase division feedback signal fb2x of the opposite phase with respect to the positive phase division reference signal ref2. The integrated descending signal DW has a pulse width proportional to the phase 450 ° (based on 2 divisions before) as the logical sum of the first descending signal dw1 and the second descending signal dw2. The current signal Icpo draws charge from the capacitor 31 in proportion to the phase 450 ° (based on before division by 2).

The lower part of FIG. 22 shows when the phase of the feedback signal fb is equal to the phase of the reference signal ref. The second descending signal dw2 has a pulse width corresponding to the phase advance 360 ° (based on 2 divisions before) of the phase division feedback signal fb2x with respect to the positive phase division reference signal ref2. The integrated descending signal DW has a pulse width proportional to the phase 360 ° (based on two divisions before) as the logical sum of the first descending signal dw1 and the second descending signal dw2. The current signal Icpo draws charge from the capacitor 31 in proportion to the phase 360 ° (with reference to two divisions before).

The upper part of FIG. 23 shows the time when the phase of the feedback signal fb is 90 ° later than the phase of the reference signal ref. The first rising signal up1 has a pulse width corresponding to a phase delay of 90 ° (based on 2 division before) of the positive phase divided feedback signal fb2 with respect to the positive phase divided reference signal ref2. The second descending signal dw2 has a pulse width corresponding to the phase advance 270 ° (based on 2 division before) of the phase division feedback signal fb2x of the opposite phase with respect to the positive phase division reference signal ref2. The integrated rising signal UP has a pulse width proportional to the phase 90 ° (based on 2 divisions before) as the logical sum of the first rising signal up1 and the second rising signal up2. The integrated descending signal DW has a pulse width proportional to the phase 270 ° (based on two divisions before) as the logical sum of the first descending signal dw1 and the second descending signal dw2. The current signal Icpo extracts charges from the capacitor 31 in proportion to the phase of 270 ° -90 ° = 180 ° (based on 2 divisions before).

The time when the phase of the feedback signal fb is 180 ° later than the phase of the reference signal ref is shown in the lower part of FIG. The first rising signal up1 has a pulse width corresponding to a phase delay of 180 ° (based on 2 division before) of the positive phase divided feedback signal fb2 with respect to the positive phase divided reference signal ref2. The second descending signal dw2 has a pulse width corresponding to the phase advance 180 ° (based on 2 division before) of the phase division feedback signal fb2x of the opposite phase with respect to the positive phase division reference signal ref2. The integrated rising signal UP has a pulse width proportional to the phase 180 ° (based on 2 divisions before) as the logical sum of the first rising signal up1 and the second rising signal up2. The integrated descending signal DW has a pulse width proportional to the phase 180 ° (based on 2 divisions before) as the logical sum of the first descending signal dw1 and the second descending signal dw2. The current signal Icpo does not supply charge to or extract charge from the capacitor 31.

That is, the oscillation frequency of the oscillator 4 is locked by the phase difference + πrad of the feedback signal fb before division by 2 with respect to the phase of the reference signal ref before division by 2 and 2 minutes with respect to the phase of the reference signal ref before division by 2. In the vicinity of the phase difference + πrad of the feedback signal fb before the lap, the first rising signal up1 and the second falling signal dw2 have a wide pulse width corresponding to the phase difference πrad before dividing by two.

The upper part of FIG. 24 shows when the phase of the feedback signal fb is 270 ° later than the phase of the reference signal ref. The first rising signal up1 has a pulse width corresponding to a phase delay of 270 ° (based on 2 division before) of the positive phase divided feedback signal fb2 with respect to the positive phase divided reference signal ref2. The second descending signal dw2 has a pulse width corresponding to a phase advance of 90 ° (based on 2 divisions before) of the phase division feedback signal fb2x of the opposite phase with respect to the positive phase division reference signal ref2. The integrated rising signal UP has a pulse width proportional to the phase 270 ° (based on two divisions before) as the logical sum of the first rising signal up1 and the second rising signal up2. The integrated descending signal DW has a pulse width proportional to the phase 90 ° (based on two divisions before) as the logical sum of the first descending signal dw1 and the second descending signal dw2. The current signal Icpo supplies electric charge to the capacitor 31 in proportion to the phase of 270 ° -90 ° = 180 ° (based on 2 divisions before).

The time when the phase of the feedback signal fb is 360 ° later than the phase of the reference signal ref is shown in the lower part of FIG. 24. The first rising signal up1 has a pulse width corresponding to a phase delay of 360 ° (based on 2 division before) of the positive phase divided feedback signal fb2 with respect to the positive phase divided reference signal ref2. The integrated rising signal UP has a pulse width proportional to the phase 360 ° (based on 2 divisions before) as the logical sum of the first rising signal up1 and the second rising signal up2. The current signal Icpo supplies electric charge to the capacitor 31 in proportion to the phase 360 ° (with reference to two divisions before).

FIG. 25 shows when the phase of the feedback signal fb is 450 ° later than the phase of the reference signal ref. The first rising signal up1 has a pulse width corresponding to a phase delay of 450 ° (based on 2 division before) of the positive phase divided feedback signal fb2 with respect to the positive phase divided reference signal ref2. The second rising signal up2 has a pulse width corresponding to a phase delay of 90 ° (based on 2 divisions before) of the phase division feedback signal fb2x with respect to the positive phase division reference signal ref2. The integrated rising signal UP has a pulse width proportional to the phase 450 ° (based on 2 divisions before) as the logical sum of the first rising signal up1 and the second rising signal up2. The current signal Icpo supplies electric charge to the capacitor 31 in proportion to the phase of 450 ° (based on the two divisions before).

FIG. 26 shows the phase detection characteristics of the first and second phase comparators 1-1 and 1-2 and the charge pump 2 of the PLL circuit P of the second embodiment of the present disclosure. The horizontal axis shows the difference in the phase of the feedback signal fb with respect to the phase of the reference signal ref with the lock point + πrad as a reference. The phase detection characteristic of the broken line is the phase detection characteristic of the first system, the phase detection characteristic of the one-point chain line is the phase detection characteristic of the second system, and the phase detection characteristic of the solid line is the phase detection characteristic of the first and second systems. It is a phase detection characteristic by the integrated system.

In the phase detection characteristic shown in FIG. 4, the input phase difference becomes 0 every 2π rad, whereas in the phase detection characteristic by the first and second systems, the input phase difference is detected every 4π rad. The output becomes 0. The reasons why the phase detection characteristics are different in this way are that (1) the frequency division reference signal ref2 and the frequency division feedback signal fb2 are divided by two as compared with the reference signal ref and the feedback signal fb, and (2) minutes. The phase difference of the divided feedback signal fb2 with respect to the phase of the circumferential reference signal ref2 may be equal to the phase difference of the feedback signal fb with respect to the phase of the reference signal ref2. In the transition from the first and second prior art techniques to the second embodiment of the present disclosure, in order to align the specifications such as the bandwidth of the PLL, the inclinations of the phase detection characteristics shown in FIGS. 26 are shown in FIGS. It must be the same as the slope of the phase detection characteristic shown, and the current of each charge pump of the second embodiment of the present disclosure needs to be half the current of each charge pump of the first and second prior art. ..

As shown in FIG. 26, in the PLL circuit P having a high frequency of the reference signal ref, even if the through rate is low with respect to the first and second rising signals up1 and up2 and the first and second falling signals dw1 and dw2. It is possible to improve the linearity of the phase detection characteristics of the first and second phase comparators 1-1 and 1-2 and the charge pump 2 while having the frequency discrimination function.

Here, the integrated rising signal UP is a logical sum signal of the first rising signal up1 and the second rising signal up2. The integrated down signal DW is a logical sum signal of the first down signal dw1 and the second down signal dw2. Therefore, at a point distant from the lock point + πrad by ± πrad, the phase detection characteristic by the system in which the first and second systems are integrated has a kink.

Here, when the frequency divider 5 uses MASH, the MASH order is M and the decimal point frequency divider is N, and the decimal point divider is a decimal point divider, the phase swing width of MASH is 2 ^M / N × 2πrad. Is. Therefore, in the input phase difference width πrad in which the linearity of the phase detection characteristics of the first and second phase comparators 1-1 and 1-2 and the charge pump 2 is ensured, the swing width of the phase of MASH is 2 ^M /. It is desirable that N × 2π rad is included. Then, the linearity of the phase detection characteristics of the first and second phase comparators 1-1 and 1-2 and the charge pump 2 can be improved over a swing width of 2 ^M / N × 2πrad of the phase of MASH. ..

In the PLL circuit P of the second embodiment of the present disclosure, as compared with the PLL circuit P of the first embodiment of the present disclosure, only one charge pump 2 is arranged, so that the current consumption of the charge pump 2 is reduced. be able to.

In the above description, the first phase comparator 1-1 has the first rising signal up1 according to the difference in the phase of the positive phase divided feedback signal fb2 with respect to the phase of the positive phase divided reference signal ref2. And the first descending signal dw1 is output, and the second phase comparator 1-2 outputs the phase difference of the frequency dividing feedback signal fb2x of the opposite phase with respect to the phase of the frequency dividing reference signal ref2 of the positive phase. The second rising signal up2 and the second falling signal dw2 are output, and the lock point is + πrad.

Here, as a modified example, as shown in FIG. 27, the first phase comparator 1-1 is the difference in the phase of the positive phase divided feedback signal fb2 with respect to the phase of the positive phase divided reference signal ref2. The first ascending signal up1 and the first descending signal dw1 may be output depending on the phase, and the second phase comparator 1-2 has a positive phase with respect to the phase of the opposite phase division reference signal ref2x. The second ascending signal up2 and the second descending signal dw2 may be output depending on the phase difference of the divided feedback signal fb2, and the lock point may be −πrad.

Alternatively, as a modified example, as shown in FIG. 28, the first phase comparator 1-1 determines the difference in the phase of the opposite-phase divided feedback signal fb2x with respect to the phase of the opposite-phase divided reference signal ref2x. Depending on the situation, the first rising signal up1 and the first falling signal dw1 may be output, and the second phase comparator 1-2 divides the phase of the positive phase division reference signal ref2 into the opposite phase. The second ascending signal up2 and the second descending signal dw2 may be output according to the phase difference of the peripheral feedback signal fb2x, and the lock point may be −πrad.

Alternatively, as a modification, as shown in FIG. 29, the first phase comparator 1-1 determines the difference in the phase of the anti-phase division feedback signal fb2x with respect to the phase of the anti-phase division reference signal ref2x. Depending on the situation, the first ascending signal up1 and the first descending signal dw1 may be output, and the second phase comparator 1-2 is a positive phase component with respect to the phase of the opposite phase frequency dividing reference signal ref2x. The second ascending signal up2 and the second descending signal dw2 may be output according to the phase difference of the peripheral feedback signal fb2, and the lock point may be + πrad.

Summarizing the above, one of the frequency dividing reference signal and the frequency dividing feedback signal may be input in phase to the first and second phase comparators 1-1 and 1-2, and the other signal may be input. May be input in opposite phase to the first and second phase comparators 1-1 and 1-2.

In the above description, the reference signal divider 6 divides the reference signal ref input to the PLL circuit P by two, and the feedback signal divider 7 divides the feedback signal fb output by the divider 5 by two. The lock point is ± π rad, and π ≧ 2 ^M / N × 2π holds.

Here, as a modification, the reference signal divider 6 may divide the reference signal ref input to the PLL circuit P by 2 ⁿ (n is a natural number), and the feedback signal divider 7 divides the frequency. The feedback signal fb output by the device 5 may be divided by 2 ⁿ , the lock point may be ± nπrad, and nπ ≧ 2 ^M / N × 2π may be established.

However, when the reference signal ref and the feedback signal fb are divided by two, the first ascending signal up1 and the second descending signal dw2 are compared with the case where the reference signal ref and the feedback signal fb are divided by 2 ^n. It has a pulse width corresponding only to the phase difference πrad before the division by 2 and can reduce the ON time of the switches 23 and 24 of the charge pump 2 and reduce the output noise of the charge pump 2.

When the frequency of the feedback signal fb is higher than the frequency of the reference signal ref, even if the ascending signal up due to the delayed phase is initially output, once the descending signal dw due to the advancing phase is output, the descending due to the advancing phase is subsequently output. Continue to output the signal dw. On the contrary, when the frequency of the feedback signal fb is lower than the frequency of the reference signal ref, even if the descending signal dw due to the leading phase is output at the initial stage, once the rising signal up due to the delayed phase is output, it depends on the delayed phase thereafter. Continue to output the rising signal up. Therefore, the PLL circuit P does not transition to an unstable state.

The PLL circuit of the present disclosure is particularly effective when the frequency of the reference signal is high.

P: PLL circuit 1: Phase comparator 1-1: 1 First phase comparator 1-2: 2nd phase comparator 2: Charge pump 2-1: 1st charge pump 2-2: 2nd charge Pump 3: Loop filter 4: Oscillator 5: Divider 6: Reference signal divider 7: Feedback signal divider 8: Up signal combiner 9: Down signal combiner 11, 11-1, 11-2, 12 , 12-1, 12-2: Delay flip flop circuit 13, 13-1, 13-2: AND circuit 14: Delay circuit 15: EXOR circuit 21, 21-1, 21-2, 22, 22-1, 22 -2: Constant current sources 23, 23-1, 23-2, 24, 24-1, 24-2: Switch 31: Capacitor 32: Resistors 81, 82, 91, 92: NOT circuit 83, 93: NAND circuit

Claims (4)

It is a PLL (Phase-Locked-Loop) circuit.
An oscillator that controls the oscillation frequency based on a voltage signal,
A frequency divider that divides the oscillation signal output by the oscillator, and
A reference signal divider that divides the reference signal input to the PLL circuit by 2 ⁿ (n is a natural number) and outputs a positive-phase divided reference signal and a negative-phase divided reference signal.
A feedback signal divider that divides the feedback signal output by the frequency divider by 2 ⁿ and outputs a positive phase divided feedback signal and a negative phase divided feedback signal.
Depending on the phase difference of the positive phase divided feedback signal output by the feedback signal divider with respect to the phase of the positive phase divided reference signal output by the reference signal divider, or the reference. The oscillation frequency of the oscillator according to the difference in phase of the opposite-phase divided feedback signal output by the feedback signal divider with respect to the phase of the opposite-phase divided reference signal output by the signal divider. A delay flip-flop type first phase comparator that outputs a first rising signal instructing the rise of the above and a first falling signal instructing the falling of the oscillation frequency of the oscillator.
Depending on the phase difference of the opposite-phase divided feedback signal output by the feedback signal divider with respect to the phase of the positive-phase divided reference signal output by the reference signal divider, or the reference. The oscillation frequency of the oscillator according to the phase difference of the positive-phase divided feedback signal output by the feedback signal divider with respect to the phase of the opposite-phase divided reference signal output by the signal divider. A delay flip-flop type second phase comparator that outputs a second rising signal instructing the rise of the above and a second falling signal instructing the falling of the oscillation frequency of the oscillator.
A first charge pump that outputs a first current signal according to the pulse widths of the first rising signal and the first falling signal output by the first phase comparator.
A second charge pump that outputs a second current signal according to the pulse widths of the second rising signal and the second falling signal output by the second phase comparator.
A capacitor that integrates the first current signal output by the first charge pump and the second current signal output by the second charge pump and converts it into the voltage signal input to the oscillator. With a loop filter
A PLL circuit comprising. It is a PLL (Phase-Locked-Loop) circuit.
An oscillator that controls the oscillation frequency based on a voltage signal,
A frequency divider that divides the oscillation signal output by the oscillator, and
A reference signal divider that divides the reference signal input to the PLL circuit by 2 ⁿ (n is a natural number) and outputs a positive-phase divided reference signal and a negative-phase divided reference signal.
A feedback signal divider that divides the feedback signal output by the frequency divider by 2 ⁿ and outputs a positive phase divided feedback signal and a negative phase divided feedback signal.
Depending on the phase difference of the positive phase divided feedback signal output by the feedback signal divider with respect to the phase of the positive phase divided reference signal output by the reference signal divider, or the reference. The oscillation frequency of the oscillator according to the difference in phase of the opposite-phase divided feedback signal output by the feedback signal divider with respect to the phase of the opposite-phase divided reference signal output by the signal divider. A delay flip-flop type first phase comparator that outputs a first rising signal instructing the rise of the above and a first falling signal instructing the falling of the oscillation frequency of the oscillator.
Depending on the phase difference of the opposite-phase divided feedback signal output by the feedback signal divider with respect to the phase of the positive-phase divided reference signal output by the reference signal divider, or the reference. The oscillation frequency of the oscillator according to the phase difference of the positive-phase divided feedback signal output by the feedback signal divider with respect to the phase of the opposite-phase divided reference signal output by the signal divider. A delay flip-flop type second phase comparator that outputs a second rising signal instructing the rise of the above and a second falling signal instructing the falling of the oscillation frequency of the oscillator.
An ascending signal integrator that calculates the logical sum of the first ascending signal output by the first phase comparator and the second ascending signal output by the second phase comparator and outputs an integrated ascending signal. When,
A down signal integrater that calculates the logical sum of the first down signal output by the first phase comparator and the second down signal output by the second phase comparer and outputs an integrated down signal. When,
A charge pump that outputs a current signal according to the pulse width of the integrated ascending signal output by the ascending signal integrating unit and the integrated descending signal output by the descending signal integrating unit.
A loop filter having a capacitor that converts the current signal output by the charge pump into the voltage signal input to the oscillator.
A PLL circuit comprising. The frequency divider is a decimal point divider that uses MASH (Multi-stAge noise Shaping) and has a MASH order of M and a decimal point divider of N.
The PLL circuit according to claim 1 or 2, wherein nπ ≧ 2 ^M / N × 2π is established between the MASH order M and the decimal point division number N. The reference signal divider divides the reference signal input to the PLL circuit by two.
The PLL circuit according to any one of claims 1 to 3, wherein the feedback signal divider divides the feedback signal output by the divider by two.

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