JP6823114B1 - Oscillator circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an oscillation circuit capable of outputting a clock signal even when the type of an oscillator is changed and capable of suppressing power consumption. SOLUTION: An oscillation circuit 150 is connected in parallel to an oscillator 5, and a buffer circuit 1 that outputs an amplified output voltage synchronized with an oscillation voltage from the oscillator 5 by inputting a first DC current, and an output voltage. A current adjusting circuit 9 is provided, which applies a second DC current having a current value corresponding to a difference voltage obtained by subtracting the level of the output voltage from a preset set voltage to the first DC current. The set voltage is set to a value at which the clock signal output circuit 10 that generates a clock signal synchronized with the output voltage from the output voltage can output the clock signal. [Selection diagram] Fig. 2

Description

The present invention relates to the output of a clock signal.

Crystal oscillator circuits are widely used as clock signal generators for digital circuits.

FIG. 1 is a conceptual diagram showing the configuration of an oscillator circuit 150, which is an example of a general oscillator circuit. The oscillation circuit 150 includes a buffer circuit 1, a DC feedback resistor 2, load capacitances 3 and 4, an oscillator 5, a constant current source 6, and a clock signal output circuit 10.

The oscillator 5 generates a voltage that vibrates at a unique frequency. The oscillator 5 is typically a crystal oscillator.

The buffer circuit 1 is generally an inverter. The buffer circuit 1 outputs an amplified sinusoidal voltage having the same frequency as the vibration voltage generated by the vibrator 5. The output is input to the clock signal output circuit 10 and is input to the oscillator 5 by positive feedback. The vibration of the vibrator 5 is maintained by the input.

The constant current source 6 inputs a DC supply current having a predetermined current value to the buffer circuit 1. The supply current causes the transistor included in the buffer circuit 1 to perform a signal amplification operation, limits the through current flowing through the buffer circuit 1 (see the background technology of Patent Document 1), and suppresses power consumption.

The load capacitances 3 and 4 adjust the frequency of the vibration voltage generated by the vibrator 5.

The clock signal output circuit 10 includes an inverter circuit (not shown). Then, the clock signal output circuit 10 converts the sine wave voltage input from the buffer circuit 1 into a square waveform by the inverter circuit, and outputs the clock signal to the terminal 11.

Here, Patent Document 1 describes a piezoelectric vibrator, an inverter that amplifies the vibration voltage, a Schmidt trigger circuit that shapes the output of the inverter into a waveform and outputs an oscillation output signal, and a constant current source that supplies current to those power supplies. An oscillation circuit including the above is disclosed.

Further, Patent Document 2 has a control circuit that generates a DC voltage corresponding to the amplitude of an AC signal component included in the output voltage of the inverting amplifier circuit, and the load drive capability of the inverting amplifier circuit is continuously valued by the DC voltage. Disclosed is an integrated circuit device having an oscillating circuit that is constantly controlled.

Japanese Unexamined Patent Publication No. 2005-045695 JP-A-59-114908

In the oscillation circuit 150 shown in FIG. 1, the current value of the current supplied by the constant current source 6 to the buffer circuit 1 is such that the clock signal output by the clock signal output circuit 10 is continuously and stably performed. The power consumption of the oscillation circuit 150 is optimized to a small value. However, the optimized current value differs depending on the type of the oscillator 5. The reason is that the parasitic capacitance may differ depending on the type of the vibrator 5, and the current is also used for charging the parasitic capacitance, so that the required current differs depending on the difference in the parasitic capacitance.

When the parasitic capacitance is large, the gain of the buffer circuit 1 decreases when the supply current from the constant current source 6 to the buffer circuit 1 is constant. The reason is conceptually as follows. That is, the supply current is also used for signal amplification by the transistor included in the buffer circuit 1 as described in the section of background technology. When the supply current is constant, the portion of the supply current used for charging the parasitic capacitance increases, and the portion used for signal amplification by the transistor decreases. Therefore, the gain of the buffer circuit 1 is reduced. Therefore, the amplitude of the sinusoidal voltage output from the buffer circuit 1 decreases. If the amplitude of the sinusoidal voltage is too small, the clock signal output circuit 10 does not output the clock signal. The clock signal output circuit 10 generates a clock signal by turning on and off the power supply voltage at the timing when the sinusoidal voltage becomes zero level by the inverter circuit. However, as is well known, if the level of the input sinusoidal voltage is too low, the inverter circuit cannot turn on / off the power supply voltage at the timing when the sinusoidal voltage reaches the zero level. In that case, the clock signal output circuit 10 does not output the clock signal.

In order to solve this problem, it is effective to set the value of the current supplied from the constant current source 6 to the buffer circuit 1 to a large value according to the assumed value of the parasitic capacitance of the vibrator 5. .. However, in that case, if the parasitic capacitance of the vibrator 5 is small, an unnecessarily large supply current is input to the buffer circuit. The unnecessarily large DC current of the supply current is simply consumed in the oscillator circuit 150. Therefore, the power consumption of the oscillation circuit 150 becomes unnecessarily large.

An object of the present invention is to provide an oscillation circuit or the like that enables output of a clock signal even when the type of oscillator is changed and can suppress power consumption.

The oscillation circuit of the present invention has a buffer circuit that is connected in parallel to the transducer and outputs an amplified output voltage synchronized with the oscillation voltage from the transducer by inputting the first DC current, and the level of the output voltage. The output voltage includes a current adjusting circuit that applies a second DC current having a current value corresponding to a differential voltage subtracted from a preset set voltage to the first DC current, and the set voltage is derived from the output voltage. The clock signal output circuit that generates a clock signal synchronized with the output voltage is set to a value capable of outputting the clock signal.

The oscillation circuit or the like of the present invention can output a clock signal even when the type of oscillator is changed, and can suppress power consumption.

It is a conceptual diagram which shows the structural example of a general oscillation circuit. It is a conceptual diagram which shows the structural example of the oscillation circuit of this embodiment. It is a conceptual diagram which shows the structural example of the voltage level setting circuit and the current adjustment circuit. It is an image diagram which shows the time change example of each voltage and current when an oscillator whose parasitic capacitance is larger than a reference value is connected. It is an image diagram which shows the time change example of each voltage and current when an oscillator whose parasitic capacitance is smaller than a reference value is connected. It is a block diagram which shows the minimum structure of the oscillation circuit of an embodiment.

In the oscillation circuit of the present embodiment, when the parasitic capacitance of the connected oscillator is larger than the reference value, the current corresponding to the difference from the set voltage of the amplitude of the output signal output from the buffer circuit to the clock signal output circuit. Is added to the supply current to the buffer circuit. Then, the oscillation circuit makes the amplitude of the output signal equal to the set voltage. As a result, the oscillation circuit enables the output of the clock signal from the clock signal output circuit even when the parasitic capacitance of the connected oscillator is too large.

The oscillation circuit also has a current corresponding to the difference from the set voltage of the amplitude of the output signal output from the buffer circuit to the clock signal output circuit when the parasitic capacitance of the connected oscillator is smaller than the reference value. Is subtracted from the supply current to the buffer circuit. Then, the oscillation circuit makes the amplitude of the output signal equal to the set voltage. As a result, when the parasitic capacitance of the connected oscillator is too small, the oscillation circuit suppresses the power consumed by the unnecessarily large supply current to save power.
[Configuration and operation]
FIG. 2 is a conceptual diagram showing the configuration of the oscillation circuit 150, which is an example of the oscillation circuit of the present embodiment. The oscillation circuit 150 shown in FIG. 2 includes a voltage level setting circuit 8 and a current adjustment circuit 9 in addition to the configuration included in the oscillation circuit 150 shown in FIG.

A set voltage is input to the terminal 12. The set voltage is the voltage level of the sine wave voltage of the terminal A output from the buffer circuit 1 to the clock signal output circuit 10. For the set voltage, for example, when the parasitic capacitance of the transducer 5 is a standard value, the clock signal output circuit 10 stably and continuously outputs the clock signal, and the constant current source 6 to the buffer circuit 1 The supply current to is set so that it is not too high.

The voltage level setting circuit 8 inputs a voltage corresponding to the difference voltage obtained by subtracting the amplitude of the sinusoidal voltage of the terminal A from the set voltage to the current adjusting circuit 9.

When the amplitude of the sinusoidal voltage is larger than the set voltage, the current adjusting circuit 9 causes a part of the current supplied from the constant current source 6 to the buffer circuit 1 to flow to the ground through the current adjusting circuit 9. As a result, the current adjusting circuit 9 reduces the supply current to the buffer circuit 1. The supply current is used for amplifying the sinusoidal voltage from the buffer circuit 1, and the smaller the supply current, the smaller the amplitude of the sinusoidal voltage. Therefore, the current adjusting circuit 9 reduces the amplitude of the sinusoidal voltage by reducing the supply current to the buffer circuit 1. As a result, the current adjusting circuit 9 makes the sinusoidal voltage equal to the set voltage.

On the other hand, when the sinusoidal voltage is smaller than the set voltage, the current adjusting circuit 9 adds the current supplied from the current adjusting circuit 9 to the buffer circuit 1 to the current supplied from the constant current source 6 to the buffer circuit 1. .. As a result, the current adjustment circuit 9 increases the amplitude of the sinusoidal voltage. As a result, the current adjusting circuit 9 makes the amplitude of the sinusoidal voltage equal to the set voltage.

FIG. 3 is a conceptual diagram showing a configuration example of the voltage level setting circuit 8 and the current adjustment circuit 9 shown in FIG.

The voltage level setting circuit 8 includes a peak hold circuit 85 and an addition / subtraction circuit 84. The peak hold circuit 85 includes an amplifier circuit 81, a diode 82, a capacitance 83, and an addition / subtraction circuit 84. The amplifier circuit 81 is an operational amplifier. The configuration of the peak hold circuit 85 is a well-known configuration, and as is well known, it corresponds to the amplitude of the sinusoidal voltage input from the buffer circuit 1 via the A terminal shown in FIG. 2 by the action of negative feedback. The electric charge to be stored is stored in the capacity 83. As a result, from the capacitance 83, a DC voltage having a value equal to the amplitude of the sinusoidal voltage is input to the addition / subtraction circuit 84.

The peak hold circuit 85 may have a configuration other than that shown in FIG.

The addition / subtraction circuit 84 adjusts the current by subtracting the subtraction voltage obtained by subtracting the amplitude voltage of the sinusoidal voltage from the peak hold circuit 85 from the above-mentioned set voltage input from the terminal 12 and further adding the added voltage to the set voltage. Input to circuit 9. A well-known configuration can be used as the addition / subtraction circuit 84.

The subtraction voltage becomes a positive value when the set voltage is larger than the voltage of the amplitude. In that case, the added voltage becomes larger than the set voltage. On the other hand, the subtraction voltage becomes a negative value when the set voltage is smaller than the level. In that case, the added voltage becomes smaller than the set voltage.

The current adjusting circuit 9 includes DC current generating circuits 111 and 112 and current mirror circuits 121, 122 and 123. Terminal 103 is connected to a current source (not shown).

The DC current generation circuit 111 includes an amplifier circuit 91, an N-channel MOSFET 93, and a resistor 92. Here, MOSFET is an abbreviation for metal-oxide-semiconductor field-effect transistor. The configuration of the DC current generation circuit 111 is well known. The DC current generation circuit 111 causes a current corresponding to the above-mentioned added voltage input from the addition / subtraction circuit 84 of the voltage level setting circuit 8 to flow downward to the positive input terminal of the amplifier circuit 91. As a result, a current having the same current value flows downward in the P-channel MOSFET 94 of the current mirror circuit 121.

The current mirror circuit 121 includes P-channel MOSFETs 94 and 95. The configuration shown in FIG. 3 of the current mirror circuit 121 is well known. The current mirror circuit 121 causes the P-channel MOSFET 95 to flow downward toward the terminal C with a current having a current value equal to the current flowing through the P-channel MOSFET 94.

On the other hand, the DC current generation circuit 112 includes an amplifier circuit 102, an N-channel MOSFET 101, and a resistor 100. The configuration of the DC current generation circuit 112 is well known, similar to the configuration of the DC current generation circuit 111. The DC current generation circuit 112 downwards a current having a current value proportional to the value of the above-mentioned set voltage input from the terminal 12 to the positive input terminal of the amplifier circuit 102. As a result, a current having the same current value flows downward in the P-channel MOSFET 97 of the current mirror circuit 122.

The current mirror circuit 122 includes P-channel MOSFETs 96 and 97. The configuration shown in FIG. 3 of the current mirror circuit 122 is well known, similar to the configuration of the current mirror circuit 121. The current mirror circuit 122 causes the P-channel MOSFET 96 to flow downward with a current having a current value equal to the current flowing through the P-channel MOSFET 97.

The current flowing downward through the P-channel MOSFET 96 flows downward through the N-channel MOSFET 99 of the current mirror circuit 123.

The current mirror circuit 123 includes N-channel MOSFETs 98 and 99. The configuration shown in FIG. 3 of the current mirror circuit 123 is well known, as is the configuration of the current mirror circuits 121 and 122. The current mirror circuit 123 causes the N-channel MOSFET 98 to flow downward from the terminal C with a current having a current value equal to the current flowing through the N-channel MOSFET 99.

As described above, the P-channel MOSFET 95 causes a current corresponding to the added voltage to flow toward the terminal C, and the N-channel MOSFET 98 causes a current corresponding to the set voltage to flow from the terminal C toward the ground. As a result, a current proportional to the difference voltage, which is the difference between the added voltage and the set voltage, flows from the terminal C to the terminal B shown in FIG. The current flowing into the terminal B is a positive current when the subtracted voltage has a positive value. On the other hand, the current flowing into the terminal B is a negative current when the subtracted voltage has a negative value. Here, the fact that the current flowing into the terminal B is negative means that the current flows out from the terminal B. When a current flows out from the terminal B, the current flows to the ground through the N-channel MOSFET 98 via the terminal C in FIG.

As a result, from the terminal B shown in FIG. 2 to the buffer circuit 1, in addition to the current supplied from the constant current source, the decrease in the amplitude of the sinusoidal voltage from the buffer circuit 1 from the set voltage is applied. The current of the current value is added. Here, the decrease may be negative. In that case, from the terminal B shown in FIG. 2 to the buffer circuit 1, a current having a current value corresponding to the absolute value of the decrease is subtracted from the current supplied from the constant current source.

In FIG. 4, in the oscillation circuit 150 shown in FIG. 2, an oscillator 5 having a parasitic capacitance value larger than the reference value is connected as shown in FIG. 2, and the constant current source 6 starts supplying current to the buffer circuit 1. It is an image diagram which shows the example of the time change of each voltage and current in the case. The reference value is a capacitance value at which the level of the output voltage from the buffer circuit 1 becomes equal to the set voltage when the supply current to the buffer circuit 1 is equal to the output current from the constant current source 6.

The “set voltage” shown in FIG. 5 is the above-mentioned set voltage input to the terminals 12 of FIGS. 2 and 3. The "output from the buffer circuit 1" is a sine wave voltage output from the buffer circuit 1 shown in FIG. 2 to the clock signal output circuit 10, and is a voltage at the terminal A. The amplitude of the output voltage is the value of the envelope of the maximum value of the sinusoidal voltage, and is the voltage of the terminal D in FIG.

The "output current from the current adjusting circuit 9" is the current flowing from the current adjusting circuit 9 to the terminal B. The "input current to the buffer circuit 1" is the supply current input from the terminal B of FIG. 2 to the buffer circuit, and the current flowing from the constant current source 6 to the terminal B and the current flowing from the current adjusting circuit 9 to the terminal B. It is the sum of the current. The "output voltage from the clock signal output circuit 10" is the voltage of the clock signal output from the clock signal output circuit 10 of FIG. 2 to the terminal 11.

The time ta shown in FIG. 4 is the time immediately after the oscillator 5 is connected and the input of the supply current from the constant current source 6 to the buffer circuit 1 is started as shown in FIG. At time ta, the "output voltage amplitude" is significantly lower than the "set voltage". This is because the supply current is too small for the size of the parasitic capacitance of the vibrator 5. As described in the background art section, the supply current is used for signal amplification by the transistors in the buffer circuit 1 and is also allocated for charging the parasitic capacitance. Therefore, if the parasitic capacitance is large, the supply current allocated to the signal amplification by the transistor decreases, and the amplitude of the output voltage decreases.

At time ta, the "output voltage amplitude" is significantly lower than the "set voltage", so that the clock signal output circuit 10 does not generate a clock signal from the "output voltage from the buffer circuit 1". Therefore, the "output voltage from the clock signal output circuit 10" is low level.

The voltage level setting circuit 8 shown in FIGS. 2 and 3 inputs to the current adjustment circuit 9 an additional voltage obtained by adding a differential voltage obtained by subtracting the “output voltage amplitude” from the “set voltage” to the “set voltage”. .. As a result, the current adjusting circuit 9 increases the output current. As a result, the "input current to the buffer circuit 1" increases.

Along with this increase, the "output voltage amplitude" increases.

Then, at time tb, the differential voltage obtained by subtracting the "output voltage amplitude" from the "set voltage" becomes sufficiently small, and the cycle equal to the cycle of the "output voltage from the buffer circuit 1" from the clock signal output circuit 10. Clock signal is output. Then, at time tc, the "amplitude of the output voltage" becomes equal to the "set voltage". After that, the output of the clock signal from the clock signal output circuit 10 is continued.

FIG. 5 shows a case where the oscillator 5 having a parasitic capacitance smaller than the reference value in the oscillation circuit 150 shown in FIG. 2 is connected as shown in FIG. 2 and the current supply to the buffer circuit 1 by the constant current source 6 is started. It is an image diagram which shows the example of the time change of each voltage and current. Here, the reference value is the same as in the case of FIG.

Here, the "set voltage" shown in FIG. 4 is the above-mentioned set voltage input to the terminals 12 of FIGS. 2 and 3. The "output from the buffer circuit 1" is a sine wave voltage output from the buffer circuit shown in FIG. 2 to the clock signal output circuit 10, and is a voltage at the terminal A. Further, the “output voltage amplitude” is the voltage value of the envelope of the maximum value of the sinusoidal voltage, and is the voltage of the terminal D in FIG.

The "output current from the current adjusting circuit 9" is the current flowing from the current adjusting circuit 9 to the terminal B. However, in the case shown in FIG. 5, since the current is below the zero level, the current of the absolute value of the current flows from the terminal B to the current adjusting circuit 9.

The "input current to the buffer circuit 1" is a current input from the terminal B of FIG. 2 to the buffer circuit, and is a current flowing from the constant current source 6 to the terminal B and a current flowing from the current adjusting circuit 9 to the terminal B. Is the sum of. The "output voltage from the clock signal output circuit 10" is the voltage of the clock signal output from the clock signal output circuit 10 of FIG. 2 to the terminal 11.

The time td shown in FIG. 5 is the time immediately after the oscillator 5 is connected and the supply of the supply current from the constant current source 6 to the buffer circuit 1 is started as shown in FIG. At time td, the input current to the buffer circuit 1 is sufficiently large, so that the “output voltage amplitude” is higher than the “set voltage”. Therefore, the clock signal output circuit 10 generates a clock signal from the "output voltage from the buffer circuit 1", and the clock signal output circuit 10 outputs the clock signal.

However, at time td, the input current to the buffer circuit 1 is unnecessarily large. Therefore, the power obtained by multiplying the surplus current, which is an unnecessarily large current, by the resistance value of the current path of the buffer circuit 1 shown in FIG. 2 is unnecessarily consumed in the current path. That is, the state at time td is a state in which the power consumption of the oscillation circuit 150 is unnecessarily high.

The voltage level setting circuit 8 shown in FIGS. 2 and 3 sends an added voltage obtained by adding a differential voltage obtained by subtracting the voltage of the “output voltage amplitude” from the “set voltage” to the set voltage to the current adjusting circuit 9. To do. Then, the current adjusting circuit 9 increases the negative output current in the negative direction. That is, the current adjusting circuit 9 increases the current flowing from the terminal B to the ground via the current adjusting circuit 9. As a result, the "input current to the buffer circuit 1" is reduced.

Along with this decrease, the "output voltage amplitude" decreases.

Then, at time te, the "amplitude of the output voltage" becomes equal to the "set voltage". Since the "output voltage amplitude" is equal to the "set voltage", the output of the clock signal from the clock signal output circuit 10 is maintained. On the other hand, at time te, there is no surplus current. Therefore, at time te, the oscillation circuit 150 is in a state where the power consumption due to the surplus current is suppressed and the power consumption is low. After that, the state in which the output of the clock signal and the low power consumption are compatible is maintained.

The current flowing from the terminal B to the ground via the current adjustment circuit 9 flows from the terminal C in FIG. 3 to the ground via the N-channel MOSFET 98. Therefore, power is consumed according to the resistance between the source and drain of the N-channel MOSFET 98. However, in general, the resistance between the source and drain of a MOSFET is negligibly small. Therefore, the power consumption in the resistance between the source and drain of the N-channel MOSFET 98 can be ignored.
[effect]
In the oscillation circuit of the present embodiment, when the parasitic capacitance of the connected oscillator is larger than the reference value, the current corresponding to the difference from the set voltage of the amplitude of the output signal output from the buffer circuit to the clock signal output circuit. Is added to the supply current to the buffer circuit. As a result, the oscillator circuit makes the amplitude of the output signal equal to the set voltage. Therefore, the oscillation circuit enables the output of the clock signal from the clock signal output circuit even when the parasitic capacitance of the connected oscillator is large.

The oscillation circuit also has a current corresponding to the difference from the set voltage of the amplitude of the output signal output from the buffer circuit to the clock signal output circuit when the parasitic capacitance of the connected oscillator is smaller than the reference value. Is subtracted from the supply current to the buffer circuit. As a result, the oscillator circuit makes the amplitude of the output signal equal to the set voltage. Therefore, in the oscillation circuit, when the parasitic capacitance of the connected oscillator is small, the power consumed by the unnecessarily large supply current is suppressed to save power.

FIG. 6 is a block diagram showing the configuration of the oscillation circuit 100x, which is the minimum configuration of the oscillation circuit of the embodiment.

The oscillation circuit 150x includes a buffer circuit 1x and a current adjustment circuit 9x.

The buffer circuit is connected in parallel to the oscillator and outputs an amplified output voltage synchronized with the oscillation voltage from the oscillator by inputting the first direct current.

The current adjusting circuit 9x adds a buffer circuit and a second direct current having a current value corresponding to a difference voltage obtained by subtracting the level of the output voltage from a preset voltage set for the output voltage to the first direct current.

The set voltage is set to a value at which the clock signal output unit that outputs a clock signal synchronized with the output voltage can output the clock signal from the output voltage.

According to the above configuration, the oscillation circuit 150x adjusts the current value of the first direct current so that the level of the output voltage becomes the set voltage. Therefore, the oscillation circuit 150x enables the output of the clock signal even when the type of the oscillator is changed.

Further, when the amplitude of the output voltage is larger than the set voltage, the oscillation circuit 150x reduces the current value of the first direct current. As a result, the oscillation circuit 150x reduces the power consumption.

As described above, the oscillation circuit 150x can output the clock signal even when the type of the oscillator 5 is changed, and can suppress the power consumption.

Therefore, the oscillation circuit 150x exhibits the effects described in the section [Effects of the Invention] according to the above configuration.

Although each embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment, and further modifications, substitutions, and adjustments can be made without departing from the basic technical idea of the present invention. Can be added. For example, the composition of the elements shown in each drawing is an example for assisting the understanding of the present invention, and is not limited to the composition shown in these drawings.

1, 1x buffer circuit 2 DC feedback resistor 3, 4 load capacity 5 oscillator 6 constant current source 8 voltage level setting circuit 9, 9x current adjustment circuit 10 clock signal output circuit 11, 12, 103 terminals 81, 91, 102 amplification Circuit 82 Diode 83 Capacity 84 Addition / subtraction circuit 85 Peak hold circuit 92,100 Resistance 93,98,99,101 N-channel MOSFET
94, 95, 96, 97 P-channel MOSFET
150, 150x Oscillator circuit 111, 112 DC current generation circuit 121, 122, 123 Current mirror circuit

Claims (5)

A buffer circuit that is connected in parallel to the oscillator and outputs an amplified output voltage that is synchronized with the oscillation voltage from the oscillator by inputting the first direct current.
A current adjusting circuit that applies a second DC current having a current value corresponding to a difference voltage obtained by subtracting the output voltage level from a preset voltage set for the output voltage level to the first DC current.
With
The set voltage is set to a value at which a clock signal output circuit that outputs a clock signal synchronized with the output voltage from the output voltage can output the clock signal.
The current adjusting circuit includes a first DC current generator that generates a third DC current having a current value corresponding to an added voltage obtained by adding the difference voltage to the set voltage, and a fourth current value corresponding to the set voltage. A second DC current generator for generating a DC current is provided, and the second DC current is generated by excluding the fourth DC current from the third DC current.
The first direct current generator includes a first generator that generates a fifth direct current with a current value corresponding to the added voltage, and a third direct current generator that generates a third direct current with a current value equal to the fifth direct current. Equipped with a one-current mirror circuit
The second direct current generator includes a second direct current generator that generates a sixth direct current with a current value corresponding to the set voltage, and a second direct current generator that generates a seventh direct current with a current value equal to the sixth direct current. A current mirror circuit and a third current mirror circuit that generates the fourth direct current with a current value equal to the seventh direct current are provided.
The second direct current of the current value corresponding to the absolute value of the difference voltage may be passed to the ground via the source and drain of the field effect transistor provided in the third current mirror circuit.
Oscillation circuit.
The current adjusting circuit adds the second DC current having a current value corresponding to the difference voltage to the first DC current when the difference voltage is positive, and the absolute difference voltage when the difference voltage is negative. The oscillation circuit according to claim 1 , wherein the second direct current having a current value corresponding to the value is subtracted from the first direct current. The oscillation circuit according to claim 2 , wherein the positive case and the negative case occur depending on the type of the vibrator. The oscillation circuit according to claim 2 or 3 , wherein the positive case and the negative case are caused by the magnitude of the parasitic capacitance of the vibrator. The oscillation circuit according to any one of claims 1 to 4 , further comprising the clock signal output circuit.

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