JP6812160B2 - Control method of solid-state image sensor, image sensor and solid-state image sensor - Google Patents

Description

The present invention relates to a solid-state image sensor, an image pickup device, and a method for controlling a solid-state image sensor.

Patent Document 1 discloses a solid-state image sensor having an optical sensor and an analog-digital conversion circuit (hereinafter referred to as an AD conversion circuit) that converts an analog signal output from the optical sensor into a digital signal. Further, the document also discloses a solid-state image sensor whose circuit scale is reduced by connecting a plurality of optical sensors to a common AD conversion circuit.

JP-A-2002-44527

In a configuration in which a plurality of photoelectric conversion units share a signal processing circuit such as an AD conversion circuit as in the solid-state image pickup device described in Patent Document 1, signals obtained from the plurality of photoelectric conversion units are not processed at the same time. Therefore, processing in the signal processing circuit may take a long time. Therefore, both reduction of circuit scale and speeding up of processing can be an issue.

Therefore, an object of the present invention is to provide a solid-state image pickup device and an image pickup apparatus capable of both reducing the circuit scale and speeding up the processing.

The solid-state imaging device according to the embodiment of the present invention is provided corresponding to at least one first photoelectric conversion unit, a plurality of second photoelectric conversion units, and at least one said first photoelectric conversion unit. A first signal processing circuit that processes a first signal based on the charge generated by the first photoelectric conversion unit, and a plurality of the second photoelectric conversion units are provided. A second signal processing circuit that processes a second signal based on the charge generated by the photoelectric conversion unit 2 is provided between the first photoelectric conversion unit and the first signal processing circuit. A first amplification means for amplifying the first signal based on the charge generated by the first photoelectric conversion unit is provided between the second photoelectric conversion unit and the second signal processing circuit. A second amplification means for amplifying the second signal based on the charge generated by the second photoelectric conversion unit is provided, and the strength of the second signal is higher than the strength of the first signal. small, wherein the second number of photoelectric conversion units corresponding to the second signal processing circuit, rather multi than the first number of photoelectric conversion units corresponding to the first signal processing circuit, the second The amplification factor of the amplification means is smaller than the amplification factor of the first amplification means .

The imaging device according to the embodiment of the present invention is provided corresponding to at least one first photoelectric conversion unit, a plurality of second photoelectric conversion units, and at least one said first photoelectric conversion unit. A first signal processing circuit that processes a first signal based on the charge generated by the first photoelectric conversion unit, and a second signal processing circuit corresponding to the plurality of second photoelectric conversion units. A second signal processing circuit that processes a second signal based on the charge generated by the photoelectric conversion unit is provided between the first photoelectric conversion unit and the first signal processing circuit. The first amplification means for amplifying the first signal based on the charge generated by the photoelectric conversion unit 1 is provided between the second photoelectric conversion unit and the second signal processing circuit. A second amplification means for amplifying the second signal based on the charge generated by the second photoelectric conversion unit is provided, and the strength of the second signal is smaller than the strength of the first signal. , wherein the second number of photoelectric conversion units corresponding to the second signal processing circuit, wherein the first in many than the first number of photoelectric conversion units corresponding to the signal processing circuit, the second It is characterized by having a solid-state imaging element in which the amplification factor of the amplification means is smaller than the amplification factor of the first amplification means, and a calculation unit that performs an calculation on a signal output from the solid-state imaging element.

The method for controlling a solid-state image sensor according to an embodiment of the present invention corresponds to at least one first photoelectric conversion unit, a plurality of second photoelectric conversion units, and at least one of the first photoelectric conversion units. The first signal processing circuit provided in the above section, the second signal processing circuit provided corresponding to the plurality of the second photoelectric conversion units, the first photoelectric conversion unit, and the first photoelectric conversion unit. A first amplification means provided between the signal processing circuit and amplifying a first signal based on the charge generated by the first photoelectric conversion unit, the second photoelectric conversion unit, and the second photoelectric conversion unit. A method for controlling a solid-state image sensor , which is provided between a signal processing circuit and a second amplification means for amplifying a second signal based on a charge generated by the second photoelectric conversion unit . processing the first processing step and said second signal based on the electric charge produced in the second photoelectric conversion unit for processing the first signal based on the electric charges generated in the first photoelectric conversion unit The second processing step includes the second processing step in which the strength of the second signal is smaller than that of the first signal and is processed in the second processing step within a predetermined synchronization period. the number of signals, the amplification factor of the first processing rather multi than the number of said first signals to be processed in step, said second amplifying means, from the gain of the first amplifying means Is also small .

According to the present invention, there is provided a solid-state image sensor and an image pickup apparatus capable of both reducing the circuit scale and increasing the processing speed.

It is a block diagram which shows the structure of the image pickup apparatus which concerns on embodiment of this invention. It is a figure which shows the structure of the solid-state image sensor which concerns on embodiment of this invention. It is a circuit diagram which shows the structure of the unit block of the solid-state image sensor which concerns on embodiment of this invention. It is a layout figure which shows the arrangement of a photodiode and a microlens which concerns on embodiment of this invention. It is a timing chart which shows the driving method of the solid-state image sensor which concerns on embodiment of this invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
(Embodiment)
Hereinafter, the configuration of the image pickup device, the configuration of the solid-state image sensor, and the driving method of the solid-state image sensor according to the embodiment of the present invention will be described with reference to the drawings.

First, the configuration of the image pickup apparatus according to the embodiment will be described with reference to FIG. FIG. 1 is a block diagram showing a configuration of an image pickup apparatus according to the present embodiment. Examples of the image pickup apparatus include a digital still camera, a digital camcorder, and a surveillance camera.

The image pickup device includes a solid-state image sensor 1, a photographing lens 2, a photographing lens driving unit 3, an overall control / calculation unit 4, a memory 5, a display unit 6, a recording medium 7, an operation unit 8, and a signal processing unit 9. The photographing lens 2 may include one or more lenses. The incident light to the image pickup device passes through the photographing lens 2 and is imaged by the solid-state image pickup device 1. Further, the photographing lens 2 may further include an aperture that changes the amount of light passing through.

The photographing lens driving unit 3 controls the zoom, focus, aperture, etc. of the image pickup apparatus by driving the lens or the like of the photographing lens 2. The solid-state image sensor 1 converts an optical image generated by incident light into an electric signal, and outputs a signal for image generation to the signal processing unit 9. The signal processing unit 9 makes various corrections to the signal output from the solid-state image sensor 1. The overall control / calculation unit 4 has a function as a control unit that controls the entire image pickup apparatus and a function as a calculation unit that generates image data by performing various calculations on the signal output from the signal processing unit 9. Have. Further, when the solid-state image sensor 1 has a function of outputting a focus detection signal, the overall control / calculation unit 4 can also perform a focus detection operation using the focus detection signal.

The memory 5 is a memory circuit that temporarily stores image data. The display unit 6 is a display device that displays various information and captured images. The recording medium 7 is a detachable recording medium such as a semiconductor memory for recording and reading image data, or a recording medium built in an image pickup apparatus. The operation unit 8 is various interfaces of the image pickup device, and electrically receives an instruction input by the user via the input device of the image pickup device, an instruction input by an external control device via the communication path, and the like.

Next, with reference to FIGS. 2 (a) to 2 (c), FIGS. 3 (a) and 3 (b), and FIGS. 4 (a) to 4 (e), a solid-state imaging according to the present embodiment is performed. The configuration of the element will be described.

The solid-state image sensor 1 according to the present embodiment has a structure in which the first substrate 60 and the second substrate 70 are connected by a plurality of bumps 80 as an example of the element structure to which the present invention can be applied. FIG. 2A is a block diagram showing the configuration of the first substrate 60. The pixel array unit 10 and the peripheral circuit unit 12 are provided on the first substrate 60. The pixel array unit 10 has pixels 100 (first pixels) arranged in a matrix. Further, in a part of the rows of the pixel array unit 10, pixels 110 (second pixels) having a configuration different from that of the pixels 100 are arranged in place of the pixels 100. The peripheral circuit unit 12 may include a control circuit that generates a drive signal or the like of the pixel array unit 10, and a peripheral circuit such as an output circuit for outputting a signal from the solid-state image sensor 1.

FIG. 2B is a block diagram showing the configuration of the second substrate 70. The second substrate 70 is provided with a signal processing circuit array unit 30 and a peripheral circuit unit 22. The signal processing circuit array unit 30 has a signal processing circuit 200 (first signal processing circuit) arranged in a matrix. Further, a signal processing circuit 210 (second signal processing circuit) is provided in a part of the lines of the signal processing circuit array unit 30. The signal processing circuits 200 and 210 may include an AD conversion circuit that converts an analog signal output from the pixels 100 and 110 into a digital signal. The signal processing circuit 200 constitutes a first unit block together with pixels 100 arranged at adjacent positions. The signal processing circuit 210 constitutes a second unit block together with the pixels 110 arranged at adjacent positions. As shown in FIG. 2B, a plurality of unit blocks including a plurality of first unit blocks and a plurality of second unit blocks are arranged in a two-dimensional manner. The peripheral circuit unit 22 may include a control circuit that generates a drive signal or the like of the signal processing circuit array unit 30. The first unit block may further include a selection transistor arranged between the pixel 100 and the signal processing circuit 200. Further, the second unit block may further include a selection transistor arranged between the pixel 110 and the signal processing circuit 210.

FIG. 2 (c) is a diagram schematically showing a cross section of CC'in FIGS. 2 (a) and 2 (b). The first substrate 60 and the second substrate 70 are electrically and mechanically connected by a plurality of bumps 80. Circuit elements such as transistors forming the pixels 100 and 110 of the first substrate 60 and the peripheral circuit unit 12 are formed on the lower surface in the drawing, that is, the surface on the side to which the plurality of bumps 80 are connected. Circuit elements such as transistors constituting the signal processing circuits 200 and 210 of the second substrate 70 and the peripheral circuit unit 22 are formed on the upper surface in the drawing, that is, the surface on the side to which the plurality of bumps 80 are connected. The bump 80 is provided for each of the above-mentioned first unit block or the second unit block, and connects the pixels 100 and 110 of each unit block to the signal processing circuits 200 and 210.

A color filter 106 and a microlens 105 are formed on a surface of the first substrate 60 opposite to the surface to which the bump 80 is connected. The incident light on the solid-state image sensor 1 is incident from above in FIG. 2C, passes through the microlens 105 and the color filter 106, and is incident on the photoelectric conversion element in the pixel 100 of the first substrate 60. When the surface on which circuit elements such as transistors constituting the pixels 100 and 110 of the first substrate 60 and the peripheral circuit unit 12 are formed is the front surface, light is incident from the back surface. Therefore, the solid-state imaging of the present embodiment is performed. The element 1 is a back-illuminated solid-state image sensor.

It is also possible to form the pixels 100 and 110, the signal processing circuits 200 and 210, and the peripheral circuit units 12 and 22 on the same substrate. However, since the structure in which the first substrate 60 and the second substrate 70 are laminated is adopted in this embodiment, the pixels 100 and 110, the signal processing circuits 200 and 210, and the peripheral circuit units 12 and 22 are placed on the same substrate. The area of the photoelectric conversion element can be increased as compared with the case where it is formed. Therefore, the sensitivity is improved as compared with the case where each circuit element is formed on the same substrate.

FIG. 3A is a circuit diagram showing the configuration of the first unit block. FIG. 3B is a circuit diagram showing a second unit block.

First, the configuration of the first unit block will be described with reference to FIG. 3A. The first unit block includes a pixel 100, a signal processing circuit 200, and a selection transistor 204. The pixel 100 includes a photodiode (hereinafter referred to as PD) 101, a transfer transistor 102, a floating diffusion (hereinafter referred to as FD) 103, a reset transistor 104, and an input capacitance 107. Further, a selection transistor 204 is arranged between the pixel 100 and the signal processing circuit 200. Each transistor may be composed of a MOS transistor or the like. In the following description, it is assumed that each transistor is an N-type MOS transistor.

Although the selection transistor 204 may be formed on the second substrate 70, it may be formed on the first substrate 60. Further, the selection transistor 204 may be included in the signal processing circuit 200. Further, in the description of the present embodiment, since the input capacitance 107 is included in the pixel 100, it is assumed that the input capacitance 107 is formed on the first substrate 60, but the present invention is not limited to this. The input capacitance 107 may be formed on the second substrate 70, and by further providing a dielectric layer between the first substrate 60 and the second substrate 70, the first substrate 60 and the second substrate 70 may be formed. The input capacitance 107 may be formed between the 70s.

The PD101 is a photoelectric conversion unit (first photoelectric conversion unit) that generates and stores electric charges according to incident light by photoelectric conversion. The cathode of PD101 is connected to the source of transfer transistor 102, and the anode of PD101 is grounded. The drain of the transfer transistor 102 is connected to the FD 103. The transfer transistor 102 transfers the electric charge generated and accumulated by the PD 101 to the FD 103. The FD 103 is a diffusion region in which a voltage corresponding to the electric charge transferred from the PD 101 is generated. The source of the reset transistor 104 is connected to the FD 103, and the drain of the reset transistor 104 is connected to the power supply voltage line having the power supply voltage VDD. The reset transistor 104 resets the voltage of the FD 103 by moving the electric charge transferred to the FD 103 to the power supply voltage line. The FD 103 is connected to one terminal of the input capacitance 107. The other terminal of the input capacitance 107 is connected to the drain of the selection transistor 204. The source of the selection transistor 204 is connected to the signal processing circuit 200. A drive signal φTX output from the peripheral circuit unit 12 is input to the gate of the transfer transistor 102. A drive signal φRES output from the peripheral circuit unit 12 is input to the gate of the reset transistor 104. A drive signal φSEL output from the peripheral circuit unit 22 is input to the gate of the selection transistor 204. As described above, the signal processing circuit 200 is provided corresponding to the PD 101, and processes a signal (first signal) based on the electric charge generated by the PD 101.

Next, the configuration of the second unit block will be described with reference to FIG. 3 (b). The second unit block includes pixels 110, a signal processing circuit 210, and selection transistors 204a and 204b. The pixel 110 includes PD101a, 101b, transfer transistors 102a, 102b, FD103a, 103b, reset transistors 104a, 104b, and input capacitances 107a, 107b. Since the pixel 110 includes PD101a and 101b (second photoelectric conversion unit), it can be said that the pixel 110 includes a larger number of photoelectric conversion units than the pixel 100. Selection transistors 204a and 204b are arranged between the pixel 110 and the signal processing circuit 210.

The cathode of PD101a is connected to the source of transfer transistor 102a, and the anode of PD101a is grounded. The drain of the transfer transistor 102a is connected to the FD 103a. The source of the reset transistor 104a is connected to the FD 103a, and the drain of the reset transistor 104a is connected to the power supply voltage line having the power supply voltage VDD. The FD103a is connected to one terminal of the input capacitance 107a. The other terminal of the input capacitance 107a is connected to the drain of the selection transistor 204a. The source of the selection transistor 204a is connected to the signal processing circuit 210. A drive signal φTXA output from the peripheral circuit unit 12 is input to the gate of the transfer transistor 102a. A drive signal φRESA output from the peripheral circuit unit 12 is input to the gate of the reset transistor 104a. A drive signal φSELA output from the peripheral circuit unit 22 is input to the gate of the selection transistor 204a.

The cathode of PD101b is connected to the source of transfer transistor 102b, and the anode of PD101b is grounded. The drain of the transfer transistor 102b is connected to the FD 103b. The source of the reset transistor 104b is connected to the FD 103b, and the drain of the reset transistor 104b is connected to the power supply voltage line having the power supply voltage VDD. The FD 103b is connected to one terminal of the input capacitance 107b. The other terminal of the input capacitance 107b is connected to the drain of the selection transistor 204b. The source of the selection transistor 204b is connected to the signal processing circuit 210. A drive signal φTXB output from the peripheral circuit unit 12 is input to the gate of the transfer transistor 102b. A drive signal φRESB output from the peripheral circuit unit 12 is input to the gate of the reset transistor 104b. A drive signal φSELB output from the peripheral circuit unit 22 is input to the gate of the selection transistor 204b. As described above, the signal processing circuit 210 is provided corresponding to the PD 101a and 101b, and processes the signal (second signal) based on the electric charge generated by the PD 101a and 101b.

As described above, in the present embodiment, the number of PD101a and 101b corresponding to the signal processing circuit 210 is larger than the number of PD101s corresponding to the signal processing circuit 200. In the present embodiment, as an example, the number of PDs corresponding to the signal processing circuit 210 is set to 2, but the number is not limited to this, and may be 3 or more. Further, in this case, the number of PDs 101 corresponding to the signal processing circuit 200 is not limited to one, and may be a plurality as long as it is smaller than the number of PDs corresponding to the signal processing circuit 210. Further, in the present embodiment, as an example, the configuration has two FDs, FD103a and FD103b, but the present invention is not limited to this, and one FD may be shared by the two PDs.

Further, in the present embodiment, the strength of the second signal processed by the signal processing circuit 210 is smaller than the strength of the first signal processed by the signal processing circuit 200. An example of a configuration having such a signal strength relationship will be described with reference to FIGS. 4 (a) to 4 (e).

4 (a) to 4 (e) are layout diagrams showing arrangements of a photodiode and a microlens that can be applied to the solid-state image sensor 1 according to the present embodiment.

FIG. 4A shows the positional relationship between the PD 101 provided on the pixel 100 and the microlens 105 (condensing unit) in a top view. One microlens 105 is provided corresponding to one PD101 and is arranged above the PD101.

FIG. 4B shows the positional relationship between the PD 101a and 101b provided on the pixel 110 and the microlens 105 in a top view. One microlens 105 is provided corresponding to two PD101a and 101b formed side by side, and is arranged above the PD101a and 101b. Light that has passed through different pupils (exit pupils of the photographing lens 2) of the microlens 105 is incident on the PD101a and 101b. Therefore, the charge-based signals generated by the PD 101a and 101b can be used as a phase difference signal for focus detection. Here, as shown in FIG. 4B, the area of the light receiving portion provided on the PD101a and 101b is smaller than the area of the light receiving portion provided on the PD101. Therefore, the sensitivity of PD101a and 101b to the incident light is smaller than the sensitivity of PD101 to the incident light. Therefore, the strength of the signal based on the charge generated by PD101a and 101b is smaller than the strength of the signal based on the charge generated by PD101.

FIG. 4C is a top view of the pixel 110a according to a modification of the pixel 110 of FIG. 4B. In this modification, the microlenses 105a and 105b are provided corresponding to the PD101a and 101b provided in the pixel 110a, respectively. Also in this case, as in the example of FIG. 4B, the charge-based signals generated by PD101a and 101b can be used as the phase difference signal for focus detection. As shown in FIG. 4C, the area of the light receiving portion provided on the PD101a and 101b is smaller than the area of the light receiving portion provided on the PD101. Therefore, the sensitivity of PD101a and 101b to the incident light is smaller than the sensitivity of PD101 to the incident light. Therefore, the strength of the signal based on the charge generated by PD101a and 101b is smaller than the strength of the signal based on the charge generated by PD101. In the present embodiment, as an example, the PD in which the area of the light receiving portion is reduced is shown in FIG. 4C, but the present invention is not limited to this, and the normal PD shown in FIG. 4A is partially shielded from light. You may do so.

The pixel configuration applied to the solid-state image sensor 1 according to the present embodiment is not limited to that for obtaining a phase difference signal as in the examples of FIGS. 4 (b) and 4 (c) described above. For example, the solid-state image sensor 1 according to the present embodiment may include low-sensitivity pixels for the purpose of obtaining a low-sensitivity signal used for processing for expanding the dynamic range. In order to realize this, for example, PD101a and 101b may have a sensitivity smaller than that of PD101 by applying the modification described below.

FIG. 4D is a top view of the pixel 110b according to another modification of the pixel 110 of FIG. 4B. The pixel 110b of this modification has a light-shielding member 108 that blocks a part of the incident light on the PD 101a and 101b. The position where the light-shielding member 108 is arranged may be a position where a part of the incident light can be shielded, and is, for example, arranged above the PD101a and 101b and below the microlenses 105a and 105b. As shown in FIG. 4D, the light-shielding member 108 has a structure in which, for example, the vicinity of the central portion of each of PD101a and 101b is open and the vicinity of the end portion is shielded from light. The light-shielding member 108 is made of a material that does not transmit incident light or a material that does not easily transmit incident light. For example, a metal material such as aluminum can be adopted for the light-shielding member 108. With such a configuration, the area of the light receiving portion of the PD 101a and 101b that is not shaded by the light shielding member 108 is smaller than the area of the light receiving portion of the PD 101. Therefore, the strength of the signal based on the charge generated by PD101a and 101b is smaller than the strength of the signal based on the charge generated by PD101.

The configuration of FIGS. 4 (b) to 4 (d) described above can be rephrased as a configuration that limits the angular range of the incident light with respect to the PD 101a and 101b. The microlens 105 that collects the incident light on the PD 101 is used as the first light collecting unit, and the microlens 105 or the microlenses 105a and 105b that collect the incident light on the PD 101a and 101b are used as the second light collecting unit. At this time, the angle range of the incident light that can be incident on the light receiving portions of PD101a and 101b of the light incident on the second condensing unit is the light receiving portion of PD101 of the incident light on the first condensing unit. It is smaller than the angular range of incident light that can be incident on. As a result, the strength of the signal based on the charges generated by PD101a and 101b is made smaller than the strength of the signal based on the charges generated by PD101.

FIG. 4 (e) is a top view of the pixel 110c according to another modification of the pixel 110 of FIG. 4 (b). The pixel 110c of this modification has a dimming filter 109 (dimming portion) that reduces the intensity of the incident light on the PD 101a and 101b. The position where the dimming filter 109 is arranged may be a position through which the incident light passes, and is, for example, arranged above the PD101a and 101b and below the microlenses 105a and 105b. The dimming filter 109 is made of a material that transmits a part of the incident light by reflecting or absorbing a part of the incident light. With such a configuration, the amount of incident light on the PD101a and 101b is reduced, so that the intensity of the signal based on the charge generated by the PD101a and 101b can be made smaller than the intensity of the signal based on the charge generated by the PD101. it can.

Further, as another configuration example of the present embodiment, by further providing an amplification means such as an amplifier in the solid-state image sensor 1, the strength of the signal processed by the signal processing circuit 210 is changed to the signal processed by the signal processing circuit 200. It may be realized that the strength is smaller than the strength of. The amplification means is provided corresponding to each of the pixel 100 and the pixel 110. The first amplification means corresponding to the pixel 100 is provided between the PD 101 and the signal processing circuit 200. For example, the first amplification means may be provided in the pixel 100, or may be provided between the pixel 100 and the signal processing circuit 200. The second amplification means corresponding to the pixel 110 is provided between at least one of the PD 101a and 101b and the signal processing circuit 200. For example, the second amplification means may be provided in the pixel 110, or may be provided between the pixel 110 and the signal processing circuit 210. In these configurations, the intensity of the signal processed by the signal processing circuit 210 is processed by the signal processing circuit 200 by setting the amplification factor of the second amplification means to be smaller than the amplification factor of the first amplification means. It can be less than the strength of the signal.

Next, the reading operation of the solid-state image sensor 1 according to the present embodiment will be described with reference to FIG. FIG. 5 is a timing chart showing a driving method of the solid-state image sensor. FIG. 5 shows the drive timings of the drive signals φSEL, φRES, φTX, φSELA, φRESA, φTXA, φSELB, φRESB, and φTXB, and the AD conversion performed by the signal processing circuits 200 and 210. The timing chart shown in FIG. 5 is an operation for a predetermined line, and this operation is performed within a horizontal synchronization period defined by a horizontal synchronization signal (not shown). This operation is executed for each line, and by executing for all lines, a signal for one frame can be obtained. In the figure, "AD conversion (200)" indicates the content of AD conversion performed by the signal processing circuit 200, and "AD conversion (210)" indicates the content of AD conversion performed by the signal processing circuit 210. ing. When each drive signal is high level, each transistor is turned on, and when each drive signal is low level, each transistor is turned off.

In the initial state before the time t100, the drive signals φSEL, φTX, φSELA, φTXA, φSELB, and φTXB are at low level, and the selection transistors 204, 204a, 204b and the transfer transistors 102, 102a, 102b are in the off state. .. Further, the drive signals φRES, φRESA, and φRESB are at a high level, and the reset transistors 104, 104a, and 104b are in the ON state. As a result, the charges of the FDs 103, 103a, and 103b are reset.

At time t100, the drive signal φRES goes low and the reset transistor 104 turns off. As a result, the reset of the FD 103 is completed. Further, the drive signal φRESA becomes low level, and the reset transistor 104a is turned off. As a result, the reset of the FD103a is completed.

At time t101, the drive signal φSEL becomes high level and the selection transistor 204 turns on. As a result, the input capacitance 107 is connected to the signal processing circuit 200, and AD conversion in the signal processing circuit 200 is started. At this time, the voltage input to the signal processing circuit 200 is the voltage corresponding to the reset state of the FD 103. This AD conversion is called an N conversion. Further, the drive signal φSELA becomes high level, and the selection transistor 204a is turned on. As a result, the input capacitance 107a is connected to the signal processing circuit 210, and AD conversion in the signal processing circuit 210 is started. At this time, the voltage input to the signal processing circuit 210 is the voltage corresponding to the reset state of the FD103a. This AD conversion is called NA conversion.

At time t102, the drive signal φRESB goes low and the reset transistor 104b turns off. This completes the reset of the FD103b.

At time t103, the AD conversion in the signal processing circuits 200 and 210 ends. The digital signal obtained in the signal processing circuit 200 is stored as a reference signal N in a storage means (not shown). Further, the digital signal obtained in the signal processing circuit 210 is stored as a reference signal NA in a storage means (not shown). Further, the drive signal φSELA becomes low level, and the selection transistor 204a is turned off. As a result, the input capacitance 107a is not connected to the signal processing circuit 210. Further, the drive signal φSELB becomes high level and the selection transistor 204b is turned on. As a result, the input capacitance 107b is connected to the signal processing circuit 210, and AD conversion in the signal processing circuit 210 is started. At this time, the voltage input to the signal processing circuit 210 is the voltage corresponding to the reset state of the FD 103b. This AD conversion is called an NB conversion.

At time t104, the drive signal φTX becomes high level and the transfer transistor 102 turns on. As a result, the transfer of the electric charge accumulated in the PD 101 to the FD 103 is started, and the electric charge is started to be accumulated in the FD 103. Further, the drive signal φTXA becomes high level, and the transfer transistor 102a is turned on. As a result, the transfer of the electric charge accumulated in the PD101a to the FD103a is started, and the electric charge is started to be accumulated in the FD103a.

At time t105, the drive signal φTX goes low and the transfer transistor 102 turns off. As a result, the transfer of electric charge from PD101 to FD103 is completed. Further, the drive signal φTXA becomes low level, and the transfer transistor 102a is turned off. As a result, the transfer of electric charge from PD101a to FD103a is completed.

At time t106, the AD conversion in the signal processing circuit 210 is completed, and the digital signal obtained in the signal processing circuit 210 is stored as a reference signal NB in a storage means (not shown). Further, the drive signal φSELB becomes low level, and the selection transistor 204b is turned off. As a result, the input capacitance 107b is not connected to the signal processing circuit 210. In addition, AD conversion in the signal processing circuit 200 is started. At this time, the voltage input to the signal processing circuit 200 is a voltage corresponding to the electric charge transferred to the FD 103. This AD conversion is called S conversion. Further, the drive signal φSELA becomes high level and the selection transistor 204a is turned on. As a result, the input capacitance 107a is connected to the signal processing circuit 210, and AD conversion in the signal processing circuit 210 is started. At this time, the voltage input to the signal processing circuit 210 is the voltage corresponding to the electric charge transferred to the FD 103a. This AD conversion is called SA conversion.

At time t107, the drive signal φTXB becomes high level and the transfer transistor 102b is turned on. As a result, the transfer of the electric charge accumulated in the PD101b to the FD103b is started, and the electric charge is started to be accumulated in the FD103b.

At time t108, the drive signal φTXB goes low and the transfer transistor 102b turns off. As a result, the transfer of electric charge from PD101b to FD103b is completed.

At time t109, the AD conversion in the signal processing circuit 210 ends. The digital signal obtained in the signal processing circuit 210 is stored as an optical signal SA in a storage means (not shown). Further, the drive signal φSELA becomes low level, and the selection transistor 204a is turned off. As a result, the input capacitance 107a is not connected to the signal processing circuit 210. Further, the drive signal φSELB becomes high level and the selection transistor 204b is turned on. As a result, the input capacitance 107b is connected to the signal processing circuit 210, and AD conversion in the signal processing circuit 210 is started. At this time, the voltage input to the signal processing circuit 210 is the voltage corresponding to the electric charge transferred to the FD 103b. This AD conversion is called SB conversion.

At time t110, the drive signal φRESA becomes high level and the reset transistor 104a is turned on. As a result, the reset of the FD103a is started.

At time t111, the AD conversion in the signal processing circuits 200 and 210 is completed, and the digital signal obtained in the signal processing circuit 200 is stored as an optical signal S in a storage means (not shown). Further, the digital signal obtained in the signal processing circuit 210 is stored as an optical signal SB in a storage means (not shown). Further, the drive signal φSEL becomes low level, and the selection transistor 204 is turned off. As a result, the input capacitance 107 is not connected to the signal processing circuit 200. Further, the drive signal φSELB becomes low level and the selection transistor 204b is turned off. As a result, the input capacitance 107b is not connected to the signal processing circuit 210.

At time t112, the drive signals φRES and φRESB become high level, and the reset transistors 104 and 104b are turned on. As a result, the reset of FD103 and 103b is started.

By the above operation, one reading from the pixels 100 and 110 is completed, and the reference signals N, NA, NB, the optical signals S, SA, and SB are stored in a storage means (not shown). Noise at the time of reset can be removed by performing a process of subtracting reference signals N, NA, and NB from the optical signals S, SA, and SB, respectively, inside the solid-state image sensor 1 or in the image pickup device.

As described above, in the present embodiment, the strength of the signal processed by the signal processing circuit 210 is smaller than the strength of the signal processed by the signal processing circuit 200. Generally, in AD conversion, the larger the signal strength, the longer the processing time. Therefore, the SA conversion and the SB conversion in the signal processing circuit 210 can be performed in a shorter time than the S conversion in the signal processing circuit 200.

In the present embodiment, the drive signal related to the first unit block and the drive signal related to the first unit block are different from each other. Therefore, the first unit block and the first unit block can be driven at different operation timings from each other. Therefore, SA conversion and SB conversion can be performed in parallel with the S conversion period. More generally, during the period in which the signal processing circuit 200 performs the AD conversion process a predetermined number of times, the signal processing circuit 210 can perform the AD conversion process a predetermined number of times. In the present embodiment, as shown in FIG. 5, the length of the SA conversion and SB conversion period is about half of the S conversion period. Therefore, the signal processing is performed during the period when the signal processing circuit 200 performs the AD conversion once. The circuit 210 can perform AD conversion twice.

As described above, the solid-state image sensor 1 according to the present embodiment has a configuration in which a plurality of PD101a and 101b share one signal processing circuit 210. Further, since the strength of the signal processed by the signal processing circuit 210 is smaller than the strength of the signal processed by the signal processing circuit 200, the SA conversion and the SB conversion in the signal processing circuit 210 are performed by the S in the signal processing circuit 200. It can be done in a shorter time than the conversion. Therefore, it is possible to reduce the circuit scale of the signal processing circuit and speed up the processing at the same time.

(Other embodiments)
It should be noted that the above-described embodiments are merely examples of embodiment in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner by these. That is, the present invention can be implemented in various forms without departing from the technical idea or its main features.

The present invention supplies a program that realizes one or more functions of the above-described embodiment to a system or device via a network or storage medium, and one or more processors in the computer of the system or device reads and executes the program. It can also be realized by the processing to be performed. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

1 Solid-state image sensor 100, 110 pixels 101, 101a, 101b Photodiodes 102, 102a, 102b Transfer transistors 103, 103a, 103b Floating diffusion 104, 104a, 104b Reset transistors 107, 107a, 107b Input capacitances 204, 204a, 204b Selective transistors 200, 210 signal processing circuit

Claims (18)

With at least one first photoelectric conversion unit,
With a plurality of second photoelectric conversion units,
A first signal processing circuit provided corresponding to the at least one first photoelectric conversion unit and processing a first signal based on an electric charge generated by the first photoelectric conversion unit.
A second signal processing circuit provided corresponding to the plurality of the second photoelectric conversion units and processing a second signal based on the electric charge generated by the second photoelectric conversion unit.
A first amplification means provided between the first photoelectric conversion unit and the first signal processing circuit to amplify the first signal based on the electric charge generated by the first photoelectric conversion unit. ,
A second amplification means provided between the second photoelectric conversion unit and the second signal processing circuit to amplify the second signal based on the electric charge generated by the second photoelectric conversion unit. ,
With
The strength of the second signal is smaller than the strength of the first signal.
Said second number of photoelectric conversion units corresponding to the second signal processing circuit, rather multi than the first number of photoelectric conversion units corresponding to the first signal processing circuit,
A solid-state image sensor, characterized in that the amplification factor of the second amplification means is smaller than the amplification factor of the first amplification means . A first pixel including one first photoelectric conversion unit of the at no small, the provided corresponding to at least one of said first photoelectric conversion unit, generated by the first photoelectric conversion unit charge A first signal processing circuit that processes a first signal based on , and a first unit block that includes.
A second pixel including a second photoelectric conversion unit of the multiple, the plurality of the provided corresponding to the second photoelectric conversion unit, a second based on the electric charges generated by the second photoelectric conversion unit A second signal processing circuit that processes the signal of
Bei to give a,
A plurality of unit blocks including the plurality of the first unit blocks and the plurality of the second unit blocks are arranged in a two-dimensional manner .
The strength of the second signal is smaller than the strength of the first signal.
Solid said second number of photoelectric conversion units corresponding to the second signal processing circuit, you characterized in that more than said first number of photoelectric conversion units corresponding to the first signal processing circuit Body image sensor. The solid-state image sensor according to claim 2 , wherein the first unit block and the second unit block are driven by different drive signals. The solid-state image sensor according to claim 2 or 3 , wherein the first unit block and the second unit block are driven at different drive timings. The solid-state imaging according to any one of claims 1 to 4 , wherein the sensitivity of the second photoelectric conversion unit to the incident light is smaller than the sensitivity of the first photoelectric conversion unit to the incident light. element. A first condensing unit that collects incident light on the first photoelectric conversion unit,
A second condensing unit that condenses the incident light on the second photoelectric conversion unit,
With more
The angular range of the incident light that can be incident on the light receiving portion of the second photoelectric conversion unit among the incident light on the second condensing unit is the angle range of the incident light on the first condensing unit. The solid-state imaging device according to any one of claims 1 to 5 , characterized in that it is smaller than the angle range of incident light that can be incident on the light receiving portion of the first photoelectric conversion unit. Any one of claims 1 to 6 , wherein the area of the light receiving unit provided in the second photoelectric conversion unit is smaller than the area of the light receiving unit provided in the first photoelectric conversion unit. The solid-state image sensor according to the section. The second photoelectric conversion unit includes a light-shielding member that shields a part of the second photoelectric conversion unit from incident light.
Any of claims 1 to 7 , wherein the area of the light-receiving portion of the second photoelectric conversion unit that is not shaded by the light-shielding member is smaller than the area of the light-receiving portion of the first photoelectric conversion unit. The solid-state image sensor according to item 1. The solid according to any one of claims 1 to 8 , further comprising a dimming unit provided corresponding to the plurality of the second photoelectric conversion units and reducing the intensity of incident light. Image sensor. The solid-state image sensor according to any one of claims 1 to 9 , wherein the second signal processed by the second signal processing circuit is used for focus detection. The solid-state image sensor according to any one of claims 1 to 10 , wherein the second signal processed by the second signal processing circuit is used for expanding the dynamic range. The solid-state image sensor according to any one of claims 1 to 11 , wherein the first signal processing circuit and the second signal processing circuit each include an analog-to-digital conversion circuit. Time during which the second signal processing circuit to process said second signal, characterized in that shorter than the time the first signal processing circuit to process said first signal, claims 1 to 12 The solid-state image sensor according to any one of the above items. While the first signal processing circuit processes the first signal a predetermined number of times, the second signal processing circuit processes the second signal more times than the predetermined number of times. The solid-state imaging device according to any one of claims 1 to 13 , which is characterized. A first substrate provided with the at least one first photoelectric conversion unit and the plurality of second photoelectric conversion units.
One of claims 1 to 14 , further comprising a second substrate different from the first substrate provided with the first signal processing circuit and the second signal processing circuit. The solid-state image sensor according to. The solid-state image sensor according to any one of claims 1 to 15 .
An arithmetic unit that performs arithmetic on the signal output from the solid-state image sensor, and
An imaging device characterized by having. A first signal processing circuit provided corresponding to at least one first photoelectric conversion unit, a plurality of second photoelectric conversion units, and the at least one first photoelectric conversion unit, and the plurality of. A second signal processing circuit provided corresponding to the second photoelectric conversion unit, and the first photoelectric conversion unit provided between the first photoelectric conversion unit and the first signal processing circuit. A first amplification means for amplifying a first signal based on the charge generated in the unit is provided between the second photoelectric conversion unit and the second signal processing circuit, and the second photoelectric conversion is provided. A method for controlling a solid-state image sensor , comprising: a second amplification means for amplifying a second signal based on the charge generated in the unit .
A first processing step of processing the first signal based on the electric charges generated in the first photoelectric conversion unit,
And a second processing step of processing said second signal based on the electric charge produced in the second photoelectric conversion unit,
The strength of the second signal is smaller than the strength of the first signal.
The number of the second signal to be processed by said second processing step in a predetermined synchronization period, rather multi than the number of said first signals to be processed by the first processing step,
A method for controlling a solid-state image sensor, characterized in that the amplification factor of the second amplification means is smaller than the amplification factor of the first amplification means . A first unit block including a first pixel including at least one first photoelectric conversion unit and a first signal processing circuit provided corresponding to the at least one first photoelectric conversion unit. A second unit block including a second pixel including a plurality of second photoelectric conversion units, and a second signal processing circuit provided corresponding to the plurality of the second photoelectric conversion units. A method for controlling a solid-state image sensor in which a plurality of the first unit block and a plurality of unit blocks including the plurality of the second unit blocks are arranged in a two-dimensional manner.
A first processing step of processing a first signal based on the electric charge generated by the first photoelectric conversion unit, and
Including a second processing step of processing a second signal based on the charge generated by the second photoelectric conversion unit.
The strength of the second signal is smaller than the strength of the first signal.
The number of the second signals processed in the second processing step within a predetermined synchronization period is larger than the number of the first signals processed in the first processing step. A method for controlling a solid-state image sensor.

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