JP5899653B2 - Imaging device - Google Patents

Description

  The present invention relates to an imaging apparatus.

  In recent years, video cameras and digital cameras having an automatic focus adjustment function (AF function) have been widely used. For this type of digital camera, a CMOS type imaging device or a CCD type imaging device is used. For example, a CMOS-type imaging device has a pixel array in which a plurality of pixels are arranged in a two-dimensional matrix. Each pixel has a photoelectric conversion unit that converts an optical signal into an electrical signal. In addition, the digital camera may have a dedicated focus detection element for performing focus detection separately from the pixel array for imaging. An imaging apparatus in which imaging pixels and focus detection pixels are mixedly arranged has also been proposed (for example, Patent Document 1).

Japanese Patent No. 4027113

  In a CMOS type imaging apparatus, a rolling shutter system that performs a shutter operation for each selected row is often used. For this reason, in the configuration of Patent Document 1, it is difficult to make the exposure timings of a plurality of focus detection pixels the same. When the exposure timings of the focus detection pixels are different among the plurality of focus detection pixels, the focus detection accuracy may be lowered. Further, when the imaging pixels and the focus detection pixels are arranged in the same row, when the imaging pixels are exposed with an appropriate exposure time, the focus detection pixels are set to an appropriate exposure time. It is difficult to expose with. When the focus detection pixels cannot be exposed with an appropriate exposure time, the focus detection accuracy decreases.

  An object of the present invention is to provide an imaging apparatus capable of appropriately controlling the exposure timing of pixels for focus detection.

An example of the imaging apparatus has a pixel array in which a plurality of focus detection pixels and a plurality of imaging pixels are arranged. Each focus detection pixel has a first photoelectric conversion unit that photoelectrically converts incident light to generate charges, and stores charges transferred from the first photoelectric conversion unit that are controlled by a voltage applied to the electrodes. A first transfer unit that has an electrode and is controlled by a voltage applied to the electrode and transfers charge from the first photoelectric conversion unit to the memory unit; and a second transfer unit that transfers charge from the memory unit to the amplification unit And a light-shielding part that shields the memory part. Each imaging pixel has a second photoelectric conversion unit that photoelectrically converts incident light to generate charges. In addition, the first photoelectric conversion unit is smaller than the second photoelectric conversion unit, and the memory unit is disposed only in a region that is shielded by the light shielding unit of the focus detection pixel and does not have the first photoelectric conversion unit. . A common signal voltage is applied to the electrodes of the memory section and the first transfer section.
Another example of the imaging apparatus includes a pixel array in which a plurality of focus detection pixels and a plurality of imaging pixels are arranged, and a control unit that controls operations of the imaging pixels and the focus detection pixels. Each focus detection pixel includes a first photoelectric conversion unit that photoelectrically converts incident light to generate charges, a memory unit that accumulates charges transferred from the first photoelectric conversion unit, and a memory unit from the first photoelectric conversion unit A first transfer unit that transfers charges to the second transfer unit, a second transfer unit that transfers charges from the memory unit to the amplification unit, and a light-shielding unit that shields the memory unit. Each imaging pixel has a second photoelectric conversion unit that photoelectrically converts incident light to generate charges. In addition, the first photoelectric conversion unit is smaller than the second photoelectric conversion unit, and the memory unit is disposed only in a region that is shielded by the light shielding unit of the focus detection pixel and does not have the first photoelectric conversion unit. . Further, the control unit controls the operation of the focus detection pixels so that the exposure timings of the plurality of focus detection pixels arranged in different rows in the pixel array are the same.

  ADVANTAGE OF THE INVENTION According to this invention, the imaging device which can control appropriately the exposure timing of the pixel for focus detection can be provided.

It is a figure which shows the outline | summary of the imaging device in one Embodiment. It is a figure which shows the outline | summary of the pixel for an imaging shown in FIG. 1, and the pixel for a focus detection. FIG. 3 is a diagram showing a cross section taken along line A-A ′ of the imaging pixel shown in FIG. 2. FIG. 3 is a diagram showing a cross section taken along line B-B ′ of the focus detection pixel shown in FIG. 2. It is a figure which shows the outline | summary of the control part shown in FIG. It is a figure which shows an example of a structure of the pixel for imaging shown in FIG. It is a figure which shows an example of a structure of the pixel for focus detection shown in FIG. It is a figure which shows an example of operation | movement of the imaging pixel shown in FIG. FIG. 8 is a diagram illustrating an example of the operation of the focus detection pixel illustrated in FIG. 7. FIG. 8 is a diagram illustrating another example of the operation of the focus detection pixel illustrated in FIG. 7. It is a figure which shows an example of operation | movement of the pixel array shown in FIG. It is a figure which shows another example of operation | movement of the pixel array shown in FIG. It is a figure which shows an example of operation | movement of the pixel array by which the pixel for focus detection is arrange | positioned in the some line. It is a figure which shows an example of operation | movement of a pixel array when exposure of the pixel for a focus detection is implemented in multiple times in 1 frame. It is a figure which shows an example of operation | movement of a pixel array when exposure of the pixel for focus detection is implemented ranging over several frames. It is a figure which shows an example of operation | movement of a pixel array when correlated double sampling is implemented. It is a figure which shows another example of operation | movement of a pixel array when correlated double sampling is implemented. It is a figure which shows an example of the potential of each part of the pixel for imaging when resetting a floating diffusion. It is a figure which shows an example of the potential of each part of the pixel for focus detection when resetting a floating diffusion.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows an embodiment of the present invention. The shaded portion in FIG. 1 shows the memory unit MU in the focus detection pixel PXF described in FIG. The imaging device IMU of this embodiment is, for example, a CMOS type imaging device and is mounted on a digital camera. For example, the imaging device IMU includes a pixel array ARY and a control unit CNT.

  The pixel array ARY includes, for example, a plurality of imaging pixels PXI that generate an electrical signal (hereinafter also referred to as an image signal) corresponding to the amount of light incident through a micro lens and a color filter, and a plurality of focus detection pixels. And a pixel PXF. For example, the plurality of imaging pixels PXI have red (R), green (Gr, Gb), and blue (B) color filters, respectively, and are arranged in a Bayer array. Note that the arrangement of the imaging pixels PXI each having red (R), green (Gr, Gb), and blue (B) color filters is not limited to the Bayer arrangement.

  The focus detection pixel PXF is, for example, a pixel for generating a signal used for an automatic focus detection process by a known pupil division method, and a focus detection area FDA (in the horizontal direction in FIG. 1) ( (Region surrounded by a broken line in FIG. 1). The focus detection area FDA in which the focus detection pixels PXF are arranged may be provided so as to extend in the column direction (vertical direction in FIG. 1), or a plurality of focus detection areas FDA may be provided.

  For example, the control unit CNT controls the operations of the imaging pixels PXI and the focus detection pixels PXF of the pixel array ARY. Note that the control unit CNT may be provided separately from the imaging device IMU. That is, the imaging apparatus IMU may have a configuration in which the control unit CNT is omitted from the configuration in FIG.

  FIG. 2 shows an outline of the imaging pixel PXI and the focus detection pixel PXF shown in FIG. FIG. 2 shows the imaging pixels PXI and the focus detection pixels PXF viewed from the imaging surface side of the pixel array ARY (upper side in FIGS. 3 and 4 described later). Further, in FIG. 2, illustrations of wirings, color filters, and the like are omitted for easy viewing of the drawing. The shaded portion in FIG. 2 indicates the memory unit MU.

  The imaging pixel PXI includes a photodiode PDa as a photoelectric conversion unit and a circuit unit CIRU for reading out an image signal. For example, the photodiode PDa generates electric charge by photoelectrically converting light incident through the microlens MLN and the opening AP. For example, in a region such as the circuit unit CIRU other than the opening AP, light incident through the microlens MLN is shielded by the light shielding unit MS illustrated in FIG.

  The circuit unit CIRU includes, for example, a transfer transistor MTR, an amplification transistor MAM, a pixel selection transistor MSE, a reset transistor MRS, and a floating diffusion FD shown in FIGS. For example, in the imaging pixel PXI, the transfer transistor MTR of the circuit unit CIRU is disposed adjacent to the photodiode PDa. For example, in the focus detection pixel PXF, the transfer transistor MTR of the circuit unit CIRU is disposed adjacent to the memory unit MU. The arrangement of the circuit unit CIRU is not limited to this example.

  The focus detection pixel PXF includes a photodiode PDb as a photoelectric conversion unit, a memory unit MU that accumulates charges transferred from the photodiode PDb, and a circuit unit CIRU for reading out an image signal. For example, the photodiode PDb photoelectrically converts light incident through the microlens MLN and the opening AP to generate charges. For example, in a region such as the memory unit MU other than the opening AP, light incident through the microlens MLN is shielded by the light shielding unit MS shown in FIG.

  The focus detection pixel group PXFG includes, for example, a pair of focus detection pixels PXF arranged in the row direction (horizontal direction in FIG. 2), and generates a pair of images that are pupil-divided in the row direction. For example, the defocus amount is calculated by detecting the image shift amount of a pair of images generated from the focus detection pixel group PXFG (a pair of focus detection pixels PXF).

  Here, for example, in the left focus detection pixel PXF in the focus detection pixel group PXFG, the photodiode PDb and the memory unit MU are arranged in the left half and the right half of the microlens MLN, respectively. Further, for example, in the right focus detection pixel PXF in the focus detection pixel group PXFG, the photodiode PDb and the memory unit MU are arranged in the right half and the left half of the microlens MLN, respectively.

  FIG. 3 shows a cross section taken along the line A-A ′ of the imaging pixel PXI shown in FIG. 2. In FIG. 3, illustration of wiring and the like is omitted. For example, the photodiode PDa has an n-type semiconductor region NA1 formed on the light receiving surface side (upper side in FIG. 3) of the p-type semiconductor substrate SUB. Note that the conductivity type of the photodiode PDa is not limited to this example. The insulating part IS formed in the semiconductor substrate SUB is a region for insulating between adjacent photodiodes PDa, for example. Further, for example, in the gate layer GLY provided on the semiconductor substrate SUB, the gate electrode of the transistor of the circuit unit CIRU shown in FIG. 2 described above is formed.

  A wiring layer MLY having a plurality of layers is provided on the gate layer GLY. For example, the light shielding portion MS is formed of a metal film or the like in the lowest layer (layer on the semiconductor substrate SUB side) of the wiring layer MLY, and is disposed at a position corresponding to a region (insulating portion IS or the like) other than the photodiode PDa. That is, the opening AP is formed on the photodiode PDa. The light shielding portion MS may be formed other than the lowermost layer of the wiring layer MLY, or may be shared with the wiring. For example, the wiring may be formed in a layer different from the layer in which the light shielding unit MS is provided, or may be formed in the same layer as the layer in which the light shielding unit MS is provided.

  An optical filter OFL that functions as a color filter is disposed on the wiring layer MLY. In FIG. 3, optical filters OFL that function as green (Gb) and blue (B) color filters are alternately arranged. A flat layer PLY is formed on the optical filter OFL. The microlens MLN is disposed on the flat layer PLY. For example, in the imaging pixel PXI, the photodiode PDa receives light that has passed through the microlens MLN, the optical filter OFL (color filter), and the opening AP.

  FIG. 4 shows a cross section taken along line B-B ′ of the focus detection pixel PXF shown in FIG. 2. In FIG. 4, description of wiring and the like is omitted. For example, the photodiode PDb has an n-type semiconductor region NA1 formed on the light receiving surface side (upper side in FIG. 4) of the p-type semiconductor substrate SUB.

  The memory unit MU includes a storage unit MEM that stores charges transferred from the photodiode PDb, and a memory transfer unit MTX that transfers charges of the photodiode PDb to the storage unit MEM. For example, the memory transfer unit MTX includes an n-type semiconductor region NA2 formed on the p-type semiconductor substrate SUB and a part of the gate electrode GT formed on the gate layer GLY (a portion of the gate electrode GT on the region NA2). And have.

  For example, the memory transfer unit MTX includes a p-type semiconductor region PA1 formed between the regions NA1 and NA2, and a part of the gate electrode GT (a part of the gate electrode GT on the region PA1). That is, the memory transfer unit MTX is formed between the storage unit MEM and the photodiode PDb. The insulating part IS is formed between the adjacent areas NA1 and between the adjacent areas NA2. That is, the regions NA1, PA1, and NA2 are formed between the insulating portions IS.

  Here, for example, the impurity concentrations of the region NA1 of the photodiode PDb, the region PA1 of the memory transfer unit MTX, and the region NA2 of the storage unit MEM are different from each other. The impurity concentrations of the regions NA1, PA1, and NA2 are set so as to realize, for example, the potential relationship shown in FIGS. For example, the impurity concentrations of the regions NA1 and NA2 are respectively set so that the potential of the storage unit MEM when the voltage of the gate electrode GT is the ground voltage GND is located between the potential of the photodiode PDb and the potential of the floating diffusion FD. Is set. Note that the impurity concentration of the region PA1 may be different from the impurity concentration of the semiconductor substrate SUB, or may be the same as the impurity concentration of the semiconductor substrate SUB.

  A gate layer GLY is formed on the semiconductor substrate SUB. As described above, the gate electrode GT of the storage unit MEM and the memory transfer unit MTX is formed in the gate layer GLY. For example, the gate electrodes GT of the storage unit MEM and the memory transfer unit MTX are provided in common with each other. Note that the gate electrode GT of the storage unit MEM and the memory transfer unit MTX may be provided separately from each other. Further, for example, in the gate layer GLY, the gate electrode of the transistor of the circuit unit CIRU shown in FIG. 2 described above is formed separately from the gate electrode GT of the storage unit MEM and the memory transfer unit MTX.

  A wiring layer MLY having a plurality of layers is provided on the gate layer GLY. For example, the light shielding portion MS is formed of a metal film or the like in the lowermost layer (semiconductor substrate SUB side layer) of the wiring layer MLY and is located at a position corresponding to a region other than the photodiode PDb (memory portion MU, insulating portion IS, etc.). Be placed. That is, the opening AP is formed on the photodiode PDb. As described above, the focus detection pixel PXF includes the light shielding unit MS that shields the memory unit MU. The light shielding portion MS may be formed other than the lowermost layer of the wiring layer MLY, or may be shared with the wiring. For example, the wiring may be formed in a layer different from the layer in which the light shielding unit MS is provided, or may be formed in the same layer as the layer in which the light shielding unit MS is provided.

  On the wiring layer MLY, for example, an optical filter OFL (CLR) that transmits light from a blue wavelength to a red wavelength is disposed. A flat layer PLY is formed on the optical filter OFL. The microlens MLN is disposed on the flat layer PLY. For example, in the focus detection pixel PXF, the photodiode PDb receives light that has passed through the microlens MLN, the optical filter OFL (CLR), and the opening AP. In addition, the charge generated by the photodiode PDb is transferred to the storage unit MEM via the memory transfer unit MTX by controlling the gate electrode GT, for example. Therefore, in this embodiment, the charge generated by the photodiode PDb of the focus detection pixel PXF can be accumulated in the accumulation unit MEM.

  Note that the conductivity types of the semiconductors such as the photodiode PDb, the memory transfer unit MTX, and the storage unit MEM are not limited to this example.

  FIG. 5 shows an overview of the control unit CNT shown in FIG. FIG. 5 shows an outline of the control unit CNT that controls the operations of the imaging pixels PXI and the focus detection pixels PXF of the pixel array ARY of n rows and m columns. For example, the focus detection pixels PXF are arranged in the “m−1” column from the second column of the fourth row.

  The control unit CNT includes, for example, a vertical scanning circuit VSC and a timing generator TG. The vertical scanning circuit VSC controls the imaging pixels PXI of the pixel array ARY for each row using the control signals RST, TR, and SEL. For example, the vertical scanning circuit VSC controls the control signals RST (1), TR (1), and SEL (1), and controls the imaging pixels PXI in the first row. Further, for example, the vertical scanning circuit VSC controls the control signals RST (4), TR (4), and SEL (4), and controls the imaging pixels PXI in the first and mth columns of the fourth row.

  Further, the vertical scanning circuit VSC controls the focus detection pixels PXF of the pixel array ARY independently of the imaging pixels PXI using the control signals RST_f, TR_f, TX_f, and SEL_f. For example, the vertical scanning circuit VSC controls the control signals RST_f (4), TR_f (4), TX_f (4), and SEL_f (4), and controls the focus detection pixels PXF in the fourth row. Hereinafter, the control signals RST and RST_f are also referred to as reset signals RST. The control signals TR and TR_f are also referred to as transfer signals TR. The control signals SEL and SEL_f are also referred to as selection signals SEL. Further, the control signal TX_f is also referred to as a memory transfer signal TX_f.

  The timing generator TG supplies, for example, a drive clock to the vertical scanning circuit VSC, and controls the output timing of the control signals RST, TR, SEL, RST_f, TR_f, TX_f, and SEL_f of the vertical scanning circuit VSC. Note that the timing generator TG may be provided separately from the imaging device IMU. That is, the imaging apparatus IMU may have a configuration in which the timing generator TG is omitted from the configuration in FIG.

  Here, the pixel array ARY has a vertical signal line VL for outputting an output signal OUT of each pixel (imaging pixel PXI and focus detection pixel PXF). For example, a plurality of pixels (imaging pixels PXI and focus detection pixels PXF) arranged in the column direction (vertical direction in the figure) are connected to a vertical signal line VL provided for each column. Each vertical signal line VL is connected to a constant current source CS shown in FIGS. 6 and 7 to be described later in order to read out an output signal OUT from each pixel.

  FIG. 6 shows an example of the configuration of the imaging pixel PXI shown in FIG. The imaging pixel PXI includes a photodiode PDa and a circuit unit CIRU. The circuit unit CIRU includes, for example, a transfer transistor MTR, an amplification transistor MAM, a pixel selection transistor MSE, a reset transistor MRS, and a floating diffusion FD (floating diffusion region). For example, the transistors MTR, MAM, MSE, and MRS formed in the circuit unit CIRU are all nMOS transistors.

  The photodiode PDa has an anode grounded and a cathode connected to the source of the transfer transistor MTR. The transfer transistor MTR is turned on while the transfer signal TR applied to the gate is at a high level, and transfers the signal charge stored in the photodiode PDa to the floating diffusion FD.

  The floating diffusion FD is a region where parasitic capacitance for accumulating charges transferred from the photodiode PDa is formed (a drain region of the transistor MTR, a wiring region between the transistors MTR and MAM, a gate region of the transistor MAM, and a source of the reset transistor MRS). Area). Therefore, the signal charge transferred from the photodiode PDa is accumulated in the floating diffusion FD.

  The amplification transistor MAM has a source connected to the drain of the pixel selection transistor MSE, a drain connected to the power supply VDD, and a gate connected to the drain of the transfer transistor MTR. That is, the voltage corresponding to the signal charge transferred to the floating diffusion FD is input to the gate of the amplification transistor MAM. For example, the amplification transistor MAM outputs, from the source, a voltage obtained by dropping the gate voltage by the threshold voltage of the amplification transistor MAM. As described above, the amplification transistor MAM generates a signal corresponding to the signal charge transferred to the floating diffusion FD.

  The pixel selection transistor MSE is turned on when the selection signal SEL applied to the gate is at a high level, and conducts between the vertical signal line VL connected to the source and the source of the amplification transistor MAM. Therefore, during the period in which the pixel selection transistor MSE is on, the amplification transistor MAM, the pixel selection transistor MSE, and the constant current source CS connected to the vertical signal line VL constitute a source follower circuit. Thereby, the signal of the imaging pixel PXI selected by the pixel selection transistor MSE is output to the vertical signal line VL.

  The reset transistor MRS has a source connected to the gate of the amplification transistor MAM and a drain connected to the power supply VDD. For example, the reset transistor MRS is turned on while the reset signal RST applied to the gate is at a high level, and resets the charge of the floating diffusion FD.

  FIG. 7 shows an example of the configuration of the focus detection pixel PXF shown in FIG. The focus detection pixel PXF includes a photodiode PDb, a memory unit MU, and a circuit unit CIRU. The configuration of the circuit unit CIRU of the focus detection pixel PXF is the same as the configuration of the circuit unit CIRU of the imaging pixel PXI except for the connection destination of the source of the control signal and the transfer transistor MTR. Therefore, detailed description of the circuit unit CIRU is omitted. For example, the control signals RST_f, TR_f, and SEL_f correspond to the control signals RST, TR, and SEL shown in FIG.

  The photodiode PDb has an anode grounded and a cathode connected to the memory transfer unit MTX. The memory unit MU includes a memory transfer unit MTX and a storage unit MEM. For example, the memory transfer unit MTX is an nMOS transistor, the drain is connected to the storage unit MEM, the source is connected to the cathode of the photodiode PDb, and the gate receives the memory transfer signal TX_f. Hereinafter, the memory transfer unit MTX is also referred to as a memory transfer transistor MTX. For example, the memory transfer transistor MTX is turned on while the memory transfer signal TX_f is at a high level, and transfers the signal charge generated by the photodiode PDb to the storage unit MEM.

  The accumulation unit MEM is formed of, for example, a MOS structure, and accumulates charges in a potential well formed under the gate electrode. For example, the storage unit MEM has a potential well that can store a larger amount of charge than the amount of charge stored in the photodiode PDb. Note that the gate electrode (gate electrode on the potential well) of the storage unit MEM is controlled by, for example, the memory transfer signal TX_f.

  In this embodiment, since the gate electrode of the storage unit MEM and the gate of the memory transfer transistor MTX are controlled by the common memory transfer signal TX_f, the operation of the memory unit MU can be easily controlled. For example, in a configuration in which the gate electrode of the storage unit MEM and the gate of the memory transfer transistor MTX are separated from each other, the gate electrode of the storage unit MEM may be controlled by a control signal different from the gate of the memory transfer transistor MTX. .

  In the transfer transistor MTR, the drain is connected to the gate of the amplification transistor MAM, the source is connected to the storage unit MEM, and the gate receives the transfer signal TR_f. For example, the transfer transistor MTR is turned on while the transfer signal TR_f is at a high level, and transfers the signal charge generated by the photodiode PDb to the floating diffusion FD via the memory unit MU. Alternatively, for example, during a period when the transfer signal TR_f is at a high level, the transfer transistor MTR transfers the signal charge accumulated in the accumulation unit MEM to the floating diffusion FD.

  The amplification transistor MAM has a source connected to the drain of the pixel selection transistor MSE, a drain connected to the power supply VDD, and a gate connected to the drain of the transfer transistor MTR. The pixel selection transistor MSE is turned on when the selection signal SEL_f applied to the gate is at a high level, and conducts between the vertical signal line VL and the source of the amplification transistor MAM. As a result, the signal of the focus detection pixel PXF selected by the pixel selection transistor MSE is output to the vertical signal line VL.

  The reset transistor MRS has a source connected to the gate of the amplification transistor MAM and a drain connected to the power supply VDD. For example, the reset transistor MRS is turned on while the reset signal RST_f applied to the gate is at a high level, and resets the charge of the floating diffusion FD.

  FIG. 8 shows an example of the operation of the imaging pixel PXI shown in FIG. The symbol p in the figure indicates the potential (potential). Note that the broken line in the figure indicates the potential before the transistor state (on / off) is switched.

  In the reset period RESa, the transfer signal TR and the reset signal RST are maintained at a high level, and the transfer transistor MTR and the reset transistor MRS are maintained in an on (ON) state. As a result, the charges accumulated in the photodiode PDa and the floating diffusion FD are discharged to the power supply VDD.

  In the exposure period EXPa, the transfer signal TR and the reset signal RST are maintained at a low level, and the transfer transistor MTR and the reset transistor MRS are maintained in an off state. As a result, the photodiode PDa generates charges according to the incident light, and accumulates the generated charges.

  In the transfer period TRAa, the transfer signal TR and the reset signal RST are maintained at a high level and a low level, respectively. Therefore, in the transfer period TRAa, the transfer transistor MTR and the reset transistor MRS are maintained in the on state and the off state, respectively. Thereby, the electric charge accumulated in the photodiode PDa is transferred to the floating diffusion FD. Since the reset transistor MRS is in an off state, the charge transferred to the floating diffusion FD is not discharged to the power supply VDD.

  In the read period REAa, the transfer signal TR and the reset signal RST are maintained at a low level, and the transfer transistor MTR and the reset transistor MRS are maintained in an off state. Thereby, the charge transferred from the photodiode PDa to the floating diffusion FD is accumulated in the floating diffusion FD. Further, in the read period REAa, the selection signal SEL is maintained at a high level, and a voltage corresponding to the signal charge accumulated in the floating diffusion FD is output to the vertical signal line VL.

  FIG. 9 shows an example of the operation of the focus detection pixel PXF shown in FIG. FIG. 9 shows an example of the operation of the focus detection pixel PXF when no charge is accumulated in the accumulation unit MEM. The meaning of the broken line in the figure is the same as in FIG.

  In the reset period RESb, the memory transfer signal TX_f, the transfer signal TR, and the reset signal RST are maintained at a high level for a certain period (the left side diagram of the reset period RESb). Accordingly, the memory transfer transistor MTX, the transfer transistor MTR, and the reset transistor MRS are maintained in an on state for a certain period. Since the high-level memory transfer signal TX_f is applied to the gate electrode GT of the storage unit MEM, the potential of the storage unit MEM is maintained closer to the power supply VDD than the potential of the photodiode PDb. Thereby, the electric charge accumulated in the photodiode PDb moves to at least the accumulation unit MEM.

  After the memory transfer signal TX_f, the transfer signal TR, and the reset signal RST are maintained at a high level for a certain period, the memory transfer signal TX_f changes from a high level to a low level. Then, the memory transfer signal TX_f, the transfer signal TR, and the reset signal RST are maintained at a low level, a high level, and a high level, respectively (the diagram on the right side of the reset period RESb). Thereby, the memory transfer transistor MTX, the transfer transistor MTR, and the reset transistor MRS are maintained in the off state, the on state, and the on state, respectively.

  Since the low level memory transfer signal TX_f is applied to the gate electrode GT of the storage unit MEM, the potential of the storage unit MEM is maintained closer to the ground voltage GND than the potential of the floating diffusion FD. As a result, the charges accumulated in the accumulation unit MEM and the floating diffusion FD are discharged to the power supply VDD. As a result, in the reset period RESb, the charges accumulated in the photodiode PDb, the accumulation unit MEM, and the floating diffusion FD are discharged to the power supply VDD.

  In the exposure period EXPb, the memory transfer signal TX_f, the transfer signal TR, and the reset signal RST are maintained at a low level, and the memory transfer transistor MTX, the transfer transistor MTR, and the reset transistor MRS are maintained in an off state. Thereby, the photodiode PDb generates charges according to the incident light, and accumulates the generated charges.

  In the transfer period TRAb, the memory transfer signal TX_f, the transfer signal TR, and the reset signal RST are respectively maintained at a high level, a high level, and a low level for a certain period (the left side diagram of the transfer period TRAb). As a result, the memory transfer transistor MTX, the transfer transistor MTR, and the reset transistor MRS are maintained in an on state, an on state, and an off state, respectively, for a certain period. Since the high-level memory transfer signal TX_f is applied to the gate electrode GT of the storage unit MEM, the potential of the storage unit MEM is maintained closer to the power supply VDD than the potential of the photodiode PDb. Thereby, the electric charge accumulated in the photodiode PDb moves to the accumulation unit MEM.

  After the memory transfer signal TX_f, the transfer signal TR, and the reset signal RST are respectively maintained at a high level, a high level, and a low level for a certain period, the memory transfer signal TX_f changes from a high level to a low level. Then, the memory transfer signal TX_f, the transfer signal TR, and the reset signal RST are maintained at a low level, a high level, and a low level, respectively (the diagram on the right side of the transfer period TRAb). Thereby, the memory transfer transistor MTX, the transfer transistor MTR, and the reset transistor MRS are maintained in the off state, the on state, and the off state, respectively.

  Since the low level memory transfer signal TX_f is applied to the gate electrode GT of the storage unit MEM, the potential of the storage unit MEM is maintained closer to the ground voltage GND than the potential of the floating diffusion FD. Thereby, the charge transferred from the photodiode PDb to the storage unit MEM moves to the floating diffusion FD. As a result, in the transfer period TRAb, the charge accumulated in the photodiode PDb is transferred to the floating diffusion FD. Since the reset transistor MRS is in an off state, the charge transferred to the floating diffusion FD is not discharged to the power supply VDD.

  In the read period REAb, the memory transfer signal TX_f, the transfer signal TR, and the reset signal RST are maintained at a low level, and the memory transfer transistor MTX, the transfer transistor MTR, and the reset transistor MRS are maintained in an off state. Thereby, the charge transferred from the photodiode PDb to the floating diffusion FD is accumulated in the floating diffusion FD. Further, in the read period REAb, the selection signal SEL is maintained at a high level, and a voltage corresponding to the signal charge accumulated in the floating diffusion FD is output to the vertical signal line VL.

  FIG. 10 shows another example of the operation of the focus detection pixel PXF shown in FIG. FIG. 10 shows an example of the operation of the focus detection pixel PXF when charges are accumulated in the accumulation unit MEM. The meaning of the broken line in the figure is the same as in FIG. In the operation of the focus detection pixel PXF shown in FIG. 10, the operation of the memory transfer period METR is performed after the exposure period EXPb, and the operation of the transfer period TRAc is performed instead of the operation of the transfer period TRAb shown in FIG. Is done. Other operations are the same as the operations of the focus detection pixel PXF shown in FIG. Therefore, the memory transfer period METR and the transfer period TRAc will be described.

  In the memory transfer period METR, the memory transfer signal TX_f, the transfer signal TR, and the reset signal RST are maintained at a high level, a low level, and a low level for a certain period of time (the left diagram in the memory transfer period METR). As a result, the memory transfer transistor MTX, the transfer transistor MTR, and the reset transistor MRS are maintained for a certain period in an on state, an off state, and an off state, respectively.

  Since the high-level memory transfer signal TX_f is applied to the gate electrode GT of the storage unit MEM, the potential of the storage unit MEM is maintained closer to the power supply VDD than the potential of the photodiode PDb. Thereby, the electric charge accumulated in the photodiode PDb moves to the accumulation unit MEM. Note that, since the transfer transistor MTR is in the off state, the charge transferred to the storage unit MEM does not move to the floating diffusion FD.

  After the memory transfer signal TX_f, the transfer signal TR, and the reset signal RST are respectively maintained at a high level, a low level, and a low level for a certain period, the memory transfer signal TX_f changes from a high level to a low level. Then, the memory transfer signal TX_f, the transfer signal TR, and the reset signal RST are maintained at a low level (the diagram on the right side of the memory transfer period METR). Thereby, the memory transfer transistor MTX, the transfer transistor MTR, and the reset transistor MRS are maintained in the off state. As a result, charges are accumulated in the accumulation unit MEM. Thus, in the memory transfer period METR, charges generated by the photodiode PDb in the exposure period EXPb are accumulated in the accumulation unit MEM. Hereinafter, of the memory transfer period METR, a period during which the memory transfer signal TX_f, the transfer signal TR, and the reset signal RST are maintained at a low level (the right side of the memory transfer period METR) is also referred to as a charge holding period.

  In the transfer period TRAc, the memory transfer signal TX_f, the transfer signal TR, and the reset signal RST are maintained at a low level, a high level, and a low level, respectively. Therefore, in the transfer period TRAc, the memory transfer transistor MTX, the transfer transistor MTR, and the reset transistor MRS are maintained in the off state, the on state, and the off state, respectively. As a result, charges accumulated in the accumulation unit MEM (charges generated by the photodiode PDb during the exposure period EXPb) are transferred to the floating diffusion FD. Since the reset transistor MRS is in an off state, the charge transferred to the floating diffusion FD is not discharged to the power supply VDD.

  FIG. 11 shows an example of the operation of the pixel array ARY shown in FIG. FIG. 11 shows an example of the operation of the pixel array ARY when the exposure period EXPb of the focus detection pixel PXF is the same as the exposure period EXPa of the imaging pixel PXI. That is, FIG. 11 shows an example of the operation of the pixel array ARY when charges are not accumulated in the accumulation unit MEM. Stars in the figure indicate rows including focus detection pixels PXF. For example, the focus detection pixels PXF are arranged in the fourth row (L4). Therefore, in the fourth row (L4), the operation of the imaging pixel PXI is shown on the upper side, and the operation of the focus detection pixel PXF is shown on the lower side.

  The vertical scanning circuit VSC performs, for example, a series of operations (the operations illustrated in FIG. 8 described above) performed on the imaging pixel PXI in the order of the reset period RESa, the exposure period EXPa, the transfer period TRAa, and the readout period REAa. Sequentially for each row. For example, the vertical scanning circuit VSC first performs each operation on the imaging pixels PXI in the first row (L1) in the order of the reset period RESa, the exposure period EXPa, the transfer period TRAa, and the readout period REAa. Thereby, in the readout period REAa, the output signals OUT (OUT (1), OUT (2),..., OUT (m)) of the imaging pixels PXI in each column of the first row (L1) are output. .

  Then, for example, after the reset period RESa of the first row (L1) ends, the vertical scanning circuit VSC performs the reset period RESa, the exposure period EXPa, and the transfer period for the imaging pixel PXI of the second row (L2). Each operation is performed in the order of TRAa and readout period REAa. For example, the reset period RESa of the second row (L2) is started so that the transfer period TRAa of the second row (L2) is started after the reading period REAa of the first row (L1) ends. Here, for example, one frame FRM is from the start of the reset period RESa of the first row (L1) to the end of the read period REAa of the last row (Ln).

  Further, the vertical scanning circuit VSC performs, for example, a series of operations (the operations illustrated in FIG. 9 described above) performed in the order of the reset period RESb, the exposure period EXPb, the transfer period TRAb, and the readout period REAb, as shown in FIG. It carries out against. For example, the vertical scanning circuit VSC performs the operations of the reset period RESb, the exposure period EXPb, the transfer period TRAb, and the readout period REAb in accordance with the operations of the imaging pixels PXI in the fourth row (L4). This is performed for the focus detection pixel PXF of L4).

  As described above, in this embodiment, when the charge is not accumulated in the accumulation unit MEM of the focus detection pixel PXF, the operation of the focus detection pixel PXF can be performed in accordance with the operation of the imaging pixel PXI. The signal read operation can be simplified. As shown in FIG. 16, the vertical scanning circuit VSC sets the selection signal SEL to the high level before the transfer periods TRAa and TRAb (exposure periods EXPa and EXPb), and reads out the noise signal for correlated double sampling. Also good. Here, the noise signal is a signal indicating a fixed noise component including, for example, a reset noise component of the pixels PXI and PXF.

  Further, when the noise signal or the like is not read, the transfer period TRA (TRAa, TRAb) of each row may be started before the read period REA (REAa, REAb) of the previous row ends. For example, the vertical scanning circuit VSC may start the transfer period TRA so that the start of the read period REA for each row is approximately the same as the end of the read period REA for the previous row.

  FIG. 12 shows another example of the operation of the pixel array ARY shown in FIG. FIG. 12 shows an example of the operation of the pixel array ARY when the exposure period EXPb of the focus detection pixel PXF is shorter than the exposure period EXPa of the imaging pixel PXI. That is, FIG. 12 shows an example of the operation of the pixel array ARY when charges are accumulated in the accumulation unit MEM. The meaning of the star in the figure is the same as in FIG. The operation of the imaging pixel PXI is the same as that in FIG. Therefore, the operation of the focus detection pixel PXF will be described.

  The vertical scanning circuit VSC, for example, performs focus detection on a series of operations (the operations shown in FIG. 10 described above) performed in the order of the reset period RESb, the exposure period EXPb, the memory transfer period METR, the transfer period TRAc, and the read period REAb. This is performed for the pixel PXF. For example, the vertical scanning circuit VSC operates on the focus detection pixels PXF in the fourth row (L4) in the order of the reset period RESb, the exposure period EXPb, the memory transfer period METR, the transfer period TRAc, and the readout period REAb. carry out.

  For example, the vertical scanning circuit VSC is configured so that the transfer period TRAa of the imaging pixel PXI in the fourth row (L4) and the transfer period TRAc of the focus detection pixel PXF in the fourth row (L4) are at the same timing. The charge retention period of the memory transfer period METR is adjusted. Note that the operation of the reset period RESb of the focus detection pixel PXF may be performed in accordance with the reset period RESa of the imaging pixel PXI. Also at this time, the vertical scanning circuit VSC can adjust the charge holding period of the memory transfer period METR to match the transfer period TRAc of the focus detection pixel PXF with the transfer period TRAa of the imaging pixel PXI. As described above, the vertical scanning circuit VSC accumulates electric charges in the accumulating unit MEM, thereby reducing the exposure time (exposure period EXPb) of the focus detection pixel PXF and the exposure time (exposure period EXPa) of the imaging pixel PXI. Control independently. Thereby, in this embodiment, exposure of the focus detection pixel PXF can be performed at an arbitrary timing within one frame FRM for an arbitrary time.

  Therefore, in this embodiment, even when the exposure period EXPb of the focus detection pixel PXF is different from the exposure period EXPa of the imaging pixel PXI, the transfer period TRAc of the focus detection pixel PXF is set to the transfer period TRAa of the imaging pixel PXI. Can be matched. Accordingly, in this embodiment, even when the exposure period EXPb of the focus detection pixel PXF is different from the exposure period EXPa of the imaging pixel PXI, the readout period REAb of the focus detection pixel PXF is set as the readout period REAa of the imaging pixel PXI. Can be adapted to As a result, in this embodiment, the signal read operation from the pixel array ARY can be simplified.

  As shown in FIG. 17, the vertical scanning circuit VSC sets the selection signal SEL to a high level before the transfer periods TRAa and TRAc (exposure period EXPa and memory transfer period METR), and generates a noise signal for correlated double sampling. May be read out. In this embodiment, since the timing for transferring charges to the floating diffusion FD is the same between the imaging pixel PXI and the focus detection pixel PXF, a noise signal can be easily read out.

  Further, when the noise signal or the like is not read, the transfer period TRA (TRAa, TRAc) of each row may be started before the read period REA (REAa, REAb) of the previous row ends. For example, the vertical scanning circuit VSC may start the transfer period TRA so that the start of the read period REA for each row is approximately the same as the end of the read period REA for the previous row.

  FIG. 13 shows an example of the operation of the pixel array ARY in which the focus detection pixels PXF are arranged in a plurality of rows. FIG. 13 shows an example of the operation of the pixel array ARY in which the focus detection pixels PXF are arranged in the fourth row (L4) and the seventh row (L7). The meaning of the star in the figure is the same as in FIG. The operation of the imaging pixel PXI is the same as that in FIG. Therefore, the operation of the focus detection pixel PXF will be described. For example, the exposure period EXPb of the focus detection pixel PXF is shorter than the exposure period EXPa of the imaging pixel PXI.

  The vertical scanning circuit VSC performs, for example, a series of operations (the operations shown in FIG. 10 described above) performed in the order of the reset period RESb, the exposure period EXPb, the memory transfer period METR, the transfer period TRAc, and the readout period REAb in four rows. This is performed for the focus detection pixels PXF in the eye (L4) and the seventh row (L7).

  For example, the vertical scanning circuit VSC is configured so that the transfer period TRAa of the imaging pixel PXI in the fourth row (L4) and the transfer period TRAc of the focus detection pixel PXF in the fourth row (L4) are at the same timing. The charge holding period of the memory transfer period METR of the focus detection pixel PXF in the fourth row (L4) is adjusted. Further, the vertical scanning circuit VSC focuses the seventh row (L7) so that the exposure periods EXPb of the focus detection pixels PXF in the fourth row (L4) and the seventh row (L7) are at the same timing. The operation of the reset period RESb is started for the detection pixel PXF. In the vertical scanning circuit VSC, for example, the transfer period TRAa of the imaging pixel PXI in the seventh row (L7) and the transfer period TRAc of the focus detection pixel PXF in the seventh row (L7) have the same timing. In addition, the charge holding period of the memory transfer period METR of the focus detection pixel PXF in the seventh row (L7) is adjusted.

  As described above, the vertical scanning circuit VSC accumulates charges in the accumulation unit MEM, so that the focus detection pixels PXF arranged in different rows have the same exposure timing, so that the focus detection pixels in each row are the same. Control the operation of PXF. That is, even when the focus detection pixels PXF are arranged in a plurality of rows, the vertical scanning circuit VSC causes the plurality of focus detection pixels PXF to have the same exposure timing. To control the operation.

  Thereby, in this embodiment, exposure at the time of focus detection can be simultaneously performed by the focus detection pixels PXF arranged in different rows. As a result, in this embodiment, focus detection accuracy can be improved. Furthermore, in this embodiment, even when the focus detection pixels PXF are arranged in a plurality of rows, the readout period REAb of the focus detection pixels PXF can be easily matched with the readout period REAa of the imaging pixels PXI. The signal read operation from the pixel array ARY can be simplified.

  As shown in FIG. 17, the vertical scanning circuit VSC also precedes the transfer periods TRAa, TRAc (exposure period EXPa, memory transfer period METR), as shown in FIG. 17, even when the focus detection pixels PXF are arranged in a plurality of rows. The noise signal for correlated double sampling may be read by setting the selection signal SEL to a high level. In this embodiment, even when the focus detection pixels PXF are arranged in a plurality of rows, the transfer periods TRAc and TRAa of the focus detection pixels PXF and the imaging pixels PXI arranged in the same row are matched with each other. be able to. Therefore, in this embodiment, a noise signal can be easily read even when the focus detection pixels PXF are arranged in a plurality of rows.

  Further, when the noise signal or the like is not read, the transfer period TRA (TRAa, TRAc) of each row may be started before the read period REA (REAa, REAb) of the previous row ends. For example, the vertical scanning circuit VSC may start the transfer period TRA so that the start of the read period REA for each row is approximately the same as the end of the read period REA for the previous row.

  FIG. 14 shows an example of the operation of the pixel array ARY when exposure of the focus detection pixel PXF is performed a plurality of times during one frame FRM. The meaning of the star in the figure is the same as in FIG. The operation of the imaging pixel PXI is the same as that in FIG. Therefore, the operation of the focus detection pixel PXF will be described. For example, the exposure period EXPb of the focus detection pixel PXF is shorter than the exposure period EXPa of the imaging pixel PXI.

  For example, for the focus detection pixels PXF in the fourth row (L4), the vertical scanning circuit VSC includes a reset period RESb, an exposure period EXPb, a memory transfer period METR, a transfer period TRAc, a read period REAb, an exposure period EXPb, and a memory. The respective operations are performed in the order of the transfer period METR, the transfer period TRAc, and the read period REAb. Note that the number of exposures of the focus detection pixels PXF performed during one frame FRM is not limited to two. In this embodiment, since the focus detection pixel PXF can be independently exposed and read out independently, exposure of the focus detection pixel PXF can be performed a plurality of times within one frame FRM.

  For example, in the operation of FIG. 14, the signal of the focus detection pixel PXF (the signal used for focus detection) is output a plurality of times during one frame FRM. Therefore, in this embodiment, focus detection can be performed a plurality of times during one frame FRM, and high-speed focus detection can be realized. Note that the vertical scanning circuit VSC may perform the operation of the transfer period TRAb instead of performing the operations of the first memory transfer period METR and the transfer period TRAc. Further, the vertical scanning circuit VSC may sequentially perform the above-described operation illustrated in FIG. 9 and the above-described operation illustrated in FIG. 10 during one frame FRM. Alternatively, the vertical scanning circuit VSC may repeatedly perform the operations shown in FIGS. 9 and 10 a plurality of times during one frame FRM.

  Here, for example, when the storage unit MEM of the focus detection pixel PXF has a potential well that can sufficiently store a larger amount of charge than the amount of charge stored in the photodiode PDb of the focus detection pixel PXF, The operations of the first transfer period TRAc and the read period REAb may be omitted. For example, the vertical scanning circuit VSC applies the reset period RESb, the exposure period EXPb, the memory transfer period METR, the exposure period EXPb, the memory transfer period METR, the transfer period TRAc to the focus detection pixels PXF in the fourth row (L4). Each operation may be performed in the order of the read period REAb. In this case, the charge stored in the photodiode PDb can be transferred to the storage unit MEM before the charge stored in the photodiode PDb overflows. As a result, in this embodiment, the charge accumulated in the photodiode PDb can be prevented from overflowing, and focus detection accuracy can be improved. For example, in this embodiment, focus detection of a high-luminance subject and focus detection in a high-illuminance environment can be performed with high accuracy.

  Further, the vertical scanning circuit VSC is configured so that the transfer period TRAa of the imaging pixel PXI in the fourth row (L4) and the transfer period TRAc of the focus detection pixel PXF in the fourth row (L4) are at the same timing. The charge retention period of the second memory transfer period METR of the focus detection pixel PXF in the fourth row (L4) is adjusted. Thereby, in this embodiment, even when the exposure of the focus detection pixel PXF is performed a plurality of times during one frame FRM, the signal reading operation from the pixel array ARY can be simplified.

  Further, as shown in FIG. 17, the vertical scanning circuit VSC also performs the exposure before the transfer periods TRAa and TRAc (exposure period EXPa, memory) when the focus detection pixel PXF is exposed a plurality of times during one frame FRM. In the transfer period METR), the selection signal SEL may be set to a high level to read a noise signal for correlated double sampling. In this embodiment, even when the exposure of the focus detection pixel PXF is performed a plurality of times during one frame FRM, the transfer period TRAc of the focus detection pixel PXF can be matched with the transfer period TRAa of the imaging pixel PXI. . Therefore, in this embodiment, the noise signal can be easily read even when the exposure of the focus detection pixel PXF is performed a plurality of times during one frame FRM.

  When the noise signal or the like is not read, the transfer period TRA (TRAa, TRAc) of each row may be started before the read period REA (REAa, REAb) of the previous row ends. For example, the vertical scanning circuit VSC may start the transfer period TRA so that the start of the read period REA for each row is approximately the same as the end of the read period REA for the previous row.

  FIG. 15 shows an example of the operation of the pixel array ARY when exposure of the focus detection pixels PXF is performed across a plurality of frames FRM. The meaning of the star in the figure is the same as in FIG. The operation of the imaging pixel PXI is the same as that in FIG. Therefore, the operation of the focus detection pixel PXF will be described. For example, the exposure period EXPb of the focus detection pixel PXF is longer than the exposure period EXPa of the imaging pixel PXI.

  In the period of the frame FRM (1), for example, when the vertical scanning circuit VSC is performing the operation of the exposure period EXPa on the imaging pixels PXI in the fourth row (L4), the fourth row (L4). The operations are performed on the focus detection pixels PXF in the order of the reset period RESb and the exposure period EXPb. Note that the operation in the exposure period EXPb of the focus detection pixel PXF in the fourth row (L4) is continued halfway through the frame FRM (2).

  For example, after the operation of the last readout period REAa of the frame FRM (1) is performed on the imaging pixel PXI of the last row (Ln), the operation of the first reset period RESa of the frame FRM (2) is 1 This is performed for the imaging pixel PXI in the row (L1). That is, the vertical scanning circuit VSC, for example, after the read period REAa of the last row (Ln), for the imaging pixel PXI of the first row (L1), the reset period RESa, the exposure period EXPa, the transfer period TRAa, and the readout Each operation is performed in the order of the period REAa.

  In the period of the frame FRM (2), the vertical scanning circuit VSC performs, for example, the operation in the exposure period EXPa on the imaging pixels PXI in the fourth line (L4). The operation of the exposure period EXPb for the focus detection pixel PXF is terminated. That is, for example, when the vertical scanning circuit VSC controls the operation of the imaging pixel PXI in the fourth row (L4), the vertical scanning circuit VSC performs a memory transfer period for the focus detection pixel PXF in the fourth row (L4). Each operation is performed in the order of METR, transfer period TRAc, and read period REAb.

  In this embodiment, since the focus detection pixel PXF can be independently exposed and read out independently, the focus detection pixel PXF can be exposed at any time over a plurality of frames FRM. As described above, in this embodiment, by performing exposure of the focus detection pixel PXF across a plurality of frames FRM, long exposure is performed on the focus detection pixel PXF regardless of the exposure time of the imaging pixel PXI. Can be implemented. Thereby, in this embodiment, focus detection of a low-luminance subject and focus detection in a low-illuminance environment can be performed with high accuracy.

  Further, in the period of the frame FRM (2), the vertical scanning circuit VSC includes the transfer period TRAa of the imaging pixels PXI in the fourth row (L4) and the transfer period TRAc of the focus detection pixels PXF in the fourth row (L4). Are adjusted at the same timing, the charge holding period of the memory transfer period METR of the focus detection pixels PXF in the fourth row (L4) is adjusted. As a result, in this embodiment, even when exposure of the focus detection pixel PXF is performed across a plurality of frames FRM, it is possible to simplify the operation of reading a signal from the pixel array ARY. Note that the exposure of the focus detection pixel PXF may be performed over three frames FRM or more.

  In addition, when the exposure of the focus detection pixel PXF is performed across a plurality of frames FRM, the vertical scanning circuit VSC also performs the transfer periods TRAa and TRAc (exposure period EXPa, memory transfer) as shown in FIG. In the period METR), the selection signal SEL may be set to a high level to read out a noise signal for correlated double sampling. In this embodiment, even when the exposure of the focus detection pixel PXF is performed across a plurality of frames FRM, the transfer period TRAc of the focus detection pixel PXF can be matched with the transfer period TRAa of the imaging pixel PXI. Therefore, in this embodiment, a noise signal can be easily read even when the exposure of the focus detection pixel PXF is performed across a plurality of frames FRM.

  When the noise signal or the like is not read, the transfer period TRA (TRAa, TRAc) of each row may be started before the read period REA (REAa, REAb) of the previous row ends. For example, the vertical scanning circuit VSC may start the transfer period TRA so that the start of the read period REA for each row is approximately the same as the end of the read period REA for the previous row.

  FIG. 16 shows an example of the operation of the pixel array ARY when correlated double sampling is performed. The triangle in the figure indicates the operation of the imaging pixels PXI in the row (L4) including the focus detection pixels PXF. The star symbol indicates the operation of the focus detection pixels PXF in the row (L4) including the focus detection pixels PXF. The operation of FIG. 16 is different from the operation of FIG. 11 in that the floating diffusion FD is reset before the transfer period TRA (TRAa, TRAb).

  For example, in the fourth row (L4) imaging pixel PXI and the focus detection pixel PXF, when the readout period REAa of the third row (L3) imaging pixel PXI ends, the selection signals SEL (4), SEL_f ( 4) changes from a low level to a high level (FIGS. 16A and 16B). Then, the reset signals RST (4) and RST_f (4) are maintained at a high level for a certain period T10. As a result, the reset transistor MRS is turned on and the floating diffusion FD is reset. Since the selection signals SEL (4) and SEL_f (4) are maintained at a high level, a voltage (noise signal) corresponding to the potential of the reset floating diffusion FD is output to the vertical signal line VL.

  The noise signal output to the vertical signal line VL is read, for example, in the period T20. Note that the noise signal may be read out while the reset signals RST and RST_f are at a high level. After the noise signal is read, charges accumulated in the photodiode PD (PDa, PDb) are transferred to the floating diffusion FD in the transfer period TRA (TRAa, TRAb). Note that in the transfer period TRA, the reset transistor MRS is in an off state, so that the charge transferred to the floating diffusion FD is not discharged to the power supply VDD.

  For example, in the imaging pixel PXI, after the noise signal is read, the transfer signal TR (4) is maintained at a high level for a certain period. As a result, the transfer transistor MTR is turned on, and the charge accumulated in the photodiode PDa is transferred to the floating diffusion FD. Note that the photodiode PDa is also exposed when the transfer transistor MTR is on. That is, the photodiode PDa is exposed until the transfer signal TR falls (FIG. 16C). Therefore, in the imaging pixel PXI, the charge accumulated in the photodiode PDa before the transfer signal TR falls is transferred to the floating diffusion FD.

  For example, in the focus detection pixel PXF, after the noise signal is read, the transfer signal TR_f (4) and the memory transfer signal TX_f (4) change from the low level to the high level. Thereby, the transfer transistor MTR and the memory transfer transistor MTX are turned on, and the charge accumulated in the photodiode PDb moves to at least the accumulation unit MEM. Then, after a predetermined period after the memory transfer signal TX_f (4) changes from the high level to the low level, the transfer signal TR_f (4) changes from the high level to the low level. During the period when the transfer transistor MTR is on, the charge in the storage unit MEM is transferred to the floating diffusion FD.

  Note that the photodiode PDb is also exposed when the memory transfer transistor MTX is on. That is, the photodiode PDb is exposed until the memory transfer signal TX_f falls (FIG. 16D). Accordingly, in the focus detection pixel PXF, the charge accumulated in the photodiode PDb before the memory transfer signal TX_f falls is transferred to the floating diffusion FD.

  In the read period REA (REAa, REAb), since the selection signals SEL (4) and SEL_f (4) are maintained at a high level, a voltage corresponding to the charge transferred to the floating diffusion FD is output to the vertical signal line VL. Is done.

  FIG. 17 shows another example of the operation of the pixel array ARY when correlated double sampling is performed. The meanings of triangles and stars in the figure are the same as those in FIG. The operation of FIG. 17 is different from the operation of FIG. 12 in that the floating diffusion FD is reset before the transfer period TRA (TRAa, TRAc). The operation of the imaging pixel PXI is the same as that of the imaging pixel PXI shown in FIG. Therefore, the operation of the focus detection pixel PXF will be described.

  For example, in the focus detection pixel PXF in the fourth row (L4), the selection signal SEL_f (4) changes from the low level to the high level when the readout period REAa of the imaging pixel PXI in the third row (L3) ends. (FIG. 17B). The reset signal RST_f (4) is maintained at a high level for a certain period T10. As a result, the reset transistor MRS is turned on and the floating diffusion FD is reset. Since the selection signal SEL_f (4) is maintained at a high level, a voltage (noise signal) corresponding to the potential of the reset floating diffusion FD is output to the vertical signal line VL.

  The noise signal output to the vertical signal line VL is read, for example, in the period T20. After the noise signal is read, the transfer signal TR_f (4) is maintained at a high level for a certain period in the transfer period TRAc. As a result, the transfer transistor MTR is turned on, and the charge in the storage unit MEM is transferred to the floating diffusion FD. Note that charges are transferred from the photodiode PDb to the storage unit MEM during the memory transfer period METR.

  For example, the photodiode PDb is exposed even when the memory transfer transistor MTX is on. That is, the photodiode PDb is exposed until the memory transfer signal TX_f falls (FIG. 17D). Accordingly, in the focus detection pixel PXF, the charge accumulated in the photodiode PDb until the memory transfer signal TX_f falls is transferred to the floating diffusion FD via the accumulation unit MEM. Since the reset transistor MRS is in an off state, the charge transferred to the floating diffusion FD is not discharged to the power supply VDD.

  In the read period REAb, since the selection signal SEL_f (4) is maintained at a high level, a voltage corresponding to the charge transferred to the floating diffusion FD is output to the vertical signal line VL.

  Here, in the configuration in which the floating diffusion FD is reset (the configuration in which the operations in FIGS. 16 and 17 are performed), when the frames FRM are continuous by continuous shooting or the like, the operations in the reset periods RESa and RESb of the second and subsequent frames FRM are performed. May be omitted. For example, in the second and subsequent frames FRM, the photodiode PD and the storage unit MEM are reset by the operations of the transfer period TRA and the memory transfer period METR of the previous frame FRM. For this reason, in the second and subsequent frames FRM, each pixel is in the same state as when the operation in the reset period RES is performed by resetting the floating diffusion FD. The reset of the floating diffusion FD may be performed during the memory transfer period METR.

  FIG. 18 shows an example of the potential of each part of the imaging pixel PXI when the floating diffusion is reset. The meaning of the broken line in the figure is the same as in FIG.

  When the floating diffusion is reset (for example, the period T10 in FIGS. 16 and 17), the transfer signal TR and the reset signal RST are maintained at a low level and a high level, respectively. Accordingly, the transfer transistor MTR and the reset transistor MRS are maintained in the off state and the on state, respectively. As a result, the electric charge accumulated in the floating diffusion FD is discharged to the power supply VDD. Note that since the transfer transistor MTR is in the off state, the charge accumulated in the photodiode PDa is not discharged to the power supply VDD.

  FIG. 19 shows an example of the potential of each part of the focus detection pixel PXF when the floating diffusion is reset. The meaning of the broken line in the figure is the same as in FIG.

  When resetting the floating diffusion (for example, the period T10 in FIGS. 16 and 17), the memory transfer signal TX_f, the transfer signal TR, and the reset signal RST are maintained at a low level, a low level, and a high level, respectively. Thereby, the memory transfer transistor MTX, the transfer transistor MTR, and the reset transistor MRS are maintained in the off state, the off state, and the on state, respectively. As a result, the electric charge accumulated in the floating diffusion FD is discharged to the power supply VDD. Note that, since the transfer transistor MTR and the memory transfer transistor MTX are in the off state, the charges accumulated in the photodiode PDb and the accumulation unit MEM are not discharged to the power supply VDD.

  As described above, in this embodiment, the imaging device IMU includes the focus detection pixel PXF including the memory unit MU. For example, the memory unit MU includes a storage unit MEM that stores charges transferred from the photodiode PDb, and a memory transfer unit MTX that transfers charges of the photodiode PDb to the storage unit MEM. Thereby, in this embodiment, the exposure timing of the focus detection pixel PXF can be appropriately controlled, and the focus detection accuracy can be improved.

  In the above-described embodiment, the regions NA1 and NA2 are arranged so that the potential of the storage unit MEM when the voltage of the gate electrode GT is the ground voltage GND is located between the potential of the photodiode PDb and the potential of the floating diffusion FD. An example in which the impurity concentration of each is set has been described. The present invention is not limited to such an embodiment. For example, the potential of the storage unit MEM when the voltage of the gate electrode GT is the ground voltage GND may be higher than the potential of the photodiode PDb. That is, the potential of the storage unit MEM is maintained closer to the ground voltage GND than the potential of the floating diffusion FD when the voltage of the gate electrode GT is the ground voltage GND, and when the voltage of the gate electrode GT is the power supply VDD, the potential of the photodiode PDb is maintained. What is necessary is just to be maintained on the power supply VDD side from the potential. Also in this case, the same effect as the above-described embodiment can be obtained.

  In the above-described embodiment, the example in which the storage unit MEM includes the gate electrode GT has been described. The present invention is not limited to such an embodiment. For example, the storage unit MEM may be formed without including the gate electrode GT. In this case, the impurity concentrations of the regions NA1 and NA2 are set so that the potential of the storage unit MEM is located between the potential of the photodiode PDb and the potential of the floating diffusion FD. Also in this case, the same effect as the above-described embodiment can be obtained.

  In the above-described embodiment, the example in which the circuit unit CIRU is provided for each pixel (imaging pixel PXI, focus detection pixel PXF) has been described. The present invention is not limited to such an embodiment. For example, the circuit unit CIRU excluding the transfer transistor MTR may be shared by a plurality of pixels (imaging pixels PXI, focus detection pixels PXF) adjacent to each other in the column direction. That is, the floating diffusion FD may be shared by a plurality of pixels (imaging pixel PXI, focus detection pixel PXF). The transfer transistor MTR is provided for each pixel (imaging pixel PXI, focus detection pixel PXF). Also in this case, since the charge generated by the photodiode PDb of the focus detection pixel PXF can be accumulated in the accumulation unit MEM, the same effect as that of the above-described embodiment can be obtained.

  In the above-described embodiment, the example in which the control signals RST_f, TR_f, and SEL_f of the focus detection pixel PXF are controlled independently of the control signals RST, TR, and SEL of the imaging pixel PXI has been described. The present invention is not limited to such an embodiment. For example, the control signal SEL_f for the focus detection pixel PXF may also be used as the control signal SEL for the imaging pixel PXI. Also in this case, the same effect as the above-described embodiment can be obtained.

  In the above-described embodiment, the example in which the image signal of the imaging pixel PXI is read from the first row to the last row in order has been described. The present invention is not limited to such an embodiment. For example, the control unit CNT may read the image signal from the even-numbered imaging pixels PXI after reading the image signals from the odd-numbered imaging pixels PXI. Also in this case, the same effect as the above-described embodiment can be obtained.

  In the above-described embodiment, the example in which the signal of the focus detection pixel PXF is used for focus detection has been described. The present invention is not limited to such an embodiment. For example, the signal of the focus detection pixel PXF may be used for exposure detection. Also in this case, the same effect as the above-described embodiment can be obtained. Further, in this case, for example, since the exposure of the focus detection pixel PXF can be performed a plurality of times during one frame FRM, it is possible to detect a periodic change in exposure due to a blinking light source or the like. Furthermore, in this case, by performing the operations described with reference to FIGS. 12 to 15, high-speed exposure detection, exposure detection under a high illuminance environment, exposure detection under a low illuminance environment, and the like can be performed.

  In the embodiment described above, after the operation of the last readout period REAa of the frame FRM (1) is performed on the imaging pixel PXI of the last row (Ln), the first reset period RESa of the frame FRM (2) is performed. The example in which the operation is performed on the imaging pixel PXI in the first row (L1) has been described. The present invention is not limited to such an embodiment. For example, before the operation of the last readout period REAa of the frame FRM (1) is performed on the imaging pixel PXI of the last row (Ln), the operation of the first reset period RESa of the frame FRM (2) You may implement with respect to the imaging pixel PXI of the 1st line (L1). Also in this case, the same effect as the above-described embodiment can be obtained.

  In the above-described embodiment, the example in which the transfer period TRAa of the imaging pixel PXI and the transfer period TRAc of the focus detection pixel PXF are set to the same timing has been described. The present invention is not limited to such an embodiment. For example, the transfer period TRAc of the focus detection pixel PXF may be at a timing different from the transfer period TRAa of the imaging pixel PXI. Also in this case, the exposure timing of the focus detection pixel PXF can be appropriately controlled, and the focus detection accuracy can be improved.

  As mentioned above, although this invention was demonstrated in detail, said embodiment and its modification are only examples of this invention, and this invention is not limited to this. Obviously, modifications can be made without departing from the scope of the present invention.

  It can be used for an imaging device.

  AP, aperture, ARY, pixel array, CIRU, circuit unit, CNT, control unit, FDA, focus detection area, IMU, imaging device, MEM, storage unit, MLN, microlens, MS, shading unit, MTX, memory transfer Unit: MU, memory unit, PDa, PDb, photodiode, PXF, focus detection pixel, PXFG, focus detection pixel group, PXI, imaging pixel, TG, timing generator, VSC, vertical scanning circuit

Claims (8)

A first photoelectric conversion unit that photoelectrically converts incident light to generate charges, a memory unit that has electrodes and is controlled by a voltage applied to the electrodes and stores charges transferred from the first photoelectric conversion unit; A first transfer unit that has an electrode and is controlled by a voltage applied to the electrode and transfers charge from the first photoelectric conversion unit to the memory unit; and a second transfer unit that transfers charge from the memory unit to the amplification unit A plurality of focus detection pixels each having a transfer unit and a light shielding unit that shields the memory unit;
A plurality of imaging pixels having a second photoelectric conversion unit that photoelectrically converts incident light to generate charges;
A pixel array in which the focus detection pixels and the imaging pixels are arranged;
The first photoelectric conversion unit is smaller than the second photoelectric conversion unit,
The memory unit is disposed only in a region that is shielded from light by the light shielding unit of the focus detection pixel and does not include the first photoelectric conversion unit;
IMAGING DEVICE common signal voltage that is applied to the electrode and the electrode of the first transfer portion of the memory unit. The imaging device according to claim 1,
The light shielding unit shields the light receiving region of the focus detection pixel so that the first photoelectric conversion unit of the focus detection pixel is halved as compared to the second photoelectric conversion unit of the imaging pixel. . The imaging apparatus according to claim 1 or 2,
Wherein said memory unit and the first photoelectric conversion unit is the same conductivity type semiconductor region der Ru imaging device of. In the imaging device according to any one of claims 1 to 3,
Imaging device that has a control unit for controlling the operation of the image pickup pixels and the focus detection pixels. The imaging apparatus according to claim 4.
Wherein the control unit that controls the exposure time of the image pickup pixel and the exposure time of the focus detection pixels independently imaging device. The imaging apparatus according to claim 4.
Wherein the control unit is configured so that the exposure timings of a plurality of the focus detection pixels arranged in different rows in the pixel array is identical to each other, the focus detection control to that imaging device the operation of the pixel. A first photoelectric conversion unit that photoelectrically converts incident light to generate charges, a memory unit that accumulates charges transferred from the first photoelectric conversion unit, and transfers charges from the first photoelectric conversion unit to the memory unit A plurality of focus detection pixels having a first transfer unit, a second transfer unit that transfers charges from the memory unit to the amplification unit, and a light shielding unit that shields the memory unit;
A plurality of imaging pixels having a second photoelectric conversion unit that photoelectrically converts incident light to generate charges;
A pixel array in which the focus detection pixels and the imaging pixels are arranged;
A control unit that controls operations of the imaging pixels and the focus detection pixels;
The first photoelectric conversion unit is smaller than the second photoelectric conversion unit,
The memory unit is disposed only in a region that is shielded from light by the light shielding unit of the focus detection pixel and does not include the first photoelectric conversion unit;
Wherein the control unit is configured so that the exposure timings of a plurality of the focus detection pixels arranged in different rows in the pixel array is identical to each other, the focus detection control to that imaging device the operation of the pixel. In the imaging device according to any one of claims 1 to 7,
The second transfer unit, to that an imaging device transfers a charge to the floating diffusion of the amplifying portion.

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