JP6806455B2 - Reference voltage generation circuit, regulator, semiconductor device - Google Patents

Description

The present invention relates to a reference voltage generation circuit and a regulator, and a semiconductor device in which these are integrated.

In recent years, semiconductor devices (so-called voltage reference ICs) that generate an output voltage that is not easily affected by power supply fluctuations and temperature fluctuations from an input voltage have been used in various applications.

As an example of the prior art related to the above, Patent Document 1 can be mentioned.

Japanese Unexamined Patent Publication No. 2011-232931

However, there is room for further improvement in improving the accuracy of the voltage reference IC.

In view of the above problems found by the inventors of the present application, the invention disclosed in the present specification includes a reference voltage generation circuit and a regulator having high output accuracy, and a semiconductor device in which these are integrated. The purpose is to provide.

The reference voltage generation circuit disclosed in the present specification includes a first reference voltage source that generates a first reference voltage and a second reference voltage that generates a second reference voltage whose temperature characteristics are different from those of the first reference voltage. A voltage source, a first comparator that compares the first reference voltage with the second reference voltage to generate a first comparison signal, and the first reference voltage and the second reference according to the first comparison signal. It has a configuration (first configuration) having a selector for selectively outputting one of the voltages as a reference voltage.

Further, the reference voltage generation circuit disclosed in the present specification includes an amplifier, a first resistor connected between the output end of the amplifier and the first input end of the amplifier, and an output terminal of the amplifier. A second resistor connected between the amplifier and the second input end of the amplifier, a third resistor connected between the second input end of the amplifier and the grounded end, and the first input end of the amplifier. It has a first diode connected to the ground end and a plurality of parallel second diodes connected between the second input end of the amplifier and the ground end, and has the first resistance and the first resistor. One of the two resistors is a first resistance portion, a second resistance portion having a temperature characteristic different from that of the first resistance portion, and resistances of the first resistance portion and the second resistance portion according to a trimming signal. It has a configuration (second configuration) including a first trimming unit that adjusts the value so that the combined resistance value does not change.

Further, the reference voltage generation circuit disclosed in the present specification includes an amplifier, a first resistor connected between the output end of the amplifier and the first input end of the amplifier, and an output end of the amplifier. A second resistor connected between the amplifier and the second input end of the amplifier, a third resistor connected between the second input end of the amplifier and the ground end, and the first input end of the amplifier. It has a first diode connected to the ground end and a plurality of parallel second diodes connected between the second input end of the amplifier and the ground end, and has the first resistor and the first resistor. One of the two resistors has a configuration (third configuration) in which a poly resistance portion and a diffusion resistance portion are combined.

Further, the regulators disclosed in the present specification include an amplifier that outputs an amplified voltage so that the feedback voltage matches a reference voltage, a resistance ladder that divides the amplified voltage to generate the feedback voltage, and the above. A group of first switches that are connected to the output end of a constant voltage by selecting one from the nodes at both ends or intermediate nodes of the first resistance row included in the resistance ladder and the second resistance row included in the resistance ladder are parallel to each other. It has a configuration (fourth configuration) including a connected second switch group and a decoder that controls the first switch group and the second switch group according to a trimming signal.

Further, the semiconductor device disclosed in the present specification has a reference voltage generation circuit having any of the first to third configurations or a regulator having the fourth configuration (fifth configuration). ).

The other features, elements, steps, advantages, and properties of the present invention will be further clarified by the following detailed description and the accompanying drawings relating thereto.

According to the invention disclosed in the present specification, it is possible to provide a reference voltage generation circuit and a regulator having high output accuracy, and a semiconductor device in which these are integrated.

Block diagram showing an overall configuration example of the semiconductor device 1 Circuit diagram showing a configuration example of the pre-regulator 10 A circuit diagram showing a first configuration example of the reference voltage generation circuit 20 Temperature characteristic diagram of reference voltage Vref in the first configuration example Circuit diagram showing a second configuration example of the reference voltage generation circuit 20 Temperature characteristic diagram of reference voltage Vref in the second configuration example Circuit diagram showing a third configuration example of the reference voltage generation circuit 20 Longitudinal sectional view showing the element structure of the diffusion resistance portion R2b Temperature characteristic diagram of diffusion resistance part R2b Temperature characteristic diagram of reference voltage Vref in the third configuration example Circuit diagram showing a fourth configuration example of the reference voltage generation circuit 20 Circuit diagram showing a fifth configuration example of the reference voltage generation circuit 20 Circuit diagram showing the first configuration example of the regulator 30 Circuit diagram showing a second configuration example of the regulator 30 Circuit diagram showing a third configuration example of the regulator 30 Trimming operation diagram in the third configuration example

<Semiconductor device>
FIG. 1 is a block diagram showing an overall configuration example of the semiconductor device 1. The semiconductor device 1 of this configuration example is a voltage reference IC that generates output voltages Vout1 to Vout3 that are not easily affected by power supply fluctuations and temperature fluctuations from the input voltage Vin and outputs them to the outside of the device. The pre-regulator 10 and a reference voltage The generation circuit 20, the regulator 30, the buffer 40, and the non-volatile memory 50 are integrated. The output voltages Vout1 to Vout3 can be suitably used as a reference for a comparator or operational amplifier connected to the subsequent stage.

The pre-regulator 10 is connected between the application end of the input voltage Vin and the application end of the ground voltage Vss, and generates predetermined first internal power supply voltage Va and second internal power supply voltage Vb from the input voltage Vin. The first internal power supply voltage Va is used as the power supply voltage of the regulator 30 and the buffer 40, and is also output to the outside of the semiconductor device 1 as the first output voltage Vout1. On the other hand, the second internal power supply voltage Vb is used as the power supply voltage of the reference voltage generation circuit 20.

The reference voltage generation circuit 20 is connected between the application end of the second internal power supply voltage Vb and the application end of the ground voltage Vss, and receives the supply of the second internal power supply voltage Vb from the pre-regulator 10 to obtain a predetermined reference. Generate a voltage Vref. In particular, when the fluctuation range of the input voltage Vin is wide, the reference voltage Vref is not directly generated from the input voltage Vin, but the reference voltage Vref is generated from the second internal power supply voltage Vb in which the input voltage Vin is stabilized to some extent. Is desirable to generate. With such a configuration, a desired reference voltage Vref can be stably generated without depending on fluctuations in the input voltage Vin. However, the reference voltage generation circuit 20 is not necessarily limited to the configuration in which the reference voltage Vref is generated from the second internal power supply voltage Vb. That is, if the desired reference voltage Vref can be stably generated, the reference voltage Vref may be directly generated from the input voltage Vin. The reference voltage Vref is output to the regulator 30 as a reference for output feedback control.

The regulator 30 is connected between the application end of the first internal power supply voltage Va and the application end of the ground voltage Vss, and receives the supply of the first internal power supply voltage Va from the pre-regulator 10 to obtain a predetermined constant voltage Vreg. Generate. Specifically, the regulator 30 performs output feedback control so that the constant voltage Vreg (or the feedback voltage Vfb corresponding thereto) matches the reference voltage Vref. The constant voltage Vreg is output to the buffer 40 and is also output to the outside of the semiconductor device 1 as the second output voltage Vout2.

The buffer 40 is connected between the application end of the first internal power supply voltage Va and the application end of the ground voltage Vss, receives the input of the constant voltage Vreg from the regulator 30, and outputs the buffer voltage Vbuff. The buffer voltage Vbuff is output to the outside of the semiconductor device 1 as the third output voltage Vout3.

The non-volatile memory 50 operates by being supplied with an input voltage Vin, and is trimmed to adjust various control data (for example, the temperature characteristics of the reference voltage generation circuit 20 and the output gain of the regulator 30) used in the semiconductor device 1. Signal) is stored non-volatilely. As the non-volatile memory 50, for example, EEPROM [electrically erasable programmable read-only memory] or the like can be preferably used. Further, the nonvolatile memory 50, as an interface for performing data access from the outside of the semiconductor device 1, I ^{2 C} bus using clock signal SCL and the data signal SDA is connected.

Although not specified in this figure, the semiconductor device 1 provides an enable signal for controlling the operation availability of each of the above blocks (particularly, the pre-regulator 10, the reference voltage generation circuit 20, the regulator 30, and the buffer 40). It may be configured to accept.

<Pre-regulator>
FIG. 2 is a circuit diagram showing a configuration example of the pre-regulator 10. The pre-regulator 10 of this configuration example includes a bandgap reference voltage source 11, operational amplifiers 12 and 13, and resistors 14 to 17.

The bandgap reference voltage source 11 is connected between the application end of the input voltage Vin and the application end of the ground voltage Vss, and obtains a bandgap reference voltage Vbg that is not easily affected by power supply fluctuations and temperature fluctuations from the input voltage Vin. Generate.

The operational amplifier 12 is connected between the application end of the input voltage Vin and the application end of the ground voltage Vss, and has a band gap reference voltage Vbg input to the non-inverting input terminal (+) and an inverting input terminal (-). The output feedback control of the first internal power supply voltage Va is performed so that the voltage dividing voltage Va'(= the divided voltage of the first internal power supply voltage Va) input to is matched with.

The operational amplifier 13 is connected between the application end of the input voltage Vin and the application end of the ground voltage Vss, and has a band gap reference voltage Vbg input to the non-inverting input terminal (+) and an inverting input terminal (-). The output feedback control of the second internal power supply voltage Vb is performed so that the voltage divided voltage Vb'(= the divided voltage of the second internal power supply voltage Vb) input to is matched with.

The resistors 14 and 15 are connected between the output end of the operational amplifier 12 (= the application end of the first internal power supply voltage Va) and the application end of the ground voltage Vss, and the voltage dividing voltage Va'is transmitted from each other's connection nodes. It functions as a first voltage divider circuit to output.

The resistors 16 and 17 are connected between the output end of the operational amplifier 13 (= the application end of the second internal power supply voltage Vb) and the application end of the ground voltage Vss, and the voltage dividing voltage Vb'is applied from each other's connection nodes. It functions as a second voltage divider circuit to output.

<Reference voltage generation circuit (first configuration example)>
FIG. 3 is a circuit diagram showing a first configuration example of the reference voltage generation circuit 20. As the reference voltage generation circuit 20 of the first configuration example, the bandgap reference voltage source 21 can be preferably used. The bandgap reference voltage source 21 includes resistors R1 to R3 (all poly resistors), diodes D1 and D2, and an operational amplifier AMP.

The first power supply end of the operational amplifier AMP is connected to the application end of the second internal power supply voltage Vb. The second power supply end of the operational amplifier AMP is connected to the application end of the ground voltage Vss. Both the first end of the resistor R1 and the first end of the resistor R2 are connected to the output end of the operational amplifier AMP (= the output end of the reference voltage Vref). The second end of the resistor R1 and the anode of the diode D1 are both connected to the non-inverting input end (+) of the operational amplifier AMP. Both the second end of the resistor R2 and the first end of the resistor R3 are connected to the inverting input end (−) of the operational amplifier AMP. The second end of the resistor R3 is connected to the anode of the diode D2. Both the cathode of the diode D1 and the cathode of the diode D2 are connected to the application end of the ground voltage Vss. However, the resistor R3 may be connected to the cathode side of the diode D2 instead of the anode side of the diode D2.

The diode D2 corresponds to m (for example, m = 4) diodes D1 connected in parallel. That is, the PN junction area of the diode D2 is designed to be m times the PN junction area of the diode D1. Therefore, the current density of the diode D2 is smaller than the current density of the diode D1. As the diodes D1 and D2, transistors (= so-called diode connection transistors) in which the gate / drain or the base / collector is short-circuited may be used.

The above circuit configuration can also be applied to the bandgap reference voltage source 11 described above.

Next, the operation of the bandgap reference voltage source 21 will be described. The operational amplifier AMP has a reference voltage so that the first node voltage V1 input to the non-inverting input end (+) and the second node voltage V2 input to the inverting input terminal (-) match (imaginary short circuit). Negative feedback control of Vref is performed. As a result, the reference voltage Vref is expressed by the following equation (1).

R1 to R3 are resistance values of resistors R1 to R3 (for example, R1 = R2 = 250 kΩ), Vf1 is a forward voltage drop of diode D1, Is1 and Is2 are saturation currents of diodes D1 and D2, and Vt is heat. It shows the voltage.

In the above equation (1), the first term on the right side has a negative temperature coefficient, and the second term on the right side has a positive temperature coefficient. Therefore, the temperature characteristics of the reference voltage Vref can be ideally flattened by appropriately adjusting the resistance values of the resistors R1 to R3 and the current values of the saturation currents Is1 and Is2.

FIG. 4 is a temperature characteristic diagram of the reference voltage Vref in the first configuration example. The horizontal axis of this figure shows the temperature, and the vertical axis shows the reference voltage Vref. As shown in this figure, the temperature characteristic of the reference voltage Vref in the first configuration example is not necessarily flat in reality, but is convex (egg-shaped) having a maximum value with respect to a temperature change. With such temperature characteristics, a temperature drift of about 18 ppm / ° C. occurs in the reference voltage Vref, so there is room for further improvement.

<Reference voltage generation circuit (second configuration example)>
FIG. 5 is a circuit diagram showing a second configuration example of the reference voltage generation circuit 20. The reference voltage generation circuit 20 of the second configuration example includes a first bandgap reference voltage source 21A, a second bandgap reference voltage source 21B, a third bandgap reference voltage source 21C, a selector 22, and a first comparator 23x. , A second comparator 23y, and a logic calculation unit 24.

The first bandgap reference voltage source 21A is connected between the application end of the second internal power supply voltage Vb and the application end of the ground voltage Vss, and generates the first reference voltage VrefA.

The second bandgap reference voltage source 21B is connected between the application end of the second internal power supply voltage Vb and the application end of the ground voltage Vss, and has a second reference voltage having different temperature characteristics from the first reference voltage VrefA. Generate VrefB.

The third band gap reference voltage source 21C is connected between the application end of the second internal power supply voltage Vb and the application end of the ground voltage Vss, and the temperature of both the first reference voltage VrefA and the second reference voltage VrefB is high. A third reference voltage VrefC with different characteristics is generated.

The first bandgap reference voltage source 21A, the second bandgap reference voltage source 21B, and the third bandgap reference voltage source 21C each have the same configuration as the bandgap reference voltage 21 shown in FIG. However, the resistance ratio (R2 / R3) of the resistor R2 and the resistor R3 is different for each reference voltage source.

The selector 22 includes PMOSFETs [p-channel type metal oxide semiconductor field effect transistors] 22A to 22C, and has a first reference voltage VrefA and a second reference voltage according to switching signals SA to SC input from the logic calculation unit 24. One of VrefB and the third reference voltage VrefC is selectively output as the reference voltage Vref.

The PMOSFET 22A is connected between the output end of the first band gap reference voltage source 21A (= the output end of the first reference voltage VrefA) and the output end of the reference voltage generation circuit 20 (= the output end of the reference voltage Vref). It turns on when the switching signal SA is at a low level and turns off when the switching signal SA is at a high level.

The PMOSFET 22B is connected between the output end of the second band gap reference voltage source 21B (= the output end of the second reference voltage VrefB) and the output end of the reference voltage generation circuit 20 (= the output end of the reference voltage Vref). It turns on when the switching signal SB is at a low level and turns off when the switching signal SB is at a high level.

The PMOSFET 22C is connected between the output end of the third band gap reference voltage source 21C (= the output end of the third reference voltage VrefC) and the output end of the reference voltage generation circuit 20 (= the output end of the reference voltage Vref). It turns on when the switching signal SC is at a low level and turns off when the switching signal SC is at a high level.

That is, when the switching signal SA is at a low level and the switching signals SB and SC are at a high level, the first reference voltage VrefA is selectively output as the reference voltage Vref. When the switching signal SB is at a low level and the switching signals SA and SC are at a high level, the second reference voltage VrefB is selectively output as the reference voltage Vref. Further, when the switching signal SC is at a low level and the switching signals SA and SB are at a high level, the third reference voltage VrefC is selectively output as the reference voltage Vref.

The first comparator 23x generates a first comparison signal Sx by comparing the first reference voltage VrefA input to the non-inverting input end (+) with the second reference voltage VrefB input to the inverting input terminal (-). To do. The first reference voltage Sx becomes a high level when the first reference voltage VrefA is higher than the second reference voltage VrefB, and conversely becomes a low level when the first reference voltage VrefA is lower than the second reference voltage VrefB. ..

The second comparator 23y compares the second reference voltage VrefB input to the non-inverting input end (+) with the third reference voltage VrefC input to the inverting input terminal (-) to generate a second comparison signal Sy. To do. The second reference voltage Sy becomes a high level when the second reference voltage VrefB is higher than the third reference voltage VrefC, and conversely becomes a low level when the second reference voltage VrefB is lower than the third reference voltage VrefC. ..

The logical operation unit 24 is a circuit block that generates switching signals SA to SC from the first comparison signal Sx and the second comparison signal Sy, and includes a NAND gate 24a, a NAND gate 24b, and an OR gate 24c.

The NAND gate 24a generates a switching signal SA by performing a negative logical product operation of the first comparison signal Sx input to the first input terminal and the second comparison signal Sy input to the second input terminal. The switching signal SA becomes low level when both the first comparison signal Sx and the second comparison signal Sy are high level, and when at least one of the first comparison signal Sx and the second comparison signal Sy is low level. It becomes a high level.

The NAND gate 24b generates a switching signal SB by performing a negative logical product operation of the first comparison signal Sx input to the first inverting input end and the second comparison signal Sy input to the second input end. .. The switching signal SB becomes low level when the first comparison signal Sx is low level and the second comparison signal Sy is high level, and whether the first comparison signal Sx is high level or the second comparison signal Sy is low. When it is a level, it becomes a high level.

The OR gate 24c generates a switching signal SC by performing a logical sum operation of the first comparison signal Sx input to the first input end and the second comparison signal Sy input to the second input end. The switching signal SC becomes low level when both the first comparison signal Sx and the second comparison signal Sy are low level, and when at least one of the first comparison signal Sx and the second comparison signal Sy is high level. It becomes a high level.

FIG. 6 is a temperature characteristic diagram of the reference voltage Vref in the second configuration example, in order from the top, the reference voltage Vref (thick solid line), the first reference voltage VrefA (broken line), the second reference voltage VrefB (dashed line), and so on. The third reference voltage VrefC (dashed line), the first comparison signal Sx, the second comparison signal Sy, and the switching signals SA to SC are depicted. The horizontal axis in this figure indicates the temperature (-80 ° C to + 160 ° C).

In the example of this figure, the first bandgap reference voltage source 21A is designed to exhibit a temperature characteristic at which the first reference voltage VrefA reaches a maximum near −20 ° C. Further, the second bandgap reference voltage source 21B is designed so as to exhibit a temperature characteristic in which the second reference voltage VrefB is maximized in the vicinity of + 40 ° C. Further, the third bandgap reference voltage source 21C is designed so as to exhibit a temperature characteristic at which the third reference voltage VrefC becomes maximum in the vicinity of + 100 ° C. The peak temperature can be arbitrarily adjusted by changing the resistance ratio between the resistor R2 and the resistor R3.

In the temperature range where VrefA> VrefB> VrefC (approximately less than + 10 ° C.), both the first comparison signal Sx and the second comparison signal Sy become high levels, so that the switching signal SA becomes low level and the switching signals SB and SC Becomes a high level. As a result, the PMOSFET 22A is turned on and the PMOSFETs 22B and 22C are turned off, so that the first reference voltage VrefA is output as the reference voltage Vref.

On the other hand, in the temperature range where VrefB> VrefA and VrefC (approximately + 10 ° C. to + 70 ° C.), the first comparison signal Sx becomes low level and the second comparison signal Sy becomes high level, so that the switching signal SB becomes low level. , Switching signals SA and SC become high level. As a result, the PMOSFET 22B is turned on and the PMOSFETs 22A and 22C are turned off, so that the second reference voltage VrefB is output as the reference voltage Vref.

Further, in the temperature range where VrefC> VrefB> VrefA (approximately + 70 ° C. or higher), both the first comparison signal Sx and the second comparison signal Sy become low level, so that the switching signal SC becomes low level and the switching signal SA And SB becomes high level. As a result, the PMOSFET 22C is turned on and the PMOSFETs 22A and 22B are turned off, so that the third reference voltage VrefC is output as the reference voltage Vref.

As described above, in the reference voltage generation circuit 20 of the second configuration example, the region where the temperature characteristics are flat (first reference voltage VrefA, second reference voltage VrefB, and third reference) due to the extremely simple circuit configuration. Since it is possible to logically select and output (near the maximum value of each voltage VrefC), it is possible to reduce the temperature drift of the reference voltage Vref.

In the above, a configuration in which three bandgap reference voltage sources are selectively used is given as an example, but the number of bandgap reference voltage sources is not limited to this, and may be two. Or it may be 4 or more.

<Reference voltage generation circuit (third configuration example)>
FIG. 7 is a circuit diagram showing a third configuration example of the reference voltage generation circuit 20. The third configuration example is based on the first configuration example (FIG. 3), and is characterized in that the resistor R2 is formed by combining the poly resistance portion R2a and the diffusion resistance portion R2b. Therefore, the same components as those in the first configuration example are designated by the same reference numerals as those in FIG. 1 to omit duplicated explanations, and the feature portions of the third configuration example will be mainly described below.

As the polyresistor portion R2a, a polyresistor (polysilicon resistor) is used as in the case of the resistor R1 and the resistor R3. On the other hand, as the diffusion resistance portion R2b, a diffusion resistor having a different temperature characteristic from the poly resistance portion R2a is used.

However, the resistor R1 and the resistor R2 are both designed to have the same resistance value. That is, the poly resistance portion R2a and the diffusion resistance portion R2b are designed so that their combined resistance values match the resistance values of the resistance R1 (for example, R2a + R2b = R1 = 250 kΩ).

FIG. 8 is a vertical cross-sectional view showing the element structure of the diffusion resistance portion R2b. As shown in this figure, the diffusion resistance portion R2b is formed in a pair of first low-concentration n-type diffusion regions 102 and a pair of first low-concentration n-type diffusion regions 102 formed on the p-type semiconductor substrate 101, respectively. A pair of high-concentration n-type diffusion regions 103 (contact regions) and a second low-concentration n-type diffusion region 104 formed on the semiconductor substrate 101 sandwiched between a pair of first low-concentration n-type diffusion regions 102. Includes a pair of VDD electrodes 105, each formed on a pair of high-concentration n-type diffusion regions 103.

A pair of wirings 106 are connected to the pair of VDD electrodes 105, respectively. Further, the pair of the first low-concentration n-type diffusion region 102, the pair of high-concentration n-type diffusion regions 103, and the second low-concentration n-type diffusion region 104 are all covered with the insulating layer 107. Further, the diffusion resistance portion R2b is electrically separated from other adjacent elements by the element separation region 108 formed around the diffusion resistance portion R2b.

Further, the diffusion resistance portion R2b can be formed by diverting a floating gate type cell transistor forming the non-volatile memory 50. That is, as shown in this figure, a floating gate region 109 is formed on the second low-concentration n-type diffusion region 104 with the insulating layer 107 interposed therebetween.

In the diffusion resistance portion R2b having the above element structure, the second low concentration diffusion region 104 (that is, the tunnel region of the cell transistor) is used as a resistance component. Here, the impurity concentration of the second low-concentration n-type diffusion region 104 is adjusted so that the resistance value of the diffusion resistance portion R2b has a minimum value with respect to a temperature change.

FIG. 9 is a temperature characteristic diagram of the diffusion resistance portion R2b. The horizontal axis of this figure shows the temperature, and the vertical axis shows the resistance value of the diffusion resistance portion R2b. As shown in this figure, the resistance value of the diffusion resistance portion R2b is a concave type (bowl type) having a minimum value with respect to a temperature change by appropriately adjusting the impurity concentration of the second low concentration n-type diffusion region 104. It becomes.

FIG. 10 is a temperature characteristic diagram of the reference voltage Vref in the third configuration example. The horizontal axis of this figure shows the temperature, and the vertical axis shows the reference voltage Vref. The temperature characteristic of FIG. 4 can be canceled by adding the diffusion resistance portion R2b having the temperature characteristic of FIG. 9 as a part of the resistor R2 forming the bandgap reference voltage source 21.

Therefore, as shown in this figure, the temperature characteristics of the reference voltage Vref can be made extremely flat, and the temperature drift of the reference voltage Vref can be reduced to 1 ppm / ° C. or less (for example, 0.2 ppm / ° C.). ) Can be suppressed.

In the above, the configuration in which the diffusion resistance portion R2b is added as a part of the resistor R2 is illustrated, but the configuration in which the diffusion resistance portion is added as a part of the resistor R1 by exchanging the relationship between the resistor R1 and the resistor R2 is also described above. It is possible to obtain the same effect as.

<Reference voltage generation circuit (4th configuration example)>
FIG. 11 is a circuit diagram showing a fourth configuration example of the reference voltage generation circuit 20. The fourth configuration example is based on the third configuration example (FIG. 7), and a trimming function (= a function of adjusting the mixing ratio of the poly resistance portion R2a and the diffusion resistance portion R2b) is added to the second resistor R2. It is characterized by the above points. Therefore, the same components as those in the third configuration example are designated by the same reference numerals as those in FIG. 7, and duplicated explanations are omitted. Hereinafter, the characteristic portions of the fourth configuration example will be focused on.

In the reference voltage generation circuit 20 of the fourth configuration example, the second resistor R2 includes a poly-resistor portion R2a, a diffusion resistance portion R2b, and a trimming portion TRIM1. The trimming signals S1 and S2 input to the trimming unit TRIM1 are read from the non-volatile memory 50.

The diffusion resistance portion R2b includes a diffusion resistance r1 having a resistance value of AkΩ and a diffusion resistance r2 having a resistance value of BkΩ (≠ AkΩ). On the other hand, the poly resistance portion R2a includes a poly resistance r3 having a resistance value of AkΩ, a poly resistance r4 having a resistance value of BkΩ, and a poly resistance r5 having a resistance value of CkΩ. The diffusion resistors r1 and r2 and the poly resistors r3 to r5 are connected in series between the output end and the inverting input end (−) of the operational amplifier AMP in the order shown in the drawing.

The trimming unit TRIM1 is a circuit unit that adjusts the resistance values of the poly resistance unit R2a and the diffusion resistance unit R2b in accordance with the trimming signals S1 and S2 with the combined resistance value unchanged, and is an NMOSFET [N-channel type MOSFET] N1 to N4. And the inverters INV1 and INV2.

The NMOSFET N1 is connected in parallel to the diffusion resistor r1 and is turned on / off according to the trimming signal S1 input to the gate. More specifically, the NMOSFET N1 is turned on when the trimming signal S1 is at a high level and turned off when the trimming signal S1 is at a low level.

The NMOSFET N2 is connected in parallel to the diffusion resistor r2 and is turned on / off according to the trimming signal S2 input to the gate. More specifically, the NMOSFET N2 is turned on when the trimming signal S2 is at a high level and turned off when the trimming signal S2 is at a low level.

The NMOSFET N3 is connected in parallel to the poly resistor r3 and is turned on / off according to the inverting trimming signal S1B input to the gate via the inverter INV1. More specifically, the NMOSFET N3 is turned on when the inverting trimming signal S1B is at a high level and turned off when the inverting trimming signal S1B is at a low level.

The NMOSFET N4 is connected in parallel to the poly resistor r4, and is turned on / off according to the inverting trimming signal S2B input to the gate via the inverter INV2. More specifically, the NMOSFET N4 is turned on when the inverting trimming signal S2B is at a high level and turned off when the inverting trimming signal S2B is at a low level.

First, consider a first state in which the trimming signal S1 is at a low level and the trimming signal S2 is at a high level. In this case, NMOSFETs N1 and N4 are turned off and NMOSFETs N2 and N3 are turned on. Therefore, since the diffusion resistor r2 and the poly resistor r3 are short-circuited, the resistor R2 is in a state where the diffusion resistor r1 and the poly resistors r4 and r5 are connected in series.

Next, consider a second state in which the trimming signal S1 is at a high level and the trimming signal S2 is at a low level. In this case, NMOSFETs N1 and N4 are turned on and NMOSFETs N2 and N3 are turned off. Therefore, since the diffusion resistor r2 and the poly resistor r4 are short-circuited, the resistor R2 is in a state where the diffusion resistor r2 and the poly resistors r3 and r5 are connected in series.

In both the first state and the second state described above, the combined resistance value of the resistor R2 is (A + B + C) kΩ, and this invariant value is designed to match the resistance value of the resistor R1 (for example, R2 =). R1 = 250kΩ).

By adding such a trimming function, the blending ratio of the poly resistance portion R2a and the diffusion resistance portion R2b can be adjusted, so that even if the production variation of the diffusion resistance portion R2b occurs, the influence thereof can be affected. It can be made smaller. Therefore, the temperature characteristic of the reference voltage Vref can be made extremely flat regardless of the manufacturing variation of the diffusion resistance portion R2b.

The polyresistor r5 to which the NMOSFET is not connected in parallel is incorporated in the resistor R2 in both the first state and the second state. Therefore, by adjusting the resistance value (CkΩ) of the polyresistor r5, the blending ratio of the reference diffusion resistance portion R2b can be determined.

Further, in the above description, it has been described that the trimming signals S1 and S2 are mutually exclusive logic signals (a binary signal in which one is at a high level and the other is at a low level), but the resistor R2 has a diffusion resistance. If you want to check the behavior when both r1 and r2 are incorporated, or when the resistor R2 is composed of only poly resistors r3 to r5, the trimming signals S1 and S2 are set to the same logic level (high level or low). Level) is also possible.

On the other hand, if the above behavior confirmation is unnecessary, the trimming signals S1 and S2 may be combined into a single trimming signal S0. In that case, for example, the trimming signal S0 may be input to the gates of NMOSFETs N1 and N4, and the inverting trimming signal S0B (= logical inverting signal of the trimming signal S0) may be input to the gates of NMOSFETs N2 and N3.

<Reference voltage generation circuit (fifth configuration example)>
FIG. 12 is a circuit diagram showing a fifth configuration example of the reference voltage generation circuit 20. The fifth configuration example is characterized in that a formal trimming function is added to the first resistor R1 while being based on the fourth configuration example (FIG. 11). Therefore, with respect to the same components as those in the fourth configuration example, the same reference numerals as those in FIG. 11 are used to omit duplicated explanations, and the feature portions of the fifth configuration example will be mainly described below.

In the reference voltage generation circuit 20 of the fifth configuration example, the first resistor R1 includes polyresistors R1a and R1b and a trimming section TRIM2.

The poly resistance portion R1b includes a poly resistance r6 having a resistance value of AkΩ and a poly resistance r7 having a resistance value of BkΩ. Further, the polyresistor portion R1a includes a polyresistor r8 having a resistance value of AkΩ, a polyresistor r9 having a resistance value of BkΩ, and a polyresistor r10 having a resistance value of CkΩ. The poly resistors r6 to r10 are connected in series between the output end of the operational amplifier AMP and the non-inverting input end (+) in the order shown in the drawing.

Here, in order to clarify the association between the poly-resistor portion R2a and the diffusion resistance portion R2b in the resistor R2, the components of the resistor R1 are divided into two, the poly-resistor portions R1a and R1b. However, the plurality of element resistors forming the poly resistance portions R1a and R1b, respectively, are the poly resistors r6 to r10. Therefore, it is also possible to understand the poly resistance portions R1a and R1b as one poly resistance portion.

The trimming unit TRIM2 is a circuit unit that adjusts the resistance values of the poly resistance units R1a and R1b in accordance with the trimming signals S1 and S2 so that the combined resistance value does not change, and includes NMOSFETs N5 to N8 and inverters INV3 and INV4.

The NMOSFET N5 is connected in parallel to the poly resistor r6 and is turned on / off according to the trimming signal S1 input to the gate. More specifically, the NMOSFET N5 is turned on when the trimming signal S1 is at a high level and turned off when the trimming signal S1 is at a low level.

The NMOSFET N6 is connected in parallel to the poly resistor r7 and is turned on / off according to the trimming signal S2 input to the gate. More specifically, the NMOSFET N6 is turned on when the trimming signal S2 is at a high level and turned off when the trimming signal S2 is at a low level.

The NMOSFET N7 is connected in parallel to the poly resistor r8, and is turned on / off according to the inverting trimming signal S1B input to the gate via the inverter INV3. More specifically, the NMOSFET N7 turns on when the inverting trimming signal S1B is at a high level and turns off when the inverting trimming signal S1B is at a low level.

The NMOSFET N8 is connected in parallel to the poly resistor r9, and is turned on / off according to the inverting trimming signal S2B input to the gate via the inverter INV4. More specifically, the NMOSFET N8 is turned on when the inverting trimming signal S2B is at a high level and turned off when the inverting trimming signal S2B is at a low level.

First, consider a first state in which the trimming signal S1 is at a low level and the trimming signal S2 is at a high level. In this case, NMOSFETs N5 and N8 turn off and NMOSFETs N6 and N7 turn on. Therefore, since the poly resistors r7 and r8 are short-circuited, the resistor R1 is in a state where the poly resistor r6 and the poly resistors r9 and r10 are connected in series.

Next, consider a second state in which the trimming signal S1 is at a high level and the trimming signal S2 is at a low level. In this case, NMOSFETs N5 and N8 are turned on and NMOSFETs N6 and N7 are turned off. Therefore, since the poly resistors r6 and r9 are short-circuited, the resistor R1 is in a state where the poly resistors r7 and r8 and the poly resistor r10 are connected in series.

In both the first state and the second state, the combined resistance value of the resistor R1 is (A + B + C) kΩ, and this invariant value is designed to match the resistance value of the resistor R2 (for example, R1 =). R2 = 250kΩ).

As described above, the technical significance of adding a formal trimming function to the resistor R1 that does not include the diffusion resistance portion will be described. When the above-mentioned fourth configuration example is adopted, the resistance value matching between the resistors R1 and R2 is deviated due to the leakage current generated between the source and drain of the NMOSFETs N1 to N4 and between the subs. In particular, at high temperatures where the leakage current becomes large, the above problem becomes remarkable, which can be a factor of deteriorating the temperature characteristics of the reference voltage Vref.

On the other hand, in the reference voltage generation circuit 20 of the fifth configuration example, the same leakage characteristics are given to both the resistor R1 and the resistor R2. Therefore, it is possible to cancel the deviation of the resistance value matching caused by the leakage current of NMOSFETs N1 to N4, and it is possible to improve the temperature characteristic of the reference voltage Vref under high temperature.

<Regulator (first configuration example)>
FIG. 13 is a circuit diagram showing a first configuration example of the regulator 30. The regulator 30 of the first configuration example includes an operational amplifier AMP1, a resistor ladder RL1, a switch group SW1, and a decoder DEC1. The trimming signal Strim input to the decoder DEC1 is read from the non-volatile memory 50.

The operational amplifier AMP1 outputs the amplification voltage Vamp so that the feedback voltage Vfb input to the inverting input terminal (−) matches the reference voltage Vref input to the non-inverting input terminal (+). The amplified voltage Vamp is output to the subsequent stage as the above-mentioned constant voltage Vreg.

The resistance ladder RL1 is a resistance voltage dividing circuit that divides the amplification voltage Vamp to generate a feedback voltage Vfb, and is between the output end (= application end of the amplification voltage Vamp) of the operational amplifier AMP1 and the application end of the ground voltage Vss. , Resistors R11, resistors R12, and resistor trains R13 (= m resistors R13 (1) to R13 (m)) are connected in series.

A specific description will be given according to the example in this figure. The first end of the resistor R12 is connected to the output end of the operational amplifier AMP1. The second end of the resistor R12 is connected to the first end of the resistor R13 (1). The second end of the resistor R13 (k) (where k = 1, 2, ..., M-1) is connected to the first end of the resistor R13 (k + 1). The second end of the resistor R13 (m) is connected to the first end of the resistor R11. The second end of the resistor R11 is connected to the application end of the ground voltage Vss.

The switch group SW1 is a circuit unit that selects one of the nodes at both ends or the intermediate node of the resistance train R13 included in the resistance ladder RL1 and connects it to the inverting input end (-) of the operational amplifier AMP1. PMOSFETs P1 (0) to P1 Includes (m). The PMOSFET P1 (0) is connected between the first end of the resistor R13 (1) and the inverting input end (−) of the operational amplifier AMP1, and is turned on / off according to an instruction from the decoder DEC1. PMOSFETs P1 (1) to P1 (m) are connected between the second end of the resistors R13 (1) to R13 (m) and the inverting input end (-) of the operational amplifier AMP1, respectively, and are connected from the decoder DEC1. It is turned on / off according to the instruction.

The decoder DEC1 controls ON / OFF of PMOSFETs P1 (0) to P1 (m) included in the switch group SW1 according to the trimming signal Strim. For example, when PMOSFET P1 (0) is selectively turned on, the constant voltage Vreg is set to the minimum value VregL represented by the following equation (2a). On the other hand, when PMOSFET P1 (m) is selectively turned on, the constant voltage Vreg is set to the maximum value VregH represented by the following equation (2b).

Note that R11 and R12 in both equations indicate the resistance values of the resistors R11 and R12, respectively. Further, R13 indicates the maximum combined resistance value of the resistance column R13 (= the value obtained by adding all the resistance values of the resistors R13 (1) to R13 (m)).

Further, if any one of PMOSFETs P1 (1) to P1 (m-1) is alternately turned on, the constant voltage Vreg can be set in the range of VregL <Vreg <VregH.

As described above, in the regulator 30 of the first configuration example, the voltage division ratio of the resistance ladder RL1 (and the output gain of the regulator 30) can be arbitrarily adjusted according to the trimming signal Strim, so that the constant voltage Vreg is high. It is possible to improve the accuracy.

In particular, in the regulator 30 of the first configuration example, PMOSFETs P1 (0) to P1 (m) forming the switch group SW1 are inserted in a path through which current does not flow. Therefore, since each on-resistance does not affect the trimming accuracy, it is advantageous for improving the accuracy of the constant voltage Vreg.

However, in the regulator 30 of the first configuration example, the resistance values of the resistors R13 (1) to R13 (m) included in the resistance column R13 must all have the same value, and each of them can be weighted. Can not. Therefore, in order to finely trim the voltage division ratio of the resistor ladder RL1, a large number of resistors R13 (1) to R13 (m) and PMOSFETs P1 (0) to P1 (m) are required. Therefore, it is disadvantageous in reducing the scale of the regulator 30.

<Regulator (second configuration example)>
FIG. 14 is a circuit diagram showing a second configuration example of the regulator 30. The regulator 30 of the second configuration example includes an operational amplifier AMP2, a resistance ladder RL2, a switch group SW2, and a decoder DEC2. The trimming signal Strim input to the decoder DEC2 is read from the non-volatile memory 50.

The operational amplifier AMP2 outputs the amplification voltage Vamp so that the feedback voltage Vfb input to the inverting input terminal (−) matches the reference voltage Vref input to the non-inverting input terminal (+). The amplified voltage Vamp is output to the subsequent stage as the above-mentioned constant voltage Vreg.

The resistance ladder RL2 is a resistance voltage dividing circuit that divides the amplification voltage Vamp to generate a feedback voltage Vfb, and is between the output end (= application end of the amplification voltage Vamp) of the operational amplifier AMP2 and the application end of the ground voltage Vss. , Resistance R21, resistance R22, and resistance train R23 (= n resistors R23 (1) to R23 (n)) are connected in series.

A specific description will be given according to the example in this figure. The first end of the resistor R22 is connected to the output end of the operational amplifier AMP2. The second end of the resistor R22 is connected to the first end of the resistor R23 (1). The second end of the resistor R23 (k) (where k = 1, 2, ..., N-1) is connected to the first end of the resistor R23 (k + 1). The second end of the resistor R23 (n) is connected to the first end of the resistor R21 and the inverting input end (−) of the operational amplifier AMP2. The second end of the resistor R21 is connected to the application end of the ground voltage Vss.

The switch group SW2 includes PMOSFETs P2 (1) to P2 (n) connected in parallel to the resistors R23 (1) to R23 (n), respectively. The PMOSFETs P2 (1) to P2 (n) are turned on / off in response to an instruction from the decoder DEC2, respectively.

The decoder DEC2 controls ON / OFF of PMOSFETs P2 (1) to P2 (n) included in the switch group SW2 according to the trimming signal Strim. For example, when all PMOSFETs P2 (1) to P2 (n) are turned on, the constant voltage Vreg is set to the minimum value VregL represented by the following equation (3a). On the other hand, when all PMOSFETs P2 (1) to P2 (n) are turned off, the constant voltage Vreg is set to the maximum value VregH represented by the following equation (3b).

Note that R21 and R22 in both equations indicate the resistance values of the resistors R21 and R22, respectively. Further, R23 indicates the maximum combined resistance value of the resistance column R23 (= the value obtained by adding all the resistance values of the resistors R23 (1) to R23 (n)).

Further, the constant voltage Vreg can be set in the range of VregL <Vreg <VregH by turning on any one or a plurality of PMOSFETs P2 (1) to P2 (n).

In this way, in the regulator 30 of the second configuration example, the voltage division ratio of the resistance ladder RL2 (and the output gain of the regulator 30) is arbitrarily adjusted according to the trimming signal Strim, as in the first configuration example described above. Therefore, it is possible to improve the accuracy of the constant voltage Vreg.

In particular, in the regulator 30 of the second configuration example, the resistance values of the resistors R23 (1) to R23 (n) included in the resistance column R23 can be set to different values, and each weighting can be performed. Therefore, even if the resistors R23 (1) to R23 (n) and PMOSFET P2 (1) to P2 (n) are reduced as compared with the first configuration example, the voltage division ratio of the resistance ladder RL2 is trimmed with the same fineness. This is advantageous in reducing the scale of the regulator 30.

However, in the regulator 30 of the second configuration example, a current flows through the PMOSFETs P2 (1) to P2 (n) forming the switch group SW2 that are on. Therefore, the on-resistance may affect the trimming accuracy, which is disadvantageous in improving the accuracy of the constant voltage Vreg.

<Regulator (3rd configuration example)>
FIG. 15 is a circuit diagram showing a third configuration example of the regulator 30. The regulator 30 of the third configuration example includes an operational amplifier AMP3, a resistance ladder RL3, switch groups SW31 and SW32, and a decoder DEC3. The trimming signal Strim input to the decoder DEC3 is read from the non-volatile memory 50.

The operational amplifier AMP3 outputs the amplification voltage Vamp so that the feedback voltage Vfb input to the inverting input terminal (−) matches the reference voltage Vref input to the non-inverting input terminal (+).

The resistor ladder RL31 is a resistance voltage divider circuit that divides the amplification voltage Vamp to generate a feedback voltage Vfb and a constant voltage Vreg, and is an output end (= application end of the amplification voltage Vamp) and an application end of the ground voltage Vss of the operational amplifier AMP3. Between the resistors R31 (= i resistors R31 (1) to R31 (i)), the resistor column R32 (= j resistors R32 (1) to R32 (j)), and the resistors R33 and R34 are connected in series.

A specific description will be given according to the example in this figure. The first end of the resistor R31 (1) is connected to the output end of the operational amplifier AMP3. The second end of the resistor R31 (p) (where p = 1, 2, ..., I-1) is connected to the first end of the resistor R31 (p + 1). The second end of the resistor R31 (i) is connected to the first end of the resistor R33. The second end of the resistor R33 is connected to the first end of the resistor R32 (1). The second end of the resistor R32 (q) (where q = 1, 2, ..., J-1) is connected to the first end of the resistor R32 (q + 1). The second end of the resistor R32 (j) is connected to the first end of the resistor R34 and the inverting input end (−) of the operational amplifier AMP3. The second end of the resistor R34 is connected to the application end of the ground voltage Vss.

The switch group SW31 is a circuit unit that selects one of the nodes at both ends or the intermediate node of the resistance train R31 included in the resistance ladder RL3 and connects it to the output terminal of the constant voltage Vreg, and is connected to the output terminal of the constant voltage Vreg, and is connected to the output terminal of the constant voltage Vreg. including. The PMOSFET P31 (0) is connected between the first end (= output end of the operational amplifier AMP3) of the resistor R313 (1) and the output end of the constant voltage Vreg, and is turned on / off according to an instruction from the decoder DEC3. Will be done. The PMOSFETs P31 (1) to P31 (i) are connected between the second end of the resistors R31 (1) to R31 (i) and the output end of the constant voltage Vreg, respectively, and respond to an instruction from the decoder DEC3. On / off.

The switch group SW32 includes PMOSFETs P32 (1) to P32 (j) connected in parallel to the resistors R32 (1) to R32 (j), respectively. The PMOSFETs P32 (1) to P32 (j) are turned on / off in response to an instruction from the decoder DEC3, respectively.

The decoder DEC3 controls the on / off of PMOSFETs P31 (0) to P31 (i) included in the switch group SW31 and the PMOSFETs P32 (1) to P32 (j) included in the switching group SW32 according to the trimming signal Strim. Perform on / off control. For example, when PMOSFET P31 (i) is selectively turned on in the switch group SW31 and all PMOSFETs P32 (1) to P32 (j) are turned on in the switch group SW32, the constant voltage Vreg is expressed by the following equation (4a). It is set to the lowest value VregL represented. On the other hand, when PMOSFET P31 (0) is selectively turned on in the switch group SW31 and both PMOSFETs P32 (1) to P32 (j) are turned off in the switch group SW32, the constant voltage Vreg is the following equation (4b). It is set to the maximum value VregH represented by.

In both equations, R31 indicates the maximum combined resistance value of the resistance column R31 (= the value obtained by adding all the resistance values of the resistors R31 (1) to R31 (i)). Further, R32 indicates the maximum combined resistance value of the resistance column R32 (= the value obtained by adding all the resistance values of the resistors R32 (1) to R32 (j)). Further, R33 and R34 indicate the resistance values of the resistors R33 and R34, respectively.

Further, the constant voltage Vreg is set in the range of VregL <Vreg <VregH by appropriately turning on / off the PMOSFETs P31 (0) to P31 (i) and the PMOSFETs P32 (1) to P32 (j) in a combination other than the above. Can be done.

As described above, in the regulator 30 of the third configuration example, the voltage division ratio of the resistance ladder RL3 (and the output gain of the regulator 30) according to the trimming signal Strim, as in the first configuration example and the second configuration example described above. Can be arbitrarily adjusted, so that the constant voltage Vreg can be made highly accurate.

Here, the resistors R31 (1) to R31 (i) are all designed to have the same resistance value (for example, less than 5 kΩ). Further, the resistors R32 (1) to R32 (j) all have a higher resistance value (for example, 5 kΩ or more) than the resistors R31 (1) to R31 (i), and all have different resistance values. Each weighting is done.

With such a configuration, it is possible to overcome the disadvantages of each of the above-mentioned first configuration example (FIG. 13) and second configuration example (FIG. 14) while inheriting the advantages. Therefore, it is possible to achieve both high accuracy of the constant voltage Vreg and miniaturization of the regulator 30.

It is desirable that the element sizes of the resistors R32 (1) to R32 (j) are appropriately determined according to the element sizes of the PMOSFETs P32 (1) to P32 (j) connected in parallel with them. That is, it is desirable that the resistance values of the resistors R32 (1) to R32 (j) be designed so that the influence of the on-resistance of the PMOSFETs P32 (1) to P32 (j) can be almost ignored.

More specifically, for resistors R32 (1) to R32 (j) of 5 kΩ or more, weighting of each resistance value is realized by allowing parallel connection of PMOSFETs P32 (1) to P32 (j), and a regulator. It is desirable to reduce the size of 30.

On the other hand, with respect to the resistors R31 (1) to R31 (i) having a resistance of less than 5 kΩ, PMOSFETs P1 (0) to P1 (m) are inserted into a path through which current does not flow in view of being easily affected by the on-resistance of the PMOSFET. It is desirable to improve the trimming accuracy.

FIG. 16 is a trimming operation diagram in the third configuration example, in order from the top, trimming signals Strim, gate signals of PMOSFETs P31 (0) to P31 (4), gate signals of PMOSFETs P32 (1) to P32 (3), and , The reference voltage Vreg is depicted. In this figure, for the sake of simplicity, i = 4 and j = 3, and R31 (1) = R31 (2) = R31 (3) = R31 (4) = 1 kΩ, R32 ( 1) = 5 kΩ, R32 (2) = 10 kΩ, R32 (3) = 20 kΩ.

When the data value of the trimming signal Strim is "0", PMOSFET P31 (0) is selectively turned on in the switch group SW31, and all PMOSFETs P32 (1) to P32 (3) are turned off in the switch group SW32. As a result, the constant voltage Vreg is set to the maximum value VregH (= (39 kΩ + R33 + R34) / R34 × Vref) represented by the above equation (4b).

When the data values of the trimming signal Strim are "1" to "4", PMOSFETs P31 (1) to P31 (4) are alternately turned on in the switch group SW31, while PMOSFET P32 (1) in the switch group SW32. ~ P32 (3) is all maintained in the off state. As a result, the constant voltage Vreg is set to a voltage value lowered by one step to four steps from the maximum value VregH due to the voltage drop in the resistance row R31. The amount of voltage reduction for each step is (1 kΩ / R34) × Vref.

When the data value of the trimming signal Strim is "5", the PMOSFET P31 (0) is selectively turned on again in the switch group SW31, and the PMOSFET P32 (1) is selectively turned on in the switch group SW32. That is, the amplified voltage Vamp is output as a constant voltage Vreg in a state where the combined resistance value of the resistance train R32 is lowered to 30 kΩ. As a result, the constant voltage Vreg is set to a voltage value (= (34 kΩ + R33 + R34) / R34 × Vref) which is lowered by 5 steps from the maximum value VregH.

When the data values of the trimming signal Strim are "6" to "9", PMOSFETs P31 (1) to P31 (4) are alternately turned on in the switch group SW31, while PMOSFET P32 (1) in the switch group SW32. Only remains on. As a result, the constant voltage Vreg is set to a voltage value that is 6 to 9 steps lower than the maximum value VregH.

When the data value of the trimming signal Strim is "10", the PMOSFET P31 (0) is selectively turned on again in the switch group SW31, and the PMOSFET P32 (2) is selectively turned on in the switch group SW32. That is, the amplified voltage Vamp is output as a constant voltage Vreg in a state where the combined resistance value of the resistance train R32 is lowered to 25 kΩ. As a result, the constant voltage Vreg is set to a voltage value (= (29 kΩ + R33 + R34) / R34 × Vref) which is lowered by 10 steps from the maximum value VregH.

When the data values of the trimming signal Strim are "11" to "14", PMOSFETs P31 (1) to P31 (4) are alternately turned on in the switch group SW31, while PMOSFET P32 (2) in the switch group SW32. Only stays on. As a result, the constant voltage Vreg is set to a voltage value lowered by 11 to 14 steps from the maximum value VregH.

When the data value of the trimming signal Strim is "15", the PMOSFET P31 (0) is selectively turned on again in the switch group SW31, and the PMOSFETs P32 (1) and P32 (2) are turned on in the switch group SW32. That is, the amplified voltage Vamp is output as a constant voltage Vreg in a state where the combined resistance value of the resistance train R32 is lowered to 20 kΩ. As a result, the constant voltage Vreg is set to a voltage value (= (24 kΩ + R33 + R34) / R34 × Vref) which is lowered by 15 steps from the maximum value VregH.

When the data value of the trimming signal Strim is "16" to "19", PMOSFETs P31 (1) to P31 (4) are alternately turned on in the switch group SW31, while PMOSFET P32 (1) in the switch group SW32. And P32 (2) are kept on. As a result, the constant voltage Vreg is set to a voltage value that is 16 to 19 steps lower than the maximum value VregH.

When the data value of the trimming signal Strim is "20", the PMOSFET P31 (0) is selectively turned on again in the switch group SW31, and the PMOSFET P32 (3) is selectively turned on in the switch group SW32. That is, the amplified voltage Vamp is output as a constant voltage Vreg in a state where the combined resistance value of the resistance train R32 is lowered to 15 kΩ. As a result, the constant voltage Vreg is set to a voltage value (= (19 kΩ + R33 + R34) / R34 × Vref) which is lowered by 20 steps from the maximum value VregH.

When the data values of the trimming signal Strim are "21" to "24", PMOSFETs P31 (1) to P31 (4) are alternately turned on in the switch group SW31, while PMOSFET P32 (3) in the switch group SW32. Only stays on. As a result, the constant voltage Vreg is set to a voltage value that is 21 to 24 steps lower than the maximum value VregH.

When the data value of the trimming signal Strim is "25", the PMOSFET P31 (0) is selectively turned on again in the switch group SW31, and the PMOSFETs P32 (1) and P32 (3) are turned on in the switch group SW32. That is, the amplified voltage Vamp is output as a constant voltage Vreg in a state where the combined resistance value of the resistance train R32 is lowered to 10 kΩ. As a result, the constant voltage Vreg is set to a voltage value (= (14 kΩ + R33 + R34) / R34 × Vref) that is lowered by 25 steps from the maximum value VregH.

When the data values of the trimming signal Strim are "26" to "29", PMOSFETs P31 (1) to P31 (4) are alternately turned on in the switch group SW31, while PMOSFET P32 (1) in the switch group SW32. And P32 (3) are kept on. As a result, the constant voltage Vreg is set to a voltage value that is 26 to 29 steps lower than the maximum value VregH.

When the data value of the trimming signal Strim is "30", the PMOSFET P31 (0) is selectively turned on again in the switch group SW31, and the PMOSFETs P32 (2) and P32 (3) are turned on in the switch group SW32. That is, the amplified voltage Vamp is output as a constant voltage Vreg in a state where the combined resistance value of the resistance train R32 is lowered to 5 kΩ. As a result, the constant voltage Vreg is set to a voltage value (= (9 kΩ + R33 + R34) / R34 × Vref) which is lowered by 30 steps from the maximum value VregH.

When the data values of the trimming signal Strim are "31" to "34", PMOSFETs P31 (1) to P31 (4) are alternately turned on in the switch group SW31, while PMOSFET P32 (2) in the switch group SW32. And P32 (3) are kept on. As a result, the constant voltage Vreg is set to a voltage value that is 31 to 34 steps lower than the maximum value VregH.

When the data value of the trimming signal Strim is "35", the PMOSFET P31 (0) is selectively turned on again in the switch group SW31, and the PMOSFETs P32 (1) to P32 (3) are all turned on in the switch group SW32. .. That is, the amplification voltage Vamp is output as a constant voltage Vreg in a state where the resistance train R32 is short-circuited. As a result, the constant voltage Vreg is set to a voltage value (= (4 kΩ + R33 + R34) / R34 × Vref) that is lowered by 35 steps from the maximum value VregH.

When the data value of the trimming signal Strim is "36" to "39", PMOSFETs P31 (1) to P31 (4) are alternately turned on in the switch group SW31, while PMOSFET P32 (1) in the switch group SW32. ~ P32 (3) are all maintained in the ON state. As a result, the constant voltage Vreg is set to a voltage value that is 36 to 39 steps lower than the maximum value VregH. When the data value of the trimming data Strim is "39", the constant voltage Vreg is set to the minimum value VregL (= (R33 + R34) / R34 × Vref) represented by the above equation (4a).

For example, when the data value "20" of the trimming signal Strim is used as a reference (offset 0), if the data value is set to be smaller than "20", a positive electrode offset can be given to the constant voltage Vreg. If the data value is set to be larger than "20", a negative electrode property can be given to the constant voltage Vreg.

<Other variants>
In addition to the above-described embodiment, various technical features disclosed in the present specification can be modified in various ways without departing from the spirit of the technical creation. For example, mutual replacement between a bipolar transistor and a MOS field effect transistor and logic level inversion of various signals are arbitrary. That is, it should be considered that the above-described embodiment is exemplary in all respects and is not restrictive, and the technical scope of the present invention is not the description of the above-mentioned embodiment but the scope of claims. It is shown and should be understood to include all modifications that fall within the meaning and scope of the claims.

The invention disclosed in the present specification can be used, for example, for improving the accuracy of a voltage reference IC.

1 Semiconductor device (voltage reference IC)
10 Pre-regulator 11 Bandgap reference voltage source 12, 13 Operational amplifier 14 to 17 Resistance 20 Reference voltage generation circuit 21, 21A to 21C Bandgap reference voltage source 22 Selector 22A to 22C PMOSFET
23x, 23y comparator 24 Logical operation unit 24a AND gate 24b NAND gate 24c OR gate 30 Regulator 40 Buffer 50 Non-volatile memory 100 Semiconductor device 101 Semiconductor substrate 102 1st low concentration n type diffusion area 103 High concentration n type diffusion area 104 2nd Low concentration n-type diffusion region (tunnel region)
105 ► Electrode 106 Wiring 107 Insulation layer 108 Element separation area 109 Floating gate area R1, R2, R3 Resistance D1, D2 Diode AMP operational amplifier N1 to N8 NMOSFET
INV1 to INV4 Inverters R1a, R1b, R2a Poly resistance part R2b Diffusion resistance part r1 to r10 Element resistance TRIM1, TRIM2 Trimming part RL1 to RL3 Resistance ladder R11, R12 Resistance R13 Resistance series R13 (1) to R13 (m) Resistance R21, R22 resistance R23 resistance row R23 (1) to R23 (n) resistance R31, R32 resistance row R31 (1) to R31 (i) resistance R32 (1) to R32 (j) resistance R33, R34 resistance SW1, SW2, SW31, SW32 switch group P1 (), P2 (), P31 (), P32 () PMOSFET
AMP1 to AMP3 operational amplifier DEC1 to DEC3 decoder

Claims (10)

A first reference voltage source that produces a first reference voltage,
A second reference voltage source that generates a second reference voltage having a temperature characteristic different from that of the first reference voltage,
A first comparator that compares the first reference voltage with the second reference voltage to generate a first comparison signal, and
A third reference voltage source that generates a third reference voltage having different temperature characteristics from both the first reference voltage and the second reference voltage.
A second comparator that compares the second reference voltage with the third reference voltage to generate a second comparison signal, and
A logical operation unit that generates a switching signal from the first comparison signal and the second comparison signal, and
A selector that selectively outputs one of the first reference voltage, the second reference voltage, and the third reference voltage as a reference voltage according to the switching signal.
A reference voltage generation circuit characterized by having. Said first reference voltage becomes maximum at around -20 ° C., the second reference voltage becomes maximum at around + 40 ° C., according to claim 1, wherein the third reference voltage is equal to an maximum at around + 100 ° C. Reference voltage generation circuit. The reference voltage generation circuit according to claim 1 or 2 , wherein each reference voltage source is a bandgap reference voltage source. Each reference voltage source is
With an amplifier
A first resistor connected between the output end of the amplifier and the first input end of the amplifier,
A second resistor connected between the output end of the amplifier and the second input end of the amplifier,
A third resistor connected between the second input end and the ground end of the amplifier,
A first diode connected between the first input end and the ground end of the amplifier,
A plurality of parallel second diodes connected between the second input end and the ground end of the amplifier,
The reference voltage generation circuit according to claim 3 , wherein each of the reference voltage generation circuits is included. The reference voltage generation circuit according to claim 4 , wherein the resistance ratio between the second resistor and the third resistor is different for each reference voltage source. A semiconductor device comprising the reference voltage generation circuit according to any one of claims 1 to 5 . A pre-regulator that generates the first internal power supply voltage and the second internal power supply voltage from the input voltage,
A regulator that generates a constant voltage from the first internal power supply voltage,
Have more
The reference voltage generation circuit receives the supply of the second internal power supply voltage from the pre-regulator to generate the reference voltage.
The semiconductor device according to claim 6 , wherein the regulator performs output feedback control so that the constant voltage or the feedback voltage corresponding thereto matches the reference voltage. A semiconductor device having a reference voltage generation circuit.
The reference voltage generation circuit is
In a predetermined temperature range, the voltage decreases as the temperature rises, and in a temperature range lower than one temperature included in the predetermined temperature range, the voltage increases as the temperature rises and turns to decrease after passing the maximum. A first reference voltage source that produces a first reference voltage that falls within a predetermined temperature range,
In the predetermined temperature range, the voltage increases as the temperature rises, and after entering a temperature region higher than the one temperature included in the predetermined temperature range, the voltage further increases as the temperature rises to the maximum. A second reference voltage source that produces a second reference voltage that passes and turns to decrease,
A first comparator that compares the first reference voltage with the second reference voltage to generate a first comparison signal, and
A selector that selectively outputs the larger of the first reference voltage and the second reference voltage as the reference voltage according to the first comparison signal.
Have,
The first reference voltage and the second reference voltage coincide with each other at the one temperature included in the predetermined temperature range.
The semiconductor device is
A pre-regulator that generates the first internal power supply voltage and the second internal power supply voltage from the input voltage,
A regulator that generates a constant voltage from the first internal power supply voltage,
Have more
The reference voltage generation circuit receives the supply of the second internal power supply voltage from the pre-regulator to generate the reference voltage.
The regulator is a semiconductor device characterized in that output feedback control is performed so that the constant voltage or the feedback voltage corresponding thereto matches the reference voltage. The semiconductor device according to claim 7 or 8, further comprising a buffer that receives an input of the constant voltage and outputs a buffer voltage. The semiconductor device according to claim 9, wherein at least one of the first internal power supply voltage, the constant voltage, and the buffer voltage is output to the outside.

Images