JP2009003568A - Reference voltage generation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a constant output voltage in a reference voltage generation circuit with high accuracy. <P>SOLUTION: This reference voltage generation circuit has: a first PN junction element D1 constituting a temperature coefficient correction circuit 1; a third PN junction element D3 having the same configuration as a second PN junction element D2 constituting a reference voltage circuit 2, connected in parallel to the first PN junction element D1 so as to be electrically cut; and a first reference voltage circuit 4 including a fourth resistor R4 having the same composition as a first resistor R1 constituting the temperature coefficient correction circuit 1 and a fifth resistor R5 comprising a diffusion layer formed in the same substrate as the second PN junction element D2. The third PN junction element D3 is dynamically and electrically connected/cut to/from the first PN junction element D1 according to a ratio of a finished value of a resistance value of the fifth resistor to the fourth resistor R4. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a reference voltage generation circuit that generates a reference voltage used in an analog circuit.

  The reference voltage generation circuit is a circuit that generates a predetermined constant voltage regardless of a change in temperature or a change in the power supply voltage of the circuit. Conventionally, various circuit systems have been devised. Among them, the most commonly used reference voltage generating circuit is a circuit system that utilizes the temperature dependence of the forward voltage of a PN junction element.

  A conventional reference voltage generation circuit will be described below.

FIG. 7 shows a circuit configuration of a conventional reference voltage generating circuit. The first PN junction element D1 having a cathode connected to the ground voltage V _SS, a first resistor R1 having one end connected to the anode of the first PN junction element D1, one end first resistor R1 The second resistor R2 is connected to the other end of the first resistor R2 and the other end is connected to the output terminal BGROUT. The voltage at the connection point between the first resistor R1 and the second resistor R2 is set to the first resistor R2. the temperature coefficient compensation circuit 101 for outputting a voltage V ₁ of the cathode is the second PN junction element D2 which is connected to the ground voltage V _SS, one end thereof connected to the anode of the second PN junction element D2, the other end There is constituted by a third resistor R3 connected to the output terminal BGROUT, reference for outputting a voltage at a connection point between the second PN junction element D2 and the third resistor R3 as the second voltage V ₂ a voltage circuit 102, the first voltage _{V 1} is inverted Is inputted from the force terminal, a second voltage V ₂ is input from the non-inverting input terminal, and a differential amplifier circuit 103 which controls the output voltage V _o of the differential voltage between the two voltages to the operational amplifier ( For example, see Patent Document 1 or Non-Patent Document 1.)

For the relationship between the output voltage V _o and the circuit constant in the reference voltage generating circuit configured as described above will be described with reference to FIG.

The saturation currents of the first PN junction element D1 and the second PN junction element D2 are I _s1 and I _s2 , the PN junction currents are I ₁ and I ₂ , and the anode-cathode voltages are V _PN1 and V _PN2. The resistance values of the first resistor R1, the second resistor R2, and the third resistor R3 are r ₁ , r ₂ , and r ₃ , respectively.

  The relationship of the following formulas (1) and (2) is established between the PN junction current, the saturation current, and the anode-cathode voltage.

I ₁ = I _s1 · {exp (V _PN1 / V _T ) −1} (1)
I ₂ = I _s2 · {exp (V _PN2 / V _T ) −1} (2)
Here, _VT is a thermal voltage, and the relationship of the following formula | equation (3) is formed.

V _T = k · T / q (3)
Here, k is a Boltzmann constant, q is a unit charge, T is an absolute temperature, and when T = 300 K (about 27 ° C.), V _T is about 26 mV. Usually, V _PN1 and V _PN2 take a value in the vicinity of 0.7 V, and −1 on each right side of Equation (1) and Equation (2) is negligibly small compared to the exponent part, and can be omitted.

When the voltage across the first resistor R1 is V _R1 , the relationship of the following formula (4) is established.

V _R1 = V _PN2 −V _PN1
= V _T · LN (I ₂ / I _s2 ) −V _T · LN (I ₁ / I _s1 )
= V _T · LN (I ₂ · I _s1 / I ₁ · I _s2 ) (4)
Here, LN represents a natural logarithm.

The differential amplifier circuit 103, first voltages V ₁ and so that the second and the voltage V ₂ of equal the input voltage, the feedback control of the output voltage V _o. That is, the relationship of the following formula (5) is established.

I ₁ · r ₂ = I ₂ · r ₃ (5)
From the above equations (3), (4), and (5), the output voltage V _o is calculated as in the following equation (6).

V _o = V ₂ + I ₂ · r ₃
= V ₂ + I ₁ · r ₂
= V ₂ + (V _R1 / r ₁ ) · r ₂
= V ₂ + r ₂ / r ₁ · k / q · LN (I _s1 / I _s2 · r ₂ / r ₃ ) · T (6)
I _s1 and I _s2 are proportional to the areas of the first PN junction element D1 and the second PN junction element D2. Usually, the first PN junction element D1 has a PN junction element D5 having the same configuration as the second PN junction element D2 as a basic unit, and a plurality of PN junction elements D5 are connected in parallel by a required area. It is constituted by doing. When the number of parallel connections is n, Expression (6) is expressed as the following Expression (7).

V _o = V ₂ + r ₂ / r ₁ · k / q · LN (n · r ₂ / r ₃ ) · T (7)
The first term on the right side of the equation (7) is the anode-cathode voltage V _PN2 of the second PN junction element D2 and has a negative temperature coefficient (at −27 mV / ° C. at 27 ° C.). The second term on the right side of Equation (7) is a function that increases in proportion to the absolute temperature T, and has a positive temperature coefficient. Accordingly, the first resistor R1, the second resistor R2, and the third resistor R3 are arranged so as to cancel the negative temperature coefficient of the anode-cathode voltage V _PN2 in the second PN junction element D2. and the resistance value r ₁ ~r _3, by selecting the number of parallel connections n PN junction element D5 constituting the first PN junction element D1 appropriate to set the temperature coefficient of the output voltage V _o to approximately 0 be able to. Further, Equation (7) has no term relating to the power supply voltage, and is essentially independent of the power supply voltage. Further, the performance of the differential amplifier circuit 103, for example, a voltage gain, input offset voltage, drivability and power supply rejection ratio, etc., which affect the characteristics of the output voltage V _o, usually required in the reference voltage generating circuit performance of the differential amplifier circuit 103 are readily implemented in a semiconductor integrated circuit using the modern semiconductor processes, can be substantially eliminated practical effect on the output voltage V _o. Furthermore, although the resistance values r _{1 to} r ₃ are represented in the second term of the equation (7), they are represented by the ratio of the two resistance values, and the absolute resistances that vary due to process variations. It does not depend on the value.

  As described above, the conventional reference voltage generation circuit has no dependency on the temperature, the power supply voltage, and the process variation, and can always supply a constant voltage. As a reference voltage source of the semiconductor integrated circuit, the power supply circuit And other analog circuits such as an analog / digital (A / D) converter, a digital / analog (D / A) converter, or a PLL (phase-locked loop) circuit.

  In a standard complementary metal-oxide semiconductor (CMOS) process widely applied to the current semiconductor integrated circuit, no special process option is required to realize the reference voltage generation circuit. Therefore, the first resistor R1, A structure using polysilicon resistors as the second resistor R2 and the third resistor R3, respectively, and a boundary portion between the diffusion layer and the well as the first PN junction element D1 and the second PN junction element D2 A configuration using a PN junction element is common.

  8 and 9 schematically show a configuration example of a PN junction element including a boundary portion between a diffusion layer and a well formed by a standard CMOS process.

  FIG. 8 shows a planar configuration of the PN junction element, and FIG. 9 shows a cross-sectional configuration taken along line IX-IX in FIG.

  As shown in FIGS. 8 and 9, the PN junction element includes a semiconductor layer 201 constituted by a P-type or N-type semiconductor substrate or well, and a first separation layer 202 constituted above the semiconductor layer 201. Are formed in a region surrounded by the first isolation layer 202 and the semiconductor layer 201, and have a well 203 having a polarity opposite to that of the semiconductor layer 201, the well 203 and the first isolation layer 202. A first diffusion layer 204 formed along the inner periphery and having the same polarity as the well 203, and a second isolation formed on the well 203 along the inner periphery of the first diffusion layer 204 The layer 105 and the second diffusion layer 206 formed in a region surrounded by the well 203 and the second separation layer 205 and having the opposite polarity to the well 203, and the well 203 and the second diffusion layer. PN contact at boundary with layer 206 Element 207 is formed.

  In the PN junction element shown in FIGS. 8 and 9, when the well 203 is P-type, the second diffusion layer 206 is N-type, and the direction from the well 203 toward the second diffusion layer 206 is the forward direction. It becomes. Conversely, when the well 203 is N-type, the second diffusion layer 206 is P-type, and the direction from the second diffusion layer 206 toward the well 203 is the forward direction.

  When the PN junction element shown in FIGS. 8 and 9 is used in the forward direction region, the well 203 and the second diffusion layer 206 from the upper surface of the first diffusion layer 204 through the first diffusion layer 204 are used. A forward voltage is applied across the upper surface of the substrate. Since a voltage in the opposite direction to the well 203 is applied to the semiconductor layer 201, a forward current flows only through the well 203 and the second diffusion layer 206 via the first diffusion layer 204.

Figure 10 shows a characteristic example at 27 ° C. in the forward current _{I s} (about 300K) for the forward voltage _{V PN} PN junction element shown in FIGS. The horizontal axis is the forward voltage V _PN, the vertical axis represents the forward current I _s shown in logarithm. As shown in FIG. 10, the forward characteristics of the PN junction element are as follows. In the voltage region from the forward voltage V _PN starting to be shown to around 0.7 V, the forward current Is is expressed by the equations (1) and (2). As shown in (), it increases exponentially with increasing forward voltage VPN. It exceeds the forward voltage _{V PN} is 0.7V around, the forward current _{I s} is in the vicinity of 1 × ^{10 -4} A, the forward current _{I s} start off the exponential increase, increase rate is decreased Go. The main cause of such characteristics is the resistance component of the well 203 from the boundary portion of the well 203 to the first diffusion layer 204 in the PN junction element 207 shown in FIG. The PN junction element shown in FIGS. 8 and 9 when used in the conventional reference voltage generating circuit shown in FIG. 7, the forward current I _s is sufficiently negligible the influence of the resistance component of the well 203 Basically, a low current region (for example, a region up to about 1 × 10 ⁻⁵ A) is used.

For example, assuming that the characteristic shown in FIG. 10 is the second PN junction element D2 of the conventional reference voltage generating circuit shown in FIG. 7, the conventional reference voltage generation is performed at the first operating point OP1 shown in FIG. when operating the circuit, PN junction elements constituting the respective resistance values _r 1 ~r ₃ of the first to third resistors R1-R3, the first PN junction element D1 for the second PN junction element D2 The parallel connection number n of D5 can be set as follows. That is, the output voltage V _o is a constant voltage of about 1.25 V, and the anode-cathode voltage V _PN2 = second voltage V ₂ = 0.0 by the first operating point OP1 of the second PN junction element D2. Since the PN junction current I ₂ = 6 μA at 65 V, the resistance value r _{3 of the third} resistor R ₃ = (V _o −V _PN2 ) / I ₂ = (1.25−0.65) V / 6 μA = 100KΩ. Therefore, the resistance values r ₁ and r _{2 of} the first resistor R1 and the second resistor R2 and the number n of parallel connections of the PN junction element D5 are determined by the second term on the right side of Equation (7) being 27 ° C. It is necessary to set so as to cancel the negative temperature coefficient of about −2 mV / ° C. of the anode-cathode voltage V _PN2 of the second PN junction element D2. Usually, the number n of parallel connections of the PN junction element D5 is often selected to be about 10. Here, n = 10 is set. Further, by setting the resistance value _{r 3} of the third resistor R3 and the resistance value _{r 2} of the second resistor R2 together 100 K.OMEGA, by setting the resistance value _{r 1} of the first resistor R1 to 10KΩ The second term on the right side of Equation (7) is r ₂ / r ₁ · k / q · LN (n · r ₂ / r ₃ ) · T = 100 KΩ / 10 KΩ · LN (10 · 100 KΩ / 100 KΩ) · 26 mV≈ 0.6V and the temperature coefficient is about 0.6V / 300K = 2 mV / ° C., and the negative temperature coefficient of the second PN junction element D2 can be offset.

At this time, according to the equation (5), the PN junction current I ₁ = r ₃ / r ₂ · I ₂ = 100 KΩ / 100 KΩ · 6 μA = 6 μA. Since the first voltage V ₁ and the second voltage V ₂ are controlled to be equal to each other by the differential amplifier circuit 103, the first voltage V ₁ = the second voltage V ₂ = 0.65V. . Accordingly, the anode-cathode voltage V _PN1 of the first PN junction element D1 is V ₁ −I ₁ · r ₁ = 0.65 V−6 μA · 10 KΩ = 0.59 V. The second operating point OP2 shown in FIG. 10 takes the PN junction current of the PN junction element D5 that constitutes the first PN junction element D1 and has the same configuration as the second PN junction element D2. Since it is 0.6 μA and multiplied by 10 which is the number n of parallel connections of the PN junction element D5, it is 6 μA, so that the PN junction current I ₁ is 6 μA, and the entire temperature coefficient correction circuit is matched.

In summary, in the conventional reference voltage generating circuit shown in FIG. 7, the operating point of the second PN junction element D2 is the first operating point OP1 shown in FIG. 10 (forward voltage V _PN = 0.65V, When the forward current = 6 μA), the resistance value r _{1 of the first} resistor R ₁ = 10 KΩ, the resistance value r _{2 of the second} resistor R ₂ = ₁₀₀ KΩ, and the resistance value r of the third resistor R 3 ₃ = 100 KΩ, and the number of parallel connections n = 10 of the PN junction elements D5 constituting the first PN junction element D1 can be set.
JP 2003-7837 A Phillip E. Allen, CMOS Analog Circuit Design Second Second Edition, Oxford University Press, Inc. , P. 153-p. 159, 2002

However, the conventional reference voltage generation circuit mainly reduces the resistance of the first resistor R1, the second resistor R2, and the third resistor R3 for the purpose of reducing the circuit area. raises the output voltage V _o influence the constant voltage characteristic of the resistance component output voltage V _o of the wells 203 in the PN junction element shown in FIGS. 8 and 9, the problem of increasing the positive temperature dependence tendency Have.

Specifically, in the conventional reference voltage generation circuit, in order to reduce the circuit area, the area of each resistor and each PN junction element which are main components of the reference voltage generation circuit is reduced. In order to reduce the area of the resistor, since the length of the resistor is reduced rather than reducing the width of the resistor from the viewpoint of variation in the resistance value depending on the manufacturing process, the resistance value of the resistor is lowered. Since the output voltage V _o of the reference voltage generating circuit is substantially constant at about 1.25V, the decreases the resistance value of the resistor, because the current flowing through the circuit increases in proportion thereto, PN junction As long as the area of the element is not increased, the current density increases. Here, the current density of the PN junction element is increased, the resistance component parasitic on the PN junction element (in the PN junction element shown in example FIGS. 8 and 9, the resistance component of the well 203) effect on the output voltage V _o of Cannot be ignored. That is, assuming that the forward characteristic of the PN junction element shown in FIG. 10 is the second PN junction element D2 shown in FIG. 7, the first resistor R1 and the second resistance for the purpose of reducing the circuit area. When the resistance values of the resistor R2 and the third resistor R3 are to be reduced to about 1/10, it is necessary to increase the circuit current to about 10 times (the PN junction element shown in FIG. 10). The third operating point OP3 in the forward characteristics of (refer to the forward voltage V _PN = 0.71 V, the forward current = 60 μA). At this time, the current density of the second PN junction element D2 is also increased 10 times. Actually, when the current density of the second PN junction element D2 increases, the resistance component of the well 203 of the PN junction element shown in FIG. 9 becomes obvious, and the well 203 with respect to the resistance value r1 of the _first resistor R1. When the relative ratio of the resistance components of the is increased, the forward current as designed cannot be obtained.

Hereinafter, the resistance value of the resistance component of the well 203 as r _w, taking into account the influence, equation representing the relationship between the output voltage V _o and the circuit constant of the conventional reference voltage generating circuit shown in FIG. 7 ( Try recalculating 7). However, since the first PN junction element D1 connects n PN junction elements D5 identical to the second PN junction element D2 in parallel, and n is about 10, the first PN junction element D1 The resistance component of the well 203 of D1 is as small as about 1/10 compared to the second PN junction element D2. For this reason, it is not explicitly shown in the following calculation. (Because the first PN junction element D1 is connected in series with the first resistor R1, it is included in the first resistor R1. You can think about that.) The relationship of the following new formula with respect to the output voltage V _o (8) holds.

V _o = V ₁ + I ₁ · (r ₁ + r ₂ ) = V ₂ + I ₂ · (r ₃ + r _w ) (8)
Equation (8), the above-mentioned formula (3), by the equation (4) and (5), the output voltage _{V o} is expressed as the following equation (9).

V _o = V ₂ + r ₂ · (1 + r _w / r ₃ ) / {r ₁ · (1-r ₂ · r _w / r ₁ / r ₃ )} · k / q · LN (n · r ₂ / r ₃ ) ・ T ...... (9)
Here, regarding the second term on the right side of Expression (7) and Expression (9), when the ratio of Expression (9) to Expression (7) is taken, it is expressed as the following Expression (10).

(1 + r _w / r ₃ ) / (1-r ₂ · r _w / r ₁ / r ₃ ) (10)
In this setting example, when r ₂ = r ₃ and r ₃ = 10 · r ₁ is considered in consideration of >> r _w , Expression (10) is expressed as Expression (11) below.

_{1 / (1-r w /} r 1) ...... (11)
As described above, in this configuration example, the resistance component of the well 203 of the PN junction element shown in FIG. 9, the output voltages V _o with respect to the second term on the right side of equation (7), about 1 / (1-r _w / r ₁ ) times higher, degrading the constant voltage characteristics in the reference voltage generating circuit.

Furthermore, the operating temperature of the circuit is varied from 27 ° C., since the second term of Equation (7) is proportional to the absolute temperature T, determines the degree of increase of the output voltage V _o is proportional to the temperature difference between 27 ° C. . For example, when the operating temperature is 125 ° C., the temperature difference from 27 ° C. is 98 ° C., so the degree of increase is increased by 98 / (300K) × 100 = 33% compared to 27 ° C. Further, when the operating temperature is −40 ° C., the temperature difference from 27 ° C. is −67 ° C., so that the degree of increase is reduced by −67 / (300 K) × 100 = −22% compared to 27 ° C. It will be. That is, the positive temperature dependence tendency of the output voltage V _o increases.

As described above, the conventional reference voltage generation circuit reduces the resistance values of the first resistor R1, the second resistor R2, and the third resistor R3 mainly for the purpose of reducing the circuit area. As you, the resistance component of the well 203 of the PN junction element shown in FIGS. 8 and 9, since it affects the constant voltage characteristic of the output voltage V _o increases the output voltage V _o, a positive temperature dependence tendency Increase.

The degree of influence is relative to the resistance values of the first resistor R1, the second resistor R2, and the third resistor R3 and the resistance component of the well 203, as shown in the equation (11). Only affected by the ratio. However, even if the circuit constants are optimized so as to offset this influence at a certain specific ratio (usually the reference value at the time of finishing each resistor), in actuality, in each of the resistors R1 to R3, The relative resistance value at the time of finishing will fluctuate. Therefore, a constant voltage characteristic of the output voltage V _o is deteriorated. For example, if the circuit is optimized by setting the resistance value of the resistance component of the well 203 to r _w = 100Ω with respect to the resistance value r ₁ = 1KΩ of the first resistor R1 in the previous setting example, Assuming that the fluctuation range of the first resistance type made of silicon and the second resistance type made of the diffusion layer are both ± 20%, the fluctuations of the first resistance type and the second resistance type are −20% and + 20%, respectively. The second term on the right side of equation (7) rises the most and fluctuates by about + 5.9%, and is the most when the fluctuations of the first resistance type and the second resistance type are + 20% and -20%. Decrease and change by about -3.6%. Conventionally, in order to obtain a high-accuracy output voltage by suppressing fluctuations in the output voltage due to these deviations caused by the resistance value manufacturing process, the resistance value must be trimmed in the wafer inspection process.

  An object of the present invention is to solve the above-mentioned conventional problems and to obtain a voltage characteristic with a constant output voltage in a reference voltage generation circuit with high accuracy.

  In order to achieve the above-mentioned object, the present invention monitors a relative finish of a resistance value of a first resistor or the like and a resistance component of a PN junction element formed of a well or the like by using a reference voltage generating circuit. The circuit constant of the reference voltage generation circuit can be dynamically changed in accordance with the value ratio.

  Specifically, a first reference voltage generation circuit according to the present invention includes a first resistor and a second resistor connected in series, and a first PN junction forward-connected to the first resistor. A temperature coefficient correction circuit including an element, a third resistor having one end connected to the output terminal and the second resistor, a forward connection with the third resistor, and a first diffusion layer of the substrate. A reference voltage circuit including the formed second PN junction element, a first voltage at a connection between the first resistor and the second resistor, a third resistor, and a second PN junction element A differential amplifier circuit for controlling the output voltage of the output terminal by amplifying a difference voltage from the second voltage at the connection portion of the first and second terminals connected to the constant current source and having the same composition as the first resistor. And a fifth resistor comprising a second diffusion layer connected to the constant current source and formed on the substrate. A first comparison circuit for comparing a voltage difference between a voltage generated by the fourth resistor and a voltage generated by the fifth resistor in the first reference voltage circuit, and a first PN junction element. And a third PN junction element connected in parallel via one switch circuit, wherein the first switch circuit is opened and closed based on a comparison result of the first comparison circuit.

  According to the first reference voltage generation circuit, for example, the resistance of the fifth resistor comprising the second diffusion layer formed on the substrate with respect to the resistance value of the fourth resistor having the same composition as the first resistor. When the value becomes higher than the predetermined ratio, the first switch circuit transitions from the conductive state to the non-conductive state, and the third PN junction element connected in parallel to the first PN junction element is disconnected. The increase in output voltage and the increase in the positive temperature dependence tendency can be suppressed. On the other hand, when the resistance value of the fifth resistor with respect to the resistance value of the fourth resistor is lower than a predetermined ratio, the first switch circuit transits from the non-conductive state to the conductive state. By connecting a third PN junction element connected in parallel to the first PN junction element, it is possible to suppress a decrease in output voltage and an increase in negative temperature dependence.

  In the first reference voltage generation circuit, the first reference voltage circuit is configured such that the ratio of the resistance value of the fifth resistor to the resistance value of the fourth resistor is higher than a predetermined value or higher than a predetermined value. It is preferable to output a differential voltage generated by the cooperation of the fourth resistor and the fifth resistor, the polarity of which is inverted when it is low, as the first reference voltage.

  In the first reference voltage generation circuit, a sixth resistor connected to the constant current source and having the same composition as the first resistor, and a third diffusion layer connected to the constant current source and formed on the substrate A second reference voltage circuit including a seventh resistor and a second reference voltage circuit for comparing a difference voltage between a voltage generated by the sixth resistor and a voltage generated by the seventh resistor in the second reference voltage circuit. And a fourth PN junction element connected in parallel to the first PN junction element via the second switch circuit, and the second switch circuit is a comparison of the second comparison circuit. It is preferable to open and close based on the result.

  In this case, the first reference voltage circuit includes a fourth resistor whose polarity is reversed when the ratio of the resistance value of the fifth resistor to the resistance value of the fourth resistor is higher than a predetermined value. A differential voltage generated by the cooperation of the resistor and the fifth resistor is output as a first reference voltage, and the second reference voltage circuit has a resistance of the seventh resistor with respect to the resistance value of the sixth resistor. It is preferable to output, as the second reference voltage, a differential voltage generated by the cooperation of the sixth resistor and the seventh resistor whose polarity is inverted when the ratio value of the values is lower than a predetermined value.

  In the first reference voltage generation circuit, the first PN junction element is preferably formed by connecting a plurality of PN junction elements having the same configuration as the second PN junction element in parallel.

  A second reference voltage generation circuit according to the present invention includes a first resistor connected in series, a second resistor and a third resistor, and a first resistor connected in a forward direction with the first resistor. A temperature coefficient correction circuit including a PN junction element; a fourth resistor having one end connected to the output terminal and the third resistor; and a first diffusion of the substrate connected in a forward direction to the fourth resistor. A reference voltage circuit including a second PN junction element formed in the layer; a first voltage at a connection between the second resistor and the third resistor; a fourth resistor and a second PN A differential amplifying circuit for amplifying a difference voltage from the second voltage at the connection portion of the junction element to control an output voltage of the output terminal, and a constant current source and having the same composition as the second resistor A first resistor including a fifth resistor and a sixth resistor connected to the constant current source and formed of a second diffusion layer formed on the substrate; A reference voltage circuit, a first comparison circuit for comparing a difference voltage between a voltage generated by the fifth resistor and a voltage generated by the sixth resistor in the first reference voltage circuit, and a first resistor in parallel with each other And a first switch circuit that is opened and closed based on a comparison result of the first comparison circuit.

  According to the second reference voltage generation circuit, for example, the resistance of the fifth resistor formed of the second diffusion layer formed on the substrate with respect to the resistance value of the fifth resistor having the same composition as the second resistor. When the value becomes higher than a predetermined ratio, the first switch circuit transits from the conductive state to the non-conductive state, and the first resistor connected in series to the second resistor is enabled. Therefore, an increase in output voltage and an increase in a positive temperature dependence tendency can be suppressed. On the other hand, when the resistance value of the fifth resistor with respect to the resistance value of the second resistor becomes lower than a predetermined ratio, the first switch circuit transitions from the non-conductive state to the conductive state. Since the first resistor is short-circuited in series with the second resistor, a decrease in output voltage and an increase in negative temperature dependence can be suppressed.

  In the second reference voltage generation circuit, a seventh resistor connected to the constant current source and having the same composition as the second resistor, and a third diffusion layer connected to the constant current source and formed on the substrate A second reference voltage circuit including an eighth resistor and a second reference voltage circuit for comparing a difference voltage between a voltage generated by the seventh resistor and a voltage generated by the eighth resistor in the second reference voltage circuit. A ninth resistor connected in series between the first resistor and the second resistor in the temperature coefficient correction circuit, and a second resistor connected in parallel to the ninth resistor, And a second switch circuit that is opened and closed based on the result of the comparison circuit.

  The third reference voltage generation circuit according to the present invention includes a first resistor and a second resistor connected in series, and a first PN junction element connected in the forward direction with the first resistor. A temperature coefficient correction circuit; a third resistor having one end connected to the output terminal and the second resistor; a fourth resistor connected in series to the third resistor; and the fourth resistor. And a first reference voltage circuit including a second PN junction element formed in the first diffusion layer of the substrate and a fifth resistor having one end connected to the output terminal, A sixth resistor connected in series with the fifth resistor, and a third PN junction element connected to the sixth resistor in the forward direction and formed in the second diffusion layer formed on the substrate. A second reference voltage circuit; a first voltage at a connection between the first resistor and the second resistor; and a first voltage at the first reference voltage circuit. The difference voltage between the second resistor and the fourth resistor or the second voltage of the fifth resistor and the sixth resistor in the second reference voltage circuit is amplified and output from the output terminal A differential amplifier circuit for controlling the voltage; a seventh resistor connected to the constant current source and having the same composition as the first resistor; and a third diffusion layer connected to the constant current source and formed on the substrate A first reference voltage circuit including an eighth resistor comprising: a first reference voltage circuit for comparing a difference voltage between a voltage generated by the seventh resistor and a voltage generated by the eighth resistor in the first reference voltage circuit; And a logic circuit that selects either the first reference voltage circuit or the second reference voltage circuit by performing a logical operation based on the comparison result of the first comparison circuit. It is characterized by being.

  According to the third reference voltage generation circuit, for example, the resistance of the eighth resistor comprising the third diffusion layer formed on the substrate with respect to the resistance value of the seventh resistor having the same composition as the first resistor. When the value becomes higher than a predetermined ratio, the output voltage of the first comparison circuit is inverted. Therefore, according to the output signal from the logic circuit, the first reference voltage circuit and the second reference voltage circuit according to the variation in the ratio of the resistance value when the seventh resistor is finished and the resistance value when the eighth resistor is finished. Since either one of the two reference voltage circuits is selected, it is possible to suppress an increase in the output voltage and an increase in the positive temperature dependence tendency, or a decrease in the output voltage and an increase in the negative temperature dependence tendency.

  In the third reference voltage generation circuit, a ninth resistor connected to the output terminal, a tenth resistor connected in series with the ninth resistor, and a forward connection to the tenth resistor A third reference voltage circuit including a fourth PN junction element formed in the fourth diffusion layer of the substrate and an eleventh resistor connected to the constant current source and having the same composition as the first resistor A second reference voltage circuit including a capacitor and a twelfth resistor connected to the constant current source and formed of a fifth diffusion layer formed on the substrate, and an eleventh resistor in the second reference voltage circuit A second comparison circuit for comparing a difference voltage between the generated voltage and the voltage generated by the twelfth resistor, and the logic circuit performs logic based on a comparison result of the first comparison circuit and the second comparison circuit. By performing the operation, the first reference voltage circuit, the second reference voltage circuit, and It is preferable to select one of the third reference voltage circuit.

  According to the reference voltage generation circuit of the present invention, the resistance component that is parasitic in series with the PN junction element that forms the reference voltage circuit with respect to the resistance value of the resistor that forms the temperature coefficient correction circuit fluctuates. Even when the output voltage constant voltage characteristic exceeds the predetermined range, the same resistance as the resistor constituting the temperature coefficient correction circuit and the parasitic resistance component of the diffusion layer constituting the PN junction element The relative finish of the resistance value of the resistance type can be monitored, and the circuit constant of the reference voltage generation circuit can be dynamically changed according to the ratio, so that the output voltage constant voltage characteristics can be maintained with high accuracy. Can do.

(First embodiment)
A first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a circuit configuration of a reference voltage generating circuit according to the first embodiment of the present invention. As shown in FIG. 1, the reference voltage generation circuit according to the first embodiment includes a temperature coefficient correction circuit 1, a reference voltage circuit 2, a differential amplifier circuit 3, a first reference voltage circuit 4, Two reference voltage circuits 5, a first comparison circuit 6, a second comparison circuit 7, a bias unit 8 that generates constant current sources for the first reference voltage circuit 4 and the second reference voltage circuit 5, and The third PN junction has its cathode connected to the ground voltage _VSS and its anode connected to the common connection point of the first resistor R1 and the first PN junction element D1 via the first switch circuit SW1. an element D3, the cathode is connected to the ground voltage V _SS, the anode is connected to the common connection point between the first resistor R1 and the first PN junction element D1 through the second switching circuit SW2 4 PN junction element D4.

Temperature coefficient compensation circuit 1 includes a first PN junction element D1 having a cathode connected to the ground voltage V _SS, a first resistor R1 having one end connected to the anode of the first PN junction element D1, one end Is connected to the other end of the first resistor R1, and the other end is connected to the output terminal BGROUT, and the second resistor R2 is connected to the first resistor R1 and the second resistor R2. and outputs to the differential amplifier 3 a voltage of the point as the first voltage V _1.

The reference voltage circuit 2 includes a second PN junction element D2 having a cathode connected to the ground voltage, a third end connected to the anode of the second PN junction element D2, and the other end connected to the output terminal BGROUT. It consists of resistors R3 Prefecture, and outputs to the differential amplifier 3 a voltage of the common connection point of the second PN junction element D2 and the third resistor R3 as the second voltage V _2.

The differential amplifier circuit 3, the voltage V ₁ from the temperature coefficient compensation circuit 1 are input to the inverting input terminal, a second voltage V ₂ of the reference voltage circuit 2 is input to the non-inverting input terminal, a first by voltages V ₁ and amplifies and outputs a difference voltage between the second voltage V _2, for controlling the output voltage V _o output from the output terminal BGROUT.

The first reference voltage circuit 4 has the same first resistance type (for example, the first resistor R1 and the second resistor R2 of the temperature coefficient correction circuit 1 and the third resistor R of the reference voltage circuit 2). And a second resistor type having the same resistance component as that parasitic in series with the first PN junction element D1 and the second PN junction element D2. For example, when the PN junction element is constituted by a well formed in a semiconductor layer or a semiconductor substrate, a pair is formed by a fifth resistor R5 made of a semiconductor layer or a resistance component of the well), and each resistor R4, R5 is commonly connected one end of the ground voltage V _SS to each other, is applied a predetermined bias current I _B1 at the other end, a first reference voltage V _R4 is a voltage across the fourth resistor R4 of the fifth The second reference voltage V which is the voltage across the resistor R5 _R5 is output.

  2A and 2B show a second PN junction element D2 according to the first embodiment, which is composed of a boundary portion between a diffusion layer and a well formed by a standard CMOS process. The example of a structure is shown. FIG. 2A shows a plan configuration, and FIG. 2B shows a cross-sectional configuration taken along the line IIb-IIb in FIG.

  As shown in FIGS. 2A and 2B, the second PN junction element D2 includes a semiconductor layer 51 composed of a P-type or N-type semiconductor substrate or well, and an upper portion of the semiconductor layer 51. Formed in a region surrounded by the first separation layer 52 and the semiconductor layer 51, and a well 53 having a polarity opposite to that of the semiconductor layer 51, and the well 53 And a first diffusion layer 54 having the same polarity as the well 53 and an inner periphery of the first diffusion layer 54 on the well 53. And a second diffusion layer 56 formed in a region surrounded by the well 53 and the second separation layer 55 and having a polarity opposite to that of the well 53. And a second PN junction element at the boundary between the well 53 and the second diffusion layer 56 2 is formed.

  In the second PN junction element D2 shown in FIGS. 2A and 2B, when the well 53 is P-type, the second diffusion layer 56 is N-type, and the second 53 The direction toward the diffusion layer 56 is the forward direction. Conversely, when the well 53 is N-type, the second diffusion layer 56 is P-type, and the direction from the second diffusion layer 56 toward the well 53 is the forward direction.

The second reference voltage circuit 5 is paired with a sixth resistor R6 made of the first resistance type and a seventh resistor R7 made of the second resistance type, and the resistors R6 and R7 are are commonly connected one end of the ground voltage V _SS to each other, is applied a predetermined bias current I _B2 in the other end, a third reference voltage V _R6 is the voltage across the resistor R6 of the sixth seventh resistor A fourth reference voltage _VR7 that is a voltage across _R7 is output.

In the first comparison circuit 6, the first reference voltage _VR4 is input to the inverting input terminal, the second reference voltage _VR5 is input to the non-inverting input terminal, the two voltages are compared, and the magnitude relationship is established. Corresponding two-bit logic signals C1 and C1B having a predetermined complementary relationship are output from the non-inverting output terminal and the inverting output terminal, respectively.

In the second comparison circuit 7, the third reference voltage _VR6 is input to the inverting input terminal, the fourth reference voltage _VR7 is input to the non-inverting input terminal, the two voltages are compared, and the magnitude relationship is established. Corresponding two-bit logic signals C2 and C2B having a predetermined complementary relationship are output from the non-inverting output terminal and the inverting output terminal, respectively.

  The first switch circuit SW1 is controlled to be conductive or non-conductive based on the logic signal C1B output from the first comparison circuit 6, and the second switch circuit SW2 is output from the second comparison circuit 7. The conduction or non-conduction state is controlled based on the logic signal C2B.

The bias unit 8 that outputs the bias currents I _B1 and I _B2 includes an NMOS transistor 9 having a source connected to the ground voltage _VSS and a gate and drain connected to a diode, a source connected to the power supply voltage V _DD , a gate and The drain is diode-connected, the first PMOS transistor 10 outputs a bias voltage V _{B1 in} cooperation with the NMOS transistor 9, the source is connected to the power supply voltage V _DD , the gate is connected to the bias voltage V _B1, and the bias The first PMOS pair transistors 11 and 12 as constant current sources that output the current I _B1 , the source is connected to the power supply voltage V _DD , the gate is connected to the bias voltage V _B1, and the constant current source that outputs the bias current I _B2 is output. It is composed of second PMOS pair transistors 13 and 14 as current sources. .

  The first PN junction element D1 is configured by n, for example, nine, PN junction elements D5 having the same configuration as the second PN junction element D2 connected in parallel.

  A known circuit can be used for the first comparison circuit 6 and the second comparison circuit 7. For example, each of the comparison circuits 6 and 7 may be a circuit configured with a PMOS differential input type or an NMOS differential input type, and further a comparison circuit having hysteresis characteristics.

  FIG. 3 shows an example of the circuit configuration of the first switch circuit SW1 and the second switch circuit. As shown in FIG. 3, one of the source and drain is connected to the terminal T8, the other of the source and drain is connected to the terminal T9, and the gate is connected to the control terminal T10. Is connected to the terminal T8, the other of the source and drain is connected to the terminal T9, the gate is connected to the control terminal T10 via the inverter 36, and the NMOS transistor 35 and the PMOS transistor 37 constituting the CMOS transfer gate are configured. ing.

  Hereinafter, the operation of the reference voltage generating circuit according to the first embodiment configured as described above will be described with reference to the drawings.

In the first embodiment, the first resistor type constituting the first resistor R1, the second resistor R2, and the third resistor R3, the first PN junction element D1, and the second PN. The fifth PN that constitutes the first PN junction element D1 in the temperature coefficient correction circuit 1 by the relative finished value of the resistance value of the second resistance type having the same configuration as the resistance component parasitic in series with the junction element D2. by dynamically changing the number of parallel connections n the junction elements D5, to suppress fluctuations in the output voltage V _o in the reference voltage generating circuit.

The temperature coefficient correction circuit 1 and the reference voltage circuit 2 according to the first embodiment have the same configuration as the temperature coefficient correction circuit 101 and the reference voltage circuit 102 that constitute the conventional reference voltage generation circuit shown in FIG. If the circuit constants are also the same, the saturation currents of the PN junction elements D1 and D2 are respectively I _s1 and I _s2 , the PN junction currents are I ₁ and I ₂ , and the anode-cathode voltages are V _PN1 , V _PN2, and When the resistance value of each resistor R1~R3 and _{r 1,} r 2, _{r 3,} respectively, for the output voltage _{V o,} is satisfied the relationship of formula (7) described above.

As described above, the fourth resistor R4 configuring the first reference voltage circuit 4 is configured by the same first resistance type as the first to third resistors R1 to R3, and the fifth resistor The device R5 is composed of the same second resistance type as the resistance component parasitic in series with the first and second PN junction elements D1 and D2. Accordingly, the resistance value of the fourth resistor R4 and r _4, and the resistance value of the fifth resistor R5 and r _5, the same bias current I _B1 is applied to the resistor R4, R5 Therefore, the first reference voltage V _R4 is V _R4 = r ₄ · I _B1 , and the second reference voltage V _R5 is V _R5 = r ₅ · I _B1 .

Since and the resistance value r ₅ resistance r _4, r ₄ is a high-resistance by a predetermined ratio (this ratio d _{r4 (high} resistance to finish the reference values of the respective resistors species resistance (Positive value), r ₄ = r ₀ · (1 + d _r4 ), where r ₀ is set to a predetermined resistance value), and r ₅ is a low resistance by a predetermined ratio (this ratio is d _r5 If it is (negative value because of low resistance), r ₅ = r ₀ · (1 + d _r5 )) is set. Accordingly, as long as the relative ratio of the finished value of the resistance value of the second resistance type to the actual first resistance type satisfies (1 + d _r5 ) / (1 + d _r4 ) −1 <0, each reference voltage The magnitude relationship is V _R4 > V _R5 , but when (1 + d _r5 ) / (1 + d _r4 ) −1> 0, the magnitude relationship of each reference voltage becomes V _R4 <V _R5 and the magnitude relationship is inverted.

The logic signal C1B output from the first comparison circuit 6 that compares the first reference voltage V _R4 and the second reference voltage V _R5 is a logic level “1” when V _R4 > V _R5. On the contrary, when V _R4 <V _R5 , the logic level is “0”. The first switch circuit SW1 is composed of the CMOS transfer gate shown in FIG. 3, and is in a conductive state when the logic signal C1B is “1”, and the third PN junction element D3 is the first PN junction. Added in parallel to the element D1. Further, the first switch circuit SW1 becomes non-conductive when the logic signal C1B is “0”, and the third PN junction element D3 connected in parallel with the first PN junction element D1 is electrically connected. Disconnected.

Similar to the first reference voltage circuit 4, the sixth resistor R <b> 6 constituting the second reference voltage circuit 5 is composed of the same first resistance type as the resistors R <b> 1 to R <b> 3. The resistor R7 is composed of the same second resistance type as the resistance component parasitic in series with the first and second PN junction elements D1 and D2. The resistance value of the sixth resistor R6 and r _6, when the resistance value of the seventh resistor R7 and r _7, since the two resistors the same bias current I _B2 is applied, the third reference The voltage V _R6 is V _R6 = r ₆ · I _B2 , and the fourth reference voltage V _R7 is V _R7 = r ₇ · I _B2 .

Here, the resistance value r ₆ and the resistance value r ₇ are as follows: r ₆ is a low resistance by a predetermined ratio with respect to the reference value of the finish of each resistance type (if this ratio is d _r6 (<0), r 6 ₆ = r ₀ · (1 + d _r6 )), and r ₇ is set to a high resistance by a predetermined ratio (r ₇ = r ₀ · (1 + d _r7 )) where this ratio is d _r7 (> 0). ing.

Therefore, as long as the relative ratio of the finished value of the resistance value of the second resistance type to the actual first resistance type satisfies (1 + d _r7 ) / (1 + d _r6 ) −1> 0, The magnitude relationship is V _R6 <V _R7 , but when (1 + d _r7 ) / (1 + d _r6 ) −1 <0, the magnitude relationship of each reference voltage becomes V _R6 > V _R7 and the magnitude relationship is inverted.

The logic signal C2B output from the second comparison circuit 7 that compares the third reference voltage V _R6 and the fourth reference voltage V _R7 is “0” at the logic level when V _R6 <V _{R7. Yes} , when V _R6 > V _R7 , the logic level is “1”. The second switch circuit SW2 is composed of the CMOS transfer gate shown in FIG. 3, and is in a non-conductive state when the logic signal of the logic signal C2B is “0”, and is in parallel with the first PN junction element D1. The fourth PN junction element D4 connected to is electrically disconnected. Further, the second switch circuit SW2 becomes conductive when the logic signal C2B is “1”, and the fourth PN junction element D4 is added in parallel to the first PN junction element D1.

  In summary, when the relative finish value of the resistance value of the second resistance type with respect to the first resistance type becomes higher than a predetermined ratio, the third PN junction element D1 connected in parallel with the first PN junction element D1 is used. The PN junction element D3 is cut. On the other hand, when the relative finished value of the resistance value of the second resistance type with respect to the first resistance type becomes lower than a predetermined ratio, the fourth PN junction element D4 is parallel to the first PN junction element D1. Connected to. That is, assuming that the PN junction elements D3 and D4 have the same configuration as that of the second PN junction element D2, this series of operations increases or decreases the number n of parallel connections of the PN junction elements D5 in Equation (7). It will be.

  For example, in the first embodiment, when the parallel connection number n of the PN junction elements D5 constituting the first PN junction element D1 is 9, the resistance value of the second resistance type with respect to the first resistance type When the ratio of the relative finished values of the first and second PN junction elements becomes higher than a predetermined ratio, the first PN junction element D1 to the third PN junction element D3 are electrically disconnected from n = 10 to n = 9. When the ratio is lower than the predetermined ratio, the third PN junction element D3 and the fourth PN junction element D4 are added to the first PN junction element D1, so that n = 10 to n = 11. That is, one increase / decrease with respect to n = 10 of the number of parallel connections. In this case, the second term on the right side of Equation (7) is LN (9) / LN (10) -1 = approximately −4.6% when n = 9 with respect to n = 10, and LN when n = 11. (11) / LN (10) -1 = shifted by about + 4.1%.

As in the conventional reference voltage generation circuit shown in FIG. 7, the circuit is optimized by setting the resistance value of the first resistor R1 to r ₁ = 1 KΩ and the resistance value of the resistance component of the well 53 to r _w = 100Ω. If the variation widths of the first resistance type and the second resistance type are both ± 20%, the variations of the first resistance type and the second resistance type are −20% and + 20%, respectively. Sometimes, the second term on the right side of equation (7) rises the most and varies by about + 5.9%, and when the variation of the first resistance type and the second resistance type is + 20% and −20%, respectively. The second term on the right-hand side of equation (7) decreases the most and varies by about −3.6%. But here the fourth _{d r4} to + 10% of the resistor R4, the _{d r5} of the fifth resistor R5 is set to -10%, _d r6 = -10% of the resistor R6 of the sixth, seventh When the _dr7 of the resistor R7 is set to + 10%, when the ratio of the finished value of the resistance value of the second resistance type to the first resistance type deviates from each setting, the first PN junction element Since the number n of parallel connections in D1 increases or decreases, the increase in the second term on the right side of Equation (7) is suppressed to about + 2.5%, and the decrease is suppressed to about -2.0%, approximately -2.0%. be able to.

As described above, according to the first embodiment, the third PN junction element D3 and the fourth PN junction element D4 having the same configuration as the PN junction element D5 constituting the first PN junction element D1 are replaced with the first PN. The junction element D1 is provided so as to be electrically cutable, and further, the resistance component variation generated in the second resistance type according to the ratio of the finished value of the resistance value of the second resistance type to the first resistance type. Can be compensated. Thus, the variation of the output voltage V _o in the reference voltage generating circuit can be suppressed highly accurately and extensively.

In the first embodiment, the number of increase / decrease stages of the PN junction elements connected in parallel to the first PN junction element D1 is one step, but each increase and decrease is configured by a plurality of stages. the second to the resistance type finish reference resistor species resistance by setting two or more stages, it is possible to more accurately and wide variation in output voltage V _o.

(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

  FIG. 4 shows a circuit configuration of a reference voltage generating circuit according to the second embodiment of the present invention. In FIG. 4, the same components as those shown in FIG.

  In the first embodiment, in order to dynamically compensate for the variation in the ratio of the finished value of the resistance value of the second resistance type (for example, diffusion layer) to the first resistance type (for example, polysilicon), It was set as the structure which can change the parallel connection number n of the some PN junction element which comprises the 1st PN junction element D1.

  On the other hand, as shown in FIG. 4, the reference voltage generation circuit according to the second embodiment is replaced with a configuration in which the temperature coefficient correction circuit 39 can change the number n of parallel connections of a plurality of PN junction elements. The resistor array 38 capable of dynamically changing the resistance value of the first resistor R1 is provided.

Specifically, the resistor string 38 instead of the first resistor R1 includes an eighth resistor R8, a ninth resistor R9, and a tenth resistor R10 connected in series. The terminal opposite to the ninth resistor R9 in R8 is connected to the anode of the first PN junction element D1, and the terminal opposite to the ninth resistor R9 in the tenth resistor R10 is the second resistor. Connected to the device R2. Accordingly, the voltage of the common connection point between the second resistor R2 and the resistor string 38 is output as the third voltage V _3.

  In the resistor string 38, a third switch circuit SW3 that receives the logic signal C1B from the first comparison circuit 6 is provided at both terminals of the eighth resistor R8, and both ends of the ninth resistor R9. The child is provided with a fourth switch circuit SW4 that receives the logic signal C2B from the second comparison circuit 7. Here, the configuration of each of the switch circuits SW3 and SW4 is the same as that of the switch circuit of FIG. 3 shown in the first embodiment.

  In addition, the 1st PN junction element D1 which concerns on 2nd Embodiment is comprised by connecting n pieces which take the same structure as the 2nd PN junction element D2, for example, 10 PN junction elements D5 in parallel. .

  The operation of the reference voltage generating circuit according to the second embodiment configured as described above will be described below with reference to the drawings.

In the second embodiment, the resistor array 38, the first resistor R2 and the third resistor R3 constituting the third resistor R3, the first PN junction element D1, and the second PN junction element the relative finish of the second resistor species of the resistance value of the parasitic resistance component of the same in series in D2, the dynamic resistance value r ₁ of the resistor string 38 in the temperature correction coefficient correction circuit 39 shown in FIG. 4 by changing the, suppress the variation of the output voltage V _o in the reference voltage generating circuit.

  The operations of the reference voltage generation circuit 2, the first reference voltage circuit 4, the second reference voltage circuit 5, the first comparison circuit 6, and the second comparison circuit 7 are the same as those in the first embodiment.

  The third switch circuit SW3 becomes conductive when the logic signal C1B from the first comparison circuit 6 is “1”, and is connected in series to the tenth resistor R10. Resistor R8 is shorted. Conversely, when the logic signal C1B is “0”, the third switch circuit SW3 is in a non-conductive state, and the eighth resistor R8 is connected in series to the tenth resistor R10.

  The fourth switch circuit SW4 becomes non-conductive when the logic signal C2B from the second comparison circuit 7 is “0”, and the ninth resistor R9 is connected in series to the tenth resistor R10. Is done. On the other hand, when the logic signal C2B is “1”, the fourth switch circuit SW3 becomes conductive, and the ninth resistor R9 connected in series to the tenth resistor R10 is short-circuited.

In summary, when the relative finished value of the resistance value of the second resistance type with respect to the first resistance type becomes higher than a predetermined ratio, the eighth resistor R8 is connected in series with the tenth resistor R10. Is done. On the other hand, when the relative finish value of the resistance value of the second resistance type with respect to the first resistance type becomes lower than a predetermined ratio, the ninth resistance connected in series to the tenth resistor R10. R9 is short-circuited. That is, by this series of operations, the resistance value r1 of the _first resistor R1 in the equation (7) is increased or decreased.

For example, when the circuit is optimized with the resistance value r ₁ = 1 KΩ of the resistor array 38 and the resistance value of the resistance component of the well 53 set to r _w = 100Ω, as described above, Assuming that the variation widths of the resistance type and the second resistance type are both ± 20%, when the variations of the first resistance type and the second resistance type are −20% and + 20%, respectively, The second term rises the most and fluctuates by about + 5.9%, and when the fluctuations of the first resistance type and the second resistance type are + 20% and −20%, respectively, it decreases the most by about −3.6%. It will fluctuate. However, here, _dr4 of the fourth resistor R4, _dr5 of the fifth resistor R5, _dr6 of the sixth resistor R6, and _dr7 of the seventh resistor R7 are _expressed by the equation (7). Set to a ratio corresponding to about one third of the positive and negative maximum fluctuation range of the second term on the right side (for example, _dr4 = + 6%, _dr5 = -6%, _dr6 = -7%, _dr7 = + 7% And the resistance value r _{8 of} the eighth resistor R8 constituting the resistor string 38 is about 0.32 KΩ, the resistance value r _{9 of} the ninth resistor R9 is about 0.22 KΩ, and the tenth resistance. When the resistance value r ₁₀ of the resistor R10 is set to about 0.78 KΩ (actually, the on-resistances of the third and fourth switch circuits SW3 and SW4 are taken into consideration), the second resistance for the first resistance type since the ratio of the species of the finished value when deviated from the set value, the resistance value r ₁ of the resistor string 38 is increased or decreased, their In each of the expressions (7), the increase in the second term on the right side can be suppressed to about + 1.7%, and the decrease can be suppressed to about −1/3, approximately −1/3.

Thus, according to the second embodiment, the resistance value r ₁ of the resistor string 38 which constitutes the temperature coefficient compensation circuit 39 and can be dynamically changed, furthermore, the second resistor species to the first resistor species It is possible to compensate for the variation in resistance value occurring in the first resistance type according to the ratio of the finished resistance values. From this, the variation of the output voltage V _o in the reference voltage generating circuit can be suppressed highly accurately and extensively.

In the second embodiment, the number of stages of increase / decrease of the resistors connected in series to the resistor string 38 is one stage. by setting 2 of a finish reference resistor species resistance to two or more stages, it is possible to vary the further high accuracy and wide range of output voltage V _o.

In the second embodiment, the resistance value r ₁ in the resistor string 38 constituting the temperature coefficient correction circuit 39 is dynamically changeable. However, the second resistor R 2 or the reference voltage circuit 2 is used. It is good also as a structure which can change the resistance value of 3rd resistor R3 which comprises these, and it is good also as a structure which combined these.

(Third embodiment)
Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.

  FIG. 5 shows a circuit configuration of a reference voltage generating circuit according to the third embodiment of the present invention. In FIG. 5, the same components as those shown in FIG.

  In the second embodiment, in order to dynamically compensate for the variation in the ratio of the finished value of the resistance value of the second resistance type (for example, diffusion layer) to the first resistance type (for example, polysilicon), For example, the resistance value of the first resistor R1 constituting the temperature coefficient correction circuit can be changed by using the resistor string 38.

  In contrast, in the reference voltage generation circuit according to the third embodiment, a resistor is provided in series with the second PN junction element constituting the reference voltage circuit, and the resistance value of the resistor added in series is 3 By configuring as above, the finished value of the resistance component parasitic on the second PN junction element can be dynamically changed.

  Specifically, as shown in FIG. 5, the reference voltage generation circuit according to the third embodiment includes a first reference voltage circuit 40, a second reference voltage circuit 41, and a third reference that are connected in parallel to each other. A logic signal from the voltage circuit 42 and the first comparison circuit 6 and the second comparison circuit 7 is received, and the switching is controlled by the received logic signal to select any one of a plurality of reference voltage circuits A fifth switch circuit SW5, a sixth switch circuit SW6, and a seventh switch circuit SW7.

The first reference voltage circuit 40 includes a second PN junction element D2 having a cathode connected to the ground voltage V _SS, and the resistor R11 of the first 11 of which one end is connected to the anode of the second PN junction element D2 The third resistor R3 has one end connected to the eleventh resistor R11 and the other end connected to the output terminal BGROUT, and the eleventh resistor R11 and the third resistor R3 are connected in common. and it outputs the voltage at point a voltage V ₆ of the sixth.

The second reference voltage circuit 41 includes a second PN junction element D2 having a cathode connected to the ground voltage V _SS, and a twelfth resistor R12 of which one end is connected to the anode of the second PN junction element D2 The third resistor R3 has one end connected to the twelfth resistor R12 and the other end connected to the output terminal BGROUT. The twelfth resistor R12 and the third resistor R3 are connected in common. and it outputs the voltage at point a voltage V ₇ of the seventh.

Third reference voltage circuit 42 includes a second PN junction element D2 having a cathode connected to the ground voltage V _SS, a thirteenth resistor R13, one end of which is connected to the anode of the second PN junction element D2 The third resistor R3 has one end connected to the thirteenth resistor R13 and the other end connected to the output terminal BGROUT. The common connection between the thirteenth resistor R13 and the third resistor R3 and it outputs the voltage at point a voltage V ₈ of the eighth.

  The logic circuit 43 receives the logic signals C1 and C1B output from the first comparison circuit 6 and the logic signals C2 and C2B output from the second comparison circuit 7, and performs a predetermined logic operation as a first input. Any one of the selection signal S1, the second selection signal S2, and the third selection signal S3 is output.

Fifth switch circuit SW5 is inputted from one terminal voltage V ₆ of the sixth conduction / non-conduction state based on the first selection signal S1 is controlled, the sixth voltage during conduction from another terminal V ₆ is input to the non-inverting input terminal of the differential amplifier 3 as the ninth voltage V ₉ .

Switching circuit SW6 sixth is input a seventh voltage V ₇ from one terminal, the second selection conduction / non-conduction state based on the signal S2 is controlled, a seventh voltage from the other terminal at the time of conducting V ₇ is input to the non-inverting input terminal of the differential amplifier 3 as the ninth voltage V ₉ .

The seventh switch circuit SW7 for is inputted from one terminal of an eighth voltage V _8, a third selection signal S3 Based on conduction / non-conduction state is controlled, eighth voltage during conduction from another terminal V ₈ is input to the non-inverting input terminal of the differential amplifier 3 as the ninth voltage V ₉ .

The bias unit 8 that outputs the bias currents I _B1 and I _B2 has the same configuration as that of the first embodiment shown in FIG. Further, the configurations of the fifth, sixth and seventh switch circuits SW5, SW6 and SW7 are the same as the configuration of FIG. 3 shown in the first embodiment.

  FIG. 6 shows an example of the circuit configuration of the logic circuit 43. As shown in FIG. 6, the logic circuit 43 includes, for example, five two-input NAND gates 44 to 48 and two inverter gates 49 and 50.

  The two-input NAND gates 44 to 47 receive the logic signals C1, C1B, C2, and C2B output from the first comparison circuit 6 and the second comparison circuit 7 shown in FIG. A NAND operation is performed on the 2-bit information of C1 and C2 in the truth table, that is, four logical levels.

2-input NAND gate 48 receives an output signal from the 2-input NAND gates 44 and 45, performs a NAND operation corresponding to S1 in the truth table, "1" level and the voltage _{V 6} of the sixth The first selection signal S1 is output.

The inverter gate 49 receives the output signals from the 2-input NAND gate 46 performs a negative logic operation corresponding to the S2 of the truth table, a second selection of the seventh "1" level with respect to the voltage V ₇ of The signal S2 is output.

The inverter gate 50 receives the output signals from the 2-input NAND gate 47 performs a negative logic operation corresponding to S3 in the truth table, a third selection of the "1" level with respect to the voltage V ₈ of the eighth The signal S3 is output.

  The operation of the reference voltage generating circuit according to the third embodiment configured as described above will be described below with reference to the drawings.

In the third embodiment, the first resistor type constituting the first resistor R1, the second resistor R2, and the third resistor R3, the first PN junction element D1, and the second PN. An eleventh resistor R11 and a twelfth resistor for the second PN junction element D2, respectively, depending on the relative finished value of the resistance value of the second resistance type having the same configuration as the resistance component parasitic in series with the junction element D2. By selectively applying any one of the first to third reference voltage circuits 40, 41, 42 in which the resistor R12 and the thirteenth resistor R13 are connected in series, a reference voltage generation circuit The fluctuation of the output voltage V _o at is suppressed.

  Here, as described above, with respect to the resistance value of the eleventh resistor R11, the resistance value of the twelfth resistor R12 is set to a low resistance, and the resistance value of the thirteenth resistor R13 is set to a high resistance. Has been.

  The operations of the temperature coefficient correction circuit 1, the first reference voltage circuit 4, the second reference voltage circuit 5, the first comparison circuit 6, and the second comparison circuit 7 are the same as those in the first embodiment.

  The logic signals C1, C1B, C2, and C2B output from the first and second comparison circuits 6 and 7, respectively, are input to the logic circuit 43 shown in FIG. The logic circuit 43 outputs the first to third selection signals S1 to S3 to the switch circuits SW5, SW6, and SW7 according to the truth table shown in [Table 1].

  There are four combinations of logic levels of the logic signals C1 and C2, as shown in [Table 1], and the first selection signal S1 is a relative value of the resistance value of the second resistance type with respect to the first resistance type. When the ratio does not deviate from the set values of both the first reference voltage circuit 4 and the second reference voltage circuit 5, the logic level “1” is output, and the second selection signal S2 is the first resistor When the relative finish of the resistance value of the second resistance type with respect to the seed becomes higher than a predetermined ratio, the logic level “1” is output, and the third selection signal S3 is the first selection signal S3. When the relative finish of the resistance value of the resistance type 2 becomes lower than a predetermined ratio, the logic level “1” is output. In other cases, the logic level “0” is output except in the following cases.

That is, when C1 = "1" and C2 = "0", the logic level of the first selection signal S1 is "1". Fifth switch circuit SW5 is rendered conductive when the first selection signal S1 is "1" to the logic circuit 43 outputs a voltage V ₆ of the sixth first reference voltage circuit 40 outputs and outputs as a voltage _{V 9} of the ninth. Switching circuit SW6 sixth is rendered conductive when the second selection signal S2 is "1" the logic circuit 43 outputs, the seventh voltage V ₇ which second reference voltage circuit 41 outputs and outputs as a voltage _{V 9} of the ninth. The seventh switch circuit SW7 for is rendered conductive when the third selection signal S3 is "1" to the logic circuit 43 outputs a voltage V ₈ eighth third reference voltage circuit 42 outputs and outputs as a voltage _{V 9} of the ninth.

  In summary, when the relative finished value of the resistance value of the second resistance type with respect to the first resistance type becomes higher than a predetermined ratio, the second PN junction element D2 is connected in series. The resistance value decreases. On the other hand, when the relative finished value of the resistance value of the second resistance type with respect to the first resistance type becomes lower than a predetermined ratio, the second PN junction element D2 is added in series and connected. The resistance value is increased. That is, by this series of operations, the resistance value of the resistance component parasitic in series with the second PN junction element D2 is increased or decreased equivalently.

For example, as in the description so far, the circuit is optimal with the resistance value r _{1 of the first} resistor R ₁ = 1 KΩ and the sum of the resistance component of the well 53 and the resistance value of the eleventh resistor R 11 as r _w = 100Ω. If the variation widths of the first and second resistance types are both ± 20%, the variations of the first resistance type and the second resistance type are −20% and + 20%, respectively. Sometimes the second term on the right side of equation (7) rises the most and fluctuates by about + 5.9%, and decreases most when the fluctuations of the first resistance type and the second resistance type are + 20% and -20%, respectively. As a result, it varies by about -3.6%. However, here, _dr4 of the fourth resistor R4, _dr5 of the fifth resistor R5, _dr6 of the sixth resistor R6, and _dr7 of the seventh resistor R7 are _expressed by the equation (7). Set to a ratio corresponding to about one third of the positive and negative maximum fluctuation range of the second term on the right side (for example, _dr4 = + 6%, _dr5 = -6%, _dr6 = -7%, _dr7 = + 7% In addition, the twelfth resistor is set to −24% and + 28% with respect to the sum of the resistance component parasitic in series with the second PN junction element D2 and the resistance value of the eleventh resistor R11, respectively. When the resistance values of the resistor R12 and the thirteenth resistor R13 are set, when the finished ratio of the second resistance type to the first resistance type is out of the setting, the second PN junction element D2 Since the resistance value of the series resistance component is increased or decreased, the rise of the second term on the right side of Equation (7) 1.7% of the decrease and the degree of -1.6%, can be suppressed to about one-third.

Thus, according to the third embodiment, one of the three reference voltage circuits 40 to 42 each including the second PN junction element D2 and having different resistance values added to the second PN junction elements. One of them is dynamically selected, and further compensates for variations in the resistance value generated in the second resistance type according to the ratio of the finished value of the resistance value of the second resistance type to the first resistance type. Is possible. From this, the variation of the output voltage V _o in the reference voltage generating circuit can be suppressed highly accurately and extensively.

In the third embodiment, the resistance value of the resistor connected in series to the second PN junction element D2 is increased and decreased by one stage, but each of the increase and decrease is configured by a plurality of stages. by setting one second to the resistance type resistor species finish reference resistance value in two or more stages, it is possible to more accurately and wide variation in output voltage V _o.

  The reference voltage generation circuit according to the present invention includes, for example, a reference voltage generation circuit according to a ratio of a resistance component parasitic in series to a PN junction element constituting a reference voltage circuit with respect to a resistance value of a resistor constituting a temperature coefficient correction circuit. This circuit constant can be dynamically changed to maintain a voltage characteristic with a constant output voltage with high accuracy, and is particularly useful for a reference voltage generating circuit for generating a reference voltage used in an analog circuit.

1 is a circuit diagram showing a reference voltage generating circuit according to a first embodiment of the present invention. (A) is the 2nd PN junction element which comprises the reference voltage circuit which concerns on the 1st Embodiment of this invention, Comprising: The diffusion layer formed by a standard CMOS process, and the PN junction element formed in a well boundary part It is a top view which shows typically the structural example. (B) is sectional drawing in the IIb-IIb line | wire of (a). 1 is a circuit diagram showing a switch circuit constituting a reference voltage generation circuit according to a first embodiment of the present invention. It is a circuit diagram which shows the reference voltage generation circuit which concerns on the 2nd Embodiment of this invention. It is a circuit diagram which shows the reference voltage generation circuit which concerns on the 3rd Embodiment of this invention. It is a circuit diagram which shows an example of the logic circuit which comprises the reference voltage generation circuit which concerns on the 3rd Embodiment of this invention. It is a circuit diagram which shows the conventional reference voltage generation circuit. It is a top view which shows the example of a structure of the PN junction element which comprises the diffusion layer and well well part which comprise the conventional reference voltage generation circuit and are formed of a standard CMOS process. It is sectional drawing in the IX-IX line of FIG. It is a graph which shows the example of a characteristic in 27 degreeC of the forward current with respect to the forward voltage of the PN junction element which consists of the diffused layer formed by the standard CMOS process in the conventional reference voltage generation circuit, and a well boundary part.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Temperature coefficient correction circuit 2 1st reference voltage circuit 3 Differential amplifier circuit 4 1st reference voltage circuit 5 2nd reference voltage circuit 6 1st comparison circuit 7 2nd comparison circuit 8 Bias part 9 NMOS transistor 10 First PMOS transistor 11 First PMOS pair transistor 12 First PMOS pair transistor 13 Second PMOS pair transistor 14 Third PMOS pair transistor 35 NMOS transistor 36 Inverter 37 PMOS transistor 38 Resistor string 39 Temperature coefficient correction circuit 40 First reference voltage circuit 41 Second reference voltage circuit 42 Third reference voltage circuit 43 Logic circuit 51 Semiconductor layer 52 First separation layer 53 Well 54 First diffusion layer 55 Second separation layer 56 Second Diffusion layer D1 First PN junction element D2 Second PN junction element D3 Third PN junction element D4 fourth PN junction element D5 PN junction elements R1~R13 first through 13 resistor SW1~SW7 first through seventh switching circuit

Claims (9)

A temperature coefficient correction circuit including a first resistor and a second resistor connected in series, and a first PN junction element connected in the forward direction with the first resistor;
A third resistor having one end connected to the output terminal and the second resistor, and a second PN junction element connected to the third resistor in the forward direction and formed in the first diffusion layer of the substrate A reference voltage circuit including:
Amplifying a difference voltage between a first voltage at a connection portion of the first resistor and the second resistor and a second voltage at a connection portion of the third resistor and the second PN junction element; A differential amplifier circuit for controlling the output voltage of the output terminal;
A fourth resistor connected to a constant current source and having the same composition as the first resistor, and a fifth resistor comprising a second diffusion layer connected to the constant current source and formed on the substrate A first reference voltage circuit including:
A first comparison circuit for comparing a difference voltage between a voltage generated by the fourth resistor and a voltage generated by the fifth resistor in the first reference voltage circuit;
A third PN junction element connected in parallel to the first PN junction element via a first switch circuit;
The reference voltage generation circuit according to claim 1, wherein the first switch circuit is opened and closed based on a comparison result of the first comparison circuit.   The polarity of the first reference voltage circuit is reversed when the ratio of the resistance value of the fifth resistor to the resistance value of the fourth resistor is higher than a predetermined value or lower than a predetermined value. The reference voltage generation circuit according to claim 1, wherein a differential voltage generated by cooperation of the fourth resistor and the fifth resistor is output as a first reference voltage. A seventh resistor comprising a sixth resistor connected to the constant current source and having the same composition as the first resistor, and a third diffusion layer connected to the constant current source and formed on the substrate A second reference voltage circuit comprising:
A second comparison circuit for comparing a difference voltage between a voltage generated by the sixth resistor and a voltage generated by the seventh resistor in the second reference voltage circuit;
A fourth PN junction element connected in parallel to the first PN junction element via a second switch circuit;
The reference voltage generating circuit according to claim 1, wherein the second switch circuit is opened and closed based on a comparison result of the second comparison circuit. The first reference voltage circuit includes a fourth resistor whose polarity is inverted when a ratio value of a resistance value of the fifth resistor to a resistance value of the fourth resistor is higher than a predetermined value. A differential voltage generated by the cooperation of the resistor and the fifth resistor is output as a first reference voltage;
The second reference voltage circuit includes the sixth resistor whose polarity is reversed when a ratio value of a resistance value of the seventh resistor to a resistance value of the sixth resistor is lower than the predetermined value. 4. The reference voltage generation circuit according to claim 3, wherein a differential voltage generated by the cooperation of a resistor and the seventh resistor is output as a second reference voltage. 5.   5. The first PN junction element includes a plurality of PN junction elements having the same configuration as that of the second PN junction element and connected in parallel. 6. Reference voltage generator circuit. A temperature coefficient correction circuit including a first resistor, a second resistor, and a third resistor connected in series, and a first PN junction element connected in the forward direction with the first resistor;
A fourth resistor having one end connected to the output terminal and the third resistor, and a second PN junction element connected to the fourth resistor in the forward direction and formed in the first diffusion layer of the substrate A reference voltage circuit including:
Amplifying a difference voltage between a first voltage at a connection portion of the second resistor and the third resistor and a second voltage at a connection portion of the fourth resistor and the second PN junction element; A differential amplifier circuit for controlling the output voltage of the output terminal;
A fifth resistor connected to a constant current source and having the same composition as the second resistor; a sixth resistor connected to the constant current source and formed of a second diffusion layer formed on the substrate; A first reference voltage circuit comprising:
A first comparison circuit for comparing a difference voltage between a voltage generated by the fifth resistor and a voltage generated by the sixth resistor in the first reference voltage circuit;
And a first switch circuit connected in parallel to the first resistor and opened and closed based on a comparison result of the first comparison circuit. An eighth resistor comprising a seventh resistor connected to the constant current source and having the same composition as the second resistor, and a third diffusion layer connected to the constant current source and formed on the substrate A second reference voltage circuit comprising:
A second comparison circuit for comparing a difference voltage between a voltage generated by the seventh resistor and a voltage generated by the eighth resistor in the second reference voltage circuit;
A ninth resistor connected in series between the first resistor and the second resistor in the temperature coefficient correction circuit;
The reference voltage according to claim 6, further comprising a second switch circuit connected in parallel to the ninth resistor and opened and closed based on a result of the second comparison circuit. Generation circuit. A temperature coefficient correction circuit including a first resistor and a second resistor connected in series, and a first PN junction element connected in the forward direction with the first resistor;
A third resistor having one end connected to the output terminal and the second resistor, a fourth resistor connected in series to the third resistor, and a forward connection to the fourth resistor And a first reference voltage circuit including a second PN junction element formed in the first diffusion layer of the substrate,
A fifth resistor having one end connected to the output terminal; a sixth resistor connected in series to the fifth resistor; and a forward connection to the sixth resistor and formed on the substrate. A second reference voltage circuit including a third PN junction element formed in the second diffusion layer;
The first voltage at the connection of the first resistor and the second resistor, and the connection of the third resistor and the fourth resistor in the first reference voltage circuit or the second reference A differential amplifier circuit for amplifying a difference voltage from the second voltage of the connection portion of the fifth resistor and the sixth resistor in the voltage circuit to control the output voltage of the output terminal;
A seventh resistor connected to a constant current source and having the same composition as the first resistor; and an eighth resistor comprising a third diffusion layer connected to the constant current source and formed on the substrate A first reference voltage circuit including:
A first comparison circuit for comparing a difference voltage between a voltage generated by the seventh resistor and a voltage generated by the eighth resistor in the first reference voltage circuit;
A logic circuit that selects one of the first reference voltage circuit and the second reference voltage circuit by performing a logical operation based on a comparison result of the first comparison circuit. A characteristic reference voltage generation circuit. A ninth resistor connected to the output terminal; a tenth resistor connected in series with the ninth resistor; and a fourth diffusion of the substrate connected in a forward direction with the tenth resistor. A third reference voltage circuit including a fourth PN junction element formed in the layer;
An eleventh resistor connected to a constant current source and having the same composition as the first resistor, and a twelfth resistor consisting of a fifth diffusion layer connected to the constant current source and formed on the substrate A second reference voltage circuit including:
A second comparison circuit for comparing a voltage difference between the voltage generated by the eleventh resistor and the voltage generated by the twelfth resistor in the second reference voltage circuit;
The logic circuit performs a logical operation based on a comparison result of the first comparison circuit and the second comparison circuit, thereby causing the first reference voltage circuit, the second reference voltage circuit, and the third reference voltage to be performed. 9. The reference voltage generating circuit according to claim 8, wherein any one of the circuits is selected.

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