JP6802644B2 - Regulated power supply circuit - Google Patents

Description

The present invention relates to a regulated power supply circuit capable of supplying a regulated output voltage.

In the regulated power supply circuit, when the current supplied to the load is small, reducing the current consumption of the regulated power supply circuit is an important factor for extending the operating time of the battery-powered equipment and the like. As a regulated power supply circuit for reducing current consumption, for example, there is one described in Patent Document 1.

FIG. 5 is a circuit diagram showing the configuration of the conventional regulated power supply circuit 100 described in Patent Document 1. In the figure, the regulated power supply circuit 100 is supplied with a power supply voltage VDD for operation from the first voltage source V1. Further, in the regulated power supply circuit 100, the reference voltage VREF is supplied from the second voltage source V2. The output voltage VOUT of the regulated power supply circuit 100 is output from the VOUT terminal. The transistors MN1 to MN6 constituting the regulated power supply circuit 100 are N-channel MOSFETs (Metal-Oxide-Semiconductor Dutor / Field-Effect-Transistor), respectively. Further, the transistors MP1 to MP4 constituting the regulated power supply circuit 100 are P-channel MOSFETs, respectively.

The transistor MP1 is inserted between the first voltage source V1 and the VOUT terminal to control the current supplied to the VOUT terminal. The transistors MN1 and MN2 and the transistors MP3 and MP4 form a differential amplification unit DAMP, and the reference voltage VREF of the second voltage source V2 is applied to the gate of the transistor MN1 which is one input element of the differential amplification unit DAMP. A voltage obtained by dividing the output voltage VOUT at the VOUT terminal by the resistance value ratio of the resistance elements R1 and R2 is applied to the gate of the transistor MN2 which is the other input element. A capacitor C2 for phase compensation is connected between the connection points of the resistance elements R1 and R2 and the VOUT terminal.

The connection point between the drain of the transistor MN1 and the drain of the transistor MP4 constituting the differential amplification unit DAMP corresponds to the output of the differential amplification unit DAMP, and controls the gate voltage of the transistor MP1. The output voltage VOUT is controlled to the voltage represented by the equation (1) by the negative feedback action via the differential amplification unit DAMP.

R1: Resistance value of resistance element R1 R2: Resistance value of resistance element R2 VOUT: Output voltage at VOUT terminal VREF: Reference voltage of second voltage source V2

The transistor MN4 is an element for controlling the tail current of the differential amplification unit DAMP, and constitutes a current mirror circuit together with the transistor MN3 to sink a current proportional to the current source IB1 from the transistors MN1 and MN2. Further, in addition to the drain current of the transistor MN4, the drain of the transistor MN6 that flows a drain current proportional to the drain current of the transistor MP2 is connected to each source of the transistors MN1 and MN2.

Further, by increasing or decreasing the drain current of the transistor MN6, which is the tail current of the differential amplification unit DAMP, in proportion to the load current, the current consumption of the stabilized power supply circuit 100 is reduced when the load current is small, and the load is increased. In a situation where a large amount of current is supplied, by increasing the tail current of the differential amplification unit DAMP, the current for driving the gate voltage of the transistor MP1 is increased, and the output voltage is increased even when the load current suddenly fluctuates. It is possible to quickly control to a constant value.

By the way, as a problem peculiar to the stabilized power supply circuit 100 having such a circuit configuration, there is a problem of circuit phase compensation. Normally, in the negative feedback path of such a circuit, the drain current of the transistor MP1 raises the output voltage VOUT at the VOUT terminal, the output voltage VOUT is divided by the resistance elements R1 and R2, and the input of the differential amplifier DAMP is input. It is applied to the gate of the transistor MN2 as the gate voltage of the transistor MN2 which is an element. When the gate voltage of the transistor MN2 rises, the drain current of the transistor MN2 increases, and this drain current is mirrored by the transistors MP3 and MP4 constituting the current mirror circuit in the differential amplification unit DAMP to raise the gate voltage of the transistor MP1. This reduces the output current and controls the output voltage.

In addition to such a negative feedback path, in the stabilized power supply circuit 100 of the type that increases the tail current, the tail current of the differential amplification unit DAMP increases according to the drain current of the transistor MP1 that controls the output current. , The drain current of the transistor MN5 increases the drain current of the transistors MN1 and MN2, and a feedback path acting on the node voltage of the gate of the transistor MP1 is formed. There is no problem in the feedback of this path if the drain currents of the transistors MN1 and MN2 increase at exactly the same ratio, but if there is a difference, it can be either negative feedback or positive feedback.

Since the gain due to the feedback of the path that increases the tail current is usually smaller than the gain of the feedback from the VOUT terminal, there is no problem in controlling the output voltage VOUT. However, if the current amplification factor of the transistors MN6 and MN5 in the current mirror circuit is large, or if the difference in transconductance between the transistors MN1 and MN2 is large, the output voltage VOUT of the regulated power supply circuit 100 can be controlled. Affect.

Normally, the regulated power supply circuit 100 as shown in FIG. 5 has a VOUT terminal for the purpose of phase compensation for smoothing fluctuations in the output voltage due to changes in the load current and preventing the output voltage VOUT from oscillating. A capacitor CL of about several μF is added between the and GND. By adding this capacitor CL, the gain of feedback via the VOUT terminal is attenuated at the frequency of fp1 in the equation (2) as shown in FIG.

fp1: Frequency of pole generated at VOUT terminal RL: Resistance value of load resistance RL CL: Capacitor value of capacitor CL

This frequency fp1 becomes lower as the capacitance value CL of the capacitor CL of the regulated power supply circuit 100 and the resistance value RL of the load resistance RL are larger. Therefore, as shown by the dotted line in the frequency characteristic diagram of the gain shown in FIG. 6, when the capacitance value CL of the capacitor CL is increased, the feedback amount due to the tail current increases from the output voltage VOUT at a certain frequency fx or higher. A region that exceeds the feedback amount of is generated. If the feedback due to the tail current is operating as negative feedback, there is no particular problem even in this frequency range or higher, but in the positive feedback state, due to the characteristics of the transistors MN1 and MN2 that are the input elements of the differential amplification unit DAMP. The phase of the feedback in the entire stabilized power supply circuit 100 fluctuates greatly at this frequency due to variations in the positive feedback, and the output voltage VOUT oscillates or rings.

In order to solve this problem, the method described in Patent Document 2 has been devised. FIG. 7 is a circuit diagram showing the configuration of the regulated power supply circuit 110 described in Patent Document 2. As shown in the figure, by adding the resistance element R3 and the capacitor C1 between the gates of the transistors MN5 and MN6, the feedback amount due to the tail current is attenuated at a high frequency and exceeds the feedback amount from the output voltage VOUT. It is preventing.

Japanese Unexamined Patent Publication No. 3-158912 Japanese Patent No. 4527592

However, also in the regulated power supply circuit 110 described in Patent Document 2, when the capacitance value CL of the capacitor CL is further increased, the capacitance value C1 of the capacitor C1 also needs to be increased, and this capacitor is placed on the chip of the semiconductor integrated circuit. When forming C1, there is a problem that a very large area is required.

The present invention has been made in view of the above circumstances, and solves the problem of phase compensation of a regulated power supply circuit having a function of changing the tail current of the differential amplification unit according to the output current by a method without using a capacitor. It is an object of the present invention to provide a regulated power supply circuit that can be realized with a smaller chip area than a conventional regulated power supply circuit having a low current consumption.

The present invention is a stabilized power supply circuit that outputs a predetermined voltage from an output terminal according to a reference voltage, and supplies a current to the first transistor and the second transistor to which the sources are connected to each other and the output terminal. The gate voltage of the third transistor is controlled by the difference between the drain currents of the first transistor and the second transistor, including the third transistor to be supplied, the first transistor and the second transistor. To the differential amplification unit, the first current source that changes the source currents of the first transistor and the second transistor according to the drain current of the third transistor, and the drain of the second transistor. connected, the second current source a first current proportional to the current of the current source is flow, wherein the said reference voltage is applied to the gate of the first transistor, a gate of said second transistor Is connected to a voltage detector that generates a voltage proportional to the voltage of the output terminal, and further limits the current values of the first current source and the second current source so that they do not exceed a certain value. It provides a stabilized power supply circuit equipped with a unit.

Further, the present invention is a stabilized power supply circuit described above, which is connected to the drain of the second transistor, said second constant current in a direction which is offset by the current of the current source a third that flows Provided is a regulated power supply circuit with a current source.

Further, the present invention is the above-mentioned stabilized power supply circuit, wherein a current reduction part composed of a fourth transistor is provided between the drain of the second transistor and the third current source, and the current reduction part is When the output current of the stabilized power supply circuit is small, the current value of the third current source is used as the fifth transistor and the fourth transistor in which the gate and drain are connected to the drain of the second transistor. that limits the current value determined by the gate aspect ratio, provides a regulated power supply circuit.

According to the present invention, the problem of phase compensation of a regulated power supply circuit having a function of changing the tail current of the differential amplification unit according to the output current is solved by a method without using a capacitor, and the conventional low current consumption is achieved. It is possible to provide a regulated power supply circuit that can be realized with a smaller chip area than a regulated power supply circuit.

It is a circuit diagram which shows the structure of the stabilized power supply circuit which concerns on 1st Embodiment of this invention. It is a circuit diagram which shows the structure of the stabilized power supply circuit which concerns on 2nd Embodiment of this invention. It is a circuit diagram which shows the structure of the stabilized power supply circuit which concerns on 3rd Embodiment of this invention. It is a figure which shows the relationship between the output current and the output voltage of the regulated power supply circuit which concerns on 3rd Embodiment of this invention. It is a circuit diagram which shows the structure of the conventional stabilized power supply circuit. It is a figure which shows the frequency characteristic of the gain of the conventional regulated power supply circuit. It is a circuit diagram which shows the structure of the conventional regulated power supply circuit which used the capacitor for attenuating the feedback amount by a tail current at a high frequency.

Hereinafter, embodiments in which the stabilized power supply circuit according to the present invention is specifically disclosed will be described in detail with reference to the drawings.

(First Embodiment)
The stabilized power supply circuit according to the first embodiment of the present invention will be described.
FIG. 1 is a circuit diagram showing a configuration of a regulated power supply circuit 1 according to a first embodiment of the present invention. Note that the elements common to the conventional regulated power supply circuit 100 shown in FIG. 5 described above in FIG. 1 are designated by the same reference numerals.

The stabilized power supply circuit 1 according to the first embodiment includes transistors MN1 to MN7 which are N-channel type MOSFETs, transistors MP1 to MP6 which are P-channel type MOSFETs, and a first voltage which outputs a power supply voltage VDD. The source V1, the second voltage source V2 that outputs the reference voltage VREF, the VOUT terminal (output terminal) for taking out the output voltage VOUT, the current source IB1 for passing a constant value current, and the voltage detection It includes resistance elements R1 and R2 and a capacitor CL for stabilizing the output voltage VOUT. A load resistor RL is connected between the VOUT terminal of the regulated power supply circuit 1 and the ground (GND).

The transistor MN1 corresponds to the first transistor, the transistor MN2 corresponds to the second transistor, and the transistor MP1 corresponds to the third transistor. Further, the transistor MN6 corresponds to the first current source, the transistor MN7 corresponds to the second current source, and the transistor MP6 corresponds to the current limiting unit. Further, the transistors MN1, MN2, MP3 and MP4 form a differential amplification unit DAMP, and the resistance elements R1 and R2 form a voltage detection unit VDET.

The connections between the elements constituting the stabilized power supply circuit 1 according to the first embodiment are as follows.
The gate of the transistor MP6 is connected to the gate and drain of the transistor MP5 to which the gate and drain are connected, and one end of the current source IB1 is connected. Further, the positive electrode of the first voltage source V1 is connected to the source of the transistor MP5, and the sources of the transistor MP4, the transistor MP3, the transistor MP6 and the transistor MP1 to which the sources are commonly connected are connected. The negative electrode of the first voltage source V1 is connected to the ground. The game and drain of the transistor MN3 to which the gate and drain are connected are connected to the other end of the current source IB1. In the current source IB1, a current flows in the direction of the arrow (direction from the transistor MP5 to the transistor MN3) as shown in the figure.

The source of transistor MN3 is connected to ground. The gate of the transistor MN4 and the drain are connected to the gate of the transistor MN4. To the drain of the transistor MN4, each source of the transistor MN1 and the transistor MN2 to which the sources are commonly connected is connected, and the drain of the transistor MN6 is connected. The source of transistor MN4 is connected to ground.

The positive electrode of the second voltage source V2 is connected to the gate of the transistor MN1. The negative electrode of the second voltage source V2 is connected to the ground. The gate and drain of the transistor MP3 to which the gate and drain are connected are connected to the gate of the transistor MP4. Further, the drain of the transistor MN1 is connected to the drain of the transistor MP4, and the gates of the transistor MP2 and the transistor MP1 to which the gates are commonly connected are connected. Each drain of the transistor MN2 and the transistor MN7 to which the drain is commonly connected is connected to the gate and the drain of the transistor MP3. Each end of the resistance element R1 and the resistance element R2 is connected to the gate of the transistor MN2. Transistors MP3 and MP4 form a current mirror circuit. Further, as described above, the transistors MP3 and MP4 together with the transistors MN1 and MN2 form a differential amplification unit DAMP whose output is the node of the drain of the transistor MP1.

The gate of the transistor MN7 is connected to the gate of the transistor MN6, and the gate and drain of the transistor MN5 to which the gate and drain are connected are connected. Each source of the transistors MN6 and MN7 is connected to the ground. Transistors MN6 and MN7 form a current mirror circuit. The drain of the transistor MP2 is connected to the gate and drain of the transistor MN5. The source of transistor MN5 is connected to ground.

The drain of the transistor MP6 is connected to the source of the transistor MP2. A VOUT terminal is connected to the drain of the transistor MP1, and the other end of the resistance element R2 is connected. The other end of the resistance element R1 is connected to the ground. A stabilizing capacitor CL is connected between the VOUT terminal and the ground. As described above, the resistance elements R1 and R2 constitute the voltage detection unit VDET.

The connections between the elements constituting the stabilized power supply circuit 1 according to the first embodiment are as described above. The transistor MP1 supplies a current to the VOUT terminal. The differential amplification unit DAMP controls the gate voltage of the transistor MP1 by the difference between the drain currents of the transistor MN1 and the transistor MN2. The transistor MN6, which is the first current source, changes the source currents of the transistor MN1 and the transistor MN2 according to the drain current of the transistor MP1. The drain of the transistor MN7, which is the second current source is connected to the drain of the transistor MN2, the transistor MN7 has a current proportional to the current flowing through the transistor MN6 is flow. The voltage detection unit VDET composed of the resistance elements R1 and R2 generates a voltage proportional to a predetermined voltage output from the VOUT terminal according to the reference voltage VREF. This voltage is applied to the gate of transistor MN2. The transistor MP6, which is a current limiting unit, limits the current values of the transistor MN6, which is the first current source, and the transistor MN7, which is the second current source, so as not to exceed a certain value.

Since the gate of the transistor MP2 is common to that of the transistor MP1, the drain current increases in proportion to the increase in the potential difference between the gate and the source of the transistor MP1. This drain current flows to the drain of the transistor MN5 to which the gate and the drain are connected. The drain current flowing through the drain of the transistor MN5 and the drain current of the transistors MN6 and MN7 constituting the current mirror circuit are controlled. That is, a current proportional to the current supplied to the VOUT terminal flows through the transistor MN6 which is the first current source and the transistor MN7 which is the second current source.

The drain current flowing through the transistor MP6 inserted between the source of the transistor MP2 and the first voltage source V1 is controlled by the voltage between the gate and the source of the transistor MP5 to a current proportional to the current source IB1. As a result, the current flowing through the source of the transistor MP2 is limited to a certain value or less, and the transistor MP6 functions as a current limiting unit.

In a state where there is no load resistance or the like between the VOUT terminal and the ground, the drain current of the transistor MP3 is only the current flowing through the resistance elements R1 and R2 which are feedback resistors. Further, when the gate aspect ratio of the transistor MP1 is sufficiently smaller than that of the transistor MP2, the drain current of the transistor MP2 is substantially 0. In this case, the drain current of the transistor MN4, which constitutes the current mirror circuit with the transistor MN3 and sinks a constant current proportional to the current source IB1, is substantially all of the tail current of the differential amplification unit DAMP. In this state, the drain current of the transistor MN7 is also substantially 0, and a current equal to the transistors MN1 and MN2 flows.

When a resistance or the like that becomes a load enters between the VOUT terminal and the ground and the current increases, the drain current of the transistors MP1 and MP2 increases due to the negative feedback action. Along with this, the transistors MN6 and MN7 also start to flow the drain current. In this state, the drain current of the transistor MN7 is added to the drain current of the transistor MN2, and the drain currents of the transistor MN1 and the transistor MN2 are as shown in the following equation.

Here, the input impedance Zin from the source of the MOSFET in the grounded-gate circuit is as follows.

gm: MOSFET transconductance β: gain coefficient Id: drain current

Idn1: Drain current of transistor MN1 Idn2: Drain current of transistor MN2 Idn4: Drain current of transistor MN4 Idn6: Drain current of transistor MN6 Idn7: Drain current of transistor MN7 M: Gate aspect ratio of transistor MN6 and transistor MN7 (Wn6 / Ln6) ): (Wn7 / Ln7) = 1: M
Wn6: Transistor MN6 gate width Ln6: Transistor MN6 gate length Wn7: Transistor MN7 gate width Ln7: Transistor MN7 gate length M <1
From the above formula

When a small signal vi is input between the gate and the source of the transistors MN6 and MN7, the changes in drain current in the small signal vi of the transistors MN1 and MN2 idn1 and idn2 are as follows.

gmn1: Transistor MN1 transconductance gmn2: Transistor MN2 transconductance gmn6: Transistor MN6 transconductance

Since the gm of each transistor is determined by the drain current of each transistor, the above equations (9) and (10) are as follows when the gain coefficients of the transistor MN1 and the transistor MN2 are the same.

gmn1,2: Transconductance of transistors MN1 and MN2 gmn6,7: Transconductance of transistors MN6 and MN7

The current of the transistor MN7 is added to the drain current of the transistor MN2, which is folded back by the current mirror circuit composed of the transistors MP3 and MP4, and the gate voltage of the transistor MP1 is controlled by the difference from the drain current of the transistor MN1.

In the case of M << 1, it can be approximated as follows.

From the above equation, idn1-idp4 becomes negative regardless of the drain current of the transistor MN6. That is, since idn4> idn1, the feedback due to the tail current operates in the direction of reducing the currents of the transistor MP1 and the transistor MP2, and acts as negative feedback.

From the equation (14), since the drain current of the transistor MN6 increases as the output current of the regulated power supply circuit 1 increases, the difference between the drain currents of the transistors MN1 and MN2 also increases as the output current increases. This becomes the input offset voltage of the differential amplification unit DAMP, and the output voltage of the regulated power supply circuit 1 decreases as the output current increases. Therefore, the regulated power supply circuit 1 has a transistor MP6 which is an element for limiting the current to the source of the transistor MP2. As a result, even if the potential difference between the gate and the source of the transistor MP1 increases, the source current of the transistor MP2 is limited by a constant value, and as a result, the drain current of the transistors MP6 and MP7 is also limited by a constant value. The offset voltage of DAMP is also limited to a certain value or less.

As described above, in the regulated power supply circuit 1 according to the first embodiment, the tail current of the differential amplification unit DAMP is reduced when the output current is small, so that the current consumed by the regulated power supply circuit 1 itself can be reduced. .. Further, in a situation where the output current is large and a high-speed transient response is required, the gate voltage of the transistor MP1 that controls the output current can be quickly driven by increasing the tail current of the differential amplification unit DAMP. Become. Further, since the feedback path in the tail current always operates as negative feedback, it is not necessary to incorporate the capacitor C1 as shown in FIG. 7 in the regulated power supply circuit 1, as compared with the conventional regulated power supply circuit with low current consumption. Can be realized with a smaller chip area.

(Second Embodiment)
The stabilized power supply circuit according to the second embodiment of the present invention will be described.
FIG. 2 is a circuit diagram showing a configuration of a regulated power supply circuit 2 according to a second embodiment of the present invention. In FIG. 2, the regulated power supply circuit 2 according to the second embodiment has a transistor MP7, which is a P-channel MOSFET in which the gate and the source are biased by a constant voltage, as a third current source. .. In this transistor MP7, the source is connected to the positive electrode of the first voltage source V1 and the drain is connected to the drain of the transistor MN2. Further, the gate of the transistor MP7 is connected to each gate of the transistors MP5 and MP6. By adding the transistor MP7 as the third current source, the drain current of the transistor MN2 is increased as compared with the case of the regulated power supply circuit 1 according to the first embodiment. That is, the transistor MP7 has the effect of increasing the drain current of the transistor MN2 to be larger than the drain current of the transistor MN1. As a result, the transconductance of the transistor MN2 is increased as compared with the case of the regulated power supply circuit 1 according to the first embodiment, and contributes to the direction in which the feedback due to the tail current works in the negative feedback direction.

Further, the current sourced from the first voltage source V1 to the drain of the transistor MN2 through the transistor MP7 cancels out the current synced from the drain of the transistor MN2 as the drain current of the transistor MN7, so that the drain current of the transistor MP7 is used. By adjusting to the current limit value of the transistor MN7, the output current increases, and when the increase of the drain current of the transistors MN6 and MN7 stops, the difference between the drain currents of the transistors MN1 and MN2 due to the drain current of the transistor MN7 is reduced. It will work. As a result, the input offset voltage of the differential amplification unit DAMP is reduced.

As described above, the regulated power supply circuit 2 according to the second embodiment has an error with respect to the set value of the output voltage when the load current is a certain value or more as compared with the regulated power supply circuit 1 according to the first embodiment. Can be alleviated.

(Third Embodiment)
The stabilized power supply circuit according to the third embodiment of the present invention will be described.
FIG. 3 is a circuit diagram showing the configuration of the regulated power supply circuit 3 according to the third embodiment of the present invention. In FIG. 3, the regulated power supply circuit 3 according to the third embodiment is a P-channel MOSFET in the regulated power supply circuit 2 according to the second embodiment as a current reducing unit that limits the current value of the transistor MP7. It has a transistor MP8 which is. In this transistor MP8, the source is connected to the drain of the transistor MP7, and the gate and the drain are connected to the drain of the transistor MN2.

Here, the gate aspect ratio of the transistor MP8 and the transistor MP3 is set so that the drain current of the transistor MP8 does not reach the saturation current value when the drain current of the transistors MN6 and MN7 is 0.

When the output current of the stabilized power supply circuit 3 is 0 and the drain currents of the transistors MN6 and MN7 are substantially 0, the current flowing through the transistor MP7 to the drain of the transistor MN2 is the gate aspect ratio of the transistor MP8 and the transistor MP3. It is limited to the current value determined by. When the output current of the regulated power supply circuit 3 increases, the drain currents of the transistors MN6 and MN7 start to flow, and the potential difference between the gate and the source of the transistor MP3 also increases. As a result, the potential difference between the drain and the source of the transistor MP7 becomes large, and the drain current of the transistor MP7 also increases. However, in the transistor MP7, since the potential difference between the gate and the source is biased to a constant value, the increase in the current value is saturated when the potential difference between the drain and the source increases.

In the regulated power supply circuit 2 according to the second embodiment described above, the drain currents of the transistors MN1 and MN2 are as follows.

Idp7: Drain current of transistor MP7

From the above equation, when the drain current of the transistor MN6 is small, the ratio of the drain current of the transistor MN7 increases, so that the ratio of the drain current of the transistor MN1 and the transistor MN2 changes, which is the gate of the transistor MN1 and the transistor MN2. This is the difference in potential difference between the sources, and as shown in the figure showing the relationship between the output current and the output voltage in FIG. 4, the output voltage has an increasing characteristic with respect to the set value. On the other hand, the regulated power supply circuit 3 according to the third embodiment reduces the drain current of the transistor MP7 due to the addition of the transistor MP8. Therefore, it is possible to improve the fluctuation of the output voltage as shown by the dotted line in FIG. 4, especially in the operation with a small output current of 100 μA or less from the state where the regulated power supply is unloaded.

As described above, in the stabilized power supply circuit 3 according to the third embodiment, when the drain current of the transistor MN2 is small, the output current is particularly limited by limiting the current value of the transistor MP7 which is the third current source. The difference between the drain currents of the transistors MN1 and MN2 is reduced to prevent the offset voltage of the differential amplification unit DAMP from increasing and to mitigate the change in the output voltage VOUT in a state where the voltage is small or no resistance is provided as a load. To do. Therefore, as compared with the regulated power supply circuit 2 according to the second embodiment, a regulated power supply that suppresses fluctuations in the output voltage in an operating state with a small output current and has a wider range of output currents and a small fluctuation in the output voltage It is possible to realize it.

Although various embodiments have been described above with reference to the drawings, it goes without saying that the present invention is not limited to such examples. It is clear that a person skilled in the art can come up with various modifications or modifications within the scope of the claims, which naturally belong to the technical scope of the present invention. Understood.
In addition, each component in the above embodiment may be arbitrarily combined as long as the gist of the present invention is not deviated.

The present invention is useful for regulated power supply circuits with low current consumption.

1-3: Stabilized power supply circuit MN1 to MN7: N-channel type transistor MP1 to MP8: P-channel type transistor V1: First voltage source V2: Second voltage source IB1: Current source DAMP: Differential amplification unit VDET: Voltage detector R1, R2: Resistance element CL: Capacitor RL: Load resistance

Claims (3)

A regulated power supply circuit that outputs a predetermined voltage from the output terminal according to the reference voltage.
With the first and second transistors with the sources connected to each other,
A third transistor that supplies current to the output terminal and
A differential amplifier that includes the first transistor and the second transistor and controls the gate voltage of the third transistor by the difference in drain current between the first transistor and the second transistor.
A first current source that changes the source current of the first transistor and the second transistor according to the drain current of the third transistor, and
Which is connected to the drain of the second transistor, and a second current source proportional to the current is flow to the current of the first current source,
The reference voltage is applied to the gate of the first transistor,
The gate of the second transistor is connected to a voltage detector that generates a voltage proportional to the voltage of the output terminal.
Further, a current limiting unit for limiting the current values of the first current source and the second current source so as not to exceed a certain value is provided.
Regulated power supply circuit. The regulated power supply circuit according to claim 1.
Which is connected to the drain of the second transistor, said second constant current in a direction which is offset by the current of the current source with a third current source that flows,
Regulated power supply circuit. The regulated power supply circuit according to claim 2.
A current reducing unit including a fourth transistor is provided between the drain of the second transistor and the third current source.
When the output current of the regulated power supply circuit is small, the current reducing unit uses the current value of the third current source as a fifth transistor in which a gate and a drain are connected to the drain of the second transistor. that limits the current value determined by the gate aspect ratio of the fourth transistor,
Regulated power supply circuit.

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