JP6796454B2 - Regulator circuit, bias circuit - Google Patents

Description

The present invention relates to a bias circuit.

In electronic circuits, bias circuits that generate a bias current based on a reference current and supply it to an operational amplifier or the like are widely used. The bias circuit is generally composed of a current mirror circuit that copies the reference current or turns the current back. FIG. 1 is a circuit diagram of the regulator circuit 2. The regulator circuit 2 includes a bias circuit 10R and a linear regulator 20. The linear regulator 20 receives an input voltage V _IN supplied to the input line 4 (or the input pin) and generates an output voltage V _OUT stabilized at a predetermined target level on the output line 6 (or the output pin). ..

The linear regulator 20 includes a reference voltage source 22, an operational amplifier 24, a power transistor 26, and a feedback circuit 28. The reference voltage source 22 is, for example, a bandgap reference circuit, and generates a reference voltage V _REF that does not depend on temperature, power supply voltage, or the like. The power transistor 26 is a NMOS transistor, the source is connected to the input line 4, and the drain is connected to the output line 6. The reference voltage V _REF is input to the inverting input terminal (−) of the operational amplifier 24, and the feedback voltage V _FB fed back by the feedback circuit 28 is input to the non-inverting input terminal (+).
V _FB = V _OUT x β

The linear regulator 20 stabilizes the output voltage V _OUT to the target level V _{OUT (REF)} represented by the following equation.
V _{OUT (REF)} = V _REF / β

Some operational amplifiers 24 require a regulated bias current. In this example, the operational amplifier 24 operates on the basis of two bias currents, I _{2_1} and I _{2_2} . The number of bias currents to be supplied to the operational amplifier 24 depends on the configuration of the operational amplifier 24, and may be three or more or one.

A bias circuit 10R is provided to generate the bias currents I _{2_1} and I _{2_2} . The bias circuit 10R includes a reference current source 12 and a current mirror circuit 14. The reference current source 12 produces a reference current I _REF . The current mirror circuit 14 includes an input transistor _{M 1} and a plurality of output transistors _{M 2_1,} comprises _{M 2_2,} current _I 2_1 proportional to the reference current _{I REF,} and generates an _{I 2_2.} Although the current mirror circuit 14 can be grasped as a part of the operational amplifier 24, it is shown as an external circuit of the operational amplifier 24 for easy understanding.

Japanese Unexamined Patent Publication No. 2011-172203

As a result of examining the input transient fluctuation of the regulator circuit 2R of FIG. 1, the present inventors have come to recognize the following problems. FIG. 2 is an operation waveform diagram of the regulator circuit 2R of FIG. 1 at the time of input transient fluctuation. The input voltage V _IN supplied to the input line 4 may fluctuate transiently, and FIG. 2 shows the operation when the input voltage V _IN drops sharply.

Before time t ₀ , the input voltage V _IN is stable and the output voltage V _OUT is also stabilized at the target level V _{OUT (REF)} . At time t ₀ , the input voltage V _IN drops sharply. As shown in FIG. 1, a parasitic capacitance Cg exists at the gates of the transistors M ₁ , M _{2_1} , and M _{2_2} constituting the current mirror circuit 14 of the bias circuit 10R. The influence of the gate capacitance Cg, when the input voltage V _IN quickly decreases, the gate voltage V _G is reduced with a delay to the input voltage V _IN. This delay, transistor _{M 1,} M _{2_1,} the gate-source voltage _{V GS} of _{M 2_2} is, becomes less gate threshold _{V GS (TH),} the transistor _{M 2_1, M 2_2} is turned off, the bias current _{I 2_1,} I _{2_2} decreases. When the bias currents I _{2_1} and I _{2_2} decrease, the operational amplifier 24 becomes inoperable and the gate of the power transistor 26 cannot be lowered, and as a result, the output voltage V _OUT becomes lower than the target level V _{OUT (REF).} ..

Then, when the discharge of the gate capacitance by the reference current I _REF of the reference current source 12 generates progresses, the gate voltage V _G is lowered. When the gate-source voltage V _GS exceeds the threshold value V _{GS (TH)} , the current mirror circuit 14 can operate normally, the bias currents I _{2_1} and I _{2_2} are restored, and the power is supplied by the feedback from the operational amplifier 24. The gate voltage of the transistor 26 is adjusted to an appropriate voltage level, and the output voltage V _OUT returns to the target level V _{OUT (REF)} .

As described above, in the regulator circuit 2R using the bias circuit 10R of FIG. 1, when the input voltage V _IN drops, the bias currents I _{2_1} and I _{2_2} are insufficient, and the output voltage V _OUT becomes the target level V _{OUT (REF). ),} The problem arises.

This can be grasped as a problem related to the input transient fluctuation of the regulator circuit 2R, or can be grasped as a problem related to the power supply voltage fluctuation of the bias circuit 10R. A similar problem may occur when the current mirror circuit 14 is composed of a PNP type bipolar transistor.

The present invention has been made in view of the above problems, and one of the exemplary purposes of the present invention is to provide a regulator circuit having improved input transient fluctuation characteristics. Further, another one of the exemplary purposes of one aspect is to provide a bias circuit that suppresses a decrease in output current due to a decrease in power supply voltage.

One aspect of the present invention relates to a regulator circuit. The regulator circuit receives a reference voltage at an input line that receives an input voltage, an output line, a power transistor provided between the input line and the output line, and a first input terminal, and is generated at the second input terminal at the output line. It includes an operational amplifier whose output terminal is connected to a control terminal of a power transistor by receiving a feedback voltage corresponding to an output voltage, and a bias circuit that supplies N (N is a natural number) bias currents to the operational amplifier. The bias circuit is a first input transistor that is connected to an input line and a common control terminal, a first reference current source that generates a first reference current, and a second reference current source that generates a second reference current. And N first output transistors, the first input transistor is provided on the path of the first reference current, and the current flowing through the N first output transistors is N bias currents. The circuit includes a second input transistor and a second output transistor which are connected to the input line and the control terminals are commonly connected, and the second input transistor is a second current mirror circuit provided on the path of the second reference current. When the detection current flowing through the second output transistor is reduced, the correction current source for drawing the correction current from the control terminals of the first input transistor and the N first output transistors is provided.

A second current mirror circuit, which is a replica (dummy) of the first current mirror circuit, is provided, and the state of the first current mirror circuit is monitored by the second current mirror circuit. When a decrease in the bias current generated by the first current mirror circuit is detected due to a decrease in the input voltage, the correction current corrects the operating point of the first current mirror circuit at high speed to reduce the bias current. Can be suppressed and the input transient fluctuation characteristics can be improved.

The correction current source receives a predetermined bias voltage at the gate / base, and the drain / collector is corrected with an N-channel or NPN-type correction transistor in which the control terminals of the first input transistor and the N first output transistors are connected. It may include an impedance circuit provided between the source / emitter of the transistor and ground. The detection current flowing through the second output transistor may be supplied to the connection node of the correction transistor and the impedance circuit.
When the detection current is large, the correction current is zero or sufficiently small, and when the detection current decreases, the correction transistor is turned on and a large correction current can be generated.

The impedance circuit may include at least one of a resistor and a constant current source.

The mirror ratio of the second current mirror circuit may be substantially equal to the ratio of the size of the first input transistor to the total size of the N first output transistors. As a result, the state of the first current mirror circuit can be accurately monitored by the second current mirror circuit.

The regulator circuit may further include capacitors connected to the control terminals of the second input transistor and the second output transistor.
By optimizing the capacitance of the capacitor, the response characteristic of the second current mirror circuit to the input voltage fluctuation can be made closer to that of the first current mirror circuit.

The regulator circuit may further include a reference voltage source that produces a reference voltage and a low-pass filter provided between the reference voltage source and the operational amplifier. As a result, the noise of the reference voltage can be removed, so that the noise included in the output voltage can be reduced.

The regulator circuit may be integrally integrated on one semiconductor substrate.
"Integrated integration" includes cases where all the components of a circuit are formed on a semiconductor substrate or cases where the main components of a circuit are integrated integrally, and some of them are used for adjusting circuit constants. A resistor, a capacitor, or the like may be provided outside the semiconductor substrate.

The plurality of first transistor elements constituting the first input transistor and N first output transistors are arranged in the first direction in the first region on the semiconductor substrate to form the second input transistor and the second output transistor. The plurality of second transistor elements may be arranged in the second direction in the second region adjacent to the first region on the semiconductor substrate and the second direction perpendicular to the first direction.
As a result, the characteristics of the first current mirror circuit and the second current mirror circuit can be made uniform.

The first transistor element constituting the first input transistor is arranged in the center of the first region, and the second transistor element constituting the second input transistor is adjacent to the first transistor element constituting the first input transistor. May be arranged.

The regulator circuit may supply the output voltage generated in the output line to the power supply terminal of the audio circuit.

Another aspect of the present invention relates to a bias circuit that produces N bias currents (where N is an integer). This bias circuit is connected to a first reference current source that generates a first reference current, a second reference current source that generates a second reference current, a power supply line, and a first input in which control terminals are commonly connected. The first current includes a transistor and N first output transistors, the first input transistor is provided on the path of the first reference current, and the current flowing through the N first output transistors is N bias currents. A second current mirror circuit including a mirror circuit, a second input transistor connected to a power supply line, and a control terminal commonly connected, and the second input transistor provided on a path of a second reference current. And, when the detection current flowing through the second output transistor decreases, the correction current source that draws the correction current from the control terminals of the first input transistor and the N first output transistors is provided.

A second current mirror circuit, which is a replica (dummy) of the first current mirror circuit, is provided, and the state of the first current mirror circuit is monitored by the second current mirror circuit. When a decrease in the bias current generated by the first current mirror circuit is detected due to a decrease in the power supply voltage, the correction current corrects the operating point of the first current mirror circuit at high speed to reduce the bias current. Can be suppressed and the power supply fluctuation characteristics can be improved.

It should be noted that any combination of the above components or components and expressions of the present invention that are mutually replaced between methods, devices, systems, and the like are also effective as aspects of the present invention.

According to one aspect of the present invention, the input transient fluctuation characteristic of the regulator circuit can be improved, and according to another aspect, the decrease in output current due to the decrease in the power supply voltage of the bias circuit can be suppressed.

It is a circuit diagram of a regulator circuit. It is operation waveform diagram at the time of input transient fluctuation of the regulator circuit of FIG. It is a circuit diagram of the semiconductor device provided with the bias circuit which concerns on embodiment. It is an operation waveform diagram of the bias circuit of FIG. 5 (a) to 5 (d) are circuit diagrams showing a configuration example of a correction current source. It is a circuit diagram of a part of the bias circuit which concerns on the modification. It is a circuit diagram of a regulator circuit including a bias circuit. It is a circuit diagram which shows the specific configuration example of a regulator circuit. 9 (a) and 9 (b) are diagrams showing an example of the layout of the regulator IC. It is an application circuit diagram of the audio reproduction apparatus provided with a regulator IC.

Hereinafter, the present invention will be described with reference to the drawings based on preferred embodiments. The same or equivalent components, members, and processes shown in the drawings shall be designated by the same reference numerals, and redundant description will be omitted as appropriate. Further, the embodiment is not limited to the invention but is an example, and all the features and combinations thereof described in the embodiment are not necessarily essential to the invention.

In the present specification, "a state in which the member A is connected to the member B" means that the member A and the member B are physically directly connected, or the member A and the member B are electrically connected. It also includes cases of being indirectly connected via other members that do not affect the state or interfere with the function.
Similarly, "a state in which the member C is provided between the member A and the member B" means that the member A and the member C, or the member B and the member C are directly connected, and also electrically. It also includes the case of being indirectly connected via another member that does not affect the connection state or interfere with the function.

FIG. 3 is a circuit diagram of the semiconductor device 1 including the bias circuit 30 according to the embodiment. The semiconductor device 1 includes a bias circuit 30 and a biased circuit 60. Bias circuit 30, N (N is an integer) generates a bias current _I B1 _{~I BN} of supplies to the target circuit 60. The circuit configuration of the biased circuit 60 is not particularly limited.

The bias circuit 30 includes a first reference current source 32, a second reference current source 34, a first current mirror circuit 36, a second current mirror circuit 38, and a correction current source 40. The first reference current source 32 generates the first reference current I _REF1 . The second reference current source 34 generates the second reference current I _REF2 .

The first current mirror circuit 36 is connected to the power supply line 62. The first current mirror circuit 36 includes a first input transistor M ₁ and N first output transistors M _{2_1 to} M _{2_N} . First input transistor _{M 1} and N first output transistor _M 2_1 _{~M 2_n} control terminal (gate) is connected in common.

The first input transistor M ₁ is provided on the path of the first reference current I _REF 1. Current flowing through the N first output transistor _M 2_1 _{~M 2_n} is supplied to the bias circuit 60 as the N of the bias current _I B1 _{~I BN.}

The second current mirror circuit 38 includes a second input transistor M ₃ and a second output transistor M ₄ whose one end (source) is connected to the power supply line 62. The second input transistor M ₃ and the second output transistor M ₄ are of the same type as the first input transistor M ₁ and the first output transistor M ₂ . The control terminals (gates) of the second input transistor M ₃ and the second output transistor M ₄ are commonly connected. The second input transistor M ₃ is provided on the path of the second reference current I _REF 2.

The second current mirror circuit 38 is a replica of the first current mirror circuit 36, the current flowing through the second output transistor _{M 4} (detection _{current) I DET} is according to the bias current _{I B} flowing through the first current mirror circuit 36 ing.

The correction current source 40 receives the detection current I _DET , and when the detection current I _DET decreases, the correction current source 40 is enabled, and the first input transistor M ₁ and the N first output transistors M _{2_1 to} M _{2_N} are commonly connected control terminals. Pull out the correction current _ICMP from (gate). The correction current source 40 is in the disabled state when the detection current I _DET is large, and produces a correction current _ICMP that is substantially zero or sufficiently small.

The above is the configuration of the semiconductor device 1. Next, the operation will be described.

FIG. 4 is an operation waveform diagram of the bias circuit 30 of FIG. FIG. 4 shows the operation when the power supply voltage _VDD drops sharply. The vertical and horizontal axes of the waveform charts and time charts referred to in the present specification are appropriately enlarged or reduced for ease of understanding, and each waveform shown is also simplified for ease of understanding. Or exaggerated or emphasized.

In before time _{t 0,} power supply voltage _{V DD} is stable, the bias current _I B1 _{~I BN} flowing in the first current mirror circuit 36 is stabilized to an integral multiple of the current amount of the reference current _{I REF1.} Further, the detection current I _DET flowing through the second current mirror circuit 38 is also stabilized to a current amount that is an integral multiple of the reference current I _REF2 . At this time, the correction current _ICMP is zero or sufficiently small.

At time t ₀ , the power supply voltage _VDD drops sharply. At this time, since the gate voltage V _G2 of the second current mirror circuit 38 drops with a delay, the gate-source voltage V _{GS2 of} the transistors M ₃ and M ₄ constituting the second current mirror circuit 38 becomes smaller, and the detection current I _DET Decreases. This occurs by the same mechanism as the reduction of the bias current in the current mirror circuit 14 of FIG. The gate voltage V _G2, and corresponds to the gate voltage V _G in FIG. 1, when the correction current I _CMP was zero at 3, corresponding to the estimated waveform of the gate voltage V _G1.

As soon as the detection current I _DET decreases, the correction current I _CMP increases, and this correction current I _CMP is forcibly pulled out from the gate of the first current mirror circuit 36, so that the gate voltage _VG1 becomes the power supply voltage _VDD . It follows and decreases. As a result, the gate-source voltage _{V GS1} of the first current mirror circuit 36 becomes a maintaining gate threshold _{V GS} of _(TH) is greater than the state, to suppress the reduction in bias current _I B1 _{~I BN} it can. Note that FIG. 4 shows the bias current when the correction current _ICMP is not corrected by the alternate long and short dash line.

The above is the operation of the bias circuit 30. According to the bias circuit 30, the power supply voltage V _DD even when transiently steeply reduced, it is possible to suppress the reduction in bias current I _B1 ~I _BN.

Note in transient variation of the power supply voltage _{V DD,} when generating excessive correction current _{I CMP,} since so that the input current _{I REF1} of the first current mirror circuit 36 is increased, the bias current _I B1 _{~I BN} is a dotted line It will increase as shown. Therefore, the amount of correction current _{I CMP,} the variation of the bias current _I B1 _{~I BN} may be determined as possible reduced during transients in the power supply voltage _{V DD.}

Note that the target circuit 60, lowering of the bias current _I B1 _{~I BN} is hindering the operation, but an increase of the bias current _I B1 _{~I BN} are many cases where no problem. Thus the amount of correction current _{I CMP,} during transients of the power supply voltage _{V DD,} the bias current _I B1 _{~I BN} may be determined so as not to fall below the operation guarantee level of the bias circuit 60.

The present invention extends to various devices and circuits grasped as the block diagram and circuit diagram of FIG. 3 or derived from the above description, and is not limited to a specific configuration. Hereinafter, more specific configuration examples will be described not for narrowing the scope of the present invention, but for helping to understand the essence of the invention and circuit operation, and for clarifying them.

5 (a) to 5 (c) are circuit diagrams showing a configuration example of the correction current source 40. The correction current source 40 of FIG. 5A includes a correction transistor 42 and an impedance circuit 44. The correction transistor 42 is an N-channel transistor, receives a predetermined bias voltage V _BIAS at the gate, and the drain is connected to the control terminals (gates) of the first input transistor M ₁ and the N first output transistors M _2. .. The correction transistor 42 may be a PNP type bipolar transistor. In this case, the gate may be read as the base, the drain as the collector, and the source as the emitter.

The impedance circuit 44 is provided between the source / emitter of the correction transistor 42 and the ground. The detection current I _DET flowing through the second output transistor is supplied to the connection node of the correction transistor 42 and the impedance circuit 44.

The impedance circuit 44 may include a resistor as shown in FIG. 5 (a), may include a constant current source as shown in FIG. 5 (b), or may include a resistor as shown in FIG. 5 (c). And a constant current source may be connected in series. The impedance circuit 44 may include a diode for level shifting.

The operation of the correction current source 40 will be described with reference to FIG. 5A. Voltage drop in the impedance circuit 44, that is, the source voltage _{V S} of the correction transistor 42 _{is I DET} × R. R is the impedance of the impedance circuit 44. The correction current I _CMP is zero when the gate-source voltage V _GS of the correction transistor 42 is smaller than the gate threshold V _{GS (TH)} .

When _{V GS = V BIAS -V S>} V GS (TH), the correction current _{I CMP flows,} when V BIAS _-V S of _{<V GS (TH),} the correction current _{I CMP} becomes zero.
When V _BIAS- I _DET x R> V _{GS (TH)} , in other words, when (V _BIAS- V _{GS (TH)} ) / R> I _DET , the correction current I _CMP flows, and (V _BIAS- V _{GS) (TH)} ) When / R < _IDET , the correction current _ICMP becomes zero.

The same applies to FIGS. 5 (b) and 5 (c). According to the correction current sources 40 of FIGS. 5A to 5C, an appropriate correction current _ICMP can be generated according to the detection current _IDET .

The configuration of the correction current source 40 is not limited to those shown in FIGS. 5A to 5C. In the simplest case, as shown in FIG. 5D, the correction current source 40 can be configured by the current source 46. The current source 46 produces a reference current I _REF3 . Since I _DET + I _CMP = I _REF3 holds, I _CMP = I _REF3- I _DET . Therefore, when I _DET = 0, I _CMP = I _REF3 , and when I _DET ≈ I _REF3 , I _CMP ≈ 0.

Return to FIG. The mirror ratio of the second current mirror circuit 38 (size ratio of transistors M ₃ and M ₄ ) is the ratio of the size of the first input transistor M ₁ to the total size of N first output transistors M _{2_1 to} M _{2_N.} It is preferred that they be substantially equal.

Let the size (gate width / gate length ratio W / L) of the first input transistor M _{1 be} A ₁ . _Further , the sizes of the N first output transistors M _{2_1 to} M _{2_N} are set to A _{2_1 to} A _{2_N} . Further, the sizes of the transistors M ₃ and M ₄ are A ₃ and A ₄ . At this time,
A ₁ : Σ _{1 to NA 2_i} = A ₃ : A ₄
It is preferable that As a result, the state of the first current mirror circuit 36 can be accurately monitored by the second current mirror circuit 38.

I _REF1 = I _REF2 , and A ₁ = A ₃ and Σ _{1 to NA 2_i} = A ₄ may be set. In this case, since the second current mirror circuit 38 is a perfect replica of the first current mirror circuit 36, the state of the first current mirror circuit 36 can be detected with the highest accuracy.

I _REF1 / M = I _REF2 may be set. In this case, A ₁ / M = A ₃ and Σ _{1 to NA 2_i} / M = A ₄ may be set. In this case, the size of the second current mirror circuit 38 and the second reference current source 34 can be reduced.

FIG. 6 is a partial circuit diagram of the bias circuit 30 according to the modified example. Capacitors C _X ( _CY ) may be connected to the control terminals (gates) of the second input transistor M ₃ and the second output transistor M ₄ . The capacitor C _X may be provided between the ground and the power supply line 62.

By optimizing the capacitance of the capacitor C _X ( _CY ), the frequency response characteristic of the second current mirror circuit 38 with respect to the fluctuation of the power supply voltage can be made closer to that of the first current mirror circuit 36. In particular, if the size of the second current mirror circuit 38 cannot be idealized with respect to the size of the first current mirror circuit 36 due to the limitation of the circuit area, the correction current I by adding the capacitor C _X ( _CY ). The state of the first current mirror circuit 36 when no _CMP is given can be predicted accurately.

Subsequently, a specific application of the bias circuit 30 will be described. FIG. 7 is a circuit diagram of a regulator circuit 2 including a bias circuit 30. The regulator circuit 2 includes a linear regulator 20 corresponding to the biased circuit 60 and a bias circuit 30. The regulator circuit 2 receives an input voltage (power supply voltage) V _IN at the input line 4, generates an output voltage V _OUT stabilized at a predetermined target level, and applies a load (not shown) connected to the output line 6. Supply. The power supply voltage V _DD of the bias circuit 30 is the input voltage V _IN of the regulator circuit 2.

The configuration of the linear regulator 20 is the same as that in FIG. 1, and includes a reference voltage source 22, an operational amplifier 24, a power transistor 26, and a feedback circuit 28. The reference voltage source 22 is, for example, a bandgap reference circuit, which produces a reference voltage V _REF . The power transistor 26 is provided between the input line 4 and the output line 6. The power transistor 26 is a P-channel MOSFET or a PNP-type bipolar transistor.

The operational amplifier 24 receives a reference voltage V _REF at the first input terminal (inverting input terminal −), and receives a feedback voltage at the second input terminal (non-inverting input terminal +) according to the output voltage V _OUT generated in the output line 6. Receive V _FB . The output terminal of the operational amplifier 24 is connected to the control terminal (gate / base) of the power transistor 26. The feedback circuit 28 includes resistors R _FB1 and R _FB2 , _divides the output voltage V _OUT , and generates a feedback voltage V _FB .

The bias circuit 30 supplies a bias current to the operational amplifier 24. Is not particularly restricted but configuration of the operational amplifier 24, therefore is also not limited to the number of the bias current I _B, can be used operational amplifier is described in, for example, Patent Document (JP 2011-172203).

In FIG. 7, the first current mirror circuit 36 and the second current mirror circuit 38 are composed of PNP type bipolar transistors.

According to the regulator circuit 2 of FIG. 7, when the input voltage V _IN drops sharply also, since the bias current I _B1 ~I _B2 to the bias circuit 30 generates is maintained, the output voltage by the feedback by the operational amplifier 24 The decrease of V _OUT can be suppressed.

FIG. 8 is a circuit diagram showing a specific configuration example of the regulator circuit 2. The regulator circuit 2 includes a regulator IC (Integrated Circuit) 70 whose main part is integrated on one semiconductor substrate (semiconductor chip, die).

The operational amplifier 24, the power transistor 26, the bias circuit 30, and a part of the reference voltage source 22 are built in the regulator IC 70. The input voltage (VIN) pin, the input voltage _{V IN} is supplied. A feedback resistor R _FB1 is connected between the output voltage (VO) pin and the voltage detection (VS) pin, and a resistor R _FB2 is connected between the VS pin and the ground. VIN pin, each of the VO pin, capacitor _C i for smoothing, _{C O} is connected.

An external enable signal is input to the enable (EN) pin. The regulator IC 70 goes into operation when the EN pin signal is asserted (for example, high level). Specifically, in response to the assertion of the enable signal, the bandgap reference circuit 72 is activated and the protection circuit 84 is activated.

The reference voltage source 22 includes a bandgap reference circuit 72, resistors 74 and 76, an operational amplifier 78, resistors R _BA1 and R _BA2 . The bandgap reference circuit 72 generates a reference voltage _VBG . Resistance 74 and 76, divide the reference voltage _{V BG.} The operational amplifier 78 amplifies the reference voltage V _BG after the partial pressure and generates the reference voltage V _REF . The resistor R _BA1 is connected between the two bias pins BAO and BAS, and the resistor R _BA2 is connected between the bias pins BAS and ground.

A low-pass filter 80 is provided between the reference voltage source 22 and the operational amplifier 24. Low pass filter 80 includes a built-in resistor 82, constituted by the smoothing capacitor _{C BC} externally attached to the BC pins. The protection circuit 84 includes protection functions such as overcurrent protection (OCP), thermal shutdown (TSD), and low voltage lockout (UVLO).

The above is the configuration of the regulator IC 70 and the regulator circuit 2.

9 (a) and 9 (b) are diagrams showing an example of the layout of the regulator IC 70. As shown in FIG. 9A, the power transistor 26, the operational amplifier 24, the bias circuit 30, and the other circuits 50 are arranged side by side in the second direction (Y direction) on the semiconductor substrate 90. The other circuit 50 includes a bandgap reference circuit (BG), an overcurrent protection circuit (OCP), a thermal shutdown circuit (TSD), a low voltage lockout circuit (UVLO), and the like.

FIG. 9B shows the layout of the bias circuit 30. A plurality of first transistor element to the first input transistor _{M 1} and N first output transistor _M 2_1 _{~M 2_2} configuration of the first current mirror circuit 36 96_1～96_5 is the first region 92 on the semiconductor substrate 90 , Arranged in the first direction (X direction).

A plurality of second transistor elements 98_1 to 98_5 constituting the second input transistor M ₃ and the second output transistor M ₄ of the second current mirror circuit 38 are arranged in the X direction in the second region 94 on the semiconductor substrate 90. Will be done. The second region 94 and the first region 92 are adjacent to each other in the Y direction. The transistor elements 96 and 98 have the same size.

The first transistor element 96_3 constituting the first input transistor M ₁ is arranged at the center in the first region 92. The first transistor element 96_1,96_2 are connected electrically in parallel, a first output transistor _{M 2_1} formed, the first transistor element 96_4,96_5 are electrically connected in parallel to form a first output transistor _{M 2_2.}

The second transistor element 98_3 constituting the second input transistor M ₃ is arranged adjacent to the first transistor element 96_3 constituting the first input transistor M ₁ . The remaining second transistor element 98_1,98_2,98_4,98_5 is electrically connected in parallel to form a second output transistor _{M 4.}

According to this layout, the ratio accuracy of the mirror ratio of the first current mirror circuit 36 can be improved. Further, the ratio accuracy of the mirror ratio of the second current mirror circuit 38 can be improved. Further, the input transistors M ₁ and M ₃ of the first current mirror circuit 36 and the second current mirror circuit 38 are adjacent to each other, and the output transistors M ₂ and M _{4 of} the first current mirror circuit 36 and the second current mirror circuit 38 are adjacent to each other. Is adjacent to each other, so that the state of the first current mirror circuit 36 can be accurately monitored by the second current mirror circuit 38.

FIG. 10 is an application circuit diagram of the audio playback device 100 including the regulator IC 70. The switching regulator 102, which is a DC power supply, generates, for example, a power supply voltage V _{IN of} 5 V. The regulator IC 70 receives the power supply voltage V _IN , generates a DC output voltage V _OUT stabilized at, for example, 3.35 V, and supplies the regulator IC 70 to the audio DSP (Digital Signal Processor) 104. The audio DSP 104 includes a clock generator 106 and a D / A converter 108. The D / A converter 108 converts a digital audio signal into an analog audio signal. The clock generator 106 generates a clock signal CK to be supplied to the D / A converter 108.

The amplifier 110 amplifies the analog audio signal generated by the D / A converter 108 and drives the electroacoustic conversion element 112 such as headphones and speakers.

If noise is superimposed on the power supply voltage supplied to the clock generator 106 and the D / A converter 108, it causes deterioration of sound quality. Since the output voltage V _OUT of the regulator IC 70 has low noise, it is suitable as a power supply voltage for them. A plurality of regulator ICs 70 may be used to generate a power supply voltage for the amplifier 110.

Although the present invention has been described using specific terms and phrases based on the embodiments, the embodiments merely indicate the principles and applications of the present invention, and the embodiments are defined in the claims. Many modifications and arrangement changes are permitted without departing from the ideas of the present invention.

1 ... semiconductor device, 2 ... regulator circuit, 4 ... input line, 6 ... output line, 20 ... linear regulator, 22 ... reference voltage source, 24 ... arithmetic amplifier, 26 ... power transistor, 28 ... feedback circuit, 30 ... bias circuit , 31 ... reference voltage source, 32 ... first reference current source, 34 ... second reference current source, 36 ... first current mirror circuit, 38 ... second current mirror circuit, 40 ... correction current source, 42 ... correction transistor, 44 ... impedance circuit, M ₁ ... 1st input transistor, M ₂ ... 1st output transistor, M ₃ ... 2nd input transistor, M ₄ ... 2nd output transistor, 60 ... biased circuit, 62 ... power supply line, 70 ... Regulator IC, 72 ... Band gap reference circuit, 74, 76 ... Resistance, 78 ... Computational amplifier, 80 ... Low pass filter, 82 ... Protection circuit, 90 ... Semiconductor substrate, 92 ... 1st region, 94 ... 2nd region, 96 ... 1st transistor element, 98 ... 2nd transistor element, 100 ... audio reproduction device, 102 ... switching regulator, 104 ... audio DSP, 106 ... clock generator, 108 ... D / A converter, 110 ... amplifier, 112 ... electroacoustic Conversion element.

Claims (19)

The input line that receives the input voltage and
Output line and
A power transistor provided between the input line and the output line,
An operational amplifier that receives a reference voltage at the first input terminal, receives a feedback voltage corresponding to the output voltage generated in the output line at the second input terminal, and connects the output terminal to the control terminal of the power transistor.
A bias circuit that supplies N bias currents (N is a natural number) to the operational amplifier,
With
The bias circuit
The first reference current source that generates the first reference current and
A second reference current source that generates a second reference current, and
It includes a first input transistor and N first output transistors connected to the input line and commonly connected to control terminals, and the first input transistor is provided on the path of the first reference current, and the N The first current mirror circuit in which the current flowing through the first output transistors is the N bias currents, and
The second input transistor includes a second input transistor and a second output transistor connected to the input line and commonly connected to the control terminal, and the second input transistor has a second current mirror circuit provided on the path of the second reference current. ,
When the detection current flowing through the second output transistor decreases, a correction current source that draws a correction current from the control terminals of the first input transistor and the N first output transistors, and a correction current source.
A regulator circuit characterized by being provided with. The correction current source is
An N-channel or NPN-type correction transistor that receives a predetermined bias voltage on the gate / base and whose drain / collector is connected to the control terminals of the first input transistor and the N first output transistors.
An impedance circuit provided between the source / emitter and ground of the correction transistor,
Including
The regulator circuit according to claim 1, wherein the detection current flowing through the second output transistor is supplied to the connection node between the correction transistor and the impedance circuit. The regulator circuit according to claim 2, wherein the impedance circuit includes at least one of a resistor and a constant current source. Any of claims 1 to 3, wherein the mirror ratio of the second current mirror circuit is substantially equal to the ratio of the size of the first input transistor to the total size of the N first output transistors. Regulator circuit described in. The regulator circuit according to any one of claims 1 to 4, further comprising a capacitor connected to the control terminal of the second input transistor and the second output transistor. The reference voltage source that generates the reference voltage and
A low-pass filter provided between the reference voltage source and the operational amplifier,
The regulator circuit according to any one of claims 1 to 5, further comprising. The regulator circuit according to any one of claims 1 to 6, wherein the regulator circuit is integrally integrated on one semiconductor substrate. The first input transistor and the plurality of first transistor elements constituting the N first output transistors are arranged in the first direction in the first region on the semiconductor substrate.
The second input transistor and the plurality of second transistor elements constituting the second output transistor are located in a second region adjacent to the first region on the semiconductor substrate in a second direction perpendicular to the first direction. The regulator circuit according to claim 7, wherein the regulator circuit is arranged in the first direction. The first transistor element constituting the first input transistor is arranged in the center of the first region.
The regulator circuit according to claim 8, wherein the second transistor element constituting the second input transistor is arranged adjacent to the first transistor element constituting the first input transistor. The regulator circuit according to any one of claims 1 to 9, wherein the output voltage generated in the output line is supplied to a power supply terminal of an audio circuit. It is a bias circuit that generates N bias currents (N is a natural number ).
The first reference current source that generates the first reference current and
A second reference current source that generates a second reference current, and
It includes a first input transistor and N first output transistors connected to a power supply line and commonly connected to control terminals, and the first input transistor is provided on the path of the first reference current, and the N first input transistor is provided. The first current mirror circuit in which the current flowing through the first output transistor is the N bias currents, and
The second input transistor includes a second input transistor and a second output transistor connected to the power supply line and commonly connected to the control terminal, and the second input transistor has a second current mirror circuit provided on the path of the second reference current. ,
When the detection current flowing through the second output transistor decreases, a correction current source that draws a correction current from the control terminals of the first input transistor and the N first output transistors, and a correction current source.
A bias circuit characterized by comprising. The correction current source is
An N-channel or NPN-type correction transistor that receives a predetermined bias voltage on the gate / base and whose drain / collector is connected to the control terminals of the first input transistor and the N first output transistors.
An impedance circuit provided between the source / emitter and ground of the correction transistor,
Including
The bias circuit according to claim 11, wherein the detection current flowing through the second output transistor is supplied to the connection node between the correction transistor and the impedance circuit. The bias circuit according to claim 12, wherein the impedance circuit includes at least one of a resistor and a constant current source. Any of claims 11 to 13, wherein the mirror ratio of the second current mirror circuit is substantially equal to the ratio of the size of the first input transistor to the total size of the N first output transistors. The bias circuit described in. The bias circuit according to any one of claims 11 to 14, wherein a capacitor is connected to the control terminal of the second input transistor and the second output transistor. The bias circuit according to any one of claims 11 to 15, wherein the bias circuit is integrally integrated on one semiconductor substrate. The first input transistor and the plurality of first transistor elements constituting the N first output transistors are arranged in the first direction in the first region on the semiconductor substrate.
The second input transistor and the plurality of second transistor elements constituting the second output transistor are located in a second region adjacent to the first region on the semiconductor substrate in a second direction perpendicular to the first direction. The bias circuit according to claim 16, wherein the bias circuit is arranged in the first direction. The first transistor element constituting the first input transistor is arranged in the center of the first region.
The bias circuit according to claim 17, wherein the second transistor element constituting the second input transistor is arranged adjacent to the first transistor element constituting the first input transistor. The bias circuit according to any one of claims 11 to 18, wherein the N bias currents are supplied to an operational amplifier.

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