JP2013003699A - Semiconductor integrated circuit for regulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit for a regulator capable of applying a current limit at a desired current limit point even when an output voltage is set at a voltage lower than 1 V.SOLUTION: The semiconductor integrated circuit for a regulator includes: a transistor (M1) for current detection, which constitutes a current mirror circuit with a transistor for voltage control; current-voltage conversion means (R3) connected in series with the transistor for the current detection; a passive element (M3) connected in series with the current-voltage conversion means; a transistor (M6) for current limit connected between an input terminal and a control terminal of the transistor for the voltage control; and a current bypass circuit provided in parallel with the passive element between a connection node of the current-voltage conversion means and the passive element and a reference potential terminal of the circuit. The current bypass circuit has a series circuit of a depression type MOS transistor and an enhancement type MOS transistor, and the transistor for the current limit is controlled corresponding to a voltage converted by the current-voltage conversion means.

Description

  The present invention relates to a DC power supply device and further to a voltage regulator that converts a DC voltage. For example, the present invention relates to a semiconductor integrated circuit (regulator IC) constituting a series regulator (LDO: including a low saturation regulator) having an overcurrent protection function. It is related to effective technology.

  In a series regulator, for example, when an overcurrent starts flowing from the output terminal due to a short circuit of the load, the current control transistor generates heat, the IC chip temperature rises, the internal circuit malfunctions, the element is destroyed, etc. May cause problems.

  Conventionally, in a series regulator, in order to protect the chip from the overcurrent as described above, when the output current Iout exceeds a predetermined value, for example, as shown in FIG. A current limit circuit having an overcurrent protection function for reducing the output voltage and output current characteristics so as to obtain a so-called “F” -shaped output voltage is provided (Patent Document 1).

JP 2008-052516 A

  In a conventional voltage regulator provided with a current limit circuit having an overcurrent protection function having a “F” characteristic, if the output voltage setting is different, as shown by a broken line in FIG. The value Ilim changes. That is, as the set output voltage is lower, the overcurrent protection function is activated at a lower output current.

  Therefore, the present inventors have devised and studied a voltage regulator provided with a current limit circuit 14 as shown in FIG. FIG. 7 shows the output voltage-output current characteristics of the current limit circuit shown in FIG. The current limit circuit 14 of FIG. 6 is provided with a short-circuit detection point B for stopping the operation of the regulator by detecting the short-circuit state of the load in addition to the current limit point A by providing the MOS transistor M7 for short-circuit detection. It is composed.

Thus, as shown by the dotted line in FIG. 7, when the output voltage Vout is set to 5V, the current is limited at a constant current limit point (point A) and at the same time, a short-circuit detection point (point B) For example, even when the output voltage Vout is set to a voltage of 1.5V, the current limit point (point A) and the short-circuit detection point (point B) are the same. There is an advantage that you can.
However, even in the current limit circuit of FIG. 6, when the output voltage is set to a low potential such as 1V, the overcurrent protection function is activated at a point such as A ′ shown in FIG. I found that there was a problem.

  The present invention has been made under the background as described above, and an object of the present invention is to provide a regulator capable of limiting the current at a desired current limit point even when the output voltage is set to a relatively low voltage. It is to provide a semiconductor integrated circuit.

In order to achieve the above object, the present invention provides:
A voltage control transistor connected between the input terminal and the output terminal;
A control circuit for controlling the control transistor so that the output voltage becomes constant according to a feedback voltage proportional to the output voltage;
A current limiting circuit for detecting an output current flowing through the voltage control transistor and restricting the output current by regulating a control voltage of the voltage control transistor when the output current exceeds a predetermined current value;
With
The current limiting circuit is:
A current detection transistor which forms a current mirror circuit together with the voltage control transistor;
Current-voltage conversion means connected in series with the current detection transistor;
A passive element connected in series with the current-voltage conversion means;
A current limiting transistor connected between the input terminal and the control terminal of the voltage control transistor;
A current bypass circuit provided in parallel with the passive element and controlled to be turned on and off in accordance with the output voltage, between a connection node between the current-voltage converting means and the passive element and a reference potential terminal of the circuit; With
The current limiting transistor is controlled based on the voltage converted by the current-voltage converting means.

  According to the above-described means, even if the output voltage setting voltage is different, the overcurrent protection is controlled such that the current limiting transistor is turned on at a substantially constant current limiting point and the current flowing through the voltage controlling transistor is reduced. The function comes to work.

Preferably, the current bypass circuit includes a depletion type MOS transistor having a gate terminal connected to the input terminal, and an enhancement type MOS transistor provided in series with the transistor and having a gate terminal connected to the drain terminal. Constitute.
This lowers the threshold value for turning on and off the current bypass circuit (short-circuit detection transistor) that can operate according to the output state (whether or not there is a short circuit). For this reason, even when the output voltage is set to a voltage lower than 1V, it is possible to perform a current limiting operation in which the current is limited at a substantially constant current limiting point and the current is reduced according to a desired “F” character characteristic. become able to.

Further, preferably, the current limiting circuit includes a voltage characteristic conversion circuit in which a resistor, a transistor, and a passive element are connected in series between the input terminal and a reference potential terminal of the circuit, and the current-voltage conversion The voltage converted by the means is applied to the gate terminal of the transistor constituting the voltage characteristic conversion circuit, and the voltage obtained by converting the current flowing through the transistor with the resistor is input to the control terminal of the current limiting transistor. Configure.
As a result, a P-channel MOS transistor can be used as the current limiting transistor, the voltage drop between the source and drain is reduced, and the voltage control transistor is sufficiently turned off when the overcurrent protection function is activated. Can be made.

  According to the present invention, there is an effect that it is possible to realize a semiconductor integrated circuit for a regulator that can limit a current at a desired current limit point even when the output voltage is set to a relatively low voltage.

It is a circuit block diagram which shows one Embodiment of control IC of the series regulator to which this invention is applied. It is a voltage-current characteristic diagram showing the relationship between the output voltage and the output current in the control IC of the series regulator of the embodiment, (a) is a characteristic diagram of the regulator with the output voltage set to 5V, (b) These are the characteristic figures of the regulator with which the output voltage was set to 1V. (A) is an equivalent circuit when only a depletion type MOS transistor is used as a short circuit detection MOS transistor constituting the current limit circuit, and (B) is a depletion type MOS transistor and an enhancement type MOS transistor as short circuit detection MOS transistors. (C) is an equivalent circuit when only an enhancement type MOS transistor is used as a MOS transistor for short circuit detection. 4 is a graph showing changes in drain current when the input voltage VIN applied to the gate terminal is changed for each of the circuits of FIGS. 3 (A), (B), and (C). FIG. 6 is a circuit configuration diagram showing a modification of the series regulator control IC of the embodiment of FIG. 1. It is a circuit block diagram which shows the current limit circuit in control IC of the series regulator provided with the current limit circuit devised and examined in the case of this invention. FIG. 7 is a voltage-current characteristic diagram showing a relationship between an output voltage and an output current in a control IC of a series regulator including the current limit circuit of FIG. 6. It is a graph which shows the "V" -shaped output voltage-output current characteristic in the conventional series regulator.

DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the drawings.
FIG. 1 shows an embodiment of a series regulator (including an LDO) to which the present invention is applied. Although not particularly limited, the elements constituting the circuit of the portion surrounded by the alternate long and short dash line in FIG. 1 are formed on one semiconductor chip as a semiconductor integrated circuit (series regulator IC) 10. Composed.

  The series regulator IC 10 in this embodiment includes a P-channel MOSFET (insulated gate field effect transistor: hereinafter referred to as a MOS transistor) between a voltage input terminal IN and an output terminal OUT to which a DC voltage VDD from a DC voltage source (not shown) is applied. And a bleeder resistor R1, R2 for dividing the output voltage Vout is connected in series between the output terminal OUT and the ground terminal GND to which the ground potential is applied. Yes. The voltage VFB divided by the bleeder resistors R1 and R2 is fed back to the non-inverting input terminal of the error amplifier 11 that controls the gate terminal of the voltage control transistor M1.

  The error amplifier 11 controls the voltage control transistor M1 in accordance with the potential difference between the feedback voltage VFB and the reference voltage Vref so as to control the output voltage Vout to a desired potential. The potential of the output voltage Vout can be set by the resistance ratio of the bleeder resistors R1 and R2. The series regulator of this embodiment operates so as to keep the output voltage Vout constant below the output current Iout by a feedback control as described above. Although not shown, an external capacitor for stabilizing the output voltage Vout is connected to the output terminal OUT.

  Further, the regulator IC 10 of this embodiment includes a reference voltage circuit 12 for generating a reference voltage Vref, a bias circuit 13 for supplying a bias current to the reference voltage circuit 12 and the error amplifier 11, and an output current limiting circuit. A current limit circuit 14 having a current protection function is provided. The reference voltage circuit 12 includes a constant voltage circuit formed of a Zener diode, or a reference voltage generation circuit in which a depletion type MOS transistor and an enhancement type MOS transistor that operate as a constant current source are connected in series.

The bias circuit 13 is turned on and off by a chip on / off control signal (chip enable signal) input from the outside, and is configured to flow a bias current through the reference voltage circuit 12 and the error amplifier 11.
The current limit circuit 14 of this embodiment reduces the output current Iout while decreasing the output voltage Vout when the output current Iout increases and reaches a predetermined current value due to a short circuit of the load. It has a function of protecting the element from overcurrent by controlling so that the output voltage-output current characteristic of "" is obtained.

  The current limit circuit 14 forms a current mirror with the voltage control transistor M1 by connecting the source terminal to the source terminal of the voltage control transistor M1 and applying the same voltage as the gate voltage of M1 to the gate terminal. A current detection P-channel MOS transistor M2 for passing a current Is proportional to the output current Iout passed by M1, and a current-voltage conversion means connected in series with the MOS transistor M2 for converting the drain current of M2 into a voltage. Resistor R3 and an N-channel MOS transistor M3 connected in series with the resistor R3. The MOS transistor M3 has a gate and a drain coupled to each other and functions as a diode to raise the terminal voltage of the resistor R3.

  The voltage control transistor M1 and the MOS transistor M2 connected in a current mirror manner have a size (size) of 1 / N of M1 and flow a current of 1 / N of the drain current of M1. The size ratio 1 / N can be set to a value of, for example, about 1/1000. Accordingly, the current Is flowing through the current detection MOS transistor M2 can be very small, and flows through the current detection resistor R3. Wasteful current can be reduced.

  The current limit circuit 14 of this embodiment is provided with a circuit comprising a resistor R4 and MOS transistors M4 and M5 connected in series between the output terminal OUT and the ground point GND. The gate terminal of the MOS transistor M4 is connected to the connection node N1 between the current detection MOS transistor M2 and the resistor R3, and the gate terminal and the drain terminal of the MOS transistor M5 are coupled to function as a diode. ing.

  Further, the gate terminal is connected to the connection node N2 between the resistor R4 and the MOS transistor M4, the source terminal is connected to the input terminal IN, and the drain terminal is connected to the gate terminal of the voltage control transistor M1. Is provided. Therefore, the circuit composed of the resistor R4 and the MOS transistors M4 and M5 functions as a voltage characteristic conversion circuit in which the potential of the node N2 as the output terminal decreases as the potential of the node N1 as the input terminal increases.

  Further, the current limit circuit 14 of the present embodiment includes a short-circuit detection MOS transistor in which the output voltage Vout is applied to the gate terminal between the connection node N3 between the resistor R3 and the MOS transistor M3 and the ground node GND. M7 and M8 are provided. When MOS transistors M7 and M8 are turned on, the current flowing from resistor R3 flows to the ground point through M7 and M8, so that M7 and M8 function as a current bypass circuit.

In this embodiment, a normally-on depletion type MOS transistor is used as the MOS transistor M7, and an enhancement type MOS transistor similar to the other elements M1 to M6 is used as the MOS transistor M8. The threshold voltage is set to be lower than that in the case of only the enhancement type MOS transistor (FIG. 6).
In FIG. 1, transistors denoted by reference numerals M1, M2, and M6 are P-channel MOS transistors, and the other transistors are N-channel MOS transistors.

Next, the operation of the current limit circuit 14 configured as described above will be described.
In a normal operation state in which an output current Iout equal to or less than a specified value is supplied by the voltage control transistor M1, a current Is proportional to the output current Iout (for example, 1 out of Iout) / 1000) flows. At the same time, the error amplifier 11 performs feedback control on the gate terminal of M1 so that the output voltage Vout becomes a set voltage (for example, 5 V). As a result, the gate voltage of the short-circuit detection MOS transistor M7 whose gate terminal is connected to the output terminal OUT is sufficiently high, and the MOS transistor M7 is turned on.

  Therefore, the current Is flowing in the MOS transistor M2 of the current mirror flows to the ground point GND through the resistor R3 and the MOS transistor M7. As a result, the potential of the connection node N3 between the resistor R3 and the MOS transistor M7 (M3) is close to the ground potential, so the potential of the connection node N1 between M2 and R3 is also low, and the gate terminal is connected to the node N1. The MOS transistor M4 is turned off, and the current I4 flowing through M4 is reduced, so that the current flowing through the resistor R4 is kept small. As a result, the MOS transistor M6 whose gate terminal is connected to the connection node N2 between the resistor R4 and the MOS transistor M4 is turned off.

  Next, if the output current Iout increases due to a short circuit of the load or the like, the current Is of the MOS transistor M2 of the current mirror increases, the potential of the node N1 increases, the current I4 flowing through the MOS transistor M4 also increases, and the resistance R4 The potential of the connection node N2 with the MOS transistor M4 is lowered. When the output current Iout reaches a preset limit current value Ilim, the potential of the node N2 becomes lower than the threshold voltage of the MOS transistor M6, and M6 is turned on weakly. For this reason, regardless of the output of the error amplifier 11, the gate voltage of the voltage control transistor M1 is increased to make a transition in a direction in which M1 is turned off, and the output voltage Vout is decreased (point A in FIG. 2).

  When the output voltage Vout reaches a relatively low voltage such as 0.5 V, for example, the series circuit of the MOS transistors M7 and M8 is turned off. Then, the current Is flowing through the resistor R3 flows through the MOS transistor M3 to the ground point GND. As a result, the potential of the connection node N3 between the resistor R3 and the MOS transistor M3 becomes higher than before the series circuit of M7 and M8 is turned off, the MOS transistor M4 is turned on more strongly, and the current I4 flowing through the resistor R4 is As a result, the MOS transistor M6 is strongly turned on, and the gate voltage of the voltage control transistor M1 is raised to turn it off. As a result, the output current Iout decreases rapidly and the output voltage Vout also starts to decrease (point B in FIG. 2).

  In the current limit circuit of this embodiment, as described above, since the current bypass circuit including the series circuit of the MOS transistors M7 and M8 having low threshold values is provided in parallel with the MOS transistor M3 acting as a diode, the output voltage Vout Is set to a relatively low voltage (for example, 1 V), the current limit can be applied at a substantially constant current limit point (points A to A ″ in FIG. 2).

  In the current limit circuit shown in FIG. 6 in which the depletion MOS transistor (M7) is not used, the point B is in the vicinity of Vout = 1V, whereas in the circuit of this embodiment, the point B is close to Vout = 0.5V. Go down. Therefore, in the regulator using the current limit circuit shown in FIG. 6, when the set voltage of the output voltage Vout is 1V, as shown in FIG. On the other hand, in the regulator to which the circuit of this embodiment is applied, even if the set voltage of the output voltage Vout is 1 V, as shown in FIG. 2, it is in the vicinity of the point A that is the original current limit point. The overcurrent protection function comes to work.

Here, the threshold value of the MOS transistor for detecting a short circuit will be described with reference to FIG.
3A is an equivalent circuit when only a depletion type MOS transistor is used as a short-circuit detection MOS transistor, and FIG. 3B is an implementation using a depletion type MOS transistor and an enhancement type MOS transistor as short-circuit detection MOS transistors. An equivalent circuit in the case of the example, (C) is an equivalent circuit in the case of a current limit circuit (FIG. 6) using only enhancement type MOS transistors as MOS transistors for short circuit detection.

FIG. 4 shows changes in the drain current when the input voltage VIN applied to the gate terminal is changed for each of the circuits in FIGS. 3 (A), (B), and (C). In FIG. 4, symbol a is the drain current characteristic of the circuit of FIG. 3A, symbol b is the drain current characteristic of the circuit of FIG. 3B, and symbol c is the drain current characteristic of the circuit of FIG. . 4A and 4B, the threshold voltage of the circuit of FIG. 3A is 0 V or less, and the threshold voltage of the circuit of FIG. 3C is about 0.8 V, whereas the circuit of FIG. It can be seen that the threshold voltage of is about 0.3V.
Since the current limit circuit of FIG. 1 uses the circuit of FIG. 3B having a threshold voltage of about 0.3 V as described above, it has an overcurrent protection characteristic as shown in FIG. be able to.

  FIG. 5 shows a modification of the current limit circuit of the above embodiment. Specifically, in the above embodiment, the diode-connected MOS transistor M3 is provided in parallel with M7 and M8 between the connection node N3 between the resistor R3 and the short-circuit detecting MOS transistor M7 and the ground point. In the modification of FIG. 5, a diode D1 such as a PN junction is connected instead of the MOS transistor M3. A resistor may be connected instead of the diode D1. The same applies to the diode-connected MOS transistor M5 connected in series with the MOS transistor M4.

Although the invention made by the present inventor has been specifically described based on the embodiment, the present invention is not limited to the embodiment.
For example, in the above-described embodiment, a P-channel MOS transistor is used as the current limiting transistor M6, but an N-channel MOS transistor can be used. However, if an N-channel MOS transistor is used, the voltage drop between the drain and source in the transistor is larger than that in the P-channel type, and the voltage control transistor M1 is sufficiently turned off when the overcurrent protection function is activated. I can't.

  On the other hand, as in the previous embodiment, a P-channel MOS transistor is used as the current limiting transistor M6, and the detection voltage of the circuit (M2, R3, M3) for detecting the output current is input, and the resistor R4 and By providing a circuit (voltage characteristic conversion circuit) in which the MOS transistor M4 and the diode-connected MOS transistor M5 are connected in series to control the current limiting transistor M6, voltage control is performed when the overcurrent protection function works. The transistor M1 can be sufficiently turned off.

In the regulator shown in FIG. 1, a MOS transistor is used as the voltage control transistor M1, but the present invention can also be applied to a circuit using a bipolar transistor instead of the MOS transistor. In the regulator IC of the above embodiment, a reference voltage circuit for generating a reference voltage Vref serving as a reference for the error amplifier 11 is provided inside the chip. However, an external terminal is provided so that the reference voltage Vref is supplied from the outside of the chip. You may comprise. The bleeder resistors R1 and R2 for generating the feedback voltage VFB can also be constituted by external elements instead of on-chip elements.
Further, in the above description, the example in which the present invention is applied to the series regulator IC has been described. However, the present invention is not limited to the present invention, and the charging control IC constituting the charging device for charging the secondary battery is also not limited thereto. Can be used.

10 Series Regulator IC
11 Error amplifier (control circuit)
12 Reference Voltage Circuit 13 Bias Circuit 14 Current Limit Circuit (Current Limit Circuit)
M1 Voltage control transistor M2 Current detection transistor M6 Current limiting transistor M7 Short-circuit detection transistor

Claims (3)

A voltage control transistor connected between the input terminal and the output terminal;
A control circuit for controlling the control transistor so that the output voltage becomes constant according to a feedback voltage proportional to the output voltage;
A current limiting circuit for detecting an output current flowing through the voltage control transistor and restricting the output current by regulating a control voltage of the voltage control transistor when the output current exceeds a predetermined current value;
With
The current limiting circuit is:
A current detection transistor which forms a current mirror circuit together with the voltage control transistor;
Current-voltage conversion means connected in series with the current detection transistor;
A passive element connected in series with the current-voltage conversion means;
A current limiting transistor connected between the input terminal and the control terminal of the voltage control transistor;
A current bypass circuit provided in parallel with the passive element and controlled to be turned on and off in accordance with the output voltage, between a connection node between the current-voltage converting means and the passive element and a reference potential terminal of the circuit; With
A regulator semiconductor integrated circuit, wherein the current limiting transistor is controlled based on a voltage converted by the current-voltage converting means.   The current bypass circuit includes a depletion type MOS transistor having a gate terminal connected to the input terminal, and an enhancement type MOS transistor provided in series with the transistor and having a gate terminal connected to a drain terminal. The regulator semiconductor integrated circuit according to claim 1.   The current limiting circuit includes a voltage characteristic conversion circuit in which a resistor, a transistor, and a passive element are connected in series between the input terminal and a reference potential terminal of the circuit, and is converted by the current-voltage conversion unit. A voltage is applied to a gate terminal of a transistor constituting the voltage characteristic conversion circuit, and a voltage obtained by converting a current flowing through the transistor by the resistor is input to a control terminal of the current limiting transistor. A semiconductor integrated circuit for a regulator according to claim 2.

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