JP6788347B2 - ベクトル例外コードを処理するコンピュータ・プログラム、コンピュータ・システム及び方法 - Google Patents
ベクトル例外コードを処理するコンピュータ・プログラム、コンピュータ・システム及び方法 Download PDFInfo
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- G—PHYSICS
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- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
- G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
- G06F9/323—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for indirect branch instructions
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
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Description
1つ又は複数の態様の技術を通じて、付加的な特徴及び利点が実現される。他の実施形態及び態様は、本明細書で詳細に説明され、特許請求の範囲の一部と見なされる。
0−命令の第1のベクトル・レジスタ指定(例えば、ビット8−11内)のための最上位ビット。
1−もしあれば、命令の第2のベクトル・レジスタ指定(例えば、ビット12−15内)のための最上位ビット。
2−もしあれば、命令の第3のベクトル・レジスタ指定(例えば、ビット16−19内)のための最上位ビット。
3−もしあれば、命令の第4のベクトル・レジスタ指定(例えば、ビット32−35内)のための最上位ビット。
IEEE例外を引き起こすことなく、SNaN(シグナリングNaN)及びQNaN(クワイエットNaN)を含むオペランド要素が検査される。
0 全ての要素について、選択されたビットは1である(一致)
1 全ての要素ではないが、少なくとも1つの要素について、選択されたビットは1である(Sビットがゼロである場合)
2 −−
3 全ての要素について、選択されたビットは0である(非一致)
プログラム例外:
*ベクトル・ファシリティがイネーブルにされていないことを示す、データ例外コード(DXC)FEを伴うデータ、ベクトル命令
*演算(z/Architectureのためのベクトル・ファシリティがインストールされていない場合)
*指定
*トランザクション制限
1.この命令は、例外のリスクなしに又はIEEEフラグを設定せずにオペランド要素をテストする方法を提供する。
2.Sビットが設定された場合、1の条件コードは使用されない。
*ベクトル・ファシリティがイネーブルにされていないことを示す、データ例外コード(DXC)FEを伴うデータ、ベクトル命令
*演算(z/Architectureのためのベクトル・ファシリティがインストールされていない場合)
*トランザクション制限
1.第3のオペランドのコンテンツは、チェックサム計算アルゴリズムの開始時にゼロを含むことになる。
2.16ビット・チェックサムは、例えば、TCP/IPアプリケーションにおいて用いられる。32ビット・チェックサムを計算した後、以下のプログラムを実行することができる。
*ベクトル・ファシリティがイネーブルにされていないことを示す、データ例外コード(DXC)FEを伴うデータ、ベクトル命令
*演算(z/Architectureのためのベクトル・ファシリティがインストールされていない場合)
*指定
*トランザクション制限
*ベクトル・ファシリティがイネーブルにされていないことを示す、データ例外コード(DXC)FEを伴うデータ、ベクトル命令
*演算(z/Architectureのためのベクトル・ファシリティがインストールされていない場合)
*指定
*トランザクション制限
*ベクトル・ファシリティがイネーブルにされていないことを示す、データ例外コード(DXC)FEを伴うデータ、ベクトル命令
*演算(z/Architectureのためのベクトル・ファシリティがインストールされていない場合)
*指定
*トランザクション制限
1.VERIMとVGMとの組み合わせを用いて、Rotate and Insert Selected Bits命令の完全な機能を達成することができる。
2.I4フィールドのビットは、各要素を左にローテートするためのビット数を指定する符号なし2進整数を含むように定義されるが、右へのローテート量を効果的に指定する負の数をコード化してもよい。
0001 IEEE無効操作
0010 IEEEゼロ除算
0011 IEEEオーバーフロー
0100 IEEEアンダーフロー
0101 IEEE不正確
102、5026:プロセッサ
104、204、5025:メモリ
106、206:入力/出力デバイス及び/又はインターフェース
108、208:バス
202:ネイティブ中央演算処理ユニット(CPU)
210:ネイティブ・レジスタ
212:エミュレータ・コード
250:ゲスト命令
252:命令フェッチ・ユニット
254:命令変換ルーチン
256:ネイティブ命令
260:エミュレーション制御ルーチン
300:レジスタ・ファイル
302、480:ベクトル・レジスタ
304:浮動小数点レジスタ
400:Vector Floating Point Test Data Class Immediate命令
500:Vector Checksum命令
600:Vector Galois Field Multiply Sum and
700:Vector Generate Mask命令
800:Vector Element Rotate and Insert Under Mask命令
900:ベクトル例外コード
902:ベクトル・インデックス
904:ベクトル割り込みコード
1000:コンピュータ・プログラム製品
Claims (12)
- 例外処理を容易にする方法であって、前記方法は、
プロセッサが、コンピュータ環境内で複数の要素を含むベクトル・レジスタ上で動作する命令が実行された際に前記ベクトル・レジスタの前記複数の要素のうちの1つ又は複数の要素がそれぞれ例外を引き起こしたことを判断するステップであって、前記命令は、少なくとも1つのSingle Instruction Multiple Data(SIMD)操作を含む、判断するステップと、
前記プロセッサが、前記例外に基づいて、前記例外を引き起こした前記1つ又は複数の要素のうちの1つの要素の前記ベクトル・レジスタ内の位置を示す位置情報を含むベクトル例外コードを設定するステップと、
前記例外コードを前記プロセッサから出力するステップと、
を含む方法。 - 前記位置情報は、前記例外を引き起こした前記1つ又は複数の要素のうちの1つの要素に対応する前記ベクトル・レジスタ内のインデックスである、請求項1に記載の方法。
- 前記インデックスは、前記例外を引き起こした前記1つ又は複数の要素に対応する前記ベクトル・レジスタ内のインデックスのうち最小のものである、請求項2に記載の方法。
- 前記例外は、割り込みを発生させる例外である、請求項1乃至3のいずれか1項に記載の方法。
- 前記ベクトル例外コードは、前記位置情報と、前記例外の種類を示すベクトル割り込みコードとを含む、請求項1乃至4のいずれか1項に記載の方法。
- 前記ベクトル割り込みコードは、無効操作、ゼロ除算、オーバーフロー、アンダーフロー、又は不正確の結果のうちの1つを示すための値を含む、請求項5に記載の方法。
- 前記方法は、前記ベクトル・レジスタのどの1つ又は複数の要素が前記例外を引き起こしたかを判断するステップと、どの1つ又は複数の要素が前記例外を引き起こしたかの前記判断に基づいて、前記ベクトル例外コードに含まれる前記位置情報を設定するステップとを含む、請求項1乃至6のいずれか1項に記載の方法。
- 前記位置情報を設定するステップは、前記例外を引き起こした前記1つ又は複数の要素の最小インデックス付き要素を判断するステップと、前記最小インデックス付き要素のインデックスを前記位置として使用するステップとを含む、請求項7に記載の方法。
- 前記方法は、浮動小数点制御レジスタのデータ例外コード・フィールドに前記ベクトル例外コードを入れるステップをさらに含む、請求項1乃至8のいずれか1項に記載の方法。
- 前記要素のサイズは、前記命令のフィールドにおいて指定される、請求項1乃至請求項9のいずれか1項に記載の方法。
- 請求項1乃至10のいずれか1項に記載の前記方法の全てのステップを実行するように適合された手段を含むシステム。
- コンピュータ・システム上でコンピュータ・プログラムが実行されたとき、請求項1乃至10のいずれか1項に記載の前記方法の全てのステップを実行するための命令を含むコンピュータ・プログラム。
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US13/748,504 | 2013-01-23 | ||
US13/748,504 US9715385B2 (en) | 2013-01-23 | 2013-01-23 | Vector exception code |
PCT/IB2013/060697 WO2014115002A1 (en) | 2013-01-23 | 2013-12-06 | Vector exception code |
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JP2019087292A Division JP2019145164A (ja) | 2013-01-23 | 2019-05-07 | ベクトル例外コードを処理するコンピュータ・プログラム、コンピュータ・システム及び方法 |
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JP2016509716A JP2016509716A (ja) | 2016-03-31 |
JP2016509716A5 JP2016509716A5 (ja) | 2016-11-17 |
JP6788347B2 true JP6788347B2 (ja) | 2020-11-25 |
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JP2019087292A Pending JP2019145164A (ja) | 2013-01-23 | 2019-05-07 | ベクトル例外コードを処理するコンピュータ・プログラム、コンピュータ・システム及び方法 |
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US (2) | US9715385B2 (ja) |
EP (1) | EP2948870A4 (ja) |
JP (2) | JP6788347B2 (ja) |
KR (1) | KR101740841B1 (ja) |
CN (1) | CN104956364B (ja) |
AU (1) | AU2013375140B2 (ja) |
BR (1) | BR112015017663A2 (ja) |
CA (1) | CA2895653C (ja) |
HK (1) | HK1210845A1 (ja) |
IL (1) | IL240105B (ja) |
MX (1) | MX340052B (ja) |
RU (1) | RU2015109474A (ja) |
SG (1) | SG11201503786QA (ja) |
TW (1) | TWI584190B (ja) |
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JP2016509716A (ja) | 2016-03-31 |
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CN104956364A (zh) | 2015-09-30 |
HK1210845A1 (en) | 2016-05-06 |
AU2013375140A1 (en) | 2015-07-16 |
IL240105A0 (en) | 2015-09-24 |
EP2948870A1 (en) | 2015-12-02 |
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US9715385B2 (en) | 2017-07-25 |
EP2948870A4 (en) | 2016-11-09 |
SG11201503786QA (en) | 2015-06-29 |
US9727334B2 (en) | 2017-08-08 |
TW201447753A (zh) | 2014-12-16 |
US20150143074A1 (en) | 2015-05-21 |
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