JP6774395B2 - Semiconductor device - Google Patents

Description

Embodiments of the present invention relate to semiconductor devices.

Optical transmission by a photocoupler is known as an example of data transmission. In such optical transmission, data is transmitted from the transmitting side (primary side) to the receiving side (secondary side) via a photocoupler, and the clock is transmitted from the receiving side via another photocoupler. It may be transmitted to the side.
In this case, if a transmission delay occurs during data transmission using a photocoupler or the like, the transmitting side and the receiving side become asynchronous, and a data error may occur on the receiving side.

Japanese Unexamined Patent Publication No. 2008-167058

An embodiment of the present invention is to provide a semiconductor device capable of making data errors on the receiving side less likely to occur even if the transmitting side and the receiving side are asynchronous.

According to the embodiment, the semiconductor device includes a first coupler unit, a coding circuit, a second coupler unit, and a demodulation circuit. The coding circuit differentially Manchester-encodes the digital data based on the clock input via the first coupler unit and outputs the coded data. The demodulator circuit includes a first sampling circuit that samples the coded data based on a sampling frequency set to twice the frequency of the coded data input via the second coupler unit and outputs the first sample data. , A second sampling circuit that samples encoded data at a timing earlier than the first sampling circuit based on the sampling frequency and outputs the second sample data, and the first sample data and the second sample data. However, from the judgment circuit that determines whether or not they match, and the first sample data based on the judgment data of the judgment circuit, the first phase data sampled evenly and the second phase sampled oddly. Includes a selection circuit that selects one of the data.

It is a schematic block diagram of the semiconductor device which concerns on 1st Embodiment. It is a timing chart of the semiconductor device which concerns on 1st Embodiment. It is a block diagram which shows schematic the demodulation circuit which concerns on 1st Embodiment. It is a block diagram which shows schematic the error detection circuit which concerns on 1st Embodiment. It is a flowchart of the semiconductor device which concerns on 1st Embodiment. It is a flowchart which shows the switching operation procedure of selection of the 1st sample data Q. It is a schematic diagram which shows the switching operation content of the selection of the 1st sample data Q. It is a schematic block diagram of the error detection circuit which concerns on 2nd Embodiment. It is a timing chart of the semiconductor device which concerns on 2nd Embodiment. It is a schematic block diagram of the semiconductor device which concerns on 3rd Embodiment. It is a figure which shows the circuit example of the coupler part shown in FIG.

Hereinafter, embodiments according to the present invention will be described with reference to the drawings. The present embodiment does not limit the present invention.

(First Embodiment)
FIG. 1 is a schematic block diagram of the semiconductor device 1 according to the first embodiment. Further, FIG. 2 is a timing chart of the semiconductor device 1 shown in FIG.

As shown in FIG. 1, the semiconductor device 1 according to the present embodiment includes a frequency conversion circuit 2, a first photocoupler 3, an ADC (Analog to Digital Converter) 4, a coding circuit 5, and a second photocoupler. 6 and a demodulation circuit 7 are provided.

The frequency conversion circuit 2 converts the frequency of the clock Ck0 input from the outside to generate the clock Ck1 and the clock Ck2. The frequency of the clock Ck1 is twice the frequency of the clock Ck0, and the frequency of the clock Ck2 is four times the frequency of the clock Ck0. The frequency conversion circuit 2 first generates the clock Ck2 from the clock Ck0, and then divides the clock Ck2 to generate the clock Ck1.

The first photocoupler 3 has a first light emitting element 31 and a first light receiving element 32. In the first photocoupler 3, the clock Ck1 is optically transmitted from the first light emitting element 31 to the first light receiving element 32. The first light receiving element 32 outputs the clock Ck1 to the ADC 4 and the coding circuit 5, respectively.

The ADC 4 converts analog data into digital data D0 based on the clock Ck1 input via the first photocoupler 3. When the digital data D0 is directly input to the semiconductor device 1, the ADC 4 is unnecessary.

The coding circuit 5 generates coded data D1 in which digital data D0 is differentially Manchester-encoded based on the clock Ck1 input via the first photocoupler 3. The frequency of the coded data D1 is the same as the frequency of the clock Ck1.

In the differential Manchester-encoded coded data D1, as shown in FIG. 2, the data value “0” of the digital data D0 has the same code as the previous data value. On the other hand, the data value "1" has a sign opposite to that of the previous data value.

Returning to FIG. 1, the second photocoupler 6 has a second light emitting element 61 and a second light receiving element 62. The second light emitting element 61 phototransmits the coded data D1 to the second light receiving element 62. The second light receiving element 62 outputs the light receiving data D2, which is the coded data D1 received by light, to the demodulation circuit 7. As shown in FIG. 2, the phase of the received light data D2 is delayed by a time t with respect to the phase of the coded data D1.

The first light emitting element 31 and the second light emitting element 61 described above are configured by using, for example, a light emitting diode. Further, the first light receiving element 32 and the second light receiving element 62 are configured by using, for example, a photodiode. The first photocoupler 3 and the second photocoupler 6 may be optical devices that are independent of each other as in the present embodiment, or may be integrated optical devices. Further, instead of the photocoupler, a galvanic coupling element such as magnetic coupling by a coil pair, capacitive coupling by a capacitor, or magnetic coupling using a magnetoresistive element may be used.

Further, in the semiconductor device 1, the ADC 4, the coding circuit 5, the first light receiving element 32, and the second light emitting element 61 are configured as a semiconductor chip on the data transmission side (primary side), and the frequency conversion circuit 2, the first light emitting element The 31, second light receiving element 62, and the demodulator circuit 7 may be configured as a semiconductor chip on the data receiving side (secondary side).

FIG. 3 is a schematic block diagram of the demodulation circuit 7. The demodulation circuit 7 includes an error detection circuit 71, a selection circuit 72, and a decoding circuit 73. First, the error detection circuit 71 will be described with reference to FIG.

FIG. 4 is a schematic block diagram of the error detection circuit 71. The error detection circuit 71 includes a first sampling circuit 711, a delay circuit 712, a second sampling circuit 713, and a determination circuit 714.

The first sampling circuit 711 has a flip-flop that oversamples the received light data D2 based on the clock Ck2. The frequency of the clock Ck2 is set to twice the frequency of the received light data D2 (encoded data D1). That is, the sampling frequency of the first sampling circuit 711 is twice the frequency of the received light data D2.

The delay circuit 712 is provided in front of the second sampling circuit 713 and has an even number of inverters 712a connected in series. With the delay time τ set by the delay circuit 712, the second sampling circuit 713 oversamples the received light data D2 at a timing earlier than that of the first sampling circuit 711.

The second sampling circuit 713 has a flip-flop that oversamples the delay data D3 based on the clock Ck2. As shown in FIG. 2, the second sampling circuit 713 oversamples the delay data D3 delayed by the delay time τ with respect to the first sampling circuit 711. In order to oversample the delay data D3, the delay time τ of the delay circuit 712 is set to a time shorter than the sampling period Ts, which is the reciprocal of the sampling frequency (frequency of the clock Ck2).

Returning to FIG. 4, in the determination circuit 714, whether or not the level of the first sample data Q output from the first sampling circuit 711 and the level of the second sample data R output from the second sampling circuit 713 match. Includes an XOR circuit to determine. The determination data A of the determination circuit 714 is input to the selection circuit 72.

Following the error detection circuit 71 described above, the selection circuit 72 shown in FIG. 3 will be described. The selection circuit 72 includes a first storage circuit 721, a second storage circuit 722, a third storage circuit 723, and a comparison circuit 724. The first storage circuit 721 has a plurality of flip-flops 721a. A plurality of first sample data Qs are temporarily stored in these flip-flops 721a according to the sampling order.

The second storage circuit 722 has a flip-flop that temporarily stores the determination data A of the determination circuit 714. The third storage circuit 723 has a flip-flop that temporarily stores a flag for distinguishing the first phase data from the second phase data.

In the present embodiment, as shown in FIG. 2, the first sample data Q of the first sampling circuit 711 is the first phase data Q0, Q2, Q4 and the second phase data Q1, Q3, Q5 having different phases. being classified. In other words, each first phase data corresponds to even-numbered first sample data Q, and each second phase data corresponds to odd-numbered first sample data Q.

Similarly, the second sample data R of the second sampling circuit 713 is also classified into the first phase data R0, R2, and R4 and the second phase data R1, R3, and R5.

The flag stored in the third storage circuit 723 indicates whether the selection data output from the selection circuit 72 is set to the first phase data or the second phase data in the first sample data Q. .. Further, when the determination data A of the determination circuit 714 described above shows a mismatch between the first sample data Q and the second sample data R, this flag is switched.

For example, when the determination data A indicating the above mismatch is stored in the second storage circuit 722 when the first phase data is set as the selection data, the selection data is changed from the first phase data to the second by switching the flag. Switch to phase data.

When the flag is switched, the comparison circuit 724 compares the first sample data Q stored in the first storage circuit 721 with each other, and determines whether to output Q1 to the decoding circuit 73 based on the comparison result.

The decoding circuit 73 generates digital data D4 by decoding the selected data selected by the selection circuit 72. The digital data D4 corresponds to the digital data D0 before being differentially Manchester encoded in the coding circuit 5. A FIFO (First In First Out) circuit (not shown) may be provided after the decoding circuit 73 in order to adjust the output timing of the digital data D4.

Hereinafter, the operation of the semiconductor device 1 according to the present embodiment will be described. FIG. 5 is a flowchart of the semiconductor device 1. Here, the operation procedure related to data processing will be described.

First, the ADC 4 digitally converts the analog data and outputs the digital data D0 to the coding circuit 5 (step S1). In the present embodiment, the digital data D0 is serial data whose frequency is set to 25 MHz.

Next, the coding circuit 5 encodes the digital data D0 in a differential Manchester and outputs the coded data D1 to the second photocoupler 6 (step S2). The frequency of the coded data D1 is twice the frequency of the digital data D0, that is, 50 MHz.

Next, the second photocoupler 6 optically transmits the coded data D1 (step S3). As a result, the coded data D1 is converted into the light receiving data D2. The frequency of the received light data D2 is the same as the frequency of the coded data D1, that is, 50 MHz.

Next, the first sampling circuit 711 and the second sampling circuit 713 oversample the received light data D2 at different timings (step S4). Next, the determination circuit 714 performs an error determination of the first sample data Q (step S5). Here, the operation of step S5 will be described in detail with reference to FIG.

Consider, for example, a case where the determination circuit 714 compares the second phase data Q1 shown in FIG. 2 with the second phase data R1 in step S5. In this case, since the two data do not match according to FIG. 2, the determination circuit 714 outputs the determination data A indicating that the second phase data Q1 is an error to the selection circuit 72.

Next to the comparison between the second phase data Q1 and the second phase data R1, the determination circuit 714 compares the first phase data Q0 with the first phase data R0. According to FIG. 2, both data match at a high level. This means that there is no level transition of the received light data D2 immediately before the first phase data Q0 (strictly, before the delay time τ). In this case, the determination circuit 714 outputs the determination data A indicating that the first phase data Q0 is not an error to the selection circuit 72.

In this embodiment, the light receiving data D2 is differential Manchester coded, so its level transitions in a short cycle. Further, the sampling frequencies of the first sampling circuit 711 and the second sampling circuit 713 are set to be twice the frequency of the light receiving data D2. Therefore, in the first sample data Q, at least one of the first phase data and the second phase data is highly reliable and correct data.

In step S5, each time the determination circuit 714 outputs the determination data A, the selection circuit 72 selects either the first phase data or the second phase data in the first sample data Q and decodes the circuit. Either output to 73 or no data is output. (Step S6).

The first phase data and the second phase data of the first sample data Q are alternately stored in each flip-flop 721a provided in the first storage circuit 721 of the selection circuit 72. At this time, if the flag for using the first phase data as the selection sample is initially set in the third storage circuit 723, only the first phase data is output from the first storage circuit 721 to the decoding circuit 73. The decoding circuit 73 decodes the first phase data (step S7).

If the determination circuit 714 determines in step S5 that not only the first phase data but also the second phase data is not an error, either phase data may be used for decoding. In the present embodiment, the phase data set in the flag is preferentially selected.

Further, in step S6, the selection data selected by the selection circuit 72, in other words, the correct phase data, is transferred between the first phase data and the second place data of the first sample data Q during the reception of the light receiving data D2. It is expected that the situation will switch. Therefore, the operation of switching the data selection when such a situation occurs will be described with reference to FIGS. 6 and 7.

FIG. 6 is a flowchart showing a procedure for switching the selection of the first sample data Q. FIG. 7 is a schematic diagram showing the content of the selection switching operation of the first sample data Q.

For example, when the determination circuit 714 determines the first phase data Q0 as error data, the comparison circuit 724 of the selection circuit 72 has the second phase data stored in the first storage circuit 721 immediately before the first phase data Q0. Q1 (first storage data) is compared with the first phase data Q2 (second storage data) stored in the first storage circuit 721 immediately before the second phase data Q1 (step S61).

In the present embodiment, since the light receiving data D2 to be sampled is differentially Manchester-encoded, when they do not match, the boundary between the second phase data Q1 and the first phase data Q2 indicates the data delimiter. In this case, since the second phase data Q1 sampled immediately before the first phase data Q0 becomes the correct data instead of the first phase data Q0, the comparison circuit 724 selects the second phase data Q1 (step S62). ..

In step S61, when the second phase data Q1 and the first phase data Q2 match, the comparison circuit 724 stores the first phase data Q2 and the first phase data Q2 in the first storage circuit 721 immediately before the first phase data Q2. The second phase data Q3 (third storage data) is compared (step S63). If they do not match, the boundary between the first phase data Q2 and the second phase data Q3 indicates a data delimiter. In this case, the comparison circuit 724 selects the second phase data Q11 sampled immediately after the first phase data Q0 as data in place of the first phase data Q0 (step S64).

In steps S64 to S68, similarly to steps S61 to S64 described above, the comparison circuit 724 sequentially retroactively compares the first phase data and the second phase data, and the second phase is compared according to the comparison result. Select data Q1 or second phase data Q11. For example, when the second phase data Q1 is selected, the second phase data Q1 is sent to the decoding circuit 73 instead of the first phase data Q0. Further, when the second phase data Q11 is selected, no phase data is sent to the decoding circuit 73 in that cycle. Then, the second phase data Q11 sampled in the next cycle is sent to the decoding circuit 73 instead of the first phase data Q0.

Note that FIG. 7A schematically shows the operations of steps S65 and S66. On the other hand, FIG. 7B schematically shows the operation of step S67 and step S68. Further, in the present embodiment, the light receiving data D2 is differentially Manchester-encoded and oversampled at a sampling frequency twice that frequency. Therefore, even if error data occurs during reception of the received light data D2, if the first sample data Q up to at least five before the error data are compared with each other, the phase data immediately before or after the error data is correct data. Can be specified as.

According to the present embodiment described above, on the data transmission side, the data is optically transmitted in a differential Manchester coded manner in which the level changes in a short time. On the other hand, on the data receiving side, the optically received data is oversampled by the first sampling circuit 711 and the second sampling circuit 713 at different timings and at twice the sampling frequency. After that, the sample data of each sampling circuit is determined by the determination circuit 714.

The determination data A of the determination circuit 714 corresponds to the presence or absence of a level transition of the light receiving data D2 immediately before the sample data of the first sampling circuit 711, in other words, the reliability of the sample data. Therefore, by decoding highly reliable sample data, it is possible to make it difficult for data errors to occur on the receiving side.

(Second Embodiment)
The semiconductor device according to the second embodiment will be described focusing on the differences from the first embodiment. The present embodiment differs from the first embodiment in that the demodulation circuit 7 has an error detection circuit 81.

FIG. 8 is a schematic block diagram of the error detection circuit according to the second embodiment. Further, FIG. 9 is a timing chart of the semiconductor device according to the second embodiment.

The error detection circuit 81 shown in FIG. 8 includes a first sampling circuit 811, a second sampling circuit 812, and a determination circuit 813. Since the first sampling circuit 811 is the same as the first sampling circuit 711 described in the first embodiment, the description thereof will be omitted here.

The second sampling circuit 812 oversamples the received light data D2 at the same sampling frequency as the first sampling circuit 811. At this time, as shown in FIG. 9, the second sampling circuit 812 oversamples the received light data D2 based on the timing of the clock Ck3 in which the clock Ck2 is inverted. In this case, as the second sample data R of the second sampling circuit 812, a waveform having a timing earlier than the first sample data Q of the first sampling circuit 811 is sampled as in the first embodiment. It becomes.

The determination circuit 813 determines whether or not the first sample data Q and the second sample data R match, and outputs the determination data A to the selection circuit 72, similarly to the determination circuit 714 described in the first embodiment. .. The error detection circuit 81 has a flip-flop (not shown) in the subsequent stage of the first sampling circuit 811 and the subsequent stage of the determination circuit 813 in order to input the first sample data Q and the determination data A to the selection circuit 72 at the same timing. May be provided respectively.

According to the present embodiment described above, by using the clock Ck3, the second sampling circuit 812 can oversample the received light data D2 at a timing earlier than that of the first sampling circuit 811. After that, as in the first embodiment, highly reliable data is selected and decoded. Therefore, it is possible to make it difficult for data errors to occur on the receiving side.

Further, in the present embodiment, the delay circuit 712 described in the first embodiment becomes unnecessary. In this case, there is no variation in the delay time due to the characteristic variation of the delay circuit 712. Therefore, since the sampling operation of the second sampling circuit 812 is stable, it is possible to further improve the reliability of data reception.

(Third Embodiment)
In the first and second embodiments described above, the coupler unit that receives the optical signals from the light emitting elements 31 and 61 by the light receiving elements 32 and 62 while maintaining the insulated state has been described as an example of the signal transmission means. However, the coupler unit can be an insulating device such as an optical coupling device that transmits and receives an optical signal, as well as an insulating device that transmits a signal in a non-contact manner by, for example, a magnetically coupled or capacitively coupled galvanic coupling element.

When signal transmission is performed by magnetic coupling, for example, the coil on the transmitting chip side and the coil on the receiving chip side may be arranged so as to be magnetically coupled. Alternatively, a coil may be provided on the transmitting chip side, and a resistance bridge circuit or a magnetoresistive element may be provided on the receiving chip side.

When signal transmission is performed by capacitive coupling, for example, a capacitor may be provided between the transmitting chip and the receiving chip, one electrode of this capacitor may be connected to the transmitting chip, and the other electrode may be connected to the receiving chip. Good.

Even in an insulating device that transmits signals by magnetic coupling or capacitive coupling, on the data transmission side, the data is a differential Manchester-encoded signal that changes levels in a short time, or modulated OK (On-Off Keying). ) It is transmitted by a signal or the like. On the other hand, on the data receiving side, the received data is oversampled by the first sampling circuit 711 and the second sampling circuit 713 at different timings and at twice the sampling frequency. After that, the sample data of each sampling circuit is determined by the determination circuit 714.

The determination data A of the determination circuit 714 corresponds to the presence or absence of a level transition of the received data D2 immediately before the sample data of the first sampling circuit 711, in other words, the reliability of the sample data. Therefore, by decoding highly reliable sample data, it is possible to make it difficult for data errors to occur on the receiving side.

Further, by using the clock Ck3, the second sampling circuit 812 can oversample the light receiving data D2 whose timing is earlier than that of the first sampling circuit 811. After that, as in the first embodiment, highly reliable data is selected and decoded. Therefore, it goes without saying that it is possible to make it difficult for data errors to occur on the receiving side.

FIG. 10 is a schematic block diagram of the semiconductor device according to the third embodiment. In FIG. 10, the same components as those of the semiconductor device 1 according to the first embodiment described above are designated by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 10, the semiconductor device 3 according to the present embodiment is the first embodiment in that the first coupler unit 130 and the second coupler unit 160 are provided in place of the first photocoupler 3 and the second photocoupler 6. It is different from the semiconductor device 1 according to the embodiment. Here, a circuit example of the first coupler unit 130 and the second coupler unit 160 will be described with reference to FIGS. 11 (a) to 11 (c).

In the first coupler unit 130 shown in FIG. 11A, a transmission coil 131a is provided in place of the light emitting element 31 of the first photocoupler 3, and a reception coil 132a is provided in place of the light receiving element 32. Further, in the second coupler unit 160 shown in FIG. 11A, a transmission coil 161a is provided in place of the light emitting element 61 of the second photocoupler 6, and a reception coil 162a is provided in place of the light receiving element 62. There is.

In the first coupler unit 130 shown in FIG. 11B, a transmission coil 131b is provided in place of the light emitting element 31, and a magnetoresistive element 132b is provided in place of the light receiving element 32. Further, in the second coupler unit 160 shown in FIG. 11B, a transmission coil 161b is provided in place of the light emitting element 61, and a magnetoresistive element 162b is provided in place of the light receiving element 62.

The first coupler unit 130 shown in FIG. 11C is provided with a capacitive coupling element 130c instead of the light emitting element 31 and the light receiving element 32, and the second coupler unit 160 is provided with a capacitive coupling element 160c as a light emitting element 61. And is provided in place of the light receiving element 62.

In the first coupler unit 130 and the second coupler unit 160 shown in FIGS. 11 (a) to 11 (c), passive elements such as each coil, each magnetic resistance element, and each capacitance coupling element are on a frame (not shown). Insulated by, it is electrically connected to any one of the coding circuit 5, the demodizing circuit 7, the frequency conversion circuit 2, and the ADC 4. Further, these passive elements may be arranged individually, or may be arranged as semiconductor chips mixedly mounted on each of the above circuits. In the semiconductor device 3 according to the present embodiment, the semiconductor chip on the data transmission side (primary side) and the semiconductor chip on the data reception side (secondary side) are connected to each other via the first coupler unit 130 and the second coupler unit 160. The space is galvanically insulated.

Further, in the first coupler unit 130 and the second coupler unit 160, the transmission chip including the transmission circuit and the reception chip including the reception circuit are insulated and arranged on the frame. A laminated body of insulated passive elements such as the coil and the capacitive coupling element is integrated on the receiving chip or the transmitting chip. Further, the case where the first coupler unit 130 and the second coupler unit 160 are coupled to the transmission / reception chip as independent elements is also included. Further, these transmission / reception chips are connected to the frame with wires and sealed with resin.

The transmission / reception chip is covered with, for example, an encap resin made of silicone gel or silicone rubber. Further, it is sealed with a mold resin in addition to the encap resin to form a semiconductor device. It is desirable that the thickness of the encap resin is substantially the same amount and thickness from the viewpoint of ensuring the same operation of circuits such as reference voltage generation circuits provided in the transmission / reception circuits.

Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, as well as in the scope of the invention described in the claims and the equivalent scope thereof.

1 Semiconductor device, 3 1st photocoupler, 5 coding circuit, 6 2nd photocoupler, 7 demodulator circuit, 72 selection circuit, 73 decoding circuit, 711 first sampling circuit, 712 delay circuit, 713 second sampling circuit, 714 Judgment circuit, 721 first storage circuit, 722 second storage circuit, 723 third storage circuit, 724 comparison circuit

Claims (9)

1st coupler part and
A coding circuit that differentially Manchester-codes digital data based on the clock input via the first coupler unit and outputs the coded data.
The second coupler part and
A demodulation circuit for demodulating the coded data input via the second coupler unit is provided.
The demodulation circuit
A first sampling circuit that samples the coded data and outputs the first sample data based on a sampling frequency set to twice the frequency of the coded data.
Based on the sampling frequency, a second sampling circuit that samples the coded data at a timing earlier than the first sampling circuit and outputs the second sample data.
A determination circuit for determining whether or not the first sample data and the second sample data match.
A selection circuit that selects either the even-numbered sampled first phase data or the odd-numbered sampled second phase data from the first sample data based on the determination data of the determination circuit. And, including, semiconductor devices. The semiconductor device according to claim 1, wherein the demodulation circuit is provided in front of the second sampling circuit and includes a delay circuit set to a delay time shorter than a sampling period which is the reciprocal of the sampling frequency. The first sampling circuit samples the coded data based on the first sampling clock set at the sampling frequency.
The semiconductor device according to claim 1, wherein the second sampling circuit samples the coded data based on the second sampling clock obtained by inverting the first sampling clock. The selection circuit
A first storage circuit that stores a plurality of the first sample data according to the sampling order, and
A second storage circuit that temporarily stores the determination data corresponding to the first sample data, and
Includes a third storage circuit that temporarily stores a flag indicating whether the selection circuit selects the first phase data or the second phase data.
The semiconductor device according to any one of claims 1 to 3, wherein the flag is switched when the determination data indicates a mismatch between the first sample data and the second sample data. The selection circuit includes a comparison circuit connected to the first storage circuit.
When the flag is switched, the comparison circuit is of a plurality of the first sample data stored in the first storage circuit before the error data which is the first sample data that does not match the second sample data. The semiconductor device according to claim 4, wherein sample data sampled in different orders are compared with each other, and either the first phase data or the second phase data is selected based on the comparison result. The first storage circuit stores at least five different first sample data, the first to fifth storage data, sampled prior to the error data.
In the comparison circuit, when the first storage data and the second storage data do not match, or when the first to third storage data match and the third storage data and the fourth storage data do not match. The semiconductor device according to claim 5, wherein in some cases, the first storage data sampled immediately before the error data and stored in the first storage circuit is selected. The first storage circuit stores at least five different first sample data, the first to fifth storage data, sampled prior to the error data.
In the comparison circuit, when the first storage data and the second storage data match and the second storage data and the third storage data do not match, or when the first to fourth storage data match. In claim 5, when the fourth storage data and the fifth storage data do not match, the first sample data sampled immediately after the error data and stored in the first storage circuit is selected. The described semiconductor device. The semiconductor device according to any one of claims 1 to 7, wherein the determination circuit includes an XOR circuit connected to the first sampling circuit and the second sampling circuit, respectively. The semiconductor device according to claim 4, wherein the selection circuit selects the phase data set in the flag when the determination data indicates a match between the first sample data and the second sample data.

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