JP5388196B2 - DC balanced code generation circuit, serial data transmission apparatus, DC balanced code generation method, program thereof, and recording medium - Google Patents

Description

  The present invention relates to a DC balanced code generation circuit, a serial data transmission device, a DC balanced code generation method, a DC balanced code generation program, and a program recording medium, and in particular, transmits by an AC-coupled transmission line insulated by a pulse transformer, a capacitor, and the like. The present invention relates to a serial digital data transmission system.

  In recent years, with the development of transmission and coding technologies between communication networks and communication devices and between main devices and terminals in telephone devices, DC-balanced states are considered as AC-coupled serial data transmission devices using pulse transformers, etc. Transmission methods called AMI (Alternate Mark Inversion) code, CMI (Code Mark Inversion) code, and Manchester code have been put into practical use.

  For example, a circuit configuration as shown in FIG. 10 is used as a DC balanced code generation circuit using an AMI code. FIG. 10 is a block diagram showing a block configuration of a conventional AMI code generation circuit, which includes a data memory 5, a shift register 6, an AMI encoding unit 7, a DC balanced bit generation / holding unit 8, and a parity check calculation unit 9. The AMI encoding unit 7 is configured to output the data “0” as 0V and the polarity of the data “1” alternately as the AMI code serial data output 10 in consideration of the DC balanced state. ing.

  FIG. 11 is a circuit diagram illustrating a circuit configuration of an AMI encoding unit included in the AMI code generation circuit of FIG. 10, and is generally configured by an LSI (Large Scale Integrated circuit), and the LSI. As an internal circuit, D flip-flops 11 and 12, selector 13, AND gates 18 and 19 are input, serial data 14 and clock 15 are inputted, and positive sign output terminal 16 to which outputs of AND gates 18 and 19 are connected. From the negative sign output terminal 17, positive and negative AMI codes are output as the AMI code serial data output 10.

  As the LSI of the AMI encoding unit 7, any semiconductor device such as ASIC (FPGA, gate array, endbed array, cell base, full custom), SoC (System on Chip), and dedicated LSI may be applied. Absent. Further, normally, a pulse transformer is directly connected to the two terminals of the positive sign output terminal 16 (V +) and the negative sign output terminal 17 (V−) for outputting the AMI code serial data output 10 as shown in FIG. The

  Further, in Japanese Patent Laid-Open No. 2004-187117 “Serial Data Communication Method” shown in Patent Document 1, it is possible to reduce the cost by a simple circuit configuration without performing complicated encoding processing as in the AMI code generation circuit. A code generation method capable of preventing magnetic saturation of the pulse transformer has been proposed. FIG. 15 is a block diagram showing a block configuration of the communication interface circuit of the prior art described in Patent Document 1, and shows a state in which the communication interface circuits 50 and 60 are connected to each other via the transmission line 70. Yes.

  In FIG. 15, communication interface circuits 50 and 60 have the same block configuration, and are respectively UART (Universal Asynchronous Receiver Transmitter) circuits 51 and 61 for converting 8-bit parallel data into an asynchronous serial data format. LVDS (low voltage differential signaling) D / R (driver / receiver) line transceivers 52 and 62 for data transmission, pulse transformers 53 and 63, and other resistors and capacitors not shown The UART circuits 51 and 61 are connected to control devices 55 and 65 that input and output data to be transmitted and received, respectively.

  In the block configuration as shown in FIG. 15, the control devices 55, 65 transfer the bit data inverted every bit when transferring parallel data to be transmitted to the UART circuits 51, 61 or each bit per byte. Byte inversion data obtained by inverting the data is inserted into the transmission data and transferred to the UART circuits 51 and 61. Conversely, when the UART circuits 51 and 61 receive the reception data from the transmission line 70, each bit or 1 The bit-reversed data or byte-reversed data inserted for each byte is removed and captured. Thus, magnetic saturation of the pulse transformers 53 and 63 is prevented, and transfer data on the transmission line 70 transferred via the pulse transformers 53 and 63 is transmitted and received as a DC balanced code.

JP 2004-187117 A (page 4-6)

  However, in the conventional DC balanced code generation circuit and DC balanced code generation method, it is necessary to generate a data code or a DC balanced bit that alternates between positive and negative potentials, resulting in a complicated circuit configuration or positive / negative output. There is a problem that the waveforms become asymmetric and all become H level at the same time point, and in some cases, the collision of the H levels may cause circuit destruction.

  For example, in the case of the AMI code generation circuit described above with reference to FIGS. 10 and 11, the positive AMI code output (V +) and the negative code output output from the positive code output terminal 16 as shown by the broken line portion of the timing chart of FIG. A state occurs in which the negative AMI code output (V−) output from the terminal 17 becomes H level at the same timing. FIG. 12 is a timing chart showing signal waveforms in the respective circuits of the AMI encoding unit 7 of FIG.

  That is, as shown in FIG. 11, when a pulse transformer is directly connected to the two terminals of the positive sign output terminal 16 and the negative sign output terminal 17 of the AMI encoding unit 7, they are input to the AND gates 18 and 19. A positive AMI code output (V +) output from the positive sign output terminal 16 and a negative AMI code output (V−) output from the negative sign output terminal 17 due to a slight shift in data input timing, that is, a circuit timing hazard. However, as shown in the enlarged broken line portion in FIG. 12, when data “1” continuously occurs, output collisions that are both at the H level are likely to occur at the same timing, and thus, positive and negative output collisions. When this occurs, the two output voltages may be added instantaneously, resulting in a voltage exceeding the maximum rating, which may cause destruction or deterioration of the output circuit element or output terminal. .

  Furthermore, in the AMI code generation circuit as shown in FIGS. 10 and 11, there is data (that is, data “0”) in which the waveform of the signal transferred on the transmission line does not change. As described above, when the data “0” in which the signal waveform does not change in the AMI code continues to “ALL” “0” DATA (no change signal state), as shown in FIG. The data transferred on the line is easily affected by external induction noise.

  FIG. 13 is an explanatory diagram for explaining a situation where data without a change in signal waveform continues. FIG. 13A shows data '0 with no change in signal waveform as an asynchronous AMI code. FIG. 13B shows a state in which external induction noise occurs. As shown in FIG. 13B, when ALL'0 'DATA (no change signal state) continues as data sandwiched between start-stop bits (fixed to' 1 '), the worst DC balanced bit Until this occurs, the current flowing through the pulse transformer decreases, the transmission line potential between the two wires on the primary side of the pulse transformer becomes 0V, and it is easy to cause data errors and malfunctions due to external induction noise. It tends to occur.

  The Manchester code, which is one of the conventional DC balanced codes, is a code for converting data “0” into a 2-bit code of “01” and data “1” into “10”. In addition, it is difficult to embed a violation bit indicating the beginning of valid data. Therefore, in the Ethernet standard (registered trademark) 10BASE-T using the Manchester code, there is no violation flag as shown in FIG. 14, and instead, the head of data is identified at the start of data communication. In addition, a character-synchronous method is adopted by additionally inserting a preamble (56 bits) and a start frame (8 bits). FIG. 14 is an explanatory diagram showing the Manchester code adopted in the Ethernet standard 10BASE-T and the code format for data synchronization detection.

  Further, in the code generation method in Patent Document 1 using the communication interface circuit as shown in FIG. 15, at the time when valid data is transmitted and received, each bit is inverted every bit or every bit is inverted. The byte-inverted data thus transferred is inserted into the transmission data and transferred. On the other hand, in a standby state where no valid data is transmitted / received, the output signals of the UART circuits 51 and 61 are fixed to ALL'1 '. It becomes a state.

  Therefore, in the standby state, as shown in FIG. 16, for example, the output signal of the UART circuit 51 of the communication interface circuit 50 continues to be in the H level state of ALL′1 ′. The signal current on the primary side of the pulse transformer 63 disappears, and the input to the positive sign side terminal (+) and the input to the negative sign side terminal (−) of the line transceiver 62 changes to the same potential. It will be. FIG. 16 is an explanatory diagram for explaining a potential level in a standby state in the communication interface circuit of FIG. When the input potential of the positive sign side terminal (+) and the negative sign side terminal (−) of the receiving side line transceiver 62 becomes the same potential level in the standby state, a start bit arrives when some inductive noise occurs. The problem of misdetecting it as having occurred.

  Further, when new data transmission starts before the input potentials of the positive sign side terminal (+) and the negative sign side terminal (−) of the line transceiver 62 on the receiving side become the same potential, the base line (center potential) is changed. There is also a problem that the data signal changes with the shift, the reception line transceiver 62 is likely to receive a reception error, and the DC balance cannot be maintained.

(Object of the present invention)
The present invention has been made in view of the above problems, and its object is to provide a DC balanced code that enables a more complete DC balanced transmission with a circuit configuration that is simpler than the conventional transmission system. A DC balanced code generating circuit, a serial data transmission device, a DC balanced code generating method, a DC balanced code generating program, and a program recording medium are provided. In addition, in AC-coupled LVDS (low voltage differential signaling) transmission, by ensuring a DC balanced state, a reception error due to external induction noise hardly occurs even for a pseudo NRZ (Non Return to Zero) code signal. It is an object to provide a DC balanced code generation circuit, a serial data transmission device, a DC balanced code generation method, a DC balanced code generation program, and a program recording medium.

  In other words, the present invention makes it possible to ensure a complete DC balanced state, and to increase the DC balanced bit on the transmission code while taking the DC balanced state into consideration compared to the prior art, thereby enabling DC balanced digital transmission. DC balance codes to be generated can be generated with a simplified circuit, and a violation flag indicating the beginning of data can be embedded, and output collisions on the transmission output waveform due to circuit timing hazards Even if it is completely removed and all data is '0' or '1', or even in a standby state where there is no valid data, an AC signal is always generated as a DC balanced code and is supplied to the pulse transformer. The purpose is to enable strong transmission against induced noise by continuing to pass current.

  In order to solve the above-described problem, the DC balanced code generation circuit according to the present invention employs the following characteristic configuration.

  (1) In a DC balanced code generation circuit that generates code data to be transmitted as serial data in a DC balanced state via a transmission line that is AC coupled by a pulse transformer or a capacitor, The distance from the positive sign output terminal of the front-stage circuit that sequentially outputs the sign data as serial data in a DC balanced state to the positive sign output terminal connected to the pulse transformer or capacitor and the negative sign of the front-stage circuit A DC balanced code generation circuit that makes the distance from the output terminal to the negative sign output terminal connected to the pulse transformer or capacitor the same length.

  According to the DC balanced code generation circuit, serial data transmission apparatus, DC balanced code generation method, DC balanced code generation program, and program recording medium of the present invention, the following effects can be obtained.

  The first effect is that in the DC balanced code generation circuit according to the present invention, the positive code serial data on the positive code output terminal side to the AC coupling pulse transformer connected to the transmission line for transmitting DC balanced serial data. It is possible to avoid collision of H level output at the same timing between (V +) and the negative sign serial data (V−) on the negative sign output terminal side. The reason for this is that the circuit length from the positive sign side output terminal to the positive sign output terminal of the circuit at the front stage of the shift register that generates DC balanced serial data (that is, the D flip-flop at the front stage) and the negative sign side output terminal This is because a DC balanced code generation circuit is formed in which the wiring length to the negative sign output terminal is set to the same length.

  Thus, even if the pulse transformer is directly connected between the positive sign output terminal and the negative sign output terminal of the DC balanced code generation circuit according to the present invention, the positive sign serial data (V +) and the positive sign serial are connected. It is possible to match the delay time with the data (V +), and the two output voltages of the positive sign serial data (V +) and the positive sign serial data (V +) are added in the same direction, so that it exceeds the maximum rating. A situation in which a voltage is generated can be reliably prevented, and destruction and deterioration of the output circuit element and the output terminal can be avoided.

  Also, the wiring length from the positive sign side output terminal to the positive sign output terminal of the first stage circuit (that is, the first stage D flip-flop) of the shift register that generates DC balanced serial data and the negative sign output from the negative sign side output terminal By setting the wiring length to the terminal to the same length, it is easy to set the timing specification between the output buffer at the final stage of the DC balanced code generation circuit and the internal frontmost gate with respect to the clock. The effect of becoming is also obtained.

  The second effect is that the circuit configuration of the DC balanced code generating circuit according to the present invention is greatly simplified as compared with a DC balanced code generating circuit such as a conventional AMI code. The reason for this is that the DC balanced code generation circuit according to the present invention uses a D flip-flop in which DC balanced bits and data bits generated by inverting data bits traced back by a predetermined number of bits are connected in multiple stages. This is because a circuit configuration that is alternately embedded is employed.

  Thus, the DC balanced code generation circuit according to the present invention includes a DC balanced bit generation holding unit 8 and a DC balanced bit for holding a DC balanced bit as in the conventional AMI code generating circuit as shown in FIG. The parity check calculation unit 9 is not required to calculate the above, and can be operated without considering the operation timings of the two circuits of the DC balanced bit generation holding unit 8 and the parity check calculation unit 9. The circuit can be simplified.

  The third effect is that even if all the data to be transmitted is “0” or “1”, or even in a standby state where no valid data is generated, it is difficult to be affected by inductive noise and reception. It is difficult for errors to occur. The reason is that a change in the voltage amplitude waveform between the two transmission lines always occurs even when all the data to be transmitted is “0” or “1” or in a standby state. Because.

  That is, in the DC balanced code generation circuit according to the present invention, the valid data to be transmitted is ALL'0 ', ALL'1', random data, or a standby state without valid data. However, no matter what period the signal on the transmission line is extracted, a DC balanced state is always ensured on the transmission line, and the change of the sign, that is, the change of the voltage amplitude waveform is not interrupted. The code configuration is such that transmission signal errors are less likely to occur due to noise.

  The fourth effect is that a violation flag indicating the start of data communication can be embedded, and complete DC balance can be secured. The reason is that complete DC balanced serial data can be generated for any data.

  Thus, unlike the conventional Manchester code, it is not necessary to provide a 56-bit length preamble code or an 8-bit start frame at the start of data transmission and adopt a character-synchronous method. However, higher-speed data transfer can be performed.

  The fifth effect is that the standby state DC balance problem and malfunction due to induction noise in Patent Document 1 can be reliably prevented. The reason for this is that, as described above, in the DC balanced code generation circuit according to the present invention, even in a standby state where there is no valid data, a DC balanced state is always ensured on the transmission line, and the code change, that is, Since the change in the voltage amplitude waveform is not interrupted, the start bit is not erroneously detected, and the base line (center potential) during data transmission is not shifted. This is because the code configuration is less likely to occur.

It is a block diagram which shows an example of a structure of the direct current | flow balanced code generation circuit which concerns on this invention. FIG. 2 is a circuit diagram showing an example of a circuit configuration of a half shift register on the front stage side among the shift registers constituting the DC balanced code generation circuit of FIG. 1. 3 is a timing chart showing an example of operation timing of a shift register including a front-stage 8-bit shift register circuit of FIG. 2 and a back-stage 8-bit shift register circuit (not shown). FIG. 16 is a block diagram showing an example of a block configuration in which a DC balanced code generation circuit according to the present invention is applied to the conventional communication interface circuit of FIG. 15. FIG. 5 is an explanatory diagram for explaining transmission codes in a standby state in the communication interface circuit of FIG. 4. 3 is an explanatory diagram showing an example of a signal waveform of code data generated when transfer data is ALL '0' data in the DC balanced code generation circuit of FIGS. 1 and 2. FIG. FIG. 3 is an explanatory diagram illustrating an example of a signal waveform of code data generated when transfer data is random data in the DC balanced code generation circuit of FIGS. 1 and 2. FIG. 3 is an explanatory diagram illustrating an example of an insertion state of a violation flag indicating the head of valid data for transfer in the DC balanced code generation circuit of FIGS. 1 and 2. It is a block block diagram which shows an example of the serial data transmission apparatus to which the direct current | flow balanced code generation circuit shown in FIG. 1 and FIG. 2 is applied. It is a block diagram which shows the block configuration of the conventional AMI code generation circuit. FIG. 11 is a circuit diagram illustrating a circuit configuration of an AMI encoding unit included in the AMI code generation circuit of FIG. 10. 12 is a timing chart illustrating signal waveforms in each circuit of the AMI encoding unit in FIG. 11. It is explanatory drawing for demonstrating the condition when the data without a change of a signal waveform continue in the conventional AMI code generation circuit. It is explanatory drawing which shows the Manchester code | symbol employ | adopted as Ethernet standard 10BASE-T, and the code | symbol format for a data synchronous detection. FIG. 11 is a configuration diagram showing a block configuration of a communication interface circuit of a conventional technique described in Patent Document 1. FIG. 16 is an explanatory diagram for explaining a potential level in a standby state in the communication interface circuit of FIG. 15.

  Hereinafter, preferred embodiments of a DC balanced code generation circuit, a serial data transmission device, a DC balanced code generation method, a DC balanced code generation program, and a program recording medium according to the present invention will be described with reference to the accompanying drawings. In the following description, a DC balanced code generation circuit, a serial data transmission apparatus, and a DC balanced code generation method according to the present invention will be described. As a DC balanced code generation program that can be executed by a computer, the DC balanced code generation method is described. Needless to say, the DC balanced code generation program may be recorded on a computer-readable recording medium.

(Features of the present invention)
Prior to the description of the embodiments of the present invention, an outline of the features of the present invention will be described first. The present invention provides a DC balanced state on the transmission line regardless of the presence or absence of valid data to be transmitted and regardless of the data content to be transmitted (ALL'0 ', ALL'1', random data, etc.). Is always ensured, and the code is generated so that the change of the sign, that is, the change of the voltage amplitude waveform is not interrupted. That is, the data obtained by inverting the bit at the timing that goes back by a predetermined number of bits (the signal level at the timing that goes back by a predetermined time regardless of valid data) is used as a DC balanced code for each bit (effective data). The LSI circuit is configured such that the distance from the first stage circuit that outputs positive and negative DC balanced serial data to the positive and negative output terminals is the same distance. It is characterized by that.

  As described above, in the case of the conventional AMI code, if no signal state such as ALL '0' continues, the current flowing through the pulse transformer decreases until the DC balanced bit is generated, and the primary side of the pulse transformer is reduced. The potential between the two transmission lines becomes 0V, and it is easy to cause data errors and malfunctions due to external induction noise. However, the DC balanced code generation circuit, serial data transmission device, DC balanced code generation method, DC balanced code according to the present invention In the generation program and the program recording medium, NRZ (Non Return to Zero) data in a DC balanced state by a single power source can be transmitted and received in a pseudo manner. High-speed transmission with high reliability by voltage differential signaling) transmission method is possible.

  In other words, in the present invention, even if all data is “0” or “1” or in a standby state, an alternating current signal is always generated and current continues to flow through the pulse transformer, etc. A transmission system that is resistant to inductive noise. In the case of a circuit configuration in which a pulse transformer is directly connected to the positive and negative output terminals by aligning the wiring distance from the first stage circuit that outputs positive and negative DC balanced serial data to the positive and negative output terminals to the same length. Even so, the positive and negative DC balanced serial data signals output from the positive and negative output terminals are driven in the same phase, and the primary side of the pulse transformer is driven. It is possible to reliably prevent such a situation, and it is possible to avoid destruction and deterioration of the output circuit element and the output terminal.

  Furthermore, in the case of the AMI code generation circuit of the prior art, as shown in FIG. 10, the data memory 5, the shift register 6, the AMI encoding unit 7, the DC balanced bit generation holding unit 8, the parity check calculation unit 9, The circuit of the AMI encoding unit 7 and the circuit of the DC balanced bit generation / holding unit 8 are complicated, and circuits such as the DC balanced bit generation / holding unit 8 and the parity check calculation unit 9 are provided. It was essential. However, in the DC balanced code generation circuit according to the present invention, the DC balanced bit generation holding unit 8 and the parity check calculation unit 9 are not necessary, and it is necessary to have a complicated circuit configuration like the circuit of the AMI encoding unit 7. In addition, even a simpler circuit can generate a code that enables DC balanced transmission.

[Description of configuration]
Next, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing an example of the configuration of a DC balanced code generation circuit according to the present invention, and shows an example of the overall configuration of a DC balanced code generation circuit that generates a new code according to the present invention. The DC balanced code generation circuit of FIG. 1 includes at least a data memory 1, a shift register 2, and a front 2-bit data latch circuit 3, and parallel data output from the data memory 1 has a shift register 2 that sequentially shifts by 1 bit, The data of 2 bits in the previous time slot that is input to the previous 2-bit data latch circuit 3 that latches 2-bit data of 2 bits before and 1 bit before is also shifted. It is input to a predetermined position of the register 2.

  As a result, the DC balanced code generation circuit of FIG. 1 uses the shift register 2 to transfer the transfer data 2 bits before the data (transfer data) at each bit position of the parallel data output from the data memory 1. The inverted inverted data can be inserted as the DC balanced data bit by bit between the data for transfer. Thus, the parallel data output from the data memory 1 is added with the DC balanced data in the shift register 2. It has a function of converting it into serial data and outputting it as a code serial data output 4. In the present embodiment, an example is shown in which the inverted data of the transfer data of 2 bits before is used as the DC balanced data. However, the inverted data obtained by inverting the transfer data at the bit position going back by a predetermined number of bits is used. These are used as DC balanced data, and may be alternately arranged before or after each bit of transfer data.

  Here, the shift register 2 of FIG. 1 has a circuit configuration as shown in FIG. 2 is a circuit diagram showing an example of the circuit configuration of the half-stage shift register located on the output end side of the shift register 2 constituting the DC balanced code generation circuit of FIG. 4 bits from B7 to B4 from 1 and 2 bits B1 and B0 bits on the LSB (Least Significance Bit) side of the previous time slot (previous data) from the previous 2-bit data latch circuit 3, and a positive sign output terminal 28 and the negative sign output terminal 29 are provided with eight stages of 8-bit shift register circuits (that is, on the output stage side) that output the sign serial data output 4 (positive sign output (V +), negative sign output (V−)). An example of a half shift register) is shown.

  On the other hand, among the shift registers 2, the rear stage 8-bit shift register circuit located on the input stage side for inputting the 4 bits of B3 to B0 bits from the data memory 1 of FIG. It has the same circuit configuration, and the transfer data input selector in the preceding 8-bit shift register circuit of FIG. 2 uses B3 to B0 bit instead of B7 to B4 bit, and the inverting gate for DC balanced data input. Is configured to input B5 to B2 bits instead of B1, B0 bits, B7 and B6 bits of the previous two bits. Note that the output of the front-stage D flip-flop of the subsequent 8-bit shift register circuit is input to the next-stage D flip-flop, as shown in FIG. It is input to the D flip-flop via the selector. That is, the shift register 2 has a function of latching data having a bit number twice as many as the number of bits of a valid data time slot to be transferred to the other side (8 bits in this embodiment) and shifting the data bit by bit. The shift register 2 is configured as a 16-bit shift register, and 8-bit DC balanced data and 8-bit transfer data are alternately arranged and sequentially output from the shift register 2 as the code serial data output 4.

  Here, the preceding 8-bit shift register circuit of FIG. 2 is supplied from 8-stage D flip-flops 20, 21, 22,..., 27 that alternately latch transfer data and DC balanced data, and from the preceding stage D flip-flop. Selectors 33, 34, 35,..., 40 for switching and inputting the output and transfer data (or DC balanced data) from the data buffer 1 or the previous 2-bit data latch circuit 3, and inverting input for generating DC balanced data Inverting gates 41, 42, 43, and 44 are configured.

  Here, transfer data B7, B6, B5, and B4 bits are input to the D input terminals of the D flip-flops 21, 23, 25, and 27 via the selectors 34, 36, 38, and 40, respectively. At the D input terminals of the groups 20, 22, 24, and 26, the previous time slots B1 and B0 of the DC balanced data and the current time slots B7 and B6 bits are inverted by the inverting gates 41, 42, 43, and 44, respectively. Thereafter, the data is input via selectors 33, 35, 37, and 39, respectively.

  That is, the D input terminals of the D flip-flops 20 and 22 receive B1 bit data of the previous time slot (previous data) from the previous data 2 bit data latch circuit 3 via the inverting gates 41 and 42 and the selectors 33 and 35, respectively. Inversion of B0 bit data is loaded as a DC balanced bit.

  Further, the D input terminals of the D flip-flops 24 and 26 are inverted through the inversion gates 43 and 44 and the selectors 37 and 39, respectively, for inversion of B7 bit data and B6 bit data in the present time slot (present data). Loaded as a DC balanced bit.

  In addition, the D input terminals of the D flip-flops 21, 23, 25, and 27 receive B7 bit data and B6 bit data of the current time slot (present data) from the data memory 1 via selectors 34, 36, 38, and 40, respectively. , B5 bit data, and B4 bit data are loaded as transfer data.

  The pre-stage 8-bit shift register circuit shown in FIG. 2 starts the shift register operation after loading of all data, and sets the DC flip-flop 20 as the front-stage circuit in the order of the DC balanced bit and the transfer data one bit at a time. After being output as positive code serial data and negative code serial data from the code output terminal and the negative code output terminal, respectively, it is serially output as the code serial data output 4 from the positive code output terminal 28 and the negative code output terminal 29.

  FIG. 3 is a timing chart showing an example of the operation timing of the shift register 2 composed of the preceding-stage 8-bit shift register circuit of FIG. 2 and the not-shown latter-stage 8-bit shift register circuit, and shows the previous time slot (previous data). Including the latch status in the 2-bit data latch circuit 3 before latching the LSB side 2-bit B1 and B0-bit data from the bit position retroactive by a predetermined number of bits, for example, LSB (Least Significance Bit). The D flip-flop 20 shows that DC balanced data (that is, inverted data of transfer data before 2 bits) and transfer data are alternately output as the code serial data output 4.

  As shown in FIG. 3, two bits B1 and B0 on the LSB side of the previous time slot (previous data) alternately latched in the D flip-flops 20 to 27 by the shift register data load signal 31 (SHIFT REG DATA LOAD). Inverted data, DC balanced data which is 6 bits of B7 to B2 inverted data on the MSB side of the current time slot (present data), and transfer data B7 to B0 of the current time slot (present data) are clock signal 32 ( In response to (CLOCK), the signals are sequentially output from the D flip-flop 20 at the front stage.

  That is, as shown in the output of the D flip-flop 20 in the forefront stage, in the order of the DC balanced bit (DC BIT) and the transfer data (VALID DATA), Previous B1 (INV), B7 (DAT), and Previous B0 (INV). , B6 (DAT), B7 (INV), B5 (DAT), B6 (INV), B4 (DAT), B5 (INV), B3 (DAT), B4 (INV), B2 (DAT), B3 (INV) , B1 (DAT), B2 (INV), and B0 (DAT) are serially output bit by bit. That is, data obtained by inverting the transfer data (VALID DATA) two bits before is output as the DC balanced data (DC BIT) before the transfer bits (VALID DATA) after two bits.

  Here, as shown in the positive sign output terminal 28, in FIG. 3, the data of the LSD side 2 bits B1 and B0 bits of the previous time slot (Previous Data) is “00” (inverted data is “11”). The case where the data of 8 bits B7 to B0 bits of the current time slot (Present Data) is “00111011” is illustrated. From the negative sign output terminal 29, output data obtained by inverting the output data from the positive sign output terminal 28 is output in phase with the output data from the positive sign output terminal 28, and the positive sign output terminal 28 and the negative sign output terminal 29 are output. The code serial data output from each is output to an AC-coupled transmission line via a pulse transformer, and at the timing indicated by the reception side clock signal (RECEIVING CLOCK FOR SERIAL DATA) in FIG. Will be captured.

  Further, as described above, the distance from the positive output terminal of the D flip-flop 20 at the front stage to the positive sign output terminal 28 and the distance from the negative output terminal to the negative sign output terminal 29 have the same length. Thus, the output data of the positive sign output terminal 28 and the output data of the negative sign output terminal 29 are always at different levels, such as at the locations surrounded by the dashed circles in FIG. Even if the pulse transformer is directly connected to the plus sign output terminal 28 and the minus sign output terminal 29, the pulse transformer has an abnormality exceeding the rated value. The configuration is such that no voltage is generated.

[Description of operation]
Next, an overall block diagram of a new code circuit, that is, a DC balanced code generation circuit according to the present invention in FIG. 1, a detailed circuit diagram of a preceding 8-bit shift register circuit of the shift register 2 in FIG. 2, and a timing of the shift register 2 in FIG. The operation of the serial data transmission apparatus employing the DC balanced code generation circuit according to the present invention will be described with reference to the chart.

  In the timing chart of FIG. 3, at the timing when the shift register data load signal 31 (SHIFT REG DATA LOAD) is at L level and the clock signal 32 (CLOCK) rises, all of the preceding 8-bit shift register circuit shown in FIG. The data output from the data memory 1 and the previous data 2-bit data latch circuit 3 in FIG. 1 are loaded to the D input terminals of the D flip-flops 20 to 27 via the selectors 33 to 40, respectively.

  Here, the D input terminals of the D flip-flops 20 and 22 are connected to the selectors 33 and 35 with the B1 bit data and the B0 bit data from the previous data 2 bit data latch circuit 3 inverted by the inverting gates 41 and 42, respectively. Thus, it is loaded as a DC balanced bit inserted before the transfer data B7 and B6 data.

  Further, the D input terminals of the D flip-flops 24 and 26 have transfer data via the selectors 37 and 39 in a state where the B7 bit and B6 bit data from the data memory 1 are inverted by the inversion gates 43 and 44, respectively. It is loaded as a DC balanced bit inserted before the B5 and B4 data.

  Further, B7, B6, B5, and B4 bit data from the data memory 1 are transferred to the D input terminals of the D flip-flops 21, 23, 25, and 27 through the selectors 34, 36, 38, and 40, respectively. Loaded as data.

  Also in the all D flip-flops of the rear stage 8-bit shift register circuit (not shown), B5-B2 bit data among the data from the data memory 1 is inverted by the inversion gate and transferred, as in the front stage 8-bit shift register circuit. The data is loaded as a DC balanced bit inserted before the data B3 to B0, and the data B3 to B0 is loaded as transfer data.

  The period when the shift register data load signal 31 (SHIFT REG DATA LOAD) is at the H level after the loading of all the data to the D input terminals of all the D flip-flops 20 to 27 of the preceding 8-bit shift register circuit shown in FIG. In addition, at the timing when the clock signal 32 (CLOCK) rises, the preceding 8-bit shift register circuit starts the shift register operation and precedes the DC balanced bit that is the inverted data output two bits before. In this state, the transfer data is serially output as the encoded serial data output 4 one bit at a time from the D flip-flop 20 at the front stage.

  Further, as described above, the distance from the positive sign output terminal 28 to the positive sign output terminal 28 and the negative sign output terminal 29 to the negative sign output terminal 29 of the D flip-flop 20 at the front stage is set to be the same distance. Therefore, the output data of the positive sign output terminal 28 and the output data of the negative sign output terminal 29 are always at different levels at the same timing, such as in a portion surrounded by a broken circle in FIG. It is configured not to cause a collision at the level of direction.

  In Patent Document 1 shown in the prior art, when valid data is transferred, an attempt is made to achieve a DC balanced state by inversion / non-inversion for every 1 bit or inversion / inversion for every 1 byte. In the standby state where “1” data continues to be output, as described above, the DC balance problem has not been solved, and it is not possible to ensure a DC balance state at the time when transfer of valid data starts. On the other hand, in the present embodiment, even in the standby state in which ALL '1' data continues, as shown in FIG. The bit position value ('1' data) that is traced back by a bit is inverted and inserted as DC balanced data, so that ALL'1 'data is transferred as a' 01 'signal, and DC in the standby state The equilibrium problem has been solved. Thus, the problem in Patent Document 1 is that the start bit is detected when inductive noise is generated at the input of the line transceiver 62 (LVDS) on the receiving side when the potential changes to the same potential. This solves the problem and realizes ideal balanced transmission in a transmission line that is AC-coupled with a pulse transformer, a capacitor, or the like.

  Further, in Patent Document 1, when transmission of new transfer data starts before the input of the receiving-side line transceiver 62 (LVDS) becomes the same potential, the base line (center potential) remains shifted. A change in the data signal is likely to cause a reception error of the line transceiver 62 and the DC balance cannot be maintained. However, as shown in FIG. By adding 64, the transmission code in the standby state can be stably propagated while maintaining the DC balanced state.

  That is, as shown in the communication interface circuits 50A and 60A in FIG. 4, the DC balanced code generation circuit of this embodiment as shown in FIG. 1 is additionally inserted in each of the conventional communication interface circuits 50 and 60 shown in FIG. Thus, as shown in the time chart of FIG. 5, the transmission code in the standby state in which the ALL “1” data continues can maintain the DC balanced state, and “0” and “ 1 'is transferred as alternately continuous code data, and it is possible to more reliably avoid the occurrence of a reception error due to induction noise and stably propagate to the communication interface circuit 60A on the reception side. 4 is a block diagram showing an example of a block configuration in which the DC balanced code generation circuit according to the present invention is applied to the conventional communication interface circuit of FIG. 15. The conventional communication interface circuits 50 and 60 of FIG. In this example, DC balanced code generation circuits 54 and 64 according to the present invention are additionally inserted between the UART circuits 51 and 61 and the line transceivers 52 and 62, respectively.

  FIG. 5 is an explanatory diagram for explaining transmission codes in a standby state in the communication interface circuit of FIG. As shown in FIG. 5, even in a standby state in which ALL '1' data continues, the DC balanced code generation circuit 54 additionally inserted between the UART circuit 51 and the line transceiver 52 of the communication interface circuit 50A on the transmission side Since 0 'and' 1 'are converted into alternately continuous code data and output as positive code output data and negative code output data from the line transceiver 52 (LVDS), in the communication interface circuit 60A on the receiving side, Stable code data can be received without causing a reception error due to induction noise, and the DC balanced code generation circuit 64 can correctly restore the original code format and output it to the UART circuit 61.

  In the DC balanced code generation circuit shown in FIGS. 1 and 2, as described above, the circuit is configured by alternately embedding DC balanced bits and transfer bits. In contrast, the wiring delay from the positive sign output terminal to the positive sign output terminal 28 of the front D flip-flop 20 and the wiring delay from the negative sign output terminal of the D flip-flop 20 to the negative sign output terminal 29 are made the same. As described above, even when the LSI of the DC balanced code generation circuit is generated and a configuration in which a pulse transformer is directly connected to the D flip-flop 20 outside the DC balanced code generation circuit LSI, the positive code output terminal 28 is used. Therefore, it is possible to reliably avoid an H level output collision in which both of the output data of the negative sign output terminal 29 become H levels at the same timing. And it has a configuration that can be. Furthermore, as a result, the timing specification for the clock signal between the final stage output buffer and the internal frontmost gate is easily set.

  Also, the DC balanced code generation circuit shown in FIGS. 1 and 2 has a simplified circuit configuration as compared with the block diagram of the conventional AMI code generation circuit of FIG. That is, the DC balanced code generation circuit shown in FIGS. 1 and 2 is configured by alternately embedding DC balanced bits and transfer bits, and is an essential parity in the AMI code generation circuit of FIG. A circuit for calculating a DC balanced bit such as the check calculation unit 9 is unnecessary, and further, no DC balanced bit generation / holding unit 8 is required, and two circuits of a parity check calculation unit 9 and a DC balanced bit generation / holding unit 8 are provided. It is possible to operate without considering the block timing operation.

  Furthermore, in the signal waveform of the conventional AMI coding method described above with reference to FIG. 13, there is a case where data without a change in the signal waveform continues (in the example of FIG. 13, data “0” is an unchanged signal state). Yes. If the non-change signal state continues like this, a transmission error is likely to occur when external induction noise occurs in the transmission line in which the pulse transformer is interposed. However, in the transmission method of the DC balanced code generation circuit shown in FIG. 1 and FIG. 2, even if all data (VALID DATA) is “0” as shown in FIG. 6, the DC balanced data (DC BIT) is used. The voltage amplitude between the two lines of the transmission line is generated by generating, as code data in which '1' is inverted by inverting the transfer data (VALID DATA) at a predetermined bit number, for example, 2 bits backward Therefore, even if inductive noise occurs, transmission errors are unlikely to occur. FIG. 6 is an explanatory diagram showing an example of a signal waveform of code data generated when the transfer data is ALL '0' data in the DC balanced code generation circuit of FIGS.

  Further, as shown in FIG. 7, even when the transfer data is random data (data “1011101” in the example of FIG. 7), the transfer is performed at a bit position retroactive by a predetermined number of bits, for example, 2 bits. Since data obtained by inverting the data for use (VALID DATA) is alternately inserted as DC balance data (DC BIT), the DC balance state is secured and the change of the sign is interrupted regardless of which period is extracted. Even if inductive noise occurs, transmission errors are unlikely to occur. FIG. 7 is an explanatory diagram showing an example of a signal waveform of code data generated when the transfer data is random data in the DC balanced code generation circuit of FIGS. 1 and 2.

  Further, in the conventional Manchester encoding system circuit, it is difficult to embed a violation bit indicating the start of effective data to be transmitted to the other party due to the characteristics of the receiving circuit. Therefore, in the Ethernet standard 10BASE-T using the Manchester code, as described above with reference to FIG. 14, at the start of transmission of valid data for transfer, a preamble code (56 bits) is used instead of the violation flag. A character-synchronized method of newly providing a start frame (8 bits) and notifying the other party is adopted. On the other hand, in the DC balanced code generation circuit of FIGS. 1 and 2, as shown in FIG. 8, the violation flag '10' is embedded and the violation flag is traced back by a predetermined number of bits, for example, 2 bits. In the form that uses '10', DC balance data is added in a format different from normal data, which makes it possible to indicate the beginning of valid data for transfer and ensure complete DC balance It is also possible to do. FIG. 8 is an explanatory diagram showing an example of an insertion state of a violation flag indicating the head of valid data for transfer in the DC balanced code generation circuit of FIGS. 1 and 2, and “10” as the violation flag (VIOLATION). The case of 2-bit violation with data inserted is illustrated.

  Next, as a specific embodiment, an example of a serial data transmission apparatus to which the DC balanced code generation circuit according to the present invention shown in FIGS. 1 and 2 is applied will be described with reference to FIG. FIG. 9 is a block diagram showing an example of a serial data transmission device to which the DC balanced code generation circuit shown in FIGS. 1 and 2 is applied. FIG. 9A shows a key telephone main device and an extension in the key telephone device. FIG. 9B shows a serial data transmission system between the basic rack and the extension rack in the button telephone apparatus.

  As shown in FIG. 9A, a configuration for transmitting a signal for serial data transmission between the key telephone main unit 81 to the digital extension terminal 82 via a pulse transformer, or as shown in FIG. A configuration in which the basic frame 83 of the device and the expansion frame 84 are added with a cable for LVDS (low voltage differential signaling) transmission AC-coupled with a pulse transformer or the like, or between network communication devices or between communication terminals and network communication devices The DC balanced code generation circuit according to the present invention as shown in FIG. 1 and FIG. 2 is applied as a serial data transmission device in a configuration in which a signal for high-speed serial communication is transmitted by connecting them via a pulse transformer. can do.

The configuration of the preferred embodiment of the present invention has been described above. However, it should be noted that such examples are merely illustrative of the invention and do not limit the invention in any way. Those skilled in the art will readily understand that various modifications and changes can be made according to a specific application without departing from the gist of the present invention. For example, the embodiment of the present invention can be expressed as the following configuration in addition to the configuration (1) in the means for solving the problems.
(2) A data memory that sequentially holds transfer data for each time slot, and a bit position of the previous time slot from a bit position of the previous time slot that is back by a predetermined number of bits of the transfer data from the data memory. A previous bit data latch circuit that holds data for the number of bits up to LSB (Least Significance Bit), the data for transfer from the data memory, and the number of bits in the previous time slot from the previous bit data latch circuit Data is input, DC balanced data is generated, and the generated DC balanced data is alternately inserted into each bit of the transfer data to convert it into the code data in the DC balanced serial data format. A shift register, and a circuit located at the forefront of the shift register The DC balanced code generation circuit according to (1), which is connected to the positive sign output terminal and the negative sign output terminal as a stage circuit.
(3) The shift register includes a circuit in which D flip-flops having the number of stages for latching data having the number of bits twice the number of bits of the time slot are connected in cascade, and the previous time slot from the previous bit data latch circuit D constituting the first stage circuit of the D flip-flop, with the inverted data obtained by inverting the data for the number of bits and the transfer data of the current time slot from the data memory as the DC balanced data Every other flip-flop is input via a selector for switching to the output from the next-stage D flip-flop, and the transfer data in the current time slot from the data memory is transferred to the D flip-flop. Among them, every other D flip-flop located in the next stage of the foremost stage circuit, DC balanced code generation circuit of the consisting of the circuit arrangement entered respectively through the selector for switching between output from stage D flip-flop (2).
(4) In a standby state where no valid data exists, the data memory operates to hold transfer data, and the DC balanced data and the transfer data are transferred from the front-stage circuit of the shift register. The DC balanced code generation circuit according to (2) or (3), wherein code data in which data is alternately inserted is output as serial data in a DC balanced state.
(5) The DC balanced code generation circuit according to any one of (2) to (4), wherein the number of bits of the previous time slot held by the previous bit data latch circuit is two bits.
(6) The DC balanced code generation circuit according to any one of (1) to (5), wherein a violation flag indicating the head of valid data to be transmitted to the other side is embedded in the head of the valid data.
(7) In a serial data transmission device that transmits serial data in a DC balanced state via a transmission line that is AC-coupled by a pulse transformer or a capacitor, as a DC balanced code generation circuit for generating the serial data in the DC balanced state A serial data transmission apparatus using the DC balanced code generation circuit according to any one of (1) to (6) above.
(8) As the serial data transmission device, a device that performs data transmission between the key telephone main device and the digital extension terminal, a device that performs data transmission between the basic frame of the key phone device and the extension rack, and a network communication device The serial data transmission apparatus according to (7), including at least one of an apparatus that performs data transmission between each other and an apparatus that performs data transmission between a network communication apparatus and a communication terminal.
(9) A DC balanced code generation method for generating code data for transmission as serial data in a DC balanced state via a transmission line AC-coupled by a pulse transformer or a capacitor, wherein the code data is in a DC balanced state DC balanced to make the delay time of the positive sign output data output from the positive sign output terminal of the front stage circuit sequentially output as serial data and the negative sign output data output from the negative sign output terminal of the front stage circuit the same Code generation method.
(10) The transfer data for each time slot and the bit number of the previous time slot from the bit position of the previous time slot that goes back by a predetermined number of bits from the transfer data to the LSB (Least Significance Bit) of the previous time slot Data is input to generate DC balanced data, and the generated DC balanced data is alternately inserted for each bit of the transfer data to generate the code data in the DC balanced serial data format. The DC balanced code generation method according to (9) above.
(11) The DC balanced code generation method according to (10), wherein as the DC balanced data, inverted data obtained by inverting the transfer data at each bit position that is traced back by a predetermined number of bits is used.
(12) The code data in which the DC balanced data and the transfer data are alternately inserted is output as DC balanced serial data in a standby state where no valid data exists. Or the DC balanced code generation method of (11).
(13) The DC balanced code generation method according to any one of (10) to (12), wherein the number of bits going back by a predetermined number of bits is 2 bits.
(14) The DC balanced code generation method according to any one of (9) to (13), wherein a violation flag indicating the head of valid data to be transmitted to the other side is embedded in the head of the valid data.
(15) As a DC balanced code generation program for generating code data for transmission as serial data in a DC balanced state via a transmission line AC-coupled by a pulse transformer or a capacitor, any of the above (9) to (14) A DC balanced code generation program that implements the DC balanced code generation method as a program executable by a computer.
(16) A program recording medium in which the DC balanced code generation program of (15) is recorded on a computer-readable recording medium.

DESCRIPTION OF SYMBOLS 1 Data memory 2 Shift register 3 Front 2 bit data latch circuit 4 Code serial data output 5 Data memory 6 Shift register 7 AMI encoding part 8 DC balanced bit production | generation holding part 9 Parity check calculation part 10 AMI code serial data output 11 D flip-flop 12 D flip-flop 13 Selector 14 Serial data 15 Clock 16 Positive sign output terminal 17 Negative sign output terminal 18 AND gate 19 AND gate 20 D flip-flop 21 D flip-flop 22 D flip-flop 23 D flip-flop 24 D flip-flop 25 D flip-flop 26 D flip-flop 27 D flip-flop 28 Positive sign output terminal 29 Negative sign output terminal 31 Shift register data load signal 32 Clock signal 33 Selector 34 Selector 35 selector 36 selector 37 selector 38 selector 39 selector 40 selector 41 inversion gate 42 inversion gate 43 inversion gate 44 inversion gate 50 communication interface circuit 50A communication interface circuit 51 UART circuit 52 line transceiver 53 pulse transformer 54 DC balanced code generation circuit 60 communication Interface circuit 60A Communication interface circuit 61 UART circuit 62 Line transceiver 63 Pulse transformer 64 DC balanced code generation circuit 70 Transmission line 81 Key telephone main unit 82 Digital extension terminal 83 Button telephone basic frame 84 Button telephone expansion

Claims (14)

Located in the forefront of the dc balancing code generating circuit that generates the code data for transmission as a serial data DC equilibrium via a transmission line which is AC coupled by a pulse transformer or capacitors, DC balancing the code data The distance from the positive sign output terminal of the first stage circuit that sequentially outputs the serial data of the state to the positive sign output terminal connected to the pulse transformer or capacitor and the negative sign output terminal of the first stage circuit to the pulse transformer or capacitor a distance to the negative code output terminal connected to a direct current balanced code generation circuit you the same length,
And a data memory for sequentially holding the transfer data,
Enter the data memory or al before Symbol transfer data, the bit data latch circuit prior to outputting the transfer data as delayed transfer data by delaying a predetermined number bits minutes,
The transfer data from the data memory during data loading, the delay transfer data from the leading bit data latch circuit, respectively enter a shift register for outputting code data of the serial data format of the DC equilibrium when the shift register operation and, the Bei example,
The shift register is
Alternately connecting a plurality of first shift circuits and a plurality of second shift circuits of the same number as the first shift circuits;
Each of the plurality of first shift circuits inputs a transfer bit that is one bit of data included in the transfer data when the data is loaded, and inputs output data from the previous stage when the shift register is operating. Shift output sequentially,
Each of the plurality of second shift circuits inverts 1-bit data included in the delay transfer data when the data is loaded and inputs it as a DC balanced bit, and outputs data from the previous stage during the shift register operation. Are input and output sequentially.
With such a configuration, code data in which the data bits of the transfer data and the DC balanced bits are alternately arranged is generated.
DC balanced code generation circuit.   Each of the plurality of first shift circuits receives the transfer bit and the output data from the previous stage, selects and outputs each data, and the data output by the first selector. A first D flip-flop that holds input information for 1 bit and sequentially shifts and outputs the data output by the first selector;
  Each of the plurality of second shift circuits includes an inverting gate that inverts the transfer bit delayed by the predetermined number of bits to generate a DC balanced bit, the DC balanced bit, and output data from the previous stage, A second selector that selects and outputs each data, and inputs the data output by the second selector, holds 1 bit of information, and sequentially shifts the data output by the second selector A second D flip-flop for outputting,
The DC balanced code generation circuit according to claim 1. When in a standby state where no valid data exists, the data memory operates to hold data for transfer, and the DC balanced bit and the transfer bit are alternated from the first stage circuit of the shift register. 3. The DC balanced code generation circuit according to claim 1 or 2 , wherein the code data inserted in is output as serial data in a DC balanced state. The violation flags indicating the beginning of a valid data to be transmitted to the other side, the direct current balancing code generation circuit according to any one of claims 1 to 3, characterized in that embedded in the head of the valid data. A serial data transmission device that transmits serial data in a DC balanced state via a transmission line that is AC-coupled by a pulse transformer or a capacitor, and as a DC balanced code generation circuit for generating the serial data in the DC balanced state 1 to comprise a DC balanced code generation circuit according to any one of 4, the serial data transmission apparatus.   As the serial data transmission device, a device that performs data transmission between the key telephone main device and the digital extension terminal, a device that performs data transmission between the basic frame of the key telephone device and the extension rack, and a network communication device The serial data transmission device according to claim 5, comprising at least any one of a device that performs data transmission and a device that performs data transmission between a network communication device and a communication terminal.   A shift register that generates code data for transmission as serial data in a DC balanced state via a transmission line that is AC-coupled by a pulse transformer or a capacitor,
  A plurality of first shift circuits corresponding to the number of bits of transfer data for inputting the transfer data from a data memory that sequentially holds the transfer data;
  The transfer data is input from the data memory, the transfer data is delayed by a predetermined number of bits and output as delayed transfer data, and the delayed transfer data output by the previous bit data latch circuit is input. A plurality of second shift circuits equal in number to one shift circuit;
Are connected alternately,
  Each of the plurality of first shift circuits inputs 1-bit data included in the transfer data as a transfer bit at the time of data loading, inputs output data from the previous stage, and sequentially shifts and outputs it,
  Each of the plurality of second shift circuits inverts 1-bit data included in the delay transfer data and inputs it as a DC balanced bit at the time of data loading, and sequentially inputs output data from the previous stage. Shift output,
  With such a configuration, code data in which the data bits of the transfer data and the DC balanced bits are alternately arranged is generated.
Shift register.   Each of the plurality of first shift circuits receives the transfer bit and the output data from the previous stage, selects and outputs each data, and the data output by the first selector. A first D flip-flop that holds input information for 1 bit and sequentially shifts and outputs the data output by the first selector;
  Each of the plurality of second shift circuits includes an inverting gate that inverts the transfer bit delayed by the predetermined number of bits to generate a DC balanced bit, the DC balanced bit, and output data from the previous stage, A second selector that selects and outputs each data, and inputs the data output by the second selector, holds 1 bit of information, and sequentially shifts the data output by the second selector A second D flip-flop for outputting,
The shift register according to claim 7.   A first step of sequentially holding and outputting the transfer data;
  A second step of inputting the transfer data, delaying the transfer data by a predetermined number of bits and outputting it as delayed transfer data;
  At the time of data loading, a transfer bit, which is 1-bit data included in the transfer data, is input, output data from the previous stage is input and sequentially shifted out,
  At the time of data loading, the data for 1 bit included in the delayed transfer data is inverted and input as a DC balanced bit, the output data from the previous stage is input and sequentially shifted out,
  Generating code data in which the data bits of the transfer data and the DC balanced bits are alternately arranged;
A third step;
A DC balanced code generation method comprising:   The third step includes
  Inputting the transfer bit and output data from the previous stage, holding information of one bit of the input data, and sequentially shifting and outputting the input data;
  A DC balanced bit that is input by inverting and outputting the transfer bit delayed by the predetermined number of bits and the output data from the previous stage are input, information for one bit of the input data is held, and the input And sequentially shifting out the processed data.
The DC balanced code generation method according to claim 9. When in the standby state in which valid data is not present, the first step is a process of holding the transfer data, before Symbol code data DC balancing bits and said transfer bit is inserted alternately The DC balanced code generation method according to claim 9 or 10 , characterized in that is output as serial data in a DC balanced state. The violation flags indicating the beginning of a valid data to be transmitted to the other side, DC balanced code generation method according to 11 any one of claims 9, characterized in that embedded in the head of the valid data. As a DC balanced code generator for generating code data for transmission as a serial data dc equilibrium, a DC balanced code generation method according to any one of claims 9 to 12, a DC balanced code generation to be executed by a computer program. 14. A program recording medium, wherein the DC balanced code generation program according to claim 13 is recorded on a computer-readable recording medium.

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