JP6771581B2 - Semiconductor modules and semiconductor devices - Google Patents

Semiconductor modules and semiconductor devices Download PDF

Info

Publication number
JP6771581B2
JP6771581B2 JP2018550893A JP2018550893A JP6771581B2 JP 6771581 B2 JP6771581 B2 JP 6771581B2 JP 2018550893 A JP2018550893 A JP 2018550893A JP 2018550893 A JP2018550893 A JP 2018550893A JP 6771581 B2 JP6771581 B2 JP 6771581B2
Authority
JP
Japan
Prior art keywords
heat radiating
semiconductor element
semiconductor
integrated circuit
radiating member
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2018550893A
Other languages
Japanese (ja)
Other versions
JPWO2018092185A1 (en
Inventor
真紀 長谷川
真紀 長谷川
脩平 横山
脩平 横山
祥吾 柴田
祥吾 柴田
茂 森
茂 森
岩上 徹
徹 岩上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of JPWO2018092185A1 publication Critical patent/JPWO2018092185A1/en
Application granted granted Critical
Publication of JP6771581B2 publication Critical patent/JP6771581B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142Sealing arrangements between parts, e.g. adhesion promotors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334Auxiliary members in encapsulations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49537Plurality of lead frames mounted in one device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49558Insulating layers on lead frames, e.g. bridging members
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49562Geometry of the lead-frame for devices being provided for in H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49568Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49575Assemblies of semiconductor devices on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601Structure
    • H01L2224/0603Bonding areas having different sizes, e.g. different heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0618Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181On opposite sides of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293Organic, e.g. plastic
    • H01L23/295Organic, e.g. plastic containing a filler
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Description

本発明は、半導体モジュール及び半導体装置に関する。 The present invention relates to semiconductor modules and semiconductor devices.

半導体素子と、半導体素子において発生する熱を放散させる放熱部材と、半導体素子を封止する封止部材とを備える半導体モジュールが知られている(特許文献1、特許文献2を参照)。 A semiconductor module including a semiconductor element, a heat radiating member that dissipates heat generated in the semiconductor element, and a sealing member that seals the semiconductor element is known (see Patent Documents 1 and 2).

実開平5−67001号公報Jikkenhei 5-667001 特開2014−143373号公報Japanese Unexamined Patent Publication No. 2014-143373

しかしながら、特許文献1に記載された半導体モジュールでは、半導体素子は放熱部材に接している。そのため、特許文献1に記載された半導体モジュールを、半導体素子の表面と裏面とに電極を有する縦型半導体素子に適用することはできない。 However, in the semiconductor module described in Patent Document 1, the semiconductor element is in contact with the heat radiating member. Therefore, the semiconductor module described in Patent Document 1 cannot be applied to a vertical semiconductor element having electrodes on the front surface and the back surface of the semiconductor element.

また、特許文献2に記載された半導体モジュールでは、半導体素子を放熱部材から電気的に絶縁するために、半導体素子と放熱部材との間に絶縁シートが介在している。特許文献2に記載された半導体モジュールを配線基板に実装する際に加えられる熱により、絶縁シートが硬化したり脆くなる。そのため、絶縁シートが半導体素子を放熱部材から電気的に絶縁することができなくなってしまう。 Further, in the semiconductor module described in Patent Document 2, an insulating sheet is interposed between the semiconductor element and the heat radiating member in order to electrically insulate the semiconductor element from the heat radiating member. The heat applied when the semiconductor module described in Patent Document 2 is mounted on the wiring board causes the insulating sheet to harden or become brittle. Therefore, the insulating sheet cannot electrically insulate the semiconductor element from the heat radiating member.

本発明は、上記の課題を鑑みてなされたものであり、その目的は、縦型半導体素子に適用され得るとともに、配線基板に実装される際に半導体素子と放熱部材との間の電気的絶縁が確保され得る半導体モジュール及びこの半導体モジュールを備える半導体装置を提供することである。 The present invention has been made in view of the above problems, and an object of the present invention can be applied to a vertical semiconductor element, and at the same time, electrical insulation between the semiconductor element and a heat radiating member when mounted on a wiring board. The present invention is to provide a semiconductor module capable of ensuring the above, and a semiconductor device including the semiconductor module.

本発明の半導体モジュールは、半導体素子と、半導体素子が載置される第1部分を含む第1リードフレームと、少なくとも半導体素子と第1部分とを封止する封止部材と、封止部材に一体化されかつ半導体素子において発生する熱を放散させる放熱部材とを備える。放熱部材は、封止部材から露出する放熱面を有する。放熱部材は、封止部材によって、半導体素子及び第1部分から絶縁されている。 The semiconductor module of the present invention includes a semiconductor element, a first lead frame including a first portion on which the semiconductor element is mounted, a sealing member for sealing at least the semiconductor element and the first portion, and a sealing member. It is provided with a heat radiating member that is integrated and dissipates heat generated in the semiconductor element. The heat radiating member has a heat radiating surface exposed from the sealing member. The heat radiating member is insulated from the semiconductor element and the first portion by a sealing member.

本発明の半導体装置は、上記半導体モジュールと、配線基板と、半導体モジュールを配線基板上に固定する接合部材とを備える。 The semiconductor device of the present invention includes the semiconductor module, a wiring board, and a joining member for fixing the semiconductor module on the wiring board.

本発明の半導体モジュールでは、放熱部材は、封止部材によって、半導体素子及び第1部分から絶縁されているため、半導体モジュールは縦型半導体素子に適用され得る。さらに、本発明の半導体モジュールでは、放熱部材は、封止部材によって、半導体素子及び第1部分から絶縁されているため、絶縁シートを用いることなく、放熱部材は、半導体素子及び第1部分から電気的に絶縁されている。そのため、本発明の半導体モジュールを配線基板上に実装する際に、半導体素子と放熱部材との間の電気的絶縁が確保され得る。 In the semiconductor module of the present invention, since the heat radiating member is insulated from the semiconductor element and the first portion by the sealing member, the semiconductor module can be applied to the vertical semiconductor element. Further, in the semiconductor module of the present invention, since the heat radiating member is insulated from the semiconductor element and the first portion by the sealing member, the heat radiating member is electrically operated from the semiconductor element and the first portion without using an insulating sheet. Is insulated. Therefore, when the semiconductor module of the present invention is mounted on the wiring board, electrical insulation between the semiconductor element and the heat radiating member can be ensured.

本発明の半導体装置は、上記半導体モジュールと、配線基板と、半導体モジュールを配線基板上に固定する接合部材とを備える。そのため、半導体装置は縦型半導体素子に適用され得るとともに、接合部材を用いて半導体モジュールを配線基板上に実装する際に、半導体素子と放熱部材との間の電気的絶縁が確保され得る。 The semiconductor device of the present invention includes the semiconductor module, a wiring board, and a joining member for fixing the semiconductor module on the wiring board. Therefore, the semiconductor device can be applied to a vertical semiconductor element, and electrical insulation between the semiconductor element and the heat radiating member can be ensured when the semiconductor module is mounted on the wiring board by using the bonding member.

本発明の実施の形態1に係る半導体モジュールの概略平面図である。It is a schematic plan view of the semiconductor module which concerns on Embodiment 1 of this invention. 本発明の実施の形態1に係る半導体モジュールの、図1に示される断面線II−IIにおける概略断面図である。FIG. 5 is a schematic cross-sectional view taken along the cross-sectional line II-II shown in FIG. 1 of the semiconductor module according to the first embodiment of the present invention. 本発明の実施の形態1に係る半導体装置の概略断面図である。It is schematic sectional drawing of the semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態2に係る半導体モジュールの概略断面図である。It is the schematic sectional drawing of the semiconductor module which concerns on Embodiment 2 of this invention. 本発明の実施の形態2に係る半導体モジュールに含まれる放熱部材の概略平面図である。It is a schematic plan view of the heat dissipation member included in the semiconductor module which concerns on Embodiment 2 of this invention. 本発明の実施の形態2に係る半導体モジュールに含まれる放熱部材の概略平面図である。It is a schematic plan view of the heat dissipation member included in the semiconductor module which concerns on Embodiment 2 of this invention. 本発明の実施の形態3に係る半導体モジュールの概略断面図である。It is the schematic sectional drawing of the semiconductor module which concerns on Embodiment 3 of this invention. 本発明の実施の形態3に係る半導体モジュールに含まれる放熱部材の概略平面図である。It is a schematic plan view of the heat dissipation member included in the semiconductor module which concerns on Embodiment 3 of this invention. 本発明の実施の形態3に係る半導体モジュールに含まれる放熱部材の概略平面図である。It is a schematic plan view of the heat dissipation member included in the semiconductor module which concerns on Embodiment 3 of this invention. 本発明の実施の形態4に係る半導体モジュールの概略断面図である。It is the schematic sectional drawing of the semiconductor module which concerns on Embodiment 4 of this invention. 本発明の実施の形態5に係る半導体モジュールの概略断面図である。It is the schematic sectional drawing of the semiconductor module which concerns on Embodiment 5 of this invention.

以下、本発明の実施の形態を説明する。なお、同一の構成には同一の参照番号を付し、その説明は繰り返さない。 Hereinafter, embodiments of the present invention will be described. The same reference number will be assigned to the same configuration, and the description will not be repeated.

実施の形態1.
図1及び図2を参照して、実施の形態1に係る半導体モジュール1を説明する。半導体モジュール1は、表面実装型半導体モジュール(1)であってもよい。半導体モジュール1は、半導体素子23と、第1リードフレーム10と、封止部材50と、放熱部材40とを主に備える。半導体モジュール1は、集積回路30と、第2リードフレーム16と、第3リードフレーム20と、第1導電ワイヤ35と、第2導電ワイヤ36とをさらに備えてもよい。
Embodiment 1.
The semiconductor module 1 according to the first embodiment will be described with reference to FIGS. 1 and 2. The semiconductor module 1 may be a surface mount type semiconductor module (1). The semiconductor module 1 mainly includes a semiconductor element 23, a first lead frame 10, a sealing member 50, and a heat radiating member 40. The semiconductor module 1 may further include an integrated circuit 30, a second lead frame 16, a third lead frame 20, a first conductive wire 35, and a second conductive wire 36.

半導体素子23は、第1の表面24と、第1の表面24とは反対側の第2の表面25とを有している。半導体素子23は、例えば、絶縁ゲート型バイポーラトランジスタ(IGBT)、金属酸化物半導体電界効果トランジスタ(MOSFET)、ゲートターンオフ(GTO)サイリスタまたはダイオードであってもよい。半導体素子23は、シリコン(Si)、炭化ケイ素(SiC)または窒化ガリウム(GaN)のような半導体材料から構成されてもよい。 The semiconductor element 23 has a first surface 24 and a second surface 25 on the opposite side of the first surface 24. The semiconductor element 23 may be, for example, an insulated gate bipolar transistor (IGBT), a metal oxide semiconductor field effect transistor (MOSFET), a gate turn-off (GTO) thyristor, or a diode. The semiconductor element 23 may be made of a semiconductor material such as silicon (Si), silicon carbide (SiC) or gallium nitride (GaN).

半導体素子23は、複数の電極(第1電極26、第2電極27、第3電極28)を有している。例えば、半導体素子23は、2つの電極を有する二端子素子であってもよいし、3つの電極を有する三端子素子であってもよい。半導体素子23は、縦型半導体素子(23)であってもよい。縦型半導体素子(23)は、半導体素子23の第1の表面24上と第1の表面24とは反対側の第2の表面25上とに、電極(第1電極26、第2電極27)を有する。本実施の形態の半導体素子23は、第1の表面24上に設けられた第1電極26と、第2の表面25上に設けられた第2電極27と、第1の表面24上に設けられかつ第1電極26と電気的に分離された第3電極28とを有する、縦型の三端子素子である。半導体素子23は、例えば、第1の表面24上に設けられた第1電極26と、第2の表面25上に設けられた第2電極27とを有する、縦型の二端子素子であってもよい。 The semiconductor element 23 has a plurality of electrodes (first electrode 26, second electrode 27, third electrode 28). For example, the semiconductor element 23 may be a two-terminal element having two electrodes or a three-terminal element having three electrodes. The semiconductor element 23 may be a vertical semiconductor element (23). The vertical semiconductor element (23) has electrodes (first electrode 26, second electrode 27) on the first surface 24 of the semiconductor element 23 and on the second surface 25 on the side opposite to the first surface 24. ). The semiconductor element 23 of the present embodiment is provided on the first electrode 26 provided on the first surface 24, the second electrode 27 provided on the second surface 25, and the first surface 24. It is a vertical three-terminal element having a first electrode 26 and an electrically separated third electrode 28. The semiconductor element 23 is, for example, a vertical two-terminal element having a first electrode 26 provided on the first surface 24 and a second electrode 27 provided on the second surface 25. May be good.

集積回路30は、半導体素子23を制御する回路である。集積回路30は、半導体素子23に電気的に接続されている。具体的には、集積回路30は、第2導電ワイヤ36を介して、半導体素子23の第3電極28に接続されている。第2導電ワイヤ36は、半導体素子23の第3電極28と集積回路30とに接続されている。第2導電ワイヤ36は、半導体素子23(第3電極28)及び集積回路30から放熱部材40側とは反対側に引き出されている。 The integrated circuit 30 is a circuit that controls the semiconductor element 23. The integrated circuit 30 is electrically connected to the semiconductor element 23. Specifically, the integrated circuit 30 is connected to the third electrode 28 of the semiconductor element 23 via the second conductive wire 36. The second conductive wire 36 is connected to the third electrode 28 of the semiconductor element 23 and the integrated circuit 30. The second conductive wire 36 is pulled out from the semiconductor element 23 (third electrode 28) and the integrated circuit 30 on the side opposite to the heat radiating member 40 side.

第1リードフレーム10、第2リードフレーム16及び第3リードフレーム20は、銅またはアルミニウムのような、低い電気抵抗率と高い熱伝導率とを有する材料で構成されてもよい。第1リードフレーム10、第2リードフレーム16及び第3リードフレーム20は、封止部材50によって、放熱部材40から電気的に絶縁されている。 The first lead frame 10, the second lead frame 16, and the third lead frame 20 may be made of a material having a low electrical resistivity and a high thermal conductivity, such as copper or aluminum. The first lead frame 10, the second lead frame 16, and the third lead frame 20 are electrically insulated from the heat radiating member 40 by the sealing member 50.

第1リードフレーム10は、半導体素子23が載置される第1部分11と第1端子部14とを含んでいる。第1リードフレーム10は、第1部分11に接続される第2部分12と、第2部分12及び第1端子部14に接続される第3部分13とをさらに含んでもよい。第1部分11は、半導体素子23と放熱部材40との間に配置されてもよい。第1部分11は、放熱部材40に対して、第1間隔g1を空けて配置されている。第1間隔g1は、放熱部材40の厚さ方向における、第1部分11と放熱部材40との間の最短距離として定義される。第1間隔g1は、100μm以上であってもよく、特定的には150μm以上であってもよい。第1間隔g1は、500μm以下であってもよく、特定的には350μm以下であってもよい。The first lead frame 10 includes a first portion 11 on which the semiconductor element 23 is mounted and a first terminal portion 14. The first lead frame 10 may further include a second portion 12 connected to the first portion 11 and a third portion 13 connected to the second portion 12 and the first terminal portion 14. The first portion 11 may be arranged between the semiconductor element 23 and the heat radiating member 40. The first portion 11 is arranged with a first interval g 1 with respect to the heat radiating member 40. The first interval g 1 is defined as the shortest distance between the first portion 11 and the heat radiating member 40 in the thickness direction of the heat radiating member 40. The first interval g 1 may be 100 μm or more, and specifically 150 μm or more. The first interval g 1 may be 500 μm or less, and specifically 350 μm or less.

第1部分11と放熱部材40との間の第1間隔g1が、第3部分13と放熱部材40との間の第2間隔g2よりも小さくなるように、第2部分12は第1部分11及び第3部分13に対して傾斜している。第2間隔g2は、放熱部材40の厚さ方向における、第3部分13と放熱部材40との間の最短距離として定義される。金属板を折り曲げることによって、第1部分11と第2部分12と第3部分13と第1端子部14とを含む第1リードフレーム10が形成されてもよい。The second portion 12 is the first so that the first spacing g 1 between the first portion 11 and the heat radiating member 40 is smaller than the second spacing g 2 between the third portion 13 and the heat radiating member 40. It is inclined with respect to the portion 11 and the third portion 13. The second interval g 2 is defined as the shortest distance between the third portion 13 and the heat radiating member 40 in the thickness direction of the heat radiating member 40. By bending the metal plate, the first lead frame 10 including the first portion 11, the second portion 12, the third portion 13, and the first terminal portion 14 may be formed.

半導体素子23は、第1リードフレーム10の第1部分11に電気的に接続されている。具体的には、半導体素子23は、はんだのような接合部材(図示せず)を用いて、第1リードフレーム10の第1部分11に接合されてもよい。さらに具体的には、半導体素子23の第2電極27は、はんだのような接合部材(図示せず)を用いて、第1リードフレーム10の第1部分11に接合されてもよい。 The semiconductor element 23 is electrically connected to the first portion 11 of the first lead frame 10. Specifically, the semiconductor element 23 may be bonded to the first portion 11 of the first lead frame 10 by using a bonding member (not shown) such as solder. More specifically, the second electrode 27 of the semiconductor element 23 may be joined to the first portion 11 of the first lead frame 10 by using a joining member (not shown) such as solder.

第1リードフレーム10の第1部分11及び第2部分12は、封止部材50の中に埋め込まれてもよい。そのため、第1部分11と第2部分12との間の第1折曲部は、封止部材50によって湿度及び衝撃等から保護される。さらに、第2部分12側の端部を含む第3部分13の少なくとも一部は、封止部材50の中に埋め込まれてもよい。そのため、第2部分12と第3部分13との間の第2折曲部は、封止部材50によって湿度及び衝撃等から保護される。 The first portion 11 and the second portion 12 of the first lead frame 10 may be embedded in the sealing member 50. Therefore, the first bent portion between the first portion 11 and the second portion 12 is protected from humidity, impact, and the like by the sealing member 50. Further, at least a part of the third portion 13 including the end portion on the second portion 12 side may be embedded in the sealing member 50. Therefore, the second bent portion between the second portion 12 and the third portion 13 is protected from humidity, impact, and the like by the sealing member 50.

第2リードフレーム16は、集積回路30が載置される第4部分17と、第4部分17に接続される第2端子部18とを含んでいる。金属板を折り曲げることによって、第4部分17と第2端子部18とを含む第2リードフレーム16が形成されてもよい。第4部分17は、集積回路30と放熱部材40との間に配置されてもよい。第1部分11と放熱部材40との間の第1間隔g1は、第4部分17と放熱部材40との間の第3間隔g3よりも小さくてもよい。第3間隔g3は、放熱部材40の厚さ方向における、第4部分17と放熱部材40との間の最短距離として定義される。集積回路30は、第2リードフレーム16の第4部分17に電気的に接続されている。具体的には、集積回路30は、はんだのような接合部材(図示せず)を用いて、第2リードフレーム16の第4部分17に接合されてもよい。The second lead frame 16 includes a fourth portion 17 on which the integrated circuit 30 is mounted and a second terminal portion 18 connected to the fourth portion 17. The second lead frame 16 including the fourth portion 17 and the second terminal portion 18 may be formed by bending the metal plate. The fourth portion 17 may be arranged between the integrated circuit 30 and the heat radiating member 40. The first distance g 1 between the first portion 11 and the heat radiating member 40 may be smaller than the third distance g 3 between the fourth portion 17 and the heat radiating member 40. The third interval g 3 is defined as the shortest distance between the fourth portion 17 and the heat radiating member 40 in the thickness direction of the heat radiating member 40. The integrated circuit 30 is electrically connected to the fourth portion 17 of the second lead frame 16. Specifically, the integrated circuit 30 may be joined to the fourth portion 17 of the second lead frame 16 by using a joining member (not shown) such as solder.

第3リードフレーム20は、第5部分21と、第5部分21に接続される第3端子部22とを含んでいる。金属板を折り曲げることによって、第5部分21と第3端子部22とを含む第3リードフレーム20が形成されてもよい。第3リードフレーム20は、半導体素子23に電気的に接続されている。具体的には、第3リードフレーム20の第5部分21は、第1導電ワイヤ35を介して、半導体素子23の第1電極26に接続されている。第1導電ワイヤ35は、半導体素子23の第1電極26と第3リードフレーム20の第5部分21とに接続されている。第1導電ワイヤ35は、半導体素子23(第1電極26)及び第3リードフレーム20(第5部分21)から放熱部材40側とは反対側に引き出されている。 The third lead frame 20 includes a fifth portion 21 and a third terminal portion 22 connected to the fifth portion 21. By bending the metal plate, the third lead frame 20 including the fifth portion 21 and the third terminal portion 22 may be formed. The third lead frame 20 is electrically connected to the semiconductor element 23. Specifically, the fifth portion 21 of the third lead frame 20 is connected to the first electrode 26 of the semiconductor element 23 via the first conductive wire 35. The first conductive wire 35 is connected to the first electrode 26 of the semiconductor element 23 and the fifth portion 21 of the third lead frame 20. The first conductive wire 35 is pulled out from the semiconductor element 23 (first electrode 26) and the third lead frame 20 (fifth portion 21) to the side opposite to the heat radiating member 40 side.

封止部材50は、少なくとも半導体素子23と第1リードフレーム10の第1部分11とを封止する。封止部材50は、第1リードフレーム10の第2部分12と、第1リードフレーム10の第3部分13の少なくとも一部と、集積回路30と、第2リードフレーム16の第4部分17の少なくとも一部と、第3リードフレーム20の第5部分21の少なくとも一部と、第1導電ワイヤ35と、第2導電ワイヤ36とをさらに封止してもよい。第1端子部14、第2端子部18及び第3端子部22は、封止部材50から露出している。 The sealing member 50 seals at least the semiconductor element 23 and the first portion 11 of the first lead frame 10. The sealing member 50 includes a second portion 12 of the first lead frame 10, at least a part of the third portion 13 of the first lead frame 10, an integrated circuit 30, and a fourth portion 17 of the second lead frame 16. At least a part, at least a part of the fifth portion 21 of the third lead frame 20, the first conductive wire 35, and the second conductive wire 36 may be further sealed. The first terminal portion 14, the second terminal portion 18, and the third terminal portion 22 are exposed from the sealing member 50.

封止部材50は、電気的絶縁性を有する。封止部材50は、例えば、電気的絶縁性を有し、かつ、半導体モジュール1を配線基板61(図3を参照)に実装する際に加えられる熱に耐える樹脂から構成されてもよい。封止部材50は、例えば、エポキシ樹脂、ポリイミド樹脂、ポリアミド樹脂、ポリアミドイミド樹脂、フッ素系樹脂、イソシアネート系樹脂、シリコーン樹脂及びこれらの組み合わせからなる群から選択される樹脂材料から構成されてもよい。封止部材50は、シリカ、アルミナ、窒化アルミニウムまたは窒化ホウ素のような無機材料からなるフィラーをさらに含んでもよい。フィラーは、封止部材50の熱伝導性を向上させてもよい。そのため、フィラーが充填された封止部材50は、半導体素子23から発生する熱を、放熱部材40に効率的に伝達することができる。 The sealing member 50 has electrical insulation. The sealing member 50 may be made of, for example, a resin that has electrical insulation and can withstand the heat applied when the semiconductor module 1 is mounted on the wiring board 61 (see FIG. 3). The sealing member 50 may be composed of, for example, an epoxy resin, a polyimide resin, a polyamide resin, a polyamide-imide resin, a fluorine-based resin, an isocyanate-based resin, a silicone resin, or a resin material selected from the group consisting of combinations thereof. .. The sealing member 50 may further contain a filler made of an inorganic material such as silica, alumina, aluminum nitride or boron nitride. The filler may improve the thermal conductivity of the sealing member 50. Therefore, the sealing member 50 filled with the filler can efficiently transfer the heat generated from the semiconductor element 23 to the heat radiating member 40.

放熱部材40は、半導体素子23において発生する熱を放散させる。放熱部材40は、第1リードフレーム10の第1部分11及び半導体素子23に対向するように配置されている。半導体素子23の第1の表面24に垂直な方向からの平面視(図1を参照)において半導体素子23が放熱部材40に重なるように、放熱部材40は半導体素子23に対して配置されてもよい。放熱部材40は、集積回路30において発生する熱をさらに放散させてもよい。放熱部材40は、第2リードフレーム16の第4部分17及び集積回路30に対向するように配置されている。半導体素子23の第1の表面24に垂直な方向からの平面視(図1を参照)において集積回路30が放熱部材40に重なるように、放熱部材40は集積回路30に対して配置されてもよい。 The heat radiating member 40 dissipates heat generated in the semiconductor element 23. The heat radiating member 40 is arranged so as to face the first portion 11 of the first lead frame 10 and the semiconductor element 23. Even if the heat radiating member 40 is arranged with respect to the semiconductor element 23 so that the semiconductor element 23 overlaps the heat radiating member 40 in a plan view (see FIG. 1) from a direction perpendicular to the first surface 24 of the semiconductor element 23. Good. The heat radiating member 40 may further dissipate the heat generated in the integrated circuit 30. The heat radiating member 40 is arranged so as to face the fourth portion 17 of the second lead frame 16 and the integrated circuit 30. Even if the heat radiating member 40 is arranged with respect to the integrated circuit 30 so that the integrated circuit 30 overlaps the heat radiating member 40 in a plan view (see FIG. 1) from a direction perpendicular to the first surface 24 of the semiconductor element 23. Good.

放熱部材40は、銅またはアルミニウムのような導電性と熱伝導性とを有する材料からなる板部材であってもよい。放熱部材40は、封止部材50から露出する放熱面41を有している。封止部材50から露出する放熱面41は、半導体素子23において発生する熱を半導体モジュール1の外部に効率的に放散させることができる。放熱面41は、封止部材50の表面と面一であってもよい。放熱面41以外の放熱部材40の複数の表面は、封止部材50に面してもよい。放熱部材40は、封止部材50によって、半導体素子23及び第1部分11から絶縁されている。 The heat radiating member 40 may be a plate member made of a material having conductivity and thermal conductivity such as copper or aluminum. The heat radiating member 40 has a heat radiating surface 41 exposed from the sealing member 50. The heat radiating surface 41 exposed from the sealing member 50 can efficiently dissipate the heat generated in the semiconductor element 23 to the outside of the semiconductor module 1. The heat radiating surface 41 may be flush with the surface of the sealing member 50. A plurality of surfaces of the heat radiating member 40 other than the heat radiating surface 41 may face the sealing member 50. The heat radiating member 40 is insulated from the semiconductor element 23 and the first portion 11 by the sealing member 50.

放熱部材40は、封止部材50に一体化されている。例えば、半導体素子23、集積回路30、第1リードフレーム10、第2リードフレーム16、第3リードフレーム20、第1導電ワイヤ35及び第2導電ワイヤ36とともに放熱部材40を封止部材50でモールドすることによって、放熱部材40は封止部材50に一体化されてもよい。封止部材50に形成された凹部に放熱部材40を嵌合することによって、放熱部材40は封止部材50に一体化されてもよい。ねじのような固定部材を用いて放熱部材40を封止部材50に取り付けることによって、放熱部材40は封止部材50に一体化されてもよい。 The heat radiating member 40 is integrated with the sealing member 50. For example, the heat radiating member 40 is molded by the sealing member 50 together with the semiconductor element 23, the integrated circuit 30, the first lead frame 10, the second lead frame 16, the third lead frame 20, the first conductive wire 35, and the second conductive wire 36. By doing so, the heat radiating member 40 may be integrated with the sealing member 50. The heat radiating member 40 may be integrated with the sealing member 50 by fitting the heat radiating member 40 into the recess formed in the sealing member 50. The heat radiating member 40 may be integrated with the sealing member 50 by attaching the heat radiating member 40 to the sealing member 50 using a fixing member such as a screw.

図3を参照して、本実施の形態の半導体装置5を説明する。半導体装置5は、半導体モジュール1と、配線(第1配線62、第2配線63及び第3配線(図示せず))を含む配線基板61と、半導体モジュール1を配線基板61上に固定する接合部材65とを備える。第1リードフレーム10の第1端子部14、第2リードフレーム16の第2端子部18及び第3リードフレーム20の第3端子部22は、それぞれ、配線基板61の第1配線62、第2配線63及び第3配線に、接合部材65を用いて接合される。接合部材65は、例えば、はんだであってもよい。接合部材65に熱を加えること(例えば、接合部材65がはんだである場合におけるはんだリフロー工程)により、接合部材65を用いて、半導体モジュール1は配線基板61上に実装される。封止部材50はこの実装工程において加えられる熱に耐えるため、封止部材50は半導体素子23と放熱部材40との間の電気的絶縁を確保することができる。 The semiconductor device 5 of the present embodiment will be described with reference to FIG. The semiconductor device 5 includes a semiconductor module 1, a wiring board 61 including wiring (first wiring 62, second wiring 63, and third wiring (not shown)), and a junction for fixing the semiconductor module 1 on the wiring board 61. A member 65 is provided. The first terminal portion 14 of the first lead frame 10, the second terminal portion 18 of the second lead frame 16, and the third terminal portion 22 of the third lead frame 20 are the first wiring 62 and the second of the wiring board 61, respectively. It is joined to the wiring 63 and the third wiring by using the joining member 65. The joining member 65 may be, for example, solder. By applying heat to the joining member 65 (for example, a solder reflow step when the joining member 65 is solder), the semiconductor module 1 is mounted on the wiring board 61 by using the joining member 65. Since the sealing member 50 withstands the heat applied in this mounting process, the sealing member 50 can secure electrical insulation between the semiconductor element 23 and the heat radiating member 40.

本実施の形態の半導体モジュール1の効果を説明する。
本実施の形態の半導体モジュール1は、半導体素子23と、半導体素子23が載置される第1部分11を含む第1リードフレーム10と、少なくとも半導体素子23と第1部分11とを封止する封止部材50と、封止部材50に一体化されかつ半導体素子23において発生する熱を放散させる放熱部材40とを備える。放熱部材40は、封止部材50から露出する放熱面41を有する。放熱部材40は、封止部材50によって、半導体素子23及び第1部分11から絶縁されている。
The effect of the semiconductor module 1 of the present embodiment will be described.
The semiconductor module 1 of the present embodiment seals the semiconductor element 23, the first read frame 10 including the first portion 11 on which the semiconductor element 23 is mounted, and at least the semiconductor element 23 and the first portion 11. It includes a sealing member 50 and a heat radiating member 40 that is integrated with the sealing member 50 and dissipates heat generated in the semiconductor element 23. The heat radiating member 40 has a heat radiating surface 41 exposed from the sealing member 50. The heat radiating member 40 is insulated from the semiconductor element 23 and the first portion 11 by the sealing member 50.

本実施の形態の半導体モジュール1では、放熱部材40は、封止部材50によって、半導体素子23及び第1部分11から絶縁されており、放熱部材40は、半導体素子23及び第1部分11に接していない。そのため、半導体モジュール1は縦型半導体素子(23)に適用され得る。さらに、半導体モジュール1では、放熱部材40は、封止部材50によって、半導体素子23及び第1部分11から絶縁されているため、絶縁シートを用いることなく、放熱部材40は、半導体素子23及び第1部分11から電気的に絶縁されている。そのため、半導体モジュール1を配線基板61上に実装する際に、半導体素子23と放熱部材40との間の電気的絶縁が確保され得る。 In the semiconductor module 1 of the present embodiment, the heat radiating member 40 is insulated from the semiconductor element 23 and the first portion 11 by the sealing member 50, and the heat radiating member 40 is in contact with the semiconductor element 23 and the first portion 11. Not. Therefore, the semiconductor module 1 can be applied to the vertical semiconductor element (23). Further, in the semiconductor module 1, since the heat radiating member 40 is insulated from the semiconductor element 23 and the first portion 11 by the sealing member 50, the heat radiating member 40 can be the semiconductor element 23 and the first portion 11 without using an insulating sheet. It is electrically insulated from part 11. Therefore, when the semiconductor module 1 is mounted on the wiring board 61, electrical insulation between the semiconductor element 23 and the heat radiating member 40 can be ensured.

本実施の形態の半導体モジュール1では、第1部分11は、半導体素子23と放熱部材40との間に配置されている。第1部分11は、放熱部材40に対して、第1間隔g1を空けて配置されている。そのため、半導体モジュール1は縦型半導体素子(23)に適用され得るとともに、半導体モジュール1を配線基板61上に実装する際に、半導体素子23と放熱部材40との間の電気的絶縁が確保され得る。In the semiconductor module 1 of the present embodiment, the first portion 11 is arranged between the semiconductor element 23 and the heat radiating member 40. The first portion 11 is arranged with a first interval g 1 with respect to the heat radiating member 40. Therefore, the semiconductor module 1 can be applied to the vertical semiconductor element (23), and when the semiconductor module 1 is mounted on the wiring board 61, electrical insulation between the semiconductor element 23 and the heat radiating member 40 is ensured. obtain.

本実施の形態の半導体モジュール1では、第1間隔g1は、100μm以上500μm以下である。第1間隔g1を100μm以上に設定することにより、放熱部材40は、半導体素子23及び第1部分11から確実に電気的に絶縁され得る。第1間隔g1を500μm以下に設定することにより、半導体素子23から発生する熱が放熱部材40に低い熱抵抗で伝達され得る。In the semiconductor module 1 of the present embodiment, the first interval g 1 is 100 μm or more and 500 μm or less. By setting the first interval g 1 to 100 μm or more, the heat radiating member 40 can be reliably electrically insulated from the semiconductor element 23 and the first portion 11. By setting the first interval g 1 to 500 μm or less, the heat generated from the semiconductor element 23 can be transferred to the heat radiating member 40 with low thermal resistance.

本実施の形態の半導体モジュール1では、第1リードフレーム10は、第1部分11に接続される第2部分12と、第2部分12に接続される第3部分13と、第3部分13に接続される端子部とを含む。第1部分11と放熱部材40との間の第1間隔g1が、第3部分13と放熱部材40との間の第2間隔g2よりも小さくなるように、第2部分12は第1部分11及び第3部分13に対して傾斜している。そのため、放熱部材40を半導体素子23及び第1部分11から電気的に絶縁しながら、半導体素子23は放熱部材40の近くに配置され得る。半導体素子23から発生する熱が放熱部材40に低い熱抵抗で伝達され得る。In the semiconductor module 1 of the present embodiment, the first lead frame 10 is connected to the second portion 12 connected to the first portion 11, the third portion 13 connected to the second portion 12, and the third portion 13. Including the terminal part to be connected. The second portion 12 is the first so that the first spacing g 1 between the first portion 11 and the heat radiating member 40 is smaller than the second spacing g 2 between the third portion 13 and the heat radiating member 40. It is inclined with respect to the portion 11 and the third portion 13. Therefore, the semiconductor element 23 can be arranged near the heat radiating member 40 while electrically insulating the heat radiating member 40 from the semiconductor element 23 and the first portion 11. The heat generated from the semiconductor element 23 can be transferred to the heat radiating member 40 with low thermal resistance.

本実施の形態の半導体モジュール1では、第1部分11及び前記第2部分12は、封止部材50の中に埋め込まれている。第1部分11と第2部分12との間の折曲部は、封止部材50によって、湿度及び衝撃等から保護され得る。 In the semiconductor module 1 of the present embodiment, the first portion 11 and the second portion 12 are embedded in the sealing member 50. The bent portion between the first portion 11 and the second portion 12 can be protected from humidity, impact and the like by the sealing member 50.

本実施の形態の半導体モジュール1は、半導体素子23に電気的に接続される集積回路30と、集積回路30が載置される第4部分17を含む第2リードフレーム16とをさらに備える。第4部分17は、集積回路30と放熱部材40との間に配置されている。第1部分11と放熱部材40との間の第1間隔g1は、第4部分17と放熱部材40との間の第3間隔g3よりも小さい。放熱部材40を半導体素子23及び第1部分11から電気的に絶縁しながら、半導体素子23は放熱部材40のより近くに配置され得る。半導体素子23から発生する熱が放熱部材40に低い熱抵抗で伝達され得る。The semiconductor module 1 of the present embodiment further includes an integrated circuit 30 electrically connected to the semiconductor element 23, and a second read frame 16 including a fourth portion 17 on which the integrated circuit 30 is mounted. The fourth portion 17 is arranged between the integrated circuit 30 and the heat radiating member 40. The first distance g 1 between the first portion 11 and the heat radiating member 40 is smaller than the third distance g 3 between the fourth portion 17 and the heat radiating member 40. The semiconductor element 23 may be located closer to the heat radiating member 40 while electrically insulating the heat radiating member 40 from the semiconductor element 23 and the first portion 11. The heat generated from the semiconductor element 23 can be transferred to the heat radiating member 40 with low thermal resistance.

本実施の形態の半導体モジュール1は、第3リードフレーム20と、第3リードフレーム20と半導体素子23とに接続される第1導電ワイヤ35と、集積回路30と半導体素子23とに接続される第2導電ワイヤ36とをさらに備える。第1導電ワイヤ35は、第3リードフレーム20及び半導体素子23から放熱部材40側とは反対側に引き出されている。第2導電ワイヤ36は、集積回路30及び半導体素子23から放熱部材40側とは反対側に引き出されている。第4部分17と放熱部材40との間の第3間隔g3は第1部分11と放熱部材40との間の第1間隔g1と異なる。そのため、第1導電ワイヤ35及び第2導電ワイヤ36が半導体素子23から放熱部材40側とは反対側に引き出されても、第2導電ワイヤ36は集積回路30と半導体素子23とに容易にボンディングされ得る。The semiconductor module 1 of the present embodiment is connected to the third lead frame 20, the first conductive wire 35 connected to the third lead frame 20 and the semiconductor element 23, and the integrated circuit 30 and the semiconductor element 23. It further includes a second conductive wire 36. The first conductive wire 35 is pulled out from the third lead frame 20 and the semiconductor element 23 on the side opposite to the heat radiating member 40 side. The second conductive wire 36 is pulled out from the integrated circuit 30 and the semiconductor element 23 to the side opposite to the heat radiating member 40 side. The third spacing g 3 between the fourth portion 17 and the heat radiating member 40 is different from the first spacing g 1 between the first portion 11 and the heat radiating member 40. Therefore, even if the first conductive wire 35 and the second conductive wire 36 are pulled out from the semiconductor element 23 to the side opposite to the heat radiating member 40 side, the second conductive wire 36 is easily bonded to the integrated circuit 30 and the semiconductor element 23. Can be done.

本実施の形態の半導体モジュール1では、放熱面41以外の放熱部材40の複数の表面は、封止部材50に面している。そのため、放熱部材40は封止部材50に強固に一体化され得る。 In the semiconductor module 1 of the present embodiment, a plurality of surfaces of the heat radiating member 40 other than the heat radiating surface 41 face the sealing member 50. Therefore, the heat radiating member 40 can be firmly integrated with the sealing member 50.

本実施の形態の半導体モジュール1では、半導体素子23は、第1の表面24と、第1の表面24とは反対側の第2の表面25とを有している。半導体素子23は、第1の表面24上に設けられた第1電極26と、第2の表面25上に設けられた第2電極27とを有している。第2電極27は、第1リードフレーム10の第1部分11に接合されている。本実施の形態の半導体モジュール1は縦型半導体素子(23)に適用され得るとともに、半導体モジュール1を配線基板61上に実装する際に、半導体素子23と放熱部材40との間の電気的絶縁が確保され得る。 In the semiconductor module 1 of the present embodiment, the semiconductor element 23 has a first surface 24 and a second surface 25 on the opposite side of the first surface 24. The semiconductor element 23 has a first electrode 26 provided on the first surface 24 and a second electrode 27 provided on the second surface 25. The second electrode 27 is joined to the first portion 11 of the first lead frame 10. The semiconductor module 1 of the present embodiment can be applied to the vertical semiconductor element (23), and when the semiconductor module 1 is mounted on the wiring board 61, electrical insulation between the semiconductor element 23 and the heat radiating member 40 is provided. Can be secured.

本実施の形態の半導体装置5は、半導体モジュール1と、配線基板61と、半導体モジュール1を配線基板61上に固定する接合部材とを備える。そのため、半導体装置5は縦型半導体素子(23)に適用され得るとともに、接合部材を用いて半導体モジュール1を配線基板61上に実装する際に、半導体素子23と放熱部材40との間の電気的絶縁が確保され得る。 The semiconductor device 5 of the present embodiment includes a semiconductor module 1, a wiring board 61, and a joining member for fixing the semiconductor module 1 on the wiring board 61. Therefore, the semiconductor device 5 can be applied to the vertical semiconductor element (23), and when the semiconductor module 1 is mounted on the wiring board 61 by using the bonding member, the electricity between the semiconductor element 23 and the heat radiating member 40 Insulation can be ensured.

実施の形態2.
図4から図6を参照して、実施の形態2に係る半導体モジュール1bを説明する。本実施の形態の半導体モジュール1bは、基本的には、実施の形態1の半導体モジュール1と同様の構成を備えるが、主に以下の点で異なる。
Embodiment 2.
The semiconductor module 1b according to the second embodiment will be described with reference to FIGS. 4 to 6. The semiconductor module 1b of the present embodiment basically has the same configuration as the semiconductor module 1 of the first embodiment, but differs mainly in the following points.

本実施の形態の半導体モジュール1bでは、放熱部材40は、放熱面41上に、1つ以上の凸部42を含む。1つ以上の凸部42の各々は、図5に示されるように柱状の凸部42であってもよいし、図6に示されるように板状の凸部42であってもよい。1つ以上の凸部42は、放熱面41内に均一に分布してもよいし、放熱面41内に不均一に分布してもよい。半導体素子23の発熱量が集積回路30の発熱量よりも大きいときは、集積回路30に対応する放熱面41の第2領域よりも、半導体素子23に対応する放熱面41の第1領域に、より多くの1つ以上の凸部42が配置されてもよい。 In the semiconductor module 1b of the present embodiment, the heat radiating member 40 includes one or more convex portions 42 on the heat radiating surface 41. Each of the one or more convex portions 42 may be a columnar convex portion 42 as shown in FIG. 5, or may be a plate-shaped convex portion 42 as shown in FIG. The one or more convex portions 42 may be uniformly distributed in the heat radiating surface 41, or may be unevenly distributed in the heat radiating surface 41. When the heat generation amount of the semiconductor element 23 is larger than the heat generation amount of the integrated circuit 30, the first region of the heat dissipation surface 41 corresponding to the semiconductor element 23 is set rather than the second region of the heat dissipation surface 41 corresponding to the integrated circuit 30. More than one convex portion 42 may be arranged.

本実施の形態の半導体装置は、実施の形態1の半導体装置5と同様の構成を備えるが、実施の形態1の半導体モジュール1に代えて、本実施の形態の半導体モジュール1bを備える点で異なる。 The semiconductor device of the present embodiment has the same configuration as the semiconductor device 5 of the first embodiment, except that the semiconductor module 1b of the present embodiment is provided instead of the semiconductor module 1 of the first embodiment. ..

本実施の形態の半導体モジュール1bの効果を説明する。本実施の形態の半導体モジュール1bは、実施の形態1の半導体モジュール1の効果に加えて、以下の効果を奏する。本実施の形態の半導体モジュール1bでは、放熱部材40は、放熱面41上に、1つ以上の凸部42を含む。1つ以上の凸部42は、放熱部材40における放熱面積を増加させる。そのため、半導体モジュール1bの放熱特性が改善され得る。 The effect of the semiconductor module 1b of the present embodiment will be described. The semiconductor module 1b of the present embodiment has the following effects in addition to the effects of the semiconductor module 1 of the first embodiment. In the semiconductor module 1b of the present embodiment, the heat radiating member 40 includes one or more convex portions 42 on the heat radiating surface 41. One or more convex portions 42 increase the heat radiating area in the heat radiating member 40. Therefore, the heat dissipation characteristics of the semiconductor module 1b can be improved.

実施の形態3.
図7から図9を参照して、実施の形態3に係る半導体モジュール1cを説明する。本実施の形態の半導体モジュール1cは、基本的には、実施の形態1の半導体モジュール1と同様の構成を備えるが、主に以下の点で異なる。
Embodiment 3.
The semiconductor module 1c according to the third embodiment will be described with reference to FIGS. 7 to 9. The semiconductor module 1c of the present embodiment basically has the same configuration as the semiconductor module 1 of the first embodiment, but differs mainly in the following points.

本実施の形態の半導体モジュール1cでは、放熱部材40は、放熱面41上に、1つ以上の凹部44を含む。1つ以上の凹部44の各々は、図8に示されるように柱状の凹部44であってもよいし、図9に示されるように板状の凹部44であってもよい。1つ以上の凹部44は、放熱面41内に均一に分布してもよいし、放熱面41内に不均一に分布してもよい。半導体素子23の発熱量が集積回路30の発熱量よりも大きいときは、集積回路30に対応する放熱面41の第2領域よりも、半導体素子23に対応する放熱面41の第1領域に、より多くの1つ以上の凹部44が配置されてもよい。 In the semiconductor module 1c of the present embodiment, the heat radiating member 40 includes one or more recesses 44 on the heat radiating surface 41. Each of the one or more recesses 44 may be a columnar recess 44 as shown in FIG. 8 or a plate-shaped recess 44 as shown in FIG. The one or more recesses 44 may be uniformly distributed in the heat radiating surface 41, or may be unevenly distributed in the heat radiating surface 41. When the heat generation amount of the semiconductor element 23 is larger than the heat generation amount of the integrated circuit 30, the first region of the heat dissipation surface 41 corresponding to the semiconductor element 23 is set rather than the second region of the heat dissipation surface 41 corresponding to the integrated circuit 30. More one or more recesses 44 may be arranged.

本実施の形態の半導体装置は、実施の形態1の半導体装置5と同様の構成を備えるが、実施の形態1の半導体モジュール1に代えて、本実施の形態の半導体モジュール1cを備える点で異なる。 The semiconductor device of the present embodiment has the same configuration as the semiconductor device 5 of the first embodiment, except that the semiconductor module 1c of the present embodiment is provided instead of the semiconductor module 1 of the first embodiment. ..

本実施の形態の半導体モジュール1cの効果を説明する。本実施の形態の半導体モジュール1cは、実施の形態1の半導体モジュール1の効果に加えて、以下の効果を奏する。本実施の形態の半導体モジュール1cでは、放熱部材40は、放熱面41上に、1つ以上の凹部44を含む。1つ以上の凹部44は、放熱部材40における放熱面積を増加させる。そのため、半導体モジュール1cの放熱特性が改善され得る。 The effect of the semiconductor module 1c of the present embodiment will be described. The semiconductor module 1c of the present embodiment has the following effects in addition to the effects of the semiconductor module 1 of the first embodiment. In the semiconductor module 1c of the present embodiment, the heat radiating member 40 includes one or more recesses 44 on the heat radiating surface 41. The one or more recesses 44 increase the heat dissipation area of the heat dissipation member 40. Therefore, the heat dissipation characteristics of the semiconductor module 1c can be improved.

実施の形態4.
図10を参照して、実施の形態4に係る半導体モジュール1dを説明する。本実施の形態の半導体モジュール1dは、基本的には、実施の形態2の半導体モジュール1bと同様の構成を備えるが、主に以下の点で異なる。
Embodiment 4.
The semiconductor module 1d according to the fourth embodiment will be described with reference to FIG. The semiconductor module 1d of the present embodiment basically has the same configuration as the semiconductor module 1b of the second embodiment, but is mainly different in the following points.

本実施の形態の半導体モジュール1dでは、放熱部材40は、放熱面41上の1つ以上の凹部44と、1つ以上の凹部44の少なくとも一部に結合されて放熱面41から突出する1つ以上の突出部材46とを含む。1つ以上の突出部材46の各々は柱状の突出部材46であり、1つ以上の凹部44の各々は柱状の凹部44であってもよい。1つ以上の突出部材46の各々は板状の突出部材46であり、1つ以上の凹部44の各々は板状の凹部44であってもよい。1つ以上の突出部材46は、1つ以上の凹部44に圧入されてもよい。1つ以上の突出部材46は、1つ以上の凹部44に螺合してもよい。 In the semiconductor module 1d of the present embodiment, the heat radiating member 40 is one that is coupled to at least a part of one or more recesses 44 on the heat radiating surface 41 and one or more recesses 44 and protrudes from the heat radiating surface 41. The above-mentioned protruding member 46 is included. Each of the one or more projecting members 46 may be a columnar projecting member 46, and each of the one or more recesses 44 may be a columnar recess 44. Each of the one or more projecting members 46 may be a plate-shaped projecting member 46, and each of the one or more recesses 44 may be a plate-shaped recess 44. The one or more protruding members 46 may be press-fitted into the one or more recesses 44. The one or more protruding members 46 may be screwed into the one or more recesses 44.

1つ以上の突出部材46は、放熱面41内に均一に分布してもよいし、放熱面41内に不均一に分布してもよい。半導体素子23の発熱量が集積回路30の発熱量よりも大きいときは、集積回路30に対応する放熱面41の第2領域よりも、半導体素子23に対応する放熱面41の第1領域に、より多くの1つ以上の突出部材46が配置されてもよい。 The one or more protruding members 46 may be uniformly distributed in the heat radiating surface 41, or may be unevenly distributed in the heat radiating surface 41. When the heat generation amount of the semiconductor element 23 is larger than the heat generation amount of the integrated circuit 30, the first region of the heat dissipation surface 41 corresponding to the semiconductor element 23 is set rather than the second region of the heat dissipation surface 41 corresponding to the integrated circuit 30. More one or more protruding members 46 may be arranged.

本実施の形態の半導体モジュール1dの製造方法の一例では、半導体素子23、集積回路30、第1リードフレーム10、第2リードフレーム16、第3リードフレーム20、第1導電ワイヤ35及び第2導電ワイヤ36とともに放熱部材40を封止部材50でモールドした後、1つ以上の凹部44に1つ以上の突出部材46が結合されてもよい。 In an example of the method for manufacturing the semiconductor module 1d of the present embodiment, the semiconductor element 23, the integrated circuit 30, the first lead frame 10, the second lead frame 16, the third lead frame 20, the first conductive wire 35, and the second conductive wire are used. After molding the heat radiating member 40 together with the wire 36 with the sealing member 50, one or more projecting members 46 may be coupled to the one or more recesses 44.

本実施の形態の半導体装置は、実施の形態2の半導体装置と同様の構成を備えるが、実施の形態2の半導体モジュール1bに代えて、本実施の形態の半導体モジュール1dを備える点で異なる。 The semiconductor device of the present embodiment has the same configuration as the semiconductor device of the second embodiment, except that the semiconductor module 1d of the present embodiment is provided in place of the semiconductor module 1b of the second embodiment.

本実施の形態の半導体モジュール1dの効果を説明する。本実施の形態の半導体モジュール1dは、実施の形態2の半導体モジュール1bの効果に加えて、以下の効果を奏する。 The effect of the semiconductor module 1d of the present embodiment will be described. The semiconductor module 1d of the present embodiment has the following effects in addition to the effects of the semiconductor module 1b of the second embodiment.

本実施の形態の半導体モジュール1dでは、放熱部材40は、放熱面41上の1つ以上の凹部44と、1つ以上の凹部44の少なくとも一部に結合されて放熱面41から突出する1つ以上の突出部材46とを含む。そのため、半導体素子23の発熱量に応じて、1つ以上の突出部材46の数が定められ得る。本実施の形態の半導体モジュール1dは、半導体素子23に適した放熱特性を有するとともに、不必要な突出部材46を省略することによって半導体モジュール1dのコストが減少し得る。 In the semiconductor module 1d of the present embodiment, the heat radiating member 40 is one that is coupled to at least a part of one or more recesses 44 on the heat radiating surface 41 and one or more recesses 44 and protrudes from the heat radiating surface 41. The above-mentioned protruding member 46 is included. Therefore, the number of one or more protruding members 46 can be determined according to the amount of heat generated by the semiconductor element 23. The semiconductor module 1d of the present embodiment has heat dissipation characteristics suitable for the semiconductor element 23, and the cost of the semiconductor module 1d can be reduced by omitting the unnecessary protruding member 46.

本実施の形態の半導体モジュール1dは、半導体素子23、集積回路30、第1リードフレーム10、第2リードフレーム16、第3リードフレーム20、第1導電ワイヤ35及び第2導電ワイヤ36とともに放熱部材40を封止部材50でモールドした後、1つ以上の凹部44に1つ以上の突出部材46を結合することによって製造され得るように構成されている。本実施の形態の半導体モジュール1dは、実施の形態1の半導体モジュール1のモールド工程における金型と同じ金型を用いて製造され得るように構成されている。そのため、半導体モジュール1dのコストが減少し得る。 The semiconductor module 1d of the present embodiment includes a semiconductor element 23, an integrated circuit 30, a first lead frame 10, a second lead frame 16, a third lead frame 20, a first conductive wire 35, and a second conductive wire 36. It is configured so that it can be manufactured by molding 40 with a sealing member 50 and then connecting one or more protruding members 46 to one or more recesses 44. The semiconductor module 1d of the present embodiment is configured so that it can be manufactured by using the same mold as the mold in the molding process of the semiconductor module 1 of the first embodiment. Therefore, the cost of the semiconductor module 1d can be reduced.

実施の形態5.
図11を参照して、実施の形態5に係る半導体モジュール1eを説明する。本実施の形態の半導体モジュール1eは、基本的には、実施の形態1の半導体モジュール1と同様の構成を備えるが、主に以下の点で異なる。
Embodiment 5.
The semiconductor module 1e according to the fifth embodiment will be described with reference to FIG. The semiconductor module 1e of the present embodiment basically has the same configuration as the semiconductor module 1 of the first embodiment, but differs mainly in the following points.

本実施の形態の半導体モジュール1eは、第1部分11と放熱部材40との間に絶縁スペーサ55をさらに備える。絶縁スペーサ55は、第1部分11と放熱部材40との間の第1間隔g1を規定する。絶縁スペーサ55は、第1部分11と放熱部材40とに接着されていてもよい。The semiconductor module 1e of the present embodiment further includes an insulating spacer 55 between the first portion 11 and the heat radiating member 40. The insulating spacer 55 defines a first distance g 1 between the first portion 11 and the heat radiating member 40. The insulating spacer 55 may be adhered to the first portion 11 and the heat radiating member 40.

本実施の形態の半導体モジュール1eの製造方法の一例では、第1部分11と放熱部材40との間に絶縁スペーサ55を配置した後に、封止樹脂により、半導体素子23、第1リードフレーム10及び放熱部材40がモールドされる。絶縁スペーサ55は、このモールド工程において、半導体素子23と放熱部材40との間の電気的絶縁が安定的に確保され得る。 In an example of the method for manufacturing the semiconductor module 1e of the present embodiment, after arranging the insulating spacer 55 between the first portion 11 and the heat radiating member 40, the semiconductor element 23, the first lead frame 10 and the first lead frame 10 are made of a sealing resin. The heat radiating member 40 is molded. The insulating spacer 55 can stably secure electrical insulation between the semiconductor element 23 and the heat radiating member 40 in this molding process.

本実施の形態の半導体装置は、実施の形態1の半導体装置5と同様の構成を備えるが、実施の形態1の半導体モジュール1に代えて、本実施の形態の半導体モジュール1eを備える点で異なる。 The semiconductor device of the present embodiment has the same configuration as the semiconductor device 5 of the first embodiment, except that the semiconductor module 1e of the present embodiment is provided instead of the semiconductor module 1 of the first embodiment. ..

本実施の形態の半導体モジュール1eの効果を説明する。本実施の形態の半導体モジュール1eは、実施の形態1の半導体モジュール1の効果に加えて、以下の効果を奏する。本実施の形態の半導体モジュール1eは、第1部分11と放熱部材40との間に絶縁スペーサ55をさらに備える。絶縁スペーサ55は、第1部分11と放熱部材40との間の第1間隔g1を規定する。そのため、半導体素子23と放熱部材40との間の電気的絶縁が安定的に確保され得る。The effect of the semiconductor module 1e of the present embodiment will be described. The semiconductor module 1e of the present embodiment has the following effects in addition to the effects of the semiconductor module 1 of the first embodiment. The semiconductor module 1e of the present embodiment further includes an insulating spacer 55 between the first portion 11 and the heat radiating member 40. The insulating spacer 55 defines a first distance g 1 between the first portion 11 and the heat radiating member 40. Therefore, the electrical insulation between the semiconductor element 23 and the heat radiating member 40 can be stably secured.

今回開示された実施の形態はすべての点で例示であって制限的なものではないと考えられるべきである。矛盾のない限り、今回開示された実施の形態1から実施の形態5の少なくとも2つを組み合わせてもよい。本発明の範囲は、上記した説明ではなく請求の範囲によって示され、請求の範囲と均等の意味および範囲内でのすべての変更が含まれることを意図される。 It should be considered that the embodiments disclosed this time are exemplary in all respects and not restrictive. As long as there is no contradiction, at least two of the first to fifth embodiments disclosed this time may be combined. The scope of the present invention is shown by the scope of claims rather than the above description, and is intended to include all modifications within the meaning and scope of the claims.

1,1b,1c,1d,1e 半導体モジュール、5 半導体装置、10 第1リードフレーム、11 第1部分、12 第2部分、13 第3部分、14 第1端子部、16 第2リードフレーム、17 第4部分、18 第2端子部、20 第3リードフレーム、21 第5部分、22 第3端子部、23 半導体素子、24 第1の表面、25 第2の表面、26 第1電極、27 第2電極、28 第3電極、30 集積回路、35 第1導電ワイヤ、36 第2導電ワイヤ、40 放熱部材、41 放熱面、42 凸部、44 凹部、46 突出部材、50 封止部材、55 絶縁スペーサ、61 配線基板、62 第1配線、63 第2配線、65 接合部材。 1,1b, 1c, 1d, 1e Semiconductor module, 5 Semiconductor device, 10 1st lead frame, 11 1st part, 12 2nd part, 13 3rd part, 14 1st terminal part, 16 2nd lead frame, 17 4th part, 18 2nd terminal part, 20 3rd lead frame, 21 5th part, 22 3rd terminal part, 23 semiconductor element, 24 1st surface, 25 2nd surface, 26 1st electrode, 27th 2 electrodes, 28 3rd electrodes, 30 integrated circuits, 35 1st conductive wire, 36 2nd conductive wire, 40 heat dissipation member, 41 heat dissipation surface, 42 convex part, 44 concave part, 46 protruding member, 50 sealing member, 55 insulation Spacer, 61 wiring board, 62 first wiring, 63 second wiring, 65 joining member.

Claims (12)

半導体素子と、
前記半導体素子に電気的に接続される集積回路と、
前記半導体素子が載置される第1部分を含む第1リードフレームと、
前記集積回路が載置される第4部分を含む第2リードフレームと、
少なくとも前記半導体素子と前記第1部分と前記集積回路と前記第4部分とを封止する封止部材と、
前記封止部材に一体化されかつ前記半導体素子と前記集積回路とにおいて発生する熱を放散させる放熱部材とを備え、
前記放熱部材は、前記半導体素子と前記集積回路とに対向しており、
前記放熱部材は、前記封止部材から露出する放熱面を有し、
前記放熱部材は、前記封止部材によって、前記半導体素子前記第1部分と前記集積回路と前記第4部分とから絶縁されており
前記半導体素子の第1発熱量は、前記集積回路の第2発熱量よりも大きく、
前記放熱部材は、前記放熱面上に、凹部及び凸部のいずれかを含み、
前記半導体素子に対応する前記放熱面の第1領域には、前記集積回路に対応する前記放熱面の第2領域よりも多くの前記凹部及び前記凸部の前記いずれかが配置されている、半導体モジュール。
With semiconductor elements
An integrated circuit electrically connected to the semiconductor element and
A first lead frame including a first portion on which the semiconductor element is mounted,
A second lead frame including a fourth portion on which the integrated circuit is mounted, and
A sealing member that seals at least the semiconductor element, the first portion, the integrated circuit, and the fourth portion .
A heat radiating member integrated with the sealing member and dissipating heat generated in the semiconductor element and the integrated circuit is provided.
The heat radiating member faces the semiconductor element and the integrated circuit, and is opposed to the semiconductor element.
The heat radiating member has a heat radiating surface exposed from the sealing member.
The heat dissipation member, said by the sealing member are insulated from the semiconductor element and the first portion and said integrated circuit and said fourth portion,
The first calorific value of the semiconductor element is larger than the second calorific value of the integrated circuit.
The heat radiating member includes either a concave portion or a convex portion on the heat radiating surface.
A semiconductor in which any of the concave portions and the convex portions is arranged in the first region of the heat radiating surface corresponding to the semiconductor element, more than the second region of the heat radiating surface corresponding to the integrated circuit. module.
半導体素子と、With semiconductor elements
前記半導体素子に電気的に接続される集積回路と、An integrated circuit electrically connected to the semiconductor element and
前記半導体素子が載置される第1部分を含む第1リードフレームと、A first lead frame including a first portion on which the semiconductor element is mounted,
前記集積回路が載置される第4部分を含む第2リードフレームと、A second lead frame including a fourth portion on which the integrated circuit is mounted, and
少なくとも前記半導体素子と前記第1部分と前記集積回路と前記第4部分とを封止する封止部材と、A sealing member that seals at least the semiconductor element, the first portion, the integrated circuit, and the fourth portion.
前記封止部材に一体化されかつ前記半導体素子と前記集積回路とにおいて発生する熱を放散させる放熱部材とを備え、A heat radiating member integrated with the sealing member and dissipating heat generated in the semiconductor element and the integrated circuit is provided.
前記放熱部材は、前記半導体素子と前記集積回路とに対向しており、The heat radiating member faces the semiconductor element and the integrated circuit, and is opposed to the semiconductor element.
前記放熱部材は、前記封止部材から露出する放熱面を有し、The heat radiating member has a heat radiating surface exposed from the sealing member.
前記放熱部材は、前記封止部材によって、前記半導体素子と前記第1部分と前記集積回路と前記第4部分とから絶縁されており、The heat radiating member is insulated from the semiconductor element, the first portion, the integrated circuit, and the fourth portion by the sealing member.
前記半導体素子の第1発熱量は、前記集積回路の第2発熱量よりも大きく、The first calorific value of the semiconductor element is larger than the second calorific value of the integrated circuit.
前記放熱部材は、前記放熱面上の凹部と、前記凹部の少なくとも一部に結合されて前記放熱面から突出する突出部材とを含み、The heat radiating member includes a recess on the heat radiating surface and a protruding member that is coupled to at least a part of the recess and projects from the heat radiating surface.
前記半導体素子に対応する前記放熱面の第1領域には、前記集積回路に対応する前記放熱面の第2領域よりも多くの前記突出部材が配置されている、半導体モジュール。A semiconductor module in which more projecting members are arranged in a first region of the heat radiating surface corresponding to the semiconductor element than in a second region of the heat radiating surface corresponding to the integrated circuit.
前記第1部分は、前記半導体素子と前記放熱部材との間に配置されており、
前記第1部分は、前記放熱部材に対して、第1間隔を空けて配置されている、請求項1または請求項2に記載の半導体モジュール。
The first portion is arranged between the semiconductor element and the heat radiating member.
The semiconductor module according to claim 1 or 2 , wherein the first portion is arranged with a first interval with respect to the heat radiating member.
前記第1間隔は、100μm以上500μm以下である、請求項に記載の半導体モジュール。 The semiconductor module according to claim 3 , wherein the first interval is 100 μm or more and 500 μm or less. 前記第1リードフレームは、前記第1部分に接続される第2部分と、前記第2部分に接続される第3部分と、前記第3部分に接続される端子部とを含み、
前記第1部分と前記放熱部材との間の前記第1間隔が、前記第3部分と前記放熱部材との間の第2間隔よりも小さくなるように、前記第2部分は前記第1部分及び前記第3部分に対して傾斜している、請求項または請求項に記載の半導体モジュール。
The first lead frame includes a second portion connected to the first portion, a third portion connected to the second portion, and a terminal portion connected to the third portion.
The second portion includes the first portion and the heat radiating member so that the first distance between the first portion and the heat radiating member is smaller than the second spacing between the third portion and the heat radiating member. The semiconductor module according to claim 3 or 4 , which is inclined with respect to the third portion.
前記第1部分及び前記第2部分は、前記封止部材の中に埋め込まれている、請求項に記載の半導体モジュール。 The semiconductor module according to claim 5 , wherein the first portion and the second portion are embedded in the sealing member. 記第4部分は、前記集積回路と前記放熱部材との間に配置されており、
前記第1部分と前記放熱部材との間の前記第1間隔は、前記第4部分と前記放熱部材との間の第3間隔よりも小さい、請求項から請求項のいずれか1項に記載の半導体モジュール。
Before SL fourth portion is disposed between the heat radiating member and the integrated circuit,
According to any one of claims 3 to 6 , the first distance between the first portion and the heat radiating member is smaller than the third distance between the fourth part and the heat radiating member. The semiconductor module described.
第3リードフレームと、
前記第3リードフレームと前記半導体素子とに接続される第1導電ワイヤと、
前記集積回路と前記半導体素子とに接続される第2導電ワイヤとをさらに備え、
前記第1導電ワイヤは、前記第3リードフレーム及び前記半導体素子から前記放熱部材側とは反対側に引き出されており、
前記第2導電ワイヤは、前記集積回路及び前記半導体素子から前記放熱部材側とは反対側に引き出されている、請求項に記載の半導体モジュール。
With the third lead frame
A first conductive wire connected to the third lead frame and the semiconductor element,
A second conductive wire connected to the integrated circuit and the semiconductor element is further provided.
The first conductive wire is pulled out from the third lead frame and the semiconductor element to the side opposite to the heat radiating member side.
The semiconductor module according to claim 7 , wherein the second conductive wire is pulled out from the integrated circuit and the semiconductor element to a side opposite to the heat radiating member side.
前記第1部分と前記放熱部材との間に絶縁スペーサをさらに備える、請求項1から請求項のいずれか1項に記載の半導体モジュール。 The semiconductor module according to any one of claims 1 to 8 , further comprising an insulating spacer between the first portion and the heat radiating member. 前記放熱面以外の前記放熱部材の複数の表面は、前記封止部材に面している、請求項1から請求項のいずれか1項に記載の半導体モジュール。 The semiconductor module according to any one of claims 1 to 9 , wherein a plurality of surfaces of the heat radiating member other than the heat radiating surface face the sealing member. 前記半導体素子は、第1の表面と、前記第1の表面とは反対側の第2の表面とを有し、
前記半導体素子は、前記第1の表面上に設けられた第1電極と、前記第2の表面上に設けられた第2電極とを有し、
前記第2電極は前記第1リードフレームの前記第1部分に接合されている、請求項1から請求項10のいずれか1項に記載の半導体モジュール。
The semiconductor device has a first surface and a second surface opposite to the first surface.
The semiconductor element has a first electrode provided on the first surface and a second electrode provided on the second surface.
The semiconductor module according to any one of claims 1 to 10 , wherein the second electrode is bonded to the first portion of the first lead frame.
請求項1から請求項11のいずれか1項に記載の前記半導体モジュールと、
配線基板と、
前記半導体モジュールを前記配線基板上に固定する接合部材とを備える、半導体装置。
Said semiconductor module according to any one of claims 1 to 11,
Wiring board and
A semiconductor device including a joining member for fixing the semiconductor module on the wiring board.
JP2018550893A 2016-11-15 2016-11-15 Semiconductor modules and semiconductor devices Active JP6771581B2 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2016/083801 WO2018092185A1 (en) 2016-11-15 2016-11-15 Semiconductor module and semiconductor device

Publications (2)

Publication Number Publication Date
JPWO2018092185A1 JPWO2018092185A1 (en) 2019-04-11
JP6771581B2 true JP6771581B2 (en) 2020-10-21

Family

ID=62145418

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018550893A Active JP6771581B2 (en) 2016-11-15 2016-11-15 Semiconductor modules and semiconductor devices

Country Status (4)

Country Link
US (1) US11257732B2 (en)
JP (1) JP6771581B2 (en)
CN (1) CN210296341U (en)
WO (1) WO2018092185A1 (en)

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0567001A (en) 1991-09-09 1993-03-19 Nec Corp Cache memory circuit
JP3516789B2 (en) * 1995-11-15 2004-04-05 三菱電機株式会社 Semiconductor power module
JPH10112519A (en) * 1996-10-08 1998-04-28 Nippon Motorola Ltd Integrated circuit device with heat dissipation means and its manufacture
KR100403608B1 (en) * 2000-11-10 2003-11-01 페어차일드코리아반도체 주식회사 Stacked intelligent power module package and manufacturing method thereof
US7772036B2 (en) * 2006-04-06 2010-08-10 Freescale Semiconductor, Inc. Lead frame based, over-molded semiconductor package with integrated through hole technology (THT) heat spreader pin(s) and associated method of manufacturing
JP2013070026A (en) * 2011-09-08 2013-04-18 Rohm Co Ltd Semiconductor device, manufacturing method of semiconductor device, mounting structure of semiconductor device, and power semiconductor device
DE112012005791B4 (en) * 2012-01-31 2022-05-12 Mitsubishi Electric Corporation Semiconductor component and method for its manufacture
US9320173B2 (en) 2012-02-24 2016-04-19 Mitsubishi Electric Corporation Semiconductor device having a bulge portion and manufacturing method therefor
JP6028592B2 (en) 2013-01-25 2016-11-16 三菱電機株式会社 Semiconductor device
JP2016066639A (en) * 2014-09-22 2016-04-28 ファナック株式会社 Heat sink having fins connected in different methods
DE102015116807A1 (en) * 2015-10-02 2017-04-06 Infineon Technologies Austria Ag Functionalized interface structure

Also Published As

Publication number Publication date
CN210296341U (en) 2020-04-10
US11257732B2 (en) 2022-02-22
WO2018092185A1 (en) 2018-05-24
JPWO2018092185A1 (en) 2019-04-11
US20190259681A1 (en) 2019-08-22

Similar Documents

Publication Publication Date Title
US9171773B2 (en) Semiconductor device
JP3740117B2 (en) Power semiconductor device
JP6233507B2 (en) Power semiconductor modules and composite modules
JP6164364B2 (en) Semiconductor device
US9524929B2 (en) Semiconductor module package and method of manufacturing the same
JP2016018866A (en) Power module
US10163752B2 (en) Semiconductor device
JP6849660B2 (en) Semiconductor device
JP2017123360A (en) Semiconductor module
JP2014179376A (en) Semiconductor device and manufacturing method of the same
JP2016181536A (en) Power semiconductor device
WO2019038876A1 (en) Semiconductor device
JP2012064855A (en) Semiconductor device
US9633918B2 (en) Semiconductor device
JP2015076511A (en) Semiconductor device and manufacturing method of the same
WO2021005915A1 (en) Semiconductor device
JP2010050395A (en) Semiconductor device, and method of manufacturing the same
JP4046623B2 (en) Power semiconductor module and fixing method thereof
JP6248803B2 (en) Power semiconductor module
US9099451B2 (en) Power module package and method of manufacturing the same
JP2010177619A (en) Semiconductor module
JP6771581B2 (en) Semiconductor modules and semiconductor devices
JP2009231685A (en) Power semiconductor device
JP5062189B2 (en) Mounting structure of semiconductor device
JP2021027150A (en) Semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20181212

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20200212

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20200330

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20200901

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20200929

R150 Certificate of patent or registration of utility model

Ref document number: 6771581

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250