JP6757287B2 - Speed detector - Google Patents

Description

The present invention relates to a speed detection device that detects a rotation speed (in the present patent, the rotation speed is also referred to as a speed) with high accuracy from an incremental rotary encoder attached to a motor or a rotating body.

It has been widely practiced to detect a rotation position and a rotation speed from a rotary encoder attached to a motor or a rotating body to control the motor. Many inventions have been made with respect to these, and for example, the inventions of Patent Document 1 and Patent Document 2 are disclosed.

Here, the rotary encoder includes a method such as an incremental type that outputs a rectangular wave according to rotation, or an absolute type that outputs a rotation position as an absolute value. The present invention relates to an incremental rotary encoder, which will be referred to as an incremental encoder below.

Patent Document 1 discloses an invention of a speed detection device that inputs an A-phase signal and a B-phase signal output by an incremental encoder, and an embodiment thereof is cited in FIG. The speed detection device includes a latch signal creation unit 21, one angle measurement counter 22, and a time measurement counter 23. Then, the latch signal creating unit 21 detects four types of edges from the A-phase signal and the B-phase signal in one cycle, and each time each edge is detected, the phase generated by the angle measurement counter 22 and the time measurement counter 23 is generated. The corner and sample time are divided into four types of edges and latched respectively.

かように、該特許文献１ではインクリメンタルエンコーダが出力するＡ相信号、Ｂ相信号から検出した任意の１つエッジ種類にて検出と演算をするので、速度検出周期が早い、精度向上を図るなどの特徴があるとしている。 Then, the displacement (rotational phase deviation) Δθ of the phase angle of any of the edge types and the difference (capture time deviation) Δt of the sample time are detected for each speed calculation cycle, and the rotation speed ω is calculated by the following equation (1). It is supposed to be calculated.
(Equation 1)

As described above, in Patent Document 1, since the detection and calculation are performed with any one edge type detected from the A-phase signal and the B-phase signal output by the incremental encoder, the speed detection cycle is fast and the accuracy is improved. It is said that it has the characteristics of.

Patent Document 1 has an angle measurement counter 22, but Patent Document 2 discloses an invention of a speed detection device that does not use the angle measurement counter.
In the speed detection device of Patent Document 2, four types of edges are detected from one cycle of the A-phase signal and the B-phase signal output by the incremental encoder, and the detection times of these edges are recorded to perform speed calculation. .. Further, an invention is disclosed in which the speed calculation cycle is shifted by a predetermined time when the edge and the speed calculation cycle occur at the same time.
As described above, Patent Document 1 and Patent Document 2 are variously devised for speed detection.

Here, a conventional basic speed detection method will be described with reference to FIG.
In FIG. 10, 1, 2, and 3 are an incremental encoder, a signal line, and a conventional speed detection device, respectively. The incremental encoder 1 outputs a continuous rectangular wave (pulse) according to rotation, and here, an example is shown in which the output is an A-phase signal and a B-phase signal having a phase difference of 90 degrees. Then, the A-phase signal and the B-phase signal are input to the speed detection device 3 via the signal line 2.

Next, the device built in the speed detection device 3 will be described. In FIG. 10, 4, 5, and 10 are an input interface, a signal converter, and a rotation position counter, respectively. The input interface 4 inputs the A-phase signal and the B-phase signal, performs filter processing, waveform shaping processing, and insulation processing, respectively, to generate and output an A5 signal and a B5 signal.
Then, the signal converter 5 inputs the A5 signal and the B5 signal, and from these two signals, the A-phase signal or the 4F signal (or twice the frequency) which is four times the frequency of the B-phase signal. 2F signal) and FR signal indicating the rotation direction are output. Then, the rotation position counter 10 is an up / down counter, inputs the 4F signal and the FR signal, and outputs the rotation position P of the rotary encoder 1.

Similarly, in FIG. 10, 11, 12, and 13 are an oscillator, a timer, and a time latch, respectively. The oscillator 11 generates a reference frequency signal having a fixed cycle such as 20 MHz or 40 MHz, and the timer 12 is a counter that inputs the reference frequency signal and generates and outputs a real-time RT. The timer 12 is composed of a down counter or an up counter.
Then, the time latch 13 inputs the 4F signal and the real-time RT, and outputs the capture time T, which is the time when the rotation position P is updated.

なお、マイクロプロセッサやデジタルシグナルプロセッサなどを総称して以下にＭＰＵと表記する。 Similarly, in FIG. 10, reference numeral 15 denotes a speed detector composed of a microprocessor, a digital signal processor, or the like, and inputs the rotation position P and the capture time T at regular control cycles. Then, the speed detector 15 detects the capture time deviation ΔT and the rotation position deviation ΔP of the previous control cycle and the current control cycle, and calculates the rotation speed V in the same manner as in the above equation (1).
(Equation 2)

In addition, the microprocessor and the digital signal processor are generically referred to as MPU below.

Next, FIG. 11 will supplement and explain the temporal transition of each signal of FIG. 10 described above by illustration. (1) and (2) of FIG. 11 show the phase changes of the A-phase signal and the B-phase signal, respectively, and the left side, the center, and the right side of this figure are the cases of reverse rotation, stop, and forward rotation, respectively. The B-phase signal is 90 degrees ahead of the A-phase signal when it is reversed, and 90 degrees behind when it is forward. Then, the A5 signal and the B5 signal have the same phase change as the A-phase signal and the B-phase signal.
Subsequently, (3) and (4) of FIG. 11 are 4F signals and FR signals output by the signal converter 5, and the 4F signals are the (1) A phase signal and (2) B phase signal. The rising edge and the falling edge are pulsed, and the frequency of this is four times that of the A-phase signal. Further, the FR signal is a signal that detects the rotation direction, and here, forward rotation and reverse rotation are set to 0 and 1, respectively.

このとき、前記図１１の（１）Ａ相信号と（３）４Ｆ信号のそれぞれの周波数は次のとおりとなる。
(数４)

(数５)

また前記（２）式において、ΔＴは前記（２）式の制御周期１６０μｓとすれば、ΔＰは４Ｆ信号のとき、次のとおり１１パルスとなる。
(数６)

Next, (5) and (6) of FIG. 11 show the temporal transition of the rotation phase P output by the rotation phase counter 10 and the real-time RT output by the timer 12, respectively. And (7) of FIG. 11 shows the control cycle of the speed detector 15.
Here, in order to facilitate the following explanation, one numerical example is as follows.
Number of pulses per rotation of the incremental encoder 1: 600 ppr
Rotation speed of the incremental encoder 1: 1800min ^-1
(Equation 3)

At this time, the frequencies of the (1) A-phase signal and (3) 4F signal in FIG. 11 are as follows.
(Equation 4)

(Equation 5)

Further, in the above equation (2), if ΔT is the control cycle 160 μs of the above equation (2), then when ΔP is a 4F signal, it becomes 11 pulses as follows.
(Equation 6)

Japanese Unexamined Patent Publication No. 6-118090 Japanese Unexamined Patent Publication No. 2010-8235

Conventionally performed speed detection methods are shown in Patent Document 1, Patent Document 2, and FIG. 10. Here, the speed detection device according to the present invention has an accurate speed even when the characteristics of the incremental encoder 1, the circuit configuration of the speed detection device 3, and the installation conditions and ambient temperatures of these devices are different. The purpose is to stably realize the detection of.
Then, the problem to be solved by the present invention for realizing this will be described with reference to FIGS. 12 to 17 based on FIG. 10 which explains the conventional example.

The first problem will be described with reference to FIG. 10 with reference to FIG. As the incremental encoder 1 of FIG. 10, many optical encoders 1 are used, which will be described with reference to FIG. FIG. 12 (1) briefly shows the configuration of the incremental encoder 1. An optical slit is provided radially on a slit disk of a rotating object to be detected, and this is used as a light emitting element and A-phase light receiving. The element and the B-phase light receiving element generate continuous pulses according to rotation. The A-phase light receiving element and the B-phase light receiving element are physically adjusted in position so that the A-phase signal and the B-phase signal, which will be described later, have a phase difference of 90 degrees.

The incremental encoder 1 shapes the outputs of the A-phase light receiving element and the B-phase light receiving element into a rectangular wave, and outputs the A-phase signal and the B-phase signal shown in FIGS. 12 (2) and 12 (3). .. In this figure, when the incremental encoder 1 rotates in the normal rotation, the phase of the A-phase signal is 90 degrees ahead of that of the B-phase signal. Next, (4) and (5) in FIG. 12 are shown by enlarging the sections shown by the dotted lines in FIGS. 12 (2) and (3). In this figure, T1, T2, and T3 indicate one cycle, high section, and low section of the A-phase signal and B-phase signal, respectively, and T4, T5, T6, and T7 are based on the A-phase signal and B-phase signal. It shows four sections that are divided.
Next, FIG. 12 (6) is a 4F signal in which the rising and falling edges of the A-phase signal and the B-phase signal are pulsed, and the frequency of this is four times that of the A-phase signal. Conventionally, the rotation speed of the incremental encoder 1 is detected by the 4F signal.

Here, in order to detect the rotation speed with high accuracy, it is important that T2 and T3 are equal to each other and that T4, T5, T6, and T4 are equal to each other, but there are the following problems in practical use. ..

In (1) of FIG. 12, the slit pitch of the slit disk is optically manufactured with extremely high accuracy, and the (4) A-phase signal of FIG. 12 obtained from the A-phase light receiving element is also accurately generated. Therefore, the fluctuation of the duty of T2 and T3 becomes slight, and the same applies to the B-phase signal (5) of FIG. However, since the A-phase light receiving element and the B-phase light receiving element are physically installed, the accuracy of the mutual phase difference is inferior. Next, this will be specifically described with reference to FIG.

(1), (2), and (3) of FIG. 13 represent the temporal transition of the A-phase signal, the B-phase signal, and the 4F signal, respectively, and (4), (5), and (6) of FIG. ) Corresponds to each. As shown above, the (1) A-phase signal in FIG. 13 has a slight variation in duty between T2 and T3. On the other hand, since the accuracy of attaching the A-phase light receiving element and the B-phase light receiving element is inferior to the accuracy of the slit pitch of the slit disk, the (2) B-phase signal of FIG. 13 is a dotted line with respect to the (1) A-phase signal. As shown in, an error (fluctuation) occurs. As a result, when the incremental encoder 1 rotates at a constant speed, the period of the 4F signal shown in FIG. 13 (3) is disturbed and the correct rotation speed cannot be obtained. Then, as the incremental encoder 1 rotates faster, there is a problem that the influence of the fluctuation between the A-phase signal and the B-phase signal becomes larger in the detection of the rotation speed, and the correct rotation speed cannot be obtained.

Then, in order to facilitate the explanation of this problem, if a numerical example is shown, when the fluctuation is 20% in each of the sections T4 to T7 and the condition of the above equation (3) is satisfied, the speed is detected from the above equation (6). The error is 1.8% (20% divided by 11), which hinders the quality of product production. The solution to this is the first problem to be solved by the present invention.

FIG. 14 will be described in order to show the next problem. FIG. 14 shows a configuration example of the input interface 4 of FIG. 10, and the incremental encoder 1 and the signal line 2 in the figure have the same functions as those having the same reference numerals in FIG. 10, and the description thereof will be omitted. To do.

FIG. 14 shows an example of a noise removal and signal distortion shaping circuit that are normally performed when the A-phase signal and the B-phase signal output by the incremental encoder 1 are input to the speed detection device 3. Is shown. In FIG. 14, 4-1, 4-2, 4-3, and 4-4 are filters, comparators, photocouplers, and converters, respectively, and the function of the filters 4-1 is noise reduction, and the comparators. The function of 4-2 is waveform shaping.
Next, the photocoupler 4-3 electrically insulates the incremental encoder 1 side from the subsequent electronic circuit side of the input interface 4, and the converter 4-4 waveform-shapes the output of the photocoupler 4-3. It is a thing.
Then, A1 to A5 in the figure indicate the respectively illustrated input / output points of the filters 4-1 to the converter 4-4 for the A phase signal, and B1 to B5 indicate the same input / output points for the B phase signal. Is

Next, the second problem to be solved by the present invention will be described with reference to FIG. 14 with reference to FIG. In FIG. 14, when the input interface 4 is composed of the filter 4-1 and the comparator 4-2, FIG. 15 shows the waveform of each point for the A-phase signal with the passage of time. Fifteen (1) A1 signal, (2) A2 signal, and (3) A3 signal show the waveforms of the signals at points A1, A2, and A3 in FIG. 14, respectively.

First, the (1) A1 signal in FIG. 15 is an input waveform of the filter 4-1 and has a peak value V1 and a period T1. Further, in order to facilitate the explanation later, it is assumed that the time of the high section T2-1 and the time of the low section T2-2 are equal.
Next, the A2 signal (2) in FIG. 15 is an input waveform of the comparator 4-2, and this waveform has a gradual rising and falling edge as shown by the filter 4-1. Further, the comparator 4-2 usually has a hysteresis characteristic, and Vh1 and Vl1 in the figure are a hysteresis high voltage and a hysteresis low voltage of the comparator 4-2, respectively.

Next, the (3) A3 signal of FIG. 15 will be described. The A3 signal is the output waveform of the comparator 4-2, and due to the hysteresis characteristic of the comparator 4-2, the rising edge and the falling edge are delayed from the A2 signal by the delay times T3-1 and T3-2, respectively.
Then, the high section and the low section of the A3 signal are T4-1 and T4-2, respectively. Here, the delay times T3-1 and T3-2 have different values due to the difference between the rising and falling times of the A2 signal and the existence of the hysteresis high voltage Vh1 and the hysteresis low voltage Vl1. The intervals T4-1 and T4-2 also have different values.

Next, FIG. 15 (4) is a case where a 2FA signal (not shown in FIG. 14) in which the rising and falling edges of the A3 signal are pulsed is used to detect the speed, and the frequency of this is A. It is twice the phase signal. However, the period of the 2FA signal becomes T4-1 and T4-2 as shown in the figure, and variations occur. As described above in FIGS. 15 (1) to (4), the correct rotation is performed when the speed is detected from the 2FA signal extracted from the A phase signal due to the hardware of the input interface 4. There is a problem that the speed cannot be obtained.

ここで、前記区間Ｔ４-１のばらつきが１５％のとき、該（７）式より速度検出の誤差は３％（１５％を５で除した値）となって製品の生産において品質に支障をきたすものであり、これの解消が本発明にて解決しようとする第２の課題である。
なお、前記図１５はＡ相信号について説明したが、Ｂ相信号についても同様である。 If this problem is concretely shown by a numerical example, in the case of the 2FA signal under the condition of the above equation (3), ΔP becomes 5 pulses as follows instead of the above equation (6).
(Equation 7)

Here, when the variation of the section T4-1 is 15%, the error of speed detection becomes 3% (value obtained by dividing 15% by 5) from the equation (7), which hinders the quality in product production. It is a problem, and its solution is the second problem to be solved by the present invention.
Although the A-phase signal has been described in FIG. 15, the same applies to the B-phase signal.

The next problem to be solved by the present invention will be described with reference to FIG. 14 with reference to FIG. Here, FIG. 15 shows the operation by the filter 4-1 and the comparator 4-2 of FIG. 14, but in FIG. 16, the photocoupler 4-3 and the converter 4-4 are added in addition to the operation. It represents the operation of the time. The (1), (2), and (3) of FIG. 16 are the same as those of (1), (2), and (3) of FIG. 15, and the description thereof is omitted. ) A4 signal and (5) A5 signal represent the temporal transition of the signal at points A4 and A5 in FIG. 14, respectively.

Then, the photocoupler 4-3 inputs (3) A3 signal of FIG. 16 and outputs (4) A4 signal, which has a gentle rising edge and falling edge as shown in the figure. The A4 signal is an input of the converter 4-4. In the figure, V2 is the peak value, and Vh2 and Vl2 are the hysteresis high voltage and the hysteresis low voltage of the converter 4-4, respectively.
Next, the (5) A5 signal of FIG. 16 will be described. The A5 signal is the output waveform of the converter 4-4, and due to the hysteresis characteristic of the converter 4-4, the rising edge and the falling edge are delayed from the A3 signal by the delay times T5-1 and T5-2, respectively.

Then, the high section and the low section of the A5 signal are T6-1 and T6-2, respectively. Here, the delay times T5-1 and T5-2 have different values due to the difference between the rising and falling times of the A4 signal and the existence of the hysteresis high voltage Vh2 and the hysteresis low voltage Vl2. The values of the intervals T6-1 and T6-2 are also different.

Next, FIG. 16 (6) shows a 2FA signal (not shown in FIG. 14) in which the rising and falling edges of the A5 signal are pulsed in order to detect the speed, and the frequency of this is A. It is twice the phase signal. However, as shown in the figure, the period of the 2FA signal becomes T6-1 and T6-2, and variations occur.
As described above in FIGS. 16 (3) to 16 (6), even when the speed is detected from the 2FA signal extracted only from the A phase signal due to the hardware of the input interface 4. The correct rotation speed cannot be obtained, which is the same as the second problem shown in FIG. 15, and errors are accumulated due to a circuit configuration such as installing the comparator 4-2 and the photocoupler 4-3 together. Will be done. Although FIG. 16 describes the A-phase signal, the same applies to the B-phase signal.

That is, in the input interface 4 of FIG. 14, even if there are a plurality of circuit configurations that deform the waveform, such as the filter 4-1 and the photocoupler 4-3 mentioned as examples of the required functions, the speed is accurate. Is the second task.

Next, the third problem to be solved by the present invention will be described with reference to FIG. 14 with reference to FIG. FIG. 17 shows the operation of the input interface 4 when the wiring distance of the signal line 2 is long in FIG.

First, the phase A signal (1) in FIG. 17 is an output waveform of the incremental encoder 1, and has a peak value V1 and a period T1. Further, in order to facilitate the explanation later, it is assumed that the time of the high section T2-1 and the time of the low section T2-2 are equal.
The A1 signal in FIG. 17 (2) is an input waveform of the filter 4-1 built in the input interface 4, and is shown by the characteristic impedance of the signal line 2 because the wiring distance of the signal line 2 is long. It has a gentle rise and fall, and the peak value is also dropped from V1 to V3.

Next, in the (3) A2 signal of FIG. 17, the solid line represents the output of the filter 4-1 and the dotted line represents the (2) A1 signal that is the input of the filter 4-1 for comparison. .. Further, in this figure, V1 and V3 are described by the above (2) A1 signal, and V4 is the peak value of the output of the filter 4-1. Since the (3) A2 signal has a long wiring distance of the signal line 2, it is further modified from the (2) A1 signal of FIG. 15 described above.
The (3) A2 signal is also an input of the comparator 4-2, and also shows a hysteresis high voltage Vh1 and a hysteresis low voltage Vl1.

Next, with respect to the A3 signal (4) of FIG. 17, the A3 signal is the output waveform of the comparator 4-2, and due to the hysteresis characteristics of the comparator 4-2, the rising and falling delay times from the A2 signal, respectively. The delay is indicated by T7-1 and T7-2.
Then, the high section and the low section of the A3 signal are T8-1 and T8-2, respectively. Here, the delay times T7-1 and T7-2 have different values due to the difference between the rising and falling times of the A2 signal and the existence of the hysteresis high voltage Vh1 and the hysteresis low voltage Vl1. The intervals T8-1 and T8-2 also have different values.

Next, FIG. 17 (5) is a 2FA signal in which the rising and falling edges of the A3 signal are pulsed in order to detect the speed, as in the case of FIG. 15 (4) (not shown in FIG. 14). The frequency of this is twice that of the A-phase signal. However, the period of the 2FA signal becomes T8-1 and T8-2 as shown in the figure, and variations occur. As shown in FIG. 17 (2), since the wiring distance of the signal line 2 is long, the waveform output by the incremental encoder 1 is deformed, and the speed is derived from the 2FA signal extracted from the A phase signal. When the detection is performed, the correct rotation speed cannot be obtained, and the solution to this is the third problem.
Although the A-phase signal has been described in FIG. 17, the same applies to the B-phase signal.

Here, as shown in (2) A1 signal and (3) A3 signal in FIG. 17, it is shown that the A-phase signal and the B-phase signal output by the incremental encoder 1 are deformed and transmitted. However, this is because the waveforms of the A-phase signal and the B-phase signal are further deformed not only when the wiring distance of the signal line 2 is long, but also due to the environment in which each device is installed, the room temperature, and the temperature change due to the operation of the device. As a result, in the 2FA signal of FIG. 17 (5), the times of the sections T8-1 and T8-2 fluctuate from moment to moment, and when speed detection is performed from the 2FA signal, the correct rotation speed cannot be obtained. The solution to this is the fourth issue.

It is composed of an incremental encoder and a speed detection device. The incremental encoder outputs a continuous rectangular wave signal of A-phase signal and B-phase signal with a phase difference of 90 degrees according to rotation, and the speed detection device outputs an input interface and a signal. It has a built-in converter, rotation position counter and time latch, and speed detector.

The input interface inputs the A-phase signal and the B-phase signal output by the incremental encoder and outputs the A5 signal and the B5 signal that have been filtered, insulated, or waveform-shaped to the signal converter. The rotation position counter and the time latch each output the rotation position and the time (capture time) at which the rotation position was obtained by the signal output from the signal converter. The present invention relates to a speed detection device in which the speed detection unit detects a speed based on the rotation position and the capture time.

Further explaining, the signal converter built in the speed detection device has a rising edge when the rotation direction of the incremental encoder is forward rotation and a falling edge when the rotation direction of the incremental encoder is reverse rotation for the input A5 signal. Along with generating a pulse A + signal, a rotation direction FRA + signal indicating the rotation direction when the pulse A + signal is generated is generated.
Similarly, the signal converter generates a pulse A- signal at the falling edge when the input A5 signal rotates in the forward direction of the incremental encoder, and at the rising edge when the rotation direction of the incremental encoder is reversed, and the pulse. A rotation direction FRA- signal indicating the rotation direction when the A- signal is generated is generated.

Similarly, the signal converter generates a pulse B + signal at the rising edge when the input B5 signal rotates in the forward direction of the incremental encoder, and at the falling edge when the rotation direction of the incremental encoder is reversed, and the pulse B + signal. A rotation direction FRB + signal indicating the rotation direction when the signal is generated is generated.
Similarly, the signal converter generates a pulse B- signal at the falling edge when the input B5 signal rotates in the forward direction of the incremental encoder, and at the rising edge when the rotation direction of the incremental encoder is reversed, and also generates the pulse B- signal. A rotation direction FRB- signal indicating the rotation direction when the B- signal is generated is generated.

Further, the speed detection device incorporates four sets of rotation position counters and a time latch, and the four sets of rotation position counters have the functions of up / down counters, and the pulse A + signal and the rotation direction FRA + signal, respectively. By inputting the pulse A- signal and the rotation direction FRA- signal, the pulse B + signal and the rotation direction FRB + signal, and the pulse B- signal and the rotation direction FRB- signal, the rotation position PA +, the rotation position PA-, and the rotation position Detects and outputs PB + and rotation position PB-.
Further, the four sets of time latches input the pulse A + signal, the pulse A- signal, the pulse B + signal, and the pulse B- signal, respectively, to input the rotation position PA +, the rotation position PA-, and the rotation position PB +. , And the time when the rotation position PB− is updated is captured (captured), and the capture time TA +, the capture time TA−, the capture time TB +, and the capture time TB− are output.

The speed detection unit built in the speed detection device further incorporates four sets of memories, and the first set of memories PA + (0), TA + (0), PA + (-1), and TA + (-1). ), When the MPU built in the speed detection device checks and updates the capture time TA + at each speed detection timing, the memory PA + (0) and the memory TA + (0) are set to the memory PA + (0), respectively. After saving in -1) and memory TA + (-1), the rotation position PA + and the capture time TA + are saved in the memory PA + (0) and the memory TA + (0), respectively.
Next, with respect to the second set of memories PA- (0), TA- (0), PA- (-1), and TA- (-1), the MPU sets the capture time TA- for each speed detection timing. When checked and updated, the memory PA- (0) and the memory TA- (0) are saved in the memory PA- (-1) and the memory TA- (-1), respectively, and then the rotation position PA. -And the capture time TA- are saved in the memory PA- (0) and the memory TA- (0), respectively.

Further, regarding the third set of memories PB + (0), TB + (0), PB + (-1), and TB + (-1), the MPU checks and updates the capture time TB + at each speed detection timing. When, after saving the memory PB + (0) and the memory TB + (0) in the memory PB + (-1) and the memory TB + (-1), respectively, the rotation position PB + and the capture time TB + are stored in the memory PB +, respectively. Save to (0) and memory TB + (0).
Then, for the fourth set of memories PB- (0), TB- (0), PB- (-1), and TB- (-1), the MPU checks the capture time TB- for each speed detection timing. When updated, the memory PB- (0) and the memory TB- (0) are saved in the memory PB- (-1) and the memory TB- (-1), respectively, and then the rotation position PB- And the capture time TB- are saved in the memory PB- (0) and the memory TB- (0), respectively.

Next, the MPU built in the speed detection device compares the rotation speed of the incremental encoder with a predetermined speed establishment level for each speed detection timing. Then, when the rotation speed is less than the speed establishment level, the speed detection device uses the memory TA + (0), TA- (0), TB + (0), and TB- (0) at the latest time. The set calculates one of velocity VA + (n), VA− (n), VB + (n), or VB− (n) and outputs the velocity.

When the rotation speed of the incremental encoder is equal to or higher than the speed establishment level, the speeds VA + (n), VA- (n), and the same set as the set for which the speed was calculated at the previous speed detection timing are continuously used. It is a speed detection device characterized in that the speed of one of VB + (n) or VB- (n) is calculated, or a plurality of speeds are calculated and averaged, and the speed is output.

As described above, when detecting the speed from the incremental encoder, even if the signal line between the incremental encoder and the speed detection device is long, regardless of the circuit configuration of the input interface of the speed detection device. Further, regardless of whether the ambient temperature is high or low, a speed detection device that always detects a stable speed with high accuracy without impairing the accuracy of the incremental encoder is realized. As a result, the speed detection device according to the present invention can be used to accurately detect the rotation speed of the electric motor and the speed of the transfer device to realize the production of high-quality products.

It is a figure explaining the structure of the Example of this invention. It is a figure explaining the output of an incremental encoder. It is a figure explaining the operation of the input interface of this invention. It is a figure (the 2) explaining the operation of the input interface of this invention. It is a figure (the 3) explaining the operation of the input interface of this invention. It is a figure explaining the operation of a rotation phase counter. It is a figure (the 2) explaining the output of an incremental encoder. It is a figure explaining speed detection. This is an example of Patent Document 1. It is a figure explaining the conventional example of speed detection. It is a figure explaining the operation of the speed detection device. It is a figure explaining the incremental encoder. It is a figure (the 3) explaining the output of an incremental encoder. This is a configuration example of the input interface. It is a figure explaining the operation of an input interface. It is a figure (the 2) explaining the operation of an input interface. It is a figure (the 3) explaining the operation of an input interface.

A diagram of an embodiment of the present invention will be shown below for description. FIG. 1 shows an embodiment of the present invention, and FIGS. 2, 3, 4, 5, 5, 7, and 8 supplementarily explain the operation of FIG. 1.

FIG. 1 is a diagram illustrating a configuration of an embodiment of the speed control device 3-1 according to the present invention. In FIG. 1, the incremental encoder 1, the signal line 2, the input interface 4, the rotation position counter 10, the oscillator 11, the timer 12, and the time latch 13 have the same functions as those having the same reference numerals in FIG. I will omit the explanation of this. The speed detection device 3-1, the signal converter 5-1 and the speed detection unit 15-1 are according to the present invention.

First, the signal converter 5-1 built in the speed detection device 3-1 will be described. The signal converter 5-1 inputs the A5 signal and the B5 signal output by the input interface 4, detects and outputs four sets of pulse trains and rotation direction signals from the two signals.
Then, to explain the first set of the pulse train and the rotation direction signal, the signal converter 5-1 reverses the input A5 signal at the rising edge when the rotation direction of the incremental encoder 1 is forward rotation. In the case of, a pulse A + signal is generated and output at the falling edge, and a rotation direction FRA + signal indicating the rotation direction when the pulse A + signal is generated is generated and output.

Next, the second set of the pulse train and the rotation direction signal will be described. With respect to the input A5 signal, the signal converter 5-1 is at a falling edge when the rotation direction of the incremental encoder 1 is forward rotation. In the case of reverse rotation, a pulse A- signal is generated and output at the rising edge, and a rotation direction FRA- signal indicating the rotation direction when the pulse A- signal is generated is generated and output.

Next, the third set of the pulse train and the rotation direction signal will be described. With respect to the input B5 signal, the signal converter 5-1 is at the rising edge when the rotation direction of the incremental encoder 1 is forward rotation. In the case of reverse rotation, a pulse B + signal is generated and output at the falling edge, and a rotation direction FRB + signal indicating the rotation direction when the pulse B + signal is generated is generated and output.

Then, to explain the fourth set of the pulse train and the rotation direction signal, the signal converter 5-1 receives the input B5 signal at the falling edge when the rotation direction of the incremental encoder 1 is forward rotation. In the case of reverse rotation, a pulse B- signal is generated and output at the rising edge, and a rotation direction FRB- signal indicating the rotation direction when the pulse B- signal is generated is generated and output.
In this way, the signal converter 5-1 detects and outputs four sets of pulse trains and rotation direction signals.

Next, in FIG. 1, 6 shown by a dotted line is an A + processing block that processes the first set of the pulse A + signal and the rotation direction FRA + signal. Similarly, 7, 8 and 9 shown by dotted lines are the processing blocks of the second set of the pulse A- signal and the rotation direction FRA- signal A-, respectively, and the third set of the pulse B + signal and the rotation direction FRB + signal. The B + processing block and the fourth set of the pulse B- signal and the rotation direction FRB- signal B- processing block will be described in sequence.

First, the processing block 6 of the A + has the rotation phase counter 10 and the time latch 13 dedicated to this block. Then, the rotation phase counter 10 inputs the pulse A + signal and the rotation direction FRA + signal to perform count-up or count-down, and detects and outputs the rotation position PA +. Further, the time latch 13 inputs the pulse A + signal and the real-time RT, detects and outputs the capture time TA + which is the time when the rotation position PA + is updated.

Here, the speed detection device 3-1 has a built-in MPU (not shown), and the speed detection unit 15-1 has four sets of memories for the rotation position and capture. The first set is the memory PA + (0), TA + (0), PA + (-1), and TA + (-1) in the processing block 6 of the A +, and the second set is the processing of the A−. The memory PA- (0), TA- (0), PA- (-1), and TA- (-1) in the block 7, and the third set is the memory PB + (0) in the processing block 8 of the B +. ), TB + (0), PB + (-1), and TB + (-1), and the fourth set is the memory PB- (0), TB- (0), PB- in the processing block 9 of the B-. (-1) and TB- (-1).

Then, in the processing block 6 of the A +, when the MPU of the speed detection device 3-1 checks and updates the capture time TA + for each control cycle, the memory PA + (0) and the memory TA + (0) are updated. ) Are saved in the memory PA + (-1) and the memory TA + (-1), respectively, and then the rotation position PA + and the capture time TA + are saved in the memory PA + (0) and the memory TA + (0), respectively.

(数９)

Next, the speed detection unit 15-1 incorporates a speed calculator 16, and the speed calculator 16 executes the four speed calculations shown in 16-1, 16-2, 16-3, and 16-4. They belong to the A + processing block 6, the A− processing block 7, the B + processing block 8, and the B− processing block 9, respectively.
Then, the speed calculation 16-1 in the processing block 6 of the A + calculates ΔP and ΔT by the following equations (8) and (9) according to the regularity described later, and performs the calculation of the equation (2). This will give the velocity VA + (n).
(Equation 8)

(Equation 9)

The processing of the processing block 6 of the A + has been described above. Similarly, the processing block 7 of the A− processes the pulse A− signal and the rotation direction FRA− signal.
That is, the processing block 7 of A- in FIG. 1 has the rotation phase counter 10 and the time latch 13 dedicated to this block. Then, the rotation phase counter 10 inputs the pulse A- signal and the rotation direction FRA- signal to perform count-up or count-down, and detects and outputs the rotation position PA-. Further, the time latch 13 inputs the pulse A- signal and the real-time RT, detects and outputs the capture time TA- which is the time when the rotation position PA- is updated.

Similarly, in the processing block 7 of the A-, when the MPU of the speed detection device 3-1 checks and updates the capture time TA- for each control cycle, the memory PA- (0) and the memory After saving TA- (0) in the memory PA- (-1) and the memory TA- (-1), respectively, the rotation position PA- and the capture time TA- are stored in the memory PA- (0) and the memory, respectively. Save to TA- (0).

Then, the speed calculation 16-2 in the processing block 7 of the A- calculates ΔP and ΔT according to the equations (8) and (9) according to the regularity described later, and the equation (2) is described. Is calculated to obtain the velocity VA− (n).

Next, the B + processing block 8 of FIG. 1 processes the pulse B + signal and the rotation direction FRB + signal, and the B + processing block 8 is the rotation phase counter 10 and the time latch 13 dedicated to this block. have. Then, the rotation phase counter 10 inputs the pulse B + signal and the rotation direction FRB + signal to perform count-up or count-down, and detects and outputs the rotation position PB +. Further, the time latch 13 inputs the pulse B + signal and the real-time RT, detects and outputs the capture time TB + which is the time when the rotation position PB + is updated.

Similarly, in the processing block 8 of the B +, when the MPU of the speed detection device 3-1 checks and updates the capture time TB + for each control cycle, the memory PB + (0) and the memory TB + (0). ) Are saved in the memory PB + (-1) and the memory TB + (-1), respectively, and then the rotation position PB + and the capture time TB + are saved in the memory PB + (0) and the memory TB + (0), respectively.

Then, the speed calculation 16-3 in the processing block 8 of the B + calculates ΔP and ΔT according to the equations (8) and (9) according to the regularity described later, and the equation (2). The calculation is performed to obtain the velocity VB + (n).

Next, the processing block 9 of B- in FIG. 1 processes the pulse B- signal and the rotation direction FRB- signal, and the processing block 9 of B- is the rotation phase counter 10 dedicated to this block. And has a time latch 13. Then, the rotation phase counter 10 inputs the pulse B- signal and the rotation direction FRB- signal to perform count-up or count-down, and detects and outputs the rotation position PB-. Further, the time latch 13 inputs the pulse B- signal and the real-time RT, detects and outputs the capture time TB- which is the time when the rotation position PB- is updated.

Similarly, in the processing block 9 of the B-, when the MPU of the speed detection device 3-1 checks and updates the capture time TB- for each control cycle, the memory PB- (0) and the memory After saving TB- (0) in the memory PB- (-1) and the memory TB- (-1), respectively, the rotation position PB- and the capture time TB- are stored in the memory PB- (0) and the memory, respectively. Save to TB- (0).

Then, the speed calculation 16-4 in the processing block 9 of the B- calculates ΔP and ΔT according to the equations (8) and (9) according to the regularity described later, and the equation (2) is described. Is calculated to obtain the velocity VB− (n).

Next, in FIG. 1, the speed detected by the present invention is saved in 17. At the speed 17, the speed at which the speed VA + (n), the speed VA- (n), the speed VB + (n), or the speed VB- (n) is calculated and processed according to the regularity according to the present invention is saved. To. Before explaining this regularity, the solutions realized in FIG. 1 for the four problems shown above will be described with reference to FIGS. 2 to 6.

First, FIG. 2 is a diagram illustrating a solution to the first problem shown in FIG. 13. (1), (2), and (3) of FIG. 2 are the same as (1), (2), and (3) of FIG. 13, respectively, and the description thereof will be omitted. (4) of FIG. 2 corresponds to the pulse A + signal shown in FIG. 1, and for the A-phase signal, the incremental encoder 1 has a rising edge when the incremental encoder 1 rotates in the normal direction and a falling edge when the incremental encoder 1 rotates in the reverse direction. It is pulsed. here. FIG. 2 shows the case of normal rotation. And unlike the 4F signal, the pulse A + signal is generated only from the A phase signal, so the period is T1 like the original A phase signal.

Next, (5) of FIG. 2 corresponds to the pulse B + signal shown in FIG. 1, and the B-phase signal is pulsed at the rising edge during normal rotation and at the falling edge during reverse rotation. It was done. And unlike the 4F signal, the pulse B + signal is generated only from the B phase signal, so the period is T1 like the original B phase signal.

To summarize FIG. 2, when the rotation speed of the incremental encoder 1 is detected, the 4F signal extracted from both the A-phase signal and the B-phase signal cannot avoid fluctuation, and the speed is detected from the 4F signal. Then, the accuracy deteriorates. Therefore, the solution of the first problem by the speed detection device 3-1 of the present invention is to process the A + processing block 6 of FIG. 1 from the pulse A + signal with less fluctuation, or the processing of B + of FIG. 1 from the pulse B + signal. The speed is detected by the block 8.

Next, FIG. 3 is a diagram illustrating a solution to the second problem shown in FIG. (1), (2), (3), and (4) of FIG. 3 are the same as (1), (2), (3), and (4) of FIG. 15, respectively, and the description thereof will be described. Omit. (5) of FIG. 3 is the pulse A + signal shown in FIG. 1, and represents the case where the incremental encoder 1 rotates in the normal direction with respect to the A1 signal.

Here, the frequency of the A-phase signal is high as in the example of the above equation (4) even during acceleration or deceleration as well as when the incremental encoder 1 is rotating at a constant speed. It can be said that the adjacent waveforms in the (2) A2 signal of FIG. 3 are almost equal. Then, the period of the (5) pulse A + signal of FIG. 3 generated by crossing the A2 signal with the hysteresis high voltage Vh1 is the period T1 of the (1) A1 signal of FIG. 3 which is the original waveform. Is equal to.
Further, (6) of FIG. 3 is the pulse A- signal shown in FIG. 1, and the period thereof is also equal to the period T1 of the (1) A1 signal of FIG.

To summarize FIG. 3, due to the filter 4-1 built in the input interface 4, the rotation speed cannot be correctly obtained when the speed is detected from the 2FA signal extracted from the A phase signal. Therefore, the solution of the second problem by the speed detection device 3-1 of the present invention is the processing block 6 of A + of FIG. 1 from the pulse A + signal, or the processing block 6 of A− of FIG. 1 from the pulse A− signal. The speed is detected by 7. Similarly, for the B-phase signal, the velocity is detected from the pulse B + signal by the processing block 8 of B + in FIG. 1 or from the pulse B− signal by the processing block 9 of B− of FIG.

Next, in addition to FIG. 15, the second problem according to FIG. 16 has been described, and FIG. 4 is a diagram for explaining the solution to the problem shown in FIG. (1) to (6) of FIG. 4 are the same as (1) to (6) of FIG. 16, respectively, and the description thereof will be omitted. (7) of FIG. 4 is the pulse A + signal shown in FIG. 1, and represents the case where the incremental encoder 1 rotates forward with respect to the A1 signal.

Here, the frequency of the A-phase signal is high as in the example of the above equation (4) even during acceleration or deceleration as well as when the incremental encoder 1 is rotating at a constant speed. It can be said that the adjacent waveforms of the (2) A2 signal and the (4) A4 signal in FIG. 4 are almost equal to each other. Then, the period of the (7) pulse A + signal of FIG. 4 generated by crossing the A2 signal and the A4 signal with the hysteresis high voltages Vh1 and Vh2, respectively, is the original waveform (1) of FIG. It becomes equal to the period T1 of the A1 signal.
Further, (8) of FIG. 4 is the pulse A- signal shown in FIG. 1, and the period thereof is also equal to the period T1 of the (1) A1 signal of FIG.

To summarize FIG. 4, the rotation speed is correctly detected when the speed is detected from the 2FA signal extracted from the A phase signal due to the filter 4-1 and the photocoupler 4-3 built in the input interface 4. Cannot be obtained. Therefore, the solution of the second problem by the speed detection device 3-1 of the present invention is the processing block 6 of A + of FIG. 1 from the pulse A + signal, or the processing block 6 of A− of FIG. 1 from the pulse A− signal. The speed is detected by 7. Similarly, for the B-phase signal, the velocity is detected from the pulse B + signal by the processing block 8 of B + in FIG. 1 or from the pulse B− signal by the processing block 9 of B− of FIG.

Next, the third problem caused by the long wiring distance of the signal line 2 and the fourth problem caused by the temperature change are shown in FIG. 17, and FIGS. 5 and 5 show the third and fourth problems. It is a figure explaining the solution of the problem of. (1) to (5) of FIG. 5 are the same as (1) to (5) of FIG. 17, respectively, and the description thereof will be omitted. (6) of FIG. 5 is the pulse A + signal shown in FIG. 1, and represents the case where the incremental encoder 1 rotates in the normal direction with respect to the A-phase signal.

Here, too, the frequency of the A-phase signal is high as in the example of the above equation (4) even during acceleration or deceleration as well as when the incremental encoder 1 is rotating at a constant speed. It can be said that the adjacent waveforms in the (3) A2 signal of FIG. 5 are almost equal. Then, the period of the (6) pulse A + signal of FIG. 5 generated by crossing the A2 signal with the hysteresis high voltage Vh1 is the period of the (1) A phase signal of FIG. 5 which is the original waveform. Equal to T1.
Further, FIG. 5 (7) is the pulse A- signal shown in FIG. 1, and the period thereof is also equal to the period T1 of the (1) A phase signal shown in FIG.

To summarize FIG. 5, when speed detection is performed from the 2FA signal extracted from the A-phase signal, a correct rotation speed can be obtained due to a long wiring distance of the signal line 2 or a temperature change. It disappears. Therefore, in solving the third and fourth problems by the speed detection device 3-1 of the present invention, the processing block 6 of A + of FIG. 1 from the pulse A + signal or the A- of FIG. 1 from the pulse A− signal is also solved. The speed is detected by the processing block 7 of. Similarly, for the B-phase signal, the velocity is detected from the pulse B + signal by the processing block 8 of B + in FIG. 1 or from the pulse B− signal by the processing block 9 of B− of FIG.

Before explaining the next embodiment, FIG. 6 is a summary of the operations of FIG. 1 and will be described. The (1) A5 signal and (2) B5 signal in FIG. 6 represent the output of the input interface 4, and (3) in FIG. 6 represents the rotation phase PA + output by the rotation phase counter 10. Then, the incremental encoder 1 reverses until the time Ta, stops from the time Ta to Tb, and rotates forward after the time Tb.

Then, the time between Ta and Tb is enlarged and shown in (4) to (14) of FIG. 6, and (4) and (5) of FIG. 6 are the (1) A5 signal and (2) B5, respectively. It represents a signal, and the phase relationship between reverse rotation and forward rotation is as shown in the figure. Further, (6), (7), and (8) in FIG. 6 represent a pulse A + signal, a rotation direction FRA + signal, and a rotation phase PA +, respectively, and the (8) rotation phase PA + counts down one by one as shown. Or count up.

Next, (9) and (10) of FIG. 6 represent a pulse A- signal and a rotation direction FRA- signal, and FIGS. 6 (11) and (12) represent a pulse B + signal and a rotation direction FRB + signal. , (13) and (14) of FIG. 6 represent a pulse B- signal and a rotation direction FRB- signal.

In FIG. 1, the speed 17 is processed by calculating the speed VA + (n), the speed VA- (n), the speed VB + (n), or the speed VB- (n) according to the regularity according to the present invention. The speed is saved. This regularity will be described with reference to FIGS. 1 and 7 and 8.
First, in FIG. 7, (1) and (2) represent the temporal transition of the A-phase signal and the pulse A + signal, respectively. Then, in the (1) A phase signal of FIG. 7, T1 indicates the theoretical period of the (1) A phase signal when the incremental encoder 1 is rotating at a constant speed. Here, although the period of the (1) A-phase signal is accurately generated by optical technology or precision technology as described in (1) of FIG. 12, for example, a maximum of 15 is obtained with respect to the theoretical period T1. There is a period error of about%. Then, when trying to obtain the velocity from the (2) pulse A + signal extracted from the (1) A phase signal due to the periodic error, it is inevitable that a detection error will occur.
As shown in (2) of FIG. 4, the (2) pulse A + signal is uniformly delayed by T3-1 from the (1) A phase signal of FIG. 7.

Here, the (1) A-phase signal of FIG. 7 will be further described. In the figure, T10, T11, and T12 are simulated representations of the actual period, and the period T10 is shorter than the theoretical period T1. .. However, as shown in the example in the above equation (3), the number of pulses per rotation of the incremental encoder 1 is a fixed value, and when the period T10 is shorter than the theoretical period T1, another long period also exists. .. In FIG. 7, the cycles T11 and T12 represent this, and the cycle T11 is longer than the theoretical cycle T1 and the cycle T12 is shorter than the theoretical cycle T1. As shown in this example, when there is a period shorter than the theoretical period T1, a waveform having a long period is generated in an adjacent period.

Next, an aspect when speed detection is performed in the state of FIG. 7 will be described with reference to FIG. 8 (1), (2), (3), and (4) of FIG. 8 show an A-phase signal, a pulse A + signal, a processing timing of the MPU built in the speed detection device 3-1 and a speed VA + (n). ) Represents the temporal transition.
Introduction (1) A-phase signal and (2) Pulse A + signal are the same signals as (1) and (2) in FIG. 7 in a reduced time, and the (2) pulse is shown for ease of explanation. The A + signal is (1) no delay from the A phase signal. The incremental encoder 1 rotates at a constant speed, and the theoretical period of the A-phase signal is T1.

Subsequently, the process of (3) MPU in FIG. 8 represents the speed detection timing by the MPU built in the speed detection device 3-1 at the times t1, t2, t3, t4, and t5 in the figure. Detect speed. Further, ΔP2, ΔP3, ΔP4, and ΔP5 represent the rotation position deviations at the respective speed detection timings, and ΔT2, ΔT3, ΔT4, and ΔT5 represent the capture time deviations at the respective speed detection timings.
To further explain the speed detection timing t3, the rotation position deviation and the capture time deviation at the speed detection timing t3 are ΔP3 and ΔT3, respectively. Then, the MPU calculates the rotation position deviation ΔP3 by the above equation (8) to obtain 3, and ΔT3 is also obtained by the above equation (9). Then, the speed VA + (3) at the speed detection timing t3 is the speed VA + (3) = 3 / ΔT3 according to the above equation (2).

Next, (4) in FIG. 8 shows the speed VA + (n) calculated by the MPU, and the speeds at the speed detection timings t1, t2, t3, t4, and t5 are VA + (1), VA + (2), respectively. VA + (3), VA + (4), and VA + (5). Further, V1 in the figure is a fixed value at the theoretical speed of the rotary encoder 1. Then, at the speed detection timing t3, the capture time deviation ΔT3 should be (theoretical cycle T1 × 3), but assuming that a waveform shorter than the theoretical cycle T1 is included, VA + (3) is higher than the theoretical speed V1. It will be faster.
Then, at the next velocity detection timing t4, where the capture time deviation ΔT4 should be (theoretical period T1 × 3), there is a high possibility that a waveform longer than the theoretical period T1 is included, whereby VA + (4) becomes. It is slower than the theoretical speed V1.

Summarizing (4) of FIG. 8, the velocity VA + (n) detected by the MPU is such that a high velocity and a slow velocity appear alternately with respect to the theoretical velocity V1. Then, it is important that the MPU detects the speed without omission and performs feedback control or the like at all speed detection timings. Then, when averaging the speed VA + (n) or, if the load has inertia, the speed of the motor or the like to which the incremental encoder 1 is attached is controlled, the speed is controlled to be the theoretical speed V1 with extremely high accuracy. It can be done.

Here, of the four speeds, the speed VA + (n) related to the A-phase signal has been used for explanation, but instead of this, the speed VA- (n) related to the A-phase signal and the B-phase are described. The speed VB + (n) related to the signal or the speed VB- (n) related to the B-phase signal may be used. However, it is impossible to change the type of speed for each speed detection timing, and it is necessary to use the same speed continuously to obtain the speed 17.
Further, the speed to be used is not limited to one, and a plurality of speeds may be used. For example, two speeds, for example, speed VA + (n) and speed VB + (n) may be detected at each speed detection timing, and the average of these speeds may be set to the speed 17. In addition, all four speeds, speed VA + (n), speed VA- (n), speed VB + (n), and speed VB- (n) are detected at each speed detection timing in order to follow the change in speed faster. , The average of these may be the speed 17.

Here, the above-mentioned contents described in FIG. 8 will be described again in FIG. The MPU built in the detection device 3-1 compares the speed 17 of the incremental encoder 1 with a predetermined speed establishment level for each speed detection timing. Then, when the speed 17 is less than the speed establishment level, the MPU is set to the latest time set among the memories TA + (0), TA- (0), TB + (0), and TB- (0). Then, one of the velocity VA + (n), the velocity VA− (n), the velocity VB + (n), or the velocity VB− (n) is calculated and saved at the velocity 17.

(数１１)

そして、該ΔＰとΔＴを前記速度演算１６-３にて前記（２）式の演算を行って速度ＶＢ＋（ｎ）を求め、前記速度１７にセーブするものである。 Explaining this by example, if the latest time of the memories TA + (0), TA- (0), TB + (0), and TB- (0) is TB + (0), the MPU is the B +. Regarding the memories PB + (0), TB + (0), PB + (-1), and TB + (-1) in the processing block 8 of the above, ΔP and ΔT are as follows according to the above equations (8) and (9). Ask for.
(Number 10)

(Equation 11)

Then, the ΔP and ΔT are calculated by the above-mentioned equation (2) in the above-mentioned speed calculation 16-3 to obtain the speed VB + (n), and the speed is saved at the speed 17.

Further, the MPU compares the speed 17 of the incremental encoder 1 with the speed establishment level at each speed detection timing, and when the speed 17 is equal to or higher than the speed establishment level, the MPU changes to the speed 17 of the previous time. The calculation of the above equation (2) is performed in the same set as the set saved at the detection timing, and the set is saved at the speed 17.
Explaining this by example, when the speed 17 is equal to or higher than the speed establishment level, and when the speed VB + (n-1) is saved at the speed 17 at the previous speed detection timing, the MPU is the current speed. Also at the detection timing, the speed VB + (n) is obtained and saved at the speed 17.

Here, when the speed 17 is equal to or higher than the speed establishment level, in the above, a new speed is obtained in one set and saved in the speed 17, but a plurality of sets of speeds are obtained and the average value thereof is saved in the speed 17. You may. As a result, the speed detection device 3-1 detects the speed 17 extremely accurately when the incremental encoder 1 is rotating at a constant speed, and has excellent followability when accelerating or decelerating. The speed 17 is detected.

When the speed detection device according to the present invention detects the speed from the incremental encoder, the input interface of the speed detection device has a long and short signal line regardless of the circuit configuration, regardless of whether the ambient temperature is high or low. Regardless, stable and accurate speed can be detected.
As a result, it can be used for high-quality films required for liquid crystal displays and electronic components, color printing by rotary presses, and the like.

1 Incremental encoder 2 Signal line 3 Speed detector (conventional speed detector)
3-1 Speed detection device (speed detection device according to the present invention)
4 Input interface 5 Signal converter (conventional signal converter)
5-1 Signal converter (Signal converter according to the present invention)
6 A + processing block 7 A- processing block 8 B + processing block 9 B- processing block 10 Rotational position counter 11 Oscillator 12 Timer 13 Time latch 15 Speed detector (conventional speed detector)
15-1 Speed detector (speed detector according to the present invention)
16-1 Speed calculation (for A + processing block)
16-2 Speed calculation (for A- processing block)
16-3 Speed calculation (for B + processing block)
16-4 Speed calculation (for B- processing block)
17 speed

Claims (1)

It consists of an incremental encoder and a speed detector.
The incremental encoder outputs a continuous rectangular wave signal of A-phase signal and B-phase signal having a phase difference of 90 degrees according to rotation.
The speed detector has an input interface, a signal converter, a rotation position counter and a time latch, and a speed detector.
The input interface inputs the A-phase signal and the B-phase signal output by the incremental encoder and outputs the A5 signal and the B5 signal that have been filtered, insulated, or waveform-shaped to the signal converter.
The rotation position counter and the time latch output the rotation position and the time (capture time) at which the rotation position was obtained by the signal output from the signal converter, respectively.
The speed detection unit is a speed detection device that detects the speed based on the rotation position and the capture time.

The signal converter built in the speed detection device generates a pulse A + signal for the input A5 signal at the rising edge when the rotation direction of the incremental encoder is forward rotation and at the falling edge when the rotation direction is reverse rotation. At the same time, a rotation direction FRA + signal indicating the rotation direction when the pulse A + signal is generated is generated.
Similarly, the signal converter generates a pulse A- signal at the falling edge when the input A5 signal rotates in the forward direction of the incremental encoder, and at the rising edge when the rotation direction of the incremental encoder is reversed, and the pulse. Generate a rotation direction FRA-signal indicating the rotation direction when the A-signal is generated.
Similarly, the signal converter generates a pulse B + signal at the rising edge when the input B5 signal rotates in the forward direction of the incremental encoder, and at the falling edge when the rotation direction of the incremental encoder is reversed, and the pulse B + signal. Generates a rotation direction FRB + signal that indicates the rotation direction when the signal is generated.
Similarly, the signal converter generates a pulse B- signal at the falling edge when the input B5 signal rotates in the forward direction of the incremental encoder, and at the rising edge when the rotation direction of the incremental encoder is reversed, and also generates the pulse B- signal. Generates a rotation direction FRB-signal indicating the rotation direction when the B- signal is generated.

The speed detector has four sets of rotation position counters and a time latch built-in.
The four sets of rotation position counters have an up / down counter function, respectively, the pulse A + signal and the rotation direction FRA + signal, the pulse A- signal and the rotation direction FRA- signal, the pulse B + signal and the rotation direction FRB +, respectively. The signal, the pulse B- signal, and the rotation direction FRB- signal are input, and the rotation position PA +, the rotation position PA-, the rotation position PB +, and the rotation position PB- are detected and output.
The four sets of time latches input the pulse A + signal, the pulse A- signal, the pulse B + signal, and the pulse B- signal, respectively, to input the rotation position PA +, the rotation position PA-, and the rotation position PB +, respectively. And the time when the rotation position PB− is updated is captured (captured), and the capture time TA +, the capture time TA−, the capture time TB +, and the capture time TB− are output.

The speed detection unit built in the speed detection device further incorporates four sets of memories.
Regarding the first set of memories PA + (0), TA + (0), PA + (-1), and TA + (-1), the MPU built in the speed detection device checks the capture time TA + at each speed detection timing. When the memory PA + (0) and the memory TA + (0) are saved in the memory PA + (-1) and the memory TA + (-1), respectively, the rotation position PA + and the capture time TA + are updated. Are saved in the memory PA + (0) and the memory TA + (0), respectively.
Regarding the second set of memories PA- (0), TA- (0), PA- (-1), and TA- (-1), the MPU checks and updates the capture time TA- at each speed detection timing. When the above is performed, the memory PA- (0) and the memory TA- (0) are saved in the memory PA- (-1) and the memory TA- (-1), respectively, and then the rotation position PA- and the above. The capture time TA- is saved in the memory PA- (0) and the memory TA- (0), respectively.
Regarding the third set of memories PB + (0), TB + (0), PB + (-1), and TB + (-1), the MPU checks and updates the capture time TB + at each speed detection timing. After saving the memory PB + (0) and the memory TB + (0) in the memory PB + (-1) and the memory TB + (-1), respectively, the rotation position PB + and the capture time TB + are set to the memory PB + (0), respectively. ) And memory TB + (0).
Regarding the fourth set of memories PB- (0), TB- (0), PB- (-1), and TB- (-1), the MPU checks and updates the capture time TB- at each speed detection timing. If so, the memory PB- (0) and the memory TB- (0) are saved in the memory PB- (-1) and the memory TB- (-1), respectively, and then the rotation position PB- and the above. The capture time TB- is saved in the memory PB- (0) and the memory TB- (0), respectively.

Next, the MPU built in the speed detection device compares the rotation speed of the incremental encoder with a predetermined speed establishment level for each speed detection timing, and when the rotation speed is less than the speed establishment level, the memory TA + Of (0), TA- (0), TB + (0), and TB- (0), the speed VA + (n), VA- (n), VB + (n), or VB in the most recent time set. Calculate one of-(n) and output the speed.
When the rotation speed of the incremental encoder is equal to or higher than the speed establishment level, the speeds VA + (n), VA- (n), and the same set as the set for which the speed was calculated at the previous speed detection timing are continuously used. A speed detection device characterized in that a speed of one of VB + (n) or VB- (n) is calculated, or a plurality of speeds are calculated and averaged, and the speed is output.

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