JP6744610B2 - Semiconductor packages, modules and electrical equipment - Google Patents

Description

The present invention relates to a semiconductor package, a module, and an electric device, and more particularly, to a three-terminal semiconductor device using a gallium nitride (GaN) semiconductor, for example, a semiconductor package in which a GaN field effect transistor (FET) is packaged, and this semiconductor package. The present invention relates to a module including the module and an electric device including the module.

Silicon (Si)-MOS transistors, insulated gate bipolar transistors (IGBTs) and silicon carbide (SiC)-MOS transistors are the mainstream of conventional high voltage power electronic devices. These electronic devices have a vertical structure in which a drain electrode is provided on the lower surface and a source electrode and a gate electrode are provided on the upper surface.

In such a vertical element, since the electrodes are formed on the upper surface and the lower surface, the electrodes are taken out or the circuit wiring is a three-dimensional wiring. Specifically, for example, in a power Si-MOS transistor, as shown in FIGS. 61A and 61B, a power Si-MOS transistor chip 1002 is bonded onto a drain electrode pad 1001 with solder, silver (Ag) paste, or the like, The source electrode pad 1003 and the gate electrode pad 1004 are arranged on the same surface as the drain electrode pad 1001, and the source electrode (not shown) on the upper surface of the chip 1002 and the source electrode pad 1003 are bonded by wires 1005 and 1006. A gate electrode (not shown) on the upper surface of the chip 1002 and the gate electrode pad 1004 are bonded by a wire 1007, and the whole of these is exposed so that the lower surfaces of the drain electrode pad 1001, the source electrode pad 1003 and the gate electrode pad 1004 are exposed. Packaging is performed by sealing with resin 1008. The semiconductor package called SON (Small Outline Non-leaded package) or QFN (Quad Flat Non-leaded package) manufactured in this manner is generally mounted on a printed wiring board by soldering or the like.

In addition, as an example of a method of packaging a plurality of chips of the above vertical device in one package, for example, as shown in FIG. 62, a chip 1012 is bonded to a drain electrode pad 1011 and a chip 1012 is formed on the drain electrode pad 1013. And a chip 1014 bonded to the chip are arranged, source electrode pads 1015 and 1016 are arranged adjacent to them, and the source electrode pad 1015 and a source electrode (not shown) on the upper surface of the chip 1012 are bonded by a wire 1017. Then, the gate electrode on the upper surface of the chip 1012 and the gate electrode (not shown) on the upper surface of the chip 1014 are bonded by the wire 1018, and the source electrode pad 1016 and the source electrode (not shown) on the upper surface of the chip 1014 are connected by the wire. Bonding is performed by 1019.

Further, in the mounting of the vertical element by the bare chip, generally, a DBC (direct bonding copper) substrate in which a silicon nitride (SiN) layer and a Cu layer are sequentially stacked on a copper (Cu) base substrate is used. In this case, because of the structure of the vertical element, wire bonding, three-dimensional wiring by bars, terminals, etc. are required. For example, as shown in FIG. 63, by patterning the Cu layer of the DBC substrate 1100 in which the SiN layer 1100b and the Cu layer are sequentially laminated on the Cu base substrate 1100a, the drain electrode pads 1101, 1102 and the source electrode pads 1103, 1104 are formed. And connecting chips 1105 and 1106 on the drain electrode pads 1101 and 1102, respectively, and forming rod-shaped terminals 1107 and 1108 on the source electrode pads 1103 and 1104, respectively, and connecting them to the terminals 1107 on the source electrode pad 1103. A source electrode (not shown) on the upper surface of the chip 1105 is bonded by a wire 1109, and a gate electrode (not shown) on the upper surface of the chip 1105 and a gate electrode (not shown) on the upper surface of the chip 1106 are connected by a wire 1110. Bonding is performed, and the terminal 1108 on the source electrode pad 1104 and the source electrode (not shown) on the upper surface of the chip 1106 are bonded by the wire 1111.

On the other hand, the present inventors have proposed a power GaN-based field effect transistor (FET) having a lateral structure using polarization super junction (PSJ) (see Patent Documents 1 and 2). In this power polarization super-junction GaN-based FET, unlike the vertical element described above, a gate electrode composed of a source electrode, a drain electrode and a p-electrode is provided on the same surface of a semiconductor layer forming the FET.

Patent No. 5669119 Patent No. 5828435

However, the above-mentioned conventional packaging and integration technology for vertical devices has reached a technical saturation point in terms of cost reduction, high frequency, volume saving, and low thermal resistance. ..

Therefore, the problem to be solved by the present invention is to form a power polarization superjunction GaN-based FET, which is an electronic device having a horizontal structure, rather than an electronic device having a vertical structure, and more generally, is formed on an insulating substrate. Using a three-terminal semiconductor element in which all electrodes are formed on the same surface of the semiconductor layer, this semiconductor element can be easily mounted face-up on the substrate, resulting in a significant cost reduction compared to the conventional method. It is an object of the present invention to provide a semiconductor package capable of achieving high frequency, volume saving, low thermal resistance, etc., a high performance module using this semiconductor package, and a high performance electric device using this module.

The present inventors have conducted extensive studies to overcome the packaging and integration difficulties faced by the conventional vertical device, and as a result, have developed a lateral structure represented by a power polarization superjunction GaN-based FET. Using a semiconductor element that has, that is, a three-terminal semiconductor element in which all electrodes are formed on the same surface of a semiconductor layer formed on an insulating substrate. The three-terminal semiconductor element has excellent heat dissipation and is easy to mount. The inventors have come to the conclusion that it is best to mount on the substrate face up, and have devised the present invention.

That is, in order to solve the above problems, the present invention is
A semiconductor chip in which a semiconductor layer forming a three-terminal semiconductor element is provided on a first main surface of an insulating substrate, and a first electrode, a second electrode, and a third electrode are arranged in a triangle on the semiconductor layer,
A first electrode pad, a second electrode pad, and a third electrode pad that are electrically connected to the first electrode, the second electrode, and the third electrode, respectively, and are drawn outside or above the semiconductor layer;
An electrically insulating resin that seals the side surfaces of the semiconductor layer, the first electrode, the second electrode, the third electrode, and the insulating substrate;
It is a semiconductor package having.

In a typical example, the first electrode pad, the second electrode pad, and the third electrode pad respectively extend from the first electrode, the second electrode, and the third electrode on the resin in parallel with the semiconductor layer and the insulating substrate. Then, it is bent vertically and extends along the side surface of the resin in parallel with the side surface of the semiconductor layer and the insulating substrate, and terminates at the same height as the second main surface of the insulating substrate. Alternatively, in another example, the first electrode pad, the second electrode pad, and the third electrode pad are parallel to the semiconductor layer and the insulating substrate through the resin from the first electrode, the second electrode, and the third electrode, respectively. Protruding in the direction. The semiconductor layer typically has a rectangular planar shape, and the first electrode pad, the second electrode pad, and the third electrode pad are typically four different corners of the semiconductor layer. It extends so as to overlap with a predetermined region including one or two different parts. Typically, the predetermined region has a rectangular planar shape including one or two corners at one vertex. Furthermore, in another example, the first electrode pad, the second electrode pad, and the third electrode pad are respectively drawn from the first electrode, the second electrode, and the third electrode vertically above the semiconductor layer, and then, It extends above the layer parallel to the semiconductor layer. In this case, typically, the semiconductor layer has a rectangular planar shape, and the first electrode pad, the second electrode pad, and the third electrode pad are different from each other in one of the four sides of the semiconductor layer. It extends so as to straddle.

The sealing resin may be applied on the first electrode pad, the second electrode pad, and the third electrode pad from the region between the first electrode pad, the second electrode pad, and the third electrode pad, if necessary. Make it extend. By doing so, the thickness of the resin can be sufficiently secured, and the strength of the semiconductor package can be improved. Alternatively, the resin may extend from the side surface of the insulating substrate onto the second main surface of the insulating substrate while leaving the central region of the second main surface. By doing so, the thickness of the resin can be sufficiently ensured similarly, and the strength of the semiconductor package can be improved. In this case, if necessary, heat conduction to the central region of the second main surface of the insulating substrate (also referred to as an opening formed in the resin extending on the second main surface of the insulating substrate) Layers are provided. This heat conducting layer is preferably formed to have a thickness similar to that of the resin extending on the second main surface of the insulating substrate. With this configuration, when the semiconductor package is mounted on the substrate, the heat conducting layer comes into contact with the substrate, so that the heat conduction to the substrate becomes good, so that the heat dissipation can be improved. As the heat conducting layer, one formed by using a conductive paste containing fine particles of a metal such as Cu is typically used, but the heat conducting layer is not limited to this.

Typically, the semiconductor layer is a GaN-based semiconductor layer, the three-terminal semiconductor element is a GaN-based field effect transistor, and in particular, a polarization superjunction GaN-based field effect transistor, but is not limited thereto. In this case, the first electrode, the second electrode and the third electrode are the source electrode, the drain electrode and the gate electrode.

The insulating substrate is preferably, but is not limited to, a sapphire substrate, typically a C-plane sapphire substrate. The insulating substrate is preferably thin so that heat can be sufficiently radiated through the insulating substrate. For example, when the insulating substrate is a sapphire substrate, the thickness thereof is preferably 150 μm or less, generally 50 μm or more, and more preferably 50 μm or more and 120 μm or less.

但し、αは
Log（α）＝ｐ₀ ＋ｐ₁ log （ａ）＋ｐ₂ ｛log （ａ）｝²
（但し、ｐ₀ ＝７．３２９５、ｐ₁ ＝−３．５５９９、ｐ₂ ＝０．６９１２）
で表され、
かつ、βは
β＝ｐ'₀＋ｐ'₁ log（ａ）＋ｐ'₂｛log （ａ）｝²
（但し、ｐ'₀＝−３．６５０９、ｐ'₁＝１．９４４５、ｐ'₂＝−０．３７９３）
で表される。
を満足するものである。 The polarized superjunction GaN-based field effect transistor is, for example, as described in Patent Document 1,
First undoped GaN layer, have a first Al _x Ga _1-x N layer and said Al _x Ga _1-x N second polarization super junction region consisting of undoped GaN layer on the layer on the undoped GaN layer Then
When the thickness of the second undoped GaN layer is a [nm] (where a is 10 nm or more and 1000 nm or less), the Al composition x and the thickness t [nm] of the Al _x Ga _1-x N layer are as follows.

However, α is
Log(α)=p ₀ +p ₁ log (a)+p ₂ {log (a)} ²
(However, p ₀ =7.3295, p ₁ =−3.5599, p ₂ =0.6912)
Is represented by
Also, β is β=p′ ₀ +p′ ₁ log(a)+p′ ₂ {log(a)} ²
_{(However, p '0 = -3.6509, p} ' 1 = 1.9445, p '2 = -0.3793)
It is represented by.
Is satisfied.

In this polarized superjunction GaN-based field effect transistor, the second undoped GaN layer is formed in the vicinity of the hetero interface between the Al _x Ga _{1 -x} N layer and the second undoped GaN layer when not operating. A two-dimensional hole gas is formed and a two-dimensional electron gas is formed in the first undoped GaN layer in the vicinity of the hetero interface between the first undoped GaN layer and the Al _x Ga _{1 -x} N layer. To be done. This semiconductor device preferably has a p-electrode contact region provided separately from the polarization superjunction region. These polarized ultra junction region and a p-electrode contact region typically has a first undoped GaN layer, Al _x Ga _1-x N layer and the second undoped GaN layer as a common layer. Further, the p-electrode contact region has a higher concentration than the p-type GaN layer, which is provided on the second undoped GaN layer in contact with the Mg-doped p-type GaN layer and the p-type GaN layer. It further has a p-type GaN contact layer doped with Mg and a p-electrode (gate electrode) in ohmic contact with the p-type GaN contact layer. The p-type GaN contact layer is not particularly limited as to how it is provided as long as it is in contact with the p-type GaN layer. For example, the p-type GaN contact layer may be stacked on the p-type GaN layer, or may be embedded in the p-type GaN layer or the like. Regarding the latter, for example, the Al _x Ga _1-x N layer, the second undoped GaN layer and the p-type GaN layer are provided with a groove at a depth reaching at least the Al _x Ga _1-x N layer, and inside the groove. A p-type GaN contact layer is buried in the p-type GaN contact layer and the two-dimensional hole gas is joined to the p-type GaN contact layer.

Alternatively, a polarized superjunction GaN-based field effect transistor is disclosed, for example, in Patent Document 2
A polarized superjunction region and a p-electrode contact region,
The polarized superjunction region is
A first undoped GaN layer,
An undoped Al _x Ga _1-x N layer (0.17≦x≦0.35) having a thickness of 25 nm or more and 47 nm or less on the first undoped GaN layer,
A second undoped GaN layer on the undoped Al _x Ga _1-x N layer;
A p-type GaN layer doped with Mg on the second undoped GaN layer,
The thickness of the second undoped GaN layer is represented by u [nm], the thickness of the p-type GaN layer is represented by v [nm], and the Mg concentration of the p-type GaN layer is represented by w [cm ⁻³ ]. Let tR be tR=u+v(1+w×10 ^-18 ).
When defined as
tR≧0.864/(x−0.134)+46.0 [nm]
Holds,
The p-electrode contact region is
A p-type GaN contact layer that is provided in contact with the p-type GaN layer and is doped with Mg at a higher concentration than the p-type GaN layer;
It has a p-electrode in ohmic contact with the p-type GaN contact layer.

Also in this polarization superjunction GaN-based field effect transistor, the second undoped GaN layer in the vicinity of the hetero interface between the undoped Al _x Ga _1-x N layer and the second undoped GaN layer when not operating A two-dimensional electron gas is formed in the first undoped GaN layer in the vicinity of the hetero interface between the first undoped GaN layer and the undoped Al _x Ga _{1 -x} N layer. Is formed. Typically, the polarization superjunction region and the p-electrode contact region are provided separately from each other.

The p-type GaN contact layer is not particularly limited as to how it is provided as long as it is in contact with the p-type GaN layer. For example, the p-type GaN contact layer may be formed in a mesa type on the p-type GaN layer, or may be embedded in the p-type GaN layer or the like. Regarding the latter, for example, the undoped Al _x Ga _1-x N layer, the second undoped GaN layer and the p-type GaN layer are provided with a groove at a depth reaching at least the undoped Al _x Ga _1-x N layer. A p-type GaN contact layer is embedded in the inside of the, and the p-type GaN contact layer and the two-dimensional hole gas are joined.

Further, the present invention is
A mounting board having predetermined wirings provided on one main surface so as not to intersect with each other,
And a semiconductor package mounted on the main surface of the mounting board so as to form a predetermined circuit by the predetermined wiring,
The semiconductor package is
A semiconductor chip in which a semiconductor layer forming a three-terminal semiconductor element is provided on a first main surface of an insulating substrate, and a first electrode, a second electrode, and a third electrode are arranged in a triangle on the semiconductor layer,
A first electrode pad, a second electrode pad, and a third electrode pad that are electrically connected to the first electrode, the second electrode, and the third electrode, respectively, and are drawn out of the semiconductor layer;
An electrically insulating resin that seals the side surfaces of the semiconductor layer, the first electrode, the second electrode, the third electrode, and the insulating substrate,
Have
In the semiconductor package, the insulating substrate side is directed to the mounting substrate, and the first electrode pad, the second electrode pad, and the third electrode pad are connected to a predetermined portion of the predetermined wiring and the predetermined wiring is formed. The module is mounted on the main surface of the mounting board so that the circuit of FIG.

Here, as the mounting substrate, a substrate excellent in heat dissipation is used, and typically, for example, a DBC substrate in which a SiN layer and a Cu layer are sequentially laminated on a Cu base substrate is used, but the present invention is not limited to this. It is not something that will be done. In this case, the predetermined wiring can be formed by patterning the Cu layer. If necessary, one or more passive elements or active elements (including parts) that form the above-described predetermined circuit are mounted on the mounting board in addition to the semiconductor package.

Further, the present invention is
Has one or more modules,
At least one of the modules is a mounting board having predetermined wirings provided on one main surface so as not to intersect with each other,
And a semiconductor package mounted on the main surface of the mounting board so as to form a predetermined circuit by the predetermined wiring,
The semiconductor package is
A semiconductor chip in which a semiconductor layer forming a three-terminal semiconductor element is provided on a first main surface of an insulating substrate, and a first electrode, a second electrode, and a third electrode are arranged in a triangle on the semiconductor layer,
A first electrode pad, a second electrode pad, and a third electrode pad that are electrically connected to the first electrode, the second electrode, and the third electrode, respectively, and are drawn out of the semiconductor layer;
An electrically insulating resin that seals the side surfaces of the semiconductor layer, the first electrode, the second electrode, the third electrode, and the insulating substrate,
Have
In the semiconductor package, the insulating substrate side is directed to the mounting substrate, and the first electrode pad, the second electrode pad, and the third electrode pad are connected to a predetermined portion of the predetermined wiring and the predetermined wiring is formed. The electrical device is a module mounted on the main surface of the mounting board so that the circuit of FIG.

Here, the electric device includes all devices that use electricity, and is not limited in use, function, size, etc., but is, for example, an electronic device, a moving body, a power unit, a construction machine, a machine tool, or the like. Electronic equipment includes robots, computers, game machines, in-vehicle equipment, home appliances (air conditioners, etc.), industrial products, mobile phones, mobile devices, IT equipment (servers, etc.), power conditioners used in solar power generation systems, power transmission. System etc. The moving body is a railway vehicle, an automobile (electric vehicle, etc.), a two-wheeled vehicle, an aircraft, a rocket, a spacecraft, or the like.

Further, the present invention is
A metal substrate,
One or more semiconductor packages mounted on one main surface of the metal substrate;
A wiring provided so as to form a predetermined circuit on the one or more semiconductor packages,
The semiconductor package is
A semiconductor chip in which a semiconductor layer forming a three-terminal semiconductor element is provided on a first main surface of an insulating substrate, and a first electrode, a second electrode, and a third electrode are arranged in a triangle on the semiconductor layer,
A first electrode pad, a second electrode pad, and a third electrode pad that are electrically connected to the first electrode, the second electrode, and the third electrode, respectively, and are drawn outside or above the semiconductor layer;
An electrically insulating resin that seals the side surfaces of the semiconductor layer, the first electrode, the second electrode, the third electrode, and the insulating substrate,
Have
The semiconductor package is mounted on the main surface of the metal substrate with the insulating substrate in contact with the metal substrate, and the first electrode pad, the second electrode pad, and the third electrode pad have the predetermined wiring. Is a module in which the predetermined circuit is configured by being connected to a predetermined portion of.

Here, as the metal substrate, a substrate having excellent heat dissipation, such as a Cu substrate or an aluminum (Al) substrate, is preferably used. Further, the method of forming the wiring provided so as to form a predetermined circuit on the semiconductor package is not particularly limited, but for example, a lead frame of one layer or two layers or more is used. In this case, typically, the lead frame is provided so as to be electrically connected to the first electrode pad, the second electrode pad and the third electrode of the semiconductor package mounted on the metal substrate. Alternatively, instead of the lead frame, a two-layer flexible polyimide substrate or a double-sided printed wiring board (PCB) using an epoxy resin substrate may be used. In this case, the wiring can be formed by patterning the Cu layers formed on both surfaces of the two-layer flexible polyimide substrate or the epoxy resin substrate.

Further, the present invention is
Has one or more modules,
At least one of the modules is
A metal substrate,
One or more semiconductor packages mounted on one main surface of the metal substrate;
A wiring provided so as to form a predetermined circuit on the one or more semiconductor packages,
The semiconductor package is
A semiconductor chip in which a semiconductor layer forming a three-terminal semiconductor element is provided on a first main surface of an insulating substrate, and a first electrode, a second electrode, and a third electrode are arranged in a triangle on the semiconductor layer,
A first electrode pad, a second electrode pad, and a third electrode pad that are electrically connected to the first electrode, the second electrode, and the third electrode, respectively, and are drawn outside or above the semiconductor layer;
An electrically insulating resin that seals the side surfaces of the semiconductor layer, the first electrode, the second electrode, the third electrode, and the insulating substrate,
Have
The semiconductor package is mounted on the main surface of the metal substrate with the insulating substrate in contact with the metal substrate, and the first electrode pad, the second electrode pad, and the third electrode pad have the predetermined wiring. Is an electric device that is a module that is connected to a predetermined part of the above-mentioned circuit to configure the predetermined circuit.

In each of the inventions of the module and the electric device described above, what has been described in connection with the invention of the semiconductor package is established unless it goes against the property.

According to the present invention, the semiconductor layer forming the three-terminal semiconductor element is provided on the first main surface of the insulating substrate, and the first electrode, the second electrode, and the third electrode are arranged in a triangle on the semiconductor layer. The semiconductor chip has a first electrode pad, a second electrode pad, and a third electrode pad that are electrically connected to the first electrode, the second electrode, and the third electrode, respectively, and are drawn outside or above the semiconductor layer. A semiconductor package is used, and the first electrode pad, the second electrode pad, and the third electrode pad that are drawn out of or above the semiconductor layer are mounted with the insulating substrate side of the semiconductor chip of this semiconductor package facing the mounting substrate or the metal substrate. By connecting to the wiring formed on the board or the wiring formed on the semiconductor package, the 3-terminal semiconductor element can be easily mounted face-up on the mounting board or the metal board. It is possible to achieve low cost, high frequency, volume saving, low thermal resistance, and the like. Moreover, the first electrode, the second electrode, and the third electrode are arranged in a triangle, and therefore the first electrode pad, the second electrode pad, and the third electrode pad can also be arranged in a triangle. Since the wirings can be formed so as not to cross each other, it is possible to easily realize a high-performance module in which a semiconductor package is mounted. By using this module, high-performance electric equipment can be realized at low cost.

1 is a plan view showing a semiconductor package according to a first embodiment of the present invention. FIG. 3 is a bottom view showing the semiconductor package according to the first embodiment of the present invention. It is sectional drawing along the XX line of FIG. FIG. 2 is a sectional view taken along the line YY of FIG. 1. FIG. 7 is a cross-sectional view for explaining the method for manufacturing the semiconductor package according to the first embodiment of the present invention. FIG. 7 is a plan view for explaining the method for manufacturing the semiconductor package according to the first embodiment of the present invention. FIG. 7 is a plan view for explaining the method for manufacturing the semiconductor package according to the first embodiment of the present invention. FIG. 7 is a plan view for explaining the method for manufacturing the semiconductor package according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view showing an example of a semiconductor chip that constitutes a polarized superjunction GaN-based FET sealed in the semiconductor package according to the first embodiment of the present invention. FIG. 6 is a cross-sectional view showing another example of a semiconductor chip that constitutes a polarized superjunction GaN-based FET sealed in the semiconductor package according to the first embodiment of the present invention. 5A and 5B are a plan view and a cross-sectional view for explaining the semiconductor package mounting method according to the first embodiment of the present invention. 1 is a circuit diagram and a plan view showing a module 1 using a semiconductor package according to a first embodiment of the present invention. 1 is a circuit diagram and a plan view showing a module 2 using a semiconductor package according to a first embodiment of the present invention. 1 is a circuit diagram and a plan view showing a module 3 using a semiconductor package according to a first embodiment of the present invention. 1 is a circuit diagram and a plan view showing a module 4 using a semiconductor package according to a first embodiment of the present invention. It is a top view which shows the semiconductor package by the 2nd Embodiment of this invention. It is a bottom view which shows the semiconductor package by the 2nd Embodiment of this invention. FIG. 17 is a cross-sectional view taken along line ZZ of FIG. 16. It is a top view for explaining the manufacturing method of the semiconductor package by a 2nd embodiment of this invention. It is sectional drawing for demonstrating the mounting method of the semiconductor package by the 2nd Embodiment of this invention. It is a circuit diagram and a plan view showing module 5 using a semiconductor package by a 2nd embodiment of the present invention. It is a circuit diagram and a top view showing module 6 using a semiconductor package by a 2nd embodiment of the present invention. It is a circuit diagram and a plan view showing module 7 using a semiconductor package by a 2nd embodiment of the present invention. It is a circuit diagram which shows the module 8 which used the semiconductor package by the 2nd Embodiment of this invention. It is a top view which shows the module 8 which used the semiconductor package by the 2nd Embodiment of this invention. It is a top view which shows the module 9 using the semiconductor package by the 2nd Embodiment of this invention. It is sectional drawing which shows the semiconductor package by the 3rd Embodiment of this invention. It is sectional drawing for demonstrating the mounting method of the semiconductor package by the 3rd Embodiment of this invention. It is a top view which shows the module 10 which used the semiconductor package by the 3rd Embodiment of this invention. It is a circuit diagram which shows the module 11 which used the semiconductor package by the 3rd Embodiment of this invention. It is a top view which shows the module 11 using the semiconductor package by the 3rd Embodiment of this invention. It is a top view which shows the semiconductor package by the 4th Embodiment of this invention. It is a bottom view which shows the semiconductor package by the 4th Embodiment of this invention. It is sectional drawing which follows the XX line of FIG. It is sectional drawing for demonstrating the mounting method of the semiconductor package by the 4th Embodiment of this invention. It is sectional drawing which shows the semiconductor package by the 5th Embodiment of this invention. It is sectional drawing for demonstrating the mounting method of the semiconductor package by the 5th Embodiment of this invention. It is sectional drawing for demonstrating the method of mounting the semiconductor package by 3rd Embodiment in 6th Embodiment of this invention. FIG. 16 is a circuit diagram and a plan view showing a module 12 having a semiconductor package mounted according to a third embodiment of the sixth embodiment of the present invention. It is a top view which shows the diode for reverse connection protection used in the module 12 which mounted the semiconductor package by 3rd Embodiment in 6th Embodiment of this invention. It is sectional drawing for demonstrating the method of mounting the semiconductor package by 3rd Embodiment in 7th Embodiment of this invention. It is sectional drawing for demonstrating the method of mounting the semiconductor package by 3rd Embodiment in 8th Embodiment of this invention. It is sectional drawing for demonstrating the method of mounting the semiconductor package and GaN-based semiconductor chip by 3rd Embodiment in 9th Embodiment of this invention. It is sectional drawing for demonstrating the method of mounting the semiconductor package and GaN-type semiconductor chip by 3rd Embodiment in 10th Embodiment of this invention. It is a top view which shows the semiconductor package by the 11th Embodiment of this invention. It is a bottom view which shows the semiconductor package by the 11th Embodiment of this invention. It is sectional drawing which follows the XX line of FIG. It is sectional drawing which follows the YY line of FIG. It is a top view which shows the specific example of the semiconductor chip C in the semiconductor package by the 11th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the semiconductor package by the 11th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the semiconductor package by the 11th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the semiconductor package by the 11th Embodiment of this invention. It is a top view for explaining the manufacturing method of the semiconductor package by the 11th embodiment of this invention. It is sectional drawing for demonstrating the method of mounting the semiconductor package by the 11th Embodiment of this invention. It is an approximate line figure showing the circuit composition of the semiconductor package by a 12th embodiment of this invention. It is the top view, bottom view, and sectional view showing a semiconductor package by a 12th embodiment of this invention. It is an approximate line figure showing the circuit composition of the semiconductor package by a 13th embodiment of this invention. It is the top view and bottom view which show the semiconductor package by the 13th Embodiment of this invention. It is an approximate line figure showing the circuit composition of the semiconductor package by a 14th embodiment of this invention. It is a top view which shows the semiconductor package by the 14th Embodiment of this invention. It is a sectional view for explaining the technology of packaging the chip of the conventional power Si-MOS transistor of the vertical structure. FIG. 10 is a cross-sectional view for explaining a technique of packaging a plurality of chips of a conventional power Si-MOS transistor having a vertical structure in one package. It is sectional drawing for demonstrating the mounting method of the bare chip of the conventional power Si-MOS transistor of a vertical structure.

Hereinafter, modes for carrying out the invention (hereinafter, referred to as embodiments) will be described.
<1. First Embodiment>
[Semiconductor package]
The semiconductor package according to the first embodiment will be described. This semiconductor package has the same structure as the QFN package. This semiconductor package is obtained by resin-sealing a semiconductor chip that constitutes a GaN-based FET having a lateral structure in which a source electrode, a drain electrode, and a gate electrode are provided on the same surface. This semiconductor package is shown in FIGS. 1 is a plan view, FIG. 2 is a bottom view (rear view), FIG. 3 is a sectional view taken along line XX of FIG. 1, and FIG. 4 is a sectional view taken along line YY of FIG. is there.

As shown in FIGS. 1 to 4, the semiconductor package has a flat rectangular parallelepiped shape as a whole. In this semiconductor package, a semiconductor layer 20 constituting a GaN-based FET is provided on a first main surface of an electrically insulating insulating substrate 10, and a source electrode 30, a drain electrode 40 and a gate are provided on the semiconductor layer 20. The semiconductor chip C provided with the electrodes 50 is resin-sealed. The insulating substrate 10 is not particularly limited, but is typically a sapphire substrate, especially a C-plane sapphire substrate, and the thickness thereof is preferably 150 μm or less, more preferably 120 μm or less, and preferably 50 μm or more. The semiconductor layer 20 is a schematic diagram collectively showing a plurality of GaN-based semiconductor layers forming a GaN-based FET. The semiconductor layer 20 is appropriately designed according to the type of GaN-based FET and the like. The semiconductor chip C has a rectangular (including square) planar shape. These source electrode 30, drain electrode 40, and gate electrode 50 are arranged in a triangle. In other words, the center of each of the source electrode 30, the drain electrode 40, and the gate electrode 50 is arranged at each vertex of the triangle. The material forming the source electrode 30, the drain electrode 40, and the gate electrode 50 is selected from conventionally known materials as needed. The planar shapes of the source electrode 30, the drain electrode 40, and the gate electrode 50 are not particularly limited and may be selected as needed. In this example, the source electrode 30 has a rectangular shape having parallel short sides perpendicular sides S ₂ parallel long sides and sides S ₁ to the side S ₁ of the semiconductor chip C, the sides S _1, It is provided close to S ₂ , and the length of the long side of the source electrode 30 is shorter than the length of the side S ₁ . The drain electrode 40 has a rectangular shape having parallel short sides to the side S side S long sides and the side S ₂ parallel to ₃ facing the _first semiconductor chip C, the sides S _2, S ₃ And the lengths of the long side and the short side of the drain electrode 40 are equal to those of the source electrode 30. The gate electrode 50 has a rectangular shape having a long side parallel to the side S ₄ of the semiconductor chip C and a short side parallel to the side S ₁ , and a region between the source electrode 30 and the side S _4. Are provided close to the sides S ₁ and S ₄ . The source electrode 30 and the drain electrode 40 are typically formed in an interdigital structure.

Electrode pads 60, 70 and 80 are electrically connected to the source electrode 30, the drain electrode 40 and the gate electrode 50, respectively. Since the source electrode 30, the drain electrode 40, and the gate electrode 50 are arranged in a triangle, these electrode pads 60, 70, 80 can also be arranged in a triangle. The material forming these electrode pads 60, 70, 80 is selected from conventionally known materials as needed. The surfaces of the semiconductor layer 20, the source electrode 30, the drain electrode 40, and the gate electrode 50 which are not covered with the electrode pads 60, 70, 80 are electrically insulated from the side surfaces of the insulating substrate 10 and the semiconductor layer 20. Is covered with resin 90 and is sealed. The material of the resin 90 is selected as necessary, but is, for example, an epoxy resin. The electrode pad 60 connected to the source electrode 30 extends from the source electrode 30 on the resin 90 in parallel with the semiconductor layer 20 and the insulating substrate 10 and then bends vertically to form a side S of the resin 90 on the semiconductor chip C. ₁ , extends parallel to the side surfaces of the semiconductor layer 20 and the insulating substrate 10 along the side surfaces parallel to S ₁ and S ₂ , and terminates at the same height as the second main surface of the insulating substrate 10. That is, the lower end surface of the electrode pad 60 and the second main surface of the insulating substrate 10 are flush with each other. The electrode pad 70 connected to the drain electrode 40 extends from the drain electrode 40 on the resin 90 in parallel with the semiconductor layer 20 and the insulating substrate 10, and then bends vertically to form a side S of the resin 90 on the semiconductor chip C. _2, S _3, along the sides parallel to the S ₄ extends parallel to the side surface of the semiconductor layer 20 and the insulating substrate 10 and terminates in a second main surface the same height as the insulating substrate 10. That is, the lower end surface of the electrode pad 70 and the second main surface of the insulating substrate 10 are flush with each other. The electrode pad 80 connected to the gate electrode 50 extends from the gate electrode 50 on the resin 90 in parallel with the semiconductor layer 20 and the insulating substrate 10 and then bends vertically to form a side S of the resin 90 on the semiconductor chip C. ₁ , extends parallel to the side surfaces of the semiconductor layer 20 and the insulating substrate 10 along the side surfaces parallel to S ₁ and S ₄ , and terminates at the same height as the second main surface of the insulating substrate 10. That is, the lower end surface of the electrode pad 80 and the second main surface of the insulating substrate 10 are flush with each other. Further, the electrode pad 60 extends so as to overlap a rectangular region of the semiconductor layer 20 including one corner where the side S ₁ and the side S ₂ intersect. The electrode pad 70 includes a corner of the semiconductor layer 20 where the side S ₂ and the side S ₃ intersect and a corner of the side S ₃ and the side S ₄ where the long side has a length of the side S ₃ . It extends so as to overlap the same rectangular area. The electrode pad 80 extends so as to overlap a rectangular region of the semiconductor layer 20 including one corner where the side S ₁ and the side S ₄ intersect.

To give an example of the size of each part of this semiconductor package, the length of one side of the insulating substrate 10 is 2 to 5 mm, and the height from the back surface of the insulating substrate 10 to the upper surfaces of the source electrode 30, the drain electrode 40, and the gate electrode 50 is: About 0.15 mm, the total thickness is about 3 mm, the thickness of the electrode pads 60, 70, 80 on the insulating substrate 10 is about 0.15 mm, the resin 90 on the side surface of the insulating substrate 10 and the electrode pads 60, 70, 80. Has a total thickness of about 1 mm.

[Semiconductor package manufacturing method]
5A to 5E show an example of a method for manufacturing this semiconductor package.

As shown in FIG. 5A, first, a metal plate 100 for forming a lead frame is prepared. The metal plate 100 is selected from conventionally known materials as necessary, and is, for example, a Cu alloy or an iron (Fe)-nickel (Ni) alloy.

Next, as shown in FIG. 5B, the metal plate 100 is partially punched by a predetermined repeating pattern according to the QFN package to be manufactured and a step is partially formed by press working, and the lead frame 110 having a predetermined shape is formed. To form. The plan shape of the lead frame 110 is shown in FIG. However, FIG. 6 is a plan view of the lead frame 110 shown in FIG. 5B when viewed from below. 5B is a cross-sectional view taken along the line BB of FIG. Step portions 111a, 112a, 113a are formed at the tips of electrode pad forming portions 111, 112, 113 that will eventually become the electrode pads 60, 70, 80 of the lead frame 110.

Next, as shown in FIG. 5C, the source electrode 30, the drain electrode 40, and the gate are formed on the source electrode 30, the drain electrode 40, and the gate electrode 50 of the semiconductor chip C with solder (not shown) formed thereon. The electrode 50 is directed downward and brought into contact with the surfaces of the step portions 111a, 112a, 113a of the lead frame 110, respectively, and then heat treatment is performed to melt the solder. Thus, the source electrode 30, the drain electrode 40, and the gate electrode 50 are soldered to the step portions 111a, 112a, 113a of the lead frame 110, respectively. A plan view of this state is shown in FIG. However, FIG. 7 is a plan view of the lead frame 110 and the semiconductor chip C shown in FIG. 5C when viewed from below. FIG. 5C is a cross-sectional view taken along the line CC of FIG. 7.

Next, as shown in FIG. 5D, resin molding is performed so as to fill the space below the stepped portions 111 a, 112 a, 113 a of the lead frame 110 and the semiconductor layer 20 of the semiconductor chip C, and the semiconductor chip C is formed on the insulating substrate 10. It is sealed with resin 90 except the back surface. A plan view of this state is shown in FIG. However, FIG. 8 is a plan view of the lead frame 110, the semiconductor chip C, and the resin 90 shown in FIG. 5D when viewed from below. FIG. 5D is a cross-sectional view taken along the line DD of FIG.

Thereafter, the lead frame 111 is cut along a predetermined cutting line indicated by a chain double-dashed line in FIGS. 5D and 8 and separated as shown in FIG. 5E. Thus, the intended semiconductor package shown in FIGS. 1 to 4 is manufactured.

[Specific Example 1 of GaN-based FET]
FIG. 9 shows a polarization superjunction GaN-based FET (see Patent Document 2). As shown in FIG. 9, in this polarization superjunction GaN-based FET, a low-temperature grown GaN buffer layer 21 and an undoped GaN layer 22 are formed on an insulating substrate 10 such as a C-plane sapphire substrate on which a GaN-based semiconductor grows in the C-plane. An undoped Al _x Ga _1-x N layer 23 (0.17≦x≦0.35) having a thickness of 25 nm or more and 47 nm or less, an undoped GaN layer 24, and a p-type GaN layer 25 doped with Mg are sequentially stacked. ing. This polarization superjunction GaN-based FET has a polarization superjunction region (PSJ region) and a p-electrode contact region which are provided separately from each other. Further, on the p-type GaN layer 25 in the p-electrode contact region, the p ⁺ -type that is in contact with the p-type GaN layer 25 only in the p-electrode contact region and is more heavily doped with Mg than the p-type GaN layer 25 is. A GaN contact layer 26 is provided. A gate electrode 50 made of a p-electrode is provided on the p ⁺ -type GaN contact layer 26. A source electrode 30 and a drain electrode 40 are provided on the undoped Al _x Ga _1-x N layer 23. These source electrode 30, drain electrode 40, and gate electrode 50 are arranged in a triangle.

In this polarization superjunction GaN-based FET, the thickness of the undoped GaN layer 24 is u [nm], the thickness of the p-type GaN layer 25 is v [nm], and the Mg concentration of the p-type GaN layer 25 is w [cm ^{− 3} ], and the converted thickness tR is tR=u+v(1+w×10 ⁻¹⁸ ).
, The undoped Al _x Ga _1-x N layer 23,
tR≧0.864/(x−0.134)+46.0 [nm]
Is satisfied, the undoped GaN layer 24 in the vicinity of the hetero interface between the undoped GaN layer 24 and the undoped Al _x Ga _1-x N layer 23 has a two-dimensional hole gas (2DHG) concentration of 1×10 ¹² cm ^-2 or more. ) Can be generated.

[Specific Example 2 of GaN-based FET]
FIG. 10 shows a polarized superjunction GaN-based FET (see Patent Document 1). As shown in FIG. 10, in this polarization super-junction GaN-based FET, a low-temperature grown GaN buffer layer 21 and an undoped GaN layer 22 are formed on an insulating substrate 10 such as a C-plane sapphire substrate on which a GaN-based semiconductor is C-plane grown. , Al _x Ga _1-x N layer 23, undoped GaN layer 24 and Mg-doped p-type GaN layer 25 are sequentially stacked. This polarization superjunction GaN-based FET has a polarization superjunction region (PSJ region) and a p-electrode contact region which are provided separately from each other. The p-type GaN layer 25 is not provided in the polarization superjunction region, but is provided only in the p-electrode contact region. Further, on the p-type GaN layer 25 in the p-electrode contact region, the p ⁺ -type that is in contact with the p-type GaN layer 25 only in the p-electrode contact region and is more heavily doped with Mg than the p-type GaN layer 25 is. A GaN contact layer 26 is provided. A gate electrode 50 made of a p-electrode is provided on the p ⁺ -type GaN contact layer 26. A source electrode 30 and a drain electrode 40 are provided on the Al _x Ga _1-x N layer 23. These source electrode 30, drain electrode 40, and gate electrode 50 are arranged in a triangle.

但し、αは
Log（α）＝ｐ₀ ＋ｐ₁ log （ａ）＋ｐ₂ ｛log （ａ）｝²
（但し、ｐ₀ ＝７．３２９５、ｐ₁ ＝−３．５５９９、ｐ₂ ＝０．６９１２）
で表され、
かつ、βは
β＝ｐ'₀＋ｐ'₁ log（ａ）＋ｐ'₂｛log （ａ）｝²
（但し、ｐ'₀＝−３．６５０９、ｐ'₁＝１．９４４５、ｐ'₂＝−０．３７９３）
で表される。 In this polarization super-junction GaN-based FET, the Al composition x and the thickness t [nm] of the Al _x Ga _{1 -x} N layer 23 forming the polarization super-junction region are the thickness of the undoped GaN layer 24 a [nm] ( However, when a is 10 nm or more and 1000 nm or less), it is selected so as to satisfy the following formula.

However, α is
Log(α)=p ₀ +p ₁ log (a)+p ₂ {log (a)} ²
(However, p ₀ =7.3295, p ₁ =−3.5599, p ₂ =0.6912)
Is represented by
Also, β is β=p′ ₀ +p′ ₁ log(a)+p′ ₂ {log(a)} ²
_{(However, p '0 = -3.6509, p} ' 1 = 1.9445, p '2 = -0.3793)
It is represented by.

With the above structure, 2DHG having a concentration of 1×10 ¹² cm ⁻² or more is generated in the undoped GaN layer 24 in the vicinity of the hetero interface between the undoped GaN layer 24 and the Al _x Ga _{1 -x} N layer 23. be able to.

[Semiconductor package mounting method]
A method of mounting the semiconductor package will be described. Here, a case where a DBC substrate is used as the mounting substrate will be described.

As shown in FIGS. 11A and 11B, the semiconductor package 300 is mounted on the DBC substrate 200. Here, FIG. 11A is a plan view, and FIG. 11B is a cross-sectional view taken along the line BB of FIG. 11A. Specifically, the source wiring 210, the drain wiring 220, and the gate wiring 230 are formed by patterning the Cu layer on the SiN layer 200b on the Cu base substrate 200a of the DBC substrate 200. The source wiring 210 has a planar shape that is bent by 90° and includes a portion parallel to one side E ₁ of the semiconductor package 300 and a portion parallel to a side E ₂ perpendicular to the side E ₁ . The drain wiring 220 has an elongated rectangular shape parallel to the side E ₁ of the semiconductor package 300. The gate wiring 230 has a rectangular shape having sides parallel to the sides E ₁ and E ₂ of the semiconductor package 300. The semiconductor package 300 is mounted on this DBC substrate 200. That is, as shown in FIGS. 11A and 11B, predetermined portions of the source wiring 210, the drain wiring 220, and the gate wiring 230 of the DBC substrate 200 are connected to the source electrode 30, the drain electrode 40, and the gate electrode 50 of the semiconductor package 300, respectively. The electrode pads 60, 70, 80 are connected by soldering or the like.

[Module configuration example]
A configuration example of a module using the semiconductor package 300 will be described.

[Module 1]
FIG. 12A is a circuit diagram showing a module 1 having parallel-connected transistors configured by using three semiconductor packages 300, and FIG. 12B shows a configuration example of this module 1. As shown in FIG. 12B, three semiconductor packages 300 are mounted on the DBC substrate 200 to form parallel-connected transistors. Each semiconductor package 300 is mounted similarly to the mounting example shown in FIGS. 11A and 11B, but the source wiring 210, the drain wiring 220, and the gate wiring 230 are formed as wiring common to the three semiconductor packages 300. Here, none of the source wiring 210, the drain wiring 220, and the gate wiring 230 intersect with each other.

[Module 2]
FIG. 13A is a circuit diagram showing a module 2 having a series connection transistor configured by using two semiconductor packages 300, and FIG. 13B shows a configuration example of this module 2. As shown in FIG. 13B, two semiconductor packages 300 are mounted on the DBC substrate 200 to form series-connected transistors. Each semiconductor package 300 is mounted similarly to the mounting example shown in FIGS. 11A and 11B, but the source wiring 210, the drain wiring 220, and the gate wiring 230 are formed as wiring common to the two semiconductor packages 300. Here, none of the source wiring 210, the drain wiring 220, and the gate wiring 230 intersect with each other.

[Module 3]
FIG. 14A is a circuit diagram showing a module 3 having a cascode circuit configured by using one semiconductor package 300 and one commercially available SiMOS transistor, and FIG. 14B shows a configuration example of this module 3. As shown in FIG. 14B, one semiconductor package 300 is mounted on the DBC substrate 200, and a Si chip 400 forming a SiMOS transistor is mounted adjacent to this semiconductor package 300 to form a cascode circuit. The semiconductor package 300 is mounted similarly to the mounting example shown in FIGS. 11A and 11B. A part of the source wiring 210 extends below the Si chip 400 and is electrically connected to the entire surface electrode formed on the back surface of the Si substrate of the Si chip 400. Then, the source electrode 410 provided on the Si chip 400 and the pad electrode 240 provided adjacent to the Si chip 400 are bonded by the wire 510 to form the gate electrode 420 provided on the Si chip 400. A wire 520 is bonded between the Si chip 400 and a pad electrode 250 provided adjacent to the Si chip 400. Here, the pad electrodes 240 and 250 are formed by patterning the Cu layer of the DBC substrate 200, similarly to the source wiring 210, the drain wiring 220, and the gate wiring 230. Also in this case, the source wiring 210, the drain wiring 220, the gate wiring 230, and the pad electrodes 240 and 250 do not intersect each other.

[Module 4]
FIG. 15A is a circuit diagram showing a module 4 having an inverter arm configured by using two semiconductor packages 300 and two commercially available SiMOS transistors, and FIG. 15B shows a configuration example of this module 4. As shown in FIG. 15B, one semiconductor package 300 is mounted on the DBC substrate 200, one Si chip 400 constituting a SiMOS transistor is mounted adjacent to this semiconductor package 300, and adjacent to this Si chip 400. Another semiconductor package 300 is mounted, and another Si chip 400 forming a SiMOS transistor is mounted adjacent to the semiconductor package 300 to form an inverter arm. Each semiconductor package 300 is mounted similarly to the mounting example shown in FIGS. 11A and 11B, but the source wiring 210, the drain wiring 220, and the gate wiring 230 are formed as wiring common to the two semiconductor packages 300. Similar to the module 3, a part of the source wiring 210 extends below the Si chip 400 and is electrically connected to the entire surface electrode formed on the back surface of the Si substrate of the Si chip 400. A source electrode 410 provided on the Si chip 400 and a pad electrode 240 provided adjacent to the Si chip 400 are bonded by a wire 510 to form a gate electrode 420 provided on the Si chip 400. A wire 520 is bonded between the Si chip 400 and a pad electrode 250 provided adjacent to the Si chip 400. Also in this case, the source wiring 210, the drain wiring 220, the gate wiring 230, and the pad electrodes 240 and 250 do not intersect each other.

According to the first embodiment, the following various advantages can be obtained. That is, the semiconductor layer 20 constituting the GaN-based FET is provided on the first main surface of the insulating substrate 10, the source electrode 30, the drain electrode 40, and the gate electrode 50 are arranged in a triangle on the semiconductor layer 20, and the source of these sources is used. The semiconductor chip C in which the electrode pads 60, 70, and 80 are respectively pulled out from the electrode 30, the drain electrode 40, and the gate electrode 50 to the outside of the semiconductor layer 20 is sealed with the resin 90, so that the semiconductor package 300 in a QFN package shape is obtained. Can be configured. Then, by facing the insulating substrate 10 side of the semiconductor chip C of the semiconductor package 300 toward the DBC substrate 200 and connecting the electrode pads 60, 70, 80 to the wiring formed on the DBC substrate 200, the GaN-based FET is faced. Since it can be easily mounted on the DBC substrate 200, the cost can be significantly reduced, the frequency can be increased, the volume can be saved, and the thermal resistance can be reduced, as compared with the related art. Moreover, the source electrode 30, the drain electrode 40, and the gate electrode 50 are arranged in a triangle, and therefore the electrode pads 60, 70, 80 can also be arranged in a triangle, so that the wirings on the DBC substrate 200 are formed so as not to intersect with each other. Therefore, a high-performance module in which the semiconductor package 300 is mounted can be easily realized. By using this module, high-performance electric equipment can be realized at low cost.

<2. Second Embodiment>
[Semiconductor package]
A semiconductor package according to the second embodiment will be described. Similar to the semiconductor package according to the first embodiment, this semiconductor package is also a GaN-based FET that is resin-sealed and has the same structure as the QFN package. This semiconductor package is shown in FIGS. 16 is a plan view, FIG. 17 is a bottom view (rear view), and FIG. 18 is a cross-sectional view taken along the line ZZ of FIG.

As shown in FIGS. 16 to 18, in this semiconductor package, the resin 90 covering the surfaces of the semiconductor layer 20, the source electrode 30, the drain electrode 40, and the gate electrode 50 is thinner than the thickness of the electrode pads 60, 70, 80. The electrode pad 60, 70, 80 is formed to have a sufficiently large thickness and extends partway along the portion of the electrode pads 60, 70, 80 parallel to the semiconductor layer 20. Further, the electrode pads 60, 70, 80 project outward from the contour of the resin 90, extend along the side surface of the resin 90 in parallel with the side surfaces of the semiconductor layer 20 and the insulating substrate 10, and reach the first side of the insulating substrate 10. The two main surfaces and the lower surface of the resin 90 terminate at the same height. Other configurations are the same as those in the first embodiment.

To give an example of the size of each part of this semiconductor package, the length of one side of the insulating substrate 10 is 2 to 5 mm, and the height from the back surface of the insulating substrate 10 to the upper surfaces of the source electrode 30, the drain electrode 40, and the gate electrode 50 is: About 0.15 mm, the thickness of the electrode pads 60, 70, 80 is 0.3 mm, the thickness of the resin 90 on the side surface of the insulating substrate 10 is 0.6 mm, and the thickness of the electrode pads 60, 70, 80 on the side surface of the insulating substrate 10 is The thickness is about 0.7 mm, and the height from the upper surface of the electrode pads 60, 70, 80 to the upper surface of the resin 90 provided thereon is 0.3 mm.

[Semiconductor package manufacturing method]
The method of manufacturing this semiconductor package is basically the same as the method of manufacturing the semiconductor package according to the first embodiment. A plan view corresponding to FIG. 7 is shown in FIG.

[Specific Example of GaN-based FET]
Specific examples of the GaN-based FET are similar to the specific examples 1 and 2 of the semiconductor package according to the first embodiment, for example.

[Semiconductor package mounting method]
A method of mounting this semiconductor package will be described. Here, a case where a DBC substrate is used as the mounting substrate will be described.

As shown in FIG. 20, the semiconductor package 300 is mounted on the DBC substrate 200. Here, FIG. 20 is a cross-sectional view corresponding to FIG. 11B. Specifically, by patterning the Cu layer of the DBC substrate 200, the source wiring 210, the drain wiring 220, and the gate wiring 230 are formed, and at the same time, the electrode 260 is formed. On the source wiring 210, the drain wiring 220, the gate wiring 230, and the electrode 260, a conductive layer 500 made of a conductive paste containing nano Ag particles is formed. The conductive layer 500 has a thickness of 0.15 mm, for example. The semiconductor package 300 is mounted on this DBC substrate 200. That is, as shown in FIG. 20, electrodes connected to the source electrode 30, the drain electrode 40, and the gate electrode 50 of the semiconductor package 300 on predetermined portions of the source wiring 210, the drain wiring 220, and the gate wiring 230 of the DBC substrate 200, respectively. The pads 60, 70, 80 are connected via the conductive layer 500. At the same time, the back surface of the insulating substrate 10 of the semiconductor package 300 is connected to the electrode 260 of the DBC substrate 200 via the conductive layer 500. The conductive layer 500 that contacts the back surface of the insulating substrate 10 is a heat conductive layer for conducting the heat generated in the operation of the semiconductor package 300 and transferred to the insulating substrate 10 to the electrode 260, and dissipating the heat by the DBC substrate 200. work.

[Module configuration example]
A configuration example of a module using the semiconductor package 300 will be described.

[Module 5]
21A is a circuit diagram showing a module 5 having parallel-connected transistors configured by using three semiconductor packages 300, and FIG. 21B shows a configuration example of this module 5. As shown in FIG. 21B, three semiconductor packages 300 are mounted on the DBC substrate 200 to form parallel-connected transistors. Each semiconductor package 300 is mounted similarly to the mounting example shown in FIG. 20, but the source wiring 210, the drain wiring 220, and the gate wiring 230 are formed as wiring common to the three semiconductor packages 300. Here, none of the source wiring 210, the drain wiring 220, and the gate wiring 230 intersect with each other.

[Module 6]
FIG. 22A is a circuit diagram showing a module 6 having a series-connected transistor configured by using two semiconductor packages 300, and FIG. 22B shows a configuration example of this module 2. As shown in FIG. 22B, two semiconductor packages 300 are mounted on the DBC substrate 200 to form series-connected transistors. Each semiconductor package 300 is mounted similarly to the mounting example shown in FIG. 20, but the source wiring 210, the drain wiring 220, and the gate wiring 230 are formed as wiring common to the two semiconductor packages 300. Here, none of the source wiring 210, the drain wiring 220, and the gate wiring 230 intersect with each other.

[Module 7]
FIG. 23A is a circuit diagram showing a module 7 having a cascode circuit configured by using one semiconductor package 300 and one commercially available SiMOS transistor, and FIG. 23B shows a configuration example of this module 7. As shown in FIG. 23B, one semiconductor package 300 is mounted on the DBC substrate 200, and a Si chip 400 forming a SiMOS transistor is mounted adjacent to this semiconductor package 300 to form a cascode circuit. The semiconductor package 300 is mounted similarly to the mounting example shown in FIG. A part of the source wiring 210 extends below the Si chip 400 and is electrically connected to the entire surface electrode formed on the back surface of the Si substrate of the Si chip 400. Then, the source electrode 410 provided on the Si chip 400 and the pad electrode 240 provided adjacent to the Si chip 400 are bonded by the wire 510 to form the gate electrode 420 provided on the Si chip 400. A wire 520 is bonded between the Si chip 400 and a pad electrode 250 provided adjacent to the Si chip 400. Here, the pad electrodes 240 and 250 are formed by patterning the Cu layer of the DBC substrate 200, similarly to the source wiring 210, the drain wiring 220, and the gate wiring 230. Also in this case, the source wiring 210, the drain wiring 220, the gate wiring 230, and the pad electrodes 240 and 250 do not intersect each other.

[Module 8]
FIG. 24 is a circuit diagram showing a module 8 having an inverter arm configured by using a plurality of semiconductor packages 300, and FIG. 25 shows a configuration example of this module 8. As shown in FIG. 25, a plurality of semiconductor packages 300 are mounted on the DBC substrate 200 in two rows to form an inverter arm. Each semiconductor package 300 is mounted similarly to the mounting example shown in FIG. In this case, the source wiring 281, the output wiring 282 which is the drain wiring, and the gate wiring 283 (wirings denoted by Vl, Out, and Gl in FIG. 24, respectively) of the lower arm are wirings common to the semiconductor packages 300 in one row of the lower arm. Is formed as. The source wiring 281 of the upper arm is composed of the output wiring 282. The drain wiring 284 and the gate wiring 285 of the upper arm (wirings indicated by Vu and Gu in FIG. 24, respectively) are formed as wiring common to the semiconductor packages 300 in one row of the upper arm. Here, the source wiring 281, the output wiring 282, the gate wiring 283, the drain wiring 284, and the gate wiring 285 are formed by patterning the Cu layer of the DBC substrate 200. Also in this case, none of the source wiring 281, the output wiring 282, the gate wiring 283, the drain wiring 284, and the gate wiring 285 intersect with each other.

[Module 9]
FIG. 26 shows a configuration example of a module 9 having a cascode circuit configured by using one semiconductor package 300 and one commercially available SiMOS transistor SOS package 600. The circuit diagram of this module 9 is as shown in FIG. 14A. As shown in FIG. 26, a plurality of semiconductor packages 300 are mounted in a row on the DBC substrate 200, and a SiMOS transistor SOS package 600 is mounted adjacent to one semiconductor package 300 to form a cascode circuit. Each semiconductor package 300 is mounted similarly to the mounting example shown in FIG. The SiMOS transistor SOS package 600 has two source terminals 601, 602, three drain terminals 603, 604, 605 and one gate terminal 606. The source terminals 601 and 602 are connected to the source wiring 291. The drain terminals 603, 604, 605 are connected to the source wiring 210 of the semiconductor package 300. The gate terminal 606 is connected to the gate wiring 292. Here, the source wiring 291 and the gate wiring 292 are formed by patterning the Cu layer of the DBC substrate 200, similarly to the source wiring 210, the drain wiring 220, and the gate wiring 230. Also in this case, the source wiring 210, the drain wiring 220, the gate wiring 230, the source wiring 291, and the gate wiring 292 do not intersect each other.

According to the second embodiment, the same advantages as those of the first embodiment can be obtained.

<3. Third Embodiment>
[Semiconductor package]
A semiconductor package according to the third embodiment will be described. Similar to the semiconductor package according to the first embodiment, this semiconductor package is also a GaN-based FET that is resin-sealed and has the same structure as the QFN package. FIG. 27 is a sectional view of this semiconductor package. The plan view and bottom view (backside view) of this semiconductor package are similar to those shown in FIGS. FIG. 27 corresponds to a cross-sectional view taken along the line ZZ of FIG.

As shown in FIG. 27, in this semiconductor package, the electrode pads 60, 70, 80 extend in a direction parallel to the semiconductor layer 20 and project outside from the contour of the resin 90. Other configurations are similar to those of the second embodiment.

To give an example of the size of each part of this semiconductor package, the length of one side of the insulating substrate 10 is 2 to 5 mm, and the height from the back surface of the insulating substrate 10 to the upper surfaces of the source electrode 30, the drain electrode 40, and the gate electrode 50 is: About 0.15 mm, the thickness of the electrode pads 60, 70, 80 is 0.3 mm, the thickness of the resin 90 on the side surface of the insulating substrate 10 is 0.6 mm, and the electrode pads 60, 70, 80 are provided on the upper surface thereof. The height of the resin 90 to the upper surface is 0.3 mm, and the protruding length of the electrode pads 60, 70, 80 from the resin 90 is 0.7 mm.

[Semiconductor package manufacturing method]
The method of manufacturing this semiconductor package is basically the same as the method of manufacturing the semiconductor package according to the first embodiment.

[Specific Example of GaN-based FET]
Specific examples of the GaN-based FET are similar to the specific examples 1 and 2 of the semiconductor package according to the first embodiment, for example.

[Semiconductor package mounting method]
A method of mounting this semiconductor package will be described. Here, a case where a DBC substrate is used as the mounting substrate will be described.

As shown in FIG. 28, the semiconductor package 300 is mounted on the DBC substrate 200. Specifically, the Cu layer and the SiN layer 200b of the DBC substrate 200 are patterned to expose the Cu base substrate 200a of the mounting portion of the semiconductor package 300 and form the source wiring 210, the drain wiring 220, and the gate wiring 230. To do. A conductive layer 500 made of a conductive paste containing nano Ag particles is formed on the source wiring 210, the drain wiring 220, the gate wiring 230, and the Cu base substrate 200a in the mounting portion of the semiconductor package 300. The conductive layer 500 has a thickness of 0.15 mm, for example. The semiconductor package 300 is mounted on this DBC substrate 200. That is, as shown in FIG. 28, electrodes connected to the source electrode 30, the drain electrode 40, and the gate electrode 50 of the semiconductor package 300 at predetermined portions of the source wiring 210, the drain wiring 220, and the gate wiring 230 of the DBC substrate 200, respectively. The pads 60, 70, 80 are connected via the conductive layer 500. The insulating substrate 10 of the semiconductor package 300 is in contact with the Cu base substrate 200a via the conductive layer 500. The conductive layer 500 in contact with the back surface of the insulating substrate 10 functions as a heat conductive layer for conducting the heat generated during the operation of the semiconductor package 300 and transferred to the insulating substrate 10 to the Cu base substrate 200a to radiate the heat.

[Module configuration example]
The semiconductor package 300 can be used to configure the same modules as the modules 5 to 8 and the following modules 10 and 11.

[Module 10]
FIG. 29 shows a configuration example of the module 10 having a cascode circuit configured by using one semiconductor package 300 and one commercially available SiMOS transistor SOS package 600. The circuit diagram of this module 10 is as shown in FIG. 14A. As shown in FIG. 29, this module 10 has substantially the same structure as the module 9 shown in FIG. 26, but in the module 9 shown in FIG. 26, the gate wiring 230 is formed by patterning the Cu layer of the DBC substrate 200. However, this module 10 is different in that the gate electrode bar is in contact with the electrode pad 80 connected to the gate electrode 50 of each semiconductor package 300 from above.

[Module 11]
FIG. 30 is a circuit diagram showing a module 11 having parallel-connected transistors configured by using 10 semiconductor packages 300, and FIG. 31 shows a configuration example of this module 11. As shown in FIG. 31, ten semiconductor packages 300 are mounted on the DBC substrate 200 to form parallel-connected transistors. Each semiconductor package 300 is mounted similarly to the mounting example shown in FIG. 28, but the source wiring 210, the drain wiring 220, and the gate wiring 700 are formed as wiring common to these semiconductor packages 300. Here, the source wiring 210 and the drain wiring 220 are formed by patterning the Cu layer of the DBC substrate 200, while the gate wiring 700 is connected to the gate electrode 50 of each semiconductor package 300 as a gate electrode bar. The difference is that the electrode pad 80 is contacted from above. However, wire bonding may be used instead of the gate electrode bar. Here, none of the source wiring 210, the drain wiring 220, and the gate wiring 700 intersect with each other. This module 11 is suitable when it is desired to reduce the thermal resistance to the limit and when it is desired to connect the semiconductor packages 300 in parallel with a single function to obtain a large current. The lower part of each semiconductor package 300 is not connected to the electrodes and is independent of each other.

According to this third embodiment, the same advantages as those of the first embodiment can be obtained.

<4. Fourth Embodiment>
[Semiconductor package]
A semiconductor package according to the fourth embodiment will be described. Similar to the semiconductor package according to the first embodiment, this semiconductor package is also a GaN-based FET that is resin-sealed and has the same structure as the QFN package. This semiconductor package is shown in FIGS. 32 is a plan view, FIG. 33 is a bottom view (rear view), and FIG. 34 is a sectional view taken along line XX of FIG.

As shown in FIGS. 32 to 34, in this semiconductor package, the resin 90 extends from the side surface of the insulating substrate 10 to the peripheral portion of the back surface, and the resin 90 is formed on the central portion of the back surface of the insulating substrate 10. The semiconductor package has the same configuration as the semiconductor package according to the second embodiment, except that an opening having a shape similar to that of the insulated substrate 10 is formed.

To give an example of the size of each part of this semiconductor package, the length of one side of the insulating substrate 10 is 2 to 5 mm, and the height from the back surface of the insulating substrate 10 to the upper surfaces of the source electrode 30, the drain electrode 40, and the gate electrode 50 is: About 0.15 mm, the thickness of the electrode pads 60, 70, 80 is 0.3 mm, the thickness of the resin 90 on the side surface of the insulating substrate 10 is 0.6 mm, and the thickness of the resin 90 on the back surface of the insulating substrate 10 is 0. 1 mm, the length of the side of the opening of the resin 90 at the center of the back surface of the insulating substrate 10 is 1 to 4 mm, the thickness of the electrode pads 60, 70, 80 on the side surface of the insulating substrate 10 is about 0.7 mm, the electrode pad 60 The height from the upper surface of the resin 70, 80 to the upper surface of the resin 90 provided thereon is 0.3 mm.

[Semiconductor package manufacturing method]
The method of manufacturing this semiconductor package is basically the same as the method of manufacturing the semiconductor package according to the first embodiment.

[Specific Example of GaN-based FET]
Specific examples of the GaN-based FET are similar to the specific examples 1 and 2 of the semiconductor package according to the first embodiment, for example.

[Semiconductor package mounting method]
A method of mounting this semiconductor package will be described. Here, a case where a DBC substrate is used as the mounting substrate will be described.

As shown in FIG. 35, the semiconductor package 300 is mounted on the DBC substrate 200. Specifically, by patterning the Cu layer of the DBC substrate 200, the source wiring 210, the drain wiring 220, and the gate wiring 230 are formed, and at the same time, the electrode 260 is formed. The electrode 260 is formed smaller than this opening in a portion corresponding to the opening of the resin 90 in the central portion of the back surface of the insulating substrate 10 of the semiconductor package 300. On the source wiring 210, the drain wiring 220, the gate wiring 230, and the electrode 260, the conductive layer 500 made of a conductive paste containing nano Ag particles is formed. The conductive layer 500 has a thickness of 0.15 mm, for example. The semiconductor package 300 is mounted on this DBC substrate 200. That is, as shown in FIG. 35, electrodes that are respectively connected to the source electrode 30, the drain electrode 40, and the gate electrode 50 of the semiconductor package 300 at predetermined portions of the source wiring 210, the drain wiring 220, and the gate wiring 230 of the DBC substrate 200. The pads 60, 70, 80 are connected via the conductive layer 500. At the same time, the back surface of the insulating substrate 10 of the semiconductor package 300 is connected to the electrode 260 of the DBC substrate 200 via the conductive layer 500. The conductive layer 500 that contacts the back surface of the insulating substrate 10 is a heat conductive layer for conducting the heat generated in the operation of the semiconductor package 300 and transferred to the insulating substrate 10 to the electrode 260, and dissipating the heat by the DBC substrate 200. work.

[Module configuration example]
The semiconductor package 300 can be used to form modules similar to the modules 5 to 8, 10 and 11.

According to the fourth embodiment, the same advantages as those of the first embodiment can be obtained.

<5. Fifth Embodiment>
[Semiconductor package]
A semiconductor package according to the fifth embodiment will be described. Similar to the semiconductor package according to the first embodiment, this semiconductor package is also a GaN-based FET that is resin-sealed and has the same structure as the QFN package. A sectional view of this semiconductor package is shown in FIG. The plan view and bottom view (backside view) of this semiconductor package are similar to those shown in FIGS. FIG. 36 corresponds to a cross-sectional view taken along the line ZZ of FIG.

As shown in FIG. 36, in this semiconductor package, the thickness of the resin 90 on the semiconductor layer 20 and the electrode pads 60, 70, 80 is large, and the resin 90 extends from the side surface of the insulating substrate 10 to the peripheral portion of the back surface. An opening having a shape similar to that of the insulating substrate 10 formed by the resin 90 is formed in the central portion of the rear surface of the insulating substrate 10 extending in contact with the rear surface of the insulating substrate 10 inside the opening and the heat conduction layer. The semiconductor package has the same configuration as that of the semiconductor package according to the third embodiment except that the 750 is embedded. The heat conduction layer 750 is made of, for example, a conductive paste containing nano Cu particles. The thickness of this heat conduction layer 750 is, for example, 0.15 mm. Other configurations are similar to those of the third embodiment.

To give an example of the size of each part of this semiconductor package, the length of one side of the insulating substrate 10 is 2 to 5 mm, and the height from the back surface of the insulating substrate 10 to the upper surfaces of the source electrode 30, the drain electrode 40, and the gate electrode 50 is: About 0.15 mm, the thickness of the resin 90 below the electrode pads 60, 70, 80 is 0.3 mm, the thickness of the electrode pads 60, 70, 80 is 0.2 mm, the thickness of the resin 90 on the side surface of the insulating substrate 10. The thickness of the resin 90 on the side surface of the heat conduction layer 750 is 1.2 mm, and the height from the upper surface of the electrode pads 60, 70, 80 to the upper surface of the resin 90 provided thereon is 0. 8 mm, and the protruding length of the electrode pads 60, 70, 80 from the resin 90 is 0.6 mm.

[Semiconductor package manufacturing method]
The method of manufacturing this semiconductor package is basically the same as the method of manufacturing the semiconductor package according to the first embodiment. The heat conduction layer 750 can be formed as follows, for example. That is, after resin 90 is formed by resin molding so that an opening is formed in the central portion of the back surface of insulating substrate 10 on the lead frame, nano Cu particles are formed on the surface of the lead frame where the opening of resin 90 is exposed. The conductive paste containing the conductive paste is applied, and the unnecessary conductive paste is removed by a squeegee to leave the conductive paste only inside the opening of the resin 90. Then, the heat conductive layer 750 is formed by drying.

[Specific Example of GaN-based FET]
Specific examples of the GaN-based FET are similar to the specific examples 1 and 2 of the semiconductor package according to the first embodiment, for example.

[Semiconductor package mounting method]
A method of mounting this semiconductor package will be described. Here, a case where a DBC substrate is used as the mounting substrate will be described.

As shown in FIG. 37, the semiconductor package 300 is mounted on the DBC substrate 200. Specifically, by patterning the Cu layer of the DBC substrate 200, the SiN layer 200b of the mounting portion of the semiconductor package 300 is exposed and the source wiring 210, the drain wiring 220, and the gate wiring 230 are formed. On the source wiring 210, the drain wiring 220, the gate wiring 230, and the SiN layer 200b of the mounting portion of the semiconductor package 300, a conductive layer (not shown) made of a conductive paste containing nano Ag particles is formed. The semiconductor package 300 is mounted on this DBC substrate 200. That is, as shown in FIG. 37, electrodes connected to the source electrode 30, the drain electrode 40, and the gate electrode 50 of the semiconductor package 300, respectively, at predetermined portions of the source wiring 210, the drain wiring 220, and the gate wiring 230 of the DBC substrate 200. The pads 60, 70, 80 are connected via a conductive layer. The heat conduction layer 750 embedded in the opening of the resin 90 in the central portion of the insulating substrate 10 of the semiconductor package 300 is in contact with the SiN layer 200b via the conduction layer. The heat conductive layer 750 that contacts the back surface of the insulating substrate 10 transfers the heat generated during the operation of the semiconductor package 300 and transferred to the insulating substrate 10 to the SiN layer 200b via the conductive layer, and further to the Cu base substrate 200a. It is for conducting and radiating heat.

[Module configuration example]
The semiconductor package 300 can be used to form modules similar to the modules 5 to 8, 10 and 11.

According to the fifth embodiment, the same advantages as those of the first embodiment can be obtained.

<6. Sixth Embodiment>
[module]
In the sixth embodiment, a module in which a plurality of semiconductor packages according to the third embodiment are mounted on a metal substrate will be described.

FIG. 38 shows this module. As shown in FIG. 38, in this module, a plurality of semiconductor packages 300 according to the third embodiment are mounted on a metal substrate 800 as a base substrate. In this case, the back surface of the insulating substrate 10 of each semiconductor package 300 is in direct contact with the metal substrate 800. This metal substrate 800 is a heat dissipation substrate and, unlike a general mounting substrate, no wiring is formed. As the metal substrate 800, for example, a Cu substrate or an Al substrate is used, but the metal substrate 800 is not limited to this. By using the metal substrate 800 as the heat dissipation substrate, it is possible to minimize the thermal resistance when dissipating the heat generated from the semiconductor package 300. On the electrode pads 60, 70, 80 of the two semiconductor packages 300 in FIG. 38, a predetermined wiring 810 is connected via a conductive layer 500 made of Ag paste or the like laminated in two stages. The wiring 810 is typically formed by a lead frame method. The wiring 810 is provided on the upper surface of the resin 90 of the semiconductor package 300 via the conductive layer 500. A gap between the metal substrate 800, the semiconductor package 300, and the wiring 810 and a gap between the wirings 810 are sealed with a resin 820. Terminals 830 and 840 are provided at one end and the other end of the wiring 810.

[Module configuration example]
FIG. 39A is a circuit diagram showing a module 12 having a cascode circuit configured by using four semiconductor packages according to the third embodiment, one commercially available SiMOS transistor SOS package, and four reverse connection protection diodes, FIG. 39B shows a configuration example of this module 12. In the semiconductor package according to the third embodiment, when the power polarization super-junction GaN-based FETs of the first and second embodiments are used as the semiconductor chip C, body diodes are included in these power polarization super-junction GaN-based FETs. The reverse connection protection diode is not always necessary because it is provided. As shown in FIG. 39B, in this module 12, four semiconductor packages 300 are connected in parallel in order to increase the current of the cascode circuit. Four reverse connection protection diodes 900 are connected in parallel between the pad electrode 70 of the semiconductor package 300 and the source terminals 601 and 602 of the SiMOS transistor SOS package 600 connected in parallel. As shown in FIG. 40, the reverse connection protection diode 900 is formed by omitting the formation of the electrode pad 80 connected to the gate electrode 50 in the semiconductor package 300 according to the third embodiment, and the drain electrode 40 serves as an anode. The electrode and the source electrode 30 are used as the cathode electrode. As shown in FIG. 39B, the pad electrodes 60, 70, 80 of the four semiconductor packages 300, the source terminals 601, 602, the drain terminals 603, 604, 605 and the gate terminals 606 of the SiMOS transistor SOS package 600 and the reverse connection protection diode. The wiring of the electrode pads 70 and 60 connected to the drain electrode 40 and the source electrode 30 used as the anode electrode and the cathode electrode of 900 is preferably a wiring 810 formed by a lead frame method, and contacts from above. doing.

According to the sixth embodiment, the same advantages as those of the first embodiment can be obtained, and the following advantages can be obtained. That is, in the sixth embodiment, the semiconductor package 300 is mounted on the metal substrate 800 as the base substrate, and the wiring 810 for wiring them is provided on the upper portion thereof. In other words, the metal substrate 800 as the base substrate and the device portion thereon are completely separated. Therefore, the module design is easy. Further, since the metal substrate 800 used as the heat dissipation substrate generally has high thermal conductivity and good heat dissipation, the thermal resistance can be minimized.

<7. Seventh Embodiment>
[module]
In the seventh embodiment, a module in which a plurality of semiconductor packages according to the third embodiment are mounted on a metal substrate will be described.

Figure 41 shows this module. As shown in FIG. 41, in this module, a plurality of semiconductor packages 300 according to the third embodiment are mounted on a metal substrate 800 as a base substrate, and wirings 810 are provided on these semiconductor packages 300. The connection is the same as in the sixth embodiment. In this module, a predetermined second-layer wiring 850 is further provided on the wiring 810. The second-layer wiring 850 is connected to a predetermined portion of the first-layer wiring 810 via a conductive layer 500 made of Ag paste or the like that is two-tiered. A terminal 860 is provided over the wiring 850. If necessary, one or more passive components or active components (not shown) are connected to the second-layer wiring 850 shown in FIG. 41 or a wiring not shown. The passive component is, for example, a capacitor, and the active component is, for example, a driver or a cascode SiMOS transistor. Others of this module are the same as those of the sixth embodiment.

According to the seventh embodiment, the same advantages as those of the first and sixth embodiments can be obtained.

<8. Eighth embodiment>
[module]
In the eighth embodiment, a module in which a plurality of semiconductor packages according to the third embodiment are mounted on a metal substrate will be described.

FIG. 42 shows this module. As shown in FIG. 42, in this module, a plurality of semiconductor packages 300 according to the third embodiment are mounted on a metal substrate 800 as a base substrate, and wiring 810 is provided on these semiconductor packages 300. The connection and the provision of a predetermined second-layer wiring 850 on the wiring 810 are the same as in the seventh embodiment. This module differs from the seventh embodiment in that the wiring 810 and the wiring 850 are formed on the lower surface and the upper surface of the two-layer flexible polyimide substrate 910, respectively. That is, the wiring 810 is formed by patterning the lower Cu layer of the two-layer flexible polyimide substrate 910, and the wiring 850 is formed by patterning the upper Cu layer of the two-layer flexible polyimide substrate 910. is there. The wiring 850 is connected to the wiring 810 in the lower layer via a through hole 912 formed in the flexible polyimide substrate 911. In this case, the gap between the metal substrate 800, the semiconductor package 300, and the wiring 810 and the gap between the wirings 810 are made of an insulating layer 920 formed of a filler made of an electrically insulating material such as silica (SiO ₂ ) or an organic substance. Buried by. The terminal 860 provided on the wiring 850 in the seventh embodiment is not provided. Similar to the seventh embodiment, one or more passive components or active components (not shown) may be provided in the second-layer wiring 850 shown in FIG. 42 or the wiring not shown in the drawing, if necessary. Are connected. In practice, for example, the one in which the semiconductor package 300 is mounted on the wiring 810 of the two-layer flexible polyimide substrate 910 is placed on the metal substrate 800 so that the back surface of the insulating substrate 10 of the semiconductor package 300 contacts the metal substrate 800. It can be pasted. Others of this module are the same as those of the sixth embodiment.

According to the eighth embodiment, the same advantages as those of the first and seventh embodiments can be obtained.

<9. Ninth Embodiment>
[module]
In the ninth embodiment, a module in which a plurality of semiconductor packages according to the third embodiment and bare GaN-based semiconductor chips are mounted on a metal substrate will be described.

FIG. 43 shows this module. In this module, a plurality of semiconductor packages 300 according to the third embodiment are mounted on a metal substrate 800 as a base substrate as in the eighth embodiment, but the illustration thereof is omitted. As shown in FIG. 43, similar to the eighth embodiment, the wiring 810 is formed by patterning the lower Cu layer of the two-layer flexible polyimide substrate 910, and the Cu layer of the upper layer of the two-layer flexible polyimide substrate 910 is formed. The wiring 850 is formed by patterning. The wiring 810 is connected to the pad electrodes 60, 70, 80 of the semiconductor package 300 (not shown). In this module, further, a three-terminal semiconductor element, in particular, a semiconductor chip C formed with the polarization superjunction GaN-based FET described above as specific examples 1 and 2 of the GaN-based FET is mounted. The semiconductor chip C has the same structure as the semiconductor chip C of the semiconductor package 300. The back surface of the insulating substrate 10 of the semiconductor chip C is in direct contact with the metal substrate 800. The source electrode 30, the drain electrode 40, and the gate electrode 50 of this semiconductor chip C are connected to the wiring 810 formed on the lower surface of the two-layer flexible polyimide substrate 910. A passive component 930 such as a capacitor is mounted on the wiring 850 in the upper layer of the two-layer flexible polyimide substrate 910, terminals 931 and 932 of the passive component 930 are connected to the wiring 850, and an active component such as a driver or a cascode SiMOS transistor. 940 is mounted, and its terminals 941 and 942 are connected to the wiring 850. A gap between the metal substrate 800, the semiconductor package 300, the semiconductor chip C, and the wiring 810 and a gap between the wirings 810 are filled with an insulating layer 920 formed of a filler made of an electrically insulating material such as silica or an organic substance. Has been. In reality, for example, the semiconductor package 300 and the semiconductor chip C are mounted on the wiring 810 of the two-layer flexible polyimide substrate 910, and the passive component 930 and the active component 940 are mounted on the wiring 850. The back surface of the insulating substrate 10 and the back surface of the insulating substrate 10 of the semiconductor chip C are attached on the metal substrate 800 so as to be in contact with the metal substrate 800. Others of this module are the same as those of the eighth embodiment.

According to the ninth embodiment, the same advantages as those of the first and seventh embodiments can be obtained, and an IPM (integrated power module) having particularly good heat dissipation characteristics can be easily realized as a module. The advantage that can be obtained can be obtained.

<10. Tenth Embodiment>
[module]
In the tenth embodiment, a semiconductor package according to the third embodiment and a module in which a plurality of GaN-based semiconductor chips that are bare chips are mounted on a metal substrate will be described.

FIG. 44 shows this module. In this module, a heat dissipation sapphire substrate 950 is provided between the wiring 810 formed on the lower surface of the two-layer flexible polyimide substrate 910 and the metal substrate 800. The back surface of the heat dissipation sapphire substrate 950 is in direct contact with the metal substrate 800. An electrode 960 is provided on the surface of the heat dissipation sapphire substrate 950, and the electrode 960 is connected to the wiring 810. The heat generated from the GaN-based semiconductor chip C or the like during the operation of this module is efficiently conducted to the metal substrate 800 via the wiring 810, the electrode 960 and the heat dissipation sapphire substrate 950, and is radiated from the metal substrate 800. Others of this module are the same as those of the ninth embodiment.

According to the tenth embodiment, the same advantages as those of the first, seventh and ninth embodiments can be obtained.

<11. Eleventh Embodiment>
[Semiconductor package]
A semiconductor package according to the eleventh embodiment will be described. This semiconductor package is a CSP (chip size package). Similar to the semiconductor package according to the first embodiment, this semiconductor package is also a GaN-based FET resin-sealed. This semiconductor package is shown in FIGS. 45 is a plan view, FIG. 46 is a bottom view (rear view), FIG. 47 is a sectional view taken along line XX of FIG. 45, and FIG. 48 is a sectional view taken along line YY of FIG. is there.

As shown in FIG. 45 to FIG. 48, this semiconductor package has a flat rectangular parallelepiped shape as a whole having a substantially square planar shape. In this semiconductor package, a semiconductor chip C similar to that of the first embodiment is resin-sealed. The source electrode 30 and the drain electrode 40 are typically formed in a comb structure, and an example of that case is shown in FIG. 49.

Electrode pads 60, 70, and 80 are electrically connected to the source electrode 30, the drain electrode 40, and the gate electrode 50, respectively, through a conductive layer 500 made of a conductive paste or solder containing nano Ag particles. .. A resin 90 that is electrically insulative between the surface of the semiconductor layer 20, the source electrode 30, the gate electrode 50, and the like and the side surfaces of the insulating substrate 10 and the semiconductor layer 20 that are not covered with the electrode pads 60, 70, 80. It is covered and sealed by. The contour of the resin 90 is larger than the size of the semiconductor chip C by the thickness of the resin 90 on the side surface of the semiconductor chip C, but is substantially similar to the outer shape of the semiconductor chip C. The electrode pad 60 connected to the source electrode 30 extends in parallel with the source electrode 30, and has a linear lower portion 60a having a width equal to that of the source electrode 30 and both sides thereof across the side S ₁ of the semiconductor layer 20. And a flat plate-shaped upper portion 60b having a rectangular planar shape extending in parallel with the semiconductor layer 20. In other words, in the electrode pad 60, after the lower portion 60a is pulled out vertically upward from the source electrode 30 with respect to the semiconductor layer 20, the upper portion 60b extends above the semiconductor layer 20 in parallel with the semiconductor layer 20. The lower portion 60a of the electrode pad 60 is displaced in the width direction of the source electrode 30 with respect to the source electrode 30, and one side portion on the center side of the semiconductor package is provided with the conductive layer 500 formed on the upper surface of the lower portion 60a. It is electrically connected to the source electrode 30. The electrode pad 60 is provided so as to cover the source electrode 30 except for one end of the source electrode 30 on the gate electrode 50 side. The electrode pad 70 connected to the drain electrode 40 extends in parallel with the drain electrode 40 and has a linear lower portion 70 a having the same width as the drain electrode 40 and both sides of the linear lower portion 70 a across the side S ₃ of the semiconductor layer 20. And a flat plate-shaped upper portion 70b having a rectangular planar shape extending in parallel with the semiconductor layer 20. In other words, in the electrode pad 70, after the lower portion 70a is pulled out vertically from the drain electrode 40 with respect to the semiconductor layer 20, the upper portion 70b extends above the semiconductor layer 20 in parallel with the semiconductor layer 20. The lower portion 70a of the electrode pad 70 is displaced in the width direction of the drain electrode 40 with respect to the drain electrode 40, and one side portion on the center side of the semiconductor package is provided with the conductive layer 500 formed on the upper surface of the lower portion 70a. It is electrically connected to the drain electrode 40. The electrode pad 70 is provided so as to cover the entire drain electrode 40. The electrode pad 80 connected to the gate electrode 50 extends in parallel with the gate electrode 50 and has a linear lower portion 80a having the same width as the gate electrode 50 and both sides of the linear lower portion 80a straddling the side S ₄ of the semiconductor layer 20. And a flat plate-shaped upper portion 80b having a rectangular planar shape extending in parallel with the semiconductor layer 20. In other words, in the electrode pad 80, after the lower portion 80a is drawn out vertically upward from the gate electrode 50 with respect to the semiconductor layer 20, the upper portion 80b extends above the semiconductor layer 20 in parallel with the semiconductor layer 20. The lower portion 80a of the electrode pad 80 is displaced in the width direction of the gate electrode 50 with respect to the gate electrode 50, and one side portion on the center side of the semiconductor package is provided with the conductive layer 500 formed on the upper surface of the lower portion 80a. It is electrically connected to the gate electrode 50. The electrode pad 80 is provided so as to cover the entire gate electrode 50.

To give an example of the size of each part of this semiconductor package, the length of one side of the insulating substrate 10 is 2 to 5 mm, and the height from the back surface of the insulating substrate 10 to the upper surfaces of the source electrode 30, the drain electrode 40, and the gate electrode 50 is: About 0.12 mm, the lower portions 60a, 70a, 80a of the electrode pads 60, 70, 80 have a thickness of about 0.15 mm, the upper portions 60b, 70b, 80b have a thickness of about 0.2 mm, the electrode pad 60 and the electrode pad 70. And the width of the source electrode 30, the drain electrode 40 and the gate electrode 50, and thus the width of the lower portions 60a, 70a, 80a of the electrode pads 60, 70, 80 is about 0.15 mm.

[Semiconductor package manufacturing method]
50A-D, 51A-B, and 52A-C show an example of a method of manufacturing this semiconductor package.

As shown in FIG. 50A, first, a metal plate 100 for forming a lead frame is prepared. The metal plate 100 is selected from conventionally known materials as necessary, and is, for example, a Cu alloy or a Fe—Ni-based alloy. On the metal plate 100, a conductive layer 500 made of a conductive paste or solder containing nano Ag particles is formed.

Next, as shown in FIG. 50B, by pressing, the metal plate 100 and the conductive layer 500 are formed into a predetermined repeating pattern corresponding to the semiconductor package to be manufactured, and a contour slightly larger than the contours of the electrode pads 60, 70, 80. Punch partially to form.

Next, as shown in FIG. 50C, a step is partially formed on the metal plate 100 by press working so that portions corresponding to the lower portions 60a, 70a, 80a of the electrode pads 60, 70, 80 are formed. ..

Next, as shown in FIG. 50D, the metal plate 100 is partially punched by pressing so that the contours of the electrode pads 60, 70, 80 are formed, and the lead frame 110 having a predetermined shape is formed. The planar shape of this lead frame 110 is shown in FIG. However, FIG. 53 is a plan view of the lead frame 110 shown in FIG. 50D when viewed from below. FIG. 50D is a cross-sectional view taken along the line DD of FIG. In FIG. 53, the outline of the finally manufactured semiconductor package is shown by a one-dot chain line.

Next, as shown in FIG. 51A, the source electrode 30, the drain electrode 40, and the gate electrode 50 of the semiconductor chip C are directed downward, and the lower portions 60a, 70a, 80a of the electrode pads 60, 70, 80 of the lead frame 110 are respectively directed. After being brought into contact with the conductive layer 500 on the surface of a portion corresponding to, a heat treatment is performed to join the layers.

Next, as shown in FIG. 51B, the upper and lower sides of the structure shown in FIG. 51A are sandwiched by thick plates 971 and 972. The thick plates 971 and 972 are not particularly limited, but for example, a glass plate or a metal plate such as stainless steel can be used.

Next, as shown in FIG. 52A, resin molding is performed so as to fill the space formed between the thick plates 971 and 972, and the semiconductor chip C is sealed with the resin 90.

Next, as shown in FIG. 52B, the thick plates 971 and 972 are removed.

After that, the lead frame 110 is cut along a predetermined cutting line shown by a two-dot chain line in FIG. 52B, and separated as shown in FIG. 52C. Thus, the intended semiconductor package shown in FIGS. 45 to 48 is manufactured.

[Semiconductor package mounting method]
A method of mounting this semiconductor package will be described. Here, a module in which this semiconductor package is mounted on a metal substrate will be described.

FIG. 54 shows this module. As shown in FIG. 54, in this module, a plurality of semiconductor packages shown in FIGS. 45 to 48 are mounted on a metal substrate 800 as a base substrate, and an electrode 960 is provided on a heat dissipation sapphire substrate 950. The provided heat dissipation dummy element is mounted with the heat dissipation sapphire substrate 950 facing downward. The back surface of the heat dissipation sapphire substrate 950 is in direct contact with the metal substrate 800. The total thickness of the heat dissipation sapphire substrate 950 and the electrodes 960 is selected to be equal to the thickness of the semiconductor package. The side surface of the heat dissipation sapphire substrate 950 is covered with an electrically insulating resin 90 and sealed. A double-sided printed wiring board 980 made of epoxy resin is provided on the semiconductor package and the heat dissipation dummy element. The wiring 981 formed on the lower surface of the double-sided printed wiring board 980 and the electrode pads 60, 70 of the semiconductor package, 80 and the electrode 960 of the heat dissipation dummy element are electrically connected via the conductive layer 500. A resist mask 982 is provided on the lower surface of the double-sided printed wiring board 980 and the surface of the wiring 981 exposed in the portion between the wirings 981. In this case, the gap between the metal substrate 800 and the double-sided printed wiring board 980 is filled with an insulating layer 920 formed of a filler made of an electrically insulating material such as SiO ₂ or an organic material. Wirings 983 are formed on the upper surface of the double-sided printed wiring board 980. A resist mask 984 is provided on the upper surface of the double-sided printed wiring board 980 and the surface of the wiring 983 exposed in the portion between the wirings 983. A passive component 930 such as a capacitor and an active component 940 such as a driver and a cascode SiMOS transistor are mounted on the wiring 983 on the upper surface of the double-sided printed wiring board 980. The terminals 931 and 932 of the passive component 930 are connected to the wiring 983. The terminals 941 and 942 of the active component 940 are connected to the wiring 983. Through-hole wiring 985 is formed on the double-sided printed wiring board 980, and the wiring 981 on the lower surface and the wiring 983 on the upper surface of the double-sided printed wiring board 980 are connected to each other by the through-hole wiring 985. Further, embedded wiring 986 is formed on the double-sided printed wiring board 980. The embedded wiring 986 connects the passive components 930 to each other. The double-sided printed wiring board 980 further has a through hole 987 formed in a portion between the active component 940 and the heat dissipation dummy element, and a high thermal conductive filler 988 such as AlN is embedded in the through hole 987.

According to the eleventh embodiment, most of the electrode pads 60, 70, 80 are formed on the semiconductor layer 20 of the semiconductor chip C and only slightly protrude from the semiconductor chip C. The semiconductor package can be configured. The semiconductor chip C of this semiconductor package is mounted with the insulating substrate 10 side facing the metal substrate 800, and the electrode pads 60, 70, 80 are connected to the wiring 981 formed on the lower surface of the double-sided printed wiring board 980. As a result, the GaN-based FET can be easily mounted face-up on the metal substrate 800, and the cost, the frequency, the volume, and the thermal resistance can be significantly reduced as compared with the related art. Moreover, since the source electrode 30, the drain electrode 40, and the gate electrode 50 are arranged in a triangle, and therefore the electrode pads 60, 70, and 80 can also be arranged in a triangle, the wiring 981 formed on the lower surface of the double-sided printed wiring board 980 is formed. Since they can be formed so as not to cross each other, a high-performance module having a semiconductor package mounted thereon can be easily realized. By using this module, high-performance electric equipment can be realized at low cost.

<12. Twelfth Embodiment>
[Semiconductor package]
A semiconductor package according to the twelfth embodiment will be described. This semiconductor package integrates two CSPs, one CSP is a semiconductor package according to the eleventh embodiment in which a GaN-based FET is resin-sealed, and the other CSP is a GaN-based diode is resin-sealed. It has stopped.

FIG. 55 shows a circuit of this semiconductor package. As shown in FIG. 55, in this semiconductor package, the drain of the GaN-based FET is connected to the cathode of the GaN-based diode to form an inverter.

56A to C show this semiconductor package, FIG. 56A is a plan view, FIG. 56B is a bottom view, and FIG. 56C is a sectional view taken along the line CC of FIG. 56A. As shown in FIGS. 56A to 56C, this semiconductor package is a CSP-shaped semiconductor package P _{1 in} which a GaN-based FET is resin-sealed and a CSP-shaped semiconductor in which a GaN-based diode is resin-sealed. The package P ₂ and the package P ₂ are joined to each other on one side surface, and have a rectangular parallelepiped shape in plan view as a whole. Here, the GaN-based diode is formed by omitting the formation of the electrode pad 80 connected to the gate electrode 50 in the semiconductor package according to the eleventh embodiment, and the drain electrode 40 is the anode electrode and the source electrode 30 is the cathode electrode. As the electrode pads, only the electrode pads 60 and 70 are formed. An electrode pad 70 and the electrode pads 60 of the semiconductor package P ₂ of the semiconductor package P ₁ is in contact their side faces to each other are electrically connected.

According to the twelfth embodiment, a CSP type semiconductor package having a circuit configuration as shown in FIG. 55 can be realized.

<13. Thirteenth Embodiment>
[Semiconductor package]
A semiconductor package according to the thirteenth embodiment will be described. This semiconductor package is one in which four CSPs are integrated, two CSPs are semiconductor packages according to the eleventh embodiment in which a GaN-based FET is resin-sealed, and the remaining two CSPs are GaN-based diodes are resin-sealed. It is sealed.

FIG. 57 shows a circuit of this semiconductor package. As shown in FIG. 57, in this semiconductor package, the cathodes of two GaN-based diodes connected in parallel are connected to the drains of two GaN-based FETs connected in parallel to form an inverter.

58A and B show this semiconductor package, FIG. 58A is a plan view, and FIG. 58B is a bottom view. As shown in FIGS. 58A and 58B, this semiconductor package is a CSP-shaped semiconductor package P ₁₁ or P ₁₂ according to the eleventh embodiment in which a GaN-based FET is resin-sealed and a CSP in which a GaN-based diode is resin-sealed. The semiconductor packages P ₁₃ and P ₁₄ having a rectangular shape are joined to each other at the side surfaces, and have a flat rectangular parallelepiped shape as a whole in a substantially square planar shape. Here, the GaN-based diode is formed by omitting the formation of the electrode pad 80 connected to the gate electrode 50 in the semiconductor package according to the eleventh embodiment, and the drain electrode 40 is the anode electrode and the source electrode 30 is the cathode electrode. As the electrode pads, only the electrode pads 60 and 70 are formed. The side surfaces of the electrode pad 70 of the semiconductor package P _{11 and} the electrode pad 60 of the semiconductor package P ₁₃ are in contact with each other and are electrically connected. An electrode pad 70 and the electrode pads 60 of the semiconductor package P ₁₄ of the semiconductor package P ₁₂ is in contact their side faces to each other are electrically connected. The side surfaces of the electrode pad 80 of the semiconductor package P _{11 and} the electrode pad 80 of the semiconductor package P ₁₂ are in contact with each other and are electrically connected.

According to the thirteenth embodiment, a CSP type semiconductor package having a circuit configuration as shown in FIG. 57 can be realized.

<14. Fourteenth Embodiment>
[Semiconductor package]
A semiconductor package according to the fourteenth embodiment will be described. This semiconductor package is one in which four CSPs are integrated, two CSPs are semiconductor packages according to the eleventh embodiment in which a GaN-based FET is resin-sealed, and the remaining two CSPs are GaN-based diodes are resin-sealed. It is sealed.

FIG. 59 shows a circuit of this semiconductor package. As shown in FIG. 59, in this semiconductor package, the anodes of two GaN-based diodes connected in parallel are connected to the drains of two GaN-based FETs connected in parallel to form a DC/DC up-converter. There is.

FIG. 60 is a plan view showing this semiconductor package. As shown in FIG. 60, this semiconductor package is a CSP type semiconductor package P ₂₁ , P ₂₂ according to the eleventh embodiment in which a GaN type FET is resin-sealed and a CSP type semiconductor package in which a GaN type diode is resin sealed. The semiconductor packages P ₂₃ and P ₂₄ are joined to each other at their side surfaces, and have a flat rectangular parallelepiped shape as a whole in a plan view having a substantially square shape. Here, the GaN-based diode is formed by omitting the formation of the electrode pad 80 connected to the gate electrode 50 in the semiconductor package according to the eleventh embodiment, and the drain electrode 40 is the anode electrode and the source electrode 30 is the cathode electrode. As the electrode pads, only the electrode pads 60 and 70 are formed. The side surfaces of the electrode pad 70 of the semiconductor package P _{21 and} the electrode pad 70 of the semiconductor package P ₁₃ are in contact with each other and are electrically connected. The side surfaces of the electrode pad 70 of the semiconductor package P _{22 and} the electrode pad 70 of the semiconductor package P ₂₄ are in contact with each other and are electrically connected. The side surfaces of the electrode pad 80 of the semiconductor package P _{21 and} the electrode pad 80 of the semiconductor package P ₂₂ are in contact with each other and are electrically connected.

According to the fourteenth embodiment, it is possible to realize a CSP type semiconductor package having a circuit configuration as shown in FIG.

The embodiments of the present invention have been specifically described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made based on the technical idea of the present invention.

For example, the numerical values, structures, shapes, materials, etc. mentioned in the above-mentioned embodiments are merely examples, and numerical values, structures, shapes, materials, etc. different from these may be used if necessary.

Although the semiconductor package 300 and the semiconductor chip C are mounted on the metal substrate 800 in the ninth and tenth embodiments, the semiconductor package 300 is mounted on the wiring 810 of the two-layer flexible polyimide substrate 910. It is also possible to mount only the semiconductor chip C, which is a bare chip, on the metal substrate 800 without mounting. In this case, the semiconductor chip C is mounted on the wiring 810 of the two-layer flexible polyimide substrate 910, and the passive component 930 and the active component 940 are mounted on the wiring 850. However, the back surface of the insulating substrate 10 of the semiconductor chip C is metal. The metal substrate 800 is attached so as to be in contact with the substrate 800. By doing so, it is possible to easily realize an IPM having good heat dissipation characteristics.

Further, in the semiconductor package according to the present invention, a three-terminal semiconductor element having a horizontal structure is resin-sealed. However, a structure similar to this semiconductor package is a two-terminal semiconductor element (diode) or four terminals having a horizontal structure. It can also be applied to the case where the above semiconductor element is resin-sealed.

10... Insulating substrate, 20... Semiconductor layer, 30... Source electrode, 40... Drain electrode, 50... Gate electrode, 60, 70, 80... Pad electrode, 90... Resin, C... Semiconductor chip, 100... Metal plate, 110... Lead frame, 200... DBC substrate, 200a... Cu base substrate, 200b... SiN layer, 300... Semiconductor package, 400... Si chip, 500... Conductive layer, 600... SiMOS transistor SOS package, 800... Metal substrate, 900... Reverse connection Protecting diode, 910... Two-layer flexible polyimide substrate, 930... Passive component, 940... Active component, 950... Heat dissipation sapphire substrate

Claims (15)

A semiconductor package used between being provided between one main surface of a metal substrate and one main surface of a double-sided printed wiring board,
The semiconductor package is
A semiconductor layer forming a three-terminal semiconductor element is provided on the first main surface of the sapphire substrate, and the first electrode, the second electrode, and the third electrode are arranged in a triangular shape on the semiconductor layer to form a rectangular planar shape. A semiconductor chip having
A first electrode pad, a second electrode pad, and a third electrode pad that are brought into contact with the first electrode, the second electrode, and the third electrode to be electrically connected to each other and are drawn out of the semiconductor layer;
An electrically insulating resin that seals the side surfaces of the first electrode, the second electrode, the third electrode, the semiconductor layer, and the sapphire substrate,
Have
The four sides of the semiconductor chip are sequentially counter-clockwise S ₁ , S ₂ , S ₃ , S _Four And the first electrode is the side S ₁ Long side parallel to and side S ₂ Has an elongated rectangular shape having a short side parallel to ₁ , S ₂ The length of the long side of the first electrode is close to the side S ₁ Shorter than the length of the second electrode, ₃ Long side parallel to and side S ₂ Has an elongated rectangular shape having a short side parallel to ₂ , S ₃ Is provided close to the second electrode, and the length of the long side of the second electrode is the side S ₃ Shorter than the length of the third electrode, _Four Long side parallel to and side S ₁ Has a rectangular shape having a short side parallel to the first electrode and the side S _Four Edge S in the area between ₁ , S _Four Is installed close to
The first electrode pad is a side S from the first electrode via the resin. ₁ Projecting in a direction perpendicular to, and in a direction parallel to the semiconductor layer and the sapphire substrate, and the tip of the projecting first electrode pad has a side S. ₁ And the second electrode pad is parallel to the side S from the second electrode via the resin. ₃ Projecting in a direction perpendicular to, and parallel to the semiconductor layer and the sapphire substrate, and the tip of the projecting second electrode pad has a side S. ₃ And the third electrode pad is parallel to the side S from the third electrode via the resin. _Four Projecting in a direction perpendicular to, and in a direction parallel to the semiconductor layer and the sapphire substrate, the tip of the projecting third electrode pad has a side S. _Four Parallel to
The semiconductor package is mounted on the one main surface of the metal substrate with the second main surface of the sapphire substrate in contact with the one main surface of the metal substrate, the first electrode pad, the second Surfaces of the electrode pads and the third electrode pads, which are opposite to the sapphire substrate, of the portions protruding from the resin are electrically connected to predetermined portions of predetermined wiring on the one main surface of the double-sided printed wiring board. A semiconductor package characterized by comprising a predetermined circuit. A semiconductor package used between being provided between one main surface of a metal substrate and one main surface of a double-sided printed wiring board,
The semiconductor package is
A semiconductor layer forming a three-terminal semiconductor element is provided on the first main surface of the sapphire substrate, and the first electrode, the second electrode, and the third electrode are arranged in a triangular shape on the semiconductor layer to form a rectangular planar shape. A semiconductor chip having
A first electrode pad, a second electrode pad, and a third electrode pad that are brought into contact with and electrically connected to the first electrode, the second electrode, and the third electrode, respectively, and are drawn out above the semiconductor layer;
An electrically insulating resin that seals the side surfaces of the first electrode, the second electrode, the third electrode, the semiconductor layer, and the sapphire substrate,
Have
The four sides of the semiconductor chip are sequentially counter-clockwise S ₁ , S ₂ , S ₃ , S _Four And the first electrode is the side S ₁ Long side parallel to and side S ₂ Has an elongated rectangular shape having a short side parallel to ₁ , S ₂ Is provided close to the first electrode, and the length of the long side of the first electrode is the side S ₁ Shorter than the length of the second electrode, ₃ Long side parallel to and side S ₂ Has an elongated rectangular shape having a short side parallel to ₂ , S ₃ Is provided close to the second electrode, and the length of the long side of the second electrode is the side S ₃ Shorter than the length of the third electrode, _Four Long side parallel to and side S ₁ Has a rectangular shape having a short side parallel to the first electrode and the side S _Four Edge S in the area between ₁ , S _Four Is installed close to
After the first electrode pad is vertically upwardly drawn from the first electrode with respect to the semiconductor layer, a side S ₁ Extending over the semiconductor layer in parallel with the semiconductor layer so as to straddle the semiconductor layer, and the outer tip of the first electrode pad has a side S ₁ The second electrode pad is parallel to the first electrode pad, and the second electrode pad is vertically upwardly drawn from the second electrode with respect to the semiconductor layer. ₃ So as to extend over the semiconductor layer in parallel to the semiconductor layer, and the outer tip of the second electrode pad has a side S ₃ And the third electrode pad is vertically upwardly drawn from the third electrode with respect to the semiconductor layer, and then the side S _Four Extending over the semiconductor layer in parallel to the semiconductor layer so as to straddle the semiconductor layer, and the outer tip of the third electrode pad has a side S _Four Parallel to
The contour of the resin is larger than the semiconductor chip by the thickness of the resin on the side surface of the semiconductor chip, but is substantially similar to the outer shape of the semiconductor chip,
The tip of the first electrode pad, the tip of the second electrode pad, and the tip of the third electrode pad match the contour of the resin,
The semiconductor package is mounted on the one main surface of the metal substrate with the second main surface of the sapphire substrate in contact with the one main surface of the metal substrate, the first electrode pad, the second Surfaces of the electrode pad and the third electrode pad opposite to the sapphire substrate are electrically connected to predetermined portions of predetermined wiring on the one main surface of the double-sided printed wiring board to form a predetermined circuit. A semiconductor package characterized by the following. The semiconductor package according to claim 1, wherein the semiconductor layer is a GaN-based semiconductor layer, and the three-terminal semiconductor element is a GaN-based field effect transistor. The semiconductor package according to claim 3, wherein the GaN-based field effect transistor is a polarized superjunction GaN-based field effect transistor. The semiconductor package according to claim 3, wherein the first electrode is a source electrode, the second electrode is a drain electrode, and the third electrode is a gate electrode. A metal substrate,
One or more semiconductor packages mounted on one main surface of the metal substrate;
A double-sided printed wiring board having a predetermined wiring provided on one main surface so as to form a predetermined circuit on the one or more semiconductor packages;
The semiconductor package is
A semiconductor layer forming a three-terminal semiconductor element is provided on the first main surface of the sapphire substrate, and the first electrode, the second electrode, and the third electrode are arranged in a triangular shape on the semiconductor layer to form a rectangular planar shape. A semiconductor chip having
A first electrode pad, a second electrode pad, and a third electrode pad that are brought into contact with the first electrode, the second electrode, and the third electrode to be electrically connected to each other and are drawn out of the semiconductor layer;
An electrically insulating resin that seals the side surfaces of the first electrode, the second electrode, the third electrode, the semiconductor layer, and the sapphire substrate,
Have
The four sides of the semiconductor chip are sequentially counter-clockwise S ₁ , S ₂ , S ₃ , S _Four And the first electrode is the side S ₁ Long side parallel to and side S ₂ Has an elongated rectangular shape having a short side parallel to ₁ , S ₂ Is provided close to the first electrode, and the length of the long side of the first electrode is the side S ₁ Shorter than the length of the second electrode, ₃ Long side parallel to and side S ₂ Has an elongated rectangular shape having a short side parallel to ₂ , S ₃ Is provided close to the second electrode, and the length of the long side of the second electrode is the side S ₃ Shorter than the length of the third electrode, _Four Long side parallel to and side S ₁ Has a rectangular shape having a short side parallel to the first electrode and the side S _Four Edge S in the area between ₁ , S _Four Is installed close to
The first electrode pad is a side S from the first electrode via the resin. ₁ Projecting in a direction perpendicular to, and in a direction parallel to the semiconductor layer and the sapphire substrate, and the tip of the projecting first electrode pad has a side S. ₁ And the second electrode pad is parallel to the side S from the second electrode via the resin. ₃ Projecting in a direction perpendicular to, and parallel to the semiconductor layer and the sapphire substrate, and the tip of the projecting second electrode pad has a side S. ₃ And the third electrode pad is parallel to the side S from the third electrode via the resin. _Four Projecting in a direction perpendicular to, and in a direction parallel to the semiconductor layer and the sapphire substrate, the tip of the projecting third electrode pad has a side S. _Four Parallel to
The semiconductor package is mounted on the one main surface of the metal substrate with the second main surface of the sapphire substrate in contact with the one main surface of the metal substrate, the first electrode pad, the second Surfaces of the electrode pads and the third electrode pads, which are opposite to the sapphire substrate, of the portions projecting from the resin are electrically connected to predetermined portions of the predetermined wiring on the one main surface of the double-sided printed wiring board. A module in which the predetermined circuit is configured. A metal substrate,
One or more semiconductor packages mounted on one main surface of the metal substrate;
A double-sided printed wiring board having a predetermined wiring provided on one main surface so as to form a predetermined circuit on the one or more semiconductor packages;
The semiconductor package is
A semiconductor layer forming a three-terminal semiconductor element is provided on the first main surface of the sapphire substrate, and the first electrode, the second electrode, and the third electrode are arranged in a triangular shape on the semiconductor layer to form a rectangular planar shape. A semiconductor chip having
A first electrode pad, a second electrode pad, and a third electrode pad that are brought into contact with and electrically connected to the first electrode, the second electrode, and the third electrode, respectively, and are drawn out above the semiconductor layer;
An electrically insulating resin that seals the side surfaces of the first electrode, the second electrode, the third electrode, the semiconductor layer, and the sapphire substrate,
Have
The four sides of the semiconductor chip are sequentially counter-clockwise S ₁ , S ₂ , S ₃ , S _Four And the first electrode is the side S ₁ Long side parallel to and side S ₂ Has an elongated rectangular shape having a short side parallel to ₁ , S ₂ Is provided close to the first electrode, and the length of the long side of the first electrode is the side S ₁ Shorter than the length of the second electrode, ₃ Long side parallel to and side S ₂ Has an elongated rectangular shape having a short side parallel to ₂ , S ₃ Is provided close to the second electrode, and the length of the long side of the second electrode is the side S ₃ Shorter than the length of the third electrode, _Four Long side parallel to and side S ₁ Has a rectangular shape having a short side parallel to the first electrode and the side S _Four Edge S in the area between ₁ , S _Four Is installed close to
After the first electrode pad is vertically upwardly drawn from the first electrode with respect to the semiconductor layer, a side S ₁ Extending over the semiconductor layer in parallel with the semiconductor layer so as to straddle the semiconductor layer, and the outer tip of the first electrode pad has a side S ₁ The second electrode pad is parallel to the first electrode pad, and the second electrode pad is vertically upwardly drawn from the second electrode with respect to the semiconductor layer. ₃ So as to extend over the semiconductor layer in parallel to the semiconductor layer, and the outer tip of the second electrode pad has a side S ₃ And the third electrode pad is vertically upwardly drawn from the third electrode with respect to the semiconductor layer, and then the side S _Four Extending over the semiconductor layer in parallel to the semiconductor layer so as to straddle the semiconductor layer, and the outer tip of the third electrode pad has a side S _Four Parallel to
The contour of the resin is larger than the semiconductor chip by the thickness of the resin on the side surface of the semiconductor chip, but is substantially similar to the outer shape of the semiconductor chip,
The tip of the first electrode pad, the tip of the second electrode pad, and the tip of the third electrode pad match the contour of the resin,
The semiconductor package is mounted on the one main surface of the metal substrate with the second main surface of the sapphire substrate in contact with the one main surface of the metal substrate, the first electrode pad, the second The surface of the electrode pad and the third electrode pad opposite to the sapphire substrate is electrically connected to a predetermined portion of the predetermined wiring on the one main surface of the double-sided printed wiring board, and the predetermined circuit is formed. The module that is configured. Has one or more modules,
At least one of the modules is
A metal substrate,
One or more semiconductor packages mounted on one main surface of the metal substrate;
A double-sided printed wiring board having a predetermined wiring provided on one main surface so as to form a predetermined circuit on the one or more semiconductor packages;
The semiconductor package is
A semiconductor layer forming a three-terminal semiconductor element is provided on the first main surface of the sapphire substrate, and the first electrode, the second electrode, and the third electrode are arranged in a triangular shape on the semiconductor layer to form a rectangular planar shape. A semiconductor chip having
A first electrode pad, a second electrode pad, and a third electrode pad that are brought into contact with the first electrode, the second electrode, and the third electrode to be electrically connected to each other and are drawn out of the semiconductor layer;
An electrically insulating resin that seals the side surfaces of the first electrode, the second electrode, the third electrode, the semiconductor layer, and the sapphire substrate,
Have
The four sides of the semiconductor chip are sequentially counter-clockwise S ₁ , S ₂ , S ₃ , S _Four And the first electrode is the side S ₁ Long side parallel to and side S ₂ Has an elongated rectangular shape having a short side parallel to ₁ , S ₂ Is provided close to the first electrode, and the length of the long side of the first electrode is the side S ₁ Shorter than the length of the second electrode, ₃ Long side parallel to and side S ₂ Has an elongated rectangular shape having a short side parallel to ₂ , S ₃ Is provided close to the second electrode, and the length of the long side of the second electrode is the side S ₃ Shorter than the length of the third electrode, _Four Long side parallel to and side S ₁ Has a rectangular shape having a short side parallel to the first electrode and the side S _Four Edge S in the area between ₁ , S _Four Is installed close to
The first electrode pad is a side S from the first electrode via the resin. ₁ Projecting in a direction perpendicular to, and in a direction parallel to the semiconductor layer and the sapphire substrate, and the tip of the projecting first electrode pad has a side S. ₁ And the second electrode pad is parallel to the side S from the second electrode via the resin. ₃ Projecting in a direction perpendicular to, and parallel to the semiconductor layer and the sapphire substrate, and the tip of the projecting second electrode pad has a side S. ₃ And the third electrode pad is parallel to the side S from the third electrode via the resin. _Four Projecting in a direction perpendicular to, and in a direction parallel to the semiconductor layer and the sapphire substrate, the tip of the projecting third electrode pad has a side S. _Four Parallel to
The semiconductor package is mounted on the one main surface of the metal substrate with the second main surface of the sapphire substrate in contact with the one main surface of the metal substrate, the first electrode pad, the second Surfaces of the electrode pads and the third electrode pads, which are opposite to the sapphire substrate, of the portions projecting from the resin are electrically connected to predetermined portions of the predetermined wiring on the one main surface of the double-sided printed wiring board. A module in which the predetermined circuit is configured
Electrical equipment. Has one or more modules,
At least one of the modules is
A metal substrate,
One or more semiconductor packages mounted on one main surface of the metal substrate;
A double-sided printed wiring board having a predetermined wiring provided on one main surface so as to form a predetermined circuit on the one or more semiconductor packages;
The semiconductor package is
A semiconductor layer forming a three-terminal semiconductor element is provided on the first main surface of the sapphire substrate, and the first electrode, the second electrode, and the third electrode are arranged in a triangular shape on the semiconductor layer to form a rectangular planar shape. A semiconductor chip having
A first electrode pad, a second electrode pad, and a third electrode pad that are brought into contact with and electrically connected to the first electrode, the second electrode, and the third electrode, respectively, and are drawn out above the semiconductor layer;
An electrically insulating resin that seals the side surfaces of the first electrode, the second electrode, the third electrode, the semiconductor layer, and the sapphire substrate,
Have
The four sides of the semiconductor chip are sequentially counter-clockwise S ₁ , S ₂ , S ₃ , S _Four And the first electrode is the side S ₁ Long side parallel to and side S ₂ Has an elongated rectangular shape having a short side parallel to ₁ , S ₂ Is provided close to the first electrode, and the length of the long side of the first electrode is the side S ₁ Shorter than the length of the second electrode, ₃ Long side parallel to and side S ₂ Has an elongated rectangular shape having a short side parallel to ₂ , S ₃ Is provided close to the second electrode, and the length of the long side of the second electrode is the side S ₃ Shorter than the length of the third electrode, _Four Long side parallel to and side S ₁ Has a rectangular shape having a short side parallel to the first electrode and the side S _Four Edge S in the area between ₁ , S _Four Is installed close to
After the first electrode pad is vertically upwardly drawn from the first electrode with respect to the semiconductor layer, a side S ₁ Extending over the semiconductor layer in parallel with the semiconductor layer so as to straddle the semiconductor layer, and the outer tip of the first electrode pad has a side S ₁ The second electrode pad is parallel to the first electrode pad, and the second electrode pad is vertically upwardly drawn from the second electrode with respect to the semiconductor layer. ₃ So as to extend over the semiconductor layer in parallel to the semiconductor layer, and the outer tip of the second electrode pad has a side S ₃ And the third electrode pad is vertically upwardly drawn from the third electrode with respect to the semiconductor layer, and then the side S _Four Extending over the semiconductor layer in parallel to the semiconductor layer so as to straddle the semiconductor layer, and the outer tip of the third electrode pad has a side S _Four Parallel to
The contour of the resin is larger than the semiconductor chip by the thickness of the resin on the side surface of the semiconductor chip, but is substantially similar to the outer shape of the semiconductor chip,
The tip of the first electrode pad, the tip of the second electrode pad, and the tip of the third electrode pad match the contour of the resin,
The semiconductor package is mounted on the one main surface of the metal substrate with the second main surface of the sapphire substrate in contact with the one main surface of the metal substrate, the first electrode pad, the second The surface of the electrode pad and the third electrode pad opposite to the sapphire substrate is electrically connected to a predetermined portion of the predetermined wiring on the one main surface of the double-sided printed wiring board, and the predetermined circuit is formed. Modules configured
Electrical equipment. A semiconductor package used between being provided between one main surface of a metal substrate and one main surface of a double-sided printed wiring board,
The semiconductor package is
A semiconductor chip having a rectangular planar shape in which a semiconductor layer forming a diode is provided on a first main surface of a sapphire substrate, and first electrodes, second electrodes, and third electrodes are arranged in a triangle on the semiconductor layer. When,
A first electrode pad and a second electrode pad that are brought into contact with the first electrode and the second electrode to be electrically connected to each other and are drawn out of the semiconductor layer;
An electrically insulating resin that seals the side surfaces of the first electrode, the second electrode, the third electrode, the semiconductor layer, and the sapphire substrate,
Have
The four sides of the semiconductor chip are sequentially counter-clockwise S ₁ , S ₂ , S ₃ , S _Four And the first electrode is the side S ₁ Long side parallel to and side S ₂ Has an elongated rectangular shape having a short side parallel to ₁ , S ₂ Is provided close to the first electrode, and the length of the long side of the first electrode is the side S ₁ Shorter than the length of the second electrode, ₃ Long side parallel to and side S ₂ Has an elongated rectangular shape having a short side parallel to ₂ , S ₃ Is provided close to the second electrode, and the length of the long side of the second electrode is the side S ₃ Shorter than the length of the third electrode, _Four Long side parallel to and side S ₁ Has a rectangular shape having a short side parallel to the first electrode and the side S _Four Edge S in the area between ₁ , S _Four Is installed close to
The first electrode pad is a side S from the first electrode via the resin. ₁ Projecting in a direction perpendicular to, and in a direction parallel to the semiconductor layer and the sapphire substrate, and the tip of the projecting first electrode pad has a side S. ₁ And the second electrode pad is parallel to the side S from the second electrode via the resin. ₃ Projecting in a direction perpendicular to, and parallel to the semiconductor layer and the sapphire substrate, and the tip of the projecting second electrode pad has a side S. ₃ Parallel to
The first electrode and the second electrode configure an anode electrode and a cathode electrode, the first electrode pad and the second electrode pad configure an anode electrode pad and a cathode electrode pad,
The semiconductor package is mounted on the one main surface of the metal substrate such that the second main surface of the sapphire substrate is in contact with the one main surface of the metal substrate, and the semiconductor package is mounted on the one main surface of the metal substrate. The surface of the part of the electrode pad protruding from the resin opposite to the sapphire substrate is electrically connected to a predetermined portion of a predetermined wiring on the one main surface of the double-sided printed wiring board to form a predetermined circuit. A semiconductor package characterized by being processed. A semiconductor package used between being provided between one main surface of a metal substrate and one main surface of a double-sided printed wiring board,
The semiconductor package is
A semiconductor chip having a rectangular planar shape in which a semiconductor layer forming a diode is provided on a first main surface of a sapphire substrate, and first electrodes, second electrodes, and third electrodes are arranged in a triangle on the semiconductor layer. When,
A first electrode pad and a second electrode pad which are brought into contact with and electrically connected to the first electrode and the second electrode, respectively, and which are drawn out above the semiconductor layer;
An electrically insulating resin that seals the side surfaces of the first electrode, the second electrode, the third electrode, the semiconductor layer, and the sapphire substrate,
Have
The four sides of the semiconductor chip are sequentially counter-clockwise S ₁ , S ₂ , S ₃ , S _Four And the first electrode is the side S ₁ Long side parallel to and side S ₂ Has an elongated rectangular shape having a short side parallel to ₁ , S ₂ Is provided close to the first electrode, and the length of the long side of the first electrode is the side S ₁ Shorter than the length of the second electrode, ₃ Long side parallel to and side S ₂ Has an elongated rectangular shape having a short side parallel to ₂ , S ₃ Is provided close to the second electrode, and the length of the long side of the second electrode is the side S ₃ Shorter than the length of the third electrode, _Four Long side parallel to and side S ₁ Has a rectangular shape having a short side parallel to the first electrode and the side S _Four Edge S in the area between ₁ , S _Four Is installed close to
After the first electrode pad is vertically upwardly drawn from the first electrode with respect to the semiconductor layer, a side S ₁ Extending over the semiconductor layer in parallel with the semiconductor layer so as to straddle the semiconductor layer, and the outer tip of the first electrode pad has a side S ₁ The second electrode pad is parallel to the first electrode pad, and the second electrode pad is vertically upwardly drawn from the second electrode with respect to the semiconductor layer. ₃ So as to extend over the semiconductor layer in parallel to the semiconductor layer, and the outer tip of the second electrode pad has a side S ₃ Parallel to
The contour of the resin is larger than the semiconductor chip by the thickness of the resin on the side surface of the semiconductor chip, but is substantially similar to the outer shape of the semiconductor chip,
The tip of the first electrode pad and the tip of the second electrode pad match the contour of the resin,
The first electrode and the second electrode constitute an anode electrode and a cathode electrode, the first electrode pad and the second electrode pad constitute an anode electrode pad and a cathode electrode pad,
The semiconductor package is mounted on the one main surface of the metal substrate such that the second main surface of the sapphire substrate is in contact with the one main surface of the metal substrate, and the semiconductor package is mounted on the one main surface of the metal substrate. A surface of the electrode pad opposite to the sapphire substrate is electrically connected to a predetermined portion of a predetermined wiring on the one main surface of the double-sided printed wiring board to form a predetermined circuit. Semiconductor package. A metal substrate,
One or more semiconductor packages mounted on one main surface of the metal substrate;
A double-sided printed wiring board having a predetermined wiring provided on one main surface so as to form a predetermined circuit on the one or more semiconductor packages;
The semiconductor package is
A semiconductor chip having a rectangular planar shape in which a semiconductor layer forming a diode is provided on a first main surface of a sapphire substrate, and first electrodes, second electrodes, and third electrodes are arranged in a triangle on the semiconductor layer. When,
A first electrode pad and a second electrode pad that are brought into contact with the first electrode and the second electrode to be electrically connected to each other and are drawn out of the semiconductor layer;
An electrically insulating resin that seals the side surfaces of the first electrode, the second electrode, the third electrode, the semiconductor layer, and the sapphire substrate,
Have
The four sides of the semiconductor chip are sequentially counter-clockwise S ₁ , S ₂ , S ₃ , S _Four And the first electrode is the side S ₁ Long side parallel to and side S ₂ Has an elongated rectangular shape having a short side parallel to ₁ , S ₂ Is provided close to the first electrode, and the length of the long side of the first electrode is the side S ₁ Shorter than the length of the second electrode, ₃ Long side parallel to and side S ₂ Has an elongated rectangular shape having a short side parallel to ₂ , S ₃ Is provided close to the second electrode, and the length of the long side of the second electrode is the side S ₃ Shorter than the length of the third electrode, _Four Long side parallel to and side S ₁ Has a rectangular shape having a short side parallel to the first electrode and the side S _Four Edge S in the area between ₁ , S _Four Is installed close to
The first electrode pad is a side S from the first electrode via the resin. ₁ Projecting in a direction perpendicular to, and in a direction parallel to the semiconductor layer and the sapphire substrate, and the tip of the projecting first electrode pad has a side S. ₁ And the second electrode pad is parallel to the side S from the second electrode via the resin. ₃ Projecting in a direction perpendicular to, and parallel to the semiconductor layer and the sapphire substrate, and the tip of the projecting second electrode pad has a side S. ₃ Parallel to
The first electrode and the second electrode constitute an anode electrode and a cathode electrode, the first electrode pad and the second electrode pad constitute an anode electrode pad and a cathode electrode pad,
The semiconductor package is mounted on the one main surface of the metal substrate with the second main surface of the sapphire substrate in contact with the one main surface of the metal substrate, and the first electrode pad and the second The surface of the part of the electrode pad protruding from the resin opposite to the sapphire substrate is electrically connected to a predetermined portion of the predetermined wiring on the one main surface of the double-sided printed wiring board, and the predetermined circuit is formed. The modules that are configured. A metal substrate,
One or more semiconductor packages mounted on one main surface of the metal substrate;
A double-sided printed wiring board having a predetermined wiring provided on one main surface so as to form a predetermined circuit on the one or more semiconductor packages;
The semiconductor package is
A semiconductor chip having a rectangular planar shape in which a semiconductor layer forming a diode is provided on a first main surface of a sapphire substrate, and first electrodes, second electrodes, and third electrodes are arranged in a triangle on the semiconductor layer. When,
A first electrode pad and a second electrode pad which are brought into contact with and electrically connected to the first electrode and the second electrode, respectively, and which are drawn out above the semiconductor layer;
An electrically insulating resin that seals the side surfaces of the first electrode, the second electrode, the third electrode, the semiconductor layer, and the sapphire substrate,
Have
The four sides of the semiconductor chip are sequentially counter-clockwise S ₁ , S ₂ , S ₃ , S _Four And the first electrode is the side S ₁ Long side parallel to and side S ₂ Has an elongated rectangular shape having a short side parallel to ₁ , S ₂ Is provided close to the first electrode, and the length of the long side of the first electrode is the side S ₁ Shorter than the length of the second electrode, ₃ Long side parallel to and side S ₂ Has an elongated rectangular shape having a short side parallel to ₂ , S ₃ Is provided close to the second electrode, and the length of the long side of the second electrode is the side S ₃ Shorter than the length of the third electrode, _Four Long side parallel to and side S ₁ Has a rectangular shape having a short side parallel to the first electrode and the side S _Four Edge S in the area between ₁ , S _Four Is installed close to
After the first electrode pad is vertically upwardly drawn from the first electrode with respect to the semiconductor layer, a side S ₁ Extending over the semiconductor layer in parallel with the semiconductor layer so as to straddle the semiconductor layer, and the outer tip of the first electrode pad has a side S ₁ The second electrode pad is parallel to the first electrode pad, and the second electrode pad is vertically upwardly drawn from the second electrode with respect to the semiconductor layer. ₃ So as to extend over the semiconductor layer in parallel to the semiconductor layer, and the outer tip of the second electrode pad has a side S ₃ Parallel to
The contour of the resin is larger than the semiconductor chip by the thickness of the resin on the side surface of the semiconductor chip, but is substantially similar to the outer shape of the semiconductor chip,
The tip of the first electrode pad and the tip of the second electrode pad match the contour of the resin,
The first electrode and the second electrode constitute an anode electrode and a cathode electrode, the first electrode pad and the second electrode pad constitute an anode electrode pad and a cathode electrode pad,
The semiconductor package is mounted on the one main surface of the metal substrate with the second main surface of the sapphire substrate in contact with the one main surface of the metal substrate, and the first electrode pad and the second A module in which the predetermined circuit is configured by electrically connecting a surface of the electrode pad opposite to the sapphire substrate to a predetermined portion of the predetermined wiring on the one main surface of the double-sided printed wiring board. Has one or more modules,
At least one of the modules is
A metal substrate,
One or more semiconductor packages mounted on one main surface of the metal substrate;
A double-sided printed wiring board having a predetermined wiring provided on one main surface so as to form a predetermined circuit on the one or more semiconductor packages;
The semiconductor package is
A semiconductor chip having a rectangular planar shape in which a semiconductor layer forming a diode is provided on a first main surface of a sapphire substrate, and first electrodes, second electrodes, and third electrodes are arranged in a triangle on the semiconductor layer. When,
A first electrode pad and a second electrode pad that are brought into contact with the first electrode and the second electrode to be electrically connected to each other and are drawn out of the semiconductor layer;
An electrically insulating resin that seals the side surfaces of the first electrode, the second electrode, the third electrode, the semiconductor layer, and the sapphire substrate,
Have
The four sides of the semiconductor chip are sequentially counter-clockwise S ₁ , S ₂ , S ₃ , S _Four And the first electrode is the side S ₁ Long side parallel to and side S ₂ Has an elongated rectangular shape having a short side parallel to ₁ , S ₂ Is provided close to the first electrode, and the length of the long side of the first electrode is the side S ₁ Shorter than the length of the second electrode, ₃ Long side parallel to and side S ₂ Has an elongated rectangular shape having a short side parallel to ₂ , S ₃ Is provided close to the second electrode, and the length of the long side of the second electrode is the side S ₃ Shorter than the length of the third electrode, _Four Long side parallel to and side S ₁ Has a rectangular shape having a short side parallel to the first electrode and the side S _Four Edge S in the area between ₁ , S _Four Is installed close to
The first electrode pad is a side S from the first electrode via the resin. ₁ Projecting in a direction perpendicular to, and in a direction parallel to the semiconductor layer and the sapphire substrate, and the tip of the projecting first electrode pad has a side S. ₁ And the second electrode pad is parallel to the side S from the second electrode via the resin. ₃ Projecting in a direction perpendicular to, and parallel to the semiconductor layer and the sapphire substrate, and the tip of the projecting second electrode pad has a side S. ₃ Parallel to
The first electrode and the second electrode constitute an anode electrode and a cathode electrode, the first electrode pad and the second electrode pad constitute an anode electrode pad and a cathode electrode pad,
The semiconductor package is mounted on the one main surface of the metal substrate with the second main surface of the sapphire substrate in contact with the one main surface of the metal substrate, and the first electrode pad and the second The surface of the part of the electrode pad protruding from the resin opposite to the sapphire substrate is electrically connected to a predetermined portion of the predetermined wiring on the one main surface of the double-sided printed wiring board, and the predetermined circuit is formed. The modules that are configured
Electrical equipment. Has one or more modules,
At least one of the modules is
A metal substrate,
One or more semiconductor packages mounted on one main surface of the metal substrate;
A double-sided printed wiring board having a predetermined wiring provided on one main surface so as to form a predetermined circuit on the one or more semiconductor packages;
The semiconductor package is
A semiconductor chip having a rectangular planar shape in which a semiconductor layer forming a diode is provided on a first main surface of a sapphire substrate, and first electrodes, second electrodes, and third electrodes are arranged in a triangle on the semiconductor layer. When,
A first electrode pad and a second electrode pad which are brought into contact with and electrically connected to the first electrode and the second electrode, respectively, and which are drawn out above the semiconductor layer;
An electrically insulating resin that seals the side surfaces of the first electrode, the second electrode, the third electrode, the semiconductor layer, and the sapphire substrate,
Have
The four sides of the semiconductor chip are sequentially counter-clockwise S ₁ , S ₂ , S ₃ , S _Four And the first electrode is the side S ₁ Long side parallel to and side S ₂ Has an elongated rectangular shape having a short side parallel to ₁ , S ₂ Is provided close to the first electrode, and the length of the long side of the first electrode is the side S ₁ Shorter than the length of the second electrode, ₃ Long side parallel to and side S ₂ Has an elongated rectangular shape having a short side parallel to ₂ , S ₃ Is provided close to the second electrode, and the length of the long side of the second electrode is the side S ₃ Shorter than the length of the third electrode, _Four Long side parallel to and side S ₁ Has a rectangular shape having a short side parallel to the first electrode and the side S _Four Edge S in the area between ₁ , S _Four Is installed close to
After the first electrode pad is vertically upwardly drawn from the first electrode with respect to the semiconductor layer, a side S ₁ Extending over the semiconductor layer in parallel with the semiconductor layer so as to straddle the semiconductor layer, and the outer tip of the first electrode pad has a side S ₁ The second electrode pad is parallel to the first electrode pad, and the second electrode pad is vertically upwardly drawn from the second electrode with respect to the semiconductor layer. ₃ So as to extend over the semiconductor layer in parallel to the semiconductor layer, and the outer tip of the second electrode pad has a side S ₃ Parallel to
The contour of the resin is larger than the semiconductor chip by the thickness of the resin on the side surface of the semiconductor chip, but is substantially similar to the outer shape of the semiconductor chip,
The tip of the first electrode pad and the tip of the second electrode pad match the contour of the resin,
The first electrode and the second electrode constitute an anode electrode and a cathode electrode, the first electrode pad and the second electrode pad constitute an anode electrode pad and a cathode electrode pad,
The semiconductor package is mounted on the one main surface of the metal substrate with the second main surface of the sapphire substrate in contact with the one main surface of the metal substrate, and the first electrode pad and the second A module in which the predetermined circuit is configured by electrically connecting the surface of the electrode pad opposite to the sapphire substrate to a predetermined portion of the predetermined wiring on the one main surface of the double-sided printed wiring board.
Electrical equipment.

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