JP6742282B2 - Amusement machine - Google Patents

Description

The present invention relates to a gaming machine that causes a big hit state by a lottery process resulting from a gaming operation, and relates to a gaming machine that eliminates noise troubles of a display device.

A ball game machine such as a pachinko machine is provided with a symbol starting opening provided on the game board, a symbol display section for displaying a series of symbol variation modes by a plurality of display symbols, and a large winning opening for opening and closing the opening/closing plate. Is configured. Then, when the detection switch provided in the symbol starting port detects the passage of the game ball, the winning state is established, and after the game ball is paid out as the prize ball, the display symbol is changed in the symbol display portion for a predetermined time. After that, when the symbol stops in a predetermined mode such as 7/7, it becomes a big hit state, the special winning opening is repeatedly opened, and a game state advantageous to the player is generated.

Whether or not to generate such a game state is determined by a jackpot lottery executed on the condition that a game ball is won in the symbol start opening, and the above-mentioned symbol variation operation is based on this lottery result. It has become a thing. For example, when the lottery result is a winning state, a production operation called a reach action or the like is executed for about 20 seconds, and then special symbols are arranged. On the other hand, even in the case of the lost state, the same reach action may be executed, and in this case, the player pays close attention to the transition of the performance operation while strongly keeping in mind the big hit state. Then, at the end of the symbol changing operation, if the predetermined symbols are aligned with the stop line, the player is guaranteed to be in the big hit state.

By the way, in this type of gaming machine, generally, an image effect on a display device, a lamp effect in which an illumination lamp blinks, and a sound effect from a speaker are executed in synchronization, and a movable object (character ) Moving effect is executed. Then, these effect operations are realized by one or a plurality of computer devices (control means) that execute image control, lamp control, voice control, and motor control.

JP, 2017-006164, A JP, 2016-214741, A JP, 2016-034357, A JP, 2005-177885, A JP, 2013-128606, A

Among various kinds of effect control described above, image effect is particularly important, and there is also known a configuration in which a display device configured to be movable executes image effect (Patent Documents 1 to 4). However, when the movable mechanism is added to the display device, the transmission distance of the image signal becomes longer by that amount, and there is a problem that it is easily affected by noise or the like.

That is, LVDS (Low Voltage Differential Signaling) transmission is generally said to be resistant to noise, but in order to display a high-resolution image on a large-screen display device, the pixel clock (dot clock) is correspondingly increased. Since the frequency increases, for example, when the transmission distance is about 1 m, all pixel information may not be accurately transmitted due to the influence of signal level attenuation and noise. In addition, a long signal transmission line may function as an antenna and radiate EMI (Electro Magnetic Interference) noise.

Therefore, an unnatural flicker may occur on the display screen, or a black screen may be displayed for a moment due to the fail-safe function of the transmission IC or the display device that transmits the LVDS signal. A certain image production may be ruined.

Here, the configuration of Patent Document 5 is known as a countermeasure against noise, but in Patent Document 5, RGB parallel data (for example, 3×8 bits) is converted into an LVDS signal in a liquid crystal relay substrate 320 (see FIG. 5). It just teaches to convert. That is, since it is practically impossible to dispose the liquid crystal relay substrate 320 that receives the RGB data output from the VDP (Video Display Processor) at a position away from the VDP, from the viewpoint of the number of transmission lines and noise resistance, the cited document is cited. The configuration of No. 5 cannot be a countermeasure against noise on the LVDS transmission line.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a gaming machine capable of eliminating a malfunction of a display device.

In order to achieve the above object, the present invention controls an image effect corresponding to a lottery result of a lottery process executed based on a predetermined switch signal based on a control command received from another control means. In a gaming machine provided with control means, the sub-control means outputs a drawing instruction for specifying display contents of a display device for executing image effect, and controls the image effect with the effect control means. An image signal generated by accessing the data storage means on the basis of the data storage means for storing the compressed data which is a constituent element of the still picture and/or the moving picture and the drawing instruction received from the effect control means are LVDS. An image generating means capable of outputting in the form of a (Low Voltage Differential Signaling) signal, and a first wiring cable set to a predetermined length between the image generating means and the display device. A relay board connected to the image generation means and connected to the display device by a second wiring cable set to a predetermined length is arranged, and the LVDS signal output by the image generation means is input to the relay board. An electronic circuit element capable of outputting to the output terminal an LVDS signal having the same frequency of the dot clock or having the frequency doubled while being received by the terminal is disposed, and the electronic circuit element passes through the first wiring cable. Then, the receiving unit that de-serializes the received LVDS signal to restore the RGB signal and the control signal, and outputs the LVDS signal generated by performing the serialized processing of the restored RGB signal and the control signal to the second wiring cable. Located between the transmission unit and the reception unit and the transmission unit, it is possible to perform either a first Repeater operation in which the frequency of the dot clock does not change or a second Repeater operation in which the frequency of the dot clock changes. And a control unit .

Preferably, the inductor should be arranged for each differential signal line, and it is preferable that the relay board is further provided with a protection element that performs a short-circuit operation during electrostatic discharge.

Further, the present invention, a game provided with a sub-control means for controlling the image effect corresponding to the lottery result of the lottery processing executed due to the predetermined switch signal based on the control command received from the other control means. In the machine, the sub-control unit outputs a drawing instruction that specifies the display content of the display device that executes the image effect, controls the image effect, and a still image and/or a still image forming the image effect. Alternatively, an image signal generated by accessing the data storage means on the basis of the data storage means for storing the compressed data which is a constituent element of the moving image and the drawing instruction received from the effect control means is LVDS (Low Voltage Differential Signaling). And an image generating unit capable of outputting in the form of a signal, and is connected to the image generating unit between the image generating unit and the display device by a first wiring cable set to a predetermined length. Further, a relay board connected to the display device by a second wiring cable set to a predetermined length is arranged, and the relay board receives the LVDS signal output from the image generating means at its input terminal, and the dot An electronic circuit element capable of outputting an LVDS signal having the same clock frequency or a frequency obtained by changing the frequency by half is arranged, and the electronic circuit element is received via the first wiring cable. A receiver that de-serializes the LVDS signal to restore the RGB signal or control signal, and a transmitter that outputs the LVDS signal generated by serializing the restored RGB signal or control signal to the second wiring cable. An intermediate control unit that is located between the receiving unit and the transmitting unit and is capable of executing either a first Repeater operation in which the frequency of the dot clock does not change or a second Repeater operation in which the frequency of the dot clock changes. Is configured.

In any case, it is preferable that a plurality of the display devices are arranged, and the relay substrate is arranged corresponding to each display device, and the plurality of display devices are related to the display device to be compared. It is preferable that the display devices have the same vertical pixel number and horizontal pixel number on their respective display screens.

In addition to the image effect, the sub-control unit integrally controls all or part of a lamp effect for driving a lamp, a sound effect for driving a speaker, and a movable effect for moving a movable object. It is preferable that it is configured with.

According to the present invention, by providing the relay board on which the relay circuit having the special configuration is mounted, it is possible to realize the gaming machine capable of eliminating the noise trouble of the display device.

It is a perspective view of a pachinko machine shown in an example. It is the front view which shows the game board of the pachinko machine of Figure 1, and the one which illustrates the operation of each display device. It is a perspective view which shows the movable mechanism of a display apparatus. It is a block diagram which shows the whole structure of the pachinko machine shown in an Example. It is the block diagram which shows the circuit constitution of the production IF baseplate, the production control baseplate, and the liquid crystal IF baseplate. It is a block diagram showing an internal configuration of a composite chip in charge of various performance operations. It is drawing explaining the memory content and the operation procedure which implement|achieves an image production. 6 is a diagram illustrating an operation of a display circuit. It is drawing which shows the structure of an LVDS relay substrate. 3 is a diagram showing an internal configuration of a transmission IC mounted on an LVDS relay board. 6 is a diagram illustrating an operation of a transmission IC. It is a flow chart explaining an internal operation of a compound chip. 6 is a diagram illustrating an operation of a CPU and an operation of an internal circuit of a VDP circuit. It is a block diagram explaining other Examples. It is drawing explaining operation|movement of other Example. It is drawing explaining another apparatus structure. It is drawing explaining a part of apparatus structure of FIG.

Hereinafter, the present invention will be described in detail based on examples. FIG. 1 is a perspective view showing a pachinko machine GM of this embodiment. The pachinko machine GM includes a rectangular frame-shaped wooden outer frame 1 that is detachably attached to an island structure, and a front frame 3 that is pivotally mounted to be openable and closable via a hinge 2 fixed to the outer frame 1. It is configured. A game board 5 is detachably attached to the front frame 3 from the front side, not from the back side, and a glass door 6 and a front plate 7 are pivotally attached to the front side so as to be openable and closable.

On the outer periphery of the glass door 6, an electric lamp such as an LED lamp is arranged in a substantially C shape. On the other hand, a total of three speakers are arranged at the upper left and right positions and the lower side of the glass door 6. The two speakers arranged in the upper part output the sounds of the left and right channels R and L, respectively, and the lower speaker outputs the bass sound.

The upper plate 8 for storing the game balls for firing is attached to the front plate 7, and the lower plate 9 for storing the game balls overflowing or extracted from the upper plate 8 and the launch handle are mounted on the lower portion of the front frame 3. And 10 are provided. The firing handle 10 is interlocked with a firing motor, and a gaming ball is fired by a batting mallet that operates in accordance with the rotation angle of the firing handle 10.

A chance button 11 is provided on the outer peripheral surface of the upper plate 8. The chance button 11 is provided at a position where it can be operated by the player's left hand, and the player can operate the chance button 11 without releasing the right hand from the firing handle 10. The chance button 11 is not functioning normally, but when the game state is the button chance state, the built-in lamp is turned on and it can be operated. The button chance state is a game state provided as necessary.

On the right side of the upper plate 8, there is provided an operation panel 12 for ball lending operation to a card type ball lending machine, a frequency display section for displaying the card remaining amount by a three-digit number, and a ball for a predetermined amount of game balls. A ball lending switch for instructing lending and a return switch for instructing the return of the card at the end of the game are provided.

As shown in FIG. 2, a guide rail 13 including an outer rail and an inner rail made of metal is annularly provided on the surface of the game board 5, and a central opening HO is provided substantially at the center thereof. A movable effect body (not shown) is housed under the central opening HO in a concealed state. When the movable notice effect is performed, the movable effect body rises to be in an exposed state, so that a predetermined reliability is obtained. A notice production is realized. Here, the advance notice effect is an effect that informs uncertainly that a big hit state advantageous to the player is coming, and the reliability of the notice effect means a probability that the big hit state is brought.

A pair of display devices DS1a and DS1b formed of a liquid crystal color display are movably arranged in the central opening HO. Although not limited in any way, the pair of display devices DS1a and DS1b each have a pixel number of 800×600 pixels and a diagonal dimension of about 12.1 inches. Appropriate places of the display devices DS1a and DS1b function as special symbol display portions, and are configured so that special symbols relating to the lottery result of the big hit lottery are variably displayed.

When the jackpot lottery is executed due to the winning of the game balls to the symbol starting ports 15a and 15b, the variable display of the special symbol is started in front of the background image displayed on the display devices DS1a and DS1b, The lottery result of the jackpot lottery is notified based on the stop mode at the end of the variable display. In addition, in the middle of this variable display, a reach effect that expects a big hit state may be executed, and a notice effect is executed by an image effect in which various characters appear at appropriate timing. There is also.

Next, the movable mechanism STR of the display device DS1a and the display device DS1b will be described based on FIGS. 2B and 3. FIG. 3A is a perspective view of the main part of the movable mechanism STR as seen from the back side, and FIG. 3B is a perspective view of the movable mechanism STR as seen from the front side.

As shown in FIG. 3A, the movable mechanism STR is driven by two left and right drive motors MOR and MOL that rotate integrally with each other and the motors MOR and MOL, and pass through rotary rollers RO and RO. Circulating fan belts BT, BT, a pair of left and right rear holding pieces HLb, HLb held by the left and right fan belts BT, BT at a rear position, and a rear base plate BSb fixed to the rear holding pieces HLb, HLb. , A pair of left and right front holding pieces HLa and HLa that are held by the left and right fan belts BT and BT at the front position, and a front base plate BSa that is fixed to the front holding pieces HLa and HLa, and are spaced apart from each other at the front and rear positions. It has a total of four guide poles GDa, GDa, GDb, GDb.

The display device DS1b is fixed to the rear base plate BSb, while the display device DS1a is held by being fixed to the front base plate BSa. Further, the front holding pieces HLa, HLa and the rear holding pieces HLb, HLb are respectively provided with receiving holes for receiving the guide poles GDa, GDa, GDb, GDb, and are integrated with the display devices DS1a, DS1b. The holding pieces HLa and HLb are guided by the corresponding guide poles GDa and GDb to smoothly move up and down in the vertical direction.

FIG. 2B shows the positional relationship between the two display devices DS1a and DS1b and the moving position. FIG. 2B1 shows a steady state, in which the display device DS1a located on the upper side and the display device DS1b located on the lower side are continuous in the up-down direction without overlapping, and thus 12.1 inches. The display screen is twice as large as the display screen. Since the lower display frame FM of the display device DS1a coincides with the position of the upper display frame of the display device DS1b, the two display devices DS1a and DS1b display one display screen except for the lower display frame FM. Form.

Here, since the two drive motors MOR and MOL are configured to rotate integrally with each other, for example, when the drive motors MOR and MOL start to rotate integrally in the counterclockwise direction shown in the drawing, the upper display device is displayed. Corresponding to the fall of DS1a, the lower display device DS1b rises.

Then, after the two display devices DS1a and DS1b are overlapped in the front-rear direction with the overlapping state of FIG. 2(b2), when the display device DS1a further descends and reaches the limit position, the state of FIG. 2(b3) is obtained. .. As shown in the figure, the descent limit of the display device DS1a is the ascent limit of the display device DS1b, and a display screen twice as large as 12.1 inches is displayed by the display device DS1b located on the upper side and the display device DS1a located on the lower side. It is formed.

When the drive motors MOR and MOL rotate integrally in the illustrated clockwise direction from the state of FIG. 2(b3), the overlapping state of FIG. 2(b2) is returned to the steady state of FIG. 2(b1). Become.

In view of this, in the present embodiment, the drive motors MOR and MOL are rotated clockwise or counterclockwise by an appropriate amount to produce a staging operation including the initial state (b1) and the overlapping state (b2). A, the production operation B including the overlapping state (b2) and the descent limit (b3), the production operation C including the initial state (b1) and the descent limit (b3), and the like are used to excite the player. .. These movable effects are preferably executed as a notice effect.

As described above, since the display devices DS1a and DS1b move up and down, the signal transmission line (see the broken line) needs to have a length that allows this up and down movement. Therefore, in the present embodiment, RGB image signals to be transmitted to the display devices DS1a and DS1b and control signals such as synchronization signals are transmitted as LVDS signals (Low Voltage Differential Signaling) and at the same distance from the effect control board 23. In addition, a pair of LVDS relay boards 27a and 27b are provided near the display devices DS1a and DS1b (see FIG. 2B and FIGS. 4 to 5).

Here, the transmission distance from the effect control board 23 to the LVDS relay boards 27a and 27b, and the transmission distance from the LVDS relay boards 27a and 27b to the display devices DS1a and DS1b, respectively, indicate that normal transmission of the LVDS signal is experimental. Limited to a guaranteed distance (for example, within 1 m).

Then, the RGB signal and the control signal restored from the LVDS signal by the De-serialize process in the LVDS relay boards 27a and 27b are serialized again to regenerate the LVDS signal and transmitted to each of the display devices DS1a and DS1b. (Fig. 10). Therefore, in this embodiment, the effect control board 23 is located substantially at the positions of the LVDS relay boards 27a and 27b, the signal level attenuation does not become a problem, and it is resistant to common mode noise. Since the differential signal (Differential Signaling) is used, it is possible to avoid the abnormal operation of the display devices DS1a and DS1b due to the influence of noise or the like.

However, for example, even though the LVDS relay boards 27a and 27b are used, the transmission distance of the LVDS signal as a whole is considerably long (for example, 1 m or more). Therefore, when common mode noise is superimposed on the LVDS signal line, the LVDS signal line is overlapped. The signal line functions as an antenna, and a harmful level of EMI (Electro Magnetic Interference) noise is radiated.

Therefore, in this embodiment, in the LVDS relay boards 27a and 27b, the common mode choke coil CH (FIG. 9) is arranged in each LVDS signal line to prevent EMI. Also, because of the use of game balls, electrostatic discharge (ESD: Electro-Static Discharge) is a concern, so ESD protection devices are placed on the LVDS relay boards 27a and 27b to protect electronic elements and prevent EMI noise. The occurrence is suppressed to a minimum. Note that these points will be described later based on FIGS. 9 to 11.

Returning to FIG. 2(a) and continuing the description, an ordinary symbol display section 18 is provided on the right side of the pair of display devices DS1a, DS1b, and the ordinary symbol relating to the winning lottery is variably displayed. ing.

In the game area where the game balls fall and move, the first symbol starting opening 15a, the second symbol starting opening 15b, the first big winning opening 16a, the second big winning opening 16b, and the gate 17 are arranged. .. Each of these winning openings 15 to 17 has a detection switch inside so that the passage of a game ball can be detected.

At the upper part of the first symbol starting port 15a, after the game ball that has entered from the introduction port IN moves in the shape of a seesaw or roulette wheel, the production stage 14 configured to be able to win the first symbol starting port 15a is arranged. There is. Then, when the game ball wins the first symbol starting port 15a or the second symbol starting port 15b, the display device DS1a, DS1b, the special symbol fluctuating operation is started.

The second symbol starting port 15b is configured to be opened and closed by an electric tulip having a pair of left and right opening and closing claws, and when the normal symbol of the normal symbol display unit 18 is stopped in a predetermined mode, only for a predetermined time, Alternatively, the opening/closing claw is opened until a predetermined number of game balls are detected.

In the normal symbol display portion 18, when the game ball that has passed through the gate 17 is detected, the normal symbol changes for a predetermined time, and is determined by the lottery random number value extracted when the game ball passes through the gate 17. Display the stop pattern and stop.

The first special winning opening 16a is configured to include a slide board that moves forward and backward, and the second special winning opening 16b is configured to include an opening/closing plate whose lower end is pivotally supported and which is opened forward. .. The operations of the first big winning opening 16a and the second big winning opening 16b are not particularly limited, but in this embodiment, the first big winning opening 16a corresponds to the first symbol starting opening 15a, and the second big winning opening. 16b is constituted so as to correspond to the first symbol starting port 15b.

That is, when the game ball wins the first symbol starting port 15a, the variation operation of the special symbol is started, and after that, when the predetermined special symbol (big hit first symbol) is aligned, the first special jackpot special game is started, The slide board of the first big winning opening 16a is opened to the front to facilitate the winning of game balls.

On the other hand, as a result of the variation operation started by the winning of the game ball to the second symbol starting port 15b, when a predetermined special symbol (big hit second symbol) is aligned, the second big hit special game is started, and the second major. The opening/closing plate of the winning opening 16b is opened to facilitate the winning of the game ball. The game value of the special game (big hit state) is variously different according to the big hit symbols to be arranged, but which game value is given is based on the lottery result according to the winning timing of the game ball in advance. It is determined.

In a typical big hit state, after the opening/closing plate of the special winning opening 16 is opened, the opening/closing plate is closed when a predetermined time elapses or when a predetermined number (for example, 10) of game balls are won. Such an operation is continued up to 15 times, for example, and is controlled to be advantageous to the player. In addition, when the stop symbol after the change of the special symbol is the specific symbol, a privilege that the game after the special game is in the high probability state (probably changed state) is provided.

FIG. 4 is a block diagram showing the entire circuit configuration of a pachinko machine GM that realizes each of the above-described operations, and FIG. 5 shows a part thereof in detail.

As shown in FIG. 4, this pachinko machine GM receives the AC24V, and outputs various DC voltages, power supply abnormality signals ABN1 and ABN2, a system reset signal (power supply reset signal) SYS, and the like, and a game control operation. And a control command received from the main control board 21, and a control board 23 that integrally performs various effect operations based on the control command CMD received from the main control board 21. A payout control board 25 for controlling the payout motor M based on CMD' to pay out the game ball, and a launch control board 26 for launching the game ball in response to the operation of the player are mainly configured.

On the main control board 21 and the payout control board 25, one-chip microcomputers each having a built-in 8-bit CPU are arranged to execute respective control operations. Further, on the effect control board 23, the composite chip 50 having the built-in CPU circuit 54 and the VDP circuit 56 built therein is arranged, and the CPU 60 of the built-in CPU circuit 54 provides the lamp effect, the sound effect, the image effect, and the accessory effect. The included production operation is controlled in a unified manner.

In this specification, the control boards 21, 23, 25 and the operations realized by the circuits mounted on the related boards are functionally collectively referred to as a main control section 21, a performance control section 23, and a payout control. Sometimes referred to as part 25. In addition, with respect to the main control unit 21, all or part of the effect control unit 23 and the payout control unit 25 are sub-control units.

As shown in FIG. 4, on the effect control board 23, a program memory 53 for storing a control program for controlling the above-described unified effect operation, a CGROM 53 for storing image effect material data, and a CPU 60 used as a work area. A DRAM 52 and the like are provided.

As shown in the figure, on the production control board 23, a production IF board 22 that transfers the control command CMD output by the main control board 21 and a liquid crystal that transfers the LVDS signal output by the VDP circuit 56 to the display devices DS1a and DS1b. The IF substrate 24 and the male connector and the female connector are directly connected and integrated without passing through a wiring cable.

The two systems of LVDS signals output from the VDP circuit 56 are transmitted to the LVDS relay boards 27a and 27b via the liquid crystal IF board 24, and the substantially identical LVDS signals regenerated therein are displayed on the display device DS1a. , DS1b.

As shown in FIGS. 5 and 9, the display devices DS1a and DS1b have a built-in conversion circuit that performs De-serialize processing on the LVDS signal, and each RGB signal of 8-bit length, the vertical synchronization signal VSYNC, and the horizontal synchronization signal. A display screen is constructed based on the signal HSYNC, the enable signal DE, and the dot clock. In the case of the embodiment, each display device DS1a, DS1b has 800×600 pixels and the vertical synchronizing signal is 60 Hz, so the pixel clock is about 40 MHz.

The liquid crystal IF board 24 is equipped with a clock circuit (real time clock) RTC capable of measuring the current time and a memory element (Static Random Access Memory) SRAM for storing game record information.

On the other hand, the production IF board 22 is controlled by the CPU 60 of the built-in CPU circuit 54 to reproduce a voice signal for realizing a voice production, a voice ROM 38 for storing basic data of the voice production, and a voice processor 37. And a digital amplifier 39 that amplifies the audio signal output by the class D amplifier.

As shown in the figure, a lamp drive board 28 and a motor drive board 29 are connected to the production IF board 22, and the lamp production and the motor production (characteristic production) are performed based on the control of the CPU 60 of the built-in CPU circuit 54. , Are being realized.

A plurality of effect motors Mi and drive motors MOL, MOR are connected in series to the motor drive board 29 of the present embodiment, and the drive motors MOL, MOR realize the vertical movement of the display devices DS1a, DS1b. (See Figure 3). An origin sensor is arranged in each motor, and the sensor signal SNi, which is the output of each origin sensor, is configured to be acquired by the CPU 60 via the motor drive board 29.

By the way, the pachinko machine GM is roughly divided into a frame side member GM1 surrounded by a broken line in FIG. 4 and a board side member GM2 fixed to the back surface of the game board 5. The frame-side member GM1 includes a front frame 3 to which a glass door 6 and a front plate 7 are pivotally attached, and a wooden outer frame 1 on the outer side thereof. Fixedly installed in. On the other hand, the board side member GM2 is replaced in response to a model change, and a new board side member GM2 is attached to the frame side member GM1 instead of the original board side member. In addition, everything except the frame side member 1 is the board side member GM2.

As shown by the broken line frame in FIG. 4, the frame side member GM1 includes a power supply board 20, a payout control board 25, a firing control board 26, a frame relay board 34, a lamp drive board 35, and a motor drive board 36. , And a sensor and switch board BD having a shift register for receiving a motor origin sensor signal and other button signals, and these circuit boards are fixed to appropriate positions of the front frame 3, respectively.

On the other hand, on the back surface of the game board 5, a main control board 21 and an effect control board 23 are fixed together with the display devices DS1 and DS2 and other circuit boards. The frame-side member GM1 and the board-side member GM2 are electrically connected by the connection connectors C1 to C4 centrally arranged at one place.

The power supply board 20 is connected to the main board relay board 31 through the connection connector C2, and is connected to the power supply relay board 32 through the connection connector C3. The power supply board 20 is provided with a power supply monitoring unit MNT that monitors whether the AC power supply is turned on or off. When detecting that the AC power supply is turned on, the power supply monitoring unit MNT maintains the system reset signal SYS at the L level for a predetermined time and then transitions it to the H level.

Further, the power supply monitoring unit MNT, when detecting the interruption of the AC power supply, immediately causes the power supply abnormality signals ABN1 and ABN2 to transition to the L level. The power supply abnormality signals ABN1 and ABN2 quickly reach the H level after the power is turned on.

By the way, the system reset signal of the present embodiment is generated by the DC power supply based on the AC power supply. Therefore, after detecting the turning on of the AC power supply (usually the power switch is ON) and increasing to the H level, the H level is maintained unless the DC power supply voltage drops to the abnormal level. Therefore, the system reset signal SYS does not reset the CPU even when the AC power supply is in the power failure state while the DC power supply voltage is maintained. The power supply abnormality signals ABN1 and ABN2 are output even when the AC power supply is in a momentary power failure state.

The main board relay board 31 outputs the power supply abnormality signal ABN1 output from the power supply board 20, the backup power supply BAK, and DC5V, DC12V, DC32V as they are to the main control unit 21. On the other hand, the power relay board 32 outputs the system reset signal SYS received from the power board 20 and the AC and DC power supply voltages to the production IF board 22 as they are. Then, the production IF board 22 outputs the received system reset signal SYS to the production control unit 23 as it is.

On the other hand, the payout control board 25 is directly connected to the power supply board 20 without the intermediary of the relay board, and the power supply abnormality signal ABN2 and the backup power supply BAK similar to those received by the main control unit 21 are directly supplied together with other power supply voltages. I am receiving it.

The system reset signal SYS output from the power supply board 20 is a power supply reset signal indicating that the AC power supply 24V has been turned on to the power supply board 20, and the built-in CPU circuit 54 of the effect control unit 23 causes other power supply reset signals to be generated. The power is reset together with the circuit elements and the internal circuit including the VDP 56.

However, the system reset signal SYS is not supplied to the main controller 21 and the payout controller 25, and a power reset signal (CPU reset signal) is generated in the reset circuits RST of the respective circuit boards 21 and 25. ing. Therefore, for example, even if the connector C2 rattles or noise is superimposed on the wiring cable, there is no possibility that the CPUs of the main control unit 21 and the payout control unit 25 are abnormally reset.

The effect control unit 23 subordinately executes the effect operation based on the control command CMD from the main control unit 21, so that the power supply board 20 outputs the signal to avoid complication of the circuit configuration. The system reset signal SYS is used.

The reset circuits RST provided in the main control unit 21 and the payout control unit 25 each have a watchdog timer built therein, and each CPU of the control units 21 and 25 can receive a clear pulse from the CPUs of the control units 21 and 25 as long as it does not receive the clear pulse. Is forcibly reset.

Further, in this embodiment, the RAM clear signal CLR is generated by the main controller 21 and transmitted to the one-chip microcomputers of the main controller 21 and the payout controller 25. Here, the RAM clear signal CLR is a signal for determining whether or not to initialize all the areas of the built-in RAM of the one-chip microcomputer of each of the control units 21 and 25, and turns on the initialization switch SW operated by the staff. It has a value corresponding to the /OFF state.

The main control unit 21 and the payout control unit 25 receive the power supply abnormality signals ABN1 and ABN2 from the power supply board 20 to start necessary end processing prior to power failure or business end. Further, the backup power supply BAK is a DC 5V DC power supply that retains the data of the built-in RAM of the one-chip microcomputers of the main control unit 21 and the payout control unit 25 even after the AC power supply 24V is shut off due to the closing of business or power failure. Therefore, the main control unit 21 and the payout control unit 25 can restart the game operation before power-off after power-on (power-source backup function). This pachinko machine is designed so that the stored contents of the RAM of each one-chip microcomputer are retained for at least several days.

As shown in FIG. 4, the main control unit 21 sends a control command CMD′ to the payout control unit 25 via the main board relay substrate 31, while the payout control unit 25 shows a payout operation of a game ball. The prize ball counting signal, the status signal CON relating to the abnormality in the payout operation, and the operation start signal BGN are received.

Further, the main controller 21 is connected to each game component of the game board 5 via the game board relay board 30. Then, while receiving a switch signal of a detection switch built in each of the winning openings 16 to 17 on the game board, it drives a solenoid such as an electric tulip.

As described above, the production IF board 22, the production control board 23, and the liquid crystal IF board 24 are integrated by connector connection, and the production control unit 23 is connected to the power supply board 20 via the power relay board 32. It receives the DC voltage of each level and the system reset signal SYS.

As shown in FIG. 5, the built-in CPU circuit 54 of the effect control board 23 receives the system reset signal SYS and other signals via the input buffer 40 of the effect IF board 22. Specifically, the parallel port (PIO) 62 of the built-in CPU circuit 54 receives the control command CMD and the strobe signal STB via the input buffer 40.

Then, the built-in CPU circuit 54 of the effect control unit 23 executes the effect operation based on the control command CMD. Specifically, the serial port (SIO) 61 of the built-in CPU circuit 54 serially transmits the lamp drive signal SDATA to the driver ICs mounted on the lamp drive boards 28 and 35 in synchronization with the clock signal CK. As a result, a lamp group composed of a large number of LED lamps and illuminated lamps is driven to realize a lamp effect based on the control command CMD.

Similarly, the serial port 61 of the built-in CPU circuit 54 serially transmits the motor drive signal SDATA in synchronization with the clock signal CK to the driver ICs mounted on the motor drive boards 29 and 36, thereby providing a control command. It realizes a character effect based on CMD.

As shown in FIG. 5, in this embodiment, five channels (CH0 to CH4) of the serial port 61 realize five serial lines (see CK0 to CK4). The clock signal CK0 and the drive signal SDATA0 are transmitted to the drive substrate 36 and the lamp drive substrate 35. The drive signal SDATA0 is a serial signal that is a combination of the lamp drive signal and the motor drive signal.

Then, after a series of serial signals SDATA0 is serially transmitted in synchronization with the clock signal CK0, a latch signal LT0 is output from the parallel port 62 and is transmitted to all the driver ICs via the output buffer 43 all at once. As a result, each driver IC acquires the serial signal SDATA0 transmitted to itself.

Further, the clock signal CK1 is transmitted to the motor & switch board BD via the output buffer 43, and the sensor signal and the switch signal acquired by the shift register (not shown) of the sensor & switch board BD are transmitted. , Is serially transmitted in synchronization with the clock signal CK1, and the serial signal SDATA1 is transmitted to the serial port 61 via the input buffer 41.

Prior to a series of serial transmission, the parallel port 62 outputs the latch signal LT1 to the motor & switch board BD, and the sensor & switch board is synchronized with the latch signal LT1. The BD shift register serially converts the sensor signal and the switch signal.

The above points also apply to the lamp driving board 28 and the motor driving board 29. That is, the serial port 61 transmits the clock signal CK2 and the drive signal SDATA2 to the lamp drive board 28 via the output buffer 44 to realize the lamp effect. After a series of serial transmissions, the parallel port 62 outputs the latch signal LT2.

On the other hand, the serial port 61 transmits the clock signal CK3 and the drive signal SDATA3 to the motor drive board 29 via the output buffer 45 to realize a necessary accessory effect. In this case also, the latch signal LT3 is output from the parallel port 62 after a series of serial transmissions.

The motor drive board 29 updates the motor drive signal based on the latch signal LT3 to drive the effect motors M1 to Mi and the drive motors MOL and MOR. As described above, each of the motors M1 to Mi, MOL, and MOR is provided with an origin sensor, and the sensor signal SNi of each origin sensor is input in parallel to the shift register arranged on the motor drive board 29. It is configured to be transmitted to the terminal.

Corresponding to this configuration, the parallel port 62 outputs the latch signal LT4 to the shift register of the motor drive board 29 via the output buffer 45, and then the serial port 61 passes through the output buffer 45. The clock signal CK4 is transmitted to the shift register of the motor drive board 29.

The sensor signal SNi serially converted in synchronization with the latch signal LT4 is serially transmitted in synchronization with the clock signal CK4, and the serial signal SDATA4 is transmitted to the serial port 61 via the input buffer 42 and then to the CPU 60. To be acquired.

Next, the effect control unit 23 will be described in detail with reference to FIGS. 6 to 8. First, FIG. 6A is a circuit block diagram illustrating the composite chip 50 forming the effect control unit 23, including the related circuit elements. As shown, the composite chip 50 of the embodiment has a built-in CPU circuit 54 and a VDP circuit 56 built therein. The built-in CPU circuit 54 and the VDP circuit 56 are connected through the CPUIF circuit 55 that relays the transmission/reception data of each other, and a V blank interrupt signal (VBLANK) is supplied from the VDP circuit 56 to the built-in CPU circuit 54. It is supposed to be done.

Here, the V blank interrupt signal corresponds to the vertical synchronizing signal of the display device DS1a, and defines the timing at which the output of the image data of one frame of the display device DS1a is completed every 1/60 seconds. In this embodiment, of the three display circuits 74A/74B/74C, the display circuits 74A/74B function steadily, but the display circuits 74B and 74A have the same configuration and are synchronized. Since it operates, the vertical synchronizing signal (V blank interrupt signal) practically means that the output operation of the display circuits 74A/74B has ended.

Although the sequence operation based on the V blank interrupt will be described later, the CPUIF circuit 55 has a control memory (PROGRAM_ROM) 51 for storing a control program and necessary control data in a nonvolatile manner, as shown in FIG. Is connected to a work memory (RAM) 57 having a storage capacity of, and each is configured to be accessible from the built-in CPU circuit 54.

The built-in CPU circuit 54 is a circuit having a performance equivalent to that of a general-purpose one-chip microcomputer. The built-in CPU circuit 54 centrally controls the image effect and other effect operations based on the control program of the control memory 51, and the program is in a runaway state. Then, a watchdog timer (WDT) 58 forcibly resetting the CPU, a RAM 59 having a storage capacity of about 16 kbytes and used as a work area of the CPU, and a DMAC (Direct Memory) for realizing data transfer without going through the CPU Access controller) 63, a serial port (SIO) 61 having a plurality of input ports Si and an output port So, and a parallel port (PIO) 62 having a plurality of input ports Pi and an output port Po. ing.

As described above, the four channels (CH0 to CH4) of the serial port 61 are serial transmission of motor drive data (CH0, CH2), serial transmission of lamp drive data (CH4), and serial reception of sensor signals (CH1). , CH4).

In this specification, the expressions serial port 61 and parallel port 62 are used for the sake of convenience, but in the production control unit 23, the serial port 61 and the parallel port 62 have inputs that operate independently. Contains ports and output ports. This also applies to the input/output circuit 64p and the input/output circuit 64s described below.

The parallel input/output port 62 is connected to an external device (production control board 22) through an input/output circuit 64p. Then, as described with reference to FIG. 5, the CPU 60 receives the control command CMD and the interrupt signal STB output from the main control unit 21 via the input circuit 64p and the parallel input port Pi.

Next, the VDP circuit 56 will be described. The VDP circuit 56 includes a CGROM 53 that stores compressed data that is a constituent element of a still image or a moving image that forms an image effect, and an external DRAM (Dynamic) having a storage capacity of about 4 Gbit. The Random Access Memory) 52 and the pair of display devices DS1a and DS1b are connected. As shown in the figure, the display devices DS1a and DS1b receive the LVDS signals LVDS1 and LVDS2 via the LVDS relay boards 27a and 27b.

In this embodiment, the CGROM 53 is composed of a flash SSD (solid state drive) composed of a NAND flash memory having a storage capacity of about 62 Gbits, and is structured to obtain necessary compressed data by serial transmission. .. Therefore, the problem of skew (difference in transmission speed for each bit data) that is inevitable in parallel transmission is solved, and extremely high-speed transmission operation becomes possible.

The NAND flash memory is mechanically more stable than a hard disk and can be accessed at high speed, but since it is a sequential access memory, the access speed is higher than that of DRAM or SRAM (Static Random Access Memory). Inferiorly, the access speed becomes slower in the order of built-in VRAM 71>external DRAM 52>CGROM 53. However, by performing a preload operation of reading a group of compressed data (CG data) into the DRAM 52 prior to the drawing operation, smooth random access of the CG data during the drawing operation can be realized.

In detail, the VDP circuit 56 includes a register group 70 in which various operation parameters that define the operation of VDP are set, and about 48 Mbytes used when generating image data to be displayed on each of the display devices DS1a and DS1b. A VRAM (Video RAM) 71, a data transfer circuit 72 that controls data transmission/reception between each unit inside the chip and data transmission/reception with the outside of the chip, a preloader 73 that executes a preload operation, and image data of the VRAM 71 is read and appropriately read. Display circuits 74 of three systems (A/B/C) that execute various image processings in parallel, a graphics decoder 75 that decodes compressed data read from the CGROM 53, and still image data and moving image data after decoding as appropriate. , A drawing circuit 76 that generates image data for one frame of each of the display devices DS1a and DS1b, a geometry engine 77 that generates a stereoscopic image by appropriate coordinate conversion as part of the operation of the drawing circuit 76, and a serial circuit. An SMC unit 78 capable of transmitting and receiving data, an output selecting unit 79 for appropriately selecting and outputting the outputs of the three systems (A/B/C) of the display circuit 74, and image data output by the output selecting unit 79 is converted into an LVDS signal. Two systems of LVDS units 80a and 80b, a digital RGB unit 80c that outputs image data output by the output selection unit 79 in parallel as digital RGB signals, and a CPUIF unit 81 that relays data transmission/reception with the CPUIF circuit 55. It comprises a CG bus IF unit 82 for relaying data reception from the CGROM 53, a DRAM IF unit 83 for relaying data transmission/reception with the external DRAM 52, and a VRAMIF unit 84 for relaying data transmission/reception with the VRAM 71. There is.

Although not particularly limited, in this embodiment, among the display circuits 74 of three systems (A/B/C), the display circuit 74A corresponds to the first LVDS section 80a, and the display circuit 74B corresponds to the second LVDS section 81b. The display circuit 74C corresponds to the digital RGB unit 80c. Then, the first LVDS signal LVDS1 and the second LVDS signal LVDS2 are transmitted to the display devices DS1a and DS1b via the LVDS relay boards 27a and 27b, respectively. When the third display device is arranged, the display circuit 74C and the digital RGB unit 80c are used (see FIG. 14C), but they are not used in the embodiment shown in FIG. ..

FIG. 6B shows the relationship between the CPUIF unit 81, the CG bus IF unit 82, the DRAMIF unit 83, the VRAMIF unit 84, and the register group 70, the CGROM 53, the DRAM 52, and the VRAM 71, and particularly, the register group. Regarding 70, a part thereof is specifically described. As shown in the figure, the CGROM 53 and the CG bus IF unit 82 are connected by a serial line, the CGROM 53 is sequentially accessed in response to the transmission of the address information Tx, and a group of CG data (compressed data) Rx is sequentially read. It is supposed to be.

In the present embodiment in which the preloader 73 does not function, the CG data read from the CGROM 53 is stored in the VRAM 71 via the CG bus IF unit 82→VRAMIF unit 84, but the arrow at the timing T1+δ in FIG. This read operation is shown. As shown in FIG. 7, in the VRAM 71, a still image decoding area and a moving image decoding area are secured as work areas of the graphics decoder 75, and the CG data is in a compressed state at a position corresponding to the type of CG data. It is stored as is. Further, as shown in FIGS. 7 and 8, the VRAM 71 also secures a frame buffer FB area in which image data for one frame after decoding is arranged.

On the other hand, when the preloader 73 is made to function, the CG data is stored in the preload area of the DRAM 52 via the CG bus IF section 82→DRAM IF section 83 prior to the timing required for the decoding process, and thereafter, the CG data is required. At random timing, random access is performed and the data is transferred to the VRAM 71. However, the CG data stored in the still image decoding area or the moving image decoding area of the VRAM 71 is decoded by the graphics decoder 75 and then the drawing circuit 76 causes the frame of the VRAM 71 to be displayed regardless of whether the preloader 73 functions. It is expanded in a proper place in the buffer FB area. The arrow at the timing T1+δ' in FIG. 7 indicates this operation.

Returning to FIG. 6A and continuing the description, the data transfer circuit 72 uses the resource (storage medium) inside the VDP circuit and the external storage medium as a transfer source port or a transfer destination port, and performs a data transfer operation between them. Is a circuit for executing. The transfer source port includes a storage medium (resource) connected to the CPU bus, the CG bus, and the external DRAM bus in addition to the VRAM 71. Similarly, the transfer destination port includes a storage medium connected to the CPU bus, the CG bus, and the external DRAM bus in addition to the VRAM 71. Further, the data transfer circuit 72 is also in charge of the operation of transmitting the display list DL for specifying the display image for one frame to the drawing circuit 76 (preloader 73 when necessary) by a group of drawing commands.

The preloader 73 is a circuit that interprets the display list DL transmitted by the data transfer circuit 72 and transfers the CG data in the CGROM 53 referred to in the display list DL to a preloaded area of the DRAM 52 that is designated in advance. Further, at this time, the preloader 73 outputs the display list DL in which the reference destination of the CG data is rewritten to the transferred address. Then, the rewritten display list DL is transmitted to the drawing circuit 76 by the data transfer circuit 72.

However, in this embodiment, the preloader 73 is not used. On the other hand, when the preloader 73 is used, a sufficient preload area of the storage area is set in the external DRAM 52 based on the setting value in the preloader register (see FIG. 6B). Then, in this case, unless the storage area set as the preload area is used up, the preloaded compressed data is maintained without being overwritten and erased by the subsequent compressed data. Therefore, in the second embodiment using the preload process, the CGROM 53 is accessed only when the necessary compressed data does not exist in the preload area. Since a sufficient storage area is secured in the preload area, even if the CG data for a plurality of frames is preloaded at once, no problem will occur.

The drawing circuit 76 sequentially analyzes the drawing commands of the display list DL (see timing T1′ in FIG. 7) transferred from the built-in RAM 59 to the external DRAM 52 by the data transfer circuit 72, and draws the graphics decoder 75 and the geometry. This is a circuit that cooperates with the engine 77 and the like to draw an image of one frame of the display devices DS1a and DS1b in the frame buffer FB formed in the VRAM 71.

That is, the drawing circuit 76 includes a Displaylist Analyzer (hereinafter, referred to as a DL analyzer) that analyzes a drawing command of the display list DL, a Geometry Pipeline that executes coordinate conversion of a vertex and an illumination operation, a source address and a destination when drawing a triangle. Triangle Rasterizer that generates the address, Texture Sampler that samples the texture and performs bilinear filtering, Framebuffer Sampler that acquires the frame buffer and Z buffer for inter-pixel calculation, and α-blending etc. It is configured to include a Pixel Generator that generates pixel data to be written in the FB.

Here, the display list DL is composed of a group of drawing commands described in the order of drawing, and also includes a command that defines what kind of image is drawn at which position in one frame. The storage location (source address) of the CGROM or the like of the power image is also specified. Then, the DL analyzer of the drawing circuit 76 interprets such a display list DL and cooperates with other Geometry Pipelines, Triangle Rasterizers, Texture Samplers, Framebuffer Samplers, and Pixel Generators to secure the frames secured in the built-in VRAM 71. Image data for one frame of each of the display devices DS1a and DS1b is generated in the buffer FB (see FIG. 8).

The display list DL of this embodiment is roughly divided into a drawing command group for the display device DS1a and a drawing command group for the display device DS1b.

As shown in FIG. 8, the frame buffer FB of this embodiment is divided into three sections (FBa, FBb, FBc) corresponding to the display circuits 74A/74B/74C, but each frame buffer FB (FBa, FBb, The drawing position of FBc) is specified by a predetermined drawing command described in the display list DL.

Image data for one frame (800×600 pixels) of the display device DS1a is arranged in the frame buffer FBa, and image data for one frame (800×600 pixels) of the display device DS1b is arranged in the frame buffer FBb. To be done.

Since the display circuit 74C is not used in this embodiment, the frame buffer FBc does not function. Each of the functioning frame buffers FB (FBa, FBb) is a double buffer functionally divided into a drawing area and a display area, and the two areas (area 0 and area 1) are used alternately. Switched and used. That is, when the drawing circuit 76 is writing the image data in either one of the two areas, the display circuit 74 reads out and outputs the image data in the other area.

Although not particularly limited, in this embodiment, one frame of the display devices DS1a and DS1b is composed of three or more kinds of images (moving image and still image) in the maximum state. That is, the display devices DS1a and DS1b are configured such that, in the maximum state, one or a plurality of moving images are played back, while a still image that changes over time is displayed so as to be superimposed on the background image. ..

The basic shape of a still image is stored in advance in the CGROM 53 as a sprite image, and the basic shape is appropriately enlarged/reduced/rotated/deformed, and the arrangement position is changed to realize temporal change. ing. On the other hand, a moving image is a so-called movie that changes smoothly for a predetermined time, and a plurality of frames are stored in the CGROM 53 after being compressed by a moving image compression method such as the MPEG encoding method.

Although not particularly limited, the moving image of this embodiment is an IP stream moving image composed of I frames and P frames. Here, the P frame means a frame configured by a P picture (Predictive Picture) that encodes a difference from data predicted from a past frame, and although the compression rate is high, sequential reproduction is essential. On the other hand, the I frame means a frame composed of an I picture (Intra Picture) that can be independently encoded without depending on other frames.

In response to such a configuration, the graphics decoder 75 is divided into a still image decoder and a moving image decoder, and decodes a still image and a moving image encoded (compressed) by a predetermined compression algorithm by a corresponding expansion algorithm. (Stretched). For example, a still image is compressed by a predetermined algorithm for each image data that constitutes one still image, and P frames of an IP stream moving image are a plurality of still image data that realizes a series of moving images. It is compressed based on the data difference value.

Next, the display circuit 74 is a circuit that reads out the image data from the frame buffer FB, performs final image processing, and then outputs the image data (see FIG. 8). As shown in FIG. 8, in the image processing in the display circuit 74, a scaler functions to perform scaling processing for enlarging/reducing a frame image, delicate color correction processing, and dither for minimizing a quantization error of the entire image. Ring processing and are included. Note that the scaling processing includes enlargement processing of the frame data after the moving image decoding for the vertically reduced moving image data (vertical reduced data).

As shown in FIG. 8, three systems of display circuits 74A/74B/74C for performing the above-described operations in parallel are provided, and each display circuit 74A/74B/74C has a corresponding frame buffer FBa/FBb. The image data of /FBc is read out and the above-mentioned final image processing can be executed. Then, after these image processes, digital RGB data (total of 24 bits) is output to the output selection circuit 79 together with the horizontal synchronizing signal HSYNC and the vertical synchronizing signal VSYNC.

The output selection unit 79 transmits the output signal of the display circuit 74A to the LVDS unit 80a and the output signal of the display circuit 74B to the LVDS unit 80b. Then, as described above, the LVDS unit 80a and the LVDS unit 80b convert the image data (digital RGB data of 24 bits in total) into an LVDS signal, and add a pair for transmitting the clock signal to all five pairs of differences. The motion signals LVDS1 and LVDS2 are output to the LVDS relay boards 27a and 27b.

Next, the SMC unit 78 (Serial Management Controller) is a composite controller that incorporates an LED controller and a Motor controller. However, since the serial port (SIO) 61 is used in this embodiment, the SMC unit 78 is not used.

Regarding the internal circuit of the VDP circuit 56 and the operation thereof, the operation content to be executed by the internal circuit is defined by the operation parameter (set value) set in the register group 70 by the CPU 60, and the execution state of the VDP circuit 56 is It can be specified by READing the operation status value of the register group 70. The register group 70 means a large number of registers mapped in a memory space (0 to FFFFFH) of about 1 Mbyte on the memory map of the CPU 60, and the CPU 60 causes the WRITE (setting) of the operation parameter via the CPUIF unit 81. The operation and the READ operation of the operation status value are executed (see FIG. 6B).

In the register group 70, a "system control register" in which initial setting values related to system operations such as interrupt operations are written, and setting values related to data transfer processing by the data transfer circuit 72 between the CPU 60 and the internal circuit of the VDP circuit 56. "Data transfer register" in which is written, "GDEC register" in which the execution status including the error occurrence of the graphics decoder 75 can be specified, and "Drawing register" in which drawing commands and setting values for the drawing circuit 76 are written , A "preloader register" in which setting values related to the operation of the preloader 73 are written, a "display register" in which setting values related to each operation of the three-divided display circuits A/B/C are written, and an LED controller ( The "LED control register" in which the setting values for the SMC unit 78) are written and the "motor control register" in which the setting values for the Motor controller (SMC unit 78) are written are included. These control registers are Each is composed of multiple bytes.

More specifically, in the "preloader register", (1) setting whether to set the preload area in the DRAM 52 or the VRAM 84, (2) the start address of the preload area, and (3) the preload data area, The number of frames to be used is set, and (4) the data size per frame is set. Further, the data transfer source and the data transfer destination are set in the “data transfer register”, and the start position of the frame buffer FBa/FBb/FBc is set in the “display register” in correspondence with the display circuit A/B/C. Also, a buffer size, a switching instruction between a drawing area and a display area that are temporally switched in each frame buffer FBa/FBb/FBc, a vertical/horizontal enlargement ratio of a scaler, and the like are set. Further, the "drawing register", "preloader register", and "data transfer register" are instructed to start the execution of each of the drawing operation, preload operation, and data transfer operation.

In any case, the CPU 60 writes an appropriate set value to any of the register groups 70, thereby realizing the internal operation of the VDP circuit 56. Therefore, the CPU 60 realizes the image effect based on the display list DL based on the display list DL updated at an appropriate time interval and the set values in the registers configuring the register group 70 described above.

Next, the LVDS relay boards 27a and 27b will be described with reference to FIGS. Since the two LVDS relay boards 27a and 27b have exactly the same circuit configuration and circuit operation, the LVDS relay board 27a will be mainly described below.

As shown in FIG. 9, the VDP circuit 56 (LVDS unit 80) and the LVDS relay board 27 are connected by five pairs of differential signal lines (LINE1 to LINE4+CLK), and the LVDS relay board 27 and the display device DS1. Are also connected by five pairs of differential signal lines.

The display device DS1 has a built-in RGB conversion unit that executes a De-Serialize operation. From the serial signals transmitted through the five pairs of differential signal lines, the RGB signal, the vertical synchronization signal VSYNC, and the horizontal synchronization signal are generated. The display screen is constructed by restoring HSSYC, the data enable signal DE, and the like.

A distributor (Repeater) 85 having an internal configuration shown in FIG. 10A is arranged on the LVDS relay board 27a. Although the differential signal line LINE3 and the LVDS input section RC1 and LVDS output section TC1 of the distributor are not shown in FIG. 8 for convenience of drawing, they are configured in the same manner as other sections. There is.

As shown in FIG. 10A, the distributor 85 of the embodiment operates at a power supply voltage of 3.3V and is divided into a 1stLink part and a 2ndLink part, and each is an LVDS receiver Rx and an LVDS transmitter Tx. Is configured. Each unit functions at a low voltage in which the power supply voltage 3.3V is stably dropped by a linear regulator LDO (Low Dropout).

Although not particularly limited, in the present embodiment, only the 1stLink unit is used, and the LVDS receiving unit Rx includes the LDVS signals LVDS1/LVDS2 shown in FIG. 11A from the LVDS units 80a/80b of the VDP circuit 56. Is supplied (see FIG. 10B). As shown in FIG. 11A, the LVDS signal is transmitted by the LVDS clock CLK corresponding to the pixel clock and the five pairs of differential signal lines denoted as LINE1 to LINE4, which are respectively transmitted from the LVDS receiving unit Rx. It is supplied to the RCLK1 terminal and RA1 to RD1 terminals.

In the case of the present embodiment, since the RGB signals generated by the VDP circuit 56 are each 8 bits long (256 gradations for each pixel), LVDS is obtained in one cycle of the LVDS clock CLK (about 1/40 μS in this embodiment). The unit 80a outputs a total of 28 bits obtained by adding the horizontal synchronizing signal HSYNC, the vertical synchronizing signal VSYNC, the DATA enable signal DE, and the reserve signal RS to 24 bits of the RGB signal.

Here, the DATA enable signal DE is a signal indicating whether the RGB signal is valid (drawing timing), that is, whether it is in the horizontal blanking period or the vertical blanking period, and the reserve signal RS in the present embodiment. , A dummy signal that is not used.

Five pairs of differential signals including these 28 bits are supplied to the RCLK1 terminal and RA1 to RD1 terminals of the LVDS receiving unit Rx, but as shown in FIG. 11(b), the RE1 terminal is not used. ing. That is, the distributor 85 can transmit RGB signals each having a 10-bit length (1024 gradations for each pixel), but handles only the upper 8 bits by removing the lower 2 bits.

The 28-bit data in total is subjected to De-serialize processing in the LVDS receiving unit Rx, and for each cycle of the LVDS clock CLK, an HSYNC signal 1 bit, a VSYNC signal 1 bit, a DE signal 1 bit, an R signal 8 bits, and a G signal. The signal is restored to 8 bits and the B signal to 8 bits.

Then, in this embodiment, the restored RGB signals and others pass through the Inter-Link Multiplex & De-Multiple section as they are and are supplied to the LVDS transmission section Tx (see FIG. 10B). Then, in the LVDS transmitter Tx, the LVDS signal is generated again by the Serialize process and is output to the five pairs of differential signal lines.

FIG. 11C shows this relationship, and shows a state in which the regenerated LVDS signal is output from the TCLK1 terminal and the TA1 to TD1 terminals. The TE1 terminal is in the open state like the RE1 terminal.

As described above, the distributor 85 of the embodiment not only restores the signal attenuation like a simple buffer circuit, but also intentionally places the HSYNC signal, the VSYNC signal, the DE signal, and the R signal 8 at the position of the LVDS relay board 27a. The bits, the G signal 8 bits, and the B signal 8 bits are intentionally restored, and the LVDS signal is regenerated again.

As described above, the transmission distance between the VDP circuit 56 and the LVDS relay board 27a is limited to the distance at which normal transmission of the LVDS signal is experimentally ensured. Therefore, when evaluated from the display device DS1a, the LVDS relay board is evaluated. When the VDP circuit 56 is present at the position of 27a, it becomes substantially the same.

Further, the transmission distance between the LVDS relay board 27a and the display device DS1a is also limited to the distance at which normal transmission of the LVDS signal is experimentally ensured, so that the display trouble of the display device is eliminated. The distance at which normal transmission is guaranteed depends on the internal configuration of the game machine and the environment of the game hall, but is typically within 1 m, preferably within 80 cm, and more preferably within 60 cm. By providing the relay board 27a, the total length of the LVDS transmission line can be up to about 2 m to 1.2 m.

The embodiment in which the Inter-Link Multiplex & De-Multiple section does not function has been described above. However, by causing the Inter-Link Multiplex & De-Multiple section to function, the LVDS signal supplied to the LVDS receiver Rx of the 1stLink section is supplied. It is also possible to divide the stripe and output the divided LVDS signal in which the pixel clock frequency (for example, 80 MHz) is reduced to ½ from the 1stLink unit and the LVDS transmitters Tx and Tx of the 2ndLink unit (FIG. 10C). Single In / Dual OUT).

Although such a configuration is adopted in the embodiment shown in FIG. 14B, a single LVDS relay board 27 is sufficient, and one distributor 85 arranged there is sufficient. Here, the stripe division means an operation of outputting the RGB image data of one pixel from the 1stLink section and the RGB image data of the other pixel from the 2ndLink section of the left and right pixels adjacent to each other in the horizontal direction of the display screen.

Further, by operating the Inter-Link Multiplex & De-Multiple section, a pair of LVDS signals supplied to the LVDS receivers Rx and Rx of the 1stLink section and the 2ndLink section are connected in stripes, and the pixel clock frequency is 2 It is also possible to output the doubled concatenated LVDS signal from the LVDS transmitters Tx and Tx of the 1stLink unit (Dual In/Single OUT in FIG. 10D).

Stripe concatenation means that the RGB image data for 1 pixel restored by the receiving unit of the 1stLink portion and the RGB image data for 1 pixel restored by the receiving unit of the 2ndLink portion are adjacent to each other at the same timing. This means an operation of generating a pixel and outputting it from the 1stLink section.

In such an operation of the distributor 85, a pair of LVDS signals LVDS1 and LVDS2 having a relatively low dot clock are transmitted to the vicinity of the display device, and the LVDS signal connected by the distributor 85 of the LVDS relay board 27 is displayed on the display device. It is suitable for the structure which supplies to.

Returning to FIG. 9 and continuing the description, as shown in FIG. 9, the LVDS relay substrate 27 is close to the distributor 85, and the terminating resistor R (about 100Ω) of the LVDS signal line and the common mode choke coil. CH and the discharge absorption element ESD are arranged.

Here, the common mode choke coil CH means a coil in which the winding directions of a pair of conducting wires wound around a single core are opposite to each other. Therefore, when in-phase currents flow through the pair of conducting wires, the directions of the magnetic fluxes are the same and a high inductance is generated, so that the common mode noise can be effectively suppressed.

In differential signal lines such as LVDS signal lines, in-phase signals such as common mode noise are canceled on the receiving side, so that they do not adversely affect the receiving element, but on the other hand, they are large for differential signal lines with a long transmission distance. When the level common mode noise flows, the differential signal line functions as an antenna to generate high frequency noise, which adversely affects the display device and other electronic circuits.

In consideration of such a point, in the present embodiment, the common mode choke coil CH is arranged in all the differential signal lines on the input side and the output side of the distributor 85 mounted on the LVDS relay board 27. (Electro Magnetic Interference) Noise is effectively suppressed. Since the original LDVS signal is a normal mode (differential mode) signal, the magnetic flux is canceled inside the core, so that the common mode choke coil CH does not function as an inductor.

Further, discharge absorbing elements ESD are arranged in all the differential signal lines on the input side of the distributor 85. The discharge absorbing element ESD may be a semiconductor base (zener diode type) or a varistor type as long as it is an element that quickly absorbs electrostatic discharge (Electro-Static Discharge). Is used to realize inter-electrode discharge different from the varistor (inter-electrode discharge type element).

Here, the inter-electrode discharge type element means an element in which internal electrodes are arranged opposite to each other in an insulating state and a discharge is generated between the internal electrodes when a high voltage is applied. By using such an element, the inter-terminal capacitance can be made smaller than that of the Zener diode type or varistor type element, and the effect of excellent repeatability is also exhibited.

In this type of gaming machine, there is a possibility that a high level of static electricity may accumulate due to the circulation of the game balls, and there is concern that electrostatic discharge may occur in the long LVDS signal line, but in the unlikely event that electrostatic discharge occurs. However, since the discharge absorbing element ESD momentarily turns on and immediately absorbs the discharge energy, damage to the distributor 85 and generation of EMI noise are prevented.

The voltage level of the static electricity charged in the game ball or the like is very high, but the stored energy itself is low, so the stored energy can be immediately extinguished by the momentary ON operation of the discharge absorption element ESD. Further, since the inter-terminal capacitance is lower than that of the Zener diode type or varistor type element, it does not adversely affect the transmission signal. Although the discharge absorption element ESD is shown in FIG. 9 by an equivalent circuit, it merely shows an equivalent function and does not include a Zener diode.

Next, referring to the flowcharts of FIGS. 12A to 12D and the operation explanatory diagrams of FIGS. 8 and 13, regarding the control operation of the image effect performed using the display devices DS1a and DS1b. explain. These image effects are realized by the CPU 60 of the effect control unit 23 that receives the control command CMD from the main control unit 21 and the VDP circuit 56 that functions by being instructed by the CPU 60. The instruction from the CPU 60 to the VDP circuit 56 is specified by the operation parameter written in the register group 70.

As shown in FIG. 12, the image effect operation is based on the display list DL update processing (FIGS. 12A to 12B) executed by the CPU 60 at predetermined time intervals and the display list DL received from the CPU 60. It is realized by the drawing circuit 76 that operates and the sequence operations of the display circuit 74 (FIGS. 12C to 12D ). Note that the CPU 60 sets necessary operation parameters in the register group 70 at the time of power reset and at necessary timing thereafter so that the drawing circuit 76 and the display circuit 74 realize the sequence operation described below. There is.

To explain based on the above, the CPU 60 starts the update processing of the display list DL at every constant time δ (for example, 1/30 seconds) defined by the V blank interrupt every 1/60 seconds (ST1), and draws. The sequence operation of the circuit 76 and the display circuit 74 is started (ST2). As described with reference to FIG. 6A, the V blank interrupt means that the output operation of the display circuit 74A is finished, but the drawing circuit 76 and the display circuits 74A and 74B are intermittently operated based on the process of step ST2. Therefore, it executes its own operation in parallel (see FIG. 13).

First, the sequence operation of the drawing circuit 76 and the display circuit 74 will be schematically described with reference to FIG. First, in the execution cycle starting from T1, the display list DL generated by the CPU 63 is interpreted by the drawing circuit 76 in the execution cycle starting from T1+δ, and the image data generated by the drawing circuit 76 is created in the frame buffers FBa and FBb. It In the display list DL, a series of drawing command strings that specify the display screens of the two display devices DS1a and DS1b are described in two sections.

In this embodiment, the drawing buffer 76 develops image data of 800×600 pixels in the frame buffers FBa and FBb. Then, these image data are output by the display circuits 74A and 74B in the execution cycle starting from T1+2δ. Therefore, in this embodiment, one unit operation for the image effect is completed after three execution cycles.

The above relationship is also described in FIG. 7A, and the CG data of the CGROM 53 is read to the VRAM 71 at the timing of T1+δ based on the display list DL transferred to the DRAM 52 at the timing of T1′ ( However, only when necessary), image data is created in the frame buffers FBa and FBb at the same execution cycle (timing T1+δ′). Then, this image data is output to the display device DS1a/DS1b through the two communication paths (80a/80b, 27a/27b) shown in FIG. 9 at the timing of T1+2δ.

Since the outline has been described above, subsequently, the process of step ST2 will be specifically described with reference to FIG. The CPU 60 sets a predetermined value in a predetermined display register corresponding to each of the display circuits 74A and 74B in order to switch the display areas of the display circuits 74A and 74B, and instructs the start of the display operation (ST10 to ST11).

As shown in FIG. 7, the frame buffers FBa and FBb have a double buffer structure (0/1), one of which is a drawing area to be accessed by the drawing circuit 76, and the other is an access of the display circuit 74. This is the target display area. Then, the drawing area and the display area are switched by the processing of steps ST10 to ST11, and the image data for one frame generated by the drawing circuit 76 in the frame buffers FBa and FBb by then is displayed in this execution cycle. The signals are output to the display devices DS1a and DS1b by the circuits 74A and 74B.

In the present embodiment, the operation cycle of the display circuits 74A and 74B is set to 1/60 seconds, whereas the operation cycle of the CPU 60 is 1/30 seconds, so the display circuits 74A and 74B are In reality, the same image data is output twice and the same frame is displayed twice in succession.

Along with the above processing (ST10 to ST11) for the display circuit 74, the CPU 60 instructs a predetermined drawing register that defines the operation of the drawing circuit 76 to start the operation of the drawing operation (ST12). As a result, the drawing circuit 76 also starts a predetermined operation every 1/30 seconds. It should be noted that the operation contents to be executed by the drawing circuit 76 and the display circuit 74 are set in the drawing register and the display register by the CPU 60 at the time of resetting the power supply and necessary timing thereafter, as described above.

Returning to FIG. 12B from FIG. 12B, to continue the description, the CPU 60 instructs the sequence operation of the drawing circuit 76 and the display circuit 74 in the process of step ST2 described above, and then based on the image rendering scenario. Then, the display list DL for the next frame is created. Here, the image effect scenario is a concrete embodiment of the image effect specified by the control command CMD received from the main control unit 21.

In other words, the image rendering scenario includes (1) a series of moving images that continue for a certain period of time, and still images (including background images and notice images) for which the drawing position, placement posture, and scaling ratio are appropriately defined. The start time and end time of the video effect of (2), which still image, which time, which position, how to draw, etc. are defined. It should be noted that even though it is a moving image effect, the drawn image on the display device only changes quickly and smoothly, and the same or different next image data (frame image data) is drawn on the display device at regular intervals. It is the same as the still image.

Then, the CPU 60 lists a group of drawing commands for identifying display images of the display devices DS1a, DS1b at each timing (T1, T1+δ, T1+2δ,...) With reference to the effect scenario having such a configuration. The generated display list DL is generated. The display list DL specifies, for a moving image, which part of the moving image that progresses in time by specifying the storage position of the CGROM 53, and for a still image such as a sprite image, is stored in the CGROM 53. It defines the position of the displayed image on the display device and how to draw it.

The drawing command sequence forming the display list DL is divided into two sections (DL=DLi1+DLi2) corresponding to the two display devices DS1a and DS1b, and such a display list DL transfers data instructed by the CPU 60. The data is transferred from the built-in RAM 59 to the external DRAM 52 by the circuit 72 (ST4). The arrow at the timing T1' in FIG. 7 illustrates this operation. Note that the CPU 60 does not need to generate one display list DL that specifies one frame of each display device for each operation cycle, and creates a plurality of display lists DL1, DL2... That specify display contents at a plurality of timings. , May be collectively generated in one operation cycle.

Further, in FIG. 13, the process of step ST13 by the CPU 60 is shown by a vertical arrow from the CPU 63 to the drawing circuit 76, and the process of steps ST10 to ST11 by the CPU 60 is shown from the CPU 63 to the display circuits 74A and 74B. It is indicated by a directional arrow.

Subsequently, a drawing operation executed by the drawing circuit 76, the graphics decoder 75, the geometry engine 77, and the like in cooperation with each other will be described with reference to FIGS. 12C to 12D and FIG. As shown in FIG. 13, this drawing operation is repeated every fixed time (δ), but for the sake of convenience, in the following description, the drawing operation after timing T1+2δ executed based on the display list DL1 after rewriting will be described. ..

The drawing circuit 76 sequentially analyzes the drawing commands described in the display list DL1 which is the oldest unprocessed display list among the display lists stored in the external DRAM 52 (FIG. 12C). SS20), the graphics decoder 75 and the geometry engine 77 are made to function with respect to the still image or moving image specified by the drawing command.

The still image data and moving image data decoded by the graphics decoder 75 are expanded and expanded in the still image decoding region and the moving image decoding region secured in the built-in VRAM 71 (SS22 to SS23). Then, the decoded still image data or moving image data is written in a predetermined position of the frame buffer FB (FBa, FBb) of the VRAM 71 in the drawing mode defined by the drawing command, thereby executing the drawing process ( SS24). Note that the drawing mode includes the drawing position in the frame buffer FB (FBa, FBb), but in the case of a sprite image or the like, the drawing posture, the enlargement/reduction ratio, etc. may be further specified. 77 works.

Since the frame buffers FBa and FBb each have a double buffer structure divided into a drawing area and a display area, in the drawing operation (SS24), more accurately, in the drawing areas of the frame buffers FBa and FBb. Will be written.

In this way, when the drawing process for all drawing commands is completed, the process stands by until the next drawing operation which is intermittently started (SS25). In FIG. 7, it is indicated by an arrow that a necessary image is drawn in the frame buffer FB (FBa+FBb) at the timing T1+δ′.

Finally, the operation of the display circuit 74 will be described with reference to FIG. This display operation is also repeated at regular time intervals (δ), but for the sake of convenience, in the following description, the display operation after timing T1+2δ shown in FIG. 13 will be described. As described above, at this timing, the image data (A1, B1) based on the display list DL1 is secured in the drawing areas of the frame buffers FBa, FBb. Then, this drawing area functions as a display area in the display operation after the timing T1+2δ.

As shown in FIG. 12D, the display circuits 74A and 74B read the image data (A1 and B1) stored in the display areas of the frame buffers FBa and FBb corresponding to the display circuits 74A and 74B and output them to the output selection unit 79. Yes (SS30). Here, the image data (A1) of the frame buffer FBa is image data that specifies one frame of the display device DS1a, and the image data (B1) of the frame buffer FBb is image data that specifies one frame of the display device DS1b. Is.

After that, based on the operation of the output selection unit 79, the image data (A1) of the frame buffer FBa output by the display circuit 74A is output as the LVDS signal LVDS1 via the LVDS unit 80a, and the frame output by the display circuit 74B. The image data (B1) in the buffer FBb is output as the LVDS signal LVDS2 via the LVDS unit 80b.

As shown in FIG. 9, the LVDS signal LVDS1 relating to the image data (A1) output by the LVDS unit 80a is regenerated by the LVDS relay board 27a and then transmitted to the display device DS1a to display an 800×600 pixel display screen. Realize.

Similarly, the LVDS signal LVDS2 relating to the image data (B1) output from the LVDS unit 80b is regenerated by the LVDS relay board 27b and then transmitted to the display device DS1b to realize a display screen of 800×600 pixels.

The above operation is the same not only in the display operation starting from the timing T1+2δ but also in the display operation starting from the timing T1+3δ. That is, in the display operation starting from the timing T1+3δ, the display circuits 74A and 74B output the image data A2 and B2 to be displayed on the respective display devices DS1a and DS1b.

Since the same operation is repeated thereafter, the image data Ai, Bi updated every 1/30 seconds is displayed on the display devices DS1a, DS1b. Since the display circuits 74A and 74B are initially set to operate every 1/60 seconds, the same image data Ai and Bi are continuously output twice as described above. Therefore, the moving image displayed on the display devices DS1a and DS1b has a reproduction speed of 30 fps (Frames Per Second).

The configuration in which the image data for one frame of the two display devices DS1a and DS1b is generated in the frame buffers FBa and FBb and the display circuits 74A and 74B function has been described above. However, the configuration is not particularly limited. Absent.

FIG. 14A shows that image data for one frame (stripe-connected image data) of two display devices DS1a and DS1b is collectively generated in the frame buffer FBa, and the output of the display circuit 74A is output to the output selection unit. 79 shows a configuration in which the stripe division is performed at 79 and the image data for one frame of the display devices DS1a and DS1b is divided.

Here, the stripe connection means that the RGB image data of each pixel of the two display devices DS1a and DS1b are horizontally adjacent to each other to generate a composite pixel. The stripe division means an operation of outputting the RGB image data of one pixel to the LVDS unit 80a and the RGB image data of the other pixel to the LVDS unit 80b for the composite pixels adjacent in the horizontal direction of the display screen. ..

The pair of LVDS signals LVDS1 and LVDS2 output from the LVDS units 80a and 80b that receive the output (RGB parallel signal) of the output selection unit 79 are sent to the display devices DS1a and DS1b via the LVDS relay boards 27a and 27b. Is transmitted.

In order to realize such an operation, it is necessary to secure in the frame buffer FBa image data in which the image data for one frame of the display devices DS1a and DS1b are stripe-connected.

Therefore, next, a method of sprite-connecting image data of 800×600 pixels for the display device DS1a and image data of 800×600 pixels for the display device DS1b will be described with reference to FIG.

As shown in FIG. 15B, in this embodiment, a work area WK1 for temporarily storing image data (Ai) of 800×600 pixels for the display device DS1a and an 800×600 pixel area for the display device DS1b. A work area WK2 for temporarily storing image data (Bi) is secured.

Then, the image data Ai for one frame generated based on the drawing command for the display device DS1a listed in the display list DLi is temporarily stored in the work area WK1, while based on the drawing command for the display device DS1b. The generated image data Bi for one frame is temporarily stored in the work area WK1. The left side of FIG. 15B shows this temporary storage state.

Further, since these image data (Ai, Bi) need to be sprite-concatenated and stored in the frame buffer FBa, 1600×600 in order to store the sprite-concatenated image data (Ai+Bi) as the frame buffer FBa. A storage capacity of ×2 pixels is secured.

The frame buffer FBa is configured to have an α channel for specifying an α value for each of 1600×600 pixels P(i, j), in addition to 3 bytes for specifying RGB data. Here, the α value is transparency information set at each pixel position P(i, j), and is a new image (source) overwritten in the frame buffer FBa and an original image (destination) in the frame buffer FBa. It is a value that specifies the α blending process that defines the transparency of and.

Although not particularly limited, if the α value has a 1-byte configuration, the information of each pixel position P(i,j) is specified by a total of 4 bytes, and the frame buffer FBa has a total of 1600×600×. It has a data capacity of 4 bytes.

Continuing the description based on the above, the completed image data (Ai, Bi) temporarily stored in the work areas WK1, WK2 are stripe-connected by the stripe connection processing JOIN described at the final position of the display list DLi. It The drawing command sequence that realizes the stripe concatenation process JOIN is stored as a subroutine JOIN accessible by the drawing circuit 76 (DL analyzer) in, for example, the built-in VRAM 71 or the external DRAM 54 when the power is reset.

FIG. 15A is a flow chart for explaining this stripe connection processing JOIN. In the stripe concatenation process JOIN, first, the α value=0 is written in the α channel that specifies the odd column pixels, while the α value=255 is written in the α channel that specifies the even column pixels (SS51). ..

Next, the image data Ai (800×600 pixels) of the display device DS1a in the completed state stored in the work area WK1 is laterally enlarged to be image data of 1600×600 pixels, which is used as the frame buffer FBa. Write to (SS52).

This double enlargement processing is performed by a drawing command for transferring image data from the work area WK1 to the frame buffer FBa, and the image area on the source side (work area WK1) and the image area on the destination side (larger frame buffer FBa in the horizontal direction). It is enough to specify. That is, since the destination side frame buffer FBa is twice as large as the source side in the horizontal direction, the horizontal enlargement process is automatically executed in the drawing circuit (Pixel Generator).

In the 2× enlargement process, the image data on the first column of the work area WK1 is copied to the first and second columns of the frame buffer FBa, and the image data on the second column of the work area WK1 is changed to the frame buffer. It is configured to be copied to the third and fourth columns of FBa. The same applies hereinafter, and the image data of the Nth column of the work area WK1 is copied to the 2*N-1th column and the 2*Nth column of the frame buffer FBa to form the destination image.

Next, the image data Bi (800×600 pixels) of the display device DS1b in the completed state stored in the work area WK2 is laterally doubled to be 1600×600 pixels of image data, and a frame is obtained. The α blending process is executed with the image data in the buffer FBa (SS53). In this case also, the image data of the Nth column of the work area WK2 acts on the 2*N-1th column and the 2*Nth column of the frame buffer FBa by the enlargement processing, and the image data between the destination image at that position is obtained. α blending processing is performed.

In the α blending process, for example, the calculation of Cr=Cd*(1−α/255)+Cs*α/255 is executed as shown in Expression 1 shown in FIG. In this arithmetic expression, Cd is RGB information of the original image (Destination) written in each pixel position P(i,j) of the frame buffer FBa, that is, Cd is written in the frame buffer FBc in the process of step SS52. Image data of the work area WK1 (1600×600 pixels of the horizontally enlarged display device DS1a).

On the other hand, Cs is RGB information of the Source image (1600×600 pixels of the display device DS1b) of the horizontally expanded work area WK2, and Cr is RGB information of the frame buffer FBc after the α blending process. Note that in the α blend processing formula, 255 is the upper limit value of the α value in the 1-byte configuration (n=8), which changes according to the data configuration (2 ⁿ −1).

As described above, the α value is 0 in the odd-numbered pixel column and 255 in the even-numbered pixel column shown in FIG. 15B as a result of the process of step SS51, so that in the frame buffer FBa corresponding to the odd-numbered pixel column, eventually. , Cr=Cd, the original image (Destination), that is, the image data for the sub display device DS1a remains as it is.

On the other hand, in the frame buffer FBa corresponding to the even-numbered pixel column, the original image (Destination) disappears and is overwritten by the new image (Source), that is, only the image data for the sub display device DS1b, due to the relationship of Cr=Cs. Will be remembered.

As a result, the image data of the display device DS1a and the image data of the display device DS1b are stored in the frame buffer FBa in stripes.

In the α-brent process described above, the horizontally enlarged image of the sub display device DS1b is used as the Source image, but instead of this, the horizontally enlarged image of the sub display device DS1a may be used as the Source image. Of course. It is also possible to leave the image of the sub display device DS1a or the image of the sub display device DS1b in the odd-numbered pixel column, and correspondingly, the circuit connection of the LVSD relay substrate and the display device may be changed. .. Further, the process of step SS51 may be limited to once when the power is turned on.

In any case, the image data sprite-combined in this way is sprite-divided in the output selection unit 79, and the LDVS1 signal for specifying the image data (Ai) for the display device DS1a and the image data for the display device DS1b ( The LDVS2 signal that specifies Bi) is transmitted to the LDVS relay boards 27a and 27b.

Then, the LDVS signals regenerated in the LDVS relay boards 27a and 27b are transmitted to the respective display devices DS1a and DS1b, so that respective display screens in which the influence of noise is eliminated are displayed.

In the configuration of FIG. 14A, the sprite division process is executed in the output selection unit 79, but the sprite division may be performed in the LVDS relay board 27 as illustrated in FIG. 14B. In the case of the configuration of FIG. 14B, the clock frequency of the LVDS signal output from the VDP circuit is, for example, 80 MHz, but since the LVDS signal is regenerated in the LVDS relay board 27, noise due to level drop or the like is generated. No trouble will occur.

As described above, FIG. 10C illustrates the operation of the distributor 85 arranged on the LVDS relay board 27. The frequency of the dot clock is lowered from 80 MHz to 40 MHz in the distributor 85. It

When adopting the configurations of FIGS. 14A and 14B, it is necessary to generate the image data of another display device by using the frame buffers FBb and FBc in the empty state and the display circuits 74B and 74C. You can

FIG. 14C shows an embodiment in which six display devices DS1a, DS1b, DS2 to DS5 are arranged, and sprite-connected image data is generated in each frame buffer FBa, FBb, FBc. .. The LVDS signal including the sprite-connected image data is sprite-divided in the LVDS relay boards 27a to 27c and transmitted to each of the display devices DS1a, DS1b, DS2 to DS5.

Since the output of the display circuit 74C is RGB parallel data, the LVDS conversion circuit is arranged on the liquid crystal IF substrate and transmitted as an LVDS signal to the LVDS relay substrate 27c.

By the way, in the above description, the gaming machine GM having the glass door 6 and the front plate 7 pivotally mounted on the front frame 3 has been described, but a common member that can be permanently used in the gaming hall for a certain period of time. In order to secure the (general-purpose member GER) and to make the gaming machine richer in individuality, it is preferable to adopt the device configuration shown in FIG.

In this gaming machine GM, the front frame 3 pivotally attached to the wooden outer frame 1 is configured to be disassembled into the first front frame 3A and the second front frame 3B, and the second front frame 3B and the door frame 4A. And the design frame 4B are mounted.

The game board 5 is mounted on the first front frame 3A, and the second front frame 3B, the door frame 4A, and the design frame 4B are arranged in front of the game board 5. In this device configuration, the wooden outer frame 1, the first front frame 3A, and the second front frame 3B are a common member GER arranged in the game hall, and the game board 5, the door frame 4A, and the design frame. 4B is a changing member CHG that can be changed for each model. However, the door frame 4A and the design frame 4B do not necessarily have to be replaced every time, corresponding to the replacement of the game board 5.

In addition, when the device configuration shown in FIG. 16 is made to correspond to the configuration diagram of FIG. 4, the frame side member GM1 is a common member GER (wooden outer frame 1+first front frame 3A+second front frame 3B), The door frame 4A and the design frame 4B are combined, and the board side member GM2 becomes the game board 5.

By the way, the door frame 4A is roughly classified into a general-purpose frame 4A1 that can be used for general purposes and an individuality frame 4A2 that is roughly classified for each game concept of each model. The personality frame 4A2, for example, hundred girl frame to be used in the boxing movie series of and gong frame 4A2 _G to be used in the gaming machine in the motif, a series of gaming machines that motif anime hero (hundred girls) 4A2 _S etc. are prepared.

The circuit board arranged on the door frame 4A stores a discrimination code for specifying the type (4A1, 4A2,...) Of the door frame described above, and when the power is turned on, the type of the door frame 4A is stored. It is configured so that it can be determined. And, in the unlikely event that the irrational door frame 4A is attached to the game board 5, the fact is notified.

On the other hand, the design frame 4B, for each type of door frame 4A, a plurality are prepared, for example, as a design frame 4B corresponding to hundred girl frame 4A2 _S, hero clothing colors and designs are different Multiple types are available.

As described above, in the present embodiment, since the plurality of door frames 4A to be mounted on the second front frame 3B are prepared and the plurality of design frames 4B are prepared for each door frame 4A, the game board 5 is provided. It is possible to optimally decorate the periphery of the game board 5 in accordance with the game property intended by.

In this embodiment, the three photo interrupters PI0 to PI2 are arranged on the door frame 4A, while the light shielding plate MK is arranged on the design frame 4B, and the light shielding plate MK is arranged at the time of assembling the design frame. The photo interrupter PIi is configured to penetrate into the gap (see FIG. 17A).

As shown in FIG. 17A, each photo interrupter PIi is configured by facing a photodiode D, which emits inspection light, and a photo transistor TR, which receives the inspection light, with an appropriate gap GP interposed therebetween. ..

Further, the light shielding plate MK is a transparent plastic material in which a base portion MK1 fixed to the design frame 4B and a protruding portion MK2 are formed in a substantially T shape in cross section. Then, the mask sheet SH is attached to the transparent protrusion MK2 to realize the light shielding performance.

As shown in the figure, the projecting portion MK2 is divided into three parts corresponding to the photo interrupters PI0 to PI2, and the appropriate place is a light shielding part by the mask sheet SH. Therefore, the output Di of each photo interrupter PIi is 0 (=L) when the inspection light is blocked, and 1 (=H) when the light is transmitted.

Although not particularly limited, in the present embodiment, one or two of the three parts of the divided protrusion MK2 is a light shielding part, and the outputs D2 to D0 of the photo interrupters PI2 to PI0 are shown in FIG. As in b), up to five types of design units 6 (designs A to F) can be specified.

Then, when the power is turned on, the data of the photo interrupters PI0 to PI2 are acquired, the type of the design frame 4B is determined, and the image effect corresponding to the type of the design frame 4B is executed. For example, the color and design of the main character's clothes appearing on the display device match the design of the design frame 4B.

Although various embodiments have been described in detail in this specification, the specific description does not limit the invention in any way.

23 Sub Control Means GM Gaming Machine 54 Production Control Means 53 Data Storage Means 56 Image Generation Means 85 Relay Circuit 27 Relay Board

Claims (6)

A game machine provided with sub-control means for controlling, based on a control command received from another control means, an image effect corresponding to the lottery result of the lottery processing executed due to a predetermined switch signal,
The sub control means,
Production control means for controlling the image production by outputting a drawing instruction for specifying the display content of the display device for executing the image production,
Data storage means for storing compressed data that is a constituent element of a still image and/or a moving image that constitutes an image effect,
And an image generation unit capable of outputting an image signal generated by accessing the data storage unit based on the drawing instruction received from the effect control unit, in the form of an LVDS (Low Voltage Differential Signaling) signal. Was
Between the image generating means and the display device, a first wiring cable set to a predetermined length is connected to the image generating means, and a second wiring cable set to a predetermined length is connected to the display device. Place the relay board that will be
An electronic circuit capable of receiving the LVDS signal output from the image generating means at an input terminal of the relay board, and outputting the LVDS signal at the same dot clock frequency or by doubling the frequency to the output terminal. The elements are arranged ,
The electronic circuit element performs a De-Serialize process on the LVDS signal received via the first wiring cable to restore an RGB signal or a control signal, and a serialize process on the restored RGB signal or a control signal. A transmitter that outputs the generated LVDS signal to a second wiring cable, and a first repeater operation that is located between the receiver and the transmitter and does not change the frequency of the dot clock, or the frequency of the dot clock changes. An intermediate control unit capable of executing any one of the second Repeater operations, and a gaming machine. A game machine provided with sub-control means for controlling, based on a control command received from another control means, an image effect corresponding to the lottery result of the lottery processing executed due to a predetermined switch signal,
The sub control means,
Production control means for controlling the image production by outputting a drawing instruction for specifying the display content of the display device for executing the image production,
Data storage means for storing compressed data that is a constituent element of a still image and/or a moving image that constitutes an image effect,
And an image generation unit capable of outputting an image signal generated by accessing the data storage unit based on the drawing instruction received from the effect control unit, in the form of an LVDS (Low Voltage Differential Signaling) signal. Was
Between the image generating means and the display device, a first wiring cable set to a predetermined length is connected to the image generating means, and a second wiring cable set to a predetermined length is connected to the display device. Place the relay board that will be
The relay board can receive the LVDS signal output from the image generating means at an input terminal, and output the LVDS signal at the same dot clock frequency or at a frequency obtained by halving the frequency to the output terminal. Electronic circuit elements are arranged ,
The electronic circuit element performs a De-Serialize process on the LVDS signal received via the first wiring cable to restore an RGB signal or a control signal, and a serialize process on the restored RGB signal or a control signal. A transmitter that outputs the generated LVDS signal to a second wiring cable, and a first repeater operation that is located between the receiver and the transmitter and does not change the frequency of the dot clock, or the frequency of the dot clock changes. An intermediate control unit capable of executing any one of the second Repeater operations, and a gaming machine. The gaming machine according to claim 1 or 2 , wherein an inductor that exhibits a high impedance with respect to a common mode signal and a protection element that performs a short circuit operation during electrostatic discharge are arranged on the relay board. The gaming machine according to claim 3 , wherein the inductors are arranged on an input side and an output side of the electronic circuit element, respectively. Wherein the display device is a plurality placed, the gaming machine according to any one of claims 1-4 in which the relay substrate are arranged corresponding to each display device. The plurality of display devices,
The gaming machine according to claim 5 , further comprising display devices having the same number of vertical pixels and the same number of horizontal pixels of their respective display screens in relation to the display device to be compared.