JP2008167840A - Control device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To have high tolerance for noise, enhance the speed and transmit a long cable transmittable signal from a VDP (Video Display Processor) to an LCD in a game machine. <P>SOLUTION: In an ornamental symbol control board for controlling a performance display of the LCD in the game machine, display data are transmitted from the VDP 385 to the LCD 16 in the following methods. When the VDP outputs an LVDS (Low Voltage Differential Signaling), a receiver 338A once converts it into CMOS signal, a transmitter 336A converts it into LVDS and outputs it to the outside. The use of the transmitter dedicated to the LVDS can secure a signal precision and transmit a signal with high tolerance for noise while effectively utilizing the LVDS signal output from the VDP. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a circuit structure of a control device for controlling a predetermined device, and a gaming machine equipped with the control device.

  In gaming machines such as pachinko machines and swivel-type gaming machines, various effects are displayed on the display panel during the game. The display data for effect display is generated by an arithmetic circuit called a VDP (Video Display Processor). This display data is transmitted to the display panel via a cable such as a twisted pair. Regarding the transmission of display data, there are mainly the following two requests in gaming machines. First, gaming machines often do not have enough space to arrange display panels and control devices in the device, so by connecting them with a relatively long cable, the degree of freedom of the arrangement of both is secured. It is desirable. In general, a gaming machine is used in an environment where there is a lot of noise due to static electricity or the like. Patent Document 1 discloses a technique of converting an output from VDP into LVDS and outputting the signal in order to realize signal transmission resistant to noise.

JP 2005-274935 A

  In recent years, in gaming machines, display panels have been increased in size and resolution, and the capacity of display data has been increasing. Accordingly, there is a demand for the realization of signal transmission that can withstand noise and increase the speed and that can transmit a long cable. Since LVDS is not only resistant to noise but also capable of high-speed communication as compared with a CMOS signal, a VDP that enables LVDS output has also been proposed.

  However, the LVDS signal output from the VDP itself has a problem that when the cable becomes long, the signal waveform collapses and signal accuracy cannot be ensured. FIG. 14 is a graph showing LVDS signal waveforms. FIG. 14A shows a signal waveform when the LVDS output from the VDP is transmitted through a 15 cm-long twisted pair cable. In this state, sufficient accuracy can be secured. FIG. 14B shows a waveform when the cable length is 30 cm. With this length, the waveform collapses and sufficient signal accuracy cannot be secured. FIG. 14C shows a signal waveform when a 35 cm long flexible cable is used. It can be seen that with a flexible cable, signal accuracy can be secured even with a cable length of 35 cm. However, the flexible cable has a drawback that it is more susceptible to noise than the twisted pair cable.

  On the other hand, with the technique described in Patent Document 1, it has been confirmed that sufficient signal accuracy can be secured even with a twisted pair cable of about 30 cm length by using a transmitter dedicated to LVDS. However, since a CMOS signal is used between the VDP and the LVDS dedicated transmitter, there is room for improvement in terms of noise countermeasures and speedup.

  As described above, the prior art has not been able to sufficiently realize signal transmission that can be transmitted with a long cable while being resistant to noise and speeding up. This viewpoint is a common problem not only for the output signal from the VDP in the gaming machine but also for various control devices that need to output the control signal to the outside in a high noise environment. An object of the present invention is to solve at least a part of the above-described problems in signal transmission.

  The present invention is directed to a control device that controls a predetermined device. The control device as the first configuration has an arithmetic circuit that executes predetermined control processing and outputs a control signal LVDS (Low-Voltage Differential Signaling). The control process may be executed by software or hardware. The LVDS output from the arithmetic circuit is transmitted to the receiver and converted into a CMOS signal. The control device includes a transmitter that receives the CMOS signal from the receiver circuit and converts it into an LVDS signal, and outputs the LVDS signal converted by the transmitter to the outside via a connector.

  According to the present invention, since the LVDS signal is output from the arithmetic circuit, it is resistant to noise and can be increased in speed. Since this LVDS signal is output to the outside via a transmitter dedicated to LVDS, signal transmission over a relatively long distance is also possible. Although a CMOS signal is used between the receiver and the transmitter, it is possible to mitigate the influence of noise by arranging the two close enough on the substrate.

  The above-described CMOS signal may be converted by a converter into a data line obtained by multiplying the number of unit bits of the control signal by n (n is a natural number of 2 or more) and transmitted to the transmitter. For example, when the control signal is output in 24 bits from the arithmetic circuit, a mode in which the data line is increased to 48 bits by the converter and transmitted in parallel can be adopted. This converter may be provided as one function of the receiver, or may be provided separately from the receiver. By increasing the number of bits in this manner, the signal transmission speed by CMOS can be improved, and the overall signal transmission speed can be increased.

  In the control device of the present invention, the receiver and the transmitter may be configured by an arithmetic circuit and a separate substrate. By doing so, it becomes possible to switch the configuration of the control device according to the distance over which the signal is transmitted by LVDS. In other words, when short-distance transmission that can be accurately transmitted with the LVDS signal from the arithmetic circuit is sufficient, the cost is reduced by removing the board (hereinafter referred to as “relay board”) including the receiver and the transmitter. A simple circuit configuration can be realized. Instead of the relay board, a simple relay board that simply transmits the LVDS signal between the arithmetic circuit and the external output connector may be used without mounting the receiver and the transmitter. On the other hand, when the above-described relay board is used, it is possible to realize long-distance transmission to the extent that signal accuracy cannot be ensured with the LVDS signal from the arithmetic circuit.

  When such a relay board is used, a power supply circuit or the like corresponding to the device to be controlled may be mounted on the relay board. By doing so, there is an advantage that the substrate on which the arithmetic circuit is mounted can be shared for various control objects.

  In the present invention, as a second configuration, an arithmetic circuit that executes a predetermined control process and outputs a control signal in CMOS may be used. In this case, the number of data lines of the CMOS signal is increased by the converter described above and then transmitted to the transmitter. Since the CMOS signal is output, the receiver for the LVDS signal can be omitted. The converter may be provided as one function of the arithmetic circuit or may be provided separately. The transmitter converts the converted CMOS signal into an LVDS signal and outputs it to the outside via a connector.

  According to the second configuration, since the LVDS signal is output to the outside via the LVDS-dedicated transmitter, signal transmission over a relatively long distance is possible. Further, increasing the number of CMOS signal lines can improve the transmission speed of CMOS signals. As a result, it is possible to realize signal transmission capable of being transmitted over a long cable while being resistant to noise and speeding up.

  Also in the second configuration, the transmitter may be configured on a separate substrate from the arithmetic circuit. This makes it possible to use the CMOS signal output and the LVDS signal output properly in accordance with the device to be controlled. In addition, by mounting a power supply circuit or the like corresponding to the control target on the relay board on which the transmitter is mounted, there is an advantage that the board on which the arithmetic circuit is mounted can be shared.

  In any of the first and second configurations described above, various devices can be controlled. As an example, the control device may be configured as a device that controls a display device for displaying an image. In this case, the arithmetic circuit may be a circuit that generates display data to be output to the display device such as VDP. In this aspect, the display data may have a large capacity, and transmission at a high speed is required, so that the present invention can be used effectively.

  In the present invention, various cables can be used for transmission of the control signal from the control device, but it is preferable to use a twisted pair cable as an example. Various experiments have confirmed that twisted pair cables are more resistant to noise than flexible cables. Therefore, by applying a twisted pair cable to the present invention, signal transmission resistant to noise can be realized. As previously shown in FIG. 14, the twisted cable tends to deteriorate in signal accuracy in accordance with the cable length as compared with the flexible cable. However, according to the present invention, both the first and second configurations are used. Since the signal is output via the LVDS-dedicated transmitter, such an adverse effect can be avoided.

  In the present invention, it is not necessary to have all the various features described above, and some of them may be omitted, or may be applied in combination as appropriate.

Embodiments of the present invention will be described in the following order. In the present embodiment, a configuration example as a pachinko machine is shown, but the gaming machine may be a spinning-type gaming machine.
A. Game machine configuration:
B. Control hardware configuration:
C. Board configuration:
D. Memory board configuration:
E. Relay board configuration:
F. Variation of relay board:
G. effect:

A. Game machine configuration:
FIG. 1 is a front view of a pachinko machine 1 as an embodiment. The pachinko machine 1 has a game board 4 provided with a game area 6 in the center. The player can play a game by operating the handle 8 and driving a game ball into the game area 6 to win a winning opening. When a game ball wins a start winning opening 9 which is one of the winning openings, the pachinko machine 1 performs a lottery, and it is determined whether or not it is a “hit” according to the result. When a big hit occurs, a big hit game such as opening the big prize opening 10 for a predetermined period is performed.

  The result of the above lottery is displayed on a special symbol display device 41 composed of four lamps. In the center of the game area 6, an LCD 16 is provided, and various effect screens (sometimes referred to as decorative symbols) are displayed during the game. An effect screen corresponding to the state of the game is also displayed when winning at the start winning opening 9 or when a big hit occurs.

  The gaming machine 1 is installed in the island facility of the hall. The island facility holds the gaming machines 1 in a state where a plurality of gaming machines 1 are placed back to back, and a plurality of sets are arranged in a horizontal line. The gap between the gaming machines 1 arranged back to back becomes a space for installing a game ball supply mechanism and wiring such as a power supply line. Since the island facility is a facility for installing not only the gaming machine 1 but also other models, the gaming machine 1 is designed to fit within the depth suitable for the island facility.

B. Control hardware configuration:
FIG. 2 is a block diagram showing a control hardware configuration of the pachinko machine 1. The pachinko machine 1 is controlled by distributed processing of each control board such as the main control board 3, the payout control board 25, the sub control board 35, and the decorative design control board 300. The main control board 3, the payout control board 25, and the sub control board 35 are each configured as a microcomputer having a CPU, a RAM, a ROM, and the like, and implement various control processes according to programs recorded in the ROM. . In the present embodiment, the sub-control board 35 and the decorative design control board 300 are configured as separate boards, but they may be integrated with each other. In this case, the function of the sub control board 35 and the function of the decorative design control board 300 may be realized by distributed processing of a plurality of CPUs or may be realized by a single CPU.

  In the pachinko machine 1 according to the embodiment, input from the outside to the main control board 3 is restricted in order to prevent various frauds. The main control board 3 and the sub control board 35 are connected by a unidirectional parallel electric signal, and the main control board 3 and the payout control board 25 are connected by a bi-directional serial electric signal for the necessity of control processing. Yes. The payout control board 25 and the sub control board 35 operate in response to commands from the main control board 3, respectively. The decorative design control board 300 operates in response to a command from the sub control board 35. The pachinko machine 1 also has a mechanism that is directly controlled by the main control board 3. In the figure, as an example of a device controlled by the main control board 3, a special winning opening solenoid 18 for driving the special winning opening 10 and a special symbol display device 41 are illustrated. In addition to this, the main control board 3 can control displays such as a normal symbol display device, a special symbol hold lamp, a normal symbol hold lamp, a big hit type display lamp, and a status display lamp. Further, detection signals from various sensors are input to the main control board 3 in order to control the operation during the game. In the figure, the input from the winning detector 15a is illustrated as an example. The winning detector 15 a is a sensor for detecting a winning at the start winning opening 9. The main control board 3 can execute the jackpot game by performing the lottery described above according to the signal from the winning detector 15a. Various other inputs are made on the main control board 3, but the description thereof is omitted here.

  Other controls during the game are performed via the payout control board 25 and the sub-control board 35. The payout control board 25 controls the launch and payout of the game ball being played in the following procedure. The launch of the game ball is directly controlled by the launch control board 47. That is, when the player operates the launch handle 8, the launch control board 47 controls the launch motor 49 according to the operation to launch a game ball. The game ball is fired only under a situation where the touch detector 48 detects that the player is touching the firing handle 8. The payout control board 25 indirectly controls the launch of the sphere by sending a launch control signal to the launch control board 47.

  When a command indicating that a prize has been won during the game is received from the main control board 3, the payout control board 25 controls the payout motor 20 in the prize ball payout device 21 and regulates the number of balls by the payout ball detector 22. Pay out a number of balls. The operation of the payout motor 20 is monitored by a motor drive sensor 24, and when an abnormality such as a ball bit or a ball break is detected, the payout control board 25 displays an error code on the display unit 4a. When an error is displayed, it can be recovered by operating the operation switch 4b after the attendant has removed the abnormality.

  The sub-control board 35 controls effects such as voice, display, and lamp lighting during the game. These effects vary according to the status during the game, such as a normal time, a prize, a big win, an error, an alarm when an illegal act or other abnormality occurs. When an effect command corresponding to each status is transmitted from the main control board 3, the sub control board 35 activates a program corresponding to each command to realize the effect instructed from the main control board 3. .

  In the present embodiment, the sub-control board 35 directly controls the speaker 29 as shown in the figure. The LCD 16 is controlled via the decorative design control board 300. The circuit configuration of the decorative design control board 300 will be described later. The lamps to be controlled by the sub-control board 35 include the panel decoration lamp 12 provided on the game board surface and the frame decoration lamp 31 provided on the frame. The sub control board 35 is connected to the panel decoration lamp 12 and the frame decoration lamp 31 via the lamp relay boards 32 and 34, and can blink each lamp individually.

  FIG. 3 is an explanatory diagram showing a circuit configuration of the decorative design control board 300. The decorative design control board 300 outputs display data for displaying a screen on the LCD 16 in accordance with the display command received from the sub-control board 35. The display data is data indicating display gradation values of the R, G, and B pixels provided on the LCD 16 in a matrix. The LCD 16 is a liquid crystal panel, but an organic EL, LED, plasma display, or the like may be used, for example.

  The decorative design control board 300 is provided with various circuits shown in the drawing in order to realize a function of generating display data. First, the decorative design control board 300 is provided with a CPU 381, a RAM 382, and a ROM 383 as microcomputers for controlling the generation of display data. The ROM 383 stores a display program for generating display data, a screen to be displayed in response to a display command, a scheduler for defining a display time, a display order, and screen data for defining each screen configuration of the LCD 16. . The CPU 381 refers to the ROM 383, extracts screen data corresponding to the display command, and outputs it to a VDP (Video Display Processor) 385 as a drawing command. The VDP 385 generates display data (800 × 600 pixels) for one sheet by arranging sprites based on the drawing command.

  The sprite means an image displayed as a unit on the screen of the gaming machine. For example, when various persons are displayed on the screen, data for drawing each person is referred to as “sprite”. In order to display a plurality of persons, a plurality of sprites are used. Not only a person but also a house, a mountain, a road and the like constituting a background image can be used as sprites. The entire background image may be a single sprite. The gaming machine can display various images by determining the arrangement of each sprite on the screen and determining the vertical relationship when the sprites overlap.

  The sprite is stored in the character ROM 386 in the form of character data. In gaming machines, for the convenience of handling data, each sprite is configured by combining a plurality of rectangular areas of a certain size, such as 64 pixels vertically and horizontally, and the data for drawing this rectangular area is called a “character”. In the case of a small sprite, it can be expressed by one character, and in the case of a relatively large sprite such as a person, for example, it can be expressed by a total of 6 characters arranged in a horizontal 2 × vertical 3, etc. . If the sprite is larger than the background image, it can be expressed using a larger number of characters. The number and arrangement of characters can be arbitrarily specified for each sprite.

  The VDP 385 includes a sprite register 385s and a VDP register 385v as registers for receiving and holding screen data from the CPU 381. The sprite register 385s is a register for receiving drawing commands indicating the arrangement of sprites and the order of superposition among screen data, and is configured as a double buffer. That is, two buffers having the same capacity, that is, a first buffer and a second buffer are provided. Therefore, while the drawing command output from the CPU 381 is written in the first buffer, the VDP 385 can read the drawing command held in the second buffer and execute display data generation processing. The VDP register 385v is a register for storing a command (hereinafter referred to as a “condition setting command”) that specifies a condition setting when generating display data. The condition setting command includes, for example, the overlay order of each layer, display / non-display setting, etc., when the drawing command is composed of a plurality of layers. Since the condition setting command has a relatively low capacity and the time required for writing is short, the VDP register 385v is not a double buffer.

  In addition to the configuration shown in the figure, the decorative design control board 300 may include a frame memory for storing display data for one screen of the LCD 16 and a scaler. The frame memory is preferably a double buffer in order to smoothly write data from the VDP 385 and output to the LCD 16. The scaler is a circuit that enlarges or reduces the display data size to fit the number of pixels of the LCD 16 when storing or reading the display data in the frame memory, and the display data generation capability by the VDP 385 is insufficient for the number of pixels of the LCD 16. This is useful in order to realize smooth display even in the case of doing so.

C. Board configuration:
FIG. 4 is a perspective view of the decorative design control board 300. The decorative design control board 300 has a hierarchical structure in which the memory board 320 and the first relay board 330 are attached to the arithmetic circuit board 310 via the stay 311. Signal exchange between the memory board 320 and the arithmetic circuit board 310 is performed via the connector 312. Signal exchange between the arithmetic circuit board 310 and the first relay board 330 is performed via the connector 313. In this embodiment, LVDS is used for signal output from the arithmetic circuit board 310. The first relay board 330 is provided with an LVDS driver circuit 332 and an output cable connector 334. An output signal from the connector 334 is transmitted to the LCD 16.

  FIG. 5 is an explanatory diagram showing a state in which the decorative design control board 300 is viewed from the top. As described above, the memory substrate 320 and the first relay substrate 330 are stacked on the arithmetic circuit substrate 310. The memory board 320 and the first relay board 330 are designed to be equal to or smaller than the size of the arithmetic circuit board 310 even if both are arranged. By doing so, the decorative design control board 300 can be downsized. In this embodiment, a two-layer structure is used, but the substrate may have a three-layer or higher layer structure. Conversely, the memory substrate 320 and the first relay substrate 330 may be arranged side by side with the arithmetic circuit substrate 310 without adopting a stacked structure.

  FIG. 6 is an explanatory diagram showing the structure of the arithmetic circuit board 310. The state where the memory board 320 and the first relay board 330 are removed is shown. Each circuit shown in FIG. 3, that is, the CPU 381, the RAM 382, the VDP 385, and the ROMs 383H and 383L are mounted. A power supply circuit 380 for supplying power to these is also mounted. The ROMs 383H and 383L perform the function of the ROM 383 in FIG. 3 together. When the CPU 381 designates an address, the same address signal is input in parallel to the ROMs 383H and 383L, and the data stored at the corresponding address is output 16 bits at a time from each ROM. The data output of each ROM is directly transmitted in parallel to the CPU 381 via the 32-bit data bus. In other words, the CPU 381 is supplied with data in which the upper 16 bits are output from the ROM 383H and the lower 16 bits are output from the ROM 383L.

  Character data used by the VDP 385 when generating display data is supplied from the memory board 320 via the connector 312a. The output of the VDP 385 is made by LVDS, and this LVDS signal is outputted to the first relay board 330 via the connector 313a. LVDS is a signal output method that performs high-speed transmission while avoiding the influence of noise by outputting a signal with a small amplitude of several hundred mV in a differential manner. As can be seen from comparison with FIG. 5, in this embodiment, the memory substrate 320 is disposed so as to avoid the upper side of the VDP 385, and the first relay substrate 330 is disposed on the VDP 385. By adopting such an arrangement, it is possible to transmit the output from the VDP 385 to the first relay board 330 at a short distance, and further to the LCD 16 at a short distance.

D. Memory board configuration:
FIG. 7 is an explanatory view showing the structure of the memory substrate 320. FIG. 7A shows the structure of the upper surface (sometimes referred to as the front surface) of the memory substrate 320, and FIG. 7B shows the structure of the back surface. Eight character ROMs 386A to 386H are mounted on the memory board 320 of this embodiment. FIG. 7 shows a mounting state of a socket for attaching a land grid array type character ROM. A connector 312b for connecting to the arithmetic circuit board 310 is provided on the back surface of the memory board 320 as shown in FIG. Hereinafter, for convenience of explanation, the side to which the connector 312b is attached is referred to as the front side, the opposite side is referred to as the rear side, and the direction along the connector 312b is referred to as the left-right direction.

In the present embodiment, the character ROMs 386A to 386H are handled as one set by two arranged in the left-right direction on the front surface or the back surface. In other words, four sets,
Set 1 ... Character ROM 386A, 386B;
Set 2 ... Character ROM 386C, 386D;
Set 3 ... Character ROM 386E, 386F;
Set 4 ... Character ROM 386G, 386H
Is configured. Two sets are mounted on the front surface and two sets on the back surface. The two character ROMs constituting one set have a positional relationship in which the other character ROM is arranged at a position obtained by translating one character ROM along the short side. Thus, by arranging the two character ROMs constituting one set on the left and right within the same plane, the wiring distance to each character ROM can be made relatively easy. For example, a signal supplied from the connector 312b may be branched and supplied to each of the character ROMs 386A and 386B at approximately the center of each pin of the character ROMs 386A and 386B. The same applies to the other sets. This makes it possible to read data from each set quickly and smoothly.

  The front character ROMs 386A to 386D are all arranged with the right front corner of the socket cut off, while the rear character ROMs 386E to 386H are arranged with the left rear corner of the socket cut off. Has been. That is, the character ROMs 386E to 386H on the back surface have a positional relationship in which the character ROMs 386A to 386D on the front surface are rotated 180 degrees and then turned over. By doing so, the positional relationship between the left and right of each pin can be unified on the front and back of the board. For example, there is an advantage that it is possible to avoid complicated wiring such as wiring to the first pin crossing on the front and back surfaces. is there.

  FIG. 8 is a circuit diagram showing a connection state between the VDP 385 and the character ROMs 386A to 386H. The address output from the VDP 385 is input to all the character ROMs 386A to 386H via the 25-bit address bus CAD. From the VDP 385, 2-bit chip enable signals CCSB [0] to CCSB [7] are output to the character ROMs 386A to 386H for each set. By controlling the chip enable signal, data can be output by switching between set 1 to set 4. Each character ROM 386A to 386H also outputs an output enable signal CRDB and a reset signal for controlling whether or not data output is possible.

  From the character ROMs 386A and 386B constituting the set 1, 32-bit data is output. These data are output to a 64-bit data bus with the output from the character ROM 386A being the upper 32 bits and the output from the character ROM 386B being the lower 32 bits. In other words, the data stored at the address specified by the VDP 385 is output in parallel by the character ROMs 386A and 386B, thereby realizing 64-bit data output while using the 32-bit character ROM. is there. The same applies to the character ROMs 386C to 386H constituting the sets 2 to 4.

  Thus, by using two character ROMs in parallel, the bit width of the data bus can be improved relatively easily, and as a result, access to the character ROM can be speeded up. In order to stably operate each character ROM with such a circuit configuration, it is necessary that the address designation to the character ROM constituting one set and the data output from the character ROM are substantially synchronized. . In this embodiment, as shown in FIG. 7, data transmission between character ROMs is performed by arranging the character ROMs so that the wiring distances of the character ROMs constituting one set are substantially equal. Can be suppressed, and stable operation can be realized.

E. Relay board configuration:
FIG. 9 is an explanatory view showing the structure of the first relay board 330. FIG. 9A shows the structure of the upper surface of the substrate, and FIG. 9B shows the structure of the lower surface. The first relay board 330 is a board having a simple structure for transmitting the LVDS signal from the VDP 385 to the connector 334 as it is. As shown in FIG. 9B, the LVDS signal from the VDP 385 is input to the first relay board 330 via the connector 313. This signal is transmitted as it is to the connector 334 shown in FIG. 9A and output to the outside. A driver circuit 332 suitable for the LCD 16 is mounted on the first relay board 330, and a power source for the LCD 16 is also output from the connector 334.

  As described above, in this embodiment, since the first relay board 330 is arranged above the VDP 385, it is possible to transmit the LVDS signal from the VDP 385 to the LCD 16 at a relatively short distance. Therefore, in a gaming machine in which the decorative design control board 300 can be placed on the back surface of the LCD 16 and the like can be placed sufficiently close to each other, the first relay board 330 is used to reduce costs while simplifying. The LVDS signal can be utilized with a simple circuit configuration.

  FIG. 10 is an explanatory view showing the structure of the second relay substrate 330A. FIG. 10A shows the structure of the upper surface of the substrate, and FIG. 10B shows the structure of the lower surface. The second relay board is a board for inputting the LVDS signal from the VDP 385 and outputting it externally using a transmitter dedicated to LVDS. Since a dedicated transmitter is used, there is an advantage that a LVDS signal can be transmitted over a longer distance than the first relay board 330.

  As shown in FIG. 10B, the LVDS signal from the VDP 385 is input to the second relay board 330A via the connector 313A. The receiver 338A receives this LVDS signal and converts it into a CMOS signal. Data is output from the VDP 385 in units of 24 bits, but the receiver 338A converts two sets of data into 48-bit parallel data and outputs the data. By doing so, many CMOS signals can be efficiently transmitted at a low frequency, and the speed of signal transmission can be increased. However, it is not essential to increase the number of signal lines in this manner, and a CMOS signal may be output with 24 bits.

  The transmitter 336A shown in FIG. 10A receives the CMOS signal output from the receiver 338A, converts it into an LVDS signal, and outputs it from the connector 334A. A driver circuit 332A suitable for the LCD 16 is mounted on the second relay board 330A, and a power source for the LCD 16 is also output from the connector 334A. According to the second relay board 330A, since the LVDS dedicated transmitter 336A is used, there is an advantage that an LVDS signal can be transmitted over a relatively long distance.

F. Variation of relay board:
FIG. 11 is an explanatory view showing the structure of the third relay substrate 330B. FIG. 11A shows the structure of the upper surface of the substrate, and FIG. 11B shows the structure of the lower surface. The third relay board 330B is a board used when a CMOS signal is output from the VDP 385, and has a function of converting the CMOS signal into an LVDS signal and outputting it.

  As shown in FIG. 11B, the CMOS signal from the VDP 385 is input to the third relay board 330B via the connector 313B. The transmitter 336B receives this CMOS signal, converts it into an LVDS signal, and outputs it from the connector 334B shown in FIG. A driver circuit 332B suitable for the LCD 16 is mounted on the third relay board 330B, and a power source for the LCD 16 is also output from the connector 334B. According to the third relay board 330B, since the LVDS-dedicated transmitter 336B is used, there is an advantage that an LVDS signal can be transmitted over a relatively long distance.

  In the third relay board 330B, it is preferable to convert the CMOS signal output in units of 24 bits from the VDP 385 into 48-bit parallel data. A converter for converting the output from the VDP 385 to 48 bits may be provided, or a function for outputting the 48 bits to the VDP 385 may be incorporated. In any case, the conversion to 48 bits is preferably performed by the arithmetic circuit board 310. Further, as shown in FIG. 11B, in this embodiment, the transmitter 336B is arranged in the vicinity of the connector 313B. By doing so, the transmission distance of the CMOS signal can be shortened as compared with the case where it is arranged on the surface of the third relay substrate 330B, which is also suitable as a noise countermeasure.

G. effect:
FIG. 12 is an explanatory diagram showing a circuit configuration when each output board is used. FIG. 12A shows a configuration in which the first relay board 330 (see FIG. 9) is used. In this case, the LVDS signal output from the VDP 385 of the arithmetic circuit board 310 is transmitted as it is to the LCD 16 via the connector 334. The connector 334 and the LCD 16 are connected by a twisted pair cable such as 10 pairs.

  FIG. 12B shows a configuration when the second relay board 330A (see FIG. 10) is used. In this case, the LVDS signal output from the VDP 385 of the arithmetic circuit board 310 is once converted into an RGB 48-bit CMOS signal by the receiver 338A of the second relay board 330A, re-converted to the LVDS signal by the transmitter 336A, and the LCD 16 Sent to. Between the receiver 338A and the transmitter 336A, the synchronization signal VSYNC and the like are also transmitted in parallel with RGB 48 bits. The connector 334A and the LCD 16 are connected by a 5 pair or 10 pair twisted pair cable.

  FIG. 12C shows a configuration in the case where the third relay substrate 330B (see FIG. 11) is used. In this case, the RGB 48 bits and the CMOS signal such as the synchronization signal VSYNC are output in parallel from the VDP 385 of the arithmetic circuit board 310B. This CMOS signal is converted into an LVDS signal by the transmitter 336B on the third relay board 330B and output to the LCD 16. The connector 334B and the LCD 16 are connected by a 5 pair or 10 pair twisted pair cable.

  In this embodiment, in any of the above configurations, a signal can be output to the LCD 16 by LVDS, so that data can be transmitted at a high speed against noise. Further, since a twisted pair cable is used between each connector and the LCD 16, there is an advantage that it is more resistant to noise than a flexible cable.

  Further, since both the second relay board 330A and the third relay board 330B use transmitters 336A and 336B dedicated to LVDS, there is an advantage that LVDS signals can be transmitted over a relatively long distance. As a result, in these configurations, the degree of freedom of arrangement of the LCD 16 can be improved.

  The first relay board 330 and the second relay board 330A can be connected to a common arithmetic circuit board 310. Therefore, when the distance between the arithmetic circuit board 310 and the LCD 16 is relatively short, the first relay board 330 is used, and when the distance is long, the second relay board 330A is used. Is possible. The advantage that can be properly used in this way is highly useful for the pachinko machine 1 as shown below.

  As described above, the size of the pachinko machine 1 in the depth direction is very strictly limited for the convenience of installation in the island facility of the hall. The main body frame of the pachinko machine 1 is attached to the outer frame installed in the island facility of the hall so as to be opened and closed by a hinge mechanism. In the present embodiment, a hinge mechanism is provided on the right side in FIG. Since the pachinko machine 1 has a depth, when opening and closing with the hinge mechanism, the side (left side in FIG. 1) facing the hinge mechanism interferes with the outer frame. In order to avoid this, it is necessary to reduce the size of the pachinko machine 1 in the left-right direction as it goes to the back. In order to adopt such a structure, in the pachinko machine 1, according to the respective models, in the pachinko machine 1, the LCD 16 according to the size of the LCD 16 and the size, number, position, etc. of solenoids arranged around the LCD. And the degree of freedom of the arrangement of the arithmetic circuit board 310 is very limited.

  In the embodiment, the first type of pachinko machine 1 is exemplified, but the type called a second type or a multi-function machine having a variable winning device that performs mechanical lottery using a distribution mechanism that distributes the destination where the game ball rolls. In the pachinko machine, the arrangement of the LCD and the like is further restricted due to the arrangement of a variable prize device having a depth.

  Because there are so many restrictions, the arrangement of the LCD 16 and the arithmetic circuit board 310 can be diverse and flexible, such as a close arrangement that can be connected with a short cable and an isolated arrangement that must be connected with a long cable. Sex is required. In the configuration of the embodiment, as shown in FIG. 12, both can be connected with various long and short cables, so that it is possible to meet the demands for the diversity of arrangement. Therefore, the same substrate can be used for different models, and the manufacturing cost can be reduced.

  Next, the effect of improving the signal transmission accuracy in this embodiment will be described based on experimental examples. FIG. 13 is a graph showing signal waveforms. FIG. 13A shows a signal after the LVDS signal transmitted by the first relay board 330 is transmitted through a 35 cm-long twisted pair cable (same graph as FIG. 14B). The waveform of the LVDS signal collapses, and the signal cannot be transmitted with high accuracy.

  FIG. 13B shows a waveform when the third relay board 330B is used, and FIG. 13C shows a waveform when the second relay board 330A is used. Both are signals after the LVDS signal is transmitted through a 35 cm long twisted pair cable. By using a transmitter dedicated to LVDS like these substrates, the signal waveform does not collapse and a signal can be transmitted with sufficient accuracy. As described above, by using the second relay board 330A and the third relay board 330B of this embodiment, it is possible to sufficiently transmit the LVDS signal even at a distance of 35 cm or more.

  As shown in FIG. 14A, even when the LVDS signal from the VDP 385 is used as it is, if the twisted pair cable is about 15 cm, LVDS transmission is possible without any problem. Therefore, when it is possible to arrange at a distance of about 15 cm, the first relay board 330 can perform LVDS transmission with a simple circuit configuration while reducing costs.

  Although various embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and it goes without saying that various configurations can be adopted without departing from the spirit of the present invention. In the embodiment, application to the decorative design control board 300 (see FIG. 2) of the gaming machine is illustrated. The present invention can also be used for signal transmission from other control boards in the gaming machine. Further, the present invention is not limited to gaming machines, and can be applied to various devices for which noise suppression, high speed, and long distance signal transmission are desired.

It is a front view of the pachinko machine 1 as an example. 2 is a block diagram showing a control hardware configuration of the pachinko machine 1. FIG. It is explanatory drawing which shows the circuit structure of the decoration design control board 300. FIG. 3 is a perspective view of a decorative design control board 300. FIG. It is explanatory drawing which shows the state which looked at the decoration design control board 300 from the upper surface. It is explanatory drawing which shows the structure of the arithmetic circuit board. 4 is an explanatory diagram showing a structure of a memory substrate 320. FIG. It is a circuit diagram which shows the connection state of VDP385 and character ROM 386A-386H. It is explanatory drawing which shows the structure of the 1st relay board | substrate 330. FIG. It is explanatory drawing which shows the structure of 330 A of 2nd relay boards. It is explanatory drawing which shows the structure of the 3rd relay board | substrate 330B. It is explanatory drawing which shows the circuit structure at the time of using each output board | substrate. It is a graph which shows a signal waveform. It is a graph which shows the signal waveform of LVDS.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Pachinko machine 3 ... Main control board 4 ... Game board 4a ... Display part 4b ... Operation switch 6 ... Game area 8 ... Launching handle 9 ... Start winning opening 10 ... Grand prize opening 12 ... Panel decoration lamp 15a ... Winning detector 16 ... LCD
DESCRIPTION OF SYMBOLS 18 ... Grand prize opening solenoid 20 ... Discharge motor 21 ... Prize ball payout device 22 ... Discharge ball detector 24 ... Motor drive sensor 25 ... Discharge control board 29 ... Speaker 31 ... Frame decoration lamps 32, 34 ... Lamp relay board 35 ... Sub Control board 41 ... Special symbol display device 47 ... Launch control board 48 ... Touch detection unit 49 ... Launch motor 300 ... Decoration pattern control board 310, 310B ... Operation circuit board 311 ... Stay 312, 312a, 312b ... Connectors 313, 313a, 313A Connector 320, 320a ... Memory board 330, 330A, 330B ... Relay board 332 ... Driver circuit 334, 334A, 334B ... Connector 336A, 336B ... Transmitter 338A ... Receiver 380 ... Power supply circuit 381 ... CPU
382 ... RAM
383, 383H, 383L ... ROM
385 ... VDP
385s ... Sprite register 385v ... VDP register 386, 386A-386H ... Character ROM
386M ... Memory 386S ... Socket 390, 390F, 390R ... Scaler 397, 397F, 397R ... Frame memory

Claims (7)

A control device for controlling a predetermined device,
An arithmetic circuit for executing a predetermined control process and outputting a control signal to the LVDS;
A receiver that receives the LVDS output and converts it into a CMOS signal;
A transmitter that receives the CMOS signal from the receiver circuit and converts it into an LVDS signal;
And a controller for outputting an LVDS signal from the transmitter to the outside. The control device according to claim 1,
A control apparatus comprising a converter for transmitting the CMOS signal through a data line obtained by multiplying the number of unit bits of the control signal by n (n is a natural number of 2 or more). The control device according to claim 1 or 2,
The control device in which the receiver and the transmitter are configured on a separate substrate from the arithmetic circuit. A control device for controlling a predetermined device,
An arithmetic circuit that executes predetermined control processing and outputs a control signal in CMOS;
A converter for transmitting the CMOS signal through a data line obtained by multiplying the number of unit bits of the control signal by n (n is a natural number of 2 or more);
A transmitter that receives the CMOS signal from the converter and converts it to an LVDS signal;
And a controller for outputting an LVDS signal from the transmitter to the outside. The control device according to claim 4,
The transmitter is a control device configured with a separate substrate from the arithmetic circuit. A control device according to any one of claims 1 to 5,
The control device is configured as a device that controls a display device for displaying an image,
The arithmetic circuit generates a display data to be output to the display device. The control device according to any one of claims 1 to 6,
A control device that performs external output to the predetermined device via a twisted pair cable.