JP2019047917A - Game machine - Google Patents

Abstract

To provide a game machine that can resolve a malfunction of a display device.SOLUTION: A game machine includes a common mode choke coil CH for each differential signal line on an input side and an output side of a distributor 85 for receiving LVDS signal output from VDP circuit 52 and outputting a regenerated LVDS signal.SELECTED DRAWING: Figure 9

Description

  The present invention relates to a gaming machine that generates a big hit state by a lottery process caused by a gaming operation, and relates to a gaming machine that has eliminated a noise trouble of a display device.

  A ball game machine such as a pachinko machine is provided with a symbol starting port provided on a game board, a symbol display unit for displaying a series of symbol variation modes by a plurality of display symbols, and a special winning opening with an open / close plate. Is configured. Then, when the detection switch provided in the symbol starting port detects the passage of the game ball, it becomes a winning state, and after the game ball is paid out as a prize ball, the display symbol is fluctuated for a predetermined time in the symbol display portion. Thereafter, when the symbol is stopped in a predetermined manner such as 7/7/7, the jackpot is in a big hit state, the big winning opening is repeatedly opened, and a game state advantageous to the player is generated.

  Whether or not such a game state is to be generated is determined by a big hit lottery that is executed on the condition that the gaming ball has won the symbol starting opening, and the above-mentioned symbol fluctuation operation is based on this lottery result It has become a thing. For example, when the lottery result is in the winning state, the rendering operation called reach action or the like is executed for about 20 seconds, and then the special symbols are aligned. On the other hand, even in the case of the lost state, the same reach action may be executed, and in this case, the player pays attention to the transition of the rendering operation while strongly reassuring being in the big hit state. When the predetermined symbol is aligned with the stop line at the end of the symbol variation operation, the player is guaranteed to be in the big hit state.

  By the way, in this type of game machine, generally, the image effect in the display device, the lamp effect in which the illumination lamp blinks, and the sound effect from the speaker are executed in synchronization, and the movable object ( ) Is to be executed. Then, these rendering operations are realized by one or more computer devices (control means) that execute image control, lamp control, voice control, and motor control.

JP, 2017-006164, A Unexamined-Japanese-Patent No. 2016-214741 JP, 2016-034357, A JP, 2015-177885, A JP, 2013-128606, A

  Among various effects control described above, in particular, an image effect is important, and a configuration in which a movable display device is configured to execute an image effect is also known (Patent Document 1 to Patent Document 4). However, when a movable mechanism is added to the display device, the transmission distance of the image signal becomes longer by that amount, so there is a problem that the display device is easily influenced by noise and the like.

  That is, LVDS (Low Voltage Differential Signaling) transmission is generally said to be resistant to noise, but in order to display a high resolution image on a large screen display device, the pixel clock (dot clock) is Since the frequency increases, for example, when the transmission distance is about 1 m, all pixel information may not be accurately transmitted due to the influence of signal level attenuation and noise. In addition, a long signal transmission line may function as an antenna and emit EMI (Electro Magnetic Interference) noise.

  Therefore, an unnatural flicker may occur on the display screen, or a black screen may be displayed for an instant only on the basis of a transmission IC that transmits an LVDS signal or a fail safe function of the display device. Certain image effects may be ruined.

  Here, although the configuration of Patent Document 5 is known as a countermeasure against noise, Patent Document 5 converts RGB parallel data (for example, 3 × 8 bits) into an LVDS signal in the liquid crystal relay substrate 320 (see FIG. 5). It only teaches translating. That is, arranging the liquid crystal relay substrate 320 receiving the RGB data output from a VDP (Video Display Processor) at a position away from the VDP is virtually impossible from the viewpoint of the number of transmission lines and the noise resistance. The configuration of 5 can not be a countermeasure against noise in the LVDS transmission line.

  The present invention has been made in view of the above problems, and it is an object of the present invention to provide a gaming machine capable of eliminating a malfunction of a display device.

  In order to achieve the above object, the present invention controls an image effect corresponding to a lottery result of a lottery process executed due to a predetermined switch signal, based on a control command received from another control means. It is a game machine provided with a control means, wherein the sub-control means outputs a drawing instruction for specifying display content of a display device for executing an image effect, and effects control means for controlling the image effect; A data storage unit for storing compressed data to be a component of a still image and / or a moving image, and an image signal generated by accessing the data storage unit based on the drawing instruction received from the effect control unit are LVDS (Low Voltage Differential Signaling) image forming means capable of outputting in the form of a signal, and between the image forming means and the display device, it is high relative to the common mode signal A relay substrate on which an inductor exhibiting an impedance is disposed is provided, and the relay substrate is configured to transmit an LVDS signal passed through the inductor to a display device.

  Preferably, the inductor should be disposed for each differential signal line, and it is preferable that the relay substrate further have a protective element which performs a shorting operation at the time of electrostatic discharge.

  Preferably, the relay substrate is further provided with an electronic circuit element that receives the LVDS signal output from the image generation unit and outputs a regenerated LVDS signal. In this case, the inductors are preferably disposed on the input side and the output side of the electronic circuit element. Preferably, the display device is configured to be movable.

  In any case, it is preferable that a plurality of the display devices are disposed and the relay substrate is disposed corresponding to each display device, and the plurality of display devices include the number of vertical pixels of the display screen, Preferably, one or more pairs of display devices with the same number of horizontal pixels are included.

  In addition to the image effect, the sub-control means uniformly controls the lamp effect for driving the lamp, the sound effect for driving the speaker, and all or part of the movable effect for moving the movable object. It is preferable to be configured to have

  In the present invention, by providing a relay substrate mounted with a relay circuit having a special configuration, it is possible to realize a gaming machine capable of eliminating noise troubles of a display device.

It is a perspective view of a pachinko machine shown in an example. It is the front view which shows the game board of the pachinko machine of FIG. 1, and illustrates operation | movement of each display apparatus. It is a perspective view which shows the movable mechanism of a display apparatus. BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram which shows the whole structure of the pachinko machine shown to an Example. FIG. 5 is a block diagram showing a circuit configuration of an effect IF substrate, an effect control substrate, and a liquid crystal IF substrate. It is a block diagram showing an internal configuration of a compound chip in charge of various rendering operations. It is drawing explaining the memory content of memory, and the operation | movement procedure which implement | achieves an image presentation. It is drawing explaining operation of a display circuit. It is drawing which shows the structure of a LVDS relay board. It is drawing which shows the internal structure of the transmission IC mounted in the LVDS relay board. It is drawing explaining operation of a transmission IC. It is a flow chart explaining an internal operation of a compound chip. 6 is a diagram for describing an operation of a CPU and an operation of an internal circuit of a VDP circuit. It is a block diagram explaining another Example. It is drawing explaining the operation | movement of another Example. It is drawing explaining another apparatus structure. 17 is a drawing for describing a part of the device configuration of FIG. 16;

  Hereinafter, the present invention will be described in detail based on examples. FIG. 1 is a perspective view showing a pachinko machine GM of the present embodiment. The pachinko machine GM has a rectangular frame-shaped wooden outer frame 1 detachably mounted on the island structure, and a front frame 3 pivotally mounted so as to be openable and closable through a hinge 2 fixed to the outer frame 1. It is configured. In the front frame 3, the game board 5 is detachably mounted not from the back side but from the front side, and on the front side, the glass door 6 and the front plate 7 are pivotally connected so as to be openable and closable.

  On the outer periphery of the glass door 6, the electric decoration lamp by LED lamp etc. is arrange | positioned in substantially C shape. On the other hand, a total of three speakers are disposed at the upper left and right positions and the lower side of the glass door 6. The two speakers disposed at the top output the sound of the left and right channels R and L, respectively, and the lower speakers output a deep bass.

  An upper plate 8 for storing game balls for firing is mounted on the front plate 7, and a lower plate 9 for storing game balls overflowed or removed from the upper plate 8 at a lower portion of the front frame 3, and a firing handle And 10 are provided. The firing handle 10 is interlocked with the firing motor, and the game ball is fired by a striking rod operating according to the rotation angle of the firing handle 10.

  A chance button 11 is provided on the outer peripheral surface of the upper plate 8. The chance button 11 is provided at a position where it can be operated by the left hand of the player, and the player can operate the chance button 11 without releasing the right hand from the launch handle 10. Although the chance button 11 does not function normally, the built-in lamp is turned on to be operable when the game state is the button chance state. The button chance state is a game state provided as necessary.

  The right side of the upper plate 8 is provided with an operation panel 12 for ball lending operation to a card-type ball lending machine, and a number display section for displaying the remaining amount of card with a 3-digit number and balls for gaming balls for a predetermined amount A ball lending switch instructing lending and a return switch instructing return of the card at the end of the game are provided.

  As shown in FIG. 2, on the surface of the game board 5, a guide rail 13 consisting of an outer rail and an inner rail made of metal is annularly provided, and a central opening HO is provided substantially at the center thereof. And under the central opening HO, the movable effect body (not shown) is stored in the concealed state, and at the time of the movable advance notice effect, the movable effect body rises and becomes the exposed state, so that it has a predetermined reliability. We have achieved a preview effect. Here, the notice effect is an effect that indefinitely notifies that the jackpot state advantageous to the player is brought in, and the reliability of the notice effect means the probability that the jackpot state is brought.

  Further, in the central opening HO, a pair of display devices DS1a and DS1b configured by liquid crystal color displays are movably disposed. Although there is no limitation, the pair of display devices DS1a and DS1b each have a pixel number of 800 × 600 pixels, and have a diagonal dimension of about 12.1 inches. A proper place of the display devices DS1a and DS1b functions as a special symbol display unit, and a special symbol relating to a lottery result of the big hit lottery is variably displayed.

  Then, when a big hit lottery is executed due to the game ball winning to the symbol starting opening 15a, 15b, the variation display of the special symbol is started on the front of the background image displayed on the display devices DS1a, DS1b, The lottery result of the big hit lottery is informed based on the stop mode at the end of the variable display. In addition, in the middle of this fluctuation display, reach production which expects the invitation of the big hit state may be executed, and notice production is executed by the image production where various characters appear at appropriate timing. There is also.

  Next, the movable mechanism STR of the display device DS1a and the display device DS1b will be described based on FIGS. 2 (b) and 3. FIG. FIG. 3A is a perspective view of the main part of the movable mechanism STR as viewed from the back side, and FIG. 3B is a perspective view of the movable mechanism STR as viewed from the front side.

  As shown in FIG. 3A, this movable mechanism STR is driven by the two left and right drive motors MOR and MOL, which integrally rotate in conjunction with each other, and the motors MOR and MOL, via the rotary rollers RO and RO. A pair of left and right rear holding pieces HLb and HLb held by the left and right fan belts BT and BT at the rear position and a rear base plate BSb fixed to the rear holding pieces HLb and HLb A pair of left and right front holding pieces HLa, HLa held on the left and right fan belts BT in the front position, and a front base plate BSa fixed to the front holding pieces HLa, HLa A total of four guide poles GDa, GDa, GDb, and GDb are included.

  The display device DS1b is fixed to the rear base plate BSb, while the display device DS1a is held by being fixed by the front base plate BSa. The front holding pieces HLa, HLa and the rear holding pieces HLb, HLb are provided with receiving holes for receiving the guide poles GDa, GDa, GDb, GDb, respectively, and are integrated with the display devices DS1a, DS1b. The holding pieces HLa and HLb are guided by the guide poles GDa and GDb corresponding to the holding pieces HLa and HLb, and are smoothly moved up and down in the vertical direction.

  FIG. 2B shows the positional relationship between the two display devices DS1a and DS1b and the movement position. FIG. 2 (b 1) shows a steady state, and the display device DS 1 a located on the upper side and the display device DS 1 b located on the lower side are continuous in the vertical direction without overlapping, so 12.1 inches Form a display screen twice as much. In addition, since the lower display frame FM of the display device DS1a coincides with the position of the upper display frame of the display device DS1b, the two display devices DS1a and DS1b remove one display screen except for the lower display frame FM. Form.

  Here, since the two drive motors MOR and MOL are configured to integrally rotate in conjunction with each other, for example, when the drive motors MOR and MOL start integral rotation in the counterclockwise direction shown, the upper display device The lower display device DS1b is raised in response to the lowering of the DS1a.

  Then, after the two display devices DS1a and DS1b polymerize in the front-rear direction through the polymerization state of FIG. 2 (b2), when the display device DS1a further descends and reaches the limit position, the state of FIG. 2 (b3) is obtained. . As shown in the figure, the descent limit of the display device DS1a is the rise limit of the display device DS1b, and the display screen of twice 12.1 inches is displayed by the display device DS1b located on the upper side and the display device DS1a located on the lower side. It is formed.

  When the drive motors MOR and MOL integrally rotate in the clockwise direction in FIG. 2 (b3), they return to the steady state in FIG. 2 (b1) through the polymerization state in FIG. 2 (b2). Become.

  Therefore, in the present embodiment, by rotating the drive motors MOR and MOL clockwise or counterclockwise by an appropriate amount, the rendering operation including the initial state (b1) which is a steady state and the polymerization state (b2) The player is boosted by A, a rendering operation B including the polymerization state (b2) and the descent limit (b3), and a rendering operation C including the initial state (b1) and the descent limit (b3) . These movable effects are preferably executed as advance effects.

  As described above, since the display devices DS1a and DS1b move up and down, the signal transmission line (refer to the broken line) needs to have a length that allows this up and down movement. Therefore, in the present embodiment, control signals such as RGB image signals to be transmitted to the display devices DS1a and DS1b and synchronization signals are transmitted as LVDS signals (Low Voltage Differential Signaling), and at approximately the same distance from the effect control board 23 That is, a pair of LVDS relay boards 27a and 27b are provided at positions near the display devices DS1a and DS1b (see FIGS. 2B and 4 to 5).

  Here, as for the transmission distance from the effect control board 23 to the LVDS relay boards 27a and 27b, and the transmission distances from the LVDS relay boards 27a and 27b to the display devices DS1a and DS1b, normal transmission of the LVDS signal is experimentally obtained. It is limited to the secured distance (for example, within 1 m).

  Then, the LVDS relay boards 27a and 27b re-generate the LVDS signal by reserializing the RGB signal and control signal restored from the LVDS signal by the De-serialize processing, and transmitting the signal to the display devices DS1a and DS1b. (Figure 10). Therefore, in this embodiment, the signal control circuit 23 is positioned substantially at the positions of the LVDS relay boards 27a and 27b, so that the attenuation of the signal level is not a problem, and it is resistant to common mode noise. Since differential signaling is used, abnormal operation of the display devices DS1a and DS1b due to the influence of noise and the like can be avoided.

  However, even though it passes through the LVDS relay boards 27a and 27b, the LVDS signal transmission distance as a whole is quite long (for example, 1 m or more). The signal line functions as an antenna, and harmful levels of EMI (Electro Magnetic Interference) noise will be emitted.

  Therefore, in the present embodiment, EMI measures are taken by arranging the common mode choke coil CH (FIG. 9) in each LVDS signal line in the LVDS relay boards 27a and 27b. In addition, since electrostatic discharge (ESD: Electro-Static Discharge) is also a concern from the relationship of using a game ball, an ESD protection device is disposed on the LVDS relay boards 27a and 27b to protect electronic elements and EMI noise. The occurrence is suppressed to the minimum. In addition, these points are further mentioned later based on FIGS. 9-11.

  Referring back to FIG. 2 (a), the normal symbol display section 18 is provided on the right side of the pair of display devices DS1a and DS1b, and the normal symbols related to the winning lottery are variably displayed. ing.

  Also, in the game area where the game balls fall and move, the first symbol start port 15a, the second symbol start port 15b, the first large winning opening 16a, the second large winning opening 16b, and the gate 17 are disposed. . Each of these winning openings 15 to 17 has a detection switch inside, so that the passage of the game ball can be detected.

  At the upper part of the first symbol start port 15a, after the gaming ball entering from the introduction port IN moves in a seesaw-like or roulette shape, the effect stage 14 configured to be winning possible is arranged in the first symbol start port 15a There is. Then, when the game ball is won in the first symbol start opening 15a or the second symbol start opening 15b, the variation operation of the special symbol is configured to be started in the display devices DS1a and DS1b.

  The second symbol start port 15b is configured to be opened and closed by a motorized tulip provided with a pair of left and right opening / closing claws, and when the normal symbol of the normal symbol display portion 18 stops in a predetermined mode, only for a predetermined time Alternatively, the opening and closing claws are opened until a predetermined number of gaming balls are detected.

  In the normal symbol display section 18, when the gaming ball having passed the gate 17 is detected, the normal symbol fluctuates for a predetermined time, and it is determined by the random number value for lottery extracted at the passing time of the gate 17 of the gaming ball. Stop and display the stop symbol.

  The first large winning opening 16a is configured to have a slide board advancing and retracting in the front and rear direction, and the second large winning opening 16b is configured to have an opening and closing plate whose lower end is pivotally supported and opened forward. . The operations of the first large winning opening 16a and the second large winning opening 16b are not particularly limited, but in this embodiment, the first large winning opening 16a corresponds to the first symbol starting opening 15a, and the second large winning opening 16 b is configured to correspond to the first symbol start port 15 b.

  That is, when the game ball is won in the first symbol start opening 15a, the variation operation of the special symbol is started, and then, when the predetermined special symbol (big hit first symbol) is aligned, the first big hit special game is started, The slide board of the first big winning opening 16a is opened forward to facilitate the winning of the game ball.

  On the other hand, when a predetermined special symbol (big hit second symbol) is aligned as a result of the fluctuation operation started by the game ball winning to the second symbol start opening 15b, the second hit hit special game is started, the second large The opening and closing plate of the winning opening 16b is opened to facilitate the winning of the game ball. The game value of the special game (big hit state) is variously different corresponding to the big hit symbol etc. which are aligned, but which game value is to be awarded is previously based on the lottery result according to the winning timing of the game ball It is determined.

  In a typical big hit state, after the opening / closing plate of the big winning opening 16 is opened, the opening / closing plate closes when a predetermined time passes or a predetermined number (for example, 10) of game balls win. Such an operation is continued up to, for example, 15 times, and controlled in a state advantageous to the player. In addition, when the stop symbol after the change of the special symbol is a specific symbol, a bonus is given that the game after the end of the special game is in a high probability state (probable change state).

  FIG. 4 is a block diagram showing the entire circuit configuration of the pachinko machine GM for realizing each of the above-described operations, and FIG. 5 shows a part of the circuit in detail.

  As shown in FIG. 4, the pachinko machine GM receives power of AC 24 V and outputs various DC voltages, power supply abnormality signals ABN1 and ABN2, and a system reset signal (power reset signal) SYS etc. The main control board 21 which takes an overall role as a whole, the effect control board 23 for executing various rendering operations in unison based on the control command CMD received from the main control board 21, and the control command received from the main control board 21 A payout control board 25 for controlling the payout motor M based on CMD 'to pay out the game balls and a launch control board 26 for firing the game balls in response to the operation of the player are mainly formed.

  A one-chip microcomputer incorporating an 8-bit CPU is disposed on each of the main control board 21 and the payout control board 25, and each control operation is executed. In addition, the composite chip 50 including the built-in CPU circuit 54 and the VDP circuit 56 is disposed on the effect control board 23, and the CPU 60 of the built-in CPU circuit 54 performs lamp effects, sound effects, image effects, and feature effects. It uniformly controls the included rendering operations.

  In this specification, the functions implemented by the control boards 21, 23, 25 and the circuits mounted on the related boards are functionally generically referred to as the main control unit 21, the effect control unit 23, and the payout control. It may be called part 25. In addition, with respect to the main control unit 21, all or a part of the effect control unit 23 and the payout control unit 25 serves as a sub control unit.

  As shown in FIG. 4, the effect control board 23 includes a program memory 53 for storing a control program for controlling the above-described uniform effect operation, a CGROM 53 for storing material data of image effects, and a CPU 60 as a working area. DRAM 52 etc. are arranged.

  As shown, a rendering IF substrate 22 transferring the control command CMD output from the main control substrate 21 to the rendering control substrate 23, and a liquid crystal transferring the LVDS signal output from the VDP circuit 56 toward the display devices DS1a and DS1b. The male connector and the female connector are directly coupled and integrated without passing through the wiring cable.

  Then, the two systems of LVDS signals output from the VDP circuit 56 are transmitted to the LVDS relay substrates 27a and 27b via the liquid crystal IF substrate 24, and the substantially identical LVDS signals regenerated there are displayed on the display device DS1a. , DS1b.

  As shown in FIG. 5 and FIG. 9, the display devices DS1a and DS1b incorporate conversion circuits for de-serializing the LVDS signal, and RGB signals each having a length of 8 bits, a vertical synchronization signal VSYNC, and a horizontal synchronization signal A display screen is constructed based on the signal HSYNC, the enable signal DE, and the dot clock. In the case of the embodiment, since each display device DS1a, DS1b is 800 × 600 pixels and the vertical synchronization signal is 60 Hz, the pixel clock is about 40 MHz.

  The liquid crystal IF substrate 24 is mounted with a clock circuit (real time clock) RTC capable of measuring the current time, and a memory element (Static Random Access Memory) SRAM storing game performance information.

  On the other hand, the presentation IF substrate 22 is controlled by the CPU 60 of the built-in CPU circuit 54, and an audio processor 37 for reproducing an audio signal for realizing audio presentation, an audio ROM 38 for storing basic data of audio presentation, and an audio processor 37. And a digital amplifier 39 for D class amplification of the audio signal output by

  As shown, a lamp drive board 28 and a motor drive board 29 are connected to the effect IF board 22, and based on the control of the CPU 60 of the built-in CPU circuit 54, a lamp effect and a motor effect (feature effect) , Is to be realized.

  A plurality of effect motors Mi and drive motors MOL and MOR are connected in series to the motor drive substrate 29 of the present embodiment, and the drive motors MOL and MOR realize vertical movement of the display devices DS1a and DS1b. (See Figure 3). An origin sensor is disposed in each motor, and the sensor signal SNi which is an output of each origin sensor is configured to be acquired by the CPU 60 via the motor drive board 29.

  The pachinko machine GM is roughly divided into a frame side member GM1 surrounded by a broken line in FIG. 4 and a board side member GM2 fixed to the back of the game board 5. The frame side member GM1 includes the front frame 3 to which the glass door 6 and the front plate 7 are pivotally attached, and the wooden outer frame 1 outside the frame 3. Fixedly installed. On the other hand, the panel side member GM2 is replaced in response to the model change, and a new panel side member GM2 is attached to the frame side member GM1 instead of the original panel side member. In addition, all except the frame side member 1 are board side members GM2.

  As shown by the broken line frame in FIG. 4, the frame side member GM1 includes the power supply substrate 20, the payout control substrate 25, the emission control substrate 26, the frame relay substrate 34, the lamp drive substrate 35, and the motor drive substrate 36. , A sensor & switch board BD having a shift register for receiving a home sensor signal of the motor and other button signals, and these circuit boards are fixed to appropriate positions of the front frame 3 respectively.

  On the other hand, the main control board 21 and the effect control board 23 are fixed to the back of the game board 5 together with the display devices DS1 and DS2 and other circuit boards. And frame side member GM1 and board side member GM2 are electrically connected by connection connectors C1-C4 concentratedly arranged by one place.

  The power supply substrate 20 is connected to the main substrate relay substrate 31 through the connection connector C2, and is connected to the power supply relay substrate 32 through the connection connector C3. The power supply substrate 20 is provided with a power supply monitoring unit MNT that monitors the turning on and off of AC power. When the power supply monitor unit MNT detects that the AC power supply is turned on, it maintains the system reset signal SYS at the L level for a predetermined time, and then makes it transition to the H level.

  Further, when the power supply monitoring unit MNT detects that the AC power supply is shut off, it immediately causes the power supply abnormality signals ABN1 and ABN2 to transition to the L level. The power supply abnormality signals ABN1 and ABN2 quickly become H level after the power is turned on.

  By the way, the system reset signal of the present embodiment is generated by the DC power supply based on the AC power supply. Therefore, after detecting the turning on of the AC power (normally, turning on the power switch) and increasing it to H level, the H level is maintained unless the DC power supply voltage decreases to an abnormal level. Therefore, the system reset signal SYS does not reset the CPU even if the AC power supply is momentarily interrupted while the DC power supply voltage is maintained. The power supply abnormality signals ABN1 and ABN2 are output even in the momentary interruption of the AC power supply.

  The main board relay board 31 outputs the power supply abnormality signal ABN1 output from the power supply board 20, the backup power supply BAK, and DC5V, DC12V, and DC32V to the main control unit 21 as it is. On the other hand, the power supply relay board 32 outputs the system reset signal SYS received from the power supply board 20 and the AC and DC power supply voltages to the effect IF board 22 as it is. Then, the effect IF substrate 22 outputs the received system reset signal SYS to the effect control unit 23 as it is.

  On the other hand, the payout control board 25 is directly connected to the power supply board 20 without passing through the relay board, and the same power supply abnormality signal ABN2 and backup power supply BAK as received by the main control unit 21 are directly connected with other power supply voltages. In the form of

  The system reset signal SYS output from the power supply substrate 20 is a power supply reset signal indicating that the AC power supply 24V is turned on to the power supply substrate 20, and the built-in CPU circuit 54 of the effect control unit 23 The power is reset together with the circuit elements and the internal circuit including the VDP 56.

  However, the system reset signal SYS is not supplied to the main control unit 21 and the payout control unit 25, and a power reset signal (CPU reset signal) is generated in the reset circuit RST of each of the circuit boards 21 and 25. ing. Therefore, for example, even if the connection connector C2 rattles or noise is superimposed on the wiring cable, there is no possibility that the CPUs of the main control unit 21 and the payout control unit 25 are abnormally reset.

  Since the effect control unit 23 executes the effect operation in a subordinate manner based on the control command CMD from the main control unit 21, the effect control unit 23 is outputted from the power supply substrate 20 in order to avoid complication of the circuit configuration. The system reset signal SYS is used.

  Each of the reset circuits RST provided in the main control unit 21 and the payout control unit 25 has a built-in watchdog timer, and each CPU unless it receives a regular clear pulse from the CPU of each control unit 21 or 25. Is forcibly reset.

  Further, in this embodiment, the RAM clear signal CLR is generated by the main control unit 21 and transmitted to the one-chip microcomputer of the main control unit 21 and the payout control unit 25. Here, the RAM clear signal CLR is a signal for determining whether or not to initialize all areas of the built-in RAM of the one-chip microcomputer of each of the control units 21 and 25, and it is ON of the initialization switch SW operated by the clerk. It has a value corresponding to the / OFF state.

  The main control unit 21 and the payout control unit 25 receive the power supply abnormality signals ABN1 and ABN2 from the power supply substrate 20 to start necessary termination processing prior to the power failure or the end of business. The backup power supply BAK is a DC5V DC power supply that holds data of the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 25 even after the AC power supply 24V is shut off due to business closing or power failure. Therefore, the main control unit 21 and the payout control unit 25 can resume the game operation before the power is turned off (power supply backup function). In this pachinko machine, the memory contents of the RAM of each one-chip microcomputer are designed to be held for at least several days.

  As shown in FIG. 4, the main control unit 21 transmits a control command CMD ′ to the payout control unit 25 via the main board relay substrate 31, while the payout control unit 25 indicates a payout operation of the gaming ball. A prize ball counting signal, a status signal CON related to an abnormality in the dispensing operation, and an operation start signal BGN are received.

  In addition, the main control unit 21 is connected to each game component of the game board 5 via the game board relay board 30. And while receiving the switch signal of the detection switch incorporated in each winning a prize mouth 16-17 on a game board, solenoids, such as an electrically driven tulip, are driven.

  As described above, the rendering IF substrate 22, the rendering control substrate 23, and the liquid crystal IF substrate 24 are integrated by connector connection, and the rendering control unit 23 is connected from the power supply substrate 20 via the power relay substrate 32. It receives the DC voltage of each level and the system reset signal SYS.

  As shown in FIG. 5, the built-in CPU circuit 54 of the effect control board 23 receives the system reset signal SYS and other signals via the input buffer 40 of the effect IF board 22. Specifically, the parallel port (PIO) 62 of the built-in CPU circuit 54 receives the control command CMD and the strobe signal STB via the input buffer 40.

  The built-in CPU circuit 54 of the effect control unit 23 executes the effect operation based on the control command CMD. Specifically, serial port (SIO) 61 of built-in CPU circuit 54 serially transmits lamp drive signal SDATA to driver ICs mounted on lamp drive boards 28 and 35 in synchronization with clock signal CK. Thus, a lamp group composed of a large number of LED lamps and illumination lamps is driven to realize a lamp effect based on the control command CMD.

  Similarly, the serial port 61 of the built-in CPU circuit 54 serially transmits the motor drive signal SDATA to the driver ICs mounted on the motor drive boards 29 and 36 in synchronization with the clock signal CK, thereby providing a control command. Realization of feature based on CMD is realized.

  As shown in FIG. 5, in the present embodiment, five serial lines (see CK0 to CK4) are realized by five channels (CH0 to CH4) of the serial port 61, and the motor via the output buffer 43 is realized. The clock signal CK0 and the drive signal SDATA0 are transmitted to the drive substrate 36 and the lamp drive substrate 35. The drive signal SDATA0 is a serial signal connecting the lamp drive signal and the motor drive signal.

  Then, after a series of serial signals SDATA0 are serially transmitted in synchronization with the clock signal CK0, the latch signal LT0 is output from the parallel port 62, and transmitted via the output buffer 43 to all driver ICs simultaneously. Thus, each driver IC obtains the serial signal SDATA0 transmitted to itself.

  Also, the clock signal CK1 is transmitted to the motor & switch board BD via the output buffer 43, and the sensor signal and the switch signal acquired by the shift register (not shown) of the sensor & switch board BD are Serial transmission is performed in synchronization with the clock signal CK 1, and the serial signal SDATA 1 is transmitted to the serial port 61 via the input buffer 41.

  The latch signal LT1 is output from the parallel port 62 to the motor & switch board BD prior to the serial transmission, and the sensor & switch board is synchronized with the latch signal LT1. The BD shift register serially converts the sensor signal and the switch signal.

  The above points are the same for the lamp drive board 28 and the motor drive board 29. That is, the serial port 61 transmits the clock signal CK2 and the drive signal SDATA2 to the lamp drive board 28 via the output buffer 44 to realize the lamp effect. Note that after serial transmission, a latch signal LT2 is output from the parallel port 62.

  On the other hand, the serial port 61 transmits the clock signal CK3 and the drive signal SDATA3 to the motor drive board 29 via the output buffer 45 to realize the necessary feature effects. Also in this case, after serial transmission, a latch signal LT3 is output from the parallel port 62.

  The motor drive board 29 updates the motor drive signal based on the latch signal LT3, and drives the effect motors M1 to Mi and the drive motors MOL and MOR. As described above, each of the motors M1 to Mi, MOL, and MOR has an origin sensor disposed therein, and the sensor signal SNi of each origin sensor is a parallel input of the shift register disposed on the motor drive board 29. It is configured to be transmitted to the terminal.

  In response to this configuration, after parallel port 62 outputs latch signal LT4 to the shift register of motor drive board 29 via output buffer 45, serial port 61 passes via output buffer 45. The clock signal CK4 is transmitted to the shift register of the motor drive board 29.

  The sensor signal SNi serially converted in synchronization with the latch signal LT4 is serially transmitted in synchronization with the clock signal CK4, and this serial signal SDATA4 is transmitted to the serial port 61 via the input buffer 42 and is transmitted to the CPU 60. It is acquired.

  Subsequently, the effect control unit 23 will be described in detail with reference to FIGS. 6 to 8. First, FIG. 6A is a circuit block diagram illustrating the composite chip 50 constituting the effect control unit 23 including the related circuit elements. As illustrated, the composite chip 50 of the embodiment incorporates the built-in CPU circuit 54 and the VDP circuit 56. The built-in CPU circuit 54 and the VDP circuit 56 are connected through the CPUIF circuit 55 which relays transmission / reception data to each other, and the VDP circuit 56 supplies the V-blank interrupt signal (VBLANK) to the built-in CPU circuit 54. It is supposed to be

  Here, the V blank interrupt signal corresponds to the vertical synchronization signal of the display device DS1a, and defines the timing at which the output of image data for one frame of the display device DS1a is completed every 1/60 seconds. In this embodiment, of the three display circuits 74A / 74B / 74C, the display circuits 74A / 74B function steadily, but the display circuits 74B and the display circuits 74A have the same configuration and are in synchronization with each other. As it operates, the vertical synchronization signal (V blank interrupt signal) virtually means that the output operation of the display circuit 74A / 74B has ended.

  Although the sequence operation based on the V blank interrupt will be described later, as shown in FIG. 6, the control program (PROGRAM_ROM) 51 for storing the control program and necessary control data in a nonvolatile manner and about 2 M bytes in the CPUIF circuit 55. A work memory (RAM) 57 having a storage capacity of is connected, and each is configured to be accessible from the built-in CPU circuit 54.

  The built-in CPU circuit 54 is a circuit having the same performance as a general-purpose one-chip microcomputer, and the CPU 60 for controlling image rendering and other rendering operations collectively based on the control program of the control memory 51 and the program runaway. When this happens, the watchdog timer (WDT) 58 that resets the CPU forcibly, the RAM 59 that has a storage capacity of about 16 kbytes and is used as a work area for the CPU, and the DMAC (Direct Memory) that realizes data transfer without going through the CPU And a serial port (SIO) 61 having a plurality of input ports Si and output ports So, and a parallel port (PIO) 62 having a plurality of input ports Pi and output ports Po. ing.

  As described above, four channels (CH0 to CH4) of serial port 61 perform serial transmission of motor drive data (CH0, CH2), serial transmission of lamp drive data (CH4), and serial reception of sensor signals (CH1). , CH 4).

  In the present specification, for convenience, the expressions “serial port 61 and parallel port 62” are used, but in the effect control unit 23, inputs operating independently to the serial port 61 and parallel port 62 are used. Port and output port are included. The same applies to the input / output circuit 64p and the input / output circuit 64s described below.

  The parallel input / output port 62 is connected to an external device (effect control board 22) through the input / output circuit 64p. Then, as described with reference to FIG. 5, the CPU 60 receives the control command CMD and the interrupt signal STB output from the main control unit 21 via the input circuit 64p and the parallel input port Pi.

  Next, the VDP circuit 56 will be described. The VDP circuit 56 includes an CGROM 53 for storing compressed data which is a component of still and moving images constituting image effects, and an external DRAM (Dynamic) having a storage capacity of about 4 Gbits. A Random Access Memory) 52 and a pair of display devices DS1a and DS1b are connected. As illustrated, the display devices DS1a and DS1b receive the LVDS signals LVDS1 and LVDS2 via the LVDS relay boards 27a and 27b.

  In this embodiment, the CGROM 53 is configured by a flash SSD (solid state drive) configured by a NAND flash memory having a storage capacity of about 62 Gbits, and is configured to obtain necessary compressed data by serial transmission. . As a result, the problem of skew (difference in transmission speed for each bit data) that inevitably occurs in parallel transmission is eliminated, and ultimate high-speed transmission operation is possible.

  Note that while NAND flash memory is mechanically stable and faster than hard disks, and can be accessed at high speed, it is a sequential access memory, so compared to DRAM and SRAM (Static Random Access Memory), it has an access speed. However, the access speed is slower in the following order: built-in VRAM 71> external DRAM 52> CGROM 53. However, by executing a preload operation of reading a group of compressed data (CG data) into the DRAM 52 prior to the drawing operation, smooth random access of CG data at the time of drawing operation can be realized.

  More specifically, the VDP circuit 56 has a register group 70 in which various operation parameters that define the operation of the VDP are set, and about 48 M bytes used when generating image data to be displayed on each of the display devices DS1a and DS1b. A VRAM (Video RAM) 71, a data transfer circuit 72 for controlling data transmission / reception between each part in the chip and data transmission / reception outside the chip, a preloader 73 for executing a preload operation, and image data of the VRAM 71 are read Image processing is executed in parallel, a display circuit 74 of three systems (A / B / C), a graphics decoder 75 for decoding compressed data read from the CGROM 53, and still image data and moving image data after decoding. To generate image data for one frame of each display device DS1a, DS1b in combination with As part of the operation of the path 76 and the drawing circuit 76, a geometry engine 77 that generates a stereoscopic image by appropriate coordinate conversion, an SMC unit 78 capable of transmitting and receiving serial data, and display of three systems (A / B / C) An output selection unit 79 appropriately selecting and outputting the output of the circuit 74, two systems of LVDS units 80a and 80b converting image data output by the output selection unit 79 into LVDS signals, and image data output by the output selection unit 79 Digital RGB unit 80c for parallel output of digital RGB signals, CPUIF unit 81 for relaying data transmission / reception with CPUIF circuit 55, CG bus IF unit 82 for relaying data reception from CGROM 53, and external DRAM 52 VRAMIF relays data transmission / reception between the DRAMIF unit 83 relaying data transmission / reception and the VRAM 71 It is configured to include a 84, a.

  Although not particularly limited, in this embodiment, the display circuit 74A of the three lines (A / B / C) of display circuits 74 corresponds to the first LVDS unit 80a, and the display circuit 74B is the second LVDS unit 81b. , And the display circuit 74C corresponds to the digital RGB unit 80c. The first LVDS signal LVDS1 and the second LVDS signal LVDS2 are transmitted to the display devices DS1a and DS1b via the LVDS relay boards 27a and 27b, respectively. When the third display device is disposed, the display circuit 74C and the digital RGB unit 80c are used (see FIG. 14C), but in the embodiment shown in FIG. 6, these are not used. .

  FIG. 6B shows the relationship among the CPUIF unit 81, the CG bus IF unit 82, the DRAM IF unit 83, and the VRAMIF unit 84, and the register group 70, the CGROM 53, the DRAM 52, and the VRAM 71. About 70, the part is described concretely. As shown, the CGROM 53 and the CG bus IF unit 82 are connected by a serial line, and the CGROM 53 is sequentially accessed in response to the transmission of the address information Tx, and a group of CG data (compressed data) Rx is read out sequentially It is supposed to be

  The CG data read from the CGROM 53 is stored in the VRAM 71 via the CG bus IF unit 82 → VRAMIF unit 84 in this embodiment in which the preloader 73 is not functioned, but the arrow at timing T1 + δ in FIG. This read operation is shown. As shown in FIG. 7, in the VRAM 71, a still picture decoding area and a moving picture decoding area are secured as working areas of the graphics decoder 75, and CG data is compressed at a position according to the type of CG data. It is stored as it is. Further, as shown in FIG. 7 and FIG. 8, the VRAM 71 also secures a frame buffer FB area in which image data of one frame after decoding is arranged.

  On the other hand, when the preloader 73 is made to function, the CG data is stored in the preload area of the DRAM 52 via the CG bus IF unit 82 → DRAM IF unit 83 prior to the timing necessary for the decoding process, It is randomly accessed at proper timing and transferred to the VRAM 71. However, the CG data stored in the still image decoding area or the moving image decoding area of the VRAM 71 is decoded by the graphics decoder 75 and then the frame of the VRAM 71 is processed by the drawing circuit 76 regardless of whether the preloader 73 functions. It is expanded to the appropriate place in the buffer FB area. In addition, the arrow of timing T1 + (delta) 'of FIG. 7 has shown this operation | movement.

  Referring back to FIG. 6A, the data transfer circuit 72 transfers data between the resource (storage medium) in the VDP circuit and the external storage medium as a transfer source port or transfer destination port. Is a circuit that performs The transfer source port includes, in addition to the VRAM 71, a storage medium (resource) connected to the CPU bus, the CG bus, and the external DRAM bus. Similarly, the transfer destination port includes, in addition to the VRAM 71, storage media connected to the CPU bus, the CG bus, and the external DRAM bus. In addition, the data transfer circuit 72 is also in charge of transmitting the display list DL for specifying a display image for one frame by a group of drawing commands to the drawing circuit 76 (preloader 73 if necessary).

  The preloader 73 is a circuit that interprets the display list DL transmitted by the data transfer circuit 72 and transfers CG data on the CGROM 53 referenced therein to a preload area of the DRAM 52 specified in advance. At this time, the preloader 73 outputs the display list DL in which the CG data reference destination is rewritten to the address after transfer. Then, the rewritten display list DL is transmitted by the data transfer circuit 72 to the drawing circuit 76.

  However, in this embodiment, the preloader 73 is not used. On the other hand, when the preloader 73 is used, a sufficient storage area preload area is set in the external DRAM 52 based on the setting value of the preloader register (see FIG. 6B). Then, in this case, as long as the storage area set as a preload area is used up, the preloaded compressed data is maintained without being overwritten and erased by the subsequent compressed data. Therefore, in the second embodiment using the preload process, the CGROM 53 is accessed only when the necessary compressed data does not exist in the preload area. Since a sufficient storage area is secured in the preload area, there is no problem even if CG data for a plurality of frames are preloaded at once.

  The drawing circuit 76 sequentially analyzes drawing commands of the display list DL (see the timing T1 ′ in FIG. 7) transferred from the built-in RAM 59 to the external DRAM 52 by the data transfer circuit 72 to obtain the graphics decoder 75 or geometry It is a circuit that draws an image of one frame of the display devices DS1a and DS1b in the frame buffer FB formed in the VRAM 71 in cooperation with the engine 77 and the like.

  That is, the drawing circuit 76 performs Displaylist Analyzer (hereinafter referred to as DL analyzer) which analyzes drawing commands of the display list DL, Geometry Pipeline which executes coordinate conversion of a vertex and lighting operation, and source address and destination in triangle drawing. Performs processing such as Triangle Rasterizer that generates addresses, Texture Sampler that samples textures and performs bilinear filtering, Framebuffer Sampler that acquires frame buffer and Z buffer for inter-pixel operation, and processing such as α blending It comprises pixel generator etc. which generate the pixel data written in FB.

  Here, the display list DL is composed of a group of drawing commands described in the order of drawing, and includes a command specifying which image is to be drawn at which position of one frame, A storage location (source address) such as a CGROM of the image to be displayed is also specified. Then, the DL analyzer of the drawing circuit 76 interprets such a display list DL and cooperates with other Geometry Pipeline, Triangle Rasterizer, Texture Sampler, Framebuffer Sampler, and Pixel Generator, and a frame secured in the built-in VRAM 71. In the buffer FB, image data of one frame of each of the display devices DS1a and DS1b is generated (see FIG. 8).

  The display list DL of this embodiment is roughly divided into a drawing command group for the display device DS1a and a drawing command group for the display device DS1b.

  As shown in FIG. 8, the frame buffer FB of this embodiment is divided into three sections (FBa, FBb, FBc) corresponding to the display circuits 74A / 74B / 74C, but each frame buffer FB (FBa, FBb, The drawing position of FBc) is specified by a predetermined drawing command described in the display list DL.

  In the frame buffer FBa, image data of one frame (800 × 600 pixels) of the display device DS1a is disposed, and in the frame buffer FBb, image data of one frame (800 × 600 pixels) of the display device DS1b is disposed. Be done.

  In the present embodiment, since the display circuit 74C is not used, the frame buffer FBc does not function. Each of the functional frame buffers FB (FBA, FBb) is a double buffer functionally divided into a drawing area and a display area, and uses two areas (area 0 and area 1) alternately. We switch and use. That is, when the drawing circuit 76 is writing image data in one of the two areas, the display circuit 74 reads out and outputs the image data of the other area.

  Although not particularly limited, in the present embodiment, one frame of the display devices DS1a and DS1b is composed of three or more types of images (moving images and still images) in the maximum state. That is, in the display devices DS1a and DS1b, in the maximum state, one or a plurality of moving images are reproduced, while a still image which changes over time and changes over time is displayed so as to be superimposed on the background image. .

  The basic shape of the still image is stored in advance as a sprite image in the CGROM 53, and this basic shape is appropriately enlarged / reduced / rotated / deformed, and the arrangement position is changed to realize temporal change. ing. On the other hand, a moving image is a so-called movie which changes smoothly for a predetermined time, and a plurality of frames are compressed by a moving image compression method such as the MPEG coding method and stored in the CGROM 53.

  Although not particularly limited, the moving image of this embodiment is an IP stream moving image composed of I frames and P frames. Here, the P frame means a frame composed of P pictures (Predictive Picture) encoding differences with data predicted from a past frame, and although the compression rate is high, sequential reproduction is essential. On the other hand, an I frame means a frame composed of an I picture (Intra Picture) that can be encoded independently without depending on other frames.

  Corresponding to such a configuration, the graphics decoder 75 is divided into a still picture decoder and a moving picture decoder, and decodes the still picture and the moving picture encoded (compressed) by a predetermined compression algorithm by a corresponding decompression algorithm. (Stretching). For example, a still image is compressed by a predetermined algorithm for each image data forming one still image, and a P frame of an IP stream moving image is a plurality of still image data for realizing a series of moving images, It is compressed based on the data difference value etc.

  Next, the display circuit 74 is a circuit that reads out the image data of the frame buffer FB, performs final image processing, and outputs it (see FIG. 8). As shown in FIG. 8, in image processing in the display circuit 74, scaling processing in which a scaler functions to enlarge / reduce a frame image, subtle color correction processing, and dither in which the quantization error of the entire image is minimized. Ring processing is included. Note that the scaling processing includes enlargement processing of frame data after moving image decoding for moving image data (vertical length reduced data) that has been reduced for vertical length.

  As shown in FIG. 8, three display circuits 74A / 74B / 74C that execute the above operation in parallel are provided, and each display circuit 74A / 74B / 74C is provided with a frame buffer FBa / FBb corresponding to each. The above-described final image processing can be executed by reading out the image data of / FBC. After these image processing, digital RGB data (24 bits in total) are output to the output selection circuit 79 together with the horizontal synchronization signal HSYNC and the vertical synchronization signal VSYNC.

  The output selection unit 79 transmits the output signal of the display circuit 74A to the LVDS unit 80a, and transmits the output signal of the display circuit 74B to the LVDS unit 80b. Then, as described above, the LVDS unit 80a and the LVDS unit 80b convert the image data (digital RGB data of 24 bits in total) into an LVDS signal, and add five pairs of transmitting clock signals. The dynamic signals LVDS1 and LVDS2 are output to the LVDS relay boards 27a and 27b.

  Next, the SMC unit 78 (Serial Management Controller) is a composite controller incorporating an LED controller and a motor controller. However, since the serial port (SIO) 61 is used in the present embodiment, the SMC unit 78 is not used.

  Regarding the internal circuits of the VDP circuit 56 described above and the operation thereof, the operation contents to be executed by the internal circuit are defined by the operation parameters (set values) set by the CPU 60 in the register group 70. The operation status value of the register group 70 can be identified by READ. The register group 70 means a large number of registers mapped to a memory space (0 to FFFFFH) of about 1 Mbyte on the memory map of the CPU 60, and the CPU 60 WRITEs (set) operation parameters via the CPU IF unit 81. The operation and the READ operation of the operation status value are performed (see FIG. 6 (b)).

  Setting values related to data transfer processing by data transfer circuit 72 between CPU 60 and internal circuits of VDP circuit 56 are stored in register group 70, such as "system control register" in which initial setting values related to system operation such as interrupt operation are written The “data transfer register” in which the “” is written, the “GDEC register” that can specify the execution status including the occurrence of an error in the graphics decoder 75, and the “draw register” in which the set values for the draw command and the drawing circuit 76 are written And “preloader register” into which setting values regarding the operation of the preloader 73 are written, “display register” into which setting values regarding each operation of the three divided display circuits A / B / C are written, LED controller ( "LED control register" where the set value related to SMC part 78) is written, motor control Over La (SMC unit 78) includes a a "motor control register" the setting value is written about, these control registers is composed each of a plurality of bytes long.

  More specifically, in the "preloader register", (1) setting whether to set the preload area in the DRAM 52 or VRAM 84, (2) the top address of the preload area, and (3) the preload data area, Setting of how many frames to use, (4) Data size per frame, etc. are set. Also, the data transfer source and the data transfer destination are set in the "data transfer register", and the start position of the frame buffer FBa / FBb / FBc in the "display register" corresponding to the display circuit A / B / C. And, the buffer size, the switching instruction of the drawing area and the display area which are temporally switched in each frame buffer FBa / FBb / FBc, the vertical / horizontal enlargement ratio of the scaler, etc. are set. Further, in the “drawing register”, “preloader register”, and “data transfer register”, the start of execution of each operation is instructed for the drawing operation, the preload operation, and the data transfer operation.

  In any case, the internal operation of the VDP circuit 56 is realized by the CPU 60 writing an appropriate setting value to any of the register group 70. Therefore, the CPU 60 realizes an image effect based on the display list DL based on the display list DL updated at an appropriate time interval and the set values for the registers constituting the register group 70 described above.

  Subsequently, the LVDS relay boards 27 a and 27 b will be described based on FIGS. 9 to 11. The two LVDS relay boards 27a and 27b have completely the same circuit configuration and circuit operation, and therefore, only the LVDS relay board 27a will be described below.

  As shown in FIG. 9, the VDP circuit 56 (LVDS section 80) and the LVDS relay board 27 are connected by five pairs of differential signal lines (LINE1 to LINE4 + CLK), and the LVDS relay board 27 and the display device DS1 Also, they are connected by 5 pairs of differential signal lines.

  Then, the display device DS1 incorporates an RGB conversion unit for executing the De-Serialize operation, and from the serial signals transmitted by five pairs of differential signal lines, an RGB signal, a vertical synchronization signal VSYNC, a horizontal synchronization signal The display screen is constructed by restoring the HSSYC, the data enable signal DE, and the like.

  A distributor (Repeater) 85 whose internal configuration is shown in FIG. 10A is disposed on the LVDS relay board 27a. Although the differential signal line LINE3 and the LVDS input RC1 and the LVDS output TC1 of the distributor are omitted in FIG. 8 for convenience of drawing, they are configured the same as the other parts. There is.

  As shown in FIG. 10A, the distributor 85 of the embodiment operates at a power supply voltage of 3.3 V and is divided into a 1st Link unit and a 2nd Link unit, and each of the LVDS receiver Rx and the LVDS transmitter Tx Is configured. Each part functions as a low voltage in which the power supply voltage 3.3 V is stably dropped by the linear regulator LDO (Low Dropout).

  Although not particularly limited, in this embodiment, only the 1st Link unit is used, and the LVDS reception unit Rx includes the LDVS signal LVDS1 / LVDS2 shown in FIG. 11A from the LVDS unit 80a / 80b of the VDP circuit 56. Is supplied (see FIG. 10 (b)). As shown in FIG. 11A, the LVDS signal is transmitted by the LVDS clock CLK corresponding to the pixel clock and five pairs of differential signal lines denoted as LINE1 to LINE4, and each of the LVDS receiver Rx It is supplied to the RCLK1 terminal and the RA1 to RD1 terminals.

  In the case of the present embodiment, since the RGB signals generated by the VDP circuit 56 are each 8 bits long (256 gradations for each pixel), the LVDS clock CLK is LVDS in one cycle (about 1/40 μs in this embodiment). The unit 80a outputs a total of 28 bits obtained by adding the horizontal synchronization signal HSYNC, the vertical synchronization signal VSYNC, the DATA enable signal DE, and the reserve signal RS to 24 bits of the RGB signal.

  Here, the DATA enable signal DE is a signal indicating whether the RGB signal is valid (drawing timing) or not, that is, whether it is a horizontal blanking period or a vertical blanking period, and the reserve signal RS is a signal according to this embodiment. , Is a dummy signal that is not utilized.

  Five pairs of differential signals including these 28 bits are supplied to the RCLK1 terminal and the RA1 to RD1 terminals of the LVDS reception unit Rx, but the RE1 terminal is not used as shown in FIG. ing. That is, the distributor 85 can transmit RGB signals each having a length of 10 bits (1024 gradations for each pixel), but handles only the upper 8 bits from which the lower 2 bits are deleted.

  The total of 28 bits of data is de-serialized in the LVDS reception unit Rx, and one HSYNC signal, one VSYNC signal, one DE signal, one R signal, eight bits, G for each cycle of the LVDS clock CLK. The signal is restored to 8 bits and the B signal to 8 bits.

  Then, in this embodiment, the restored RGB signals and the like pass through the Inter-Link Multiplex & De-Multiple section as they are, and are supplied to the LVDS transmission section Tx (see FIG. 10B). Then, in the LVDS transmission unit Tx, the LVDS signal is generated again by the Serialize process, and is output to five differential signal lines.

  FIG. 11C illustrates this relationship, and shows a state in which the regenerated LVDS signal is output from the TCLK1 terminal and the TA1 to TD1 terminals. The TE1 terminal is in an open state as with the RE1 terminal.

  Thus, the distributor 85 of the embodiment not only restores signal attenuation like a simple buffer circuit, but also, in the position of the LVDS relay board 27a, the HSYNC signal, the VSYNC signal, the DE signal, the R signal 8 The bit, 8 bits of G signal, and 8 bits of B signal are intentionally restored, and the LVDS signal is regenerated again.

  As described above, the transmission distance between the VDP circuit 56 and the LVDS relay substrate 27a is limited to a distance at which normal transmission of the LVDS signal is experimentally secured. Therefore, when evaluated from the display device DS1a, the LVDS relay substrate The presence of the VDP circuit 56 at the position 27a is substantially the same.

  Then, the transmission distance between the LVDS relay board 27a and the display device DS1a is also limited to the distance by which normal transmission of the LVDS signal is experimentally secured, so that the display trouble of the display device is resolved. Although the distance by which normal transmission is secured depends on the internal configuration of the gaming machine and the environment of the gaming hall, typically it is within 1 m, preferably within 80 cm, more preferably within 60 cm, LVDS By providing the relay substrate 27a, the overall length of the LVDS transmission line can be about 2 m to 1.2 m.

  Although the embodiment in which the Inter-Link Multiplex & De-Multiple unit is not functioned has been described above, the LVDS signal supplied to the LVDS reception unit Rx of the 1st Link unit is made to function by functioning the Inter-Link Multiplex & De-Multiple unit. Divided LVDS signals in which the pixel clock frequency (for example, 80 MHz) is dropped to 1/2 by stripe division can also be output from the LVDS transmitters Tx and Tx of the 1st Link unit and the 2nd Link unit (FIG. 10 (c) Single In / Dual Out).

  Such a configuration is employed in the embodiment shown in FIG. 14 (b), but a single LVDS relay board 27 suffices and one distributor 85 disposed there is sufficient. Here, stripe division means an operation of outputting RGB image data of one pixel from the 1st Link unit and outputting RGB image data of the other pixel from the 2nd Link unit for left and right pixels adjacent in the horizontal direction of the display screen.

  In addition, by making the Inter-Link Multiplex & De-Multiple unit work, a pair of LVDS signals supplied to the LVDS receivers Rx and Rx of the 1st Link unit and the 2nd Link unit are stripe-connected, and the pixel clock frequency is 2 The doubled connected LVDS signal can also be output from the LVDS transmitters Tx and Tx of the 1st Link unit (Dual In / Single OUT in FIG. 10 (d)).

  In stripe connection, RGB image data for one pixel restored by the receiving unit of the 1st Link unit and RGB image data for one pixel restored by the receiving unit of the 2nd Link unit at the same timing are adjacent to each other. This means an operation of generating a pixel and outputting it from the 1st Link unit.

  The operation of the distributor 85 transmits a pair of LVDS signals LVDS1 and LVDS2 having relatively low dot clocks to the vicinity of the display device, and the LVDS signals connected by the distributor 85 of the LVDS relay board 27 are displayed. It is suitable for the structure supplied to

  Returning to FIG. 9 and continuing the description, as shown in FIG. 9, the LVDS relay board 27 is in close proximity to the distributor 85 described above, and the termination resistance R (about 100 Ω) of the LVDS signal line and the common mode choke coil CH and a discharge absorption element ESD are arranged.

  Here, the common mode choke coil CH means a coil in which the winding directions of a pair of conductive wires wound around a single core are opposite to each other. Therefore, when current of the same phase flows in a pair of conducting wires, the directions of the magnetic fluxes become the same and high inductance is generated, so that common mode noise can be effectively suppressed.

  In differential signal lines such as LVDS signal lines, common-mode noise and other common-mode signals are canceled on the receiving side, so they do not adversely affect the receiving elements, but they are large in differential signal lines with a long transmission distance. When the level common mode noise flows, the differential signal line functions as an antenna to generate high frequency noise and adversely affect the display device and other electronic circuits.

  With this point taken into consideration, in this embodiment, the common mode choke coil CH is disposed for all the differential signal lines on the input side and the output side of the distributor 85 mounted on the LVDS relay substrate 27, so that EMI (Electro Magnetic Interference) Noise is effectively suppressed. Since the original LDVS signal is a normal mode (differential mode) signal, the magnetic flux is canceled inside the core, so the common mode choke coil CH does not function as an inductor.

  Further, the discharge absorbing element ESD is disposed in all the differential signal lines on the input side of the distributor 85. The discharge absorbing element ESD may be either semiconductor base (Zener diode type) or varistor type as long as it is an element that absorbs electrostatic discharge (Electro-Static Discharge) quickly. Is used to realize inter-electrode discharge different from that of the varistor (inter-electrode discharge type element).

  Here, the element of the inter-electrode discharge system means an element in which the internal electrodes are disposed to face each other in an insulating state, and when a high voltage is applied, a discharge occurs between the internal electrodes. By using such an element, it is possible to make the inter-terminal electrostatic capacitance smaller than that of the Zener diode type or the varistor type element, and to exert an effect excellent also in repeated tolerance.

  In this type of gaming machine, the high level of static electricity may be accumulated because the gaming ball travels cyclically, and there is concern that electrostatic discharge may occur in a long LVDS signal line, but electrostatic discharge should occur. However, since the discharge absorbing element ESD is momentarily turned on to absorb discharge energy immediately, damage to the distributor 85 and generation of EMI noise can be prevented.

  Although the voltage level of static electricity charged on a game ball or the like is very high, on the other hand, the stored energy itself is low, the stored energy can be eliminated immediately by the momentary ON operation of the discharge absorbing element ESD. In addition, since the capacitance between terminals is lower than that of the Zener diode type or the varistor type element, the transmission signal is not adversely affected. Although FIG. 9 shows the discharge absorbing element ESD as an equivalent circuit, it only shows an equivalent function, and it does not mean that a Zener diode is incorporated.

  Subsequently, with regard to the control operation of the image effect executed using the display devices DS1a and DS1b, the flowcharts of FIGS. 12A to 12D and the operation explanatory diagrams of FIGS. 8 and 13 are referred to. explain. These image effects are realized by the CPU 60 of the effect control unit 23 that receives the control command CMD from the main control unit 21 and the VDP circuit 56 that is instructed by the CPU 60 to function. The instruction from the CPU 60 to the VDP circuit 56 is specified by the operation parameter written to the register group 70.

  As shown in FIG. 12, the image rendering operation is performed based on display list DL update processing (FIG. 12A to FIG. 12B) executed by CPU 60 at predetermined time intervals and display list DL received from CPU 60. This is realized by the drawing circuit 76 operating and the respective sequence operations of the display circuit 74 (FIG. 12C to FIG. 12D). Note that the CPU 60 sets necessary operation parameters in the register group 70 at the time of power supply reset and the necessary timing thereafter so that the drawing circuit 76 and the display circuit 74 realize the sequence operation described below. There is.

  Based on the above, the CPU 60 starts the process of updating the display list DL every predetermined time δ (for example, 1/30 seconds) defined by the V blank interrupt every 1/60 seconds (ST1), and drawing The sequence operation of the circuit 76 and the display circuit 74 is started (ST2). As described with reference to FIG. 6A, the V blank interrupt means that the output operation of the display circuit 74A is finished, but the drawing circuit 76 and the display circuits 74A and 74B are intermittent based on the process of step ST2. Operationally in parallel (see FIG. 13).

  First, the sequence operation of the drawing circuit 76 and the display circuit 74 will be schematically described with reference to FIG. First, in the execution cycle starting from T1, the display list DL generated by the CPU 63 is interpreted by the drawing circuit 76 in the execution cycle starting from T1 + δ, and the image data generated by the drawing circuit 76 is created in the frame buffer FBa, FBb. Ru. In the display list DL, a series of drawing command strings specifying the display screens of the two display devices DS1a and DS1b are described in two sections.

  Further, in this embodiment, image data of 800 × 600 pixels are expanded in the frame buffers FBa and FBb by the drawing circuit 76, respectively. Then, these image data are output by the display circuits 74A and 74B in an execution cycle starting from T1 + 2δ. Therefore, in the present embodiment, one unit operation for the image effect is completed after three execution cycles.

  The above relationship is as described also in FIG. 7A, and CG data of the CGROM 53 is read out to the VRAM 71 at the timing of T1 + δ based on the display list DL transferred to the DRAM 52 at the timing of T1 ′. However, image data is created in the frame buffers FBa and FBb in the same execution cycle (limited to the time of need) (timing T1 + δ ′). Then, this image data is output to the display devices DS1a / DS1b through the communication paths (80a / 80b, 27a / 27b) shown in FIG. 9 at timing T1 + 2δ.

  The outline of the process has been described above. Subsequently, the process of step ST2 will be specifically described based on FIG. The CPU 60 sets a predetermined value in a predetermined display register corresponding to each of the display circuits 74A and 74B and instructs start of display operation to switch the display area of the display circuits 74A and 74B (ST10 to ST11).

  As shown in FIG. 7, the frame buffers FBa and FBb have a double buffer structure (0/1), one of which is a drawing area to be accessed by the drawing circuit 76, and the other is an access of the display circuit 74. It is a target display area. Then, the processing of steps ST10 to ST11 switches the drawing area and the display area, and the image data for one frame generated by the drawing circuit 76 in the frame buffers FBa and FBb so far is displayed at this execution cycle. The circuits 74A and 74B output the data to the display devices DS1a and DS1b.

  In the present embodiment, while the operation cycle of the display circuits 74A and 74B is set to 1/60 second, the operation cycle of the CPU 60 is 1/30 second, the display circuits 74A and 74B In practice, the same image data is output twice, and the same frame is displayed twice in succession.

  Along with the above processing (ST10 to ST11) for the display circuit 74, the CPU 60 instructs the predetermined drawing register that defines the operation of the drawing circuit 76 to start the operation of the drawing operation (ST12). As a result, the drawing circuit 76 also starts a predetermined operation every 1/30 seconds. The contents of operations to be executed by the drawing circuit 76 and the display circuit 74 are set in the drawing register and the display register by the CPU 60 at the time of power supply reset and the necessary timing thereafter, as described above.

  Referring back to FIG. 12 (b) to FIG. 12 (a), the CPU 60 instructs the sequence operation of the drawing circuit 76 and the display circuit 74 in the process of step ST2 described above, and then based on the image rendering scenario. Create a display list DL for the next frame. Here, the image rendering scenario is an embodiment of the image rendering specified by the control command CMD received from the main control unit 21.

  That is, in the image rendering scenario, a series of moving images continuing for a certain period of time, and a still image (including a background image and a preview image) for which the drawing position, the arrangement attitude, and the enlargement / reduction ratio are appropriately defined (1) The start time and end time of the moving image production of (2) which still picture, at which time, at which position, how to draw, etc. are defined. In addition, even if it says moving image effects, the drawing image of the display device only changes quickly and smoothly, and the same or different next image data (frame image data) is drawn on the display device at regular intervals. Is the same as a still image in terms of

  Then, the CPU 60 refers to the rendering scenario having such a configuration and lists a group of drawing commands for specifying the display image of the display devices DS1a and DS1b at each timing (T1, T1 + δ, T1 + 2δ,...). The generated display list DL is generated. The display list DL specifies which part of the moving image is to be displayed temporally by specifying the storage position of the CGROM 53 for a moving image, and for a still image such as a sprite image, it is stored in the CGROM 53 It defines, for example, at which position of the display device and how to draw the image.

  Although the drawing command string constituting display list DL is divided into two sections (DL = DLi1 + DLi2) corresponding to two display devices DS1a and DS1b, such display list DL is a data transfer instructed by CPU 60. The circuit 72 transfers data from the built-in RAM 59 to the external DRAM 52 (ST4). The arrow at timing T1 'in FIG. 7 illustrates this operation. It is not necessary for the CPU 60 to generate one display list DL for specifying one frame of each display device for each operation cycle, and a plurality of display lists DL1, DL2... For specifying display contents at a plurality of timings. It may be generated together in one operation cycle.

  Further, FIG. 13 shows the processing of step ST13 by the CPU 60 by a vertical arrow from the CPU 63 to the drawing circuit 76, and the processing of steps ST10 to ST11 by the CPU 60 from the CPU 63 to the display circuits 74A and 74B. It is indicated by a directional arrow.

  Next, the drawing operation performed by the drawing circuit 76, the graphics decoder 75, the geometry engine 77, etc. in cooperation with each other will be described with reference to FIGS. 12 (c) to 12 (d) and FIG. As shown in FIG. 13, this drawing operation is repeated every fixed time (δ), but for convenience, in the following description, the drawing operation after timing T1 + 2δ executed based on the rewritten display list DL1 will be described .

  The drawing circuit 76 sequentially analyzes drawing commands described in the display list DL1 which is the unprocessed and oldest display list among the display lists stored in the external DRAM 52 (FIG. 12 (c)). SS20) The graphics decoder 75 or geometry engine 77 is made to function for still images and moving images specified by the drawing command.

  Then, the still picture data and the moving picture data decoded by the graphics decoder 75 are expanded and developed in the still picture decoding area and the moving picture decoding area secured in the built-in VRAM 71, respectively (SS22 to SS23). Next, the drawing process is executed by writing the still image data or the moving image data after decoding in a predetermined position of the frame buffer FB (FBA, FBb) of the VRAM 71 in a drawing mode specified by the drawing command ( SS 24). Although the drawing mode includes the drawing position in the frame buffer FB (FBa, FBb), in the case of a sprite image or the like, the drawing attitude, the enlargement / reduction ratio, etc. may be further defined, and the geometry engine 77 works.

  The frame buffers FBa and FBb each have a double buffer structure divided into a drawing area and a display area. Therefore, in the drawing operation (SS24), the image data in the drawing areas of the frame buffer FBa and FBb is more accurately Will be written.

  In this way, when drawing processing for all drawing commands is completed, the next drawing operation started intermittently is put in a standby state (SS25). In FIG. 7, it is described by an arrow that a necessary image is drawn in the frame buffer FB (FBA + FBb) at the timing T1 + δ ′.

  Finally, the operation of the display circuit 74 will be described based on FIG. Although this display operation is also repeated every fixed time (δ), for convenience, in the following description, the display operation after timing T1 + 2δ shown in FIG. 13 will be described. As described above, at this timing, the image data (A1, B1) based on the display list DL1 is secured in the drawing area of the frame buffer FBa, FBb. And this drawing area functions as a display area in the display operation after timing T1 + 2δ.

  As shown in FIG. 12D, the display circuits 74A and 74B read out the image data (A1 and B1) stored in the display areas of the frame buffers FBa and FBb corresponding to the display circuits 74A and 74B, and output them to the output selection unit 79. To do (SS30). Here, the image data (A1) of the frame buffer FBa is image data specifying one frame of the display device DS1a, and the image data (B1) of the frame buffer FBb is image data specifying one frame of the display device DS1b It is.

  Thereafter, based on the operation of the output selection unit 79, the image data (A1) of the frame buffer FBa output by the display circuit 74A is output as the LVDS signal LVDS1 via the LVDS unit 80a, and the frame output by the display circuit 74B. The image data (B1) of the buffer FBb is output as the LVDS signal LVDS2 via the LVDS unit 80b.

  As shown in FIG. 9, the LVDS signal LVDS1 related to the image data (A1) output from the LVDS unit 80a is regenerated by the LVDS relay board 27a and transmitted to the display device DS1a to display an 800 × 600 pixel display screen. To realize.

  Similarly, an LVDS signal LVDS2 related to image data (B1) output from the LVDS unit 80b is regenerated by the LVDS relay board 27b and transmitted to the display device DS1b to realize a display screen of 800 × 600 pixels.

  The above operation is the same not only for display operation starting at timing T1 + 2δ, but also for display operation starting at timing T1 + 3δ. That is, in the display operation starting from the timing T1 + 3δ, the display circuits 74A and 74B output the image data A2 and B2 to be displayed on the display devices DS1a and DS1b.

  Subsequently, since the same operation is repeated, the display devices DS1a and DS1b display the image data Ai and Bi updated every 1/30 seconds. Since the display circuits 74A and 74B are initially set to operate every 1/60 seconds, the same image data Ai and Bi are continuously output twice as described above. Therefore, the moving image displayed on the display devices DS1a and DS1b has a playback speed of 30 fps (Frames Per Second).

  Although the image data for one frame of the two display devices DS1a and DS1b are respectively generated in the frame buffers FBa and FBb to cause the display circuits 74A and 74B to function, the invention is not particularly limited. Absent.

  In FIG. 14A, image data for one frame of two display devices DS1a and DS1b (image data connected in stripes) are collectively generated in the frame buffer FBa, and the output of the display circuit 74A is output selector A configuration is shown in which the image data is divided into stripes at 79 and divided into image data of one frame of the display devices DS1a and DS1b.

  Here, the stripe connection means that RGB image data of each pixel of two display devices DS1a and DS1b are horizontally adjacent to generate composite pixels. Moreover, stripe division means an operation of outputting RGB image data of one pixel to the LVDS unit 80a and outputting RGB image data of the other pixel to the LVDS unit 80b for composite pixels adjacent in the horizontal direction of the display screen. .

  The pair of LVDS signals LVDS1 and LVDS2 output from the LVDS units 80a and 80b receiving the output (RGB parallel signal) of the output selection unit 79 are sent to the display devices DS1a and DS1b via the LVDS relay boards 27a and 27b. It is transmitted.

  In order to realize such an operation, it is necessary to secure, in the frame buffer FBa, image data obtained by stripe-connecting image data of one frame of the display devices DS1a and DS1b.

  Therefore, a method of connecting sprites of image data of 800 × 600 pixels for the display device DS1a and image data of 800 × 600 pixels for the display device DS1b will be described based on FIG.

  As shown in FIG. 15B, in this embodiment, a working area WK1 for temporarily storing image data (Ai) of 800 × 600 pixels for the display device DS1a, and 800 × 600 pixels of the display device DS1b A work area WK2 for temporarily storing image data (Bi) is secured.

  Then, the image data Ai for one frame generated based on the drawing command for the display device DS1a described in the display list DLi is temporarily stored in the work area WK1, while based on the drawing command for the display device DS1b. The generated image data Bi for one frame is temporarily stored in the work area WK1. The left side of FIG. 15 (b) shows this temporary storage state.

  Further, since these image data (Ai, Bi) need to be sprite-connected and stored in the frame buffer FBa, the frame buffer FBa is 1600 × 600 to store the sprite-connected image data (Ai + Bi). A storage capacity of × 2 pixels is secured.

  The frame buffer FBa is configured to have an α channel for specifying an α value in addition to 3 bytes for specifying RGB data for each of the 1600 × 600 pixels P (i, j). Here, the α value is transparency information set at each pixel position P (i, j), and a new image (source) to be overwritten on the frame buffer FBa and an original image (destination) of the frame buffer FBa Is a value that specifies the α blending process that defines the transparency of the image.

  Although not particularly limited, if the α value is made to be 1 byte, the information of each pixel position P (i, j) is specified by 4 bytes in total, and the frame buffer FBa has a total of 1600 × 600 × It has a data capacity of 4 bytes long.

  Based on the above, the image data (Ai, Bi) in the completed state temporarily stored in the work areas WK1, WK2 is stripe-connected by the stripe connection process JOIN described in the final position of the display list DLi. Ru. The drawing command sequence for realizing the stripe concatenation process JOIN is stored in, for example, the built-in VRAM 71 or the external DRAM 54 at the time of power supply reset, as a subroutine JOIN accessible to the drawing circuit 76 (DL analyzer).

  FIG. 15A is a flow chart for explaining this stripe concatenation process JOIN. In the stripe concatenation process JOIN, first, the α value = 0 is written to the α channel specifying odd column pixels, while the α value = 255 is written to the α channel specifying even column pixels (SS 51) .

  Next, the image data Ai (for 800 × 600 pixels) of the display device DS1a in the completed state stored in the work area WK1 is expanded in the horizontal direction to form the frame buffer FBa as image data for 1600 × 600 pixels. Write to (SS 52).

  In the drawing command for transferring the image data from the work area WK1 to the frame buffer FBa, the image area on the source side (work area WK1) and the image area on the destination side (frame buffer FBa large in the horizontal direction) It is enough to specify. That is, since the frame buffer FBa on the destination side is twice in the horizontal direction compared to the source side, the horizontal enlargement processing is automatically executed in the drawing circuit (Pixel Generator).

  In this double magnification process, the image data of the first row of the work area WK1 is copied to the first and second rows of the frame buffer FBa, and the image data of the second row of the work area WK1 is frame buffer It is configured to be copied to the third and fourth columns of the FBa. The same applies to the following, and the image data of the Nth row of the work area WK1 is copied to the 2 * N-1th row and the 2 * Nth row of the frame buffer FBa to become a destination image.

  Next, the image data Bi (for 800 × 600 pixels) of the display device DS1b in the completed state stored in the work area WK2 is expanded by 2 times in the horizontal direction to form image data for 1600 × 600 pixels. Alpha blending is performed with the image data of the buffer FBa (SS 53). Also in this case, the image data of the Nth row of the work area WK2 acts on the 2 * N-1th row and the 2 * Nth row of the frame buffer FBa by the enlargement processing, and between the destination image of that position. Alpha blending is performed.

  In the α blending process, for example, as shown in equation 1 shown in FIG. 15B, the calculation of Cr = Cd * (1−α / 255) + Cs * α / 255 is performed. In this formula, Cd is written in the frame buffer FBc in the process of step SS52, that is, RGB information of the original image (Destination) written in each pixel position P (i, j) of the frame buffer FBa. Image data of the work area WK1 (for 1600 × 600 pixels of the horizontally enlarged display device DS1a).

On the other hand, Cs is RGB information of the Source image (for 1600 × 600 pixels of the display device DS1 b) of the horizontally enlarged working area WK2, and Cr is RGB information of the frame buffer FBc after α blending processing. In the α blend processing equation, 255 is the upper limit value of the α value of 1-byte configuration (n = 8), and changes according to the data configuration (2 ⁿ −1).

  As described above, since the α value is 0 in the odd pixel column shown in FIG. 15B and 255 in the even pixel column by the process of step SS51, eventually, in the frame buffer FBa corresponding to the odd pixel column. From the relationship of Cr = Cd, the original image (Destination), that is, the image data for the sub display device DS1a, remains as it is.

  On the other hand, in the frame buffer FBa corresponding to the even pixel column, the original image (Destination) disappears from the relationship of Cr = Cs, and only the new image (Source) to be overwritten, that is, the image data for the sub display device DS1b Will be stored.

  As a result of these, the image data of the display device DS1a and the display device DS1b are stripe-connected and stored in the frame buffer FBa.

  In the α-Brent processing described above, the image of the sub-display DS1b expanded horizontally is the source image, but instead of this, the image of the sub-display DS1a expanded horizontally may be the source image Of course. Further, it is optional to leave the image of the sub display DS1a or the image of the sub display DS1b in the odd pixel column, and the circuit connection of the LVSD relay substrate and the display may be changed correspondingly. . Further, the process of step SS51 may be limited to only one time when the power is turned on.

  In any case, the image data thus sprite-connected is divided into sprites by the output selection unit 79, and the LDVS1 signal specifying the image data (Ai) for the display device DS1a, the image data for the display device DS1b ( The signal is transmitted to the LDVS relay boards 27a and 27b as an LDVS2 signal for specifying Bi).

  Then, the LDVS signal regenerated on the LDVS relay boards 27a and 27b is transmitted to the display devices DS1a and DS1b, so that each display screen from which the influence of noise is eliminated is displayed.

  In the configuration of FIG. 14A, the sprite division process is performed in the output selection unit 79. However, as shown in FIG. 14B, sprite division may be performed in the LVDS relay board 27. In the case of the configuration of FIG. 14B, the clock frequency of the LVDS signal output from the VDP circuit is, for example, 80 MHz, but since the LVDS signal is regenerated at the LVDS relay board 27, noise accompanying level drop etc. There is no trouble.

  As described above, FIG. 10 (c) illustrates the operation of the distributor 85 disposed on the LVDS relay board 27, and the frequency of the dot clock is dropped from 80 MHz to 40 MHz in the distributor 85. Ru.

  In the case of adopting the configurations of FIG. 14A and FIG. 14B, the image data of another display device is generated using the frame buffers FBb and FBc in a vacant state and the display circuits 74B and 74C. Can.

  FIG. 14C shows an embodiment in which six display devices DS1a, DS1b, DS2 to DS5 are arranged, and sprite-connected image data is generated in each of the frame buffers FBa, FBb, and FBc. . Then, the LVDS signal including the image data connected to the sprite is divided into sprites in the LVDS relay boards 27a to 27c and transmitted to the display devices DS1a, DS1b, DS2 to DS5.

  Since the output of the display circuit 74C is RGB parallel data, an LVDS conversion circuit is disposed on the liquid crystal IF substrate, and is transmitted to the LVDS relay substrate 27c as an LVDS signal.

  By the way, in the explanation so far, the gaming machine GM in which the glass door 6 and the front plate 7 are pivotally attached to the front frame 3 has been described, but common members permanently usable in the game hall for a certain period In order to make the gaming machine more individual while securing (general-purpose members GER), it is preferable to adopt the device configuration shown in FIG.

  In this game machine GM, the front frame 3 pivotally attached to the wooden outer frame 1 is configured to be disassembled into the first front frame 3A and the second front frame 3B, and the second front frame 3B includes the door frame 4A. And the design frame 4B are mounted.

  Then, the game board 5 is attached to the first front frame 3A, and in front of the game board 5, the second front frame 3B, the door frame 4A, and the design frame 4B are disposed. In this device configuration, the wooden outer frame 1, the first front frame 3A, and the second front frame 3B are common members GER arranged in the game hall, and the game board 5, the door frame 4A, and the design frame 4B is a change member CHG that can be changed for each model. However, the door frame 4A and the design frame 4B do not necessarily have to be exchanged each time in response to the exchange of the game board 5.

  Note that the frame side member GM1 of FIG. 4 corresponds to the common member GER (a wooden outer frame 1 + a first front frame 3A + a second front frame 3B) when the device configuration shown in FIG. The door frame 4A and the design frame 4B are combined, and the board side member GM2 becomes the game board 5.

By the way, the door frame 4A is roughly divided into a general-purpose frame 4A1 which can be used for general purpose and an individuality frame 4A2 which is roughly classified according to the game concept of each model. The individuality frame 4A2 may be, for example, a gong frame 4A2 _G used in a series of gaming machines with a motif of boxing movies, or a group of 0 girls' frames used in a series of gaming machines with a motif of an animation hero 4A2 _S etc. are prepared.

  The circuit board disposed in the door frame 4A stores a discrimination code for identifying the above-described types (4A1, 4A2, ...) of the door frames, and the type of the door frame 4A is set when the power is turned on. It is configured to be distinguishable. Then, in the case where the door frame 4A unreasonable is attached to the game board 5, that effect is notified.

On the other hand, a plurality of design frames 4B are prepared for each type of door frame 4A. For example, as design frame 4B corresponding to 少女 girl frame 4A2 _S , the color and design of the clothes of the main character are different. Multiple types are available.

  As described above, in the present embodiment, a plurality of door frames 4A to be attached to the second front frame 3B is prepared, and a plurality of design frames 4B are prepared for each door frame 4A. The periphery of the game board 5 can be optimally decorated according to the game nature intended by the player.

  In this embodiment, three photo interrupters PI0 to PI2 are arranged in the door frame 4A, while the light shielding plate MK is arranged in the design frame 4B. When assembling the design frame, the light shielding plate MK is Each photo interrupter PIi is configured to plunge into a gap (see FIG. 17A).

  As shown in FIG. 17A, each photo interrupter PIi is configured by facing a photodiode D for emitting inspection light and a phototransistor TR for receiving inspection light with an appropriate gap GP interposed therebetween. .

  In addition, the light shielding plate MK is a transparent plastic material formed in a substantially T-shaped cross-sectional view by the base MK1 fixed to the design frame 4B and the protruding portion MK2. Then, the light shielding performance is realized by sticking the mask sheet SH to the transparent protrusion MK2.

  As illustrated, the protrusion MK2 is divided into three corresponding to the photo interrupters PI0 to PI2, and the appropriate place is a light shielding portion by the mask sheet SH. Therefore, the output Di of each photo interrupter PIi is 0 (= L) in the light blocking state of the inspection light and 1 (= H) in the light transmitting state.

  Although not particularly limited, in the present embodiment, one or two places out of three places of the three divided parts MK2 are the light shielding parts, and the outputs D2 to D0 of the photointerrupters PI2 to PI0 are shown in FIG. As in b), up to five design units 6 (design A to design F) can be specified.

  Then, when the power is turned on, the data of the photo interrupters PI0 to PI2 is acquired, so that the type of the design frame 4B is determined, and the image effect corresponding to the type of the design frame 4B is executed. For example, the color and the design of the clothes of the main character appearing on the display device match the design of the design frame 4B.

  As mentioned above, in this specification, although various examples were explained in detail, the concrete contents of description do not limit the present invention at all.

23 sub control means GM game machine 54 effect control means 53 data storage means 56 image generation means 85 relay circuit 27 relay board

Claims (9)

A gaming machine provided with sub-control means for controlling an image effect corresponding to a lottery result of a lottery process executed due to a predetermined switch signal based on a control command received from another control means,
The sub control means
Production control means for controlling the image production by outputting a drawing instruction for specifying the display content of the display device for executing the image production;
Data storage means for storing compressed data which is a component of still images and / or moving images constituting an image effect;
An image generation unit capable of outputting an image signal generated by accessing the data storage unit in the form of a Low Voltage Differential Signaling (LVDS) signal based on the drawing instruction received from the effect control unit; And
A relay board on which an inductor exhibiting high impedance to a common mode signal is disposed is provided between the image generation means and the display device, and the relay board transmits the LVDS signal passing through the inductor to the display device. A game machine characterized by having been.   The gaming machine according to claim 1, wherein the inductor is disposed for each differential signal line.   The gaming machine according to claim 1, wherein a protective element which performs a shorting operation at the time of electrostatic discharge is further arranged on the relay substrate.   The gaming machine according to any one of claims 1 to 3, further comprising electronic circuit elements disposed on the relay substrate for receiving the LVDS signal output from the image generation unit and outputting the regenerated LVDS signal.   The gaming machine according to claim 4, wherein the inductors are respectively disposed on an input side and an output side of the electronic circuit element.   The gaming machine according to any one of claims 1 to 5, wherein the display device is configured to be movable.   The gaming machine according to any one of claims 1 to 6, wherein a plurality of the display devices are disposed, and the relay substrate is disposed corresponding to each display device.   The gaming machine according to claim 7, wherein the plurality of display devices include one or more pairs of display devices in which the number of vertical pixels and the number of horizontal pixels of the display screen are the same. The sub control means
In addition to the image effects described above, it is configured to have a CPU that uniformly controls all or part of lamp effects for driving the lamp, voice effects for driving the speaker, and movable effects for moving the movable object. The gaming machine according to any one of claims 1 to 8.