JP6727697B2 - Amusement machine - Google Patents

Description

The present invention relates to a gaming machine.

2. Description of the Related Art Conventionally, there has been proposed a gaming machine that displays an image on a display device and controls a plurality of control objects based on a control signal output in a serial system to perform a gorgeous effect (for example, Patent Document 1). ..

JP, 2008-073438, A (Drawing 7-Drawing 11)

By the way, in the gaming machine, accurate control is required for the controlled object in order to perform a gorgeous effect using the controlled object as designed at the time of development.

The present invention has been made in view of such circumstances, and an object of the present invention is to provide a gaming machine capable of realizing accurate control of a control target.

The following are effective solutions for achieving the above-mentioned object. The operation and the like will be described as necessary. Further, for ease of understanding, the configurations and the like corresponding to the embodiments of the invention are also shown as appropriate, but the present invention is not limited thereto.

(Solution 1)
A game machine that produces an effect based on the progress of a game, and an information storage unit capable of storing a plurality of types of information regarding the production, and an image object creation capable of creating an image object based on the information read from the information storage unit. Means, a parallel signal output unit for outputting a parallel signal including the image object created by the image object creating unit, and a parallel signal output by the parallel signal output unit for a positive phase signal and a negative phase signal. And a twisted wire configured by twisting a wire for transmitting the signal of the positive phase and a wire for transmitting the signal of the opposite phase, The positive phase signal and the reverse phase signal transmitted by the twisted wire are input via the common mode choke coil to the positive phase side ferrite beads and the reverse phase signal is input. It is electrically connected to the phase-side ferrite beads and is composed of the positive-phase signal input via the positive-phase side ferrite beads and the reverse-phase signal input via the negative-phase side ferrite beads. An image based on the image object created by the image object creating means based on the restored parallel signal output by the signal restoring means, and a signal restoring means for restoring the serial signal to a parallel signal and outputting the parallel signal. An image display means for displaying, and a gaming machine.

In this game machine, it is possible to perform the rendering based on the progress of the game, information storage means, the image object creation means, the parallel signal output section, stranded wire, the positive phase side inductance element, reverse phase side inductance element, a signal conversion Means, signal restoration means, extraction means, image display means. The information storage means is capable of storing a plurality of types of information regarding effects. Image object creation means is capable of creating images objects on the basis of the information read from the information storage means. The parallel signal output unit is capable of outputting a parallel signal including the image object created by the image object creating means. The signal conversion means can convert the parallel signal output by the parallel signal output unit into a serial signal composed of a positive phase signal and a negative phase signal, and output the serial signal. The stranded wire is configured by twisting a wire that transmits a positive-phase signal and a wire that transmits a negative-phase signal. The positive phase side inductance element receives the positive phase signal transmitted through the twisted wire. The opposite-phase side inductance element receives the opposite-phase signal transmitted via the twisted wire. The signal restoration means restores a serial signal composed of a positive phase signal input via the positive phase side inductance element and a negative phase signal input via the negative phase side inductance element into a parallel signal. It can be output. Extraction means is, able to output removed image object that is created by the image object creation means based on the restored parallel signal output by the signal restoration unit. Image display means is a shall be displaying an image. As the positive phase side inductance element and the negative phase side inductance element, for example, ferrite beads can be cited. This ferrite bead reflects the noise that the inductor (coil) component of the ferrite bead has penetrated into the twisted wire so that it does not pass through, and the resistance component of the ferrite bead converts the noise that has entered the twisted wire into heat and removes it It has the property of being able to. Due to such characteristics of the ferrite beads, it is possible to suppress the disturbance of the waveform due to the superposition of noise on the serial signal transmitted through the twisted wire, and arrange the waveform into a beautiful waveform.

In this gaming machine, it is possible to execute an effect by a control target.

As described above, the image object creating unit creates the image object based on the information read from the information storage unit so that the control information for the control target is included as an image, and the parallel signal including the created image object is the parallel signal. An output section outputs the parallel signal to a serial signal composed of a positive-phase signal and a negative-phase signal by a signal converting means, and the converted serial signal transmits a positive-phase signal and wiring. A positive-phase signal is input to the positive-phase-side inductance element and a negative-phase signal is input to the negative-phase-side inductance element through a stranded wire that is formed by twisting the wiring that transmits the negative-phase signal. To be done. A serial signal composed of a positive phase signal input via the positive phase side inductance element and a negative phase signal input via the negative phase side inductance element is input to the signal restoration means. There is. That is, in the transmission path from the signal converting means to the signal restoring means, the serial signal is transmitted via the twisted wire, the positive phase side inductance element and the negative phase side inductance element. The signal restoration means restores the input serial signal to a parallel signal again, and the control means extracts the control information from the image object based on the restored parallel signal, and drives the controlled object based on the extracted control information. The control can be performed by the drive control means.

The twisted wire is made by twisting wires that transmit positive-phase signals and wires that transmit negative-phase signals, so if noise enters the twisted wires, wires that transmit positive-phase signals Then, noise will intrude into the wiring that transmits the signal of the opposite phase. Then, the noise invading the positive phase signal and the noise invading the negative phase signal cancel each other, and the disturbance of the waveform is suppressed through the positive phase side inductance element and the negative phase side inductance element. By inputting the signal into the signal restoring means in a state where the waveform is adjusted to a beautiful waveform, it is possible to restore the parallel signal again with noise removed in the signal restoring means. Therefore, accurate control can be realized for the controlled object.

In this embodiment, for example, the pachinko gaming machine 1 of FIG. 1 corresponds to a gaming machine, and a plurality of LEDs (decorative LEDs) mounted on various decorative boards of the door frame 5 of FIG. 2 and the door frame 5 of FIG. The dial drive motor 414 provided in the operation unit 400 corresponds to the control target, the liquid crystal in the peripheral control board 4140 in FIG. 17 and the liquid crystal in the sound control unit 4160 and the sound control ROM 4160b correspond to the information storage means, and the periphery in FIG. The frame side image object that is the drawing data generated in the door frame side display area VRGN2 provided on the built-in VRAM of the sound source built-in VDP 4160a of the sound control unit 4160 of the control board 4140 corresponds to the image object, and the periphery of FIG. The sound source built-in VDP 4160a of the liquid crystal and sound control unit 4160 in the control board 4140 corresponds to the image object creating means, the channel CH2 of the sound source built-in VDP 4160a in FIG. 19 corresponds to the parallel signal output unit, and the twisted pair cable corresponds to the twisted wire. The positive phase side ferrite beads correspond to the positive phase side inductance element, the negative phase side ferrite beads correspond to the negative phase side inductance element, the transmitter IC 4160d of the peripheral control board 4140 in FIG. 19. The receiver IC 194f of the frame decoration drive amplifier board 194 of FIG. 19 corresponds to the signal restoration means, the frame side signal separation control circuit 194g of the frame decoration drive amplifier board 194 of FIG. 19 corresponds to the extraction means, and the frame decoration drive amplifier board of FIG. The frame side VDP control target decoration LED control circuit 194i (frame side VDP control target first decoration LED control circuit 194i1 to frame side VDP control target 143 decoration LED control circuit 194i143) and the output control circuit 194it1 It corresponds to drive control means.

(Solution 2)
The gaming machine according to the solving means 1, wherein the gaming machine is a rotating-body type gaming machine.

In the gaming machine of the present invention, since the gaming machine is a rotating type gaming machine, the action and effect of the solving means 1 can be obtained in the rotating type gaming machine. As a basic configuration of the spinning drum type gaming machine, after a variable display of a symbol information sequence consisting of a plurality of symbol information (for example, a plurality of reel sequences with a plurality of symbol information), the display result of the symbol information is stopped and displayed. Along with the variable display means, the variable display of the symbol information is started based on the operation of the starting operation means (for example, the start lever), and based on the operation of the stop operation means (for example, the stop button) or the lapse of a predetermined time. Stop the variable display of the symbol information. Then, a profit-giving state generating means for generating a profit-giving state (big hit game state) is provided on condition that the symbol information is in a predetermined specific display mode, and a medal is used as a game medium to generate a profit-giving state. It is configured such that a large number of medals are sometimes paid out.

(Solution 3)
The gaming machine according to Solution 1, wherein the gaming machine is a fusion gaming machine in which a pachinko gaming machine and a spinning drum type gaming machine are fused.

In the gaming machine of the present invention, since the gaming machine is a fusion gaming machine in which a pachinko gaming machine and a rotating drum type gaming machine are fused, in a fusion gaming machine in which a pachinko gaming machine and a spinning drum type gaming machine are fused, The action and effect of the solving means 1 can be obtained. As a basic configuration of a fusion gaming machine that fuses a pachinko gaming machine and a rotating drum type gaming machine, a symbol information string consisting of a plurality of symbol information (for example, a plurality of reel rows with a plurality of symbols) is variably displayed. After that, with the variable display means for stopping and displaying the display result of the symbol information, the variable display of the symbol information is started based on the operation of the starting operation means (for example, the starting lever), and the stop operation means (for example, stop). The variable display of the symbol information is stopped based on the operation of the button) or the lapse of a predetermined time. Then, with the profit giving state generating means for generating a profit giving state (big hit game state) on condition that the symbol information becomes a predetermined specific display mode, a game ball is used as a game medium, and the profit giving state is It is configured such that a large amount of game balls are paid out at the time of occurrence.

In the gaming machine of the present invention, accurate control can be realized for the controlled object.

It is a perspective view showing a state in which the main body frame is opened with respect to the outer frame of the pachinko gaming machine and the door frame is opened with respect to the main body frame. It is a front view of a pachinko gaming machine. It is a rear view of a pachinko gaming machine. It is a front perspective view of an outer frame. It is a front perspective view of a body frame. It is a rear perspective view of the substrate unit in the body frame. It is a perspective view of a door frame. It is a front view of a game board. It is the disassembled perspective view which disassembled the game board of FIG. 8, and was seen from the front. It is a front exploded perspective view showing a configuration example when the effect display unit is viewed from the front. It is a rear surface exploded perspective view showing a configuration example when the effect display unit is viewed from the rear surface. It is the cross section diagram which shows one example of the cross section constitution of the production display unit. It is a front view which expands and shows the function display unit in a game board in the state attached to the pachinko game machine. It is a block diagram of a main control board, a payout control board, and a peripheral control board. FIG. 15 is a block diagram showing a continuation of FIG. 14. It is a schematic diagram of various detection signals that are input/output to/from a lending device connection terminal board for gaming balls or the like that relays electrical connection between a payout control board, which constitutes a main board, a CR unit, and a frequency display board. FIG. 15 is a block diagram showing a continuation of FIG. 14. It is a block diagram which shows the outline of a peripheral control MPU. FIG. 3 is a block diagram of the vicinity of a VDP with a built-in sound source in the liquid crystal and sound control unit. FIG. 20 is a block diagram following FIG. 19. It is a block diagram showing a power supply system of a pachinko gaming machine. FIG. 3 is a block diagram (a) showing a power supply generation circuit, and a diagram (b) showing a relationship between power consumption and a power consumption suppression level accompanying the power consumption. FIG. 22 is a block diagram showing a continuation of FIG. 21. It is a circuit diagram showing a circuit of a main control board. It is a circuit diagram showing a power failure monitoring circuit. It is a circuit diagram showing a communication interface circuit between the main control board and the peripheral control board. It is a circuit diagram showing a circuit and the like of the payout control unit. It is a circuit diagram showing a payout control input circuit. It is a circuit diagram which shows the continuation of FIG. It is a circuit diagram showing a payout motor drive circuit. It is a circuit diagram which shows a CR unit input/output circuit. FIG. 6 is an input/output diagram showing various input/output signals to/from a main control board and various output signals to an external terminal board. It is a figure which shows the arrangement|sequence of the output terminal of an external terminal board. It is a block diagram of a liquid crystal output substrate. It is a diagram showing a correspondence relationship between various serial controllers and output destinations in the game board side signal separation control circuit. It is a block diagram of various light guide plate control circuits. It is a block diagram of an LED control circuit for a game board side VDP control target decoration. It is a block diagram of the LED control circuit for a game board side peripheral control MPU control object decoration. It is a block diagram of a frame decoration drive amplifier board. It is a figure which shows the correspondence of various serial controllers in a frame side signal separation control circuit, and an output destination. It is a figure which shows the correspondence of the frame side VDP control object decoration LED control circuit and the some LED (decoration LED) provided in the frame side VDP control object decoration board. It is a block diagram of a frame side VDP control object decoration LED control circuit. It is a block diagram of a frame side peripheral control MPU control object decoration LED control circuit. It is a table showing an example of various commands transmitted from the main control board to the payout control board. 8 is a table showing an example of various commands transmitted from the main control board to the peripheral control board. 46 is a table showing a continuation of various commands transmitted from the main control board of FIG. 45 to the peripheral control board. It is a table showing an example of various commands from the payout control board received by the main control board. It is a flow chart which shows an example of processing at the time of main control side power supply turn-on. FIG. 49 is a flowchart showing a continuation of the main control-side power-on process shown in FIG. 48. It is a flow chart which shows an example of main control side timer interruption processing. It is a flow chart which shows an example of processing at the time of power supply of a payout control part. 52 is a flowchart showing a continuation of the payout control unit power-on processing. FIG. 53 is a flowchart illustrating a continuation of the payout control unit power-on processing subsequent to FIG. 52. It is a flow chart which shows an example of a payout control part timer interruption processing. It is a flow chart which shows an example of rotation angle switch history creation processing. It is a flowchart which shows an example of a sprocket fixed position determination skip process. It is a flow chart which shows an example of ball glide judgment processing. It is a flow chart which shows an example of a prize ball stock number addition processing for prize balls. It is a flow chart which shows an example of a prize ball stock number addition processing for ball rental. It is a flow chart which shows an example of stock monitoring processing. It is a flow chart which shows an example of pay-out ball gaze operation judgment setting processing. It is a flowchart showing an example of a payout setting process. It is a flowchart which shows an example of a ball-bending operation setting process. 7 is a flowchart illustrating an example of retry operation monitoring processing. 7 is a flowchart illustrating an example of a mismatch counter reset determination process. It is a flow chart which shows an example of error cancellation operation judging processing. It is a timing chart which shows the signal processing (a) at the time of a payout operation by ball lending, and the input signal confirmation processing (a) from a CR unit. It is a flow chart which shows an example of peripheral control part power-on processing. 7 is a flowchart showing an example of peripheral control unit V blank interrupt processing. It is a flow chart which shows an example of peripheral control part 1ms timer interruption processing. 7 is a flowchart illustrating an example of peripheral control unit command reception interrupt processing. It is a flow chart which shows an example of peripheral control part power failure notice signal interruption processing. 7 is a flowchart illustrating an example of power saving mode transition determination processing at power recovery. It is a flow chart which shows an example of power consumption monitoring processing. FIG. 4A is a diagram showing a relationship between a value set as a power control master volume value and a power consumption suppression stage, and FIG. 8B is a diagram showing a relation between a brightness set as a power suppression luminance and a power consumption suppression stage. ). It is a flow chart which shows an example of LOCKN signal history creation processing. It is a flowchart which shows an example of a connection malfunction determination process. It is a flow chart which shows an example of connection restoration processing. 7 is a timing chart for explaining the timing of outputting a connection confirmation signal to the INIT terminal of the upper plate side liquid crystal transmitter IC. It is a figure which shows an example of the variable display effect displayed on the display area of the game board side effect display unit. It is a figure which shows an example of the effect|action displayed with switching of a light guide plate in the display area of the game board side effect display unit. It is a figure which shows an example of the production|generation of the continuation of FIG. It is a figure which shows an example of the effect of the continuation of FIG. It is a figure which shows an example of the production of the continuation of FIG. It is a schematic explanatory drawing of various terminals of a serial transmission transceiver IC. It is a schematic diagram of an example of use of a serial transmission transceiver IC. It is a schematic perspective view of a slot machine.

[1. Overall configuration of pachinko machine]
Hereinafter, a pachinko gaming machine as a gaming machine of the present invention will be described with reference to the drawings. First, the entire pachinko gaming machine according to the embodiment will be described with reference to FIGS. 1 to 3. FIG. 1 is a perspective view showing a state in which a main body frame is opened with respect to an outer frame of a pachinko gaming machine according to an embodiment and a door frame is opened with respect to the main body frame, and FIG. 2 is a front view of the pachinko gaming machine. Yes, FIG. 3 is a rear view of the pachinko gaming machine.

As shown in FIGS. 1 to 3, the pachinko gaming machine 1 is an outer frame 2 installed in an island facility (not shown) in a game hall, and a box whose front side is openly supported by the outer frame 2 so as to be openable and closable. A frame-shaped main body frame 3, a game board 4 having a game area 1100 mounted and fixed to the main body frame 3 from the front side, into which a game ball as a game medium is driven, and the front surfaces of the main body frame 3 and the game board 4 are on the player side. It is provided with a door frame 5 which is rotatably supported by the main body frame 3 so as to be closed. On the door frame 5 of this pachinko gaming machine 1, a game window 101 formed so that the game area 1100 of the game board 4 can be viewed from the player side, and a game ball arranged below the game window 101 to store game balls. A dish-shaped upper plate 301 and a lower plate 302 (see FIG. 7), and a handle device 500 operated by the player to drive the game balls stored in the upper plate 301 into the game area 1100 of the game board 4. , Are provided.

Further, in the pachinko gaming machine 1, the outer frame 2, the main body frame 3, and the door frame 5 are each formed in a vertically long rectangular shape extending in the vertical direction in a front view, and the horizontal widths of the left and right sides thereof are substantially the same. The main body frame 3 and the door frame 5 are slightly shorter than the outer frame 2 in the vertical width. A decorative cover 23 is attached to the front surface of the outer frame 2 at a position lower than the main body frame 3 and the door frame 5, and the front surface of the outer frame 2 is completely closed by the door frame 5 and the decorative cover 23. It has become so. Further, the outer frame 2, the main body frame 3, and the door frame 5 are arranged so that their upper ends are substantially aligned with each other, and the main body frame 3 and the door frame 5 are rotatably supported at a position on the left front side of the outer frame 2. The main frame 3 and the door frame 5 are supported by the outer frame 2 and the right ends of the main frame 3 and the door frame 5 move to the front side to be in an open state.

Further, in the pachinko gaming machine 1, in a front view, a game area 1100 into which a game ball is driven is exposed through a substantially circular game window 101, and the game area 1100 projects forward below the game window 101. As described above, the two upper plates 301 and the lower plate 302 are arranged one above the other. A handle device 500 for a player to operate is arranged in the lower right corner of the front surface of the door frame 5, and the player can operate the handle device 500 with the game balls stored in the upper plate 301. When the rotation operation is performed, the game ball in the upper plate 301 is driven into the game area 1100 of the game board 4 with the hitting ball strength according to the rotation angle, and the player can play the game.

Although the game window 101 of the door frame 5 is closed by the transparent glass unit 590 and the player can see the inside of the game area 1100, the player inserts a hand or the like into the game area 1100 to play the game. It is not possible to touch the game balls, obstacle nails, various winning openings, accessories, etc. in the area 1100.

[2. Overall structure of outer frame]
Next, the outer frame 2 installed in the island facility of the game hall will be described with reference to FIG. FIG. 4 is a front perspective view of the outer frame. As shown in FIG. 4, the outer frame 2 includes upper and lower upper frame plates 10 and lower frame plates 11 extending in the horizontal direction, left and right side frame plates 12 and 13 extending in the vertical (vertical) direction, and respective frame plates. Four connecting members 14 for connecting the end portions of 10, 11, 12, 13 are provided, and by connecting the frame plates 10, 11, 12, 13 with the connecting member 14, a vertically long rectangular shape ( It is assembled in a square shape. The upper frame plate 10 and the lower frame plate 11 in the outer frame 2 are formed of a solid material (for example, wood, plywood, etc.) having a predetermined thickness. In addition, upper support fittings 20 described later are attached to the upper surface and the front surface of the left end portion of the upper frame plate 10.

On the other hand, the side frame plates 12 and 13 are light-weight metal mold members (for example, aluminum alloy) having a constant cross-sectional shape. In addition, a plurality of vertically extending grooves are formed on the outer and inner side surfaces of the side frame plates 12 and 13, and work is performed when the pachinko gaming machine 1 is installed in a pachinko island facility in a game hall. The pachinko gaming machine 1 can be easily held by a person's fingers and the design of the appearance can be improved.

The outer frame 2 is fixed to the upper surface of the left end of the upper frame plate 10 and the lower support fixed to a predetermined position inside the lower part of the left side frame plate 12 so as to face the upper support metal 20. A support metal fitting 21, a reinforcement metal fitting 22 arranged to support the lower surface of the lower support metal fitting 21 and fixed so as to connect the left and right side frame plates 12 and 13, and a decorative cover fixed to the front surface of the reinforcement metal fitting 22. 23 is provided. The upper support bracket 20 and the lower support bracket 21 are for pivotally supporting the main body frame 3 and the door frame 5 in an openable and closable manner. A shaft support pin 633 (see FIG. 5) of an upper shaft support member 630 of the main body frame 3 described later is detachably engaged with the support hook hole 20c of the upper support member 20. A main body frame shaft support formed on a main body frame shaft support metal fitting 644 of the main body frame 3 to be described later is inserted into the support protrusion 21d of the lower support metal fitting 21. After the body frame 3 is inserted into the support hole of the body frame shaft support metal fitting 644, the body support frame 3 can be easily locked by locking the shaft support pin 633 of the upper shaft support metal fitting 630 of the body frame 3 into the support hook hole 20c. It is designed so that it can be freely opened and closed.

Further, the outer frame 2 has two closing plates 24, 25 (see FIG. 1) mounted and fixed inside the right side frame plate 13 so as to be vertically separated from each other by a predetermined distance. These closing plates 24 and 25 are formed in a substantially L shape in a plan view. The closing plates 24 and 25 are hook portions 1054 and 1065 (see FIG. 1) of the locking device 1000 (locking device) that are attached along the open side of the main body frame 3 when closing the main body frame 3 with respect to the outer frame 2. Although the details will be described later, by inserting a key into the cylinder lock 1010 of the locking device 1000 and rotating it to one side, the hook portions 1054 and 1065 and the closing plates 24 and 25 are connected. The engagement is released, and the closed state of the main body frame 3 with respect to the outer frame 2 can be released.

[3. Overall structure of main frame]
Next, the main body frame 3 provided on the front side of the outer frame 2 so as to be openable and closable will be described with reference to FIGS. 5 and 6. 5 is a front perspective view of the main body frame, and FIG. 6 is a rear perspective view of the board unit in the main body frame. As shown in FIG. 5, the main body frame 3 forms a skeleton of the main body frame 3 and also has a main body frame base 600 having a rectangular game board holding port 601 for penetrating in the front-rear direction and holding the game board 4. An upper shaft support bracket 630 and a lower shaft support bracket 640 which are attached to the upper end and the lower end of the left end of the main body frame base 600 when viewed from the front and are pivotally supported by the outer frame 2 and pivotally support the door frame 5, respectively. A hitting ball launching device 650 that is attached to the lower front surface of the main body frame base 600 for driving a game ball into the game area 1100 of the game board 4, and a top plate 301 of the plate unit 300 that is attached to the rear side of the main body frame base 600. A prize sphere unit 700 for paying out the sphere, and a game sphere mounted on the front surface of the main body frame base 600 and opening the door frame 5 with respect to the main body frame 3 from the prize sphere unit 700 to the dish unit 300 of the door frame 5. And a ball outlet opening/closing unit 790 for shutting off the flow.

Further, the main body frame 3 is attached to the lower rear surface of the main body frame base 600, various control boards for controlling the door frame 5 except the game board 4 and electric parts provided in the main body frame 3, a power supply board 851, and the like. The board unit 800 that is a unitized body of the above, a back cover 900 that covers the rear opening of the game board holding port 601 in the main body frame base 600, and a side crime prevention plate 950 that covers the left end of the main body frame base 600 when viewed from the front. And a lock device 1000 that is attached to the right end of the main body frame base when viewed from the front and that locks the main body frame 3 with respect to the outer frame 2 and locks the door frame 5 with respect to the main body frame 3.

[3-1. Body frame base]
Next, the main body frame base 600 will be described. The main body frame base 600 is integrally molded of synthetic resin, and has an outer shape in a front view that is a vertically long rectangular shape along the outer shape of the door frame 5, and is formed to have a predetermined depth in the front-rear direction. Has been done. The main body frame base 600 has a game board holding port 601 capable of fitting and holding the outer periphery of the game board 4 by penetrating a rectangular shape in the front-rear direction within a range of about 3/4 of the whole from the upper part to the lower part, and a main body frame. A U-shaped front end frame portion 602 that forms the outer periphery of the front end of the base 600 excluding the left side in front view, and a recessed rearward from the front surface of the front end frame portion 602, and from the lower end of the door frame base body 110 in the door frame 5 to the rear side. The protruding door frame protrusion 110c (see FIG. 1), the upper bending protrusion 167 (see FIG. 1) protruding rearward of the upper reinforcing sheet metal 151 in the reinforcing unit 150 of the door frame 5, and the open side reinforcing sheet metal 153. And an engaging groove 603 into which the open side outward bending protrusion 164 (see FIG. 1) protruding rearward is inserted and engaged.

Further, the main body frame base 600 extends from the lower side of the game board holding port 601 to the lower end of the main body frame base 600, and is recessed rearward by a predetermined amount from the front end of the front end frame portion 602 and a lower rear wall portion which spreads laterally in a plate shape. 604, and a peripheral wall portion 605 that projects rearward inside the front end frame portion 602 and forms an inner peripheral wall of the game board holding port 601. By the peripheral wall portion 605, the free ends (upper and lower left end portions in a front view) of the U-shaped front end frame portion 602 are connected to each other so that the outer shape of the main body frame base 600 becomes a frame shape. It has become.

Further, the main body frame base 600 forms the lower side of the game board holding port 601 at the upper end of the lower rear wall portion 604, and the game board placing portion 606 on which the game board 4 is placed, and the game board placing portion 606. Positioning projections 607 protruding upward from the substantially center in the left-right direction and engaging with out-ball discharge grooves of the game panel 1150 in the game board 4, and the game board stopper of the game board 4 formed at a predetermined position on the inner wall on the right side in the front view of the peripheral wall portion 605. A game board locking portion to which the tool 1120 is fixed, and a plurality of upper end regulating ribs 609 that are downwardly hung from the upper inner wall of the peripheral wall portion 605 and that have a lower end abutting the upper end of the game board 4 and are arranged in the left-right direction. And are equipped with. The positioning protrusion 607 of the main body frame base 600 fits into the out-ball discharge groove of the game board 4 so that the lower end of the game board 4 can be restricted from moving leftward and rightward. There is. Further, the game board locking portion can restrict movement of the right side of the game board 4 in the front view in the front-rear direction by locking the game board stopper 1120 of the game board 4. .. The front left side of the game board 4 will be described later in detail, but its movement in the front-rear direction is restricted by the positioning member 956 of the side crime prevention plate 950.

Further, in the main body frame base 600, the lower rear wall portion 604 is formed at a position which is recessed one step rearward from the front surface of the front end frame portion 602, and the hitting ball launching device is provided on the right front surface of the lower rear wall portion 604 in front view. The hitting ball launching device 650 is mounted from the front side so that the launching solenoid 654 of 650 is housed in the solenoid housing recess. In a state in which the ball striking device 650 is attached to the front surface of the lower rear wall portion 604, a far space 626 that spreads leftward and downward is formed on the left side in front view of the upper end of the launch rail 660 of the ball striking device 650. It is like this. In the present embodiment, when the door frame 5 is closed with respect to the main body frame 3, the foul ball inlet 542e (see FIG. 1) of the foul cover unit 540 is located below the foul space 626. The game ball descending the foul space 626 is received by the foul ball inlet 542e of the foul cover unit 540 and is discharged to the lower plate 302 (see FIG. 7) of the plate unit 300.

In addition, the main body frame base 600 has an opening penetrating in a rectangular shape in the front-rear direction on the left side of the left-right center of the lower rear wall portion 604 in front view, and a plurality of openings formed on the upper side of the opening and both left and right sides in front view. And a through hole 615 penetrating therethrough. The opening of the main body frame base 600 is closed from the front side by the relay terminal board cover 692, and the board unit attached to the rear surface of the lower rear wall portion 604 through the opening 692a of the relay terminal board cover 692. The main door relay terminal plate 880 of 800 and the peripheral door relay terminal plate 882 are arranged to face the front side.

Further, the main body frame base 600 detects the opening of the door frame 5 with respect to the main body frame 3 on the lower front surface of the substantially circular cylinder lock through hole 611 penetrating in the front-rear direction at the upper right end of the lower rear wall portion 604 in a front view. A door frame opening switch 618 for operating the door frame 5 is attached, and when the door frame 5 is opened (opened) with respect to the main body frame 3, the pressing is released and the opening of the door frame 5 can be detected. It is like this. Further, in the main body frame base 600, a main body frame opening switch 619 for detecting opening of the main body frame 3 with respect to the outer frame 2 is attached to a rear surface below a position where the door frame opening switch 618 is attached, When the main body frame 3 is opened (opened) with respect to the outer frame 2, the pressing is released and the opening of the main body frame 3 can be detected.

[3-2. Upper shaft support bracket and lower shaft support bracket]
Next, the upper shaft support bracket 630 and the lower shaft support bracket 640 will be described. The upper shaft support metal fitting 630 and the lower shaft support metal fitting 640 are attached to the metal fitting mounting portions on the upper and lower left ends of the body frame base 600 when viewed from the front, respectively, by using predetermined screws to attach the door frame 5 to the body frame 3. The main frame 3 can be opened and closed, and the main body frame 3 can be opened and closed.

The upper shaft support metal fitting 630 is attached to an upper metal fitting mounting portion of the main body frame base 600, and has a plate-shaped mounting portion 631 that spreads in the vertical and horizontal directions, and a plate-shaped front extension that extends forward from the upper end of the mounting portion 631. The portion 632, the shaft support pin 633 provided so as to project upward from the vicinity of the front end of the front extension part 632, and the shaft pin 155 of the door frame 5 arranged on the left side in front view of the shaft support pin 633 (see FIG. 7). (Refer to FIG. 4) and the door frame shaft supporting hole 634 penetrating in the vertical direction and the front extending portion 632 are hung downward from the left end of the front view portion 632 to restrict the pivoting end of the door frame 5 to the open side. And a stopper. In the upper shaft support metal fitting 630, the mounting portion 631, the front extending portion 632, and the stopper are integrally formed by bending a single metal plate.

The lower shaft support metal fitting 640 is arranged below the door frame shaft support metal fitting 642 for pivotally supporting the door frame 5 and for supporting the main body frame 3 with respect to the outer frame 2. And a main body frame shaft support metal fitting 644. The door frame shaft support metal fitting 642 in the lower shaft support metal fitting 640 is attached to the metal fitting mount portion on the lower side of the main body frame base 600 and extends in the vertical and horizontal directions, and a plate-shaped mount portion that extends forward from the lower end of the mount portion. A plate-shaped front extension 642b, a door frame shaft support hole 642c through which a shaft pin 157 (see FIG. 7) of the door frame 5 is inserted in the vicinity of the front end of the front extension 642b in the vertical direction, and A stopper 642d is provided upright from the left end of the extending portion 642b when viewed from the front, and the stopper 642d that restricts the pivoting end of the door frame 5 toward the open side. In this door frame shaft support fitting 642, the mounting portion, the front extending portion 642b, and the stopper 642d are integrally formed by bending a single metal plate.

Further, the main body frame support metal fitting 644 of the lower support metal fitting 640 is attached to a lower metal fitting mounting portion of the main body frame base 600, and has a plate-shaped mounting portion that spreads in the vertical and horizontal directions, and extends from the lower end of the mounting portion to the front. The front extending portion 644b that extends is provided, and a main body frame shaft support hole that penetrates in the vertical direction near the front end of the front extending portion 644b. In the body frame shaft support 644, the mounting portion and the front extending portion 644b are integrally formed by bending a single metal plate.

The lower shaft support metal fitting 640 is in a state where the mounting portion of the door frame shaft support metal fitting 642 and the mounting portion of the main body frame shaft support metal fitting 644 overlap (contact) in the front-rear direction, and The front extension part 642b and the front extension part 644b of the main body frame support metal fitting 644 are attached to the lower metal fitting attachment part of the main body frame base 600 in a state of being separated from each other by a predetermined distance in the vertical direction.

When the upper shaft support bracket 630 and the lower shaft support bracket 640 are attached to the main body frame base 600, the shaft support pin 633 of the upper shaft support bracket 630 and the main frame support hole of the lower shaft support bracket 640 are coaxial with each other. The main body frame shaft support hole of the main body frame shaft support metal fitting 644 in the lower shaft support metal fitting 640 is fitted to the support protrusion 21d (see FIG. 4) of the lower support metal fitting 21 in the outer frame 2. The front extension part 644b of the main body frame support metal fitting 644 is placed on the support projecting piece 21c of the lower support metal fitting 21 (see FIG. 4) so as to be inserted, and then the shaft of the upper shaft support metal fitting 630 is inserted. By inserting the support pin 633 into the support hook hole 20c (see FIG. 4) of the upper support fitting 20 in the outer frame 2, the main body frame 3 can be pivotally supported with respect to the outer frame 2 so as to be openable and closable. It is like this.

The upper shaft support bracket 630 and the lower shaft support bracket 640 are attached to the body frame base 600, and the door frame shaft support hole 634 of the upper shaft support bracket 630 and the door frame shaft support hole of the lower shaft support bracket 640 are attached. 642c is located coaxially with the door frame so that the shaft pin 157 of the door frame 5 is inserted into the door frame shaft support hole 642c of the door frame shaft support metal fitting 642 in the lower shaft support metal fitting 640. 5 of the lower shaft support 158 (see FIG. 7) is placed on the front extending portion 642b of the door frame support metal fitting 642, and then the shaft pin 155 of the door frame 5 is connected to the door frame of the upper shaft support metal fitting 630. The door frame 5 can be pivotally supported on the main body frame 3 so that the door frame 5 can be opened and closed by being inserted into the shaft support hole 634. In the present embodiment, the shaft pin 155 on the upper side of the door frame 5 is slidable in the vertical direction, and when the shaft pin 155 is inserted into the door frame shaft support hole 634 of the upper shaft support metal fitting 630, the shaft pin 155 is slidable. By sliding the shaft pin 155 downward so that the upper shaft support portion 156 of the door frame 5 and the front extension portion 632 of the upper shaft support metal fitting 630 vertically overlap with each other, and then the shaft pin 155 is slid upward. It can be inserted into the door frame shaft support hole 634.

[3-3. Hit ball launcher]
Next, the hit ball launching device 650 will be described. The hitting ball launching device 650 is a metal plate launching base 652 that is attached to a predetermined position on the front surface of the lower rear wall portion 604 of the main body frame base 600, and is attached to the lower rear face of the launching base 652 so that the rotary drive shaft 654a projects forward. A firing solenoid 654, a hammer 656 fixed to the rotary drive shaft 654a of the firing solenoid 654 so as to be rotatable integrally, a hammer tip 658 fixed to the tip of the hammer 656, and a predetermined trajectory on the movement trajectory of the hammer tip 658. A hammer 658 at the tip of the batting hammer 656 passes between the launch rail 660 that extends diagonally to the upper left in a front view and is attached to the front surface of the launch base 652, and the launch rail 660 above the base end of the launch rail 660. A ball stop piece 662 which holds a game ball at the base end of the launch rail 660 by forming a gap through which the game ball cannot be passed at the same time, and a game held at the base end of the launch rail 660 by the ball stop piece 662. And a stopper 664 for restricting rotation of the hitting mallet 656 (hammer tip 658) from the hitting position at which the ball can be hit to the firing rail 660 side.

Although not shown in detail, the firing solenoid 654 in the hitting ball firing device 650 is configured such that the rotary drive shaft 654a reciprocally rotates at a strength (speed) corresponding to the rotational operation angle of the handle device 500. .. Further, the batting mallet 656 of the batting ball launching device 650 has a fixed portion 656a fixed to the rotary drive shaft 654a of the firing solenoid 654, and a tip extending in a gentle arc from the fixed portion 656a so that the tip is at the axis of the rotary drive shaft 654a. On the other hand, a rod portion 656b in which the mallet tip 658 is fixed to the tip end in the direction of the normal line, and a stopper portion 656c that extends to the opposite side with respect to the rod portion 656b with the fixing portion 656a interposed therebetween and can come into contact with the stopper 664, Equipped with. Since the stopper portion 656c of the hitting mallet 656 contacts the stopper 664, the hammer tip 658 at the tip is rotated toward the launch rail 660 side from the hitting position (the turning end in the counterclockwise direction in front view). It is becoming regulated.

In the state where the hitting ball launching device 650 is attached to the lower rear wall portion 604 of the main body frame base 600, the upper end of the launch rail 660 is substantially the center in the left-right direction, that is, the upper end of the lower rear wall portion 604, that is, the game board mounting portion. It is designed to be positioned below 606 (the lower side of the game board holding port 601) and has a predetermined width in the left-right direction between the lower end of the outer rail 1111 of the game board 4 held by the game board holding port 601. A foul space 626 that spreads downward is formed. Then, the hit ball launching device 650 launches the game ball by jumping over the foul space 626 on the left side in front view with respect to the launch rail 660, so that the game ball can be driven into the game area 1100 of the game board 4. It has become. In the state where the door frame 5 is closed with respect to the main body frame 3, the foul ball entrance 542e of the foul cover unit 540 attached to the door frame 5 is located at the bottom of the foul space 626, and the game is performed. The game ball that has become a foul ball without being driven into the area 1100 falls in the foul space 626, is received by the foul ball inlet 542e, and is discharged to the lower plate 302.

[3-4. Prize Ball Unit]
Next, the prize ball unit 700 will be described. In the pachinko island facility in the hall where the pachinko gaming machine 1 is installed, the gaming balls supplied from the pachinko island facility side to the pachinko gaming machine 1 are stored, and then the upper plate 301 of the pachinko gaming machine 1 is issued based on a predetermined payout instruction. Pay out to. This prize ball unit 700 is a prize ball base 710 attached to the rear surface of the main frame base 600, and a prize ball tank attached to the upper portion of the rear surface of the prize ball base 710 for receiving and storing game balls supplied from the Pachinko Island facility side. 720, a tank rail unit 730 which is arranged below the prize ball tank 720 and which aligns the game balls stored in the prize ball tank 720 and sends the game balls to the downstream side, and the game balls arranged by the tank rail unit 730 in a predetermined manner. The prize sphere device 740 to be paid out based on the payout instruction and the game spheres paid out by the prize sphere device 740 can be guided to the upper plate 301 of the plate unit, and the upper plate 301 is paid out when the game balls are full. It is mainly provided with a full tank branching unit 770 capable of branching and guiding the game ball to the lower plate 302 side.

The prize ball unit 700 also includes an external terminal plate 784 attached to the rear surface of the prize ball base 710, and an external terminal plate cover 786 that covers the rear side of the external terminal plate 784.

[3-4-1. Prize ball tank]
In the prize ball tank 720, the outer periphery of the bottom wall portion 721 is surrounded by the outer peripheral wall portion 722, and a predetermined amount of game balls can be stored on the bottom wall portion 721. In addition, the prize ball tank 720, the upper surface of the bottom wall portion 721 is inclined to be lowered toward the discharge port 723, so that the game balls on the bottom wall portion 721 roll toward the discharge port 723. It has become.

Further, the prize ball tank 720 includes two ball leveling members 727 that are rotatably supported by the shaft portion 725. This ball leveling member 727 is configured such that one end side is pivotally supported by the shaft portion 725 and holds a weight inside, and the other end side hangs down by its own weight. The ball leveling member 727 is adapted to hang down in a tank rail unit 730, which will be described later, and is capable of leveling and aligning game balls circulating in the tank rail unit 730.

[3-4-2. Tank rail unit]
The tank rail unit 730 is provided below the prize ball tank 720 and includes a tank rail 731 that extends in the left-right direction. The tank rail 731 is a gutter having a predetermined depth with an open upper side, and has a width (depth) in which game balls can be arranged in two rows in the front-rear direction, and a left end (axial support side) end in front view. The bottom is slanted so that

In addition, the tank rail unit 730 is connected to the alignment gear 732 that is rotatably supported above the discharge port of the tank rail 731, the gear cover 733 that covers the upper portion of the alignment gear 732, and the right end of the gear cover 733 when viewed from the front. A ball retainer plate 734 that closes the upper part of the rail 731, and a ball stopper 735 that can be moved back and forth in the tank rail 731 and can stop the game balls in the tank rail 731 from rolling toward the discharge port. , Are provided. Two alignment gears 732 are provided side by side in the front-rear direction so as to correspond to the two flow paths of the game sphere divided into two rows by the partition wall of the tank rail 731.

[3-4-3. Prize Ball Device]
The prize ball device 740 is for paying out the game balls discharged and supplied from the discharge port of the tank rail unit 730 to the upper plate 301 of the plate unit 300 based on a predetermined payout instruction. The prize ball device 740 communicates with the supply passage that opens at the upper end and is slightly wider than the outer shape of the game ball and extends to a position slightly lower than the center in the up-down direction. A distribution space having a space, a prize ball passage that communicates with the lower end (open side) of the distribution space on the rear side (open side), opens in the left side when viewed from the rear, and the right side of the distribution space on the rear side. (Spindle support side), a ball passage that communicates with the lower end and extends downward and opens at the lower end. The supply passage, the distribution space, the prize ball passage, and the ball removal passage are formed to be open rearward.

The prize ball device 740 includes a first gear fixed to the rotation shaft of the payout motor 744 so as to be integrally rotatable and arranged on the rear side of the motor support plate, a second gear meshing with the first gear, and a second gear meshing with the second gear. The third rotating gear, the payout rotating body as a sprocket that rotates integrally with the third gear and is disposed in the distribution space, and the payout rotating body are integrally rotatably fixed on the opposite side with the third gear interposed therebetween. A rotation detection board having a plurality of (three in the present embodiment) detection slits formed at equal intervals in the direction, and a ball break switch 750 for detecting the presence or absence of a game ball in the supply passage, A counting switch 751 for detecting a game ball flowing down in the prize ball passage, a rotation angle switch 752 for detecting a detection slit formed on a rotation detection plate that rotates integrally with the payout rotating body, and a rotation angle switch 752. And a payout motor 744, a ball break switch 750, a counting switch 751, and a prize ball case substrate 754 that relays the connection between the rotation angle switch 752 and a payout control substrate to be described later. ing.

The payout rotating body as a sprocket is provided with three recesses each having a size capable of accommodating one game ball at equal intervals in the circumferential direction, and the payout rotating body rotates to supply the game supplied from the supply passage. Each ball is housed in the recess one by one, and can be paid out to the prize ball passage or the ball removal passage side. Further, the three detection slits formed on the rotation detecting plate that rotates integrally with the payout rotating body are equally formed (every 120 degrees) on the outer circumference of the rotation detecting plate and correspond to the recesses of the payout rotating body. The rotation angle switch 752 detects the detection slits provided at the respective positions, so that the rotation position of the payout rotating body can be detected. In the present embodiment, the rotation between the detection slits (120 degrees) of the rotation detection board (dispensing rotor) is designed to correspond to the rotation of the dispensing motor 744 in 18 steps.

In the prize ball device 740, when the payout motor 744 rotates the payout rotating body in the counterclockwise direction in rear view, the game balls in the supply passage are paid out to the prize ball passage. The game balls paid out to the prize ball passage by the rotation of the body are counted by the counting switch 751 one by one and then passed to the prize ball passage. On the other hand, when the ball-removing operation member is operated by a clerk or the like in the hall, the game balls in the supply passage are discharged to the ball-removing passage. The pachinko gaming machine 1 can be discharged from the lower end of the passage to the outside of the rear side of the pachinko gaming machine 1 via a full tank branching unit 770 described later.

[3-4-4. Full tank branch unit]
The full-tank branching unit 770 is formed in a box shape such that the whole is lowered as it goes from the rear end to the front end. A prize ball receiving port that receives the game ball that has flowed down the ball passage, a branch space that is arranged below the prize ball receiving port and spreads in the left and right direction, and a game from directly below the prize ball receiving port in the branch space to the front side A normal passage that guides the ball, a normal ball outlet 774 that opens the game ball that has flowed through the normal passage to the front and opens at the front end right end of the front end, and separates to the right of the rear view from directly below the prize ball receiving opening in the branch space. A full tank passage that guides the game ball toward the front side from the open position, and a full tank outlet 776 that opens the game ball that has flowed through the full passage to the front and opens to the left of the normal ball outlet 774 when viewed from the front. ing.

In addition, the full tank branching unit 770 has a ball withdrawal opening that opens upward at the left end of the upper rear end when viewed from the front and receives a game ball that has flowed down the ball withdrawal passage of the prize ball device 740, and a ball withdrawal port. At the position behind the ball passage passage that guides the game ball received in the mouth to the front side, and the game ball that has flowed through the ball passage passage to the front, and behind the normal ball outlet 774 and the full tank outlet 776 at the left end in front view. And a ball outlet that is open.

In the full tank branching unit 770, when the door frame 5 is closed with respect to the main body frame 3, the normal ball outlet 774 and the full ball outlet 776 are respectively the first ball inlet 542a of the foul cover unit 540 in the door frame 5. And the second sphere inlet 542c (see FIG. 1) is adapted to communicate with each other, and the game sphere discharged from the normal sphere outlet 774 passes through the first sphere inlet 542a of the foul cover unit 540 to the plate. The game balls supplied to the upper plate 301 of the unit 300 and discharged from the full tank ball outlet 776 are supplied to the lower plate 302 of the plate unit 300 through the second ball inlet 542c of the foul cover unit 540. ing. Further, the ball outlet is formed so as to communicate with the upper right end of the body frame base ball passage of the body frame base 600 when viewed from the rear side, and the game balls emitted from the ball outlet are the body frames of the body frame base 600. It is designed to be delivered to the base ball passage.

When the upper bowl 301 of the dish unit 300 is filled with game balls and further game balls are paid out from the prize ball unit 700 (prize ball device 740), the first ball outlet of the foul cover unit 540 is moved upward. The game sphere that cannot be discharged to the plate 301 side stays in the first ball passage of the foul cover unit 540, and eventually the normal passage upstream 774 in the full tank branching unit 770 is also filled up in the normal passage. In this state, the game ball that has entered the branch space from the prize ball receiving hole cannot enter the normal passage, and starts moving laterally in the branch space, and the game ball that has moved laterally is full. It enters into the tongue passage and is supplied to the lower tray 302 of the dish unit 300 from the full tank outlet through the second ball inlet 542c of the foul cover unit 540, the second ball passage, and the second ball outlet. Is becoming

[3-5. Board unit]
Next, the board unit 800 will be described. As shown in FIG. 6, the board unit 800 includes a board unit base 810 attached to the rear surface of the lower rear wall portion of the main body frame base 600, a speaker box 820 attached to the left rear surface of the board unit base 810 in front view, and a board. A power supply board box holder 840 mounted on the rear surface of the unit base 810, and a power supply board box mounted on the rear surface of the power supply board box holder 840 and having a size such that the rear end is substantially flush with the rear end of the speaker box 820. 850, a payout control board box 860 attached to the rear surface of the power supply board box 850 and the speaker box 820, and a terminal board box 870 attached to the rear surface of the speaker box 820 so as to cover the left end portion of the payout control board box 860 in front view. And a main door relay terminal plate 880 and a peripheral door relay terminal plate 882 attached to the front surface of the board unit base 810.

The power supply board box holder 840 has a discharge ball receiving portion 841 which is opened upward and receives a game ball discharged downward from the out ball discharging portion of the game board 4 on the left front side from the center in the left and right in a front view, A discharge passage 842 that guides and discharges the game ball received by the discharge ball receiving portion 841 and a discharge passage 842 and the discharge passage 842 and the discharge ball receiving portion 841 are opened forward and upward on the front surface of the side (right side in front view). The power supply board box holder 840 is provided with a box accommodating portion that is formed so that the entire rear surface of the power supply board box holder 840 is recessed to the front side and that can accommodate the front end of the power supply board box 850.

Further, the power supply board box holder 840 is configured such that the opened front end side of the discharge passage 842 is closed by the rear surface of the board unit base 810, and the opening of the board unit base 810 faces the discharge passage 842. The main body frame base 600 is formed and flows through the main body frame base ball-removing passage formed on the rear surface of the lower rear wall portion of the main body frame base 600, and flows down to the rear side of the board unit base 810 through the opening of the board unit base 810. The game ball and the game ball discharged from the out ball discharging part of the game board 4 and received by the discharge ball receiving part 841 can be discharged to the lower rear side of the pachinko gaming machine 1 through the discharge passage 842. Has become.

The power supply board box 850 is formed in a horizontally long box shape having an open front, and includes a power supply board 851 attached so as to close a front end opening thereof. The power supply board box 850 is configured to accommodate various electronic components mounted on the power supply board 851, and heat generated from the electronic components and the like can be externally transmitted through a plurality of slits 850a formed on the upper surface and the lower surface. It can be released to. A power switch 852 attached to the power board 851 faces the rear surface of the power board box 850.

The payout control board box 860 includes a horizontally long and thin box-shaped box base 861 whose rear is opened, a thin box-shaped cover 862 which is fitted into the box base 861 from the rear side and whose front is opened, and the box base 861. And a payout control board 4110 attached to the rear surface of the payout control board 4110 and covered with the cover 862. Further, the payout control board box 860 includes a plurality of separating/cutting portions 863 formed on both the box base 861 and the cover 862 so as to project outward from the left end in rear view, and the separating/cutting portions 863 are provided at one place. The box base 861 and the cover 862 are caulked and fixed. Thus, in order to separate the box base 861 and the cover 862, the separation cutting section 863 cannot be separated without cutting, and when the payout control board box 860 is opened, a trace thereof remains. .. Therefore, it is possible to know whether or not the payout control board box 860 has been illegally opened/closed. In this embodiment, the payout control board box 860 can be opened and closed only once for inspection or the like.

Further, in the payout control board box 860, the operation switch 860a (error canceling unit) attached to the payout control board 4110, the inspection output terminal 860c, and the like are exposed rearward through the cover 862. Further, in the payout control board box 860, various connection terminals for connecting to the main control board 4100 and the like are exposed rearward through the cover 862. The operation switch 860a is operated to clear the RAM built in the microprocessor of the payout control board 4110 and the RAM built in the microprocessor of the main control board 4100 when the power is turned on, or after the power is turned on. When an error is reported, it is operated to cancel the error. The function to clear the RAM when the power is turned on and the function to clear the RAM after the power is turned on (the period when the function as the RAM clear is performed has passed. Later), the function of releasing the error is provided. A detailed description of this point will be given later.

The terminal board box 870 includes a board base 871 mounted on the rear surface of the speaker box 820, a frame peripheral relay terminal plate 868 mounted on the rear surface of the board base 871 and having peripheral panel relay terminals 872 fixed rearward, and a board base. A game ball lending device connection terminal plate 869 attached to the rear surface of the 871 and having the CR unit relay terminal 873 fixed rearward, and a board so that the peripheral panel relay terminal 872 and the CR unit relay terminal 873 face the rear side. And a substrate cover 874 that covers the rear side of the base 871. The peripheral panel relay terminal 872 is for connecting to a frequency display for displaying the operating state of the pachinko gaming machine 1 provided on the side of the pachinko gaming machine where the pachinko gaming machine 1 is installed. The terminal 873 is for connecting to a CR unit installed adjacent to the pachinko gaming machine 1.

The main door relay terminal board 880 and the peripheral door relay terminal board 882 are provided in the door frame 5 and the peripheral control board 4140 and the payout control board 4110 of the board unit 800 provided in the game board 4 attached to the main body frame 3. It is for relaying the connection with the handle device 500, various substrates, the operation unit 400, and the like. The main-door relay terminal plate 880 and the peripheral-door relay terminal plate 882 are attached to a board mounting portion formed on the front surface of the board unit base 810 so as to face from the front surface of the main body frame base 600 to the front side. The wiring extending from the door frame 5 can be connected.

Note that the main door relay terminal plate 880 and the peripheral door relay terminal plate 882 are configured such that the front sides thereof are covered by a relay terminal plate cover 692 attached to the front surface of the main body frame base 600, and the relay terminal plate cover 692 is covered. Only the connection terminal is exposed to the front side through the opening 692a, so that the front surface of the body frame 3 has a neat appearance.

In addition, the main door relay terminal plate 880, the ball rental button 361 of the ball rental unit 360 in the dish unit 300 arranged on the door frame 5 side, the return button 362, the lending remaining display portion 363, the potentiometer 512 of the handle device 500, and the touch. This is for relaying the connection between the switch 516, the firing stop switch 518, and the full tank switch 550 of the foul cover unit 540 and the payout control board 4110 arranged on the main body frame 3 side. Regarding the ball rental button 361 of the ball rental unit 360, the return button 362, the lending remaining display portion 363, the potentiometer 512 of the handle device 500, the touch switch 516, the firing stop switch 518, and the full tank switch 550 of the foul cover unit 540. The description will be given later.

Further, the peripheral door relay terminal plate 882 is provided for each of the decoration units 200, 240, 280 arranged on the door frame 5 side, the dish unit 300, and each decoration board of the door frame 5 provided in the operation unit 400 (hereinafter, referred to as “ It may be referred to as a “plurality of frame side decorative boards”), and detects the operation of the dial drive motor 414 provided in the operation unit 400, the dial operation unit 401 and the pressing operation unit 405 provided in the operation unit 400, respectively. It is for relaying connections between various switches and the peripheral control board 4140 of the game board 4 arranged on the main body frame 3 side. In addition, each of the decoration units 200, 240, 280 arranged on the side of the door frame 5, the dish unit 300, and a plurality of frame-side decoration boards provided in the operation unit 400, a dial drive motor 414 provided in the operation unit 400, The various switches for detecting the operations of the dial operation unit 401 and the pressing operation unit 405 provided in the operation unit 400 will be described later.

[4. Overall structure of door frame]
Next, the door frame 5 provided on the front side of the main body frame 3 so as to be openable and closable will be described with reference to FIG. 7. FIG. 7 is a perspective view of the door frame. As shown in FIG. 7, the door frame 5 has a door frame base unit 100 having a game window 101 whose outer shape is a vertically long rectangular shape and whose inner peripheral shape is a slightly vertically long circular shape (elliptical shape), and a door. A right side decoration unit 200 attached to the right outer periphery of the game window 101 on the front side of the frame base unit 100, and a left side facing the right side decoration unit 200 and attached to the left outer periphery of the game window 101 on the front side of the door frame base unit 100. A decoration unit 240, an upper decoration unit 280 attached to the upper outer periphery of the game window 101 on the front surface of the door frame base unit 100, and a door frame base unit arranged below the lower ends of the right side decoration unit 200 and the left side decoration unit 240. And a pair of speaker covers 290 attached to the front surface of 100.

Further, the door frame 5 is mounted on the front side of the door frame base unit 100 at the lower part of the game window 101, the operation unit 400 mounted at the center of the upper part of the plate unit 300, and at the right side of the plate unit 300. The upper plate side liquid crystal display device 470, the handle device 500 that penetrates the plate unit 300 and is attached to the lower right corner of the door frame base unit 100 for performing a game ball driving operation, and the door frame base unit 100. A foul cover unit 540 which is arranged on the rear side of the dish unit 300 and is mounted on the rear surface of the door frame base unit 100, and a ball feeding unit 580 which is mounted on the rear surface of the door frame base unit 100 on the right side of the foul cover unit 540 (see FIG. 1) and a glass unit 590 attached to the rear side of the door frame base unit 100 so as to close the game window 101.

[4-1. Door frame base unit]
Next, the door frame base unit 100 will be described. The door frame base unit 100 has a vertically elongated rectangular outer shape, and a door frame base main body 110 having a game window 101 penetrating in the front-rear direction and having a vertically elongated substantially elliptical shape, and a door frame. An upper bracket 120 mounted on the center of the upper part of the game window 101 on the front surface of the base body 110, and a pair of speakers mounted on the left and right outer sides of the lower end of the game window 101 on the front surface of the door frame base body 110. 130 and a handle bracket for supporting the handle device 500, which is attached to the lower right corner of the front surface of the door frame base body 110 in front view.

Further, the door frame base unit 100 includes a metal frame-shaped reinforcing unit 150 (see FIG. 1) fixed to the rear side of the door frame base body 110, and a game window 101 on the rear surface of the door frame base body 110. A security cover 180 (see FIG. 1) attached so as to cover the lower portion, and a glass unit locking member 190 (see FIG. 1) rotatably attached at a predetermined position on the outer periphery of the game window 101 on the rear surface of the door frame base body 110. 1)), and a firing cover 191 (see FIG. 1) that is arranged on the left side (open side) from the center in the left-right direction in rear view and is attached to the rear surface of the door frame base body 110 along the lower end of the game window 101. The handle relay terminal plate that relays the connection between the potentiometer 512 of the handle device 500, which will be described later, and the main control board 4100 provided in the game board 4, which will be described later, which is attached to the rear surface of the door frame base body 110 below the firing cover 191. 192 (see FIG. 1), a handle relay terminal plate cover 193 (see FIG. 1) covering the rear side of the handle relay terminal plate 192, and a firing cover 191 and a handle relay terminal plate 192 sandwiching the center in the left-right direction. A frame decoration drive amplifier board 194 (see FIG. 1) which is arranged on the opposite side (right side of the center in the left-right direction in rear view (shaft support side) in rear view) and attached to the rear surface of the door frame base body, and frame decoration drive A frame decoration drive amplifier board cover 195 (see FIG. 1) that covers the rear side of the amplifier board 194.

The frame decoration drive amplifier board 194 is electrically connected to the speaker 130 and electrically connected to a plurality of frame side decoration boards provided in each of the decoration units 200, 240, 280, the dish unit 300, and the operation unit 400. It is connected. The frame decoration drive amplifier board 194 is electrically connected to a peripheral control board 4140 provided on the game board 4 described later, amplifies the acoustic signal sent from the peripheral control board 4140, and outputs it to each speaker 130. In addition to the amplifier circuit, various LED controls for driving a plurality of LEDs as decorative LEDs provided on a plurality of frame-side decorative substrates included in each of the decoration units 200, 240, 280, the dish unit 300, and the operation unit 400 It has a circuit. Although not specifically shown, in the present embodiment, the frame decoration drive amplifier board 194, the dial drive motors and switches provided in the operation unit 400, the handle relay terminal plate 192, the ball rental unit 360 of the dish unit 300. Etc., and the wiring for electrically connecting the payout control board 4110, the peripheral control board 4140, and the like are collectively bundled at the right side (axis support side) position of the frame decoration drive amplifier board 194 in a rear view. It extends rearward and is connected to the main door relay terminal plate 880 and the peripheral door relay terminal plate 882 of the main body frame 3.

Here, each decoration unit 200, 240, 280 will be briefly described. As described above, each of the decoration units 200, 240, 280 is provided with the plurality of frame-side decoration substrates. A frame side peripheral control MPU control target decorative board which is a control target directly controlled by a peripheral control MPU of a peripheral control board 4140 to be described later and a sound source built-in VDP of the peripheral control board 4140 to be described later are directly attached to the frame side decorative board. There is a frame-side VDP control target decorative substrate which is a control target to be controlled.

The right side decoration unit 200 is a right side VDP control target first that is light-emitted and decorated by a plurality of LEDs (decorative LEDs) provided on the frame side VDP control target decoration substrates RV1 to RV3 from the lower side to the upper side. The light emission decoration region RTV1 to the right side VDP control target third light emission decoration region RTV3 are formed, and are arranged between the right side VDP control target first light emission decoration region RTV1 and the right side VDP control target second light emission decoration region RTV2. The plurality of LEDs (decoration) provided on the frame-side peripheral control MPU control target decoration substrate RM1 that separates the right side VDP control target first light emission decoration region RTV1 from the right side VDP control target second light emission decoration region RTV2 by a predetermined distance. Between the right side peripheral control MPU control target first light emission decoration region RTM1 and the right side VDP control target second light emission decoration region RTV2 and the right side VDP control target third light emission decoration region RTV3 which are light-emitting decorated by A plurality of LEDs provided on the frame side peripheral control MPU control target decorative substrate RM2, which are arranged to separate the right side VDP control target second light emitting decoration region RTV2 and the right side VDP control target third light emitting decoration region RTV3 by a predetermined distance. The right side peripheral control MPU control target which is light-emitted and decorated by the decoration LED) and the frame side peripheral control MPU control target which is arranged in the upper vicinity of the right side VDP control target third light emission decoration region RTV3. A right side peripheral control MPU control target third light emission decoration area RTM3, which is light emission decoration by a plurality of LEDs (decoration LEDs) provided on the decoration substrate RM3, is formed.

The left side decoration unit 240 is a left side VDP control target first that is light-emitted and decorated by a plurality of LEDs (decorative LEDs) provided on the frame side VDP control target decoration substrates LV1 to LV3 from the lower side to the upper side. The light emission decoration region LTV1 to the left side VDP control target third light emission decoration region LTV3 are formed, and are arranged between the left side VDP control target first light emission decoration region LTV1 and the left side VDP control target second light emission decoration region LTV2. The plurality of LEDs (decoration) provided on the frame-side peripheral control MPU control target decoration substrate LM1 that separates the left side VDP control target first light emission decoration region LTV1 and the left side VDP control target second light emission decoration region LTV2 by a predetermined distance. Between the left side peripheral control MPU control target first light emission decoration region LTM1, the left side VDP control target second light emission decoration region LTV2, and the left side VDP control target third light emission decoration region LTV3, which are light-emitted and decorated by the LED for LED). A plurality of LEDs provided on the frame-side peripheral control MPU control target decorative substrate LM2, which are arranged to separate the left side VDP control target second light emitting decoration region LTV2 and the left side VDP control target third light emitting decoration region LTV3 by a predetermined distance. Frame-side peripheral control MPU control target, which is arranged in the upper vicinity of the left side peripheral control MPU control target second light emission decoration region LTM2 and the left side VDP control target third light emitting decoration region LTV3, which are illuminated and decorated by the decoration LED) A left side peripheral control MPU control target third light emission decoration area LTM3, which is light emission decoration by a plurality of LEDs (decoration LEDs) provided on the decoration substrate LM3, is formed.

The upper decoration unit 280 is a right side VDP control target fourth light emission decoration area that is light-emitted from a plurality of LEDs (decoration LEDs) provided on the frame side VDP control target decoration substrate RV4 from the lower right side to the upper side. RTV4 is formed, and light emission decoration is performed by a plurality of LEDs (decorative LEDs) provided on the frame-side peripheral control MPU control target decoration substrate RM4, which is arranged in the vicinity above the right side VDP control target fourth light emission decoration region RTV4. The right side peripheral control MPU control target fourth light emission decoration region RTM4 is formed. Further, the upper decoration unit 280 is a left side VDP control target fourth light emission decoration area that is light-emitted from a plurality of LEDs (decoration LEDs) provided on the frame side VDP control target decoration substrate LV4 from the lower left side to the upper side. The LTV 4 is formed, and a plurality of LEDs (decorative LEDs) provided on the frame-side peripheral control MPU control target decorative substrate LM4 arranged near the left side VDP control target fourth light emission decoration region LTV4 emit light. The left side peripheral control MPU control target fourth light emission decoration region LTM4 is formed. The left side VDP control target fourth light emission decoration area LTV4 and the right side VDP control target fourth light emission decoration area RTV4 are arranged in a left-right pair, and the left side peripheral control MPU control target fourth light emission decoration area LTM4 and the right side. Side peripheral control MPU control object 4th light emission decoration area RTM4 and a left-right pair are arrange|positioned.

When the decoration units 200, 240, and 280 are attached to the door frame base unit 100, they are formed in the right side VDP control target third light emission decoration area RTV3 and the upper decoration unit 280 formed in the right side decoration unit 200. A right side peripheral control MPU control target third light emission decoration region RTM3 formed in the right side decoration unit 200 is disposed between the right side VDP control target fourth light emission decoration region RTV4 and the right side VDP control target fourth light emission decoration region RTV4. The third light emission decoration region RTV3 and the right side VDP control target fourth light emission decoration region RTV4 are separated from each other by a predetermined distance, and the left side VDP control target third light emission decoration region LTV3 and the upper decoration unit formed in the left side decoration unit 240. A left side peripheral control MPU control target third light emission decoration area LTM3 formed in the left side decoration unit 240 is arranged between the left side VDP control target fourth light emission decoration area LTV4 formed in 280 and the left side. The VDP control target third light emission decoration area LTV3 and the left side VDP control target fourth light emission decoration area LTV4 are separated by a predetermined distance.

In the state where the decoration units 200 and 240 are attached to the door frame base unit 100, the left side VDP control target first light emission decoration region LTV1 to the left side VDP control target third formed on the left side decoration unit 240. The light emission decoration area LTV3 and the right side VDP control target first light emission decoration area RTV1 to the right side VDP control target third light emission decoration area RTV3 formed in the right side decoration unit 200 are arranged in a pair on the left and right, and on the left side. Left side peripheral control formed on the side decoration unit 240 MPU control target first light emitting decoration area LTM1 to left side peripheral control MPU control target third light emitting decoration area LTM3 and right side peripheral control formed on the right side decoration unit 200 The MPU control target first light emission decoration region RTM1 to the right side peripheral control MPU control target third light emission decoration region RTM3 are arranged in a left-right pair.

Frame side VDP control target decorative boards RV1 to RV3 of the right side decoration unit 200, frame side VDP control target decorative boards LV1 to LV3 of the left side decoration unit 240, frame side VDP control target decorative board RV4 and frame side of the upper decoration unit 280 The resist color of the surface (mounting surface) on which a plurality of LEDs (decorative LEDs) are provided on each of the VDP control target decorative substrates LV4 and the resist color of the rear surface are black. Further, the mounting surfaces of the frame-side VDP control target decorative boards RV1 to RV4 and the frame-side VDP control target decorative boards LV1 to LV4 have rectangular openings at positions corresponding to a plurality of LEDs (decorative LEDs) provided respectively. Grid-shaped black partition plates having (square-shaped openings) formed thereon are mounted as spacers, respectively, and are covered with a designed resin cover body. In other words, the frame-side VDP control target decorative boards RV1 to RV4, and the frame-side VDP control target decorative boards RV1 to RV4 and the frame are provided between the mounting surface of the frame-side VDP control target decorative boards LV1 to LV4 and the cover body. A black grid-like partition plate having rectangular openings formed at positions corresponding to a plurality of LEDs (decorative LEDs) provided on the mounting surfaces of the side VDP control target decorative substrates LV1 to LV4, respectively, is sandwiched as spacers. It has a structured structure.

When the partition plate is sandwiched between the mounting surface of the frame-side VDP control target decorative boards RV1 to RV4 and the frame-side VDP control target decorative boards LV1 to LV4 and the cover body, a rectangular shape formed on the partition plate It is possible to individually surround a plurality of LEDs (decorative LEDs) provided on the mounting surfaces of the frame-side VDP control target decorative substrates RV1 to RV4 and the frame-side VDP control target decorative substrates LV1 to LV4 corresponding to the openings of the above. In addition, the rear side of the partition plate (that is, the mounting surface side of the frame-side VDP control target decorative boards RV1 to RV4 and the frame-side VDP control target decorative boards LV1 to LV4) and the frame-side VDP control target decorative boards RV1 to RV4. , And the mounting surfaces of the frame-side VDP control target decorative substrates LV1 to LV4 can be in close contact with each other. As a result, the partition plate is formed to emit light from a plurality of LEDs (decorative LEDs) provided on the mounting surfaces of the frame-side VDP control target decorative boards RV1 to RV4 and the frame-side VDP control target decorative boards LV1 to LV4, respectively. Since it is possible to irradiate toward the back surface side of the cover body through the rectangular openings arranged in a grid pattern, the LEDs are emitted by respectively illuminating the rectangular openings formed in the partition plate in the grid shape. Can be configured as an LED display in which a plurality of are arranged vertically and horizontally.

That is, the right side VDP control target first light emission decoration region RTV1 to right side VDP control target third light emission decoration region RTV3 formed in the right side decoration unit 200, and the right side VDP control target first light emission decoration region RTV3 formed in the upper decoration unit 280. Each of the four light emission decoration regions RTV4 can display various information as dots by an LED display, and the left side VDP control target first light emission decoration region LTV1 to the left side VDP control target formed in the left side decoration unit 240. The third light emitting decoration area LTV3 and the left side VDP control target fourth light emitting decoration area LTV4 formed in the upper decoration unit 280 can each perform dot display of various information as an LED display.

On the back surface side (mounting surface side) of the cover body that covers the mounting surfaces of the frame-side VDP control target decorative boards RV1 to RV4 and the frame-side VDP control target decoration boards LV1 to LV4, respectively, a metal vapor deposition film is thinly formed (for example, , Aluminum is thinly vapor-deposited), but is substantially transparent, and a plurality of LEDs (decorative LEDs) provided on each of the frame-side VDP control target decorative substrates RV1 to RV4 and the frame-side VDP control target decorative substrates LV1 to LV4 It is possible to easily visually recognize the light emission mode of (1).

Accordingly, the resist color of the mounting surfaces of the frame-side VDP control target decorative boards RV1 to RV4 and the frame-side VDP control target decorative boards LV1 to LV4 is black, and the base is black due to the grid-shaped black partition plate. The thin metal deposition film is formed so that the back surface side (mounting surface side) of the cover body is substantially transparent (for example, aluminum is thinly deposited), so that the frame side VDP control target decorative substrates RV1 to RV4, And the plurality of frame-side VDP control target decorative boards LV1 to LV4 are turned off, the frame-side VDP control target decorative boards RV1 to RV4 and the frame-side VDP control target decorative board LV1 The metallic feeling can be expressed on the surface of the cover body that covers the mounting surfaces of the to LV4.

The partition plate is sandwiched between the mounting surfaces of the frame-side VDP control target decorative boards RV1 to RV4 and the frame-side VDP control target decorative boards LV1 to LV4 and the cover body. You may comprise so that each substantially sandwiched lens plate in which a metal vapor deposition film is thinly formed (for example, aluminum is thinly vapor deposited). This lens plate is in a state of being sandwiched between the partition plate and the cover body, at a position corresponding to a rectangular opening (square opening) arranged in a grid pattern formed on the partition plate, A rectangular opening formed in the partition plate by a predetermined distance (for example, 2 mm) from the surface on the partition plate side (that is, the back surface of the lens plate) toward the surface of the cover body (that is, the front surface of the lens plate). Recesses having the same outer shape as the outer shape of the square opening) are formed, and the recesses are arranged in a grid pattern. These rectangular recesses function as lens portions. Light emission from a plurality of LEDs (decorative LEDs) provided on the mounting surfaces of the frame-side VDP control target decorative boards RV1 to RV4 and the frame-side VDP control target decorative boards LV1 to LV4 is a grid pattern formed on a partition plate. It is possible to diffuse through the rectangular openings arranged in the above, and the rectangular concave portions formed in the lens plate and arranged in a lattice shape.

Here, a plurality of LEDs (decorative LEDs) provided on the mounting surfaces of the frame-side VDP control target decorative boards RV1 to RV4 and a plurality of LEDs provided on the mounting surfaces of the frame-side VDP control target decorative boards LV1 to LV4, respectively. The arrangement of the LED (ornamental LED) will be briefly described.

When the decoration units 200, 240, 280 are attached to the door frame base unit 100, the right side VDP control target first light emission decoration region RTV1 to the right side VDP control target third formed on the right side decoration unit 200. The light emission decoration region RTV3, the right side VDP control target fourth light emission decoration region RTV4 formed in the upper decoration unit 280, and the left side VDP control target first light emission decoration region LTV1 to left side formed in the left side decoration unit 240. The VDP control target third light emission decoration region LTV3 and the left side VDP control target fourth light emission decoration region LTV4 formed in the upper decoration unit 280 are arranged in a pair on the left and right, and the frame side VDP control target decoration substrate RV1 to A plurality of LEDs (decorative LEDs) provided on the mounting surface of the RV4 and a plurality of LEDs (decorative LED) provided on the mounting surfaces of the frame-side VDP control target decorative substrates LV1 to LV4 are bilaterally symmetrical. Is located in. Here, a plurality of LEDs (decorative LEDs) provided on the mounting surfaces of the frame-side VDP control target decorative boards RV1 to RV4 will be described, respectively, and provided on the mounting surfaces of the frame-side VDP control target decorative boards LV1 to LV4. The description of the plurality of LEDs (ornamental LEDs) that are provided will be omitted.

As described above, the right side VDP control target first light emission decoration region RTV1 is light-emitted and decorated by a plurality of LEDs (decorative LEDs) provided on the frame-side VDP control target decoration substrate RV1. The frame-side VDP control target decorative substrate RV1 has first to fourteenth blocks in which a plurality of full-color LEDs (decorative LEDs) are horizontally provided in a line from the lower side to the upper side. The first block is provided with nine full-color LEDs (decorative LEDs) horizontally in a row, and the second block is provided with ten full-color LEDs (decorative LEDs) horizontally in a row. The block is provided with nine full-color LEDs (decorative LEDs) horizontally in a row, and the seventh and eighth blocks are provided with eight full-color LEDs (decorative LEDs) horizontally in a row, respectively. Eight full-color LEDs (decorative LEDs) are horizontally arranged in a row in blocks 9 to 11, and six full-color LEDs (decorative LEDs) are horizontally arranged in a row in the twelfth block. The block is provided with four full-color LEDs (decorative LEDs) horizontally in a row, and the fourteenth block is provided with two full-color LEDs (decorative LEDs) horizontally in a row. The first block to the fourteenth block are dots along the shape of the right side VDP control target first light emission decoration region RTV1 (that is, the size of the rectangular openings arranged in the grid formed on the partition plate described above. ) Units are arranged on the frame-side VDP control target decorative substrate RV1 with a right shift, and a total of 104 full-color LEDs (decorative LEDs) are provided on the frame-side VDP control target decorative substrate RV1. In the left side VDP control target first light emission decoration area LTV1, dots (that is, arranged in a grid pattern formed on the partition plate described above along the shape of the left side VDP control target first light emission decoration area LTV1. The first block to the fourteenth block are arranged on the left side in a unit of a size of a rectangular opening, and a total of 104 full-color LEDs (decorative LEDs) are provided.

As described above, the right side VDP control target second light emission decoration area RTV2 is light-emitted and decorated by a plurality of LEDs (decorative LEDs) provided on the frame-side VDP control target decoration substrate RV2. The frame-side VDP control target decorative substrate RV2 includes first to 22nd blocks in which a plurality of full-color LEDs (decorative LEDs) are horizontally provided in a line from the lower side to the upper side. The first block is provided with three full-color LEDs (decorative LEDs) horizontally in one row, and the second block is provided with four full-color LEDs (decorative LEDs) horizontally in one row. Five full-color LEDs (decorative LEDs) are horizontally arranged in a row in the block, and four full-color LEDs (decorative LEDs) are horizontally arranged in a row in the sixth to twentieth blocks, respectively. The block is provided with three full-color LEDs (decorative LEDs) horizontally in a row, and the 22nd block is provided with two full-color LEDs (decorative LEDs) horizontally in a row. The first block to the 22nd block are dots along the shape of the right side VDP control target second light emission decoration region RTV2 (that is, the size of the rectangular openings arranged in the grid formed on the partition plate described above. ) Units are arranged on the frame-side VDP control target decorative substrate RV2 with a right shift, and a total of 87 full-color LEDs (decorative LEDs) are provided on the frame-side VDP control target decorative substrate RV2. In the left side VDP control target second light emission decoration area LTV2, dots (that is, arranged in a grid pattern formed on the partition plate described above along the shape of the left side VDP control target second light emission decoration area LTV2. The first block to the 22nd block are arranged on the left side in a unit of the size of a rectangular opening), and a total of 87 full-color LEDs (decorative LEDs) are provided.

As described above, the right side VDP control target third light emission decoration region RTV3 is light-emitted and decorated by a plurality of LEDs (decorative LEDs) provided on the frame-side VDP control target decoration substrate RV3. The frame-side VDP control target decorative substrate RV3 has first to 26th blocks in which a plurality of full-color LEDs (decorative LEDs) are horizontally provided in a row from the lower side to the upper side. Two full-color LEDs (decorative LEDs) are horizontally provided in one row in the first block, and three full-color LEDs (decorative LEDs) are horizontally provided in three rows in the second block. Four full-color LEDs (decorative LEDs) are horizontally arranged in a row in each block, and five full-color LEDs (decorative LEDs) are horizontally arranged in each row in blocks 8 to 10, respectively. Four full-color LEDs (ornamental LEDs) are horizontally provided in a row in each of the blocks to the thirteenth block, and five full-color LEDs (ornamental LEDs) are horizontally provided in each of the fourteenth blocks to the sixteenth block. Sixteen full color LEDs (decorative LEDs) are horizontally arranged in a row in blocks 17 to 21, and full color LEDs (decorative LEDs) are horizontally arranged in a row in blocks 22 and 23, respectively. 5 full color LEDs (decorative LEDs) are provided horizontally in a row in the 24th block, and 3 full color LEDs (decorative LEDs) are provided in a row horizontally in the 25th block. In the 26th block, two full-color LEDs (decorative LEDs) are horizontally provided in a row. The first block to the 26th block are dots along the shape of the right side VDP control target third light emission decoration area RTV3 (that is, the size of the rectangular openings arranged in the grid formed on the partition plate described above. ) Units are arranged on the frame-side VDP control target decorative substrate RV3 with a shift to the right or left, and a total of 116 full-color LEDs (decorative LEDs) are provided on the frame-side VDP control target decorative substrate RV3. In the left side VDP control target third light emission decoration area LTV3, dots (that is, arranged in a grid pattern formed on the partition plate described above along the shape of the left side VDP control target third light emission decoration area LTV3. The first block to the 26th block are arranged on the left side or the right side in units of a rectangular opening size), and a total of 116 full-color LEDs (decorative LEDs) are provided.

As described above, the right side VDP control target fourth light emission decoration region RTV4 is light-emitted and decorated by a plurality of LEDs (decorative LEDs) provided on the frame-side VDP control target decoration substrate RV4. The frame-side VDP control target decorative substrate RV4 has first to twenty-fifth blocks in which a plurality of full-color LEDs (decorative LEDs) are horizontally provided in a row from the lower side to the upper side. The first block is provided with two full-color LEDs (decorative LEDs) horizontally in one row, the second block is provided with three full-color LEDs (decorative LEDs) horizontally in one row, and the third block is full-color LEDs. Four LEDs (ornamental LEDs) are provided horizontally in one row, six full-color LEDs (ornamental LEDs) are horizontally provided in one row in the fourth block, and five full-color LEDs (ornamental LEDs) are provided in the fifth block. 7 are arranged horizontally in a row, 9 full color LEDs (decorative LEDs) are arranged horizontally in a row in the sixth block, and 11 full color LEDs (decorative LEDs) are arranged horizontally in a row in the 7th block. The 8th block is provided with 12 full-color LEDs (decorative LEDs) horizontally in a row, and the 9th block is provided with 14 full-color LEDs (decorative LEDs) horizontally in a row. Blocks and 11th block are each provided with 15 full-color LEDs (decorative LEDs) horizontally in a row, and blocks 12 and 13 are each provided with 16 full-color LEDs (decorative LEDs) horizontally in a row. The fourteenth block is provided with 17 full-color LEDs (decorative LEDs) horizontally in a row, and the fifteenth block is provided with sixteen full-color LEDs (decorative LEDs) horizontally in a row. Fifteen full-color LEDs (decorative LEDs) are provided horizontally in a row in blocks and seventeenth blocks, respectively, and fourteen full-color LEDs (decorative LEDs) are provided in a row horizontally in eighteenth blocks. Blocks are provided with 13 full-color LEDs (decorative LEDs) horizontally in a row, block 20 is provided with 11 full-color LEDs (decorative LEDs) horizontally in a row, and block 21 is a full-color LED ( Decorative LEDs) are arranged horizontally in a row, ten full color LEDs (decorative LEDs) are arranged in a row horizontally in the 22nd block, and full color LEDs (decorative LEDs) are arranged in a row in the 23rd block. In the 24th block, 5 full-color LEDs (decorative LEDs) are horizontally arranged in one row, and in the 25th block, 3 full-color LEDs (decorative LEDs) are horizontally arranged in 3 rows. Has been. The first block to the 25th block are dots along the shape of the right side VDP control target fourth light emission decoration region RTV4 (that is, the size of the rectangular openings arranged in the grid formed on the partition plate described above. ) Units are arranged on the frame-side VDP control target decorative substrate RV4 with a right or left shift, and a total of 265 full-color LEDs (decorative LEDs) are provided on the frame-side VDP control target decorative substrate RV4. In the left side VDP control target fourth light emission decoration area LTV4, dots (that is, arranged in a grid pattern formed on the partition plate described above along the shape of the left side VDP control target fourth light emission decoration area LTV4. The first block to the 25th block are arranged on the left side or the right side in units of a rectangular opening size), and a total of 265 full-color LEDs (decorative LEDs) are provided.

As described above, the right side VDP control target first light emission decoration region RTV1 to the right side VDP control target fourth light emission decoration region RTV4 are 104 full-color LEDs provided on the frame side VDP control target decoration substrate RV1 as described above. , 87 full-color LEDs provided on the frame-side VDP control target decorative substrate RV2, 116 full-color LEDs provided on the frame-side VDP control target decorative substrate RV3, and 265 full-color LEDs provided on the frame-side VDP control target decorative substrate RV4. A total of 572 full-color LEDs, which are full-color LEDs, are used for light emission decoration, and the left side VDP control target first light emission decoration area LTV1 to the left side VDP control target fourth light emission decoration area LTV4 are, as described above, the frame side VDP. 104 full color LEDs provided on the control target decorative substrate LV1, 87 full color LEDs provided on the frame side VDP control target decorative substrate LV2, 116 full color LEDs provided on the frame side VDP control target decorative substrate LV3, and a frame Light emission decoration is performed by a total of 572 full color LEDs including 265 full color LEDs provided on the side VDP control target decorative substrate LV4.

That is, the right side decoration unit 200 (right side VDP control target first light emission decoration area RTV1 to right side VDP control target third light emission decoration area RTV3), left side decoration unit 240 (left side VDP control target first light emission decoration area LTV1). -Left side VDP control target third light emission decoration area LTV3) and upper decoration unit 280 (right side VDP control target fourth light emission decoration area RTV4, left side VDP control target fourth light emission decoration area LTV4) are right side VDP control Target first light emission decoration area RTV1 to right side VDP control 572 full-color LEDs (decorative LEDs) for light emission decoration of the target fourth light emission decoration area RTV4, and left side VDP control target first light emission decoration area LTV1 to left side VDP The control target fourth light emission decoration area LTV4 is light-emitted and decorated by 572 full-color LEDs (decorative LED) and a total of 1144 full-color LEDs (decorative LED).

[4-1-1. Door frame base body]
The door frame base body 110 is formed of a synthetic resin in a vertically long frame shape, and is formed in such a manner that the game window 101 that penetrates in the front-rear direction and has a vertically elongated inner shape and a substantially elliptical shape is offset upward as a whole. Has been done. This game window 101 is formed in a smooth curved shape in which the left and right inner edges are continuous, while the lower inner edge is formed in a straight line extending left and right. Further, in the inner peripheral edge of the lower side of the game window 101 in the door frame base main body 110, a rectangular notch portion capable of inserting the first ball outlet of the foul cover unit 540 is formed on the shaft support side (left side in front view). The speaker mounting portion for mounting and fixing the speaker 130 is disposed on both the left and right outer sides of the lower side of the game window 101, and the right (open side) end of the front surface that is disposed in the lower right corner in front view and bulges forward is The handle mounting portion for mounting the handle bracket so as to be slanted backward so as to mount the handle bracket, the wiring passage opening that allows the wiring from the handle device 500 to pass therethrough at a predetermined position of the handle mounting portion, and the upper side of the handle mounting portion. A lock hole 116 that is formed in a tubular shape that extends shortly toward the front and through which a cylinder lock 1010 described below can be inserted is formed. The door frame base main body 110 has an upper side formed by the game window 101, and the widths of the left and right side sides are such that an upper reinforcing sheet metal 151, a shaft supporting side reinforcing sheet metal 152, and an open side reinforcing sheet metal 153 of a reinforcing unit 150 described later. The width is substantially the same as that of the game window 101, and the game window 101 is formed as large as possible with respect to the size of the door frame base main body in the front view.

[4-1-2. Reinforcement unit]
The reinforcing unit 150 includes an upper reinforcing sheet metal 151 (see FIG. 1) attached along the rear surface of the upper side of the door frame base body 110, and a shaft support attached along the rear side of the side wall of the door frame base body 110. The side reinforcing sheet metal 152 (see FIG. 1), the open side reinforcing sheet metal 153 (see FIG. 1) attached along the back side of the open side of the door frame base body 110, and the game window 101 of the door frame base body 110. The lower reinforcing sheet metal 154 (see FIG. 1) attached along the back surface of the lower side is provided, and they are fastened to each other with screws or rivets to form a rectangular shape.

An upper shaft supporting portion 156 having a shaft pin 155 slidably provided in the upper and lower directions on an upper surface thereof and a lower shaft supporting portion 158 having a shaft pin 157 on a lower surface thereof are provided at upper and lower ends of the shaft supporting side reinforcing sheet metal 152. It is equipped as one. Then, the upper and lower shaft pins 155, 157 are pivotally supported by the upper shaft support metal fitting 630 and the lower shaft support metal fitting 640 formed above and below the shaft support side of the main body frame 3, so that the door frame 5 is moved relative to the main body frame 3. It can be opened and closed freely.

Further, a hook cover 165 that comes into contact with the door frame hook portion 1041 of the locking device 1000 is provided at the lower rear portion of the open side reinforcing sheet metal 153. The hook cover 165 engages with the door frame hook portion 1041 of the locking device 1000 (locking device) attached along the open side of the body frame 3 when closing the door frame 5 with respect to the body frame 3. By inserting a key into the cylinder lock 1010 of the locking device 1000 and rotating it to one side (rotating in the direction opposite to the direction in which the main body frame 3 is opened with respect to the outer frame 2), the door frame hook portion is obtained. The engagement between 1041 and the hook cover 165 is released, and the closed state of the door frame 5 with respect to the main body frame 3 can be released.

[4-2. Plate unit]
Next, the dish unit 300 will be described. The plate unit 300 includes an upper plate 301 and a lower plate 302 for storing the game balls paid out from the prize ball device 740, and the game balls stored in the upper plate 301 are shot through a ball feeding unit. It can be supplied to the device 650.

The upper plate upper panel 314 of the plate unit 300 is formed in a curved shape so as to project forward from the left direction toward the center when viewed from the front, and straightly forward from the center toward the right direction. It is formed to project. An operation unit attachment portion to which the operation unit 400 is attached is formed in the center of the upper portion of the dish unit 300, and a liquid crystal attachment portion 314d for attaching the upper tray side liquid crystal display device 470 is formed on the right side of the operation unit attachment portion. .. The upper plate upper panel 314 on which the liquid crystal mounting portion 314d is formed is formed in a plate shape, and when this portion is pressed downward by a player, for example, the portion is bent downward. When the pressing force exceeds a predetermined force, the upper plate upper panel 314 is broken. This is because the upper plate side liquid crystal display device 470 is expensive, and when the player presses the screen of the upper plate side liquid crystal display device 470 with the hand, the force is received by the upper plate upper panel 314. The upper plate side liquid crystal display device 470 is prevented from being damaged by bending the upper plate upper panel 314. That is, the upper plate upper panel 314 is damaged before the upper plate side liquid crystal display device 470 is damaged. If the upper plate upper panel 314 is damaged, the plate unit 300 will be replaced. In this case, the upper plate side liquid crystal display device 470 is detached from the broken upper plate upper panel 314 and attached to the upper plate upper panel 314 of the plate unit 300 to be replaced for reuse.

Further, in the plate unit 300, an upper plate ball removing mechanism 340 for removing the game balls stored in the upper plate 301 to the lower plate 302 according to the operation of the upper plate ball removing button 341, and a lower plate ball removing button 354. (Not shown) installed adjacent to the lower plate ball removing mechanism 350 for removing the game balls stored in the lower plate 302 downward through the lower plate ball removing holes 324b in accordance with the operation of, and the pachinko gaming machine 1. The ball rental unit 360 for operating the CR unit.

[4-2-1. Operation unit]
The operation unit 400 is disposed on the front surface of the upper plate 301 at the substantially center in the left-right direction when viewed from the front, and has a dial operation unit 401 (operation unit) that can be rotated by the player and a pressing operation unit 405 (which can be pressed by the player). The operation unit) is provided, and the operation of the player can be accepted or the dial operation unit 401 can be moved according to the game state, and not only the operation of driving the game ball into the player, , It is also possible to participate in the production during the game. The rotation (rotation direction) of the dial operation unit 401 is detected by a rotation detection switch included in the operation unit 400, and the operation of the pressing operation unit 405 is detected by a pressing detection switch included in the operation unit 400.

Further, the operation unit 400 can rotate the dial operation portion 401 in the clockwise direction or the counterclockwise direction by the driving force of the dial drive motor 414. In addition, the operation unit 400 gradually rotates the dial operation unit 401 in a stepwise manner by the driving force of the dial drive motor 414 using a stepping motor, or when the player rotationally operates the dial operation unit 401, It is possible to assist the rotation, prevent it from turning intentionally, and give a click feeling to the rotation. Further, the operation unit 400 can vibrate the dial operation unit 401 by alternately repeating the rotation for rotating the dial drive motor 414 in small increments and the rotation for rotating the dial drive motor 414 in reverse.

[4-2-2. Ball rental unit]
The ball lending unit 360 includes a ball lending button 361 and a return button 362 that can be pressed backward, and a lending balance display portion 363 between the ball lending button 361 and the return button 362. When the ball lending button 361 is operated, it is detected by the ball lending switch 365a, and when the return button 362 is operated, it is detected by the return switch 365b. The display content of the remaining number display 365c can be visually confirmed through the remaining lending display unit 363. The CR unit lamp 365d is arranged adjacent to the remaining frequency display 365c, and the light emission mode of the CR unit lamp 365d can be visually confirmed through the lending remaining display portion 363. The ball lending switch 365a, the return switch 365b, the remaining count display 365c, and the CR unit lamp 365d are mounted on the count display plate 365, and the count display plate 365 is mounted inside the ball rental unit 360. .. In this ball rental unit 360, when a ball or a prepaid card is inserted into a ball lending machine provided adjacent to the pachinko gaming machine 1 and a ball lending button 361 is pressed, a predetermined number of game balls are placed in a dish unit. It is possible to lend (pay out) to the upper tray 301 of 300, and when the return button 362 is pressed, the balance of the cash and the prepaid card inserted after subtracting the balance of the loan will be returned. ing. In addition, the remaining balance display unit 363 displays the remaining number of cash and prepaid cards inserted into the ball lending machine.

[4-3. Ball feeding unit]
Next, the ball feeding unit 580 will be described. The ball feeding unit 580 can supply the game balls supplied from the upper plate 301 in the plate unit 300 to the ball striking device 650 one by one, and the game balls stored in the upper plate 301 can be supplied to the upper plate ball. By operating the upper plate ball removing button 341 of the removing mechanism 340, the lower plate 302 can be pulled out.

In the ball feeding unit 580, the game balls stored in the upper plate 301 of the plate unit 300 are supplied through the upper plate ball discharge port of the upper plate 301 and the ball feeding opening of the door frame base body 110 and penetrated in the front-back direction. , And a box-shaped front cover that has a ball outlet that opens to the lower side of the entrance and has an open rear, and a box-shaped that closes the rear end of the front cover and opens the front, and penetrates in the front-back direction. Then, the rear cover having a hitting ball supply port 582a for supplying the game ball that has entered from the entrance port of the front cover to the hitting ball launching device 650, and pivoting around an axis extending in the front-rear direction between the rear cover and the front cover. A ball removing member having a partition portion that is axially supported as possible and that partitions between the entry port and the ball removing port on the rear side of the front cover, and one game ball on the partitioning portion of the ball removing member, and one ball for the rear cover. A ball feeding member rotatably supported around an axis extending in the vertical direction between the front cover and the rear cover is provided to the supply port 582a, and a ball feeding solenoid 585 for rotating the ball feeding member. There is.

When the ball feeding solenoid 585 is driven (ON state), the ball feeding member receives one game ball, while the driving of the ball feeding solenoid 585 is released (OFF state), the ball feeding member receives The game ball is sent (supplied) to the hitting ball launcher 650 side.

[4-4. Handle device]
Next, the handle device 500 will be described. The handle device 500 includes a handle base that is fixed to a handle bracket attached to the front surface of the door frame base body 110, has a cylindrical shape, and has a front end that bulges out in a direction perpendicular to the axis, and that is rotatable relative to the handle base. It is arranged on the front of the rotary handle main body 506, which is fixed to the front of the rotary handle main body, which is fixed to the front of the rotary handle main body, which is arranged on the front side, and which is integrally rotatable with the rear of the rotary handle main body. And a front end cover 508 that is fixed to the handle base and that rotatably supports the front 506 of the rotating handle body and the rear of the rotating handle body in cooperation with the handle base.

Further, the handle device 500 is attached and fixed so as to project from the front side to the rear side at the center of rotation in front of the rotary handle body, and is fitted to the shaft member having a non-circular bearing portion at the rear end, and the bearing portion of the shaft member. A potentiometer 512 that has a detection shaft portion that is rotatable together and is non-rotatably fitted to the front surface of the handle base, and the potentiometer 512 that is fixed to the front surface of the handle base so as to sandwich the potentiometer 512 with the handle base. A switch support member having a through hole through which the shaft portion can pass, a touch switch 516 attached to the rear surface of the switch support member, and a touch stop switch 516 attached to a different position on the rear surface of the switch support member. , A single-shot button that is rotatably supported by a switch support member and operates a firing stop switch 518, and a rotation handle body front 506 and a rotation handle body front 506 that are arranged so as to cover the outer periphery of the shaft member. And a handle return spring for urging the handle to return to a counterclockwise rotation end). The potentiometer 512 is for electrically adjusting the strength at which the game ball is launched toward the game area 1100 according to the rotational position of the front of the rotary handle main body 506. In addition, after the rotary handle main body 506 and after the rotary handle main body, the rotary handle body is rotated from the original rotation position to the limit rotation position that is the maximum rotation position in the clockwise direction in the front view (the rotation end in the clockwise direction in the front view). To do.

Further, in the handle device 500, the potentiometer 512 is a variable resistor, and when the front of the rotary handle main body 506 and the rear of the rotary handle main body are rotated, the detection shaft portion of the potentiometer 512 rotates via the shaft member. .. Then, the internal resistance of the potentiometer 512 changes according to the rotation position (rotation angle) of the detection shaft portion, and the driving force of the firing solenoid 654 in the ball striking device 650 changes according to the internal resistance of the potentiometer 512, and the rotation handle A game ball is driven into the game area 1100 with a firing intensity (comparable) according to the rotation angle before the main body 506 and after the rotary handle main body, that is, the rotational position before the rotary handle main body 506 and after the rotary handle main body. There is.

[4-5. Foul cover unit]
Next, the foul cover unit 540 will be described. The foul cover unit 540 is attached to the rear surface of the door frame base unit 100 below the game window 101, and is played even though a game ball paid out from the prize ball unit 700 or a ball hitting device 650 is shot. The game balls (foul balls) that have not reached the area 1100 are guided to the upper plate 301 and the lower plate 302 of the plate unit 300. The foul cover unit 540 includes a cover base whose front side is opened and has a plurality of flow paths for gaming balls inside, and a front cover which closes the front end of the cover base.

The cover base of the foul cover unit 540 has a first ball entrance 542a which is disposed in the upper right corner in a rear view and penetrates in the front-rear direction, and a first ball entrance 542a which communicates with the first ball entrance and spreads to the right in a front view as it goes to the front end of the cover base 542. Inside the cover base, which is in communication with the one ball passage, the second ball inlet 542c which is arranged outside the first ball inlet 542a (right side in rear view) and which is larger than the first ball inlet 542a, and communicates with the second ball passage. , A second sphere entrance 542c that extends downward and inclines so as to decrease toward the lower right corner in front view. The first ball entrance 542a and the second ball entrance 542c are the normal ball exit 774 and the full ball exit 776 of the full tank branching unit 770 of the prize ball unit 700 in the state where the door frame 5 is closed with respect to the main body frame 3. Are formed at positions facing each other. In addition, the second ball passage in the cover base, the height of the portion extending in the left-right direction along the lower end is about three times the height of the outer diameter of the game ball, a predetermined amount of game balls An accommodating space capable of accommodating is formed.

In addition, the cover base 542 is a foul ball inlet 542e that is arranged in the upper part of the center in the left-right direction and opens upward, and a foul that can communicate with the foul ball inlet 542e and guide the game ball to an upper part near the downstream of the second ball passage. And a ball passage. Further, the cover base is provided with an opening/closing operation piece for operating the opening/closing shutter 792 of the ball outlet opening/closing unit 790 on the rear surface below the second ball entrance. When the door frame 5 is closed with respect to the main body frame 3, the opening/closing operation piece abuts on a spherical contact portion of the opening/closing crank in the ball outlet opening/closing unit 790, thereby rotating the opening/closing crank to open the opening/closing shutter 792. It can be opened.

The front cover of the foul cover unit 540 is formed in a substantially plate shape that closes the front surface of the cover base, is arranged in the upper left corner of the front view, and is in communication with the first ball passage of the cover base, and penetrates in the front-back direction. An outlet and a second ball outlet that is arranged at the lower right corner of the front view and communicates with the downstream end of the second ball passage of the cover base 542 and penetrates in the front-rear direction. The first ball outlet of the front cover is connected to the upper plate ball supply port of the plate unit 300 through the cutout portion of the door frame base unit 100. The second ball outlet is connected to the rear end of the lower dish ball supply gutter of the dish unit 300 through the ball passage port of the door frame base body 110.

The foul cover unit 540 passes the game balls supplied from the normal ball outlet 774 of the full tank branch unit 770 of the prize ball unit 700 to the first ball inlet 542a through the first ball passage to the dish unit 300. It can be supplied to the upper plate 301 through the upper plate ball supply port. In addition, the foul cover unit 540 passes the game ball supplied from the full tank outlet 776 of the full tank branch unit 770 of the prize ball unit 700 to the second ball inlet 542c through the second ball passage to the second ball outlet. The lower plate 302 can be supplied to the lower plate 302 through the lower plate ball supply gutter and the lower plate ball supply port of the plate unit 300.

Further, in the foul cover unit 540, when the door frame 5 is closed with respect to the main body frame 3, the foul ball inlet 542e is located below the foul space 626 of the main body frame 3, and the ball striking device is provided. If the game ball shot by 650 becomes a foul ball without reaching the inside of the game area 1100 and falls in the foul space 626, it can be received by the foul ball entrance 542e. Then, the foul cover unit 540 can discharge (supply) the game ball received in the foul ball inlet 542e from the second ball outlet to the lower plate 302 of the dish unit 300 through the foul ball passage and the second ball passage. You can do it.

Further, the foul cover unit 540 forms a side surface on the upstream side (left side in front view) of the accommodation space in the second ball passage, and is pivotally supported by the cover base so as to be pivotable by the game balls stored in the accommodation space. The member, a full tank switch 550 that detects the swing of the swing member, and a spring that urges the swing member in a direction in which the full member switch 550 does not detect the swing member are provided. The swing member has a lower end rotatably supported with respect to the cover base, and an upper end that rotates leftward when viewed from the front. To form. Further, the swinging member is biased by the spring to a position where it is in a substantially vertical state. Further, the swinging member has a detection piece protruding outward on a side surface opposite to the accommodation space side, and the detection piece is detected by the full tank switch 550. That is, based on the detection signal from the full tank switch 550, it is possible to determine whether or not the gaming ball in which the accommodation space is stored is full.

[5. Overall structure of game board]
Next, the overall configuration of the game board 4 will be described with reference to FIGS. 8 and 9. 8 is a front view of the game board, and FIG. 9 is an exploded perspective view of the game board of FIG. 8 viewed from the front. As shown in FIG. 8 and FIG. 9, the game board 4 has an outer rail 1111 and an inner rail 1112, and a player operates the handle device 500 so that a game ball as a game medium is hit in a game area 1100. A frame-shaped front component member 1110 that defines the outer periphery, and a position that is visible from the game window 101 of the door frame 5 to the player side when attached to the pachinko gaming machine 1 at the lower left corner of the front component member 1110 when viewed from the front. And a plurality of openings 1158 that are attached to the front side of the front component member 1110 so as to close the game area 1100 and that penetrate through the game area 1100 in the front-rear direction in a predetermined shape at a position corresponding to the game area 1100. It has a plate-shaped game panel 1150, a front unit 2000 attached to the opening 1158 of the game panel 1150 from the front side, and a back unit 3000 attached to the rear surface of the game panel 1150.

In addition, the game board 4 is detachably attached to the front side of the back unit 3000 and is capable of displaying a predetermined effect image which can be visually recognized from the player side in accordance with the game state. Side effect display unit 1900"), and a board holder 1160 attached to the lower rear surface of the game panel 1150 so as to cover the lower portion of the back unit 3000 from the rear side. In addition, on the rear surface of the substrate holder 1160, a peripheral board box 1905 that houses the peripheral control board 4140 and the liquid crystal output board 3420, and a main control board box that houses the main control board 4100 so as to overlap the rear side of the peripheral board box 1905. 1170 and are attached.

In addition, the game board 4 includes a plurality of respective decorative boards (hereinafter, may be referred to as “a plurality of game board-side decorative boards”). The game board side decorative board includes a game board side peripheral control MPU control target decorative board which is a control target directly controlled by a peripheral control MPU of a peripheral control board 4140 described later, and a sound source built-in VDP of the peripheral control board 4140 described later. There is a game board side VDP control target decorative substrate which is a control target to be directly controlled.

[5-1. Previous component]
Next, the front component 1110 will be described. The outer shape of the front component member 1110 is a substantially rectangular shape that can be inserted into the game board holding port 601 of the main body frame 3, and the inner shape penetrates in a substantially circular shape in the front-rear direction. The outer periphery of the area 1100 is partitioned. The front component 1110 includes an outer rail 1111 that extends in a circular arc shape from a lower end on the left side to a left side in a front view in a clockwise direction and extends in an arc shape along a circumferential direction in a clockwise direction. An inner rail 1112 that is disposed inside the outer rail 1111 substantially along the outer rail 1111 and extends in an arc shape from a lower center in the left-right direction in a front view to an obliquely upper left portion in a front view so that the inner rail 1112 smoothly continues from a lower end of the inner rail 1112. An inner peripheral rail 1113 that extends in an arc shape to a position below the end (upper end) of the outer rail 1111 along the counterclockwise circumferential direction in a front view, the end (upper end) of the inner peripheral rail 1113, and the outer rail 1111. Of the game area 1100 at the boundary portion between the inner rail 1112 and the inner rail 1112, and the stop portion 1114 to which the game ball rolling along the outer rail 1111 can be brought into contact with the end (upper end) of the inner rail 1111. From the upper end of the inner rail 1112, which is rotatably supported by the upper end of the inner rail 1112 and the outer rail 1111, which is arranged at the lowermost end and is lowered toward the rear, and the upper end of the inner rail 1112. Only the closed position extending upward and the open position opened in the clockwise direction when viewed from the front to open the space between the outer rail 1111 and the closed position are allowed to rotate and return to the closed position side. And a backflow prevention member 1116 urged by a spring.

When the game board 4 is attached to the main body frame 3, the front component member 1110 has a lower end opening between the outer rail 1111 and the inner rail 1112, and the launch rail 660 (see FIG. (See) is located on the extension line. Between the lower end of the outer rail 1111 and the upper end of the launch rail 660, a space that is widened in the left-right direction and downward is formed. By jumping over the space, it can be driven into the space between the outer rail 1111 and the inner rail 1112 from the lower end opening between the outer rail 1111 and the inner rail 1112. The game ball hit between the outer rail 1111 and the inner rail 1112 rolls upward along the outer rail 1111 according to the momentum, and the backflow prevention member 1116 pivotally supported on the upper end of the inner rail 1112 is installed. , By turning to the open position side against the biasing force, it is possible to enter the game area 1100.

Further, when a game ball is strongly hit in the hit ball launching device 650, the game ball rolled along the outer rail 1111 in the game area 1100 comes into contact with the stop portion 1114 provided at the end of the outer rail 1111. It is possible to forcibly change the rolling direction of the game ball by bringing the game ball into contact with this stop portion 1114, and the game ball continuously rolls from the outer rail 1111 to the inner rail 1113. It is possible to prevent movement. In addition, even if the game ball that has entered (struck) into the game area 1100 tries to return between the outer rail 1111 and the inner rail 1112, the backflow prevention member 1116 returns to the closed position by the biasing force before that. Thus, the backflow prevention member 1116 prevents the backflow of the game ball.

Further, when the game ball hit into the game area 1100 is not accepted by the various winning openings provided in the table unit 2000, it flows down to the lower end of the game area 1100, and the inner rail 1112 and the inner peripheral rail 1113. The out-port guide surface 1115 at the boundary of is guided to the out-port 1151 of the game panel 1150, and is discharged from the out-port 1151 to the lower rear side of the game board 4.

On the other hand, if the game ball fired from the hitting ball launching device 650 cannot cross the backflow prevention member 1116 at the tip of the inner rail 1112 and enter the game area 1100, the outer rail 1111 and the inner rail 1112 And a far space 626 formed between the upper end of the firing rail 660 and the lower end of the outer rail 1111 through the lower end opening between the outer rail 1111 and the inner rail 1112. 1) and is received by the foul ball inlet 542e (see FIG. 1) of the foul cover unit 540 attached to the door frame 5 located in the lower part of the foul space 626, and then the dish unit 300 receives it. It is adapted to be discharged to the lower plate 302 (see FIG. 7).

The outer rail 1111 in the front component member 1110 has a metal plate attached to its surface to improve the wear resistance due to the rolling of the game ball and to allow the game ball to roll smoothly. ing. Further, the stopper portion 1114 has an elastic body such as rubber or synthetic resin arranged on the surface thereof, and even if the game ball rolls vigorously along the outer rail 1111 and collides, the impact is mitigated. In addition to being able to play, it is possible to repel the game ball inward.

In addition, the front component 1110 is spaced apart in the vertical direction at the left end when viewed from the front, and a pair of positioning recesses 1119 that are recessed from the front to the rear and open at the left end, and are spaced apart at the right end when viewed in the vertical direction. A pair of game board stoppers 1120 that are arranged, a fixed recess 1121 that is arranged on the left side of the outer rail 1111 on the left side in front view, is opened downward, and is formed in an arc shape on the upper side and is recessed from the front side, and the lower end on the front side. A ball passage notch 1122 that is notched in a rectangular shape that extends upward from the lower end in the left-right direction is provided in the vicinity of the left end of the. The positioning recess 1119 of the front component member 1110 is fitted with a positioning member 956 (see FIG. 5) attached to the inside of the side crime prevention plate 950 in the main body frame 3 to provide a game board holding port 601 (see FIG. 5). The front end of the game board 4 inserted in) can be restricted from moving in the front-rear direction. Further, the game board stopper 1120 can be detachably locked to the game board locking portion of the main body frame base 600 of the main body frame 3, and the game board stopper 1120 is attached to the game board member. The front end of the game board 4 inserted into the game board holding port 601 of the main body frame 3 in front view can be restricted from moving in the front-rear direction by being locked to the stop portion.

Further, the fixed recess 1121 of the front component member 1110, in a state where the game board 4 is inserted into the game board holding port 601 of the body frame 3, a game board fixture 690 pivotally supported on the front surface of the body frame 3 (see FIG. 5). (See FIG. 5) is rotated clockwise in a front view, a fixing piece 690a (see FIG. 5) of the game board fixing tool 690 is inserted, and the game board fixing tool 690 causes the game board 4 to play. The lower end of the is restricted from moving forward. Further, the ball passage cutout 1122 of the front component member 1110 has a similar ball passage cutout 1152 formed at the same position of the game panel 1150, and the game board 4 is provided with a game board holding opening 601 of the main frame 3. The front end of the full tank branching unit 770 (see FIG. 5) is inserted into the ball passage cutouts 1122 and 1152 in the state of being inserted into.

A function display unit 1180, which will be described later, is arranged at the lower right of the front component 1110 when viewed from the front.

[5-2. Table unit]
Next, the table unit 2000 of the game board 4 will be described. The table unit 200 is an attacker unit 2100 that is disposed in the lower part of the game area 1100 and above the outlet 1151 and supported on the front surface of the game panel 1150, and an inner rail 1112 on the left side of the attacker unit 2100 in the game area 1100. A side winning opening member 2200 that is arranged along and is supported on the front surface of the game panel 1150, and a frame-shaped center accessory 2300 that is arranged substantially at the center of the game area 1100 and is supported by the game panel 1150. There is.

The table unit 2000 is adapted to be inserted from the front side into an opening 1158 formed at a position corresponding to the game area 1100 in the game panel 1150 and then attached to the front surface of the game panel 1150. The portion projecting to the front side of the game panel 1150 is located in the game area 1100. As a result, the table unit 2000 comes into contact with the game ball that has been driven into the game area 1100 at an appropriate position, and with the obstacle nail that is planted on the front surface of the game panel 1150, with respect to the movement of the game ball. It is possible to add a change. In addition, the table unit 2000 can decorate the inside of the game area 1100.

[5-2-1. Attacker unit]
Next, the attacker unit 2100 of the table unit 2000 will be described. The attacker unit 2100 has a plurality of inlets (winning holes) in which the game balls that are driven into the game area 1100 can be received. Specifically, a first starting opening 2101 arranged substantially at the center in the left-right direction, a rectangular big winning opening 2103 arranged on the right side of the first starting opening 2101 and extending greatly in the left-right direction, and a big winning opening 2103. General winning opening 2104 arranged on the left side of the above and on the right side of the first starting opening 2101, and a second starting opening device 2150 provided with a second starting opening 2102 arranged above the special winning opening 2103. .. The game balls received in the first starting opening 2101, the second starting opening 2102, the special winning opening 2103, and the general winning opening 2104 are guided from the front side to the rear side of the game panel 1150.

The second starting port device 2150 is, in addition to the second starting port 2102, a gate part 2150a through which a game ball can pass, a movable piece 2106 for opening and closing the second starting port 2102, and a movable piece after passing through the gate part 2150a. Since the 2106 is closed, the game ball discharging route 2150d that discharges the game ball that cannot enter the second starting opening 2102 toward the special winning opening 2103, and the movable piece 2106 is opened after passing through the gate portion 2150a. The game ball guide route 2150e capable of guiding the game ball to the second starting opening 2102 is provided. The gate unit 2150a is provided with a gate switch 2352 that detects a game ball passing through the gate unit 2150a.

The game ball is strongly hit in the hitting ball launching device 650, and the game ball rolled along the outer rail 1111 in the game area 1100 comes into contact with the stop portion 1114 provided at the end of the outer rail 1111 and the inner circumference. When a "right hit" in which the game ball rolls on the rail 1113 is performed, the second starting opening device 2150 is reached. Then, the game ball reaches the movable piece 2106 after passing through the gate portion 2150a of the second starting opening device 2150 as it is, and the movable piece 2106 is moved from the advanced position to the retracted position to open the second starting opening 2102. In the case where the game ball can enter the second starting port 2102 and enter the ball, the movable piece 2106 is moved from the retracted position to the advanced position to close the second starting port 2102. In some cases, the game ball drops toward the special winning opening 2103. The movable piece 2106 is driven by the starting opening solenoid 2105 according to the result of the ordinary lottery that is drawn based on the detection of the passage of the game ball by the gate switch 2352 of the gate unit 2150 (when the result of the ordinary lottery is “win”). It is designed to be opened and closed.

The first starting opening 2101 and the general winning opening 2104 of the attacker unit 2100 are open upward so that game balls can be always received (winning). The special winning opening 2103 of the attacker unit 2100 can be opened and closed by a horizontally elongated rectangular opening/closing member 2107 capable of closing the opening. The opening/closing member 2107 has a lower side rotatably supported, and in a substantially vertical state, it can close the special winning opening 2103 to make it difficult to receive a game ball, and the upper side moves to the front side. When it is turned to, the special winning opening 2103 can be opened to easily accept the game ball. The opening/closing member 2107 is in a state in which the large winning opening 2103 is closed in a normal gaming state, and is selected by the game ball being received (starting winning) in the first starting opening 2101 and the second starting opening 2102. According to the special lottery result (when the result of the special lottery is “big hit” or “small hit”), the attacker solenoid 2108 is driven to open and close.

Further, although not shown in detail, the attacker unit 2100 detects a second starting opening switch 2109 for detecting a game ball received in the second starting opening 2102 and a game ball received in the special winning opening 2103. A count switch 2110 is further provided, and the game ball detected by the second starting opening switch 2109 or the count switch 2110 is discharged onto the bottom wall portion of the substrate holder 1160. The back unit 3000 includes a first starting opening switch 3022 for detecting a game ball received in the first starting opening 2101, and a general winning opening switch 3020 for detecting a game ball received in the general winning opening 2104. ing.

Further, the attacker unit 2100 includes a game board side peripheral control MPU control target decorative board PM1 which is a control target directly controlled by a peripheral control MPU of a peripheral control board 4140 described later, and this game board side peripheral control MPU control target. A plurality of LEDs (decorative LEDs) provided on the decorative substrate PM1 are used for light emission decoration.

[5-2-2. Side winning mouth member]
Next, the side winning opening member 2200 of the front unit 2000 will be described. The side winning opening member 2200 is inserted from the front side with respect to the opening 1158 formed on the left side of the opening 1158 into which the attacker unit 2100 is inserted and fixed, in the lower part to the left of the center in the left-right direction of the game panel 1150. Above, it is fixed to the front surface of the game panel 1150, and is provided with a general winning opening 2201 along the outer periphery of the game area 1100. The general winning opening 2201 is open upward so that game balls can be accepted (winning) at all times. The game ball received in the general winning opening 2201 is guided by the front side to the rear side of the game panel 1150 and then detected by the general winning opening switch 3020 provided in the back unit 3000.

Further, the side winning opening member 2200 is arranged at a position where its left end portion is substantially in contact with the outer periphery of the game area 1100 at its upper left end portion, and a shelf portion inclined so as to become lower toward the right end portion. 2202 is provided, and the game balls that have flowed down along the outer circumference of the game area 1100 can be brought closer to the center side of the game area 1100 by the shelf portion 2202.

This side winning port member 2200 is formed so as to have a light-transmitting property as a whole, and is a game board side peripheral control MPU control which is a control target directly controlled by a peripheral control MPU of a peripheral control board 4140 described later. The target decorative board PM2 is provided, and the game board side peripheral control MPU control target decorative board PM2 is provided with a plurality of LEDs (decorative LEDs) for light emission decoration.

[5-2-3. Center goods]
Next, the center accessory 2300 of the table unit 2000 will be described. The center accessory 2300 is inserted from the front side into an opening 1158 that is formed so as to penetrate substantially the center of the game panel 1150, and then fixed to the front surface of the game panel 1150. It is formed in a frame shape with a size that occupies most of the area 1100, and the outer peripheral surface on the right side in front view has an arc shape so that a gap slightly larger than the outer diameter of the game ball is formed between the outer peripheral surface of the game area 1100 and the outer peripheral surface. Has been formed.

This center accessory 2300 is an upper shelf portion 2301 which is inclined to the left from the position slightly to the right of the center in the left-right direction on the outer peripheral surface on the upper side of the front wall portion located on the front surface of the game panel 1150 so as to decrease toward the left. And the game ball that has been driven into the upper portion of the game area 1100 flows down to the upper shelf portion 2301 through the left side of the center accessory 2300 (so-called "left hitting"). ), the game ball that has flowed down (entered) to the right of the upper shelf portion 2301 passes rightward of the center accessory 2300 and flows down to the bottom of the game area 1100 at once (so-called “right hit”).

Further, the center accessory 2300 has entered the warp entrance 2302 and the warp entrance 2302 in which a game ball flowing down the game area 1100 can enter the outer peripheral surface on the left side of the front wall portion located on the front side of the game panel 1150. A warp outlet (not shown) that discharges the game ball into the frame, and the game ball discharged from the warp outlet is rolled in the left-right direction and then discharged into the game area 1100 above the attacker unit 2100 to be a center character object. The stage 2310 formed on the upper surface of the lower side of the frame in 2300 is mainly provided.

Although the detailed illustration is omitted, the stage 2310 in the center accessory 2300 has a first stage to which the game ball discharged from the warp exit is supplied, and a game ball from the first stage arranged on the front side of the first stage. It is provided with a second stage which is supplied and is capable of releasing a game ball into the game area 1100. The stage 2310 is formed in a curved surface shape such that the center in the left-right direction is lowered. Further, a chance entrance 2313 into which a game ball can enter is formed on the rear side of the center in the left-right direction of the first stage. It is designed to be discharged from the outlet 2314 into the game area 1100. This chance exit 2314 is arranged immediately above the first starting opening 2101 in the attacker unit 2100, and the game ball released from the chance exit 2314 is accepted (wins) in the first starting opening 2101 with a high probability. It has become.

The stage 2310 in the center accessory 2300 is formed of a transparent member, and through this stage 2310, the ornamental body arranged below the stage 2310 in the back unit 3000 can be seen from the player side. Has become.

Further, the center accessory 2300 includes a game board side peripheral control MPU control target decorative board PM3 which is a control target directly controlled by a peripheral control MPU of a peripheral control board 4140, which will be described later, and this game board side peripheral control MPU control. Light emission decoration is performed by a plurality of LEDs (decorative LEDs) provided on the target decorative substrate PM3.

[5-3. Back unit]
Next, the back unit 3000 of the game board 4 will be described. The back unit 3000 is opened at the front and is attached and fixed to the rear surface of the game panel 1150, a back box 3001, a rotary light emitting device 3100 arranged on the upper side in the back box 3001, and a lower part in the back box 3001. It is provided with a model 3400 simulating the detonator arranged on the left side, and a model 3500 simulating the dynamite arranged on the lower right side in the back box 3001. Further, the back box 3001 is provided with a plurality of decorative members around the rotary light emitting device 3100, the model 3400 imitating the detonator, and the model 3500 imitating dynamite arranged on the lower right side in the back box 3001. .. The rotary light emitting device 3100 and the plurality of decorative members respectively include a game board side VDP control target decorative board which is a control target directly controlled by a sound source built-in VDP of a peripheral control board 4140, which will be described later. Light emission decoration is performed by a plurality of LEDs (decorative LEDs) provided on each of the VDP control target decorative substrates.

Further, the back unit 3000 is disposed above the center of the rear left side of the back box 3001 and accommodates the lamp drive board 4170, and below the lamp drive board box 3423 is the back box 3001. A motor drive board box 3430 accommodating a motor drive board 4180 arranged in the center of the rear left part, and a panel arranged below the motor drive board box 3430 and arranged downward from the center of the rear left part of the back box 3001. And a relay terminal board 4161.

In the present embodiment, the back unit 3000 can be visually recognized from the player side through the frame of the center accessory 2300 in the front unit 2000, and each unit 3100, 3400 formed into a predetermined shape, The concept of the pachinko gaming machine 1 can be characterized by 3500 or the like.

[5-3-1. Back box]
Next, the back box 3001 of the back unit 3000 will be described. The back box 3001 is formed in a box shape with the front side opened, and is provided with a plurality of flange-shaped fixing portions 3001a protruding outward at the front end, and on the rear side of the game panel 1150 via the fixing portions 3001a. It is supposed to be fixed. In addition to the rotating light emitting device 3100, the model 3400 imitating a detonator, and the model 3500 imitating dynamite, the back box 3001 is provided with a game board side effect display unit 1900 and the like on the open side of the back box 3001. A mounting portion for fixing by fixing is formed at an appropriate position. As a result, when the game board side liquid crystal display unit 1900 is fixed to the open side of the back box 3001, the rotary light emitting device 3100 provided in the back box 3001, the model 3400 imitating the detonator, and the model imitating dynamite. The existence of 3500 can be hidden. As described above, the back box 3001 is provided with a plurality of decorative members around the rotary light emitting device 3100, the model 3400 imitating the detonator, and the model 3500 imitating dynamite. These plurality of decoration members respectively include a game board side VDP control target decoration board which is a control target directly controlled by the sound source built-in VDP of the peripheral control board 4140, and each of these game board side VDP control target decoration boards. Is provided with a plurality of LEDs (decorative LEDs). Among the plurality of decorative members, the decorative member surrounding the periphery of the game board side liquid crystal display unit 1900 is arranged in front of the game board side liquid crystal display unit 1900, and serves as the center of the table unit 2000 described above. The structure is such that it fits within the frame of the object 2300 and does not interfere.

The game balls that have entered (winning (winning)) various winning openings provided on the game board 4 pass through a guide discharge passage (not shown) formed on the lower side of the back box 3001 and on the bottom wall of the substrate holder 1160. It is discharged, and is discharged below the game board 4 from the out-ball discharging portion 1161 of the substrate holder 1160. Further, a magnetic detection switch 3024 capable of detecting magnetism is provided near the position corresponding to the first start port 2101 of the attacker unit 2100 in the guide discharge passage.

[5-3-2. Rotating light emitting device]
Next, the rotary light emitting device 3100 will be described. The rotary light emitting device 3100 is attached and fixed to the upper side in the back box 3001. The rotary light emitting device 3100 is formed in a cylindrical shape along the vertical direction, and the lower end side is formed in a hemisphere. The part of the hemisphere is formed in a transparent shape, and a plurality of LEDs provided on the game board side VDP control target decoration substrate which is a control target directly controlled by a sound source built-in VDP of a peripheral control substrate 4140 to be described later. It is provided with a (decorative LED) and a reflection plate capable of reflecting light emitted from a plurality of LEDs (decorative LED) toward the front. In the rotary light emitting device 3100, a plurality of LEDs (ornamental LEDs) provided on the game board side VDP control target decorative board are mainly lit in red, and the order of lighting is adjusted to rotate the reflector. Instead, the rotation lighting mode can be performed. In other words, the rotary light-emitting mode by the rotary light-emitting device 3100 is not realized by rotating the reflecting plate by an electric drive source such as a motor, but a plurality of LEDs provided on the game board side VDP control target decorative substrate. It is realized by adjusting the order in which the (decorative LED) lights up.

[5-3-3. Various models]
Next, various models such as a model 3400 imitating a detonator and a model 3500 imitating dynamite will be described. The model 3400 imitating the detonator is for detonating the model 3500 imitating dynamite, and the button portion 3400a imitating the detonating button can move vertically. The button part 3400a is interlocked with the pressing operation part 405 of the operation unit 400 attached to the upper center of the dish unit 300 in the door frame 5 shown in FIG. The peripheral control board 4140 controls an electric drive source such as a solenoid or a motor (not shown) to move from the upper end position to the lower end position shown in FIG. Further, in the model 3500 imitating dynamite, the peripheral control board 4140 controls an electric drive source such as a solenoid or a motor (not shown) to form a plurality of types of rattling from the position shown in FIG. It is a mechanism that gives vibration.

[5-4. Performance display unit]
Next, the effect display unit 1900 of the game board 4 will be described with reference to FIGS. 10 to 12. FIG. 10 is a front exploded perspective view showing a configuration example when the effect display unit is viewed from the front side, and FIG. 11 is a rear exploded perspective view showing a configuration example when the effect display unit is viewed from the rear side, and FIG. [Fig. 8] is a sectional view showing an example of a sectional configuration of the effect display unit.

[5-4-1. Structure of performance display unit]
As shown in FIGS. 10 and 11, the effect display unit 1900 includes a frame 5000c formed in a box shape with an open rear, a main body 5000p housed in the frame 5000c, and a transparent back that closes the rear of the frame 5000c. It is composed of a lid 5000m. On the bottom plate of the frame 5000c, an opening 5000ca to be a display area of the effect display unit 1900 is formed.

Protrusions 5000cb are formed at the center of the left side surface and the center of the right side surface of the frame 5000c, respectively. The protruding portion 550cb is formed so that its rear portion is opened, and has a function as a wiring port for passing electric wiring through various electric members accommodated in the liquid crystal display unit 1900. In addition, on the left side surface and the right side surface of the frame 5000c, attachment holes for attaching the effect display unit 1900 to another member (a back box 3001 of the back unit 3000 of the game board 4) above and below the protruding portion 5000cb. Mounting protrusions are formed. Further, a plurality of ribs 5000cc each having a rectangular parallelepiped shape are formed on the inner side surface of the frame 5000c excluding the projecting portion 5000cb from the front rear surface side of the frame 5000c toward the rear at a predetermined interval, and the ribs 5000cc are structurally separated from each other. In addition to functioning as a reinforcing member, the main body 5000p housed inside the frame 5000c also has a function as a fixing auxiliary member that restricts movement in the vertical and horizontal directions.

The effect display unit 1900 includes a liquid crystal panel 5000e, a first light guide plate 5000d, a second light guide plate 5000f, and a third guide plate between the frame 5000c and the back cover 5000m from the frame 5000c to the back cover 5000m. The light plate 5000g, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k are sandwiched between the comb-shaped upper fixing member 5000a and the comb-shaped lower fixing member 5000b in this order. , A main body 5000p arranged in parallel is housed. Although detailed description will be given later, these light guide plates 5000d, 5000f, 5000g, 5000h, 5000i, and 5000k are, for example, by reflecting the light incident from the end faces such as the upper and lower surfaces inside and diffusing it. , A type of panel that emits uniform light from its surface.

The liquid crystal panel 5000e is a 12-inch (image size 800×600 dots) transparent rectangular flat plate-shaped member.

The liquid crystal panel 5000e will be described later in terms of the basic principle, but it is provided with two polarizing layers having their polarization directions at a predetermined angle (for example, a right angle), and a large number of polarizing layers are provided between these two polarizing layers. Is provided with a liquid crystal layer in which the liquid crystal molecules are aligned. The description of other structures such as the alignment film will be omitted. In the liquid crystal panel 5000e, for example, the amount of light transmission is controlled by controlling the arrangement state of the large number of liquid crystal molecules described above according to the control of the energization state by the peripheral control substrate 4140. In this liquid crystal panel 5000e, for example, the arrangement of the liquid crystal molecules in each of the transparent dots corresponding to the three primary colors changes in accordance with the energization state to a pair of transparent electrodes, and each of the plurality of dots In addition, it is possible to adjust the amount of light passing through one polarizing layer and passing through the other polarizing layer.

The first light guide plate 5000d is a flat transparent panel, and the light guide plate decoration substrate 5000d1 (one light source) is provided on the upper end surface of the transparent panel and is guided to the lower end surface of the transparent panel. A decorative board under the light board 5000d2 (the other light source) is provided.

The first light guide plate 5000d is a surface of the first light guide plate 5000d when viewed from the front when light is incident on the inside by lighting the light sources of the upper light guide plate decoration substrate 5000d1 and the lower light guide plate decoration substrate 5000d2. The whole (hereinafter, referred to as "planar shape") has a light emitting region 5000d4 as a surface light emitting source. In the first light guide plate 5000d, a large number of reflecting portions are processed and formed in the light emitting area 5000d4 on the back surface (back surface) of the transparent panel, so that the light emitting area 5000d4 serves as a surface emission source when the light source is turned on.

In the first light guide plate 5000d, the light (first light) output from the light guide plate decoration substrate 5000d1 is incident from the upper end surface thereof and travels inside the transparent panel, and as described above, the back surface of the transparent panel. The light is reflected by a large number of reflecting portions formed on the (rear surface), and is output mainly in the form of a plane from the front surface. On the other hand, the light (second light) output from the decorative substrate below the light guide plate 5000d2 is incident from the lower end surface thereof and is reflected by a large number of reflecting portions while advancing through the inside of the transparent panel, and mainly has a planar shape from the front side. Is output.

That is, the first light guide plate 5000d makes surface emission from the light emitting region 5000d4 in the front direction (direction of the opening 5000ca of the frame 5000c). As a result, the planar light surface-emitted by the first light guide plate 5000d enters the liquid crystal panel 5000e, and when viewed from the front, the liquid crystal panel 5000e is controlled according to the control mode of the liquid crystal panel 5000e. In, the image can be easily visually recognized in the inner portion of the planar shape.

The second light guide plate 5000f is a flat plate-shaped transparent panel, and the light guide plate decoration substrate 5000f1 (one light source) is provided on the upper end surface of the transparent panel and is guided to the lower end surface of the transparent panel. An under-light-board decoration substrate 5000f2 (the other light source) is provided.

The second light guide plate 5000f is formed into a predetermined number of circular shapes when viewed from the front when light is incident on the inside by lighting the light sources of the light guide plate upper decoration substrate 5000f1 and the light guide plate lower decoration substrate 5000f2. The non-luminous area 5000f3 and the light emission as a planar light emitting source formed in a planar shape excluding the non-luminous area 5000f3 and having a hole (hereinafter, referred to as "planar shape with a hole"). And an area 5000f4. In the second light guide plate 5000f, a large number of reflecting portions are formed on the back surface (rear surface) of the transparent panel in the light emitting area 5000f4, so that the light emitting area 5000f4 becomes a surface light emitting source when the light source is turned on. On the other hand, no emission part is formed in each of the predetermined number of non-light emitting regions 5000f3, and the plurality of non-light emitting regions 5000f3 do not serve as surface emitting sources at all when the light source is turned on.

In the second light guide plate 5000f, the light (first light) output from the light guide plate decoration substrate 5000f1 enters from the upper end surface thereof and travels inside the transparent panel, and as described above, the back surface of the transparent panel. The light is reflected by a large number of reflecting portions formed on the (rear surface), and is output mainly in the form of a plane with holes from the front. On the other hand, the light (second light) output from the decorative substrate below the light guide plate 5000f2 is incident from the lower end surface thereof and is reflected by a large number of reflecting portions while advancing through the inside of the transparent panel and is mainly a plane with holes from the front. It is output as a shape.

That is, the second light guide plate 5000f makes surface emission from the light emitting region 5000f4 in the front direction (direction of the opening 5000ca of the frame 5000c). As a result, the plane-shaped light having surface emission from the second light guide plate 5000f enters the liquid crystal panel 5000e, and when viewed from the front, the liquid crystal panel 5000e has a control mode. Accordingly, in the liquid crystal panel 5000e, the image can be easily visually recognized in the inner portion of the planar shape having the holes except the holes.

The third light guide plate 5000g is a flat transparent panel, and the light guide plate decorative substrate 5000g1 (one light source) is provided on the upper end surface of the transparent panel and is guided to the lower end surface of the transparent panel. A decorative substrate under the light plate 5000g2 (the other light source) is provided.

When the third light guide plate 5000g is viewed from the front when the light enters the interior of the second light guide plate 5000f when the light sources of the upper light guide plate decoration substrate 5000g1 and the lower light guide plate decoration substrate 5000g2 are turned on. In addition to the position corresponding to the light emitting region 5000f3, a predetermined number of circular non-light emitting regions 5000g3, and a planar shape excluding the non-light emitting region 5000g3 having a hole (hereinafter referred to as "a hole is opened"). And a light emitting region 5000g4 as a surface light emitting source. In the third light guide plate 5000g, a large number of reflecting portions are processed and formed in the light emitting area 5000g4 on the back surface (back surface) of the transparent panel, so that the light emitting area 5000g4 becomes a surface light emitting source when the light source is turned on. As a result, no emission part is formed in the plurality of non-light emitting areas 5000g3, and the non-light emitting areas 5000g3 do not serve as surface emitting sources at all when the light source is turned on.

In the third light guide plate 5000g, the light (first light) output from the decorative substrate on the light guide plate 5000g1 is incident from the upper end surface thereof and proceeds inside the transparent panel, and as described above, the rear surface of the transparent panel. The light is reflected by a large number of reflection portions formed on the (rear surface), and is output mainly in the form of a plane with holes from the front surface. On the other hand, the light (second light) output from the decorative substrate below the light guide plate 5000g2 is incident from the lower end surface thereof and is reflected by a large number of reflecting portions while advancing through the inside of the transparent panel, and is mainly a plane with holes from the front. It is output as a shape.

That is, the third light guide plate 5000g makes surface emission from the light emitting region 5000g4 in the front direction (direction of the opening 5000ca of the frame 5000c). As a result, the plane-shaped light having a hole that is surface-emitted by the third light guide plate 5000g enters the liquid crystal panel 5000e, and when viewed from the front, the liquid crystal panel 5000e has a control mode. Accordingly, in the liquid crystal panel 5000e, the image can be easily visually recognized in the inner portion of the planar shape having the holes except the holes.

The fourth light guide plate 5000h is a flat transparent panel, and the light guide plate decoration substrate 5000h1 (one light source) is provided on the upper end surface of the transparent panel and is guided to the lower end surface of the transparent panel. An under-light-board decorative substrate 5000h2 (the other light source) is provided.

The fourth light guide plate 5000h is configured such that the light sources of the upper light guide plate decoration substrate 5000h1 and the lower light guide plate decoration substrate 5000h2 turn on the light of the second light guide plate 5000f when viewed from the front when light enters the inside. In addition to the positions corresponding to the light emitting area 5000f3 and the non-light emitting area 5000g3 of the third light guide plate 5000g, a predetermined number of circular non-light emitting areas 5000h3 and a planar shape excluding the non-light emitting area 5000h3 are formed. And a light emitting region 5000h4 as a surface light emitting source formed in a shape with a hole (hereinafter, referred to as a "planar shape with a hole"). In the fourth light guide plate 5000h, a large number of reflecting portions are formed in the light emitting area 5000h4 on the back surface (back surface) of the transparent panel, so that the light emitting area 5000h4 serves as a surface light emitting source when the light source is turned on. Therefore, no emission part is formed in the plurality of non-light emitting areas 5000h3, and the non-light emitting areas 5000h3 do not serve as surface emitting sources at all due to the lighting of the light source.

In the fourth light guide plate 5000h, the light (first light) output from the light guide plate decoration substrate 5000h1 is incident from the upper end surface thereof and travels inside the transparent panel, and as described above, the back surface of the transparent panel. The light is reflected by a large number of reflection portions formed on the (rear surface), and is output mainly in the form of a plane with holes from the front surface. On the other hand, the light (second light) output from the decorative substrate below the light guide plate 5000g2 is incident from the lower end surface thereof and is reflected by a large number of reflecting portions while advancing through the inside of the transparent panel, and is mainly a plane with holes from the front. It is output as a shape.

That is, the fourth light guide plate 5000h makes surface emission from the light emitting region 5000h4 in the front direction (direction of the opening 5000ca of the frame 5000c). As a result, the planar light with the holes, which is surface-emitted by the fourth light guide plate 5000h, is incident on the liquid crystal panel 5000e, and when viewed from the front, the liquid crystal panel 5000e has a control mode. Accordingly, in the liquid crystal panel 5000e, the image can be easily visually recognized in the inner portion of the planar shape having the holes except the holes.

The fifth light guide plate 5000i is a flat transparent panel, and the light guide plate decoration substrate 5000i1 (one light source) is provided on the upper end surface of the transparent panel and is guided to the lower end surface of the transparent panel. An under-light-board decoration substrate 5000i2 (the other light source) is provided.

The fifth light guide plate 5000i is formed into a plurality of polygonal shapes when viewed from the front when light is incident on the inside by lighting the light sources of the upper light guide plate decorative substrate 5000i1 and the lower light guide plate decorative substrate 5000i2. A non-luminous area 5000i3 and a planar shape excluding the non-luminous area 5000i3 having a polygonal hole (hereinafter, a plurality of planar light emitting sources formed in a "planar shape having a polygonal hole"). In the fifth light guide plate 5000i, a large number of reflective portions are formed in the plurality of light emitting areas 5000i4 on the back surface (back surface) of the transparent panel in the fifth light guide plate 5000i. While the plurality of light emitting areas 5000i4 serve as surface emission sources by lighting, no emission part is formed in the plurality of non-light emitting areas 5000i3, and the non-light emitting areas 5000i3 do not serve as surface emitting sources at all by lighting the light sources.

In the fifth light guide plate 5000i, the light (first light) output from the light guide plate decoration substrate 5000i1 is incident from the upper end surface thereof and travels inside the transparent panel, and as described above, the back surface of the transparent panel. The light is reflected by a large number of reflecting portions formed on the (rear surface), and is output in the form of a plane having polygonal holes opened mainly from the front surface. On the other hand, the light (second light) output from the light guide plate lower decorative substrate 5000i2 is incident from the lower end surface thereof and is reflected by a large number of reflecting portions while advancing through the inside of the transparent panel. It is output as an open planar shape.

That is, the fifth light guide plate 5000i surface-emites from the plurality of light emitting regions 5000i4 in the front direction (direction of the opening 5000ca of the frame 5000c). As a result, the planar light, which has surface emission from the fifth light guide plate 5000i and has polygonal holes, is incident on the liquid crystal panel 5000e. According to the control mode, in the liquid crystal panel 5000e, an image can be easily visually recognized in each of the inner portions of the planar shape having the polygonal holes opened, excluding the polygonal holes.

The sixth light guide plate 5000k is a flat plate-shaped transparent panel, and the light guide plate decoration substrate 5000k1 (one light source) is provided on the upper end surface of the transparent panel and is guided to the lower end surface of the transparent panel. An under-light-board decoration substrate 5000k2 (the other light source) is provided.

The sixth light guide plate 5000k is the upper side of the sixth light guide plate 5000k when viewed from the front when light is incident on the inside by lighting the light sources of the upper light guide plate decoration substrate 5000k1 and the lower light guide plate decoration substrate 5000k2. To the lower side, the non-light emitting region 5000k3 is formed in a thick band shape, and the non-light emitting region 5000k3 is formed in a flat band shape excluding the non-light emitting region 5000k3 (hereinafter, referred to as "planar thin band shape"). And a light emitting region 5000k4 as a surface light emitting source. In the sixth light guide plate 5000k, a large number of reflecting portions are formed in the light emitting area 5000k4 on the back surface (back surface) of the transparent panel, so that the light emitting area 5000k4 becomes a surface light emitting source when the light source is turned on. As a result, no emission part is formed in the non-light emitting area 5000k3, and the non-light emitting area 5000k3 does not serve as a surface emission source when the light source is turned on.

In the sixth light guide plate 5000k, the light (first light) output from the light guide plate decoration substrate 5000k1 is incident from the upper end surface thereof and travels inside the transparent panel, and as described above, the back surface of the transparent panel. The light is reflected by a large number of reflecting portions formed on the (rear surface), and is output in the form of a flat strip mainly from the front surface. On the other hand, the light (second light) output from the decorative substrate below the light guide plate 5000k2 is incident from the lower end surface thereof and is reflected by a large number of reflecting portions while advancing through the inside of the transparent panel, mainly from the front side into a flat strip shape. Will be output.

That is, the sixth light guide plate 5000k emits surface light in the front direction (direction of the opening 5000ca of the frame 5000c) from the light emitting region 5000k4. As a result, the flat strip-shaped light surface-emitted by the sixth light guide plate 5000k is incident on the liquid crystal panel 5000e, and when viewed from the front, depending on the control mode of the liquid crystal panel 5000e. In the liquid crystal panel 5000e, the image can be easily visually recognized in the inner portion of the flat strip shape.

As described above, the first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000g, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the first light guide plate 5000d arranged in order from the front side. Although the liquid crystal panel 5000e has a rectangular shape, depending on which of the light guide plates 5000k of No. 6 the surface light emission is performed, as a completely different existence from the liquid crystal panel 5000e having another physical shape, The display part where the image is displayed appears.

[5-4-2. Cross-sectional structure of performance display unit]
The structure of the effect display unit 1900 will be described in more detail. As shown in FIG. 12, the effect display unit 1900 has the above-described inside of the effect display unit 1900 formed by attaching the back cover 5000m to the frame 5000c. Thus, the liquid crystal panel 5000e, the first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000g, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k are They are arranged and housed in parallel with each other. It should be noted that the opening portion 5000ca which is a display area of the effect display unit 1900 formed on the front surface of the frame 5000c is formed in a rectangular shape smaller than the outer periphery of the rectangular liquid crystal panel 5000e of the liquid crystal panel 5000e.

The comb-like upper fixing member 5000a and the comb-like lower fixing member 5000b are formed in the same shape, and a plurality of comb teeth are formed at a predetermined distance from each other so that a groove is formed between the comb teeth. Each of them is formed, and each of the protrusions is formed toward the opposing wall of each groove. The liquid crystal panel 5000e, the first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000g, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k are comb-shaped upper side. When sandwiched by the fixing member 5000a and the comb-shaped lower fixing member 5000b, the liquid crystal panel 5000e, the first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000g, the fourth light guide plate 5000h, The upper end surface and the lower end surface of the fifth light guide plate 5000i and the sixth light guide plate 5000k are respectively locked to the protrusions formed on the walls facing each other.

Each groove depth into which the first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000g, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k are inserted. The first light guide plate 5000d, the second light guide plate 5000f, and the third light guide plate are provided on the side, that is, on the root side of the comb teeth of the comb-shaped upper fixing member 5000a and the root side of the comb teeth of the comb-shaped lower fixing member 5000b. A substrate accommodating space for accommodating a substrate is formed to emit light to the upper end surface and the lower end surface of the light plate 5000g, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k. , The first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000g, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k. They are in communication with each other.

More specifically, a large number of LEDs 5000d6 (in the present embodiment, white LEDs are adopted as the LEDs 5000d6) in the substrate housing space 5000d5 of the comb-shaped upper fixing member 5000a into which the first light guide plate 5000d is inserted. Although the decorative substrate on the light guide plate 5000d1 on which is mounted is housed, and the illustration is omitted in FIG. 12, the board housing space of the comb-shaped lower fixing member 5000b into which the first light guide plate 5000d is inserted. The light guide plate lower decorative substrate 5000d2 on which a large number of LEDs 5000d6 are mounted is housed in the 5000d5. The light guide plate upper decorative substrate 5000d1 and the light guide plate lower decorative substrate 5000d2 are formed in the substrate accommodation space 5000d5 and the comb shape of the comb upper fixing member 5000a from the respective side end surfaces of the comb upper fixing member 5000a and the comb lower fixing member 5000b. Each of the LEDs 5000d6 outputs light in accordance with the energization state under the control of the peripheral control board 4140, and is inserted into the board housing space 5000d5 of the lower fixing member 5000b.

These lights are reflected through the inside of the first light guide plate 5000d and output from the planar light emitting region 5000d4 toward the liquid crystal panel 5000e as described above. The light reflected in this way allows the user's eyes to see an image on the inner portion of the planar shape through the liquid crystal panel 5000e according to the control mode of the liquid crystal panel 5000e.

The first light guide plate 5000d functions as a transparent panel when the LEDs 5000d6 provided on the upper light guide plate decoration substrate 5000d1 and the lower light guide plate decoration substrate 5000d2 do not emit light (normal state). Since it is configured, the user can visually recognize the rear of the first light guide plate 5000d through the first light guide plate 5000d.

A large number of LEDs 5000f6 (white LEDs are adopted as the LEDs 5000f6 in the present embodiment) are mounted in the substrate housing space 5000f5 of the comb-shaped upper fixing member 5000a into which the second light guide plate 5000f is inserted. The upper decorative substrate 5000f1 (one light source) is accommodated, and although not shown in FIG. 12, the substrate accommodating space 5000f5 of the comb-shaped lower fixing member 5000b into which the second light guide plate 5000f is inserted. Contains a light guide plate lower decorative substrate 5000f2 (the other light source) on which a large number of LEDs are mounted. The light guide plate upper decorative substrate 5000f1 and the light guide plate lower decorative substrate 5000f2 are formed into a comb-shaped upper fixing member 5000a and a comb-shaped upper fixing member 5000a from the side end surfaces of the comb upper fixing member 5000a and the comb lower fixing member 5000b, respectively. Each of the LEDs 5000f6 outputs light in accordance with the energization state under the control of the peripheral control board 4140, and is inserted into the board housing space 5000f5 of the lower fixing member 5000b.

These lights are reflected through the inside of the second light guide plate 5000f, and are output from the planar light emitting region 5000f4 with holes as described above toward the liquid crystal panel 5000e. Due to the light reflected in this way, an image is visually recognized by the user's eyes through the liquid crystal panel 5000e in the inner portion of the planar shape with the holes except the holes, depending on the control mode of the liquid crystal panel 5000e. Like

The second light guide plate 5000f functions as a transparent panel when the LEDs 5000f6 provided on the upper light guide plate decoration substrate 5000f1 and the lower light guide plate decoration substrate 5000f2 are not emitting light (normal state). Since it is configured, the rear of the second light guide plate 5000f can be visually recognized by the user's eyes through the second light guide plate 5000f.

A large number of LEDs 5000g6 (white LEDs are adopted as the LEDs 5000g6 in the present embodiment) are mounted in the substrate housing space 5000g5 of the comb-shaped upper fixing member 5000a into which the third light guide plate 5000g is inserted. The upper decorative substrate 5000g1 (one light source) is housed, and although not shown in FIG. 12, the substrate housing space 5000g5 of the comb-shaped lower fixing member 5000b into which the third light guide plate 5000g is inserted. Contains a light guide plate lower decorative substrate 5000g2 (the other light source) on which a large number of LEDs are mounted. The light guide plate upper decorative substrate 5000g1 and the light guide plate lower decorative substrate 5000g2 are arranged in a comb-shaped upper fixing member 5000a and a comb-shaped upper fixing member 5000a from the side end surfaces of the comb upper fixing member 5000a and the comb lower fixing member 5000b, respectively. Each of the LEDs 5000g6 outputs light in accordance with the energization state under the control of the peripheral control board 4140, and is inserted into the board housing space 5000g5 of the lower fixing member 5000b.

These lights are reflected through the inside of the third light guide plate 5000g, and are output from the plane-shaped light emitting region 5000g4 having holes as described above toward the liquid crystal panel 5000e. Due to the light reflected in this way, an image is visually recognized by the user's eyes through the liquid crystal panel 5000e in the inner part of the planar shape with the holes except the holes, depending on the control mode of the liquid crystal panel 5000e. Become so.

The third light guide plate 5000g functions as a transparent panel when the LEDs 5000g6 provided on the upper light guide plate decoration substrate 5000g1 and the lower light guide plate decoration substrate 5000g2 are not emitting light (normal state). Since it is configured, the user can visually recognize the rear of the third light guide plate 5000g through the third light guide plate 5000g.

A large number of LEDs 5000h6 (white LEDs are adopted as the LEDs 5000h6 in the present embodiment) are mounted in the substrate housing space 5000h5 of the comb-shaped upper fixing member 5000a into which the fourth light guide plate 5000h is inserted. The upper decorative substrate 5000h1 (one light source) is accommodated, and although not shown in FIG. 12, the substrate accommodation space 5000h5 of the comb-shaped lower fixing member 5000b into which the fourth light guide plate 5000h is inserted. Contains a light guide plate lower decorative substrate 5000h2 (the other light source) on which a large number of LEDs are mounted. The light guide plate upper decorative substrate 5000h1 and the light guide plate lower decorative substrate 5000h2 are formed from the side end surfaces of the comb-shaped upper fixing member 5000a and the comb-shaped lower fixing member 5000b, respectively, to the substrate accommodation space 5000h5 and the comb-shaped upper fixing member 5000a. Each of the LEDs 5000h6 outputs light in accordance with the energization state under the control of the peripheral control board 4140, and is inserted into the board housing space 5000h5 of the lower fixing member 5000b.

These lights are reflected through the inside of the fourth light guide plate 5000h, and are output from the planar light emitting region 5000h4 having holes as described above toward the liquid crystal panel 5000e. Due to the light reflected in this way, an image is visually recognized by the user's eyes through the liquid crystal panel 5000e in the inner part of the planar shape with the holes except the holes, depending on the control mode of the liquid crystal panel 5000e. Become so.

The fourth light guide plate 5000h functions as a transparent panel when the LEDs 5000h6 provided on the upper light guide plate decoration substrate 5000h1 and the lower light guide plate decoration substrate 5000h2 are not emitting light (normal state). Since it is configured, the user can visually recognize the rear of the fourth light guide plate 5000h through the fourth light guide plate 5000h.

A large number of LEDs 5000i6 (in this embodiment, white LEDs are used as the LEDs 5000i6) are mounted in the substrate housing space 5000i5 of the comb-shaped upper fixing member 5000a into which the fifth light guide plate 5000i is inserted. The upper decorative substrate 5000i1 (one light source) is housed, and although not shown in FIG. 12, the substrate housing space 5000i5 of the comb-shaped lower fixing member 5000b into which the fifth light guide plate 5000i is inserted. Contains a light guide plate lower decorative substrate 5000i2 (the other light source) on which a large number of LEDs are mounted. The light guide plate upper decorative substrate 5000i1 and the light guide plate lower decorative substrate 5000i2 are formed from the side end surfaces of the comb-shaped upper fixing member 5000a and the comb-shaped lower fixing member 5000b, respectively, to the substrate accommodation space 5000i5 and the comb-shaped upper fixing member 5000a. Each of the LEDs 5000i6 outputs light in accordance with the energization state under the control of the peripheral control board 4140, which is inserted into the board housing space 5000i5 of the lower fixing member 5000b.

These lights are reflected through the inside of the fifth light guide plate 5000i and are output toward the liquid crystal panel 5000e from the planar light emitting region 5000i4 having the polygonal holes as described above. Due to the light reflected in this way, depending on the control mode of the liquid crystal panel 5000e, the user's eyes can see through the liquid crystal panel 5000e an image on the inner part of the planar shape with the polygonal hole except the hole. Will be visible respectively.

The fifth light guide plate 5000i is a transparent panel when the LEDs 5000i6 provided on the light guide plate upper decorative substrate 5000i1 and the light guide plate lower decorative substrate 5000i2 are not emitting light (normal state). Since it is configured, the user can visually recognize the rear of the fifth light guide plate 5000i through the fifth light guide plate 5000i.

A large number of LEDs 5000k6 (in this embodiment, white LEDs are used as the LEDs 5000k6) are mounted in the substrate housing space 5000k5 of the comb-shaped upper fixing member 5000a into which the sixth light guide plate 5000k is inserted. The upper decorative substrate 5000k1 (one light source) is housed, and although not shown in FIG. 12, the substrate housing space 5000k5 of the comb-shaped lower fixing member 5000b into which the sixth light guide plate 5000k is inserted. Contains a light guide plate lower decorative substrate 5000k2 (the other light source) on which a large number of LEDs are mounted. The light guide plate upper decorative substrate 5000k1 and the light guide plate lower decorative substrate 5000k2 are formed from the side end surfaces of the comb-shaped upper fixing member 5000a and the comb-shaped lower fixing member 5000b, respectively, to the substrate accommodation space 5000k5 and the comb-shaped upper fixing member 5000a. Each of the LEDs 5000k6 outputs light in accordance with the energization state under the control of the peripheral control board 4140, which is inserted into the board housing space 5000k5 of the lower fixing member 5000b.

These lights are reflected through the inside of the sixth light guide plate 5000k, and are output from the flat strip-shaped light emitting region 5000k4 toward the liquid crystal panel 5000e as described above. The light reflected in this way allows the user's eyes to visually recognize an image on the inner portion of the flat strip shape through the liquid crystal panel 5000e according to the control mode of the liquid crystal panel 5000e.

The sixth light guide plate 5000k functions as a transparent panel when the LEDs 5000k6 provided on the upper light guide plate decoration substrate 5000k1 and the lower light guide plate decoration substrate 5000k2 are not emitting light (normal state). Since it is configured, the user can visually recognize the rear of the sixth light guide plate 5000k through the sixth light guide plate 5000k.

In addition, in the present embodiment, in the display area of the transmissive liquid crystal panel 5000e, in the area where no image is displayed on the liquid crystal panel 5000e, the liquid crystal panel 5000e is transmissive, so the user What is present behind the transmissive liquid crystal panel 5000e corresponding to this area, that is, behind the effect display unit 1900 can be seen.

Here, the principle of the liquid crystal panel 5000e will be briefly described. The liquid crystal shutter is configured by enclosing liquid crystal between two glass substrates formed of an alignment film, a transparent electrode, a polarizing plate, etc., so that a voltage can be applied between the glass substrates of the liquid crystal shutter. It has become. More specifically, the liquid crystal shutter includes a pixel driving side substrate module, a counter electrode side basic module, and a liquid crystal molecular layer (liquid crystal layer). The pixel drive side substrate module has a polarizing plate, a glass substrate, a transparent conductive film (pixel electrode, drive transistor), and an alignment film in order from the outside (the light incident side, that is, the side where the light guide plate as a backlight is arranged). It is stacked. In the counter electrode side basic module, a polarizing plate, a glass substrate, a color filter, a transparent electrode film (counter electrode) and an alignment film are laminated in order from the outside (the side opposite to the outside in the pixel driving side substrate module). The liquid crystal molecular layer is arranged between the pixel driving side substrate module and the counter electrode side basic module. That is, the polarizing plate, the glass substrate, the transparent electrode film, and the alignment film form a pair.

The transparent conductive film is for applying a voltage between the pixel electrode and the counter electrode (that is, between the two glass substrates), and is made of a transparent electrode material such as ITO so as not to hinder display. There is.

The alignment film is a film for aligning liquid crystal molecules in a certain direction, and is made of a polyimide resin or the like on the transparent conductive film.

The polarizing plate is an optical film that allows only light oscillating in the same direction as the transmission axis to pass from natural light emitted from a light guide plate as a backlight.

The driving transistor is one transistor for each pixel of the pixel driving module, and controls the brightness of the liquid crystal shutter.

The color filter is a filter in which red, green, and blue, which are the three primary colors of light, are arranged for each pixel for image colorization.

The liquid crystal molecules in the liquid crystal molecule layer have the property of changing their arrangement when a voltage is applied between the two glass substrates. The amount of light transmitted is adjusted according to the voltage applied at this time.

It should be noted that it is configured so that a voltage can be applied corresponding to each of the three primary colors of light, red, green, and blue, and when a voltage is applied to red, the alignment of liquid crystal molecules corresponding thereto is When a voltage is applied to green, the arrangement of the liquid crystal molecules changes accordingly, and when a voltage is applied to blue, the arrangement of the liquid crystal molecules changes accordingly. The degree of change in the arrangement of liquid crystal molecules varies depending on the magnitude of the voltage, and by adjusting the voltage, the transmission amount of the liquid crystal shutter for light of red, green, or blue can be changed. it can. In this way, the liquid crystal shutter can add any color to the transmitted light using the three primary colors.

Regarding the alignment of the liquid crystal molecules, there are a normally white mode and a normally black mode, but in the present embodiment, the normally black mode is adopted. The normally white mode is a structure in which a liquid crystal is sandwiched by polarizing plates, where light passes through when no voltage is applied and white is displayed on the screen, while light is emitted when voltage is applied. It is a mode in which black is displayed on the screen when the power is cut off. The normally black mode is a structure in which a liquid crystal molecular layer is sandwiched by polarizing plates, and when voltage is not applied, light is blocked and black is displayed on the screen, whereas voltage is applied. Sometimes it refers to a mode in which light passes and white is displayed on the screen.

The liquid crystal panel 5000e has a large number of pixels arranged by liquid crystal shutters. A pixel is a minimum unit point having color information. In one pixel, when light of all colors of red, green and blue is transmitted through the liquid crystal shutter with the same transmission amount, it becomes white (transparent). If only one color of red light per pixel passes through the liquid crystal shutter, it becomes red. Similarly, when one pixel transmits only green color light through the liquid crystal shutter, it becomes green, and when one pixel transmits only blue color light through the liquid crystal shutter, it becomes blue. Further, when light of a color obtained by changing the transmission amount of each of red, green, and blue in one pixel is transmitted through the liquid crystal shutter, a mixed color of these lights is obtained. Then, a desired image can be displayed on the liquid crystal panel 5000e by coloring each pixel forming the liquid crystal panel 5000e.

The peripheral control board 4140 controls the transmission type liquid crystal panel 5000e in the effect display unit 1900 to display an effect image as a moving image according to the progress of the game, and also controls the first light guide plate 5000d and the second light guide plate 5000d. The light guide plate 5000f, the third light guide plate 5000g, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k are controlled so as to emit surface light. According to the above-mentioned principle of the liquid crystal panel 5000e, the transmissive liquid crystal panel 5000e in the effect display unit 1900 has an effect image as a moving image in accordance with the progress of the game in the area emitted from the light guide plate as the backlight. Can be seen, and the view behind is blocked. On the other hand, with respect to the non-light-emission area that does not emit light from the light guide plate as the backlight, the player cannot view the effect image regardless of whether or not the effect image is controlled to be displayed in this area ( However, it may be visible when light from the other passes through the liquid crystal shutter), and if a voltage is applied, the player can visually recognize the rear through the non-light emitting area.

In addition, you may comprise so that the liquid crystal shutter may be arrange|positioned and accommodated in the back surface of each light guide plate in the above-mentioned effect display unit 1900, respectively. More specifically, between the frame 5000c and the back cover 5000m, the liquid crystal panel 5000e, the first light guide plate 5000d, the liquid crystal shutter A, and the second light guide plate 5000f are provided from the frame 5000c to the back cover 5000m. The order of the liquid crystal shutter B, the third light guide plate 5000g, the liquid crystal shutter C, the fourth light guide plate 5000h, the liquid crystal shutter D, the fifth light guide plate 5000i, the liquid crystal shutter E, the sixth light guide plate 5000k, and the liquid crystal shutter F. Then, the main body 5000p arranged in parallel is housed by being sandwiched between the comb-like upper fixing member 5000a and the comb-like lower fixing member 5000b.

The liquid crystal shutters A to F are in the form of a sheet, for example, a transparent polymer film in which nematic liquid crystal droplets (called capsules) are dispersed is sandwiched between two sheets of polyester film with a transparent conductive film. When no voltage is applied, the liquid crystals represented by rod-shaped molecules are aligned along the inner wall of the capsule, and the incident light is caused by the difference in the refractive index of the polymer and the liquid crystal and the birefringence of the liquid crystal, and the surface of the capsule. And refracted inside, and as a result, the light cannot travel straight and is scattered, and the liquid crystal shutters A to F look opaque (diffused state). When a voltage is applied, the liquid crystal molecules try to line up in parallel with the direction in which the voltage is applied, and by arranging them perpendicularly to the electrodes, if the liquid crystal has a refractive index that matches that of the polymer, the capsule The state is equivalent to the absence of an interface, and as a result, light does not scatter and goes straight, and the liquid crystal shutters A to F appear transparent (non-diffused state). Switching control of the liquid crystal shutters A to F between transparent and opaque is performed by, for example, a peripheral control board 4140 (a peripheral control MPU in a peripheral control unit described later).

The liquid crystal shutter A is arranged behind the first light guide plate 5000d along the rear surface of the first light guide plate 5000d, and corresponds to the above-described planar shape behind the light emitting region 5000d4 of the first light guide plate 5000d. Composed of segments. In the case of the liquid crystal shutter A, when the light emitting region 5000d4 is caused to emit light, a voltage is not applied to the segment portion and a diffusion state (milky white) is set. In this case, a part of the light is reflected by the milky white segment portion and is directed forward. This also illuminates the inside of the above-mentioned planar shape of the liquid crystal panel 5000e from behind. Therefore, the image on the liquid crystal panel 5000e can be seen more clearly. On the other hand, when the light emitting region 5000d4 is not made to emit light, a voltage is applied to the segment portion to set the non-diffused state (transparent) in which the transmitted light is not diffused. Further, when any one of the second light guide plate 5000f to the sixth light guide plate 5000k is used as the surface light emitting source, the voltage is always applied to the segment portion on the liquid crystal shutter A side. The entire liquid crystal shutter A is controlled to be in a non-diffusing state (transparent).

The liquid crystal shutter B is arranged behind the second light guide plate 5000f so as to follow the rear surface of the second light guide plate 5000f, and is a flat surface having the above-mentioned hole behind the light emitting region 5000d4 of the second light guide plate 5000f. It is composed of a segment corresponding to the shape and another segment corresponding to the other region. In the case of the liquid crystal shutter B, when the light emitting region 5000f4 is caused to emit light, a voltage is not applied to the segment portion corresponding to the planar shape with holes, and a diffusion state (milky white) is obtained. In this case, a part of the light is reflected by the milky white segment portion and is directed forward. This also illuminates the inside of the liquid crystal panel 5000e, which has the above-described hole and has the planar shape, from the rear side, and the boundary between the light emitting region 5000f4 and other parts becomes clear. Therefore, the image on the liquid crystal panel 5000e can be seen more clearly. On the other hand, when the light emitting region 5000f4 is not made to emit light, a voltage is applied to the segment portion corresponding to the planar shape having the holes to bring the transmitted light into a non-diffused state (transparent). The other segments are controlled so that a voltage is always applied, and are in a non-diffused state (transparent). When any one of the first light guide plate 5000d, the third light guide plate 5000g to the sixth light guide plate 5000k is used as a surface light emission source, a flat surface with holes on the liquid crystal shutter B side. The liquid crystal shutter B is set to a non-diffused state (transparent) by controlling the voltage to be constantly applied to the segment portion corresponding to the shape and the other segment.

The liquid crystal shutter C is arranged behind the third light guide plate 5000g so as to follow the rear surface of the third light guide plate 5000g, and has a plane with the above-mentioned hole behind the light emitting region 5000g4 of the third light guide plate 5000g. It is composed of a segment corresponding to the shape and another segment corresponding to the other region. In the case of the liquid crystal shutter C, when the light emitting region 5000g4 is caused to emit light, a voltage is not applied to the segment portion corresponding to the planar shape with holes, and the diffusion state (milky white) is obtained. In this case, a part of the light is reflected by the milky white segment portion and is directed forward. This also illuminates the inside of the liquid crystal panel 5000e, which has the above-described hole and has a planar shape, from the rear side, and the boundary between the light emitting region 5000g4 and other portions is clear. Therefore, the image on the liquid crystal panel 5000e can be seen more clearly. On the other hand, when the light emitting region 5000g4 is not made to emit light, a voltage is applied to the segment portion corresponding to the planar shape with the holes so that the transmitted light is not diffused (transparent). The other segments are controlled so that a voltage is always applied, and are in a non-diffused state (transparent). Further, when any one of the first light guide plate 5000d, the second light guide plate 5000f, and the fourth light guide plate 5000h to the sixth light guide plate 5000k is used as the surface emission source, the liquid crystal shutter C side. In, the voltage is always applied to the segment portion corresponding to the planar shape with holes and the other segments, and the entire liquid crystal shutter C is set to the non-diffused state (transparent).

The liquid crystal shutter D is disposed behind the fourth light guide plate 5000h along the rear surface of the fourth light guide plate 5000h, and has a plane with the above-mentioned hole behind the light emitting region 5000h4 of the fourth light guide plate 5000h. It is composed of a segment corresponding to the shape and another segment corresponding to the other region. In the case of the liquid crystal shutter D, when the light emitting region 5000h4 is caused to emit light, a voltage is not applied to the segment portion corresponding to the planar shape with holes, and a diffusion state (milky white) is obtained. In this case, a part of the light is reflected by the milky white segment portion and is directed forward. This also illuminates the inner portion of the liquid crystal panel 5000e, which has the above-described hole and has a planar shape, from the rear side, and the boundary between the light emitting region 5000h4 and other portions becomes clear. Therefore, the image on the liquid crystal panel 5000e can be seen more clearly. On the other hand, when the light emitting region 5000h4 is not made to emit light, a voltage is applied to the segment portion corresponding to the planar shape with the holes so that the transmitted light is not diffused (transparent). The other segments are controlled so that a voltage is always applied, and are in a non-diffused state (transparent). When any one of the first light guide plate 5000d to the third light guide plate 5000g, the fifth light guide plate 5000i, and the sixth light guide plate 5000k is used as the surface light emission source, the liquid crystal shutter D side. In, the voltage is always applied to the segment portion corresponding to the planar shape with holes and the other segments, and the entire liquid crystal shutter D is set to the non-diffused state (transparent).

The liquid crystal shutter E is disposed behind the fifth light guide plate 5000i along the rear surface of the fifth light guide plate 5000i, and the polygonal hole described above is formed behind the light emitting region 5000i4 of the fifth light guide plate 5000i. It is composed of a segment corresponding to the open planar shape and another segment corresponding to the other region. In the case of the liquid crystal shutter E, when the light emitting region 5000i4 is caused to emit light, a voltage is not applied to the segment portion corresponding to the planar shape having the polygonal hole, and a diffusion state (milky white) is obtained. In this case, a part of the light is reflected by the milky white segment portion and is directed forward. This also illuminates the inside of the planar shape of the liquid crystal panel 5000e, in which the above-described polygonal hole is opened, from the rear side, and the boundary between the light emitting region 5000i4 and other parts becomes clear. Therefore, the image on the liquid crystal panel 5000e can be seen more clearly. On the other hand, when the light emitting region 5000i4 is not made to emit light, a voltage is applied to the segment portion corresponding to the planar shape in which the polygonal hole is opened so that the transmitted light is not diffused (transparent). The other segments are controlled so that a voltage is always applied, and are in a non-diffused state (transparent). Further, when any one of the first light guide plate 5000d to the fourth light guide plate 5000h and the sixth light guide plate 5000k is used as a surface emission source, a polygonal hole on the liquid crystal shutter E side is formed. A voltage is constantly applied to each of the segment portion corresponding to the open planar shape and the other segments, and the entire liquid crystal shutter E is set to the non-diffused state (transparent).

The liquid crystal shutter F is arranged behind the sixth light guide plate 5000k along the rear surface of the sixth light guide plate 5000k, and has the above-described flat strip shape behind the light emitting region 5000k4 of the sixth light guide plate 5000k. It is composed of a corresponding segment and other segments corresponding to other areas. In the case of the liquid crystal shutter F, when the light emitting region 5000k4 is caused to emit light, a voltage is not applied to the segment portion corresponding to the flat strip shape, and a diffusion state (milky white) is obtained. In this case, a part of the light is reflected by the milky white segment portion and is directed forward. This also illuminates the inner portion of the liquid crystal panel 5000e having the above-mentioned flat strip shape from behind, and the boundary between the light emitting region 5000k4 and other portions becomes clear. Therefore, the image on the liquid crystal panel 5000e can be seen more clearly. On the other hand, when the light emitting region 5000k4 is not made to emit light, a voltage is applied to the segment portion corresponding to the flat strip shape so that the transmitted light is not diffused (transparent). The other segments are controlled so that a voltage is always applied, and are in a non-diffused state (transparent). Further, when any one of the first light guide plate 5000d to the fifth light guide plate 5000i is used as a surface emission source, a segment portion corresponding to the flat strip shape on the liquid crystal shutter F side and other The voltage is controlled to be constantly applied to the segment and the liquid crystal shutter F, respectively, to bring the entire liquid crystal shutter F into a non-diffused state (transparent).

[6. Function display unit]
Next, the function display unit 1180 on the game board 4 will be described with reference to FIG. The function display unit 1180 is attached and arranged at a predetermined position of the front component member 1110. FIG. 13 is an enlarged front view showing a function display unit in the game board in a state where the function display unit is attached to the pachinko game machine.

As shown in an enlarged view in FIG. 13, the function display unit 1180 has a game state display including one LED for displaying a game state that changes depending on a game ball driven into the game area 1100 at the left end in front view. 1183 and upper special symbol memory display 1184 for displaying the number of reservations regarding the acceptance of the game ball to the first starting port 2101, which is made up of two LEDs lined up and down on the right side of the game state display 1183, It is arranged on the right side of the special symbol memory display 1184 and is composed of one 7-segment LED for displaying the first special lottery result selected by the receipt of the game ball into the first starting opening 2101 as the first special symbol. For displaying the special symbol display 1185 and the second special lottery result selected by the receipt of the game ball into the second starting opening 2102, which is arranged diagonally right above the special symbol display 1185, as the second special symbol A lower special symbol display 1186 consisting of one 7-segment LED and two LEDs lined up and down on the right side of the lower special symbol display 1186 to display the number of holdings of the game ball to the second starting opening 2102. And a lower special symbol memory display 1187 for doing.

In the display unit 1181 of the function display unit 1180, in order to display the number of reservations regarding the passage of the gate unit 2150 by the game ball, which are arranged side by side in an arc shape substantially above the inner peripheral rail 1113 from directly above the lower special symbol display device 1186. Normal symbol storage display 1188 consisting of four LEDs, and for displaying the normal lottery result selected by the game ball placed under the normal symbol storage display through the gate portion 2150 as a normal symbol The normal symbol display 1189 consisting of one LED and the normal symbol memory display 1188 are arranged side by side diagonally to the upper right side, and when the first special lottery result or the second special lottery result is "big hit", the special winning opening 2103 is opened and closed. A round display 1190 including two LEDs for displaying the number of times the pattern is repeated (the number of rounds).

The game status indicator 1183 is a full-color LED whose red, green, and orange colors can be changed, and various game status ( For example, a normal time state, a probability variation state, a time reduction state, a probability variation short time state, a big hit game state, a small hit game state, etc.) can be displayed.

The upper special symbol storage display 1184, when the first special symbol can not be variably displayed in the upper special symbol display 1185, when the game ball is accepted in the first starting port 2101, the start of the variable display is suspended. The number (reserved number) of the stored (memorized) first special symbols is displayed. Above this special symbol memory display 1184 has a first special symbol memory lamp 1184a and a first special symbol memory lamp 1184b consisting of a predetermined LED, the first special symbol memory lamp 1184a, 1184b lighting · The number of holdings can be displayed by a blinking pattern. Specifically, for example, when the number of holding is one, the first special symbol storage lamp 1184a is turned on and the first special symbol storage lamp 1184b is turned off, and when the number of holding is two, the first special symbol storage lamps 1184a, 1184b. Lights together, when the number of reservations is three, the first special symbol storage lamp 1184a blinks and the first special symbol storage lamp 1184b is lit, and when the number of reservations is four, the first special symbol storage lamps 1184a and 1184b are both It is supposed to blink. In the present embodiment, up to four are reserved.

The lower special symbol storage display 1187, when the second special symbol can not be variably displayed in the lower special symbol display 1186, when the game ball is accepted to the second starting port 2102, the start of the variable display is suspended. The number of stored (memorized) second special symbols is displayed. This lower special symbol memory display 1187 has a second special symbol memory lamp 1187a consisting of a predetermined LED and a second special symbol memory lamp 1187b, and lighting of the second special symbol memory lamps 1187a, 1187b. The number of holdings can be displayed by a blinking pattern. Specifically, for example, when the number of holding is one, the second special symbol storage lamp 1187a is turned on and the second special symbol storage lamp 1187b is turned off, and when the number of holding is two, the second special symbol storage display lamp 1187a, Both 1187b are lit, when the number of reservations is three, the second special symbol storage lamp 1187a blinks and the second special symbol storage lamp 1187b is lit, and when the number of reservations is four, the second special symbol storage lamps 1187a, 1187b are Both are designed to blink. In the present embodiment, up to four are reserved.

The upper special symbol display device 1185 and the lower special symbol display device 1186 display the first special lottery result and the second special lottery result that have been selected by receiving the game balls into the first starting opening 2101 and the second starting opening 2102. The 7-segment LED has changed for a predetermined time according to the special lottery result, and stopped after changing, and the light-emitting pattern (special pattern) of the stopped 7-segment LED causes the first special lottery result and the second special lottery result. Can be recognized by the player.

Ordinary symbol display device 1189 is a red/green/orange color and a full-color LED whose emission color can be changed. By combining the emitting color and the lighting/blinking, the gate portion 2150 is played. It is possible to display the result of a normal lottery that is drawn by passing a ball. The display of the normal symbol by the normal symbol display device 1189, like the special symbol, is changed and displayed for a predetermined time, and then is stopped and displayed in a light emission pattern corresponding to the ordinary lottery result.

The normal symbol storage display 1188, when the normal symbol cannot be displayed in a variable manner on the normal symbol display 1189, when the game ball passes through the gate portion 2150, the start of the variable display is suspended (stored) normal symbol. The number of reservations (memory number) is displayed. This normal symbol memory display 1188 includes four normal symbol memory lamps 1188a to 1188d arranged side by side from the bottom, each of which is a predetermined LED, and the normal symbol memory lamp 1188a from the bottom depending on the number of holdings. By sequentially lighting up to 1188d, it is possible to display the number of reserved symbols of normal symbols. In this embodiment, the variable display of the normal symbols is held (stored) up to four.

The round indicator 1190 is provided with a two-round display lamp 1190a and a fifteen-round display lamp 1190b each made of a predetermined LED, and the number of rounds in the "big hit" game can be displayed by turning on each lamp. It is like this.

In addition, as shown in FIG. 13, the function display unit 1180 can be viewed from the player side through the game window 101 of the door frame 5 in a state where the game board 4 is attached to the pachinko game machine 1. There is. Game state display 1183, upper special symbol memory display 1184, upper special symbol display 1185, lower special symbol display 1186, lower special symbol memory display 1187, normal symbol memory display 1188, normal symbol display 1189, and The round display 1190 is attached to the front surface of the function display board 1191. A connection terminal for connecting the function display board 1191 and the main control board 4100 is attached to the rear end of the rear projection of the function display unit 1180.

In this embodiment, since the function display unit 1180 is provided in the front component member 1110 of the game board 4, as compared with the case where the function display unit 1180 is provided in the front unit 2000 or the back unit 3000 attached to the game panel 1150, The function display unit 1180 can be used as the basic configuration of the game board 4, the configuration related to the pachinko gaming machine 1 can be simplified and the cost can be prevented from increasing, and the model of the pachinko gaming machine 1 (table The position of the function display unit 1180 does not change even if the detailed configuration of the game board 4 embodied by the unit 2000 or the back unit 3000 and capable of characterizing the model of the pachinko gaming machine 1 is different, so that the player or the game The position of the function display unit 1180 can be recognized by a clerk or the like in the hall without any confusion.

[7. Main control board, payout control board and peripheral control board]
Next, a control board that performs various controls of the pachinko gaming machine 1 will be described with reference to FIGS. 14 to 20. 14 is a block diagram of a main control board, a payout control board, and a peripheral control board, FIG. 15 is a block diagram showing the continuation of FIG. 14, and FIG. 16 is a payout control board, a CR unit, and a frequency which constitute the main board. FIG. 17 is a schematic diagram of various detection signals that are input/output to/from a lending device connection terminal board for gaming balls or the like that relays electrical connection with a display board, FIG. 17 is a block diagram showing the continuation of FIG. 14, and FIG. FIG. 20 is a block diagram showing an outline of a peripheral control MPU, FIG. 19 is a block diagram around a sound source built-in VDP in a liquid crystal and a sound control unit, and FIG. 20 is a block diagram following FIG.

As shown in FIG. 14, the control configuration of the pachinko gaming machine 1 is mainly configured by a main control board 4100, a payout control board 4110, and a peripheral control board 4140, and is responsible for various controls. First, the main control board will be described, and then the payout control board, the power supply board, and the peripheral control board will be described.

[7-1. Main control board]
As shown in FIG. 14, the main control board 4100 that controls the progress of the game controls the power-on process executed when the power is turned on, and is executed after a predetermined time has elapsed since the power was turned on and the game operation is performed. A main control MPU 4100a, which is a microprocessor including a ROM for storing various control programs such as a main control program for controlling, various commands, and a RAM for temporarily storing data, and detection signals from various detection switches are input. Main control input circuit 4100b, a main control output circuit 4100c for outputting various signals to an external board, a main control solenoid drive circuit 4100d for driving various solenoids, a power failure or an instantaneous voltage of a predetermined voltage. A power failure monitoring circuit 4100e that monitors a sign of a stop is mainly provided.

The main control MPU 4100a has a built-in RAM (hereinafter referred to as "main control built-in RAM") and a built-in ROM (hereinafter referred to as "main control built-in ROM"). In addition, a watchdog timer 4100af (hereinafter, referred to as "WDT 4100af with built-in main control") for monitoring its operation (system), a function for preventing fraud, and the like are also incorporated.

The main control MPU 4100a has a built-in nonvolatile RAM. This non-volatile RAM stores in advance a unique ID code with a unique code (a code that exists only once in the world) for identifying an individual by the manufacturer of the main control MPU 4100a. Since the ID code once assigned is stored in the nonvolatile RAM, it cannot be rewritten even by using an external device. The main control MPU 4100a can retrieve the ID code from the nonvolatile RAM and refer to it.

In addition, the main control MPU 4100a is a hard random number circuit 4100an (hereinafter, referred to as "main control built-in Hard random number circuit 4100an”). The main control built-in hard random number circuit 4100an generates a random number within a predetermined numerical range (in the present embodiment, a numerical range of 0 as the minimum value and 32767 as the maximum value is preset). The predetermined value is not fixed as the initial value (that is, the initial value is not fixed), and the circuit is configured so that a different value is set every time the main control MPU 4100a is reset. Specifically, when the main control MPU 4100a is reset, the main control built-in hard random number circuit 4100an first sets a clock signal (input to the main control MPU 4100a as one value within a predetermined numerical range as an initial value). Based on the clock signal output from the main control crystal oscillator, which will be described later), other values within the predetermined numerical range are extracted at high speed one after another without duplication, and all values within the predetermined numerical range are extracted. After that, one value within the predetermined numerical range is extracted again, and at high speed based on the clock signal input to the main control MPU 4100a, without overlapping other values within the predetermined numerical range. Extract one after another. The main control built-in hard random number circuit 4100an repeatedly performs such a high-speed lottery, and the main control MPU 4100a makes a big hit with the value extracted by the main control built-in hard random number circuit 4100an at the time of obtaining the value from the main control built-in hard random number circuit 4100an. It is set as a random number for judgment.

The main control input circuit 4100b is not provided with a reset terminal for forcibly resetting the information input with the detection signals from the various detection switches to its various input terminals, and does not have a reset function. Therefore, the main control input circuit 4100b is configured as a circuit to which the system reset signal from the main control system reset described later is not input. That is, in the main control input circuit 4100b, the information based on the detection signals from the various detection switches input to the various input terminals is not reset by the main control system reset, which will be described later, so that various signals based on the information are changed. It is configured as a circuit output from the output terminal.

The main control output circuit 4100c is configured as an open collector output type in which the emitter terminal is grounded to the ground (GND), and various signals for outputting various signals to an external board or the like are input to the various input terminals. Main control output circuit 4100ca with a reset function having a reset function for forcibly resetting stored information and a main control output circuit 4100cb without a reset function having no reset terminal and having no reset function It consists of and. The main control output circuit 4100ca with a reset function is configured as a circuit to which a system reset signal from a main control system reset described later is input. That is, the main control output circuit 4100ca with a reset function has information for outputting various signals input to its various input terminals to an external board or the like by being reset by a main control system reset, which will be described later. Is configured as a circuit in which no signal based on is output from its various output terminals. On the other hand, the main control output circuit 4100cb having no reset function is configured as a circuit to which a system reset signal from a main control system reset described later is not input. In other words, the main control output circuit 4100cb without the reset function outputs information for outputting various signals input to its various input terminals to an external board or the like because the information is not reset by the main control system reset described later. It is configured as a circuit in which the base signal is output from its various output terminals.

As shown in FIG. 8, a first starting opening switch 3022 that detects a game ball that has entered the first starting opening 2101, a second starting opening switch 2109 that detects a game ball that has entered the second starting opening 2102, and the general The detection signal from the general winning opening switch 3020 that detects a game ball that has entered the winning opening 2104 and the signal from the power failure monitoring circuit 4100e are input terminals of a predetermined input port of the main control MPU 4100a via the main control input circuit 4100b. Has been entered in. Further, as shown in FIG. 8, a gate switch 2352 for detecting a game ball that has passed through the gate portion 2150, a general winning opening switch 3020 for detecting a game ball entering the general winning opening 2201, and a large winning opening 2103 are entered. A detection signal from a count switch 2110 that detects a game ball and a magnetic detection switch 3024 that is attached to the back unit 3000 shown in FIG. 9 and detects fraud using a magnet is a panel relay attached to the game board 4. It is inputted to the input terminal of a predetermined input port of the main control MPU 4100a via the terminal board 4161 and the main control input circuit 4100b.

The main control MPU 4100a outputs a drive signal from the output terminal of the predetermined output port to the main control output circuit with reset function 4100ca based on the detection signal from each of these switches, thereby the main control output circuit with reset function. 4100ca outputs a control signal to the main control solenoid drive circuit 4100d, and outputs a drive signal from the main control solenoid drive circuit 4100d to the starting opening solenoid 2105 and the attacker solenoid 2108 via the panel relay terminal plate 4161, or a predetermined output thereof. By outputting a drive signal from the output terminal of the port to the main control output circuit 4100ca with the reset function, the main control output circuit 4100ca with the reset function, the panel relay terminal board 4161, and the function display board 1191, the upper special symbol display device 1185, lower special symbol display 1186, upper special symbol memory display 1184, lower special symbol memory display 1187, normal symbol display 1189, normal symbol memory display 1188, game state display 1183, and round display 1190 It outputs a drive signal.

Further, the main control MPU 4100a outputs various information regarding the game (game information) from the output terminal of the predetermined output port to the main control output circuit 4100ca with the reset function, so that the payout control is performed from the main control output circuit 4100ca with the reset function. By outputting various information (game information) about the game to the board 4110 and outputting a signal (power failure clear signal) to the main control output circuit with reset function 4100ca from the output terminal of the predetermined output port, the main with reset function A signal (power failure clear signal) is output from the control output circuit 4100ca to the power failure monitoring circuit 4100e.

In addition, in the present embodiment, a non-contact type electromagnetic proximity switch is used for the first starting port switch 3022, the second starting port switch 2109, the gate switch 2352, and the count switch 2110. As the general winning opening switches 3020 and 3020, contact-type ON/OFF operation type mechanical switches are used. This is because the game ball frequently enters the first starting port 2101 and the second starting port 2102 and frequently passes through the gate portion 2150, so the first starting port switch 3022, the second starting port switch 2109, and The detection of the game ball by the gate switch 2352 also frequently occurs. Therefore, a proximity switch having a long life is used for the first starting port switch 3022, the second starting port switch 2109, and the gate switch 2352. In addition, when the big hit game state which is advantageous to the player occurs, the special winning opening 2103 is opened and the game ball is frequently entered, so that the game ball is frequently detected by the count switch 2110. Therefore, the count switch 2110 also uses a proximity switch having a long life. On the other hand, the general winning opening 2104, 2201 in which the game ball does not enter frequently does not frequently be detected by the general winning opening switches 3020, 3020. For this reason, the general winning opening switches 3020 and 3020 are mechanical switches having a shorter life than the proximity switch.

Further, the main control MPU 4100a transmits various commands relating to payout from the output terminal of the predetermined serial output port to the main control output circuit 4100cb without reset function as serial data, thereby controlling payout from the main control output circuit 4100cb without reset function. Various commands are transmitted to the board 4110 as serial data. When the payout control board 4110 normally receives various commands from the main control board 4100 as serial data, the payout control board 4110 outputs a signal (payment main ACK signal) to that effect to the main control board 4100. This signal (payment main ACK signal) is input to the input terminal of a predetermined input port of the main control MPU 4100a via the main control input circuit 4100b.

Further, the main control MPU 4100a receives various commands relating to the state of the pachinko gaming machine 1 from the payout control board 4110 as serial data at the main control input circuit 4100b, so that the main control input circuit 4100b outputs a predetermined serial input port. Various commands are received as serial data at the input terminal. When the various commands from the payout control board 4110 are normally received as serial data, the main control MPU 4100a outputs a signal (main payout ACK signal) to that effect from the output terminal of the predetermined output port to the main control output with a reset function. The signal is output to the circuit 4100ca, and the main control output circuit with reset function 4100ca outputs a signal (main payment ACK signal) to the payout control board 4110.

In addition, the main control MPU 4100a transmits, as serial data, various commands relating to the control of game production and various commands relating to the state of the pachinko gaming machine 1 from the output terminal of the predetermined serial output port to the main control output circuit 4100cb having no reset function. Thus, various commands are transmitted as serial data from the main control output circuit 4100cb without the reset function to the peripheral control board 4140.

Here, the main serial transmission port for transmitting various commands as serial data to the peripheral control board 4140 will be briefly described. The main control MPU 4100a is mainly configured by a main control CPU core 4100aa. In addition to the main control built-in RAM, a main control serial transmission port 4100ae, which is one of various main control serial I/O ports, etc., connects the bus 4100ah. It is connected via a circuit (see FIG. 26). The main serial transmission port 4100ae transmits various commands to the peripheral control board 4140 as main serial data, and mainly includes a transmission shift register 4100ea, a transmission buffer register 4100aeb, a serial management unit 4100aec, etc. 26). When the main control CPU core 4100aa sets the command in the transmission buffer register 4100aeb and outputs the transmission start signal to the serial management unit 4100aec, the serial management unit 4100aec transmits the command set in the transmission buffer register 4100aeb from the transmission buffer register 4100aeb. The data is transferred to the transmission shift register 4100ea and started to be transmitted to the peripheral control board 4140 as main-circulation serial data. In this embodiment, the storage capacity of the transmission buffer register 4100aeb is 32 bytes. The main control CPU core 4100aa continuously transmits a plurality of commands to the peripheral control board 4140 by setting a plurality of commands in the transmission buffer register 4100aeb and then outputting a transmission start signal to the serial management unit 4100aec.

It should be noted that the power supply board 851 that supplies various voltages to the main control board 4100 is an electric power supply as a backup power supply for supplying power to the main control board 4100 for a predetermined time (3 hours in the present embodiment) even when the power is cut off. A multilayer capacitor (hereinafter, simply referred to as “capacitor”) BC0 (see FIG. 21) is provided. The capacitor BC0 enables the main control MPU 4100a to store various information in the main control built-in RAM in the power-off processing even when the power is turned off. Various types of information stored in the main control built-in RAM are operation signals (RAM clear signal) from the operation switch 860a when the operation switch 860a of the payout control board 4110, which will be described later, is operated within a predetermined period after the power is turned on. Is output from the payout control board 4110, and is input to an input terminal of a predetermined input port of the main control MPU 4100a via the main control input circuit 4100b. At this time, the main control MPU 4100a completely erases it from the main control internal RAM. It is supposed to be (cleared).

[7-2. Discharge control board]
As shown in FIG. 15, the payout control board 4110 that performs the game ball launch control, the game ball launch control, and the ball delivery control, in addition to the game ball launch control, performs various controls related to the payout, as well as the game ball launch control and the ball feed control. The payout control unit 4120 for performing the above, an operation switch 860a that also has various functions, and an error LED display 860b that displays the state of the pachinko gaming machine 1. The operation switch 860a that also has a function as a RAM clear switch is a RAM built in the main control MPU 4100a (hereinafter referred to as "main control built-in RAM") based on a detection signal output by being operated. The RAM clear signal for completely erasing the information stored in (.

[7-2-1. Dispensing control unit]
As shown in FIG. 15, the payout control unit 4120, which performs various kinds of control related to payout, controls the launch of a game ball, and controls the ball transfer, controls the power-on process that is executed when the power is turned on, and a predetermined time from when the power is turned on. A payout, which is a microprocessor in which a ROM for storing various control programs and various commands including a payout control program for controlling a payout operation of a game medium executed after a lapse of time, a RAM for temporarily storing data, and the like are incorporated. Control MPU 4120a, payout control input circuit 4120b to which detection signals from various detection switches related to payout and detection signals from various detection switches related to game ball launch are input, and payout for outputting various signals to an external board or the like. CR unit input/output for exchanging various signals with the control output circuit 4120c, the payout motor drive circuit 4120d for outputting a drive signal to the payout motor 744 of the prize ball device 740 shown in FIG. 5, and the CR unit 6. And a circuit 4120e. The payout control MPU 4120a includes a launch ball sending control circuit 4120ag for performing launch control by the launch solenoid 654 of the hitting ball launching device 650 shown in FIG. The shooting ball feeding control circuit 4120ag has a built-in shooting ball feeding failure monitoring circuit 4120ah that monitors whether or not a failure has occurred in the shooting ball feeding control circuit 4120ag. The payout control MPU 4120a has a built-in RAM (hereinafter, referred to as “payout control built-in RAM”), a built-in ROM (hereinafter, referred to as “payout control built-in ROM”), It also has a watchdog timer to monitor its operation (system) and a function to prevent fraud.

The firing ball feeding control circuit 4120ag incorporated in the payout control MPU 4120a for performing the firing control by the firing solenoid 654 and the ball feeding control by the ball feeding solenoid 585 is based on the rotational position of the front of the rotary handle body 506 shown in FIG. A touch switch for detecting whether or not a palm or a finger touches the front 506 of the rotating handle body and an operation signal from a potentiometer 512 that electrically adjusts the strength (firing strength) at which the game ball is shot toward the game area 1100. The detection signal from 516 and the detection signal from the firing stop switch 518 for detecting whether to forcibly stop the launch (launch) of the game ball according to the player's intention are the handle relay terminal board 192 and the power supply board. 851 and the payout control input circuit 4120b of the payout control board 4110. Further, when the CR unit 6 and the game ball lending device connection terminal plate 869 are electrically connected to each other, the launch ball sending control circuit 4120ag outputs a CR connection signal to that effect to the CR unit input/output of the payout control board 4110. It is input via the circuit 4120e.

The launch ball sending control circuit 4120ag adjusts a drive current for launching (launching) the game ball toward the game area 1100 based on an operation signal from the potentiometer 512, and a payout control output circuit 4120c (with a reset function described later). Through the payout control output circuit 4120ca), the power is supplied to the power supply board 851 (the firing solenoid drive circuit 858 described later) to control the firing by the firing solenoid 654, while the payout control output circuit 4120c (the payout control with a reset function described later) is performed. The ball of the ball feeding unit 580 is output to the power supply board 851 (ball feeding solenoid drive circuit 859 described later) via the output circuit 4120ca) and a constant current is output to the ball feeding solenoid 585 via the handle relay terminal plate 192. The sending member receives the one game ball stored in the upper plate 301 of the plate unit 300 shown in FIG. 7, and controls the game ball received by the ball sending member to the hitting ball launcher 650 side.

The launch ball sending control circuit 4120ag operates according to the payout control program, and when the launch operation permission is set, the game ball is played in the game area 1100 according to the rotation position of the front of the rotary handle main body 506 shown in FIG. An operation signal from a potentiometer 512 that electrically adjusts the strength to be fired toward (fire strength), and a detection signal from a touch switch 516 that detects whether or not the palm or finger touches the front 506 of the rotating handle body, The detection signal from the firing stop switch 518 for detecting whether to forcibly stop the launching (launching) of the game ball according to the player's intention, the CR unit 6 and the game ball lending device connection terminal board 869 are electrically connected. The game ball is controlled to be fired based on the CR connection signal indicating that the game ball is to be connected. On the other hand, when the firing operation prohibition is set, the above-described gaming ball firing control is forcibly stopped.

It should be noted that the launch ball sending control circuit 4120ag controls the launch of the game balls as 99.93 to 99.95 balls as the number of game balls that can be launched (launched) toward the game area 1100 per minute. It is set in advance so that it does not exceed 100 balls. This is realized by a PWM circuit (not shown) for generating a PWM (Pulse Width Modulation) signal (not shown) built in the payout control MPU 4120a. The pulse width of the PWM signal output from this circuit is such that the number of game balls that can be launched (launched) toward the game area 1100 per minute is 99.93 balls to 99.95 balls. The PWM signal is set in advance and is circuit-connected so that the PWM signal is input to the launch ball sending control circuit 4120ag. The launch ball sending control circuit 4120ag measures the launch timing of the game ball based on the input PWM signal.

As described above, the launch ball delivery failure monitoring circuit 4120ah is for monitoring whether or not there is a failure in the launch ball delivery control circuit 4120ag, and stores the monitoring result (presence or absence of failure) as status information. It can be held. When the payout control program acquires the status information from the launch ball sending defect monitoring circuit 4120ah and determines that there is a problem in the launch ball sending control circuit 4120ag, it controls the launch of the game ball by the launch ball sending control circuit 4120ag. In order to forcibly stop, the firing operation is set to the firing ball sending control circuit 4120ag.

It should be noted that the payout control program sets the launch operation prohibition to the launch ball sending control circuit 4120ag as an initial state (default) when the power is turned on or when a power failure occurs or a power failure occurs and power is restored thereafter. After that, when the status information is acquired from the launch ball sending failure monitoring circuit 4120ah and it is determined that there is no failure in the launch ball sending control circuit 4120ag, the launch ball sending control circuit 4120ag starts the game ball launch control. While the launch operation permission is set to the launch ball sending control circuit 4120ag, the status information is obtained from the launch ball sending failure monitoring circuit 4120ah and it is determined that the launch ball sending control circuit 4120ag has a failure. In order to maintain the state in which the control of launching the game ball by the ball sending control circuit 4120ag is stopped, the launching operation is set to be prohibited for the launch ball sending control circuit 4120ag.

Here, as a defect in the launch ball sending control circuit 4120ag, it becomes difficult to adjust the drive current for launching (launching) the game ball toward the game area 1100 based on the operation signal from the potentiometer 512. If the operation signal from the potentiometer 512 is affected by noise and becomes an extremely disturbed signal, the drive current for launching (launching) the game ball toward the game area 1100 cannot be specified and the drive current cannot be specified. If it is difficult to adjust, the detection signal from the touch switch 516 is affected by noise and becomes an extremely disturbed signal, and whether the palm or finger of the player's hand touches the front 506 of the rotating handle body. When it is difficult to specify whether or not it is difficult, the detection signal from the firing stop switch 518 is affected by noise and becomes a very disturbed signal, and the player is willing to launch (launch) the game ball. In addition to the case where it is difficult to specify whether or not it is stopped, the launch ball sending control circuit 4120ag itself is destroyed due to some cause and cannot be used, or a game area per predetermined time. When the number of balls of the game balls launched (fired) toward 1100 exceeds a predetermined number (in the present embodiment, the number of balls of the game balls launched (fired) toward the game area 1100 per minute) Is over 100 balls).

Under the control of the payout control MPU 4120a, the payout control program sends various kinds of information (game information) about the game from the main control board 4100 and various commands about the payout as payer serial data transmission signals via the payout control I/O port 4120b. Receive serial data by serial method. In addition, the payout control program generates a frame state 1 command when an error occurs in the payout operation of the game ball, or 16 bits based on the operation signal (detection signal) of the operation switch 860a serving as the error canceling unit. An error cancellation navigation command of (2 bytes) is created, and is output to the receiving port of the main control board 4100 via the payout control I/O port 4120b as serial data of a serial system as a payer serial data transmission signal. In addition, this payout control program is executed after a predetermined time has elapsed from the time when the power is turned on, that is, after the payout control unit main process is executed or the payout control unit timer interrupt process is executed to start the payout control. When an error occurs in the operation, the error is canceled based on the detection signal generated by the operation of the operation switch 860a, and the output of the warning information according to the error is stopped.

In addition, this payout control program acquires the status information from the launch ball sending failure monitoring circuit 4120ah and determines that there is no failure in the launch ball sending control circuit 4120ag. While setting the firing operation permission to the launch ball sending control circuit 4120ag to start the launch control, when it is determined that there is a problem in the launch ball sending control circuit 4120ag, the game by the launch ball sending control circuit 4120ag In order to forcibly stop the firing control of the ball, the firing operation inhibition is set to the firing ball sending control circuit 4120ag.

The payout control input circuit 4120b is not provided with a reset terminal for forcibly resetting the information input with the detection signals from the various detection switches to its various input terminals, and does not have a reset function. Therefore, the payout control input circuit 4120b is configured as a circuit to which a system reset signal from a payout control system reset described later is not input. That is, in the payout control input circuit 4120b, the information based on the detection signals from the various detection switches input to the various input terminals is not reset by the payout control system reset, which will be described later. It is configured as a circuit output from the output terminal.

The payout control output circuit 4120c is configured as an open collector output type in which the emitter terminal is grounded to the ground (GND), and various signals for outputting various signals to an external board or the like are input to the various input terminals. Resetting-equipped payout control output circuit 4120ca having a reset function provided with a reset terminal for forcibly resetting the generated information, and resetting-less payout control output circuit 4120cb having no reset terminal provided with no reset function It consists of and. The payout control output circuit 4120ca with a reset function is configured as a circuit to which a system reset signal from a payout control system reset described later is input. That is, in the payout control output circuit 4120ca with the reset function, the information for outputting various signals input to the various input terminals to an external board or the like is reset by a payout control system reset described later, so that the information is output. Is configured as a circuit in which no signal based on is output from its various output terminals. On the other hand, the payout control output circuit 4120cb without the reset function is configured as a circuit to which the system reset signal from the payout control system reset described later is not input. In other words, the payout control output circuit 4120cb without the reset function outputs information for outputting various signals input to its various input terminals to an external board or the like by not being reset by a payout control system reset which will be described later. It is configured as a circuit in which the base signal is output from its various output terminals.

First, the detection signal from the ball break switch 750 that detects the presence or absence of a game ball in the supply passage of the prize ball device 740, and the counting switch 751 that detects the game ball flowing down in the prize ball passage of the prize ball device 740 is the prize. It is input to the input terminal of a predetermined input port of the payout control MPU 4120a via the prize ball case substrate 754 of the ball device 740 and the payout control input circuit 4120b. The detection signals from the rotation angle switch 752 for detecting the detection slits formed on the rotation detection board of the prize ball device 740 are the rotation angle switch substrate 753 of the prize ball device 740, the substrate 754 in the prize ball case, and It is input to the input terminal of a predetermined input port of the payout control MPU 4120a via the payout control input circuit 4120b.

Further, the detection signals from the door frame opening switch 618 that detects the opening of the door frame 5 with respect to the body frame 3 and the body frame opening switch 619 that detects the opening of the body frame 3 with respect to the outer frame 2 are output to the payout control input circuit 4120b. It is input to the input terminal of a predetermined input port of the payout control MPU 4120a via the.

In addition, the detection signal from the full tank switch 550 which detects whether or not the accommodation space of the foul cover unit 540 shown in FIG. 1 is full in the stored game balls is first a handle relay terminal board 192 and a power supply board. It is input to the input terminal of a predetermined input port of the payout control MPU 4120a via the payout control input circuit 4120b.

The payout control MPU 4120a receives various commands related to the payout from the main control board 4100 via the payout control input circuit 4120b at the input terminal of the serial input port in the serial data system, and the operation signal (detection signal of the operation switch 860a). Signal) is output to the main control board 4100 via the payout control input circuit 4120b. When the payout control MPU 4120a completes the normal reception of various commands from the main control board 4100 as serial data, a signal (payment main ACK signal) to that effect is output from the output terminal of the predetermined output port of the payout control output with a reset function. By outputting to the circuit 4120ca, a payout control output circuit with reset function 4120ca outputs a signal (payment ACK signal) to the main control board 4100.

Further, the payout control MPU 4120a sends various commands for indicating the state of the pachinko gaming machine 1 as serial data from the output terminal of the serial output port to the reset function-free payout control output circuit 4120cb, thereby issuing the payout without the reset function. Various commands are transmitted as serial data from the control output circuit 4120cb to the main control board 4100. When the main control board 4100 completes the normal reception of various commands from the payout control board 4110 as serial data, it outputs a signal (main payment ACK signal) to that effect to the payout control board 4110. This signal (main payment ACK signal) is input to the input terminal of a predetermined input port of the payout control MPU 4120a via the payout control input circuit 4120b.

Further, the payout control MPU 4120a outputs a drive signal for driving the payout motor 744 from the output terminal of the predetermined output port to the payout control output circuit 4120ca with a reset function, whereby the payout control output circuit 4120ca with a reset function. From the payout motor drive circuit 4120d, the drive signal from the payout motor drive circuit 4120d to the payout motor 744 via the prize ball case substrate 754, or from the output terminal of the predetermined output port to the pachinko machine. By outputting a drive signal for displaying the state of the gaming machine 1 to the error LED indicator 860b to the payout control output circuit 4120ca with the reset function, the drive signal is output from the payout control output circuit 4120ca with the reset function to the error LED indicator 860b. Or output to.

The error LED indicator 860b is a segment indicator and displays alphanumeric characters and figures to indicate the state of the pachinko gaming machine 1. The contents displayed and notified by the error LED indicator 860b include the following. For example, when the figure "-" is displayed, it indicates that it is "normal", and when the number "0" is displayed, it indicates that "connection is abnormal" (specifically, the main control board 4100 and That there is an abnormality in the electrical connection between the payout control board 4110 and the board, and when the number "1" is displayed, it means "out of ball" (specifically, out of ball). Based on the detection signal from the switch 750, it notifies that there is no game ball in the supply passage of the prize ball device 740), and when the number "2" is displayed, it means "ball ball" (specifically Indicates that the payout rotating body and the game ball engage at the entrance of the distribution space communicating with the supply passage of the prize ball device 740 based on the detection signal from the rotation angle switch 752, and the payout rotating body becomes difficult to rotate. "Count switch error" when the number "3" is displayed (specifically, a failure occurs in the count switch 751 based on the detection signal from the count switch 751). That the number of retries of the payout operation has reached a preset upper limit) when the number "5" is displayed. However, when the number "6" is displayed, it means "full" (specifically, a game ball in which the accommodation space of the foul cover unit 540 is stored based on the detection signal from the full tank switch 550). When the number "7" is displayed, it indicates that "CR is not connected" (electrical connection is cut off at any position from the payout control board 4110 to the CR unit 6). That the number is 9), and when the number “9” is displayed, it means “in stock (award ball stock (unpaid) is available)” (specifically, the number of game balls that have not yet been paid) Has reached a predetermined number of balls).

Further, the payout control MPU 4120a outputs the number of balls of the game balls actually paid out as the prize balls from the output terminal of the predetermined output port to the payout control output circuit 4120ca with the reset function, thereby performing the payout control with the reset function. The output circuit 4120ca outputs the number of game balls actually paid out as a prize ball to the external terminal board 784 via a resistor (not shown).

Further, the payout control board 4110 outputs various kinds of information (game information) about the game from the main control board 4100 to the external terminal board 784 via a resistor (not shown). To the external terminal board 784, in addition to the payout control board 4110, various information from the peripheral control board 4140 (the number of game balls to be paid out as prize balls, etc.) is also input. The external terminal board 784 is provided with a plurality of photo couplers (not shown) (infrared LEDs and photo ICs are built in), and a game hall (hall) through the plurality of photo couplers. ), the number of balls of the game ball and various information (game information, error content regarding the payout operation of the game ball or the fact that there was an error) is transmitted to the hall computer. The external terminal board 784 and the hall computer are electrically insulated by a plurality of photocouplers, and an abnormal voltage is applied to the hall computer via the external terminal board 784 of the pachinko gaming machine 1. The hall computer does not malfunction or break down, and the main control board 4100 that advances the game from the hall computer via the external terminal board 784 of the pachinko gaming machine 1, the payout control board that controls the payout, etc. An abnormal voltage is applied to 4110 and the peripheral control board 4140 that controls the progress of the performance, so that malfunction or failure does not occur. The hall computer, such as the number of game balls actually paid out by the pachinko gaming machine 1 as a prize ball, game information of the pachinko gaming machine 1, and the number of game balls scheduled to be paid out by the pachinko gaming machine 1 as a prize ball. By grasping, the player's game and the payout information (so-called payout information) of the game ball by the payout operation of the pachinko gaming machine 1 are monitored.

The ball lending request signal of the game ball from the ball lending switch 365a of the ball lending unit 360 and the return request signal of the prepaid card from the return switch 365b shown in FIG. And, it is adapted to be input to the CR unit 6 through the lending device connection terminal board 869 for gaming balls and the like. The CR unit 6 transmits a signal designating the number of balls to be lent out according to the ball lending request signal to the payout control board 4110 through the lending device connection terminal board 869 for gaming balls in a serial manner, and this signal is the CR unit. The payout control MPU 4120a is input to the input terminal of a predetermined input port via the input/output circuit 4120e. In addition, the CR unit 6 updates the remaining amount of the inserted prepaid card in accordance with the number of balls of the rented game balls, and outputs a signal for displaying the remaining amount on the remaining number display 365c, such as the game balls. The lending device connection terminal board 869, the main door relay terminal board 880, and the frequency display board 365 are output, and this signal is input to the remaining frequency display 365c. Further, the CR unit lamp 365d adjacent to the remaining number display 365c is configured such that the supply voltage from the CR unit 6 is input through the lending device connection terminal plate 869 for gaming balls and the main door relay terminal plate 880. There is.

In addition, the CR unit 6 includes the remaining amount of the prepaid card, various kinds of information on the hall, gaming machine data (for example, the game characteristics (gaming specifications) described in the gaming machine booklet, the contents of the outline of the performance, etc.), the wagon. Various information such as guidance for services (for example, drinks) is output to the upper plate side liquid crystal display device 470 as a video signal through the game ball lending device connection terminal plate 869 and the main door relay terminal plate 880. .. The upper plate side liquid crystal display device 470 may be of a type having a touch panel so as to cover the display area, and the position information of the touch panel on the touch panel by the player is transferred from the upper plate side liquid crystal display device 470 to the main door relay terminal plate 880. , Is output to the CR unit 6 through the lending device connection terminal board 869 for gaming balls and the like. When various information, such as a wagon service guide, is displayed in the display area of the upper plate side liquid crystal display device 470 in accordance with the video signal from the CR unit 6, a player among a plurality of drink images is displayed. When you touch the image of the drink you ordered with your finger, the position information of that finger is input to the CR unit 6, the CR unit 6 acquires the information of the drink corresponding to the image touched by the player, and then the player When the image of the confirmation button is touched with a finger, the position information of the finger is input to the CR unit 6, the acquired drink information and the machine number of the pachinko gaming machine in which the ordered player is seated and playing a game ( For example, the unit number managed in the hall) and the CR unit 6 wirelessly transmit to the terminal installed in the drink service center in the hall. When the power is turned on, the CR unit 6 monitors whether or not a failure has occurred in itself, and when it is in a normal state in which no failure has occurred, an alarm lamp (not shown) is lit in green to notify the user. On the other hand, in the case of an abnormal state in which a defect has occurred, a notification lamp (not shown) is lit in red to notify. Further, when the CR unit 6 transmits information (for example, information on drinks ordered by the player) to the drink service center in the hall in accordance with the player's operation from the touch panel of the upper plate side liquid crystal display device 470, A notification lamp (not shown) is lit in blue to notify the user, and when the drink service is completed, a signal to that effect is transmitted to the CR unit 6. As a result, the CR unit 6 notifies the result of monitoring whether or not a problem occurs in itself by turning on a notifying lamp (not shown). Regarding the end of the provision of the drink service, it may be transmitted to the CR unit 6 wirelessly when the drink is provided using the terminal owned by the clerk who provided the drink, or the clerk who provided the drink is in the hall. After returning to the drink service center, the terminal installed in the drink service center may be used to wirelessly transmit to the CR unit 6.

The power supply board 851 that supplies various voltages to the payout control board 4110 has a capacitor BC1 as a backup power supply for supplying power to the payout control board 4110 for a predetermined time (1 hour in this embodiment) even when the power is shut off. (See FIG. 21). With this capacitor BC1, the payout control MPU 4120a can store various kinds of information in the payout control built-in RAM (payout storage unit) in the power-off process even when the power is shut off. The various information stored in the payout control built-in RAM is such that when the operation switch 860a is operated within a predetermined period after the power is turned on, the operation signal is a predetermined signal of the payout control MPU 4120a via the payout control input circuit 4120b. The payout control MPU 4120a, which is input to the input terminal of the input port, judges as a RAM clear signal for completely erasing the information stored in the payout control built-in RAM. It is supposed to be completely erased. This operation signal (RAM clear signal) is output to the payout control output circuit 4120cb without the reset function, and is also output from the payout control output circuit 4120cb without the reset function to the main control board 4100.

[7-2-2. Exchange of various signals with the terminal connection device for lending equipment such as game balls]
Here, exchange of various signals between the payout control unit 4120 and the CR unit 6, exchange of various signals between the CR unit 6 and the frequency display plate 365, and exchange of various signals between the CR unit 6 and the upper plate side liquid crystal display device 470. The exchange will be described with reference to FIG. As shown in FIG. 16, the game ball lending device connection terminal board 869 not only relays the electrical connection between the CR unit 6 and the payout control board 4110 but also the CR unit 6 and the frequency display board 365. The electrical connection between the boards is also relayed (more precisely, the game ball lending device connection terminal board 869 is electrically connected to the frequency display board 365 via the main door relay terminal board 880. , The CR unit 6 and the game ball lending device connection terminal plate 869 are electrically connected, the game ball lending device connection terminal plate 869 and the main door relay terminal plate 880 are electrically connected, and the main door relay The terminal board 880 and the frequency display board 365 are electrically connected). Between the board of the CR unit 6 and the lending device connection terminal plate 869 for playing balls, between the lending device connection terminal plate 869 of playing balls for the payout control substrate 4110, the lending device connection terminal plate 869 for playing balls, and the main door relay Each wiring (harness) is provided between the board with the terminal board 880, between the boards with the main door relay terminal board 880 and the frequency display board 365, and with the connection between the main door relay terminal board 880 and the upper plate side liquid crystal display device 470. Are electrically connected to each other. In addition, AC24V described later from the power supply board 851 is supplied to the CR unit 6 through the lending device connection terminal plate 869 for gaming balls and the like. The CR unit 6 creates a predetermined voltage VL (DC+12V (DC+12V, hereinafter referred to as “+12V”) in this embodiment) from the supplied AC24V by a built-in voltage creation circuit (not shown) and ground LG. At the same time, it is supplied to the payout control board 4110 via the game ball lending device connection terminal plate 869, while being supplied to the frequency display plate 365 via the game ball lending device connection terminal plate 869 and the main door relay terminal plate 880. There is. Further, the CR unit 6 incorporates a predetermined voltage LVL (DC +3.3V (DC +3.3V, hereinafter referred to as "+3.3V")) from the supplied AC 24V, which is not shown. It is created by the creation circuit and is supplied to the upper plate side liquid crystal display device 470 through the lending device connection terminal plate 869 and the main door relay terminal plate 880 together with the ground LLG.

On the frequency display plate 365, a ball lending switch 365a, which is a push button switch, is mounted on the component surface at a position corresponding to the ball lending button 361 of the ball lending unit 360 shown in FIG. 2, and the ball lending unit 360 is returned. A return switch 365b, which is a push button switch, is mounted at a position corresponding to the button 362, and a remaining count display 365c, which is a segment display, is mounted at a position corresponding to the lending remaining display portion 363 of the ball rental unit 360.

The ball LG switch 365a and the return switch 365b are electrically connected to the ground LG from the CR unit 6 via the gaming ball lending device connection terminal plate 869 and the main door relay terminal plate 880. When the ball lending button 361 is pressed, the ball lending switch 365a turns on (turns on) the ball lending switch 365a, and the ball lending operation signal TDS from the ball lending switch 365a is transmitted to the main door relay terminal board 880 and the game. It is adapted to be input to the CR unit 6 through a ball lending device connection terminal plate 869. When the return button 362 is pressed, the return switch 365b turns on (turns on) the return switch 365b, and the return operation signal RES from the return switch 365b is connected to the main door relay terminal plate 880 and the game ball lending device connection. Input is made to the CR unit 6 via the terminal plate 869.

The residual number display 365c is one in which three segment displays are arranged side by side in a row. Of these three-digit segment displays, one-digit segment display is sequentially driven, and so-called dynamic lighting method provides three digits. The segment display of is controlled to light. By such lighting control, the remaining frequency indicator 365c displays the remaining amount of the prepaid card inserted in the CR unit 6 or an error of the CR unit 6. The remaining number display 365c displays the digit signals DG0 to DG2 (three signals in total) for designating the 1-digit segment display of the 3-digit segment display and the designated 1-digit segment display. The segment drive signals SEG-A to SEG-G (7 signals in total) for designating the contents to be lit and displayed are from the CR unit 6 to the rental ball connection device connection terminal board 869 and main door relay terminal board. When input via 880, the 1-digit segment display sequentially emits light in accordance with the input digit signals DG0 to DG2 and the segment drive signals SEG-A to SEG-G. The content of the light emission of is visible through the remaining lending display portion 363.

A CR unit lamp 365d is mounted on the frequency display plate 365 adjacent to the remaining frequency display 365c. In the CR unit lamp 365d, the predetermined voltage VL from the CR unit 6 is input through the game ball lending device connection terminal plate 869 and the main door relay terminal plate 880. The predetermined voltage VL is input to the CR unit 6 as a ball lending enable signal TDL through the current limiting resistor mounted on the game ball lending device connection terminal plate 869 via the CR unit lamp 365d. The CR unit 6 creates a predetermined voltage VL from the AC24V supplied from the power supply board 851 by the built-in voltage creating circuit, and when the ball lending switch 365a and the return switch 365b are in a valid ball lending state. Controls the logic of the ball lending enable signal TDL to cause the CR unit lamp 365d to emit light, and this light emission can be visually recognized through the remaining balance display portion 363. Further, the segment drive signals SEG-A to SEG-G are input to the remaining number display 365c through a current limiting resistor mounted on the gaming ball or the like lending device connection terminal plate 869.

In the CR unit 6, the ball lending button 361 is pressed and the ball lending operation signal TDS from the ball lending switch 365a is transmitted from the frequency display plate 365 through the main door relay terminal plate 880 and the game ball lending device connection terminal plate 869. When input, BRDY, which is a ball rental request signal, is output to the payout control board 4110 (payout control MPU4120a) via the game ball etc. lending device connection terminal plate 869. Then, the CR unit 6 issues a single payout operation start request signal for paying out a predetermined number of lent balls (25 balls in the present embodiment, which corresponds to 100 yen in amount) in one payout operation. BRQ is output to the payout control board 4110 (payout control MPU 4120a) via the lending device connection terminal board 869 for gaming balls and the like. The payout control board 4110 (payout control MPU 4120a) to which BRDY and BRQ are input is EXS, which is a signal for informing that one payout operation has started or ended, and a game ball lending device connection terminal board 869. Through the, the PRDY, which is a signal for outputting to the CR unit 6 or for indicating that the payout operation for paying out the rental ball is possible or impossible, is connected to the rental device connection terminal board for game balls and the like. It outputs to CR unit 6 via 869. Note that, for example, when the hall clerk or the like is preset in the CR unit 6 such that a game ball for 200 yen is paid out when the ball rental button 361 is pressed, one payout operation is performed. It is supposed to be performed twice consecutively, and if 25 balls for 100 yen are paid out, 25 balls for 100 yen will be paid out continuously, and 50 balls for a total of 200 yen will be paid out. Become.

In the CR unit 6, the return button 362 is pressed and the return operation signal RES from the return switch 365b is input from the frequency display plate 365 through the main door relay terminal plate 880 and the game ball lending device connection terminal plate 869. Then, the prepaid card is ejected from an insertion slot (not shown) and returned. The returned prepaid card stores the remaining amount after subtracting the amount corresponding to the number of game balls dispensed as a result of pressing the ball lending button 361.

The CR unit 6 includes the remaining amount of the prepaid card, various kinds of information on the hall, gaming machine data (for example, the game characteristics (gaming specifications) described in the gaming machine booklet, contents that outline the effect, etc.), wagon service ( For example, various information such as guidance for drinks, etc. is output to the upper plate side liquid crystal display device 470 as a video signal LVS via the game ball lending device connection terminal plate 869 and the main door relay terminal plate 880. When the image signal LVS is input, the upper plate side liquid crystal display device 470 displays the various information described above in its display area.

[7-3. Power board]
Next, the power supply board 851 will be briefly described. The power supply board 851 includes a power supply switch 852 that can electrically connect or disconnect 24 V AC (24 V AC) supplied from the Pachinko Island facility, and a power control unit 855 that generates various power supplies. A firing solenoid drive circuit 858 for driving the firing solenoid 654 of the ball-striking launcher 650 shown in FIG. 5 and a ball feeding solenoid drive circuit for driving the ball feeding solenoid 585 of the ball feeding unit 580 shown in FIG. 859 and. The launch solenoid drive circuit 858 is controlled by a launch ball sending control circuit 4120ag incorporated in the payout control MPU 4120a of the payout control board 4110, and launches a game ball toward the game area 1100 based on an operation signal from the potentiometer 512 (fire). The drive current to the firing solenoid 654 is adjusted so that The ball feeding solenoid drive circuit 859 is controlled by the launch ball feeding control circuit 4120ag built in the payout control MPU 4120a of the payout control board 4110, and the ball feeding member of the ball feeding unit 580 is the upper plate of the dish unit 300 shown in FIG. The game ball stored in 301 is received by one ball, and the driving current to the ball sending solenoid 585 is adjusted to be a constant current so that the game ball received by the ball sending member can be sent to the hitting ball launching device 650 side. It has become so.

[7-3-1. Power control unit]
The power supply control unit 855 improves the power factor of the synchronous rectification circuit 855a that rectifies the AC 24V (AC24V) supplied from the pachinko island facility by operating the power switch 852, and the power rectified by the synchronous rectification circuit 855a. A power factor correction circuit 855b, a smoothing circuit 855c that smoothes the power whose power factor has been improved by the power factor correction circuit 855b, and various direct currents that are supplied from the power smoothed by the smoothing circuit 855c to various substrates. And a power supply generation circuit 855d that generates a power supply.

[7-4. Peripheral control board]
As shown in FIG. 17, the peripheral control board 4140 controls the peripheral control section 4150 that performs effect control based on various commands from the main control board 4100 and the drawing control of the game board side effect display unit 1900 (liquid crystal panel 5000e). In addition to performing light emission control of various LEDs, sound control such as music and sound effects flowing from the speaker housed in the speaker box 820 shown in FIG. 5 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 is performed. A liquid crystal and sound control unit 4160, a real-time clock (hereinafter referred to as “RTC”) control unit 4165 that holds calendar information that specifies a date, and time information that specifies a hour, minute, and second, and a main body. A volume control volume 4140a that adjusts the volume of music or sound effect that flows from the speaker accommodated in the speaker box 820 provided in the frame 3 and the speaker 130 provided in the door frame 5 by rotating the knob portion. I have it.

[7-4-1. Peripheral controller]
As shown in FIG. 17, the peripheral control unit 4150 that performs the effect control controls the peripheral control MPU 4150a as a microprocessor and the power-on process executed when the power is turned on, and after a predetermined time has elapsed after the power was turned on. A peripheral control ROM 4150b that stores various control programs such as sub-control programs that are executed and controls the production operation, various data, various control data, and various schedule data, and a sound source built-in VDP 4160a of the liquid crystal and sound control unit 4160 described later. Various information that continues over the peripheral control unit steady process executed each time the V blank signal is input (for example, schedule data and various types that define a screen to be drawn (displayed) on the game board side effect display unit 1900 or the like. Peripheral control RAM 4150c that stores information for managing schedule data that defines the light emitting mode of LEDs and the like, and various information that continues across days (for example, to manage the history of a jackpot gaming state) Peripheral control SRAM 4150d for storing information of the above and information for managing a special effect flag, and a peripheral control external watchdog timer 4150e for monitoring whether the peripheral control MPU 4150a is operating normally (hereinafter, “Peripheral control external WDT4150e”) and a value transmitted by the power consumption suppression signal from the power supply board 851 (power consumption suppression stage described later) are passed through the frame peripheral relay terminal board 868 at predetermined intervals. A power consumption status history RAM 4150f that is sampled (in the power consumption status history information creation process in the peripheral control unit 1ms timer interrupt processing described later) and sequentially stored as power consumption status history information, and a power consumption status history storage unit when power is cut off. Based on the battery 4150g that supplies backup power to the power consumption status history storage unit 4150f so that the power consumption status history information of 4150f is stored and held, and the power consumption status history information stored and held in the power consumption status history RAM 4150f. When the power is cut off (immediately before the power is cut off), the status of power consumed by the pachinko gaming machine 1 is grasped at the time of power recovery, and the state of transition to the power saving mode at power recovery is notified to suppress the power consumed by the pachinko gaming machine 1. Power saving mode transition notification LED 4150k.

The peripheral control RAM 4150c can hold the stored contents only for a time such that an instantaneous power failure occurs and power is immediately restored, and the power is cut off for a long time (when a long power failure occurs. ), the peripheral control SRAM 4150d is supplied with backup power from a large-capacity electrolytic capacitor (not shown) (hereinafter referred to as “SRAM electrolytic capacitor”) provided on the power supply board 851. By doing so, the stored contents can be retained for about 50 hours. By providing the electrolytic capacitor for SRAM on the power supply board 851, when the gaming board 4 is removed from the pachinko gaming machine 1, backup power is not supplied to the peripheral control SRAM 4150d, so the peripheral control SRAM 4150d stores the stored contents. Can no longer hold and loses its contents.

The peripheral control external WDT 4150e is a timer for monitoring whether the system of the peripheral control MPU 4150a is out of control, and when this timer is up, it is reset by hardware. That is, the peripheral control MPU 4150a is reset when the clear signal for clearing the timer of the peripheral control external WDT 4150e is not output to the peripheral control external WDT 4150e within a certain period (until the timer expires). When the peripheral control MPU 4150a outputs a clear signal to the peripheral control external WDT 4150e within a certain period, it can restart the timer count of the peripheral control external WDT 4150e, and therefore is not reset.

The peripheral control MPU 4150a has a plurality of built-in parallel I/O ports, serial I/O ports and the like, and when various commands are received from the main control board 4100, a diagram provided on the game board 4 based on these various commands. A game scheduled to be paid out as a prize ball based on the game balls that have entered the various winning openings such as the first starting opening 2101, the second starting opening 2102, the general winning openings 2104, 2201, and the big winning opening 2103 shown in FIG. Each time the number of spheres reaches a predetermined number (in this embodiment, it is set to 10 spheres), a main prize sphere number information output signal is transmitted from the parallel I/O port to notify that fact. Not output to the external terminal board 784 via the peripheral control output circuit, or based on the power consumption status history information stored and held in the power consumption status RAM 4150f, the pachinko gaming machine 1 at the time of power shutdown (immediately before power shutdown) The power saving mode information output signal for transmitting the power saving mode transition mode to the power saving mode is grasped by grasping the power status that was being consumed at the time of power recovery and suppressing the power consumed by the pachinko game machine 1 from the parallel I/O port. It outputs to the external terminal board 784 through a peripheral control output circuit (not shown).

Further, the peripheral control MPU 4150a includes a plurality of LEDs provided on each of a plurality of gaming board side peripheral control MPU control target decorative boards, which are control targets directly controlled by the peripheral control MPU4150a, among the decorative boards of the game board 4. The game board side light emitting data SL-DAT for outputting a lighting signal, a blinking signal, or a gradation lighting signal to the decoration LED) is synchronized with the game board side light emitting clock signal SL-CLK, and the game board side decorative board serial is provided. Outputs a drive signal from an I/O port to a lamp drive board 4170 via a peripheral control output circuit (not shown), or outputs a drive signal to an electric drive source such as a motor or a solenoid that operates various movable bodies provided on the game board 4. To drive the game board side motor drive data from the motor drive board serial I/O port through the peripheral control output circuit to the motor drive board 4180 (provided in the motor drive board 4180, the serial data is converted into parallel data and the parallel signal is supplied). Through a serial/parallel conversion circuit (not shown) capable of outputting a motor drive circuit (or a motor drive circuit incorporating such a serial/parallel conversion circuit) or a solenoid drive circuit (or such a serial/parallel conversion circuit). Send to the built-in solenoid drive circuit)). Further, the peripheral control MPU 4150a outputs door side motor drive data for outputting a drive signal to an electric drive source such as a dial drive motor 414 provided on the door frame 5 from the frame decoration drive amplifier board motor serial I/O port. Through the peripheral control output circuit, the frame peripheral relay terminal board 868, and the peripheral door relay terminal board 882, the frame decoration drive amplifier board 194 (provided in the frame decoration drive amplifier board 194, converts serial data into parallel data and outputs parallel signals). It is transmitted to a motor drive circuit (or a motor drive circuit incorporating such a serial/parallel conversion circuit) via a serial/parallel conversion circuit (not shown) capable of outputting, or among the decorative boards of the door frame 5, Peripheral control MPU4150a directly controls the plurality of frame-side peripheral control MPU control target decorative boards provided with lighting signals, blinking signals or gradation lighting signals to a plurality of LEDs (decorative LEDs) provided on each of the decorative boards. The frame side light emission data STL-DAT to be output is synchronized with the frame side light emission clock signal STL-CLK from the frame side decorative board serial I/O port to the peripheral control output circuit, the frame peripheral relay terminal board 868, and the peripheral door. LOCKN signal output request data for transmitting to the frame decoration drive amplifier board 194 via the relay terminal board 882 or for confirming whether or not there is a problem between the door frame 5 and the frame decoration drive board 194. LOCKN signal output request is output from the serial I/O port.

Various commands from the main control board 4100 are input to the main control board serial I/O port of the peripheral control MPU 4150a via a peripheral control input circuit (not shown). Further, a detection signal from a rotation detection switch for detecting the rotation (rotational direction) of the dial operation unit 401 provided in the operation unit 400 and a press detection switch for detecting the operation of the pressing operation unit 405 are provided. The detection signal is serialized by a door-side serial transmission circuit (not shown) provided on the frame decoration drive amplifier board 194, and the serialized operation unit detection data is output from the door-side serial transmission circuit to the peripheral door relay terminal board 882 and the frame. It is input to the operation unit detection serial I/O port of the peripheral control MPU 4150a via the peripheral relay terminal plate 868 and the peripheral control input circuit.

Detection signals from various detection switches (for example, photosensors) for detecting the original position and movable position of various movable bodies provided on the game board 4 are game board sides (not shown) provided on the motor drive board 4180. Serialized by the serial transmission circuit, the serialized movable body detection data is input from the game board side serial transmission circuit to the motor drive board serial I/O port of the peripheral control MPU4150a via the peripheral control input circuit. There is. The peripheral control MPU 4150a is configured to exchange various data between the peripheral control board 4140 and the motor drive board 4180 by switching the input/output of the motor drive board serial I/O port.

The peripheral control MPU 4150a has a built-in watchdog timer (hereinafter, referred to as “peripheral control built-in WDT”), and its own system runs out of control by using the peripheral control built-in WDT and the peripheral control external WDT 4150e together. Is diagnosed.

[7-4-1a. Peripheral control MPU]
Next, the peripheral control MPU 4150a, which is a microcomputer, will be described. As shown in FIG. 18, the peripheral control MPU 4150a has a peripheral control CPU core 4150aa as the center, a peripheral control internal RAM 4150ab, a peripheral control DMA (abbreviation of Direct Memory Access) controller 4150ac, a peripheral control bus controller 4150ad, and peripheral control various serial I. /O port 4150ae, peripheral control built-in WDT 4150af, peripheral control various parallel I/O ports 4150ag, peripheral control analog/digital converter (hereinafter referred to as peripheral control A/D converter) 4150ak, and the like.

The peripheral control CPU core 4150aa reads/writes various data from/to the peripheral control built-in RAM 4150ab and the peripheral control DMA controller 4150ac via the internal bus 4150ah, while the peripheral control built-in serial I/O port 4150ae, the peripheral control built-in WDT 4150af, Peripheral control Various parallel I/O ports 4150ag and peripheral control A/D converter 4150ak are read/written via the internal bus 4150ah, peripheral control bus controller 4150ad, and peripheral bus 4150ai.

Further, the peripheral control CPU core 4150aa reads various data into the peripheral control ROM 4150b via the internal bus 4150ah, the peripheral control bus controller 4150ad, and the external bus 4150h, while the peripheral control RAM 4150c, the peripheral control SRAM 4150d, and the power supply. Various data is read from and written to the consumption status history RAM 4150f via the internal bus 4150ah, the peripheral control bus controller 4150ad, and the external bus 4150h.

The peripheral control DMA controller 4150ac includes storage devices such as the peripheral control built-in RAM 4150ab, the peripheral control ROM 4150b, the peripheral control RAM 4150c, and the peripheral control SRAM 4150d, the peripheral control various serial I/O ports 4150ae, the peripheral control built-in WDT 4150af, and the peripheral control various parallel I. The DMA/O port 4150ag and the input/output device such as the peripheral control A/D converter 4150ak are dedicated controllers that independently perform data transfer without going through the peripheral control CPU core 4150aa. ~ DMA3 has four channels.

Specifically, the peripheral control DMA controller 4150ac includes a storage device for the peripheral control built-in RAM 4150ab built in the peripheral control MPU 4150a, various peripheral control built-in serial I/O ports 4150ae, and peripheral built-in WDT4150af. , Peripheral control parallel I/O ports 4150ag, and peripheral control A/D converters 4150ak and other input/output devices for independent data transfer without the peripheral control CPU core 4150aa. Further, while reading and writing to the storage device of the peripheral control built-in RAM 4150ab via the internal bus 4150ah, various peripheral control serial I/O ports 4150ae, peripheral control built-in WDT 4150af, peripheral control various parallel I/O ports 4150ag, and Reading/writing is performed on the input/output device such as the peripheral control A/D converter 4150ak via the peripheral control bus controller 4150ad and the peripheral bus 4150ai.

The peripheral control DMA controller 4150ac is a storage device such as a peripheral control ROM 4150b, a peripheral control RAM 4150c, and a peripheral control SRAM 4150d externally attached to the peripheral control MPU 4150a, and various peripheral control serial I/Os built in the peripheral control MPU 4150a. Between the O port 4150ae, the peripheral control built-in WDT 4150af, the peripheral control various parallel I/O ports 4150ag, and the peripheral control A/D converter 4150ak and other input/output devices without passing through the peripheral control CPU core 4150aa, In order to perform data transfer independently, the peripheral control ROM 4150b, the peripheral control RAM 4150c, the peripheral control SRAM 4150d, and other storage devices are read and written via the peripheral control bus controller 4150ad and the external bus 4150h, while various peripheral control various types are performed. For peripheral I/O port 4150ae, peripheral control built-in WDT 4150af, peripheral control various parallel I/O ports 4150ag, peripheral control A/D converter 4150ak, and other input/output devices, peripheral control bus controller 4150ad and peripheral bus 4150ai are used. Read and write.

The peripheral control bus controller 4150ad controls the internal bus 4150ah, the peripheral bus 4150ai, and the external bus 4150h, the central processing unit of the peripheral control MPU core 4150aa, the peripheral control internal RAM 4150ab, the peripheral control ROM 4150b, the peripheral control RAM 4150c, and the peripheral control. Various devices such as a storage device such as SRAM 4150d and various input/output devices such as peripheral control various serial I/O port 4150ae, peripheral control built-in WDT 4150af, peripheral control various parallel I/O port 4150ag, and peripheral control A/D converter 4150ak It is a dedicated controller for exchanging various data between them.

Peripheral control Various serial I/O ports 4150ae are game board side decorative board serial I/O ports, motor drive board serial I/O ports, frame side decorative board serial I/O ports, frame decoration drive amplifier board motors It has a serial I/O port for a main control board, a serial I/O port for acquiring operation unit information, and a LOCKN signal output request serial I/O port.

The peripheral control built-in watchdog timer (WDT with built-in peripheral control) 4150af is a timer for monitoring whether the system of the peripheral control MPU 4150a is out of control. When this timer is up, it is reset by hardware. It has become. That is, when the watchdog timer is started, the peripheral control CPU core 4150aa does not output a clear signal for clearing the timer to the peripheral control built-in WDT 4150af within a certain period (until the timer expires), and then resets. This will be the case. When the peripheral control CPU core 4150aa starts the watchdog timer and outputs a clear signal to the peripheral control built-in WDT 4150af within a certain period of time, the timer count can be restarted, so that it is not reset.

Peripheral control Various parallel I/O ports 4150ag outputs various latch signals such as a game board side motor drive latch signal and a door side motor drive light emission latch signal, and also outputs a clear signal to the peripheral control external WDT 4150e, and a game. Based on the game balls that enter the various winning openings such as the first starting opening 2101, the second starting opening 2102, the general winning openings 2104, 2201 and the big winning opening 2103 provided on the board 4 shown in FIG. Each time the number of game balls scheduled to be paid out reaches a predetermined number of balls (in the present embodiment, it is set to 10 balls), the main prize ball number information is transmitted to inform that fact. The number information output signal is output to the external terminal board 784, or the pachinko gaming machine 1 consumes the power when the power is turned off (immediately before the power is turned off) based on the power consumption status history information stored and held in the power consumption status RAM 4150f. The power saving mode information output signal is output to the external terminal board 784 as the power saving mode information for transmitting the power saving mode transition state in which the power consumption is grasped at the time of power recovery and the power consumed by the pachinko gaming machine 1 is suppressed. The detection signals from various detection switches for outputting and detecting the original position and the movable position of various movable bodies provided on the game board 4 are serialized by the game board side serial transmission circuit (not shown) provided on the motor drive board 4180. Then, the movable body information acquisition latch signal for receiving the serialized movable body detection data from the game board side serial transmission circuit at the motor drive board serial I/O port of the peripheral control MPU 4150a is output. The output control of the main prize ball number information output signal and the output control of the power saving mode information output signal are executed in the peripheral control unit 1 ms timer interrupt process described later.

The peripheral control A/D converter 4150ak is electrically connected to the volume adjusting volume 4140a, and the resistance value is changed by rotating the knob of the volume adjusting volume 4140a, and the resistance at the rotational position of the knob is changed. The voltage divided by the value is converted from an analog value to a digital value, and is converted to a value of 1024 steps from value 0 to value 1023. In the present embodiment, the value of 1024 levels is divided into 7 and managed as substrate volumes 0 to 6. The board volume 0 is set to mute, the board volume 6 is set to the maximum volume, and the volume is set to increase from the board volume 0 to the board volume 6. The peripheral control MPU 4150a (peripheral control CPU core 4150aa) controls the liquid crystal and the sound control unit 4160 (VDP4160a with a built-in sound source, which will be described later) so that the volume is set to the substrate volumes 0 to 6, and the speaker provided in the main frame 3 Music and sound effects are made to flow from the speaker housed in the box 820 and the speaker 130 provided at the door frame 5. In this way, by adjusting the volume based on the turning operation of the knob portion, music and sound effects are made to flow from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5. ..

In the present embodiment, in addition to music and sound effects, a notification sound for notifying a clerk or the like in the hall of a malfunction of the pachinko gaming machine 1 or a fraudulent activity on the pachinko gaming machine 1, contents relating to game production, etc. (For example, the screen unfolded on the game board side effect display unit 1900 is rendered as a more powerful one, or it is announced that there is a high possibility of shifting to a game state that is advantageous to the player. ) Also flows from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, but the notification sound and the notification sound are adjusted in volume based on the turning operation of the knob portion. The system controls the liquid crystal and sound control unit 4160 (VDP4160a with a built-in sound source, which will be described later) from the mute to the maximum volume by the peripheral control MPU4150a (peripheral control CPU core 4150aa). Can be adjusted. The volume adjusted by this program is different from the above-described seven levels of the substrate volume, and it is possible to smoothly change from mute to maximum volume. Thus, for example, even when a store clerk in the hall or the like rotates the knob of the volume adjusting volume 4140a to set the volume low, the speaker and the door housed in the speaker box 820 provided in the main body frame 3 are closed. Although the sound produced by the speaker 130 provided in the frame 5 and the effect sound such as the sound effect are reduced, when the pachinko game machine 1 is in trouble or when the player is committing an illegal act, the volume of the sound is high. In the form, the notification sound set to the maximum volume) can be played. Therefore, even if the volume of the effect sound is reduced, it is possible to prevent the clerk or the like in the hall from becoming less likely to notice a malfunction or a player's cheating by the notification sound. Also, based on the current board volume set by the volume adjustment based on the turning operation of the knob, the volume of the advertising sound is reduced so as not to disturb the music or the sound effect, while There is a possibility of increasing the volume of the sound played to increase the volume of the music and sound effects, and also to produce a more powerful screen on the game board side effect display unit 1900, or to shift to a game state advantageous for the player. You can also announce that it is expensive.

[7-4-1b. Peripheral control ROM]
The peripheral control ROM 4150b stores in advance various control programs for controlling the peripheral control unit 4150, the liquid crystal and sound control unit 4160, the RTC control unit 4165, various data, various control data, and various schedule data. The various schedule data includes screen generation schedule data for generating a screen to be drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e), light emission mode generation schedule data for generating various LED light emission modes, and music. And sound generation schedule data for generating sound effects, electric drive source schedule data for generating driving modes of electric drive sources such as motors and solenoids, and the number of game balls to be paid out as prize balls in advance. The main prize ball information output signal schedule data for generating a main prize ball information output signal for transmitting to the hall computer that the number of balls has reached the predetermined number (10 balls in the present embodiment) as main prize ball information is stored. is there.

The screen generation schedule data is configured by arranging screen data defining the screen configuration in time series, and there is screen generation schedule data for the game board side effect display unit 1900 (liquid crystal panel 5000e), and drawing ( The order of screens to be displayed is specified. The light emission mode generation schedule data is configured such that light emission data defining the light emission mode is arranged in time series, and the light emission mode generation schedule data for the plurality of LEDs provided on each decorative board of the game board 4 and the door. There is a light emitting mode generation schedule data for a plurality of LEDs provided on each decorative substrate of the frame 5, and the order of the light emitting modes is defined respectively. In addition, the schedule data for light emission mode generation for the plurality of LEDs provided on each decorative board of the game board 4 includes, in addition to the content for defining the light emission mode, a plurality of light guide plates included in the game board side effect display unit 1900. Among them, the content for specifying (designating) one light guide plate used as a backlight is included in the emission data and arranged in time series.

The sound generation schedule data is configured by arranging sound command data in time series, and defines the order in which music and sound effects flow. The sound command data includes an output channel number for instructing which output channel is to be used among a plurality of output channels of the built-in sound source of the sound source built-in VDP 4160a of the liquid crystal and sound control unit 4160, which will be described later, and the sound source built-in VDP 4160a. Of the plurality of tracks in the built-in sound source, the track number for instructing which track the sound data such as music and sound effect is to be incorporated is defined. The electric drive source schedule data is configured by arranging drive data of electric drive sources such as motors and solenoids in time series, and defines the operation of electric drive sources such as motors and solenoids. The main award ball information output signal schedule data indicates that the number of game balls to be paid out as award balls has reached a predetermined number (10 balls in the present embodiment) as a main award ball information. The output waveform data for generating the main prize ball information output signal to be transmitted to the computer is arranged in time series, and the output waveform of the main prize ball information output signal is defined.

Various control programs stored in the peripheral control ROM 4150b may be directly read from the peripheral control ROM 4150b and executed, and may be copied to various control program copy areas of the peripheral control RAM 4150c described later at the time of power-on. Some of them are read and executed. In addition, various data, various control data, and various schedule data stored in the peripheral control ROM 4150b may be directly read from the peripheral control ROM 4150b, or when power is turned on in various control data copy areas of the peripheral control RAM 4150c described later. In some, the copied one is read out.

[7-4-1c. Peripheral control RAM]
As shown in FIG. 18, the peripheral control RAM 4150c externally attached to the peripheral control MPU 4150a is a backup that exclusively stores, among the various types of information updated by executing various control programs, those to be backed up. A management target work area 4150ca, a backup first area 4150cb and a backup second area 4150cc for exclusively storing a copy of various information stored in this backup management target work area 4150ca, and a peripheral control ROM 4150b. The various control program copy area 4150cd for exclusively storing the copied various control programs, and the copied various data, various control data, various schedule data, etc. stored in the peripheral control ROM 4150b. Various control data copy areas 4150ce stored exclusively, and a backup non-management target work area 4150cf that stores only information that is not a backup target among various information updated by executing various control programs, Is provided.

When the power of the pachinko gaming machine 1 is turned on (including when power is restored due to momentary power failure or power failure), the value 0 is forcibly written to the backup non-managed work area 4150cf and zero-cleared. For the backup management target work area 4150ca, the backup first area 4150cb, and the backup second area 4150cc, the power-on status command (see FIG. 45) from the main control board 4100 when the pachinko gaming machine 1 is powered on is RAM clear. This is for instructing the start of production and the game state (for example, for instructing the start of production when the operation switch 860a shown in FIG. 14 is operated within a predetermined period after the power is turned on). Is cleared to zero.

The backup management target work area 4150ca is performance information that is various information updated in the peripheral control unit steady process executed each time a V blank signal from the liquid crystal and VDP 4160a with a built-in sound source of the sound control unit 4160, which will be described later, is input. Bank0 (1fr), which stores 1fr) as a backup target, and performance information (1ms), which is various information updated in the peripheral control unit 1ms timer interrupt process executed every time a 1ms timer interrupt described later occurs. It is composed of Bank 0 (1 ms) that is stored exclusively as a backup target. Here, the names of Bank0 (1fr) and Bank0 (1ms) will be briefly described. "Bank" is a minimum management unit that represents the size of a storage area for storing various types of information, and is "Bank". The following "0" means that it is a storage area that is normally used for storing various information updated by executing various control programs. In other words, “Bank0” means that the size of the storage area that is normally used is the minimum management unit. Then, “Bank1”, “Bank2”, “Bank3”, and “Bank4” provided in an area extending from a backup first area 4150cb to a backup second area 4150cc, which will be described later, are the same storage areas as “Bank0”. It is meant to have a size. As will be described later, “(1fr)” means that when the sound source built-in VDP 4160a outputs drawing data for one screen (one frame) to the game board side effect display unit 1900 (liquid crystal panel 5000e), the screen from the peripheral control MPU4150a. Since the V blank signal indicating that the data can be received is output to the peripheral control MPU4150a, the peripheral circuit control MPU4150a outputs the V blank signal every time when the V blank signal is input, in other words, every one frame (1 frame). From the place where the control unit steady process is executed, they are respectively added to "Bank0", "Bank1", "Bank2", "Bank3", and "Bank4" (effect information (1fr) and effect backup information (described below). 1fr) is also used with the same meaning). As will be described later, "(1ms)" means that the peripheral control unit 1ms timer interrupt process is executed every time a 1ms timer interrupt occurs, so that "Bank0", "Bank1", "Bank2", "Bank3", And “Bank4” (also used for production information (1 ms) and production backup information (1 ms) described later with the same meaning).

Bank0 (1fr) has a gaming board side peripheral control MPU control target LED transmission data storage area 4150caa, a frame side peripheral control MPU control target LED transmission data storage area 4150cab, a reception command storage area 4150cac, an RTC information acquisition storage area 4150cad. , And a schedule data storage area 4150cae are provided. The gaming board side peripheral control MPU control target LED transmission data storage area 4150caa is a plurality of gaming board side peripheral control MPU control objects, which are control objects to be directly controlled by the peripheral control MPU 4150a in each decorative board of the gaming board 4. This is a storage area in which game board side light emission data SL-DAT for outputting a lighting signal, a blinking signal or a gradation lighting signal to a plurality of LEDs (decorative LEDs) provided on each of the decorative substrates is set. The frame-side peripheral control MPU control target LED transmission data storage area 4150cab includes a plurality of frame-side peripheral control MPU control target decorations, which are control targets to be directly controlled by the peripheral control MPU 4150a, among the decorative substrates of the door frame 5. This is a storage area in which frame side light emission data STL-DAT for outputting a lighting signal, a blinking signal or a gradation lighting signal to a plurality of LEDs (decorative LEDs) provided on each of the substrates is set. The received command storage area 4150cac is a storage area in which various commands transmitted from the main control board 4100 are received and the received various commands are set. The RTC information acquisition storage area 4150cad is a storage area in which various information acquired from the RTC control unit 4165 (RTC internal RAM 4165aa of the RTC 41654a described later) is set. The schedule data storage area 4150cae is a storage area in which various schedule data corresponding to the received command are set based on the command received from the main control board 4100 (main control MPU 4100a). In the schedule data storage area 4150cae, various schedule data copied from the peripheral control ROM 4150b to the various control data copy areas 4150ce are read and set, and in other cases, various schedule data are directly read from the peripheral control ROM 4150b. Some are set.

In Bank 0 (1 ms), the frame decoration drive amplifier board side motor transmission data storage area 4150caf, the motor drive board side transmission data storage area 4150cag, the movable body information acquisition storage area 4150cah, and the operation unit information acquisition storage area 4150cai, and drawing A state information acquisition storage area 4150cak and the like are provided. Door side motor drive data STM-DAT for outputting a drive signal to an electric drive source such as a dial drive motor 414 provided in the door frame 5 is stored in the frame decoration drive amplifier board side motor transmission data storage area 4150caf. A storage area to be set, and a motor drive board side transmission data storage area 4150cag for outputting a drive signal to an electric drive source such as a motor or a solenoid that operates various movable bodies provided in the game board 4. The game board side motor drive data SM-DAT is a storage area in which the movable body information acquisition storage area 4150cah is provided in the game board 4 based on detection signals from various detection switches provided in the game board 4. The operation unit information acquisition storage area 4150cai is a storage area in which various kinds of information obtained by acquiring the original positions and movable positions of various movable bodies are set, and the operation unit information acquisition storage area 4150cai is based on detection signals from various detection switches provided in the operation unit 400. Information (eg, dial operation unit 401 created based on detection signals from various detection switches provided in the operation unit 400) that has acquired the rotation (rotation direction) of the dial operation unit 401 and the operation of the pressing operation unit 405. Rotation history information (rotation direction), operation history information of the pressing operation unit 405, etc.) is set in the drawing state information acquisition storage area 4150cak, and the frame decoration drive amplifier board 194 is the peripheral control board. 4140 receives the drawing data from the sound source built-in VDP 4160a and determines that the received drawing data is abnormal data, the peripheral control board 4140 and the frame decoration drive amplifier are output based on the LOCKN signal output to notify the fact. This is a storage area in which various kinds of information obtained from the frequency of defects and the occurrence state of defects during connection with the board 194 are set.

In addition, the game board side peripheral control MPU control target LED transmission data storage area 4150caa and the frame side peripheral control MPU control target LED transmission data storage area 4150cab of Bank0 (1fr), and the frame decoration drive amplifier board side of Bank0 (1ms) The motor transmission data storage area 4150caf and the motor drive board side transmission data storage area 4150cag are each divided into two areas, a first area and a second area.

The game board side peripheral control MPU control target LED transmission data storage area 4150caa becomes the first area of the game board side peripheral control MPU control target LED transmission data storage area 4150caa when the peripheral control unit steady process described later is executed. When the game board side light emission data SL-DAT is set and the next peripheral control unit steady process is executed, the game board side light emission is performed in the second area of the game board side peripheral control MPU control target LED transmission data storage area 4150caa. The data SL-DAT is set, and each time the peripheral control unit steady process is executed, the first and second areas of the game board side peripheral control MPU control target LED transmission data storage area 4150caa are set. The game board side light emission data SL-DAT is alternately set. Peripheral control unit steady process is executed, for example, in the current peripheral control unit steady process, game board side light emission data SL-DAT is set in the second area of the game board side peripheral control MPU control target LED transmission data storage area 4150caa. When the peripheral control unit steady process is executed last time, based on the game board side light emission data SL-DAT set in the first area of the game board side peripheral control MPU control target LED transmission data storage area 4150caa It is designed to proceed with processing.

When the peripheral control unit steady process is executed, the frame-side peripheral control MPU control target LED transmission data storage area 4150cab emits the frame-side light in the first area of the frame-side peripheral control MPU control target LED transmission data storage area 4150cab. When the data STL-DAT is set and the next peripheral control unit steady process is executed, the frame side light emission data STL-DAT is set in the second area of the frame side peripheral control MPU control target LED transmission data storage area 4150cab. Each time the peripheral control unit steady process is executed, the frame side light emission data STL-DAT is stored in the first and second areas of the frame side peripheral control MPU control target LED transmission data storage area 4150cab. It is set alternately. When the peripheral control unit steady process is executed and, for example, when the frame side light emission data STL-DAT is set in the second region of the frame side peripheral control MPU control target LED transmission data storage region 4150cab in the current peripheral control unit steady process , When the previous peripheral control unit steady process is executed, the process proceeds based on the frame side light emission data STL-DAT set in the first area of the frame side peripheral control MPU control target LED transmission data storage area 4150cab. It is like this.

The frame decoration drive amplifier board side motor transmission data storage area 4150caf is provided with a door in the first area of the frame decoration drive amplifier board side motor transmission data storage area 4150caf when the peripheral control unit 1ms timer interrupt processing described later is executed. When the side motor drive data STM-DAT is set and the next peripheral controller 1ms timer interrupt process is executed, the door side motor drive data STM is set in the second area of the frame decoration drive amplifier board side motor transmission data storage area 4150caf. -When DAT is set and the peripheral controller 1ms timer interrupt process is executed, the door side is set in the first and second areas of the frame decoration drive amplifier board side motor transmission data storage area 4150caf. Motor drive data STM-DAT are alternately set. The peripheral control unit 1ms timer interrupt process is executed. When it is set, the door side motor drive data STM-DAT set in the first area of the frame decoration drive amplifier board side motor transmission data storage area 4150caf when the peripheral control unit 1ms timer interrupt process is executed last time is set. The processing is carried out based on this.

When the peripheral controller 1ms timer interrupt processing is executed, the motor drive board side transmission data storage area 4150cag sets the game board side motor drive data SM-DAT in the first area of the motor drive board side transmission data storage area 4150cag. When the next peripheral controller 1ms timer interrupt process is executed, the game board side motor drive data SM-DAT is set in the second area of the motor drive board side transmission data storage area 4150cag. Every time the peripheral controller 1ms timer interrupt process is executed, the game board side motor drive data SM-DAT is alternately set in the first area and the second area of the motor drive board side transmission data storage area 4150cag. Peripheral controller 1ms timer interrupt processing is executed, for example, in the peripheral controller 1ms timer interrupt processing this time, game board side motor drive data SM-DAT is set in the second area of the motor drive board side transmission data storage area 4150cag. Sometimes, when the peripheral controller 1ms timer interrupt process is executed last time, the process proceeds based on the game board side motor drive data SM-DAT set in the first area of the motor drive board side transmission data storage area 4150cag. It is like this.

Next, the backup first area 4150cb and the backup second area 4150cc that exclusively store the copied copy of the effect information, which is various information stored in the backup management target work area 4150ca, will be described. In the backup first area 4150cb and the backup second area 4150cc, two pairs each having two banks as one pair are managed as one page. Performance information (1fr), which is the content stored in Bank0 (1fr), which is a storage area that is normally used, is used as performance backup information (1fr) each time the peripheral control unit steady process is executed for each frame (1frame). In addition, the performance information (1 ms) which is the content that is copied at high speed to the backup first area 4150cb and the backup second area 4150cc by the peripheral control DMA controller 4150ac and is stored in Bank0 (1ms) which is a storage area that is normally used. As performance backup information (1 ms), by the peripheral control DMA controller 4150ac in the backup first area 4150cb and the backup second area 4150cc each time the peripheral controller 1ms timer interrupt processing is executed every time a 1ms timer interrupt occurs. It is copied quickly. The consistency of one page is determined by whether or not the contents of the two banks forming the page match.

Specifically, in the backup first area 4150cb, two pairs of Bank1 (1fr) and Bank2 (1fr) and one pair of Bank1 (1ms) and Bank2 (1ms) are managed as one page. ing. The contents stored in Bank0 (1fr), which is a storage area that is normally used, are stored in the peripheral control DMA in Bank1 (1fr) and Bank2 (1fr) every time the peripheral control unit steady process is executed for each frame (1frame). The memory that is copied at high speed by the controller 4150ac and that is stored in Bank0 (1 ms), which is a storage area that is normally used, is stored every time a peripheral controller 1 ms timer interrupt process is executed every time a 1 ms timer interrupt occurs. The peripheral control DMA controller 4150ac copies the data to Bank1 (1 ms) and Bank2 (1 ms) at high speed, and the consistency of this page is determined by whether or not the contents of Bank1 (1fr) and Bank2 (1fr) match. It is performed depending on whether or not the contents of Bank1 (1 ms) and Bank2 (1 ms) match.

Further, in the backup second area 4150cc, two pairs of Bank3 (1fr) and Bank4 (1fr) and one pair of Bank3 (1ms) and Bank4 (1ms) are managed as one page. The contents stored in Bank0 (1fr), which is a storage area that is normally used, are stored in the peripheral control DMA in Bank3 (1fr) and Bank4 (1fr) every time the peripheral control unit steady process is executed for each frame (1frame). The memory that is copied at high speed by the controller 4150ac and that is stored in Bank0 (1 ms), which is a storage area that is normally used, is stored every time a peripheral controller 1 ms timer interrupt process is executed every time a 1 ms timer interrupt occurs. The peripheral control DMA controller 4150ac copies the data to Bank3 (1 ms) and Bank4 (1 ms) at high speed, and the consistency of this page is determined depending on whether the contents of Bank3 (1fr) and Bank4 (1fr) match. It is performed depending on whether or not the contents of Bank3 (1 ms) and Bank4 (1 ms) match.

As described above, in the present embodiment, the backup first area 4150cb has one pair of Bank1 (1fr) and Bank2 (1fr) and one pair of Bank1 (1ms) and Bank2 (1ms), that is, two pairs in total. The backup second area 4150cc is an area for managing as a page, and the backup second area 4150cc has two pairs of Bank3 (1fr) and Bank4 (1fr) as one pair and Bank3 (1ms) and Bank4 (1ms) as one pair. This is an area for managing as one page. Different ID codes are stored at the beginning and the end of each page, that is, at the beginning and the end of the backup first area 4150cb and the backup second area 4150cc.

Further, in the present embodiment, the effect information (1fr), which is the content stored in Bank0 (1fr), which is a storage area that is normally used, is the peripheral control unit for each frame (1frame) as effect backup information (1fr). Every time the regular processing is executed, the contents are copied to the backup first area 4150cb and the backup second area 4150cc at high speed by the peripheral control DMA controller 4150ac and stored in Bank0 (1 ms) which is a storage area normally used. The production information (1ms) is, as production backup information (1ms), every time the peripheral controller 1ms timer interrupt process is executed every time a 1ms timer interrupt occurs, the backup first area 4150cb and the backup second area 4150cc. The peripheral control DMA controller 4150ac is designed to perform high-speed copying, but the programs for executing high-speed copying by these peripheral control DMA controller 4150ac are common. That is, in the present embodiment, the effect information (1fr) and the effect information (1ms) are managed by a common management method (execution of a common program).

[7-4-1d. Peripheral control SRAM]
The peripheral control SRAM 4150d externally attached to the peripheral control MPU 4150a includes a backup management target work area 4150da for exclusively storing the backup target among various information updated by executing various control programs. A backup first area 4150db and a backup second area 4150dc for exclusively storing a copy of various information stored in the backup management target work area 4150da are provided. The contents stored in the peripheral control SRAM 4150d are power-on state commands from the main control board 4100 when the power of the pachinko gaming machine 1 is turned on (including power failure due to momentary power failure or power failure) (see FIG. 45). ) Is for instructing the RAM clear effect start and the game state (for example, instructing the effect start when the operation switch 860a shown in FIG. 14 is operated within a predetermined period from the time of turning on the power source). It is not cleared to zero. This point is completely different from the point that the backup management target work area 4150ca, the backup first area 4150cb, and the backup second area 4150cc of the peripheral control RAM 4150c are zero-cleared. Further, when the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400 is operated within a predetermined time after the power of the pachinko gaming machine 1 is turned on, a screen for performing the setting mode is displayed on the game board side effect display unit 1900 (liquid crystal). It is designed to be displayed on the panel 5000e). By operating the dial operation unit 401 and the pressing operation unit 405 of the operation unit 400 according to the screen of this setting mode, for each content (item) stored in the peripheral control SRAM 4150d (for example, a history of occurrence of a jackpot gaming state, etc.) While the contents can be cleared, the contents (items) stored in the peripheral control RAM 4150c are not displayed at all and cannot be cleared in the setting mode. Also in this respect, the peripheral control RAM 4150c and the peripheral control SRAM 4150d are completely different.

The backup management target work area 4150da is effect information (SRAM) that is various information that continues over days (for example, information for managing a history of occurrence of a big hit game state and a special effect flag). (For example, information) is dedicatedly stored as Bank 0 (SRAM) for backup. Here, the name of Bank0 (SRAM) will be briefly described. As described above, "Bank" is the minimum management unit indicating the size of the storage area for storing various types of information, and is "Bank". The following "0" means that it is a storage area that is normally used for storing various information updated by executing various control programs. In other words, “Bank0” means that the size of the storage area that is normally used is the minimum management unit. Then, “Bank1”, “Bank2”, “Bank3”, and “Bank4” provided in an area extending from a backup first area 4150db to a backup second area 4150dc, which will be described later, are in the same storage area as “Bank0”. It is meant to have a size. "(SRAM)" is a backup target of various information stored in the peripheral control SRAM 4150d externally attached to the peripheral control MPU 4150a, and thus "Bank0", "Bank1", "Bank2", "Bank3". , And “Bank4” (the effect information (SRAM) and effect backup information (SRAM) described later are also used in the same meaning).

Next, the backup first area 4150db and the backup second area 4150dc that exclusively store the copied copy of the effect information (SRAM) that is various information stored in the backup management target work area 4150da will be described. The backup first area 4150db and the backup second area 4150dc are managed with two banks as one pair and one pair as one page. The effect information (SRAM), which is the content stored in Bank0 (SRAM), which is a storage area that is normally used, is used as effect backup information (SRAM) every time the peripheral control unit steady process is executed for each frame (1 frame). Then, the peripheral control DMA controller 4150ac copies the backup first area 4150db and the backup second area 4150dc at high speed. The consistency of one page is determined by whether or not the contents of the two banks forming the page match.

Specifically, the backup first area 4150db has Bank1 (SRAM) and Bank2 (SRAM) as one pair, and this one pair is managed as one page. The contents stored in Bank0 (SRAM), which is a storage area that is normally used, are stored in Bank1 (SRAM) and Bank2 (SRAM) peripheral control DMA every time the peripheral control unit steady process is executed for each frame (1 frame). It is copied at high speed by the controller 4150ac, and the consistency of this page is determined by whether or not the contents of Bank1 (SRAM) and Bank2 (SRAM) match.

Further, the backup second area 4150dc has Bank3 (SRAM) and Bank4 (SRAM) as one pair, and this one pair is managed as one page. The contents stored in Bank0 (SRAM), which is a storage area that is normally used, are stored in the peripheral control DMA in Bank3 (SRAM) and Bank4 (SRAM) every time the peripheral control unit steady process is executed for each frame (1 frame). It is copied at high speed by the controller 4150ac, and the consistency of this page is determined by whether or not the contents of Bank3 (SRAM) and Bank4 (SRAM) match.

As described above, in the present embodiment, the backup first area 4150db is an area for managing Bank1 (SRAM) and Bank2 (SRAM) as one pair, and managing this one pair as one page. 4150dc is an area for managing one pair of Bank3 (SRAM) and Bank4 (SRAM) as one page. Different ID codes are stored at the beginning and the end of each page, that is, at the beginning and the end of the backup first area 4150db and the backup second area 4150dc.

[7-4-1e. Power consumption history RAM]
The power consumption status history RAM 4150f externally attached to the peripheral control MPU 4150a samples the value (power consumption suppression stage) transmitted by the power consumption suppression signal from the power supply board 851 at a predetermined cycle by the peripheral control MPU 4150a (the peripheral described later). This is stored and held as power consumption status history information (in the power consumption status history information creation processing in the control unit 1 ms timer interrupt processing). Specifically, the peripheral control MPU 4150a executes a peripheral control unit 1ms timer interrupt process each time a 1ms timer interrupt described later occurs, and in the peripheral control unit 1ms timer interrupt process, a power consumption suppression signal from the power supply board 851 is generated. Is sampled and sequentially stored in the power consumption status history RAM 4150f as power consumption status history information. In the present embodiment, this power consumption status history information can store and hold the value (power consumption suppression stage) transmitted by the power consumption suppression signal for 3000 times as the number of samplings, and the power consumption suppression signal sampled this time is When the transmitted value (power consumption suppressing stage) is stored and held, the value transmitted by the power consumption suppressing signal already sampled up to the previous time (power consumption suppressing stage) is shifted one by one so that the values are arranged in time series. When the number of samplings reaches 3000, the value transmitted by the power consumption suppression signal (the power consumption suppression stage) is stored and held, and the value transmitted by the power consumption suppression signal (power consumption suppression stage) is stored. Every time the power consumption suppressing signal is stored and held, the value transmitted by the oldest sampled power consumption suppressing signal (power consumption suppressing step) is sequentially discarded one by one. In other words, the power consumption status history information includes the latest 3000 times including the value (power consumption suppression stage) transmitted by the power consumption suppression signal sampled this time (in other words, the peripheral control MPU 4150a executes the peripheral control unit 1 ms timer interrupt process). Each time, the value (power consumption suppression stage) transmitted by the power consumption suppression signal from the power supply board 851 is sampled and sequentially stored in the power consumption status history RAM 4150f as the power consumption status history information. Is executed 3000 times, the values transmitted by the power consumption suppression signal for 3 seconds (=1 ms×3000 times) (power consumption suppression stage) are arranged in time series.

[7-4-1f. Power saving mode transition notification LED]
The power saving mode transition notification LED 4150k is used to restore the power status consumed by the pachinko gaming machine 1 at the time of power shutdown (immediately before power shutdown) based on the power consumption status history information stored and held in the power consumption status history RAM 4150f. In this case, the state of transition to the power saving mode at the time of power recovery that notifies the power consumption of the pachinko game machine 1 is notified. The power saving mode transition notification LED 4150k is not electrically connected to the peripheral control board 4140 via signal wiring, but is directly mounted on the peripheral control board 4140 and the peripheral control MPU 4150a controls the light emission mode. Has been done. In this embodiment, the power saving mode transition notification LED 4150k is of a surface mounting type and has a high-intensity single color that emits green light, and the lock staff shown in FIGS. When a key is inserted into the cylinder lock 1010 of 1000 to rotate, the closed state of the body frame 3 with respect to the outer frame 2 is released and the body frame 3 is opened with respect to the outer frame 2, the open side of the body frame 3 A power saving mode transition notification LED 4150k is directly soldered to the peripheral control board 4140 at a position where the main frame 3 is attached to the back side of the pachinko gaming machine 1 (that is, the back side of the game board 4) and the outer frame 2. A clerk such as a store clerk in the hall can visually check the light emitting mode of the power saving mode transition notification LED 4150k from the opening side of the main body frame 3 when opened.

Specifically, the peripheral control MPU 4150a stores the power consumption status history information stored and held in the power consumption status history RAM 4150f in the power recovery mode power saving mode transition determination processing in the peripheral control unit power-on processing to be described later that is executed at power recovery. Based on the above, the power status (power consumption suppression stage described later) consumed by the pachinko gaming machine 1 at the time of power shutdown (immediately before power shutdown) is specified, and it is determined whether or not to shift to the power saving mode at power recovery. The peripheral control MPU 4150a sets the light-emission mode of the power-saving mode transition notification LED 4150k to the non-power-saving notification mode (lighting state) when the determination result indicates that the power-saving mode during power recovery is not set, while the determination result indicates that the power-saving mode during power recovery has been determined. When it is to shift to, the light emission mode of the power saving mode shift notification LED 4150k is set to the power saving notification mode (light off state). A clerk such as a clerk in the hall turns the pachinko gaming machine 1 by inserting a key into the cylinder lock 1010 of the locking device 1000 to determine whether or not the pachinko gaming machine 1 is in a state of transitioning to the power saving mode at power recovery, By releasing the closed state of the body frame 3 with respect to the outer frame 2 and opening the body frame 3 with respect to the outer frame 2, it is possible to confirm by visually observing the light emission mode of the power saving mode transition notification LED 4150k.

Here, the reason why the surface mounting type LED which is directly soldered to the peripheral control board 4140 is adopted as the power saving mode transition notification LED 4150k will be briefly described. When the power saving mode transition notification LED 4150k is arranged apart from the peripheral control board 4140 and is electrically connected to the peripheral control board 4140 via signal wiring, for example, a staff member such as a clerk in the hall is working. When a finger or a tool is caught on the signal wiring and the connector of the signal wiring is disengaged from the peripheral control board 4140, or when the main body frame 3 is opened with respect to the outer frame 2, the signal wiring is in the gap on the closed side of the main body frame 3. When the main frame 3 is sandwiched and the main frame 3 is closed and the gap becomes small and the signal wiring is broken, it becomes difficult for the peripheral control MPU 4150a to control the light emission mode of the power saving mode transition notification LED 4150k. Because. In this embodiment, as the power saving mode transition notification LED 4150k, a surface mount type that is directly soldered to the peripheral control board 4140 is adopted, but it is a lead type that can be directly soldered to the peripheral control board 4140. Good.

[7-4-2. LCD and sound controller]
Drawing control of the game board side effect display unit 1900 (liquid crystal panel 5000e), light emission control of various LEDs, speakers housed in the speaker box 820 provided in the main body frame 3 and music played from the speaker 130 provided in the door frame 5. The liquid crystal and sound control unit 4160 for controlling sound such as sound effect and sound effect has a built-in sound source for controlling sound such as music and sound effect (hereinafter referred to as “internal sound source”). As shown in FIG. 17, the liquid crystal and sound control unit 4160 controls the drawing of the game board side effect display unit 1900 (liquid crystal panel 5000e) and the control target of each decorative board of the game board 4 which is directly controlled by itself. Light emission control of a plurality of LEDs (ornamental LEDs) provided on each of the plurality of game board side VDP control target decoration boards, and among the decoration boards of the door frame 5, the control object is directly controlled by itself. A VDP (abbreviation of Video Display Processor) 4160a with a built-in sound source that controls light emission of a plurality of LEDs (decorative LEDs) provided on each of the plurality of frame-side VDP control target decorative substrates, and a game board side effect display unit 1900. In addition to a plurality of various character data of the screen drawn (displayed) on the (liquid crystal panel 5000e), a predetermined screen (in the present embodiment, red (R): 50%, green (G): 50%, blue) (B): In addition to the dummy data for drawing a gray screen having 50%), a plurality of game boards, which are control objects to be directly controlled by the sound source built-in VDP 4160a, among the decorative boards of the game board 4 A plurality of game board side light emission mode setting image data for setting light emission modes of a plurality of LEDs (decorative LEDs) provided on each of the side VDP control target decoration boards, and a sound source of each of the decoration boards of the door frame 5 Plural door frame side light emission mode setting for setting the light emission mode of the plurality of LEDs (decorative LEDs) provided on each of the plurality of frame side VDP control target decorative substrates that are directly controlled by the built-in VDP 4160a A liquid crystal and sound control ROM 4160b for storing image data and a plurality of various sound data such as music and sound effects, a frame peripheral relay terminal board 868 and peripheral relay terminals as serialized music and sound effects as audio data. An audio data transmission IC 4160c for transmitting to the frame decoration drive amplifier board 194 via the board 882, serialized drawing data for the frame peripheral relay terminal board 868, and a peripheral decoration terminal board 882 for the frame decoration drive amplifier board 882. The LOCKN signal output request data, which is serial data output from the LOCKN signal output request serial I/O port built in the peripheral IC MPU 4150a of the peripheral control unit 4150 and the transmitter IC 4160d which transmits to the 194, is a plus signal and a minus signal. A signal from the differential circuit 4160e is input in addition to the signal output from the differential circuit 4160e that performs differential to and to the transmitter IC 4160d. In addition, when the signal from the differential circuit 4160e is input, the circuit is connected to transmit this signal, while when the signal from the differential circuit 4160e is not input, the signal is output from the transmitter IC 4160d. And a forced switching circuit 4160f that is circuit-connected to transmit the signal.

The peripheral control MPU 4150a of the peripheral control unit 4150 controls the peripheral control ROM 4150b of the peripheral control unit 4150 or the peripheral control RAM 4150c of the screen generation schedule data and the light emission mode generation schedule data corresponding to the command from the main control board 4100. Extracted from the data copy area 4150ce and set in the schedule data storage area 4150cae of the peripheral control RAM 4150c, the top screen data of the screen generation schedule data set in this schedule data storage area 4150cae and the head of the light emission mode generation schedule data The light emission data of is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or the various control data copy area 4150ce of the peripheral control RAM 4150c and output to the sound source built-in VDP 4160a, and then the V blank signal described later is input. , The next screen data following the first screen data and the next light emission data following the first light emission data according to the screen generation schedule data and the light emission mode generation schedule data set in the schedule data storage area 4150cae. It is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or the various control data copy areas 4150ce of the peripheral control RAM 4150c and output to the sound source built-in VDP 4160a. In this way, the peripheral control MPU 4150a, in accordance with the screen generation schedule data and the light emission mode generation schedule data set in the schedule data storage area 4150cae, the screen data arranged in time series in the screen generation schedule data, Each time the V blank signal is input, the light emission data arranged in time series in the light emission mode generating schedule data is output to the sound source built-in VDP 4160a one by one from the top screen data and one from the first light emission data. To do.

Further, the peripheral control MPU 4150a outputs the sound command data at the head of the sound generation schedule data corresponding to the command from the main control board 4100 from the peripheral control ROM 4150b of the peripheral control unit 4150 or the various control data copy areas 4150ce of the peripheral control RAM 4150c. It is extracted and set in the schedule data storage area 4150cae of the peripheral control RAM 4150c, and the sound command data at the head of the sound generation schedule data set in the schedule data storage area 4150cae is stored in the peripheral control ROM 4150b of the peripheral control unit 4150 or the peripheral control. After being extracted from the various control data copy areas 4150ce of the RAM 4150c and output to the sound source built-in VDP 4160a, the beginning of the sound according to the sound generation schedule data set in the schedule data storage area 4150cae when the V blank signal is input. The next sound command data following the command data is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c and output to the sound source built-in VDP 4160a. As described above, the peripheral control MPU 4150a receives the sound command data arranged in time series in the sound generation schedule data as the V blank signal according to the sound generation schedule data set in the schedule data storage area 4150cae. Each time, the sound command data at the head is output to the sound source built-in VDP 4160a one by one.

As described above, the peripheral control unit 4150 that performs the effect control controls the power-on process executed when the power is turned on as described above, and is executed after a predetermined time has elapsed from the time when the power is turned on and the effect operation. A peripheral control ROM 4150b for storing various control programs such as a sub-control program for controlling, various data, various control data, and various schedule data, and a V blank signal from a sound source built-in VDP 4160a of the liquid crystal and sound control unit 4160 described later are input. Since the peripheral control RAM 4150c that stores various information that continues across the peripheral control unit steady process that is executed every time, and the peripheral control SRAM 4150d that stores various information that continues across days, The peripheral control unit 4150 includes a peripheral control ROM 4150b, a peripheral control RAM 4150c, and a peripheral control SRAM 4150d that can store a plurality of types of information regarding effects. In addition, in the liquid crystal and sound control unit 4160, as described above, in addition to a plurality of various character data of the screen drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e), a predetermined screen is displayed. (In this embodiment, a gray screen having red (R): 50%, green (G): 50%, and blue (B): 50%) In addition to the dummy data for drawing, For setting the light emission mode of a plurality of LEDs (decorative LEDs) provided on each of the plurality of gaming board side VDP control target decorative boards, which are control objects to be directly controlled by the sound source built-in VDP 4160a, among the respective decorative boards Of a plurality of game board side light emission mode setting image data and a plurality of decorative boards of the door frame 5, a plurality of decorative boards provided on each of the frame side VDP control target decorative boards that are directly controlled by the sound source built-in VDP 4160a. Liquid crystal and sound control ROM 4160b for storing a plurality of door frame side light emitting mode setting image data for setting the light emitting mode of the LED (decorative LED) and a plurality of various sound data such as music and sound effects. Therefore, the liquid crystal and sound control unit 4160 is provided with a liquid crystal and sound control unit 4160 that can store a plurality of types of information regarding effects.

[7-4-2a. VDP with built-in sound source]
The VDP 4160a with a built-in sound source controlled by the peripheral control MPU 4150a has a built-in VRAM in addition to the built-in sound source described above (hereinafter, referred to as "built-in VRAM"). The VRAM may be provided in a frame memory separate from the VDP 4160a with a built-in sound source (that is, a RAM (frame memory) externally attached to the VDP 4160a with a built-in sound source). When the screen data and the light emission data are input from the peripheral control MPU 4150a, the sound source built-in VDP 4160a, based on the input screen data and the light emission data, as shown in FIG. The game board side character data for drawing in the display area of the liquid crystal panel 5000e included in the board side effect display unit 1900 (hereinafter, may be referred to as "display area of the game board side effect display unit 1900") and the above-mentioned character data. Dummy data for drawing a predetermined screen (gray screen having red (R): 50%, green (G): 50%, and blue (B): 50% in this embodiment) is extracted. Create sprite data and draw (display) one screen (one frame) on the game board side effect display unit 1900 (liquid crystal panel 5000e) and a predetermined screen (in the present embodiment, red (R): 50%, green (G): 50%, blue (B): gray screen with 50%) drawing data of one screen (one frame) for drawing (displaying) and built-in VRAM To generate.

The sound source built-in VDP 4160a can output the drawing data generated in the built-in VRAM from the channels CH1 and CH2. Specifically, the sound source built-in VDP 4160a is a VDP 4160a with a built-in sound source among screen data defining the configuration of a screen drawn on the game board side effect display unit 1900 (liquid crystal panel 5000e) and each decorative board of the game board 4. Is input from the peripheral control MPU4150a, and the light emission data defining the light emission mode of the plurality of LEDs (decorative LEDs) provided on each of the plurality of game board side VDP control target decoration substrates that are directly controlled by Then, according to the predetermined game board side generation rule, based on the input screen data, the game board side character data for drawing from the liquid crystal and sound control ROM 4160b in the display area of the game board side effect display unit 1900. The sprite data is extracted to create the game board side drawing data in the game board side drawing data area VRGN1a of the game board side display area VRGN1 provided on the built-in VRAM, and based on the input light emission data. Among the decorative boards of the game board 4 from the liquid crystal and sound control ROM 4160b, a plurality of LEDs provided on each of the plurality of game board-side VDP controlled decoration boards that are directly controlled by the sound source built-in VDP 4160a. Game board side display area VRGN1 provided on the built-in VRAM as the light guide plate information and the electric decoration information, which will be described later, as drawing data by extracting the game board side light emission mode setting image data for setting the light emitting mode of the decoration LED). It is generated in the game board side associated information area VRGN1b. Thereby, the light guide plate information and the electric decoration information are attached to the game board side drawing data of the screen drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e) according to the predetermined game board side generation rule. As a result, the drawing data generated in the game board side display area VRGN1 is output from the channel CH1. The drawing data generated in the game board side display area VRGN1 is referred to as a "game board side image object". The "predetermined game board side generation rule" will be described later.

Further, the sound source built-in VDP 4160a defines the configuration of a predetermined screen (a gray screen having red (R): 50%, green (G): 50%, and blue (B): 50% in this embodiment). Screen data and a plurality of LEDs (decorative LEDs) provided on each of a plurality of frame-side VDP control target decorative boards that are directly controlled by the sound source built-in VDP 4160a among the decorative boards of the door frame 5. When the light emission data defining the light emission mode is input from the peripheral control MPU 4150a, according to a predetermined door frame side generation rule, based on the input screen data, a predetermined screen from the liquid crystal and sound control ROM 4160b ( In the present embodiment, sprite data is created by extracting dummy data for drawing a red (R): 50%, green (G): 50%, blue (B): 50% gray screen). The door frame side drawing data is generated in the door frame side drawing data area VRGN2a of the door frame side display area VRGN2 provided on the built-in VRAM. Of the decoration boards of the door frame 5, the light emission mode of a plurality of LEDs (decorative LEDs) provided on each of the plurality of frame-side VDP control target decoration boards that are directly controlled by the sound source built-in VDP 4160a is set. The door frame side light emission mode setting image data for performing the operation is extracted, and the electric decoration information described later is generated as drawing data in the door frame side accompanying information area VRGN2b of the door frame side display area VRGN2 provided on the built-in VRAM. As a result, the door frame side drawing data of a predetermined screen (in the present embodiment, a gray screen having red (R): 50%, green (G): 50%, and blue (B): 50%) is electrically charged. The drawing data generated in the door frame side display area VRGN2 is output from the channel CH2 assuming that the decoration information is attached according to a predetermined door frame side generation rule. The drawing data generated in the door frame side display area VRGN2 is referred to as a "frame side image object". The "predetermined door frame side generation rule" will be described later.

When the drawing data output from the channel CH1 is output from the peripheral control board 4140 to the liquid crystal output board 3420, in the liquid crystal output board 3420, the game board side drawing data for the game board side effect display unit 1900 and a light guide plate described later. Information and lighting information. As a result, the liquid crystal output board 3420 outputs the game board side drawing data to the game board side effect display unit 1900 to display the screen on the game board side effect display unit 1900, and the game board side based on the light guide plate information. By selecting one of the various light guide plates of the effect display unit 1900, the selected light guide plate emits surface light, and the VDP4160a with a built-in sound source is directly controlled among the decorative boards of the game board 4 based on the illumination information. The plurality of LEDs (decorative LEDs) emit light by outputting signals to the plurality of LEDs (decorative LEDs) provided on each of the plurality of gaming board side VDP controlled decorative substrates that are controlled.

The drawing data output from the channel CH2 is output from the peripheral control board 4140 to the frame peripheral relay terminal board 868, the peripheral door relay terminal board 882, and the frame decoration drive amplifier board 194. Door frame side drawing data of a predetermined screen (in the present embodiment, a gray screen having red (R): 50%, green (G): 50%, and blue (B): 50%) and an electric power to be described later. It is separated into decoration information and. As a result, the frame decoration drive amplifier board 194, among the decoration boards of the door frame 5 on the basis of the electric decoration information, includes a plurality of frame-side VDP control object decoration boards that are directly controlled by the sound source built-in VDP 4160a. While the plurality of LEDs (decorative LEDs) emit light by outputting signals to the plurality of LEDs (decorative LEDs) provided for each, a predetermined screen (in the present embodiment, red (R): 50%, For the door frame side drawing data of green (G): 50% and blue (B): 50%), nothing is output to other electronic components and other substrates. In other words, in the drawing data output from the channel CH2, a predetermined screen (red (R): 50% in the present embodiment, in order to cut out (take out) the electric decoration information in the frame decoration drive amplifier board 194, Illumination information is attached to the door frame side drawing data of green (G): 50% and blue (B): 50% gray screen).

As described above, since the drawing data output from the channel CH1 is output from the peripheral control board 4140 to the game board side effect display unit 1900 via the liquid crystal output board 3420 as described above, the peripheral control board 4140 and the liquid crystal display. Since the output board 3420 and the game board side effect display unit 1900 are respectively attached to the game board 4, the length of wiring required for the path from the channel CH1 to the game board side effect display unit 1900 is short. On the other hand, as described above, the drawing data output from the channel CH2 is output from the peripheral control board 4140 to the frame decoration drive amplifier board 194 via the frame peripheral relay terminal board 868 and the peripheral door relay terminal board 882. Therefore, the length of the wiring required for the route to the peripheral control board 4140, the frame peripheral relay terminal board 868, the peripheral door relay terminal board 882, and the frame decoration drive amplifier board 194 is much longer than that of the channel CH1. As a result, the transmission path in the channel CH2 becomes much longer than the transmission path in the channel CH1 and is thus extremely susceptible to noise. Therefore, for the channel CH2 in which the length of the wiring for transmitting the drawing data is extremely longer than that of the channel CH1, the transmitter IC 4160d uses "V- By adopting the differential type communication called "by-One (registered trademark)", the mechanism is less susceptible to noise. The “clockless transmission method” means that, between a transmitter and a receiver, when a signal in which a clock is superimposed on data is transmitted from the transmitter to the receiver, clock data recovery (CDR: Clock Data Recovery) provided in the receiver. ) Is a method of separating data and clock by function.

The channel CH1 uses a differential interface based on a serial method called LVDS (Low Voltage Differential Signaling). To briefly describe this serial differential interface called LVDS, the channel CH1 can output a clock signal that is differentiated into a plus signal and a minus signal from the TCLK plus terminal and the TCLK minus terminal. The plus terminal and the TCLK minus terminal are electrically connected to a clock signal differential 1-pair cable in which one wire is in positive phase and the other wire is in antiphase, and the clock signal is supplied to the liquid crystal output substrate 3420. To transmit. The channel CH1 can output five signals of a red video signal, a green video signal, a blue video signal, a horizontal sync signal, and a vertical sync signal as four data streams (TA, TB, TC, and TD). ..

Specifically, the channel CH1 can output a first data stream TA signal that forms four data streams that are differentiated into a plus signal and a minus signal from the TA plus terminal and the TA minus terminal. Therefore, the TA plus terminal and the TA minus terminal are electrically connected to the differential pair signal cable for TA signal in which one wiring has a positive phase and the other wiring has a negative phase, and the TA positive terminal and the TA negative terminal are connected to the liquid crystal output substrate 3420. The first data stream TA signal forming the four data streams is transmitted. In addition, the channel CH1 can output a second data stream TB signal, which forms four data streams that are differentiated into a plus signal and a minus signal, from the TB plus terminal and the TB minus terminal. The plus terminal and the TB minus terminal are electrically connected to the differential pair signal cable for TB signal in which one wiring is in positive phase and the other wiring is in antiphase, and four data are provided on the liquid crystal output substrate 3420. The second data stream TB signal forming the stream is transmitted.

In addition, the channel CH1 can output a third data stream TC signal that forms four data streams that are differentiated into a plus signal and a minus signal from the TC plus terminal and the TC minus terminal, and TC A plus terminal and a TC minus terminal are electrically connected to a differential pair signal cable for TC signals in which one wiring is in positive phase and the other wiring is in opposite phase, and four data are provided on the liquid crystal output substrate 3420. The third data stream TC signal forming the stream is transmitted. Further, the channel CH1 can output a fourth data stream TD signal, which forms four data streams that are differentiated into a plus signal and a minus signal, from the TD plus terminal and the TD minus terminal. The plus terminal and the TD minus terminal are electrically connected to the differential 1 pair cable for TD signal in which one wiring is in the positive phase and the other wiring is in the opposite phase, and four data are provided on the liquid crystal output substrate 3420. The fourth data stream TD signal forming the stream is transmitted.

In this way, the drawing data output from the channel CH1 includes the clock signal differential 1 pair cable, the TA signal differential 1 pair cable, the TB signal differential 1 pair cable, the TC signal differential 1 pair cable, And transmitted to the liquid crystal output substrate 3420 via the differential pair cable for TD signals. The clock signal differential 1 pair cable, the TA signal differential 1 pair cable, the TB signal differential 1 pair cable, the TC signal differential 1 pair cable, and the TD signal differential 1 pair cable are each 2 The wire of the book is not a parallel line provided in parallel, but a twisted pair cable. This twisted pair cable is a cable in which two wires are twisted together, and is also called a twisted pair wire (twisted wire).

Then, the drawing data output from the channel CH1 is, as shown in FIG. 20, a signal (that is, a clock signal, a TA signal, a TB signal, a TC signal) transmitted by the LVDS system in the RGB conversion circuit 3420f of the liquid crystal output substrate 3420. Signal and TD signal). The parallel signal is composed of three video signals of a red video signal, a green video signal, and a blue video signal, and three sync signals of a horizontal sync signal, a vertical sync signal, and a clock signal.

The RGB conversion circuit 3420f converts the drawing data output from the channel CH1 into a parallel signal based on a signal transmitted by the LVDS system (that is, a red video signal which is drawing data output from the channel CH1 of the sound source built-in VDP 4160a, 3 video signals of a green video signal and a blue video signal, and 3 sync signals of a horizontal sync signal, a vertical sync signal, and a clock signal), and output to the game board side signal separation control circuit 3420g. The game board side signal separation control circuit 3420g is a red video signal and a green video signal which are game board side drawing data for the game board side effect display unit 1900 (liquid crystal panel 5000e) from the parallel signals converted by the RGB conversion circuit 3420f. , And three video signals of a blue video signal, three sync signals of a horizontal sync signal, a vertical sync signal, and a clock signal, and one light guide plate of a plurality of light guide plates included in the game board side effect display unit 1900. Information on the light guide plate to be selected, and a plurality of LEDs (for decoration) provided on each of the plurality of game board side VDP control target decoration boards that are directly controlled by the sound source built-in VDP 4160a among the respective decoration boards of the game board 4 (LED) and the electric decoration information.

The game board side signal separation control circuit 3420g is a game board side drawing data for the game board side effect display unit 1900 (liquid crystal panel 5000e), which is separated from the parallel signals converted by the RGB conversion circuit 3420f, a red video signal, green. A video board side effect display unit via the video board side liquid crystal drive circuit 3420h, which is a video signal and a blue video signal, and a horizontal sync signal, a vertical sync signal, and a clock signal. By outputting to 1900 (liquid crystal panel 5000e), the game board side effect display unit 1900 (liquid crystal panel 5000e) displays a screen. The game board side signal separation control circuit 3420g separates from the parallel signal converted by the RGB conversion circuit 3420f, and based on the light guide plate information, various light guide plates of the game board side effect display unit 1900 via the various light guide plate control circuits 3420k. By outputting any of the various light guide plates, the selected light guide plate emits surface light, and based on the electric decoration information, the game board side VDP control target decoration LED control circuit 3420i is used. Out of the decorative boards of the game board 4, output signals to a plurality of LEDs (decorative LEDs) provided on each of the plurality of game board-side VDP control target decorative boards that are directly controlled by the sound source built-in VDP 4160a. By doing so, a plurality of LEDs (decorative LEDs) emit light.

Returning to FIG. 19, the channel CH2 uses an interface in parallel with respect to the channel CH1. The drawing data output from the channel CH2 is composed of three video signals of a red video signal, a green video signal, and a blue video signal, and three sync signals of a horizontal sync signal, a vertical sync signal, and a clock signal. It is serialized by the transmitter IC 4160d and output (transmitted) to the peripheral control output circuit (not shown), the frame peripheral relay terminal plate 868, the peripheral door relay terminal plate 882, and the frame decoration drive amplifier board 194. The various serialized signals are restored to parallel signals in the frame decoration drive amplifier board 194.

In this way, the peripheral control MPU 4150a draws (displays) one screen (one frame) of screen data on the game board side effect display unit 1900 and a predetermined screen (in the present embodiment, red (R): Output screen data for one screen (one frame) for drawing (displaying) a gray screen having 50%, green (G): 50%, and blue (B): 50% to the VDP4160a with a built-in sound source. .. "Screen data for one screen (for one frame)" means drawing data for one screen (for one frame) to be drawn (displayed) on the game board side effect display unit 1900, and a predetermined screen (this embodiment). Then, drawing data for one screen (for one frame) for drawing (displaying) a gray screen having red (R): 50%, green (G): 50%, and blue (B): 50%, Is data to be generated on the built-in VRAM.

In the present embodiment, the game board side effect display unit 1900 (liquid crystal panel 5000e) adopts 12 inches having an image size of 800×600 dots, and a predetermined screen (in the present embodiment, red (R): 50%). , A gray screen with green (G): 50% and blue (B): 50%) adopts an image size of 480×272 dots. In this way, the image size of the game board side effect display unit 1900 (liquid crystal panel 5000e) has a predetermined screen (red (R): 50%, green (G): 50%, blue (B in this embodiment). ): gray screen with 50%) compared to the image size. Therefore, it is assumed that the image size is the same as that of a predetermined screen (in the present embodiment, a gray screen having red (R): 50%, green (G): 50%, and blue (B): 50%). A 4.3-inch liquid crystal display device having an image size has a predetermined screen (in the present embodiment, red (R): 50%, green (G): 50%, blue (B): 50%). When displaying a gray screen), the operating frequency of the game board side effect display unit 1900 (liquid crystal panel 5000e) is higher than the operating frequency of the 4.3-inch liquid crystal display device.

Further, the sound source built-in VDP 4160a outputs (transmits) drawing data for one screen (for one frame) from the channel CH1 to the liquid crystal output substrate 3420, and also outputs image data for one screen (for one frame) from the channel CH2. When output (transmitted) to the peripheral control output circuit (not shown), the frame peripheral relay terminal plate 868, the peripheral door relay terminal plate 882, and the frame decoration drive amplifier board 194, the screen data from the peripheral control MPU 4150a can be received. Is output to the peripheral control MPU 4150a. In the present embodiment, a game board side effect display unit 1900 and a predetermined screen (in the present embodiment, red (R): 50%, green (G): 50%, blue (B): gray with 50%). Since the frame frequency (the number of screen updates per second) that is the frequency at which the drawing data for one screen (for one screen) is updated to about 30 fps for a second, a V blank signal is output. The interval is about 33.3 ms (=1000 ms÷30 fps). The peripheral control MPU 4150a is configured to execute a peripheral control unit V blank signal interrupt process, which will be described later, when the V blank signal is input. Here, the interval at which the V blank signal is output is the liquid crystal size of the game board side effect display unit 1900 or a predetermined screen (in the present embodiment, red (R): 50%, green (G): 50%, Blue (B): Gray screen with 50%) image size varies somewhat. Also, in the manufacturing lot of the peripheral control board 4140 in which the peripheral control MPU 4150a and the sound source built-in VDP 4160a are mounted, the interval at which the V blank signal is output may change to some extent.

A frame buffer method is adopted for the VDP 4160a with a built-in sound source. The "frame buffer method" means a game board side effect display unit 1900 and a predetermined screen (in the present embodiment, red (R): 50%, green (G): 50%, blue (B): 50%. Drawing data for one screen (for one frame) with a gray screen) is held in the frame buffer (built-in VRAM), and drawing for one screen (one frame) held in this frame buffer (built-in VRAM) This is a method of outputting data.

When the sound command data described above is input from the peripheral control MPU 4150a based on a command from the main control board 4100, the sound source built-in VDP 4160a receives music stored in the liquid crystal and sound control ROM 4160b as shown in FIG. By extracting the sound data such as sound effect and sound effect and controlling the built-in sound source, the sound data such as music and sound effect are embedded in the track according to the track number specified in the sound command data, and used according to the output channel number. The output channel is set, and the music and the sound effect flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 are serialized and output as audio data to the audio data transmission IC 4160c. ..

Note that the sound command data also includes a sub-volume value for adjusting the volume of the track in which the sound data is incorporated. In addition to the sound data and the sub-volume value for adjusting the volume, the sound data and the volume of the notification sound for notifying the clerk in the hall of the occurrence of the malfunction of the pachinko gaming machine 1 or the misconduct to the pachinko gaming machine 1. A sub-volume value that adjusts is incorporated. Specifically, for the effect sound, the above-described substrate volume adjusted by rotating the knob of the volume adjustment volume 4140a is set as the sub-volume value, and for the notification sound, the volume adjustment is performed. The maximum volume is set as the sub volume value without depending on the volume adjustment based on the turning operation of the knob portion of the volume 4140a. The sub-volume value of the effect sound can be adjusted by moving to the setting mode described later by operating the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400.

The sound command data also includes a master volume value for adjusting the volume of the output channel, and a plurality of output channels in the internal sound source of the sound source built-in VDP 4160a include a plurality of output channels in the sound source built-in VDP 4160a. Of the tracks, the sound data of the effect sound incorporated in the track to be used and the sub-volume value for adjusting the volume of the effect sound incorporated in the track to be used are combined, and the volume of the combined effect sound is Actually, a master volume value that is a volume flowing from a speaker housed in a speaker box 820 provided in the main body frame 3 and a speaker 130 provided in the door frame 5 is amplified, and the amplified effect sound is serialized as audio data. The data is output to the audio data transmission IC 4160c.

In this embodiment, the master volume value is set to a constant value excluding the master volume value for power suppression, and when the volume of the synthesized effect sound is the maximum volume, the master volume value is amplified to the master volume value. The volume of sound from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 is set to be the maximum allowable volume. Specifically, for the effect sound, as a sub-volume value for adjusting the sound data of the effect sound incorporated in the track to be used among the plurality of tracks and the volume of the effect sound incorporated in the track to be used. The set volume adjusting volume 4140a is combined with the board volume adjusted by rotating the knob, and the combined volume of the effect sound is actually stored in the speaker box 820 provided in the main body frame 3. Amplify to the master volume value that is the volume that flows from the housed speaker and the speaker 130 provided on the door frame 5, serialize the amplified effect sound, and output as audio data to the audio data transmission IC 4160c. Is based on the sound data of the notification sound incorporated in the track to be used and the turning operation of the knob portion of the volume adjustment volume 4140a set as a sub-volume value for adjusting the volume of the notification sound incorporated in the track to be used. The maximum volume is totally independent of the volume adjustment, and the synthesized volume of the notification sound is actually the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker provided in the door frame 5. It is amplified to a master volume value that is a volume flowing from 130, and the amplified notification sound is serialized and output as audio data to the audio data transmission IC 4160c.

Here, when the effect sound is flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, the pachinko gaming machine 1 malfunctions and the pachinko gaming machine 1 is affected. To briefly explain the control of sending the alarm sound to notify the clerk of the hall of the illegal activity, first, the sub-volume value of the track in which the effect sound is incorporated is forcibly set to mute, and this effect sound is incorporated. Sound data of the track, the sub-volume value set to mute it, the sound data of the track in which the notification sound is incorporated, and the sub-volume value of which the volume of the notification sound is set to the maximum volume are combined. The volume of the synthesized effect sound and the volume of the notification sound are actually amplified to a master volume value that is a volume that flows from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5. Then, the amplified effect sound and notification sound are serialized and output as audio data to the audio data transmission IC 4160c.

That is, in reality, only the notification sound of the maximum volume flows from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5. At this time, since the effect sound is muted, the effect sound does not flow from the speaker accommodated in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, but the effect sound is for the sound generation described above. It is proceeding according to the schedule data. In the present embodiment, the notification sound is made to flow from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 for a predetermined period (for example, 90 seconds). When the period elapses, the volume of the effect sound that has been proceeding according to the sound generation schedule data that has been compulsorily set to mute up to now is the substrate volume that is adjusted by rotating the knob of the volume adjustment volume 4140a. The volume value is set again (at this time, when the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400 is operated to shift to the setting mode and adjustment is performed, the sub-value of the adjusted effect sound is adjusted. The volume value is set), and the sound flows from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5.

In this way, when the effect sound is flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, the malfunction of the pachinko gaming machine 1 or the pachinko gaming machine 1 occurs. When a notification sound is played to notify a clerk of the hall of an illegal act against the speaker, the volume of the effect sound is muted and the notification sound is provided in the speaker and the door frame 5 housed in the speaker box 820 provided in the main body frame 3. Although the muffled sound produced by the speaker 130 progresses in accordance with the sound generation schedule data, the speaker accommodated in the speaker box 820 provided in the main body frame 3 after the notification sound has passed the predetermined period. When the speaker 130 provided in the door frame 5 stops flowing, the effect sound does not start to flow again from where the notification sound started to flow, but according to the sound generation schedule data until a predetermined period has elapsed since the notification sound started to flow. It started to flow again from the place where it progressed.

[7-4-2b. Liquid crystal and sound control ROM]
The liquid crystal and sound control ROM 4160b, as shown in FIG. 19, the game board side character data for drawing in the display area of the game board side effect display unit 1900, and the above-described predetermined screen (in the present embodiment, red ( R): 50%, green (G): 50%, blue (B): gray screen having 50%), dummy data for drawing the decorative board of the game board 4, the VDP4160a with a built-in sound source Game board side light emission mode setting image data for setting the light emission mode of a plurality of LEDs (decorative LEDs) provided on each of the plurality of game board side VDP control target decorative boards that are directly controlled. Of the decoration boards of the door frame 5, the light emission mode of a plurality of LEDs (decorative LEDs) provided on each of the plurality of frame-side VDP control target decoration boards that are directly controlled by the sound source built-in VDP 4160a is set. Door frame side light emission mode setting image data for performing, and various sound data such as music, sound effect, notification sound, and notification sound are stored in advance.

[7-4-2c. Audio data transmission IC]
When the serialized audio data from the sound source built-in VDP 4160a is input, the audio data transmission IC 4160c uses a peripheral control output circuit, a frame peripheral relay (not shown) as serial data of a difference method in which the right audio data is a plus signal and a minus signal. A peripheral control output circuit (not shown) is transmitted to the frame decoration drive amplifier board 194 via the terminal board 868 and the peripheral door relay terminal board 882, and also as left-side audio data as positive/negative differential serial data. , The frame peripheral relay terminal board 868, and the peripheral door relay terminal board 882 to the frame decoration drive amplifier board 194. As a result, music, sound effects, etc. adapted to various effects are stereo-reproduced from the speaker accommodated in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5.

The audio data transmission IC 4160c outputs audio data as serial data of the left and right differential systems between the boards from the peripheral control board 4140 to the frame decoration drive amplifier board 194, for example, a plus signal of the left audio data, Even when the negative signal is affected by noise, when the noise component carried on the positive signal and the noise component carried on the negative signal are combined by the frame decoration drive amplifier board 194 into one left audio data, Since the noise components are removed by canceling each other, it is possible to take measures against noise.

[7-4-2d. Transmitter IC]
As shown in FIG. 19, the transmitter IC 4160d receives the drawing data output from the channel CH2 of the VDP 4160a with a built-in sound source. As described above, the channel CH2 uses the parallel interface. The drawing data is composed of three video signals of a red video signal, a green video signal, and a blue video signal, and three sync signals of a horizontal sync signal, a vertical sync signal, and a clock signal. The green video signal, the blue video signal, and the blue video signal each have 8 bits, that is, 24 bits in total. In the present embodiment, the red video signal, the green video signal, and the blue video signal that can be input to the transmitter IC 4160d each have 10 bits, that is, a total of 30 bits. Therefore, all 8 bits of each video signal are input to the transmitter IC 4160d. ing. Since the red video signal, the green video signal, and the blue video signal each have 8 bits, the extra 2 bits that can be input to the transmitter IC 4160d are invalidated (specifically, each video signal of the transmitter IC 4160d). Of the input terminals, the lower 2 bits are grounded to the ground (GND).

Three video signals, which are the red video signal, the green video signal, and the blue video signal, which are drawing data output from the channel CH2 of the sound source built-in VDP 4160a, and three sync signals, which are the horizontal sync signal, the vertical sync signal, and the clock signal. Are input to the transmitter IC 4160d, the transmitter IC 4160d outputs three video signals of a red video signal, a green video signal, and a blue video signal, and three sync signals of a horizontal sync signal, a vertical sync signal, and a clock signal. And are serialized into a differential serial signal (serial data) called "V-by-One (registered trademark)" by THine Electronics Co., Ltd., which is a type of clockless transmission system (in other words, red video signal, green A parallel signal composed of three video signals of a video signal and a blue video signal and three sync signals of a horizontal synchronization signal, a vertical synchronization signal, and a clock signal is multiplexed, and a differential serial signal ( Serial data), and these various signals are transmitted from the peripheral control board 4140 to the frame peripheral relay terminal board 868 only by the differential 1 pair cable in which one wiring is in the positive phase and the other wiring is in the reverse phase. , Peripheral door relay terminal board 882, and frame decoration drive amplifier 194 (output).

As described above, the drawing data output from the channel CH1 of the sound source built-in VDP 4160a is output (transmitted) from the peripheral control board 4140 to the liquid crystal output board 3420, so that the transmission from the channel CH1 to the game board side effect display unit 1900 is performed. Although the length of the wiring required for the path (first transmission path) is short, the drawing data output from the channel CH2 of the sound source built-in VDP 4160a is transmitted from the peripheral control board 4140 to the frame peripheral relay terminal board 868 and the peripheral door relay terminal board 882. Since it is output (transmitted) to the frame decoration drive amplifier board 194 via the, the wiring length required for the transmission path (second transmission path) from the channel CH2 to the frame decoration drive amplifier board 194 is required for the first transmission path. Since it is much longer than the length of the wiring, it becomes very susceptible to noise.

Specifically, since the door frame 5 is rotatably supported with respect to the main body frame 3 shown in FIG. 1, the door frame 5 is opposite to the lock device 1000 shown in FIG. 5 along the open side of the main body frame 3. On the closed side, which is the side, for example, the main body frame 3 side, such as the frame decoration drive amplifier board 194 housed in the dish unit 300 provided in the door frame 5 from the peripheral control board 4140 provided in the game board 4 attached to the main body frame 3 It is necessary to pass various wirings that electrically connect the various substrates provided in the above and the various substrates provided on the door frame 5 side. However, on the closed side of the main body frame 3, as shown in FIG. 3, in addition to the prize ball device 740, the game balls paid out by the prize ball device 740 are provided in the dish unit 300 shown in FIG. A full tank branching unit 770 is arranged that can guide the upper tray 301 to the lower tray 302 side when the upper tray 301 is filled with the game balls and can be guided to the upper tray 301. Further, on the lower side of the main body frame 3, the board unit 800 shown in FIG. 5 in which the power supply boards 851 and the like shown in FIG. 6 to which power is supplied from the pachinko island equipment is integrated into a unit is arranged. As described above, various wirings for electrically connecting the various substrates provided on the main body frame 3 side and the various substrates provided on the door frame 5 side are provided near the prize ball device 740, the full tank branching unit 770, the power supply substrate 851, and the like. In addition to the noise caused by driving the payout motor 744 provided in the prize ball device 740, the noise caused by electrostatic discharge from the game balls and the pachinko island equipment in which the pachinko gaming machine 1 is installed are supplied. It is in an environment where it receives noise that has entered the power supply line.

Therefore, for the channel CH2 in which the length of the wiring for sending the drawing data becomes extremely longer than that of the channel CH1, the transmitter IC 4160d provided in the peripheral control board 4140 is a type of clockless transmission system by THine Electronics. By adopting differential communication called "V-by-One (registered trademark)" of a stock company, the structure is less susceptible to noise. In the present embodiment, a wiring for electrically connecting between the transmitter IC 4160d included in the peripheral control board 4140 and the receiver IC 194f included in the frame decoration drive board 194 of the door frame 5, that is, between the transmitter and the receiver. As described above, the differential 1 pair cable is used, but the differential 1 pair cable is not a parallel line in which two wirings are simply provided in parallel, but a twisted pair cable. This twisted pair cable is a cable in which two wires are twisted together, and is also called a twisted pair wire (twisted wire). The twisted wire is made by twisting wires that transmit positive-phase signals and wires that transmit negative-phase signals, so if noise enters the twisted wires, wires that transmit positive-phase signals Then, noise will intrude into the wiring that transmits the signal of the opposite phase. Then, the noise invading the positive-phase signal and the noise invading the negative-phase signal cancel each other to cancel the noise in the receiver IC 194f, and again the red video signal, the green video signal, and It is possible to restore a parallel signal composed of three video signals called a blue video signal and three sync signals called a horizontal sync signal, a vertical sync signal, and a clock signal. It should be noted that the transmitter IC 4160d included in the peripheral control board 4140 and the receiver IC 194f included in the frame decoration drive board 194 of the door frame 5 are connected with each other, that is, with respect to the wiring for electrically connecting the transmitter and the receiver. In order to further suppress the influence of noise, for example, in addition to the above-described positive-phase wiring and negative-phase wiring, a structure in which a total of three wirings, that is, a ground (GND) wiring, may be a twisted wire Yes, it is possible to twist the positive-phase wiring and the negative-phase wiring, and to make a twisted shielded wire (also called a twisted pair shielded cable) in which the twisted wiring is covered with a shield film. it can. The shield film is grounded to the ground (GND) of the peripheral control board 4140 and the ground (GND) of the frame decoration drive board 194 to form the same ground (GND).

Here, a case where parallel lines are adopted as the differential 1-pair cable that electrically connects the transmitter and the receiver will be briefly described. For the channel CH2 of the VDP4160a with a built-in sound source, in which the length of the wiring for sending the drawing data is extremely longer than that of the channel CH1 of the VDP4160a with a built-in sound source, the transmitter IC 4160d provided in the peripheral control board 4140 is a type of clockless transmission method. Even if a mechanism that is difficult to be affected by noise by adopting differential communication called "V-by-One (registered trademark)" by THine Electronics Co., Ltd. When serial data in parallel lines is affected by noise due to electrostatic discharge, noise invading the power line supplied from the pachinko island facility where the pachinko gaming machine 1 is installed, etc., the frame decoration drive amplifier board of the door frame 5 Since the noise is not canceled (removed) when it is received by the receiver IC 194f provided in 194, the serial data is received by the receiver IC 194f in an affected state, and the drawing output from the channel CH2 of the sound source built-in VDP 4160a is performed. There is a problem that the data is received by the receiver IC 194f as irregular data different from the normal data.

Therefore, in the present embodiment, in the transmitter IC 4160d provided in the peripheral control board 4140 for the channel CH2 of the VDP 4160a with a built-in sound source in which the length of the wiring for sending the drawing data is extremely longer than the channel CH1 of the VDP 4160a with a built-in sound source. , Which is a type of clockless transmission system, adopts a differential type communication called "V-by-One (registered trademark)" by THine Electronics Co., Ltd. to make it a mechanism that is not easily affected by noise, and to provide such hardware. In addition to the configuration described above, a twisted pair cable that can cancel (remove) the noise on the receiving side even if the serial data by the differential method is affected by the noise that has entered the wiring is electrically connected between the transmitter and the receiver. It was adopted as a differential 1-pair cable that is electrically connected. As a result, even if serial data is affected in the twisted pair cable due to noise caused by electrostatic discharge of the game ball, noise invading the power line supplied from the pachinko island facility where the pachinko gaming machine 1 is installed, etc. Since noise is canceled (removed) when it is received by the receiver IC 194f provided on the frame decoration drive board 194 of the frame 5, the drawing data output from the channel CH2 of the VDP 4160a with a built-in sound source is the door frame 5 It can be reliably received by the receiver IC 194f provided in the frame decoration drive amplifier board 194.

In the present embodiment, the frame peripheral relay terminal is connected between the transmitter IC 4160d included in the peripheral control board 4140 and the receiver IC 194f included in the frame decoration drive board 194 of the door frame 5, that is, between the transmitter and the receiver. A plate 868 and a peripheral door relay terminal plate 882 are interposed. This is because the main body frame 3 and the door frame 5 are not integrally configured, but the separately assembled ones are attached to the main body frame 3 by attaching the door frame 5 to the main body frame 3. After the work of attaching the door frame 5 to the door frame 3, electrically connecting various wirings such as harnesses and twisted pair cables from various boards provided on the door frame 5 side to the peripheral door relay terminal board 882 provided on the body frame 3 side. Thus, various substrates provided on the body frame 3 side and various substrates provided on the door frame 5 side can be electrically connected. With such a configuration, after the door frame 5 is opened from the body frame 3 and various wirings are removed, the door frame 5 is removed from the body frame 3 to perform maintenance of the body frame 3 and the door frame 5. If it can be done and the trouble that has occurred in the door frame 5 cannot be eliminated, another door frame 5′ is attached to the main body frame 3 instead of the defective door frame 5, and the door frame 5 By electrically connecting various wirings from various boards provided on the'side to the peripheral door relay terminal plate 882 provided on the body frame 3 side, various boards provided on the body frame 3 side and various boards provided on the door frame 5'side The substrate can be electrically connected.

Further, in the present embodiment, as described above, in the transmitter IC 4160d provided in the peripheral control board 4140, a differential system called "V-by-One (registered trademark)" of THine Electronics Co., Ltd., which is a kind of clockless transmission system, is used. In addition to adopting communication to make it less susceptible to noise, in addition to such a hardware configuration, even if serial data from the differential method is affected by noise that has entered the wiring, that noise will still be present on the receiving side. A twisted pair cable that can cancel (remove) is adopted as a differential 1 pair cable that electrically connects the transmitter and the receiver. Specifically, between the peripheral control board 4140 and the frame peripheral relay terminal board 868, between the frame peripheral relay terminal board 868 and the peripheral door relay terminal board 882, and between the peripheral door relay terminal board 882 and the frame decoration drive. Twisted pair cables are electrically connected between the amplifier board 194 and the boards, while the power supply wiring and other wirings for transmitting various signals are electrically connected by harnesses. As a result, the frame peripheral relay terminal plate 868 and the peripheral door relay terminal plate 882 have a power supply wiring pattern and a video transmission wiring pattern for transmitting differential serial data transmitted by the transmitter IC 4160d. Various signal wiring patterns for transmitting other various signals are mixed. Therefore, the frame peripheral relay terminal board 868 and the peripheral door relay terminal board 882 are respectively formed with the above-mentioned video transmission wiring patterns separated from the power supply wiring patterns and various signal wiring patterns by a predetermined dimension. In the path from the transmitter to the receiver, the frame peripheral relay terminal board 868 and the peripheral door relay terminal board 882 are laid across a plurality of relay terminal boards, and therefore the video transmission formed on these plurality of relay terminal boards. Between the input and output of the wiring pattern, there occurs a problem that a part of the signal that transmits the serial data by the differential method transmitted by the transmitter IC 4160d is reflected and becomes noise, or the output level of the signal is lowered. Therefore, in the present embodiment, impedance matching is applied to the video transmission wiring patterns formed on the plurality of relay terminal boards.

Further, in the present embodiment, as described above, between the peripheral control board 4140 and the frame peripheral relay terminal board 868, between the frame peripheral relay terminal board 868 and the peripheral door relay terminal board 882, and the peripheral door relay. The terminal board 882 and the frame decoration drive amplifier board 194 are electrically connected to each other by a twisted pair cable, while the power supply wiring and other wirings for transmitting various signals are electrically connected by harnesses. However, one wire of the twisted pair cable is red and the other wire is gray, and the wiring that supplies power to the harness is red and the other wires are gray. There is. Note that the wiring for supplying power may be yellow instead of red.

In the present embodiment, a serial signal (serial data) by a differential system called “V-by-One (registered trademark)” of THine Electronics Co., Ltd., which is a kind of clockless transmission system, is transmitted from the transmitter IC 4160d in the peripheral control board 4140. When transmitted as a plus signal and a minus signal, they are input to a common mode choke coil (not shown) provided on the frame decoration drive amplifier board 194 through the frame peripheral relay terminal plate 868 and the peripheral door relay terminal plate 882, respectively. The common mode choke coil can separate the noise from the plus signal and the minus signal. The noise-separated plus signal and minus signal are input to the RXIN+ terminal and RXIN- terminal of the receiver IC 194f, respectively. A resistor (not shown) is electrically connected between the RXIN+ terminal and the RXIN− terminal. The resistor (not shown) is a terminating resistor (terminator), which prevents the plus signal and the minus signal from being reflected at the RXIN+ terminal and the RXIN- terminal, respectively, and prevents disturbance of the serial signal.

Further, as described above, between the peripheral control board 4140 and the frame peripheral relay terminal board 868, between the frame peripheral relay terminal board 868 and the peripheral door relay terminal board 882, and between the peripheral door relay terminal board 882 and the frame. The decorative drive amplifier board 194 and the board are electrically connected by a twisted pair cable. Of these twisted pair cables, all twisted pair cables, any number of twisted pair cables (not all twisted pair cables, but any number (predetermined number) of twisted pair cables), or any one twisted pair cable Noise can be taken by inserting the through hole. The ring core is effective for removing high-frequency noise in the hundreds of kHz to hundreds of MHz band, and can be provided with a thin coating for preventing scattering and reducing damage.

Further, by providing the ferrite beads on the positive phase side and the ferrite beads on the negative phase side on the frame decoration drive amplifier substrate 194, it is possible to further take noise countermeasures. In this case, from the transmitter IC 4160d in the peripheral control board 4140, serial signals (serial data) by a differential system called "V-by-One (registered trademark)" of THine Electronics Co., Ltd., which is a kind of clockless transmission system, are plus and minus signals. When transmitted as a signal, the plus signal is transmitted via a common mode choke coil (not shown) provided on the frame decoration drive amplifier board 194, and the RXIN+ terminal is transmitted through the positive-phase side ferrite beads provided immediately before the RXIN+ terminal of the receiver IC 194f. Circuit (that is, the terminal of the common mode choke coil (not shown) that outputs the plus signal is electrically connected to one end of the positive phase side ferrite bead, and the other end of the positive phase side ferrite bead is connected. And the RXIN+ terminal of the receiver IC 194f are electrically connected), and the negative signal is input to the RXIN- terminal via the opposite phase side ferrite bead provided immediately before the RXIN- terminal of the receiver IC 194f. (In other words, the terminal of the common mode choke coil (not shown) that outputs the negative signal and one end of the opposite phase side ferrite bead are electrically connected, and the other end of the opposite phase side ferrite bead and the receiver are connected. The circuit is configured such that the RXIN- terminal of the IC 194f is electrically connected). The positive-phase side ferrite beads and the negative-phase side ferrite beads reflect the noise that the inductor (coil) component of the ferrite bead penetrates into the twisted wire and prevent it from passing through, and the resistance component of the ferrite bead penetrates the twisted wire. Has the characteristic that it can be converted into heat and removed. Due to such characteristics of the ferrite beads, it is possible to suppress the disturbance of the waveform due to the superposition of noise on the serial signal transmitted through the twisted wire and arrange the waveform into a beautiful waveform.

The positive and negative signals of the serial signal (serial data) according to the differential method described above are directly provided immediately before the RXIN+ terminal of the receiver IC 194f without passing through a common mode choke coil (not shown). The circuit is configured to be input to the RXIN+ terminal via the ferrite bead, and the negative signal is input to the RXIN- terminal via the above-mentioned opposite phase side ferrite bead provided immediately before the RXIN- terminal of the receiver IC 194f. The circuit can be configured as follows.

[7-4-2e. Forced switching circuit, differential circuit]
The signal output from the transmitter IC 4160d is output (transmitted) to the compulsory switching circuit 4160f, the peripheral control output circuit (not shown), the frame peripheral relay terminal plate 868, the peripheral door relay terminal plate 882, and the frame decoration drive amplifier board 194. It has become. In addition to the signal output from the transmitter IC 4160d, the forced switching circuit 4160f includes a serial output from a LOCKN signal output request serial I/O port built in the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140. The LOCKN signal output request data, which is data, is input to the differential circuit 4160e after being differentiated into a plus signal and a minus signal. In the differential circuit 4160e, the LOCKN signal output request data is serialized into a differential serial signal (serial data). This LOCKN signal output request data is a demonstration by the game board side effect display unit 1900 during a period in which the start screen when the power of the pachinko game machine 1 is turned on is displayed on the game board side effect display unit 1900, or in a customer waiting state. During the period when the operation is being performed, a problem occurs in the connection between the transmitter IC 4160d included in the peripheral control board 4140 and the receiver IC 194f included in the frame decoration drive board 194 of the door frame 5, that is, the connection between the transmitter and the receiver. It is transmitted to confirm whether or not The forcible switching circuit 4160f is connected to the circuit so as to transmit the two signals when the two signals, which are differentiated into the plus signal and the minus signal in the differential circuit 4160e, are input, while the differential circuit 4160f is differentially connected. When two signals that are differentiated into a plus signal and a minus signal are not input to the digitization circuit 4160e, the circuit is configured to be connected so as to transmit the signal output from the transmitter IC 4160d. As a result, when two signals that are differentiated into a plus signal and a minus signal are input to the differential circuit 4160e, the circuits are connected so as to transmit the two signals, so that the two signals are transmitted. The peripheral control board 4140 outputs (transmits) the frame peripheral relay terminal board 868, the peripheral door relay terminal board 882, and the frame decoration drive board 194 of the door frame 5 to the plus and minus signals in the differential circuit 4160e. When two differential signals are not input to and, the circuit output is connected from the transmitter IC 4160d so that the signal output from the transmitter IC 4160d is connected to the peripheral control board 4140 and the periphery of the frame. It is output (transmitted) to the relay terminal board 868, the peripheral door relay terminal board 882, and the receiver IC 194f provided on the frame decoration drive board 194 of the door frame 5. The peripheral control MPU 4150a performs a demonstration by the game board side effect display unit 1900 during a period in which the game screen side effect display unit 1900 displays the startup screen when the pachinko game machine 1 is powered on, or in a customer waiting state. During the period, the LOCKN signal output request data is sent from the LOCKN signal output request serial I/O port to the frame decoration drive board 194 of the door frame 5 (actually, the differential circuit 4160e provided in the peripheral control board 4140). Output (send).

When the frame decoration drive board 194 of the door frame 5 receives the serial signal (serial data) from the peripheral control board 4140 by the receiver IC 194f, it outputs various serialized signals in parallel signals (that is, outputs from the channel CH2 of the sound source built-in VDP 4160a). The drawing data, which are the three video signals of the red video signal, the green video signal, and the blue video signal, and the three sync signals of the horizontal sync signal, the vertical sync signal, and the clock signal. The signal is output to the side signal separation control circuit 194g. The frame-side signal separation control circuit 194g uses the parallel signal restored by the receiver IC 194f to determine the above-described predetermined screen (in the present embodiment, red (R): 50%, green (G): 50%, blue (B). ): gray screen with 50%) door frame side drawing data, which are three video signals of red video signal, green video signal, and blue video signal, horizontal sync signal, vertical sync signal, and clock signal. Of the three synchronization signals and each of the decorative boards of the door frame 5, a plurality of LEDs (decorative LEDs) provided on each of a plurality of frame-side VDP controlled decorative boards that are directly controlled by the sound source built-in VDP 4160a. ) Illumination information for

The frame-side signal separation control circuit 194g separates from the parallel signal restored by the receiver IC 194f and has a predetermined screen (in the present embodiment, red (R): 50%, green (G): 50%, blue (B). ): gray screen with 50%) door frame side drawing data, which are three video signals of red video signal, green video signal, and blue video signal, horizontal sync signal, vertical sync signal, and clock signal. It does not output the three synchronizing signals to other electronic components or other substrates. On the other hand, the frame-side signal separation control circuit 194g receives each of the door frames 5 via the frame-side VDP control target decoration LED control circuit 194i based on the electric decoration information separated from the parallel signal restored by the receiver IC 194f. Among the decorative boards, a plurality of LEDs are provided by outputting signals to a plurality of LEDs (decorative LEDs) provided on each of the plurality of frame-side VDP control target decorative boards that are directly controlled by the sound source built-in VDP 4160a. (Decorative LED) emits light.

When the receiver IC 194f receives the drawing data from the sound source built-in VDP 4160a and determines that the received drawing data is abnormal data, the receiver IC 194f sends a LOCKN signal to that effect to the peripheral door relay terminal board 882 and the frame peripheral relay terminal board. Output to the peripheral control board 4140 via 868. This LOCKN signal is input to the peripheral control MPU 4150a of the peripheral controller 4150 in the peripheral control board 4140 via a peripheral control input circuit (not shown) in the peripheral control board 4140. Based on the input LOCKN signal, the peripheral control MPU 4150a controls the VDP 4160a with a built-in sound source to generate an image for notifying that a predetermined condition is satisfied, and displays it in the display area of the game board side effect display unit 1900. Display and inform.

When the receiver IC 194f determines that the received two signals are LOCKN signal output request data from the LOCKN signal output request serial I/O port, the receiver IC 194f outputs the LOCKN signal from the LOCKN terminal to the peripheral door relay terminal board 882, and It is output to the peripheral control board 4140 via the frame peripheral relay terminal board 868. This LOCKN signal is input to the peripheral control MPU 4150a of the peripheral controller 4150 in the peripheral control board 4140 via a peripheral control input circuit (not shown) in the peripheral control board 4140. As a result, the peripheral control MPU 4150a determines that the connection between the transmitter and the receiver is not defective when the LOCKN signal is input as a response signal to the transmission of the LOCKN signal output request data, and thus the frame decoration of the door frame 5 is performed. It can be determined that the drive amplifier board 194 is not defective, but when the LOCKN signal is not input, it is determined that the connection between the transmitter and the receiver is defective, and the frame decoration drive of the door frame 5 is performed. VDP4160a with a built-in sound source is used to determine that a problem has occurred in the amplifier board 194, and to inform the user of that fact (for example, "A problem has occurred between the transmitter and receiver. Please call the store staff."). Is controlled to draw (display) on the game board side effect display unit 1900, and a notification sound (for example, "a trouble has occurred between the transmitter and the receiver.") to inform that effect is displayed. By controlling the VDP 4160a with a built-in sound source and outputting it to the audio data transmission IC 4160c, a notification sound is output from the speaker 130 provided on the door frame 5. As a result, it is possible to perform the notification by the notification image drawn (displayed) in the display area of the game board side effect display unit 1900 and the notification sound repeatedly played from the speaker 130 provided in the door frame 5. There is. At this time, the plurality of LEDs provided on each decorative board of the door frame 5 and the plurality of LEDs provided on each decorative board of the game board 4 may all be turned on.

[7-4-3. RTC controller]
As shown in FIG. 17, the RTC control unit 4165, which holds calendar information for specifying the date and time information for specifying the hour, minute, and second, is mainly composed of the RTC 4165a. The RTC 4165a has a built-in RAM 4165aa that holds calendar information and time information (hereinafter, referred to as "RTC built-in RAM 4165aa"). The RTC 4165a is adapted to be supplied with power from a battery 4165b (a button battery is adopted in this embodiment) as a driving power source and a backup power source for the RTC built-in RAM 4165aa. That is, the RTC 4165a is supplied with power from the battery 4165b independently of the peripheral control board 4140 (pachinko gaming machine 1) without being supplied with power from the peripheral control board 4140 (pachinko gaming machine 1). As a result, the RTC 4165a can update and hold the calendar information and the time information by the power supply from the battery 4165b even when the power of the pachinko gaming machine 1 is cut off.

The peripheral control MPU 4150a of the peripheral control unit 4150 acquires calendar information and time information from the RTC built-in RAM 4165aa of the RTC 4165a and sets them in the RTC information acquisition storage area 4150cad of the peripheral control RAM 4150c described above. Based on the game board side effect display unit 1900 can be unfolded. As such an effect, for example, on December 25, a Christmas tree or reindeer screen is unfolded on the game board side effect display unit 1900, and on New Year's Eve, a screen for executing a New Year countdown is an effect on the game board side. For example, the display unit 1900 may be unfolded. The calendar information and time information are set at the time of factory shipment.

In addition to the calendar information and the time information, the RTC built-in RAM 4165aa also stores the input date/time information as the information of the year/month/day and the hour/minute/second when the calendar information and the time information were first stored in the RTC built-in RAM 4165aa. There is.

Various information such as calendar information, time information, and input date/time information stored in the RTC built-in RAM 4165aa is set on the manufacturing line of the gaming machine manufacturer. In the production line, in order to perform various tests such as a display test of the game board side effect display unit 1900, for example, the year when the input date and time information is input as the date and time when the game board side effect display unit 1900 is first turned on. It is set to the manufacturing date and time which is month and day and hour, minute and second.

As described above, the RTC built-in RAM 4165aa has calendar information that is information that needs to be maintained independently of the model information of the pachinko gaming machine 1 (for example, the probability that a big hit gaming state occurs in low probability or high probability). Time information, input date and time information, and the like can be stored and held.

The current date and time may be specified by directly acquiring the calendar information specifying the date and the time information specifying the hour, minute, and second from the RTC built-in RAM 4165aa of the RTC control unit 4165. Current calendar information set in the calendar information storage unit and updated by the system of the peripheral control board 4140 in the RTC information acquisition storage area 4150cad of the peripheral control RAM 4150c in the current time information acquisition processing of step S1002 in the control unit power-on processing. And the current time information set in the time information storage unit and updated by the system of the peripheral control board 4140 may be acquired to specify the current date and time.

[7-4-4. Volume control volume]
As described above, the volume adjusting volume 4140a rotates the knob for rotating the volume of music, sound effect, etc. flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5. It can be adjusted by doing. As described above, the volume adjustment volume 4140a has a variable resistance value when the knob portion is pivotally operated, and the peripheral control A/D converter 4150ak electrically connected to the knob portion 4140a operates as a knob portion. The voltage divided by the resistance value at the rotation position is converted from an analog value to a digital value, and is converted into a value of 1024 steps from value 0 to value 1023. In the present embodiment, as described above, the value of 1024 steps is divided into 7 and managed as the substrate volumes 0 to 6. The board volume 0 is set to mute, the board volume 6 is set to the maximum volume, and the volume is set to increase from the board volume 0 toward the board volume 6. The liquid crystal and the sound control unit 4160 (VDP4160a with a built-in sound source) are controlled so that the sound volume is set to the substrate volumes 0 to 6, and the speaker and the door frame 5 which are housed in the speaker box 820 provided in the main body frame 3 are provided. Music and sound effects are made to flow from the speaker 130.

In this way, by adjusting the volume based on the turning operation of the knob portion, music and sound effects are made to flow from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5. .. Further, in the present embodiment, as described above, in addition to music and sound effects, a notification sound for notifying a clerk of the hall of occurrence of a malfunction of the pachinko gaming machine 1 or fraudulent activity on the pachinko gaming machine 1, Announce the contents related to the game effect (for example, announcing that there is a high possibility that the screen unfolded on the game board side effect display unit 1900 will be rendered more powerful, or that the game state will be advantageous to the player. A notification sound for playing, etc. also flows from the speaker accommodated in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, but the notification sound and the notification sound are rotated by the knob portion. The volume flow from mute to maximum volume can be adjusted by controlling the liquid crystal and sound control unit 4160 (VDP4160a with a built-in sound source) by a program. ing.

The volume adjusted by this program is different from the above-described seven levels of the substrate volume, and it is possible to smoothly change from mute to maximum volume. Thus, for example, even when a store clerk in the hall or the like rotates the knob of the volume adjusting volume 4140a to set the volume low, the speaker and the door housed in the speaker box 820 provided in the main body frame 3 are closed. Although the sound produced by the speaker 130 provided in the frame 5 and the effect sound such as the sound effect are reduced, when the pachinko game machine 1 is in trouble or when the player is committing an illegal act, the volume of the sound is high. In the form, the notification sound set to the maximum volume) can be played. Therefore, even if the volume of the effect sound is reduced, it is possible to prevent the clerk or the like in the hall from becoming less likely to notice a malfunction or a player's cheating by the notification sound.

Also, based on the current board volume set by the volume adjustment based on the turning operation of the knob, the volume of the advertising sound is reduced so as not to disturb the music or the sound effect, while There is a possibility of increasing the volume of the sound played to increase the volume of the music and sound effects, and also to produce a more powerful screen on the game board side effect display unit 1900, or to shift to a game state advantageous for the player. You can also announce that it is expensive.

In the present embodiment, the volume of music or sound effect is adjusted by rotating the knob of the volume adjusting volume 4140a. By operating the operation unit 405, it is possible to shift to the setting mode and adjust the volume of music or sound effect. When the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400 is operated within a predetermined time after the power of the pachinko gaming machine 1 is turned on, a screen for performing the setting mode is displayed on the game board side effect display unit 1900. In addition, if the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400 is operated during the period in which the demonstration is performed by the game board side effect display unit 1900 in the customer waiting state, the setting mode is performed. The screen is displayed on the game board side effect display unit 1900. By operating the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400 according to the screen of the setting mode, the volume of music or sound effect can be adjusted to a desired volume.

Specifically, the peripheral control A/D converter 4150ak converts the voltage divided by the resistance value at the rotation position of the knob portion of the volume adjusting volume 4140a from an analog value to a digital value, and the converted value is Then, the value of the substrate volume can be increased or decreased by adding or subtracting a predetermined value according to the operation of the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400. .. The adjusted sound volume is set and updated as a sub-volume value for a track in which sound data of effect sound such as music and sound effect is incorporated among a plurality of tracks in the sound source with built-in sound source VDP4160a, and the effect sound is changed. Although it is reflected in the adjustment of the volume of, the volume of the above-mentioned notification sound and notification sound is not reflected in the adjustment.

As described above, in the present embodiment, the volume of music or sound effect is adjusted by directly rotating the knob portion of the volume adjustment volume 4140a, and the dial operation portion 401 or the pressing operation portion 405 of the operation unit 400. There are two methods: a case where the volume of music or a sound effect is adjusted by increasing or decreasing the value of the substrate volume by adding or subtracting a predetermined value according to the operation. Since the volume control volume 4140a is mounted on the peripheral control board 4140, it is necessary to keep the main body frame 3 open from the outer frame 2. Then, the store clerk can rotate the knob of the volume adjusting volume 4140a. However, at the volume adjusted by the clerk in the hall, the player may feel small and may be difficult to hear the music or the sound effect, or the player may feel large and feel the music or the sound effect loud. Therefore, after turning on the power of the pachinko gaming machine 1, within a predetermined time, the dial operating unit 401 and the pressing operating unit 405 of the operating unit 400 are operated, or the customer waits for a demonstration by the game board side effect display unit 1900. When the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400 is operated during the period in which the operation is performed, a screen for performing the setting mode is displayed on the game board side effect display unit 1900. By operating the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400 according to the screen of the setting mode, the volume of music or sound effect can be adjusted to a desired volume. With this, the player can adjust the volume of the music and the sound effect to a desired volume. Therefore, when the clerk in the hall feels the adjusted volume is small and it is difficult to hear the music and the sound effect, the operation unit 400 It is possible to increase the volume to a desired level by operating the dial operation section 401 or the pressing operation section 405. The dial operation unit 401 and the pressing operation unit 405 can be operated to reduce the volume to a desired level.

In addition, in the present embodiment, when the pachinko gaming machine 1 is not playing a game for a predetermined time, becomes a customer waiting state, and is repeatedly demonstrated by the game board side effect display unit 1900 (for example, 10 times). ), the volume adjusted by the player who was seated in front of the pachinko gaming machine 1 and was playing the game last time is canceled, and the volume is initialized. In the initialization of the volume, the volume is adjusted by the hall clerk, that is, the volume is adjusted by the hall clerk by directly rotating the knob portion of the volume adjusting volume 4140a. As a result, when the player sitting on the front of the pachinko gaming machine 1 last time and playing a game feels the volume is low and it is difficult to hear music or sound effects, A player who sits down to play a game can operate the dial operation unit 401 and the push operation unit 405 of the operation unit 400 to increase the volume to a desired volume, and last time, sit down on the front of the pachinko gaming machine 1 to play the game. When the player who is playing the game feels the adjusted volume to be loud and the music or the sound effect is noisy, the player who sits in front of the pachinko gaming machine 1 and plays the game this time is the dial operation unit of the operation unit 400. It is possible to reduce the volume to a desired volume by operating the 401 or the pressing operation unit 405.

[8. Power system]
Next, the power supply system of the pachinko gaming machine 1 will be described with reference to FIGS. 21 to 23. FIG. 21 is a block diagram showing a power supply system of a pachinko gaming machine, and FIG. 22 is a block diagram showing a power supply creation circuit (a), showing a relationship between power consumption and a power consumption suppression level accompanying the power consumption ( FIG. 23 is a block diagram showing the continuation of FIG. 21. First, the power supply board will be described, and then the power supplied to each control board and the like will be described. The grounds (GND) of the various boards and the grounds (GND) of the various terminal boards are electrically connected to the ground (GND) of the power supply board 851 and are the same ground (GND).

[8-1. Power board]
The power board 851 is electrically connected to a power cord, and the plug of this power cord is inserted into the power outlet of the Pachinko island facility. When the power switch 852 shown in FIG. 3 is operated, the power supplied from the pachinko island facility is supplied to the power board 851, and the pachinko gaming machine 1 can be powered on.

As shown in FIG. 21, the power supply board 851 includes a power supply controller 855, a firing solenoid drive circuit 858, and a ball feeding solenoid drive circuit 859. The power supply control unit 855 is a circuit that creates various DC voltages from AC 24V (AC24V) supplied from the pachinko island facility, and supplies backup power to the main control board 4100 and the payout control board 4110, and a firing solenoid. The drive circuit 858 is a circuit for driving the firing solenoid 654 of the hit ball firing device 650 shown in FIG. 5, and the ball feeding solenoid drive circuit 859 drives the ball feeding solenoid 585 of the ball feeding unit 580 shown in FIG. Circuit.

The power supply control unit 855 includes a synchronous rectification circuit 855a, a power factor correction circuit 855b, a smoothing circuit 855c, a power supply creation circuit 855d, and capacitors BC0 and BC1. The AC 24V supplied from the pachinko island facility is supplied to the game ball lending device connection terminal plate 869 via the power supply board 851 and is also supplied to the synchronous rectification circuit 855a. The synchronous rectification circuit 855a rectifies 24 V AC (AC 24 V) supplied from the pachinko island facility and supplies it to the power factor correction circuit 855b. The power factor correction circuit 855b improves the power factor of the rectified electric power to generate direct current +37V (DC+37V, hereinafter referred to as "+37V") and supplies it to the smoothing circuit 855c. The smoothing circuit 855c removes the supplied +37V ripple to smooth +37V and supplies the smoothed +37V to the firing solenoid drive circuit 858, the ball feeding solenoid drive circuit 859, and the power generation circuit 855d.

The capacitor BC0 supplies backup power to a RAM (main control built-in RAM) built in the main control MPU 4100a of the main control board 4100, and the capacitor BC1 is built in the payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110. The backup power is supplied to the specified RAM (RAM with built-in payout control).

The firing solenoid drive circuit 858 uses the +37V supplied from the smoothing circuit 855c as a drive power source, and is controlled by the firing ball feed control circuit 4120ag built in the payout control MPU 4120a of the payout control board 4110 shown in FIG. 15 to be controlled by the potentiometer 512. The drive current to the firing solenoid 654 is adjusted so that the game ball can be launched (launched) toward the game area 1100 based on the operation signal from. As a result, the game ball can be launched (launched) toward the game area 1100 shown in FIG. 1 with a launching strength (launching strength) corresponding to the rotation position of the rotary handle main body 506 shown in FIG. On the other hand, the ball feed solenoid drive circuit 859 is controlled by the launch ball feed control circuit 4120ag built in the payout control MPU 4120a of the payout control board 4110 shown in FIG. 15 by using +37V supplied from the smoothing circuit 855c as a drive power source. The drive current to the ball feeding solenoid 585 is adjusted to be a constant current. As a result, the ball-sending member of the ball-sending unit 580 receives one game ball stored in the upper plate 301 of the plate unit 300 shown in FIG. 7, and the game ball received by the ball-sending member is sent to the hitting ball launcher 650 side. Can be sent.

The power generation circuit 855d includes a power consumption monitoring circuit 855da, a +5V power generation circuit 855db, a +12V power generation circuit 855dc, and a +24V power generation circuit 855dd. The +37V supplied from the smoothing circuit 855c is supplied to the +5V power generation circuit 855db, the +12V power generation circuit 855dc, and the +24V power generation circuit 855dd via the power consumption monitoring circuit 855da.

The power consumption monitoring circuit 855da monitors the power consumption of +37V supplied from the smoothing circuit 855c. The power consumption monitoring circuit 855da monitors the power consumption amount of +37V supplied from the smoothing circuit 855c, and based on the power consumption amount, determines a power consumption suppression stage indicating how much the power consumption should be suppressed. The determination result is output to the frame peripheral relay terminal board 868 as a power consumption suppression signal. The power consumption suppression signal output from the power consumption monitoring circuit 855da of the power generation circuit 855d is configured as three signal wirings (that is, configured as three parallel signals), and values 0 to 7 are given. Up to eight values can be transmitted to the peripheral control board 4140 via the frame peripheral relay terminal board 868, while the frame peripheral relay terminal board 868 and the peripheral door relay terminal board 882 are used. Input to the frame decoration drive amplifier board 194 (see FIG. 23B). Then, the power consumption suppression signal from the power consumption monitoring circuit 855da of the power supply generation circuit 855d is input to the board or the like on which the door frame is mounted via the frame decoration drive amplifier board 194 (Fig. 23(b)).

Specifically, as shown in FIG. 22A, the power consumption monitoring circuit 855da includes a power measuring circuit 855daa and a power consumption suppressing stage determination circuit 855dab. The +37V supplied from the smoothing circuit 855c is supplied to the +5V power generation circuit 855db, the +12V power generation circuit 855dc, and the +24V power generation circuit 855dd via the power measurement circuit 855daa. The power measurement circuit 855daa measures +37V of power consumption supplied from the smoothing circuit 855c in real time and outputs it to the power consumption suppression stage determination circuit 855dab. The power consumption suppression stage determination circuit 855dab determines a power consumption suppression stage indicating how much power consumption should be suppressed based on the power consumption amount measured by the power measurement circuit 855daa. The value is set to the value of the power consumption suppression signal configured as the signal wiring and output to the frame peripheral relay terminal board 868.

The relationship between the power consumption suppressing stage indicating how much power consumption should be suppressed, the power consumption amount measured by the power measuring circuit 855daa, and the power consumption suppressing stage indicating how much power consumption should be suppressed (that is, the power consumption The relationship between the consumption amount and the power consumption suppression level accompanying the power consumption amount) will be briefly described. In the present embodiment, it is assumed that one transformer (maximum allowable capacity: 250 VA) provided in the pachinko island facility supplies power (AC 24 V) to one pachinko gaming machine 1, and FIG. As shown, when the horizontal axis represents the power consumption amount with respect to the maximum allowable capacity of this transformer and the vertical axes represent stages 0 to 7 as the power consumption suppression stages, the power consumption suppression stage determination circuit 855dab is the power measurement circuit. When the power consumption of +37 V measured at 855 daa is 0% or more and less than 10%, it is determined that the power consumption suppressing step is stage 0, the value 0 is set as the value of the power consumption suppressing signal, and the value is measured by the power measuring circuit 855 daa. When the power consumption amount of +37V is 10% or more and less than 20%, it is determined that the power consumption suppressing step is the stage 1, the value 1 is set as the value of the power consumption suppressing signal, and the power measuring circuit 855daa measures +37V. When the power consumption amount is 20% or more and less than 30%, it is determined that the power consumption suppression stage is the stage 2, the value 2 is set as the value of the power consumption suppression signal, and the power consumption amount of +37 V measured by the power measurement circuit 855daa. Is 30% or more and less than 40%, the value 3 is set as the value of the power consumption suppression signal by determining that the power consumption suppression step is Phase 3, and the power consumption amount of +37V measured by the power measurement circuit 855daa is 40%. When the power consumption is less than 50%, it is determined that the power consumption suppressing step is Step 4, the value 4 is set as the value of the power consumption suppressing signal, and the power consumption of +37V measured by the power measuring circuit 855daa is 50% or more and 60% or more. When it is less than, it is determined that the power consumption suppressing step is Step 5, the value 5 is set as the value of the power consumption suppressing signal, and the power consumption of +37V measured by the power measuring circuit 855daa is 60% or more and less than 70%. Occasionally, it is determined that the power consumption suppressing step is Step 6, and the value 6 is set as the value of the power consumption suppressing signal. When the power consumption of +37V measured by the power measuring circuit 855daa is 70% or more, the power consumption suppressing step is performed. When it is judged to be stage 7, the value 7 is set as the value of the power consumption suppression signal.

In addition, in the pachinko island facility, a system in which, for example, four transformers of the pachinko gaming machines 1 are normally supplied to each transformer as a group, respectively, is supplied (AC24V) (for example, in one row In the pachinko island facility where 20 pachinko gaming machines 1 are installed, 4 pachinko gaming machines 1 are managed as 5 groups, and one transformer is provided for each group (a total of 5 transformers). ), a system in which each power source (AC24V) is supplied is adopted), and a plurality of transformers having a performance of maximum allowable capacity: 1000 VA are provided in the pachinko island facility.

The +5V power supply creation circuit 855db creates a direct current +5V (DC+5V, hereinafter referred to as “+5V”) from +37V supplied from the smoothing circuit 855c via the power consumption monitoring circuit 855da. The +12V power supply creation circuit 855dc creates a direct current +12V (DC+12V, hereinafter referred to as “+12V”) from +37V supplied from the smoothing circuit 855c via the power consumption monitoring circuit 855da. The +24V power supply creation circuit 855dd creates a direct current +24V (DC+24V, hereinafter referred to as “+24V”) from +37V supplied from the smoothing circuit 855c via the power consumption monitoring circuit 855da. +5V, +12V, and +24V are supplied to the payout control board 4110 and the frame peripheral relay terminal board 868, respectively. The power supply system supplied with +5V is supplied as a +5V power supply line, the power supply system supplied with +12V is supplied as a +12V power supply line, and the power supply system supplied with +24V is supplied as a +24V power supply line.

The +5V generated by the +5V power generation circuit 855db of the power generation circuit 855d is supplied to the payout control board 4110, as described later. The +5V supplied to the payout control board 4110 is applied to the power supply terminal of the payout control MPU 4120a via the payout control filter circuit 4110a and to the power supply terminal of the payout control internal RAM via the diode PD0. ing. The +12V generated by the +12V power generation circuit 855dc of the power generation circuit 855d is supplied to the +5V generation circuit 4100g of the main control board 4100 via the payout control board 4110. The +5V creation circuit 4100g creates +5V, which is the control reference voltage of the main control MPU 4100a, from +12V from the payout control board 4110. The +5V generated by the +5V generation circuit 4100g is supplied to the power supply terminal of the main control MPU 4100a via the main control filter circuit 4100h and to the power supply terminal of the main control built-in RAM via the diode MD0. ing.

The minus terminal of the capacitor BC1 of the power supply board 851 is grounded to the ground (GND), while the plus terminal of the capacitor BC1 is electrically connected to the power supply terminal of the payout control built-in RAM of the payout control board 4110, and the payout is performed. It is also electrically connected to the cathode terminal of the diode PD0 of the control board 4110. That is, +5V created by the +5V power supply creation circuit 855db of the power supply creation circuit 855d on the power supply board 851 causes a current to flow toward the power supply terminal of the payout control MPU 4120a, and the power supply of the payout control built-in RAM that is forward by the diode PD0. A current flows toward the terminal and the positive terminal of the capacitor BC1. In this way, the capacitor BC1 is an electrical circuit in which +5V generated by the +5V power supply generation circuit 855db of the power supply generation circuit 855d in the power supply board 851 returns to the power supply board 851 from the payout control board 4110 and again. With various connection methods, +5V can be supplied and charged. As a result, when +5V generated by the +5V power supply generation circuit 855db of the power supply generation circuit 855d is no longer supplied to the payout control board 4110, the charge charged in the capacitor BC1 is supplied to the payout control board 4110 as the payout VBB. Therefore, although the payout VBB is supplied to the power supply terminal of the payout control built-in RAM, although the current is prevented from flowing to the power supply terminal of the payout control MPU 4120a by the diode PD0 and the payout control MPU 4120a does not operate. The stored contents are retained by.

The negative terminal of the capacitor BC0 of the power supply board 851 is grounded to the ground (GND), while the positive terminal of the capacitor BC0 is electrically connected to the power supply terminal of the main control internal RAM of the main control board 4100 via the payout control board 4110. And is also electrically connected to the cathode terminal of the diode MD0 of the main control board 4100. That is, +5V generated by the +5V generation circuit 4100g causes a current to flow toward the power supply terminal of the main control MPU 4100a, and the power supply terminal of the main control built-in RAM in the forward direction by the diode MD0 and the positive terminal of the capacitor BC0. The current is flowing toward. As described above, the capacitor BC0 is supplied with +5V by the electrical connection method in which +5V created by the +5V creation circuit 4100g is supplied from the main control board 4100 and the payout control board 4110 to the power supply board 851. You can do it. As a result, +12V created by the +12V power supply creation circuit 855dc of the power supply creation circuit 855d in the power supply board 851 is not supplied to the +5V creation circuit 4100g of the main control board 4100 via the payout control board 4110, and the +5V creation circuit 4100g is +5V. When it is no longer possible to create the charge, the electric charge charged in the capacitor BC0 is supplied as the main VBB to the main control board 4100 via the payout control board 4110. Therefore, the main control MPU 4100a Although the current does not flow to the power supply terminal of the main control MPU 4100a by the diode MD0 and the main control MPU 4100a does not operate, the main VBB is supplied to the power supply terminal of the main control built-in RAM so that the stored contents are retained. There is.

[8-2. Voltage supplied to each control board, etc.]
Next, an outline of the voltage supplied to each control board and the like will be described, and subsequently, the voltage supplied to the payout control board and the voltage supplied to the main control board will be described.

The three types of voltages of +5V, +12V, and +24V created by the +5V power supply creation circuit 855db, the +12V power supply creation circuit 855dc, and the +24V power supply creation circuit 855dd of the power supply creation circuit 855d on the power supply board 851 are as shown in FIG. Further, among the three types of voltages, two types of voltages of +12V and +24V are supplied to the main control substrate 4100 via the delivery control substrate 4110. Further, three types of voltages of +5V, +12V, and +24V created by the +5V power supply creation circuit 855db, the +12V power supply creation circuit 855dc, and the +24V power supply creation circuit 855dd of the power supply creation circuit 855d on the power supply board 851 are the frame peripheral relay terminals. It is supplied to the board 868 and is also supplied to the peripheral control board 4140 and the peripheral door relay terminal board 882 via the frame peripheral relay terminal board 868.

One type of voltage of +5V supplied to the peripheral control board 4140 is supplied to the lamp drive board 4170, as shown in FIG. The +5V supplied from the peripheral control board 4140 is supplied to the LED control circuit 4170k for the game board side peripheral control MPU control target decoration LED decoration circuit 4170k of the lamp drive board 4170 as a power supply for illumination (also serving as a control voltage). , And is supplied to various electronic components (electronic components having a control voltage of +5V) mounted on the lamp driving board 4170.

The three types of voltages of +5V, +12V, and +24V supplied to the peripheral control board 4140 are respectively supplied to the drive source drive circuit 4180a of the motor drive board 4180, as shown in FIG. The drive source drive circuit 4180a of the motor drive board 4180 is a circuit that outputs a drive signal to an electric drive source such as a motor and a solenoid of the game board 4, and is a diagram for converting serial data provided in the motor drive board 4180 into parallel data. No Parallel signal is input from the serial-parallel conversion circuit. This serial-parallel conversion circuit is a motor, solenoid, etc. for operating various movable bodies provided on the game board 4 via the peripheral control output circuit from the motor drive board serial I/O port of the peripheral control MPU 4150a of the peripheral control board 4140. Is a circuit that can input the game board side motor drive data (serial data) for outputting a drive signal to the electric drive source, convert the serial data into parallel data, and output a parallel signal. The drive source drive circuit 4180a includes a motor drive circuit capable of outputting a drive signal to the motor and a solenoid drive circuit capable of outputting a drive signal to the solenoid in response to the parallel signal from the serial-parallel conversion circuit. I have it. If the motor drive circuit and the solenoid drive circuit have a serial-parallel conversion circuit built-in, there is no need to arrange the serial-parallel conversion circuit in the previous stage, and the peripheral I/O MPU4150a motor drive board serial I/I of the peripheral control MPU4150a can be eliminated. The circuit can be configured so that the game board side motor drive data from the O port is input.

The three types of voltages of +5V, +12V, and +24V supplied to the peripheral control board 4140 are supplied to the liquid crystal output board 3420 as shown in FIG. +24V supplied from the peripheral control board 4140 is supplied to the game board side various light guide plate power supply circuits 3420e of the liquid crystal output board 3420. In the game board side various light guide plate power supply circuits 3420e, a total of six light guide plate power supply circuits, that is, a first light guide plate power supply circuit to a sixth light guide plate power supply circuit, are independently configured, and the light guide plate from +24V. +12V is created as each power source. +12V created by the power source circuit 3420e for various light guide plates on the game board side is supplied to each light guide plate control circuit 3420k. The various light guide plate control circuits 3420k are six independent light guide plate control circuits, that is, a first light guide plate control circuit to a sixth light guide plate control circuit, which will be described later, and six independent light source plate power supply circuits 3420e for the game board side. It is configured independently of the light guide plate power supply circuit and is supplied with +12V. +12V supplied from the peripheral control board 4140 is supplied to the game board side liquid crystal module power supply circuit 3420a of the liquid crystal output board 3420. The game board side liquid crystal module power supply circuit 3420a creates a direct current 3.3V (DC+3.3V, hereinafter referred to as "+3.3V") from +12V. +3.3V created by the game board side liquid crystal module power supply circuit 3420a is supplied to various electronic components (electronic components whose control voltage is +3.3V) mounted on the liquid crystal output substrate 3420, respectively. It is supplied to various electronic components mounted on a board included in the game board side effect display unit 1900. The +5V supplied from the peripheral control board 4140 is supplied to the gaming board side VDP control target decoration LED control circuit 3420i of the liquid crystal output board 3420 as an electric power supply for illumination (also serving as a control voltage). It is supplied to various electronic components (electronic components whose control voltage is +5V) mounted on the output board 3420.

On the other hand, three types of voltages of +5V, +12V, and +24V supplied to the peripheral door relay terminal board 882 are supplied to the frame decoration drive amplifier board 194, as shown in FIG. +5V supplied from the peripheral door relay terminal board 882 is used as a power supply for illumination (also serving as a control voltage) for the frame side VDP control target decoration LED control circuit 194i of the frame decoration drive amplifier board 194 and the frame side peripheral control MPU control. In addition to being supplied to the target decoration LED control circuit 194k, it is also supplied to various electronic components (electronic components whose control voltage is +5V) mounted on the frame decoration drive amplifier board 194. The three types of voltages of +5V, +12V, and +24V are supplied to a motor drive circuit (not shown) that outputs a drive signal to an electric drive source such as a dial drive motor 414 provided on the door frame 5. A parallel signal is input to the motor drive circuit from a serial-parallel conversion circuit (not shown) provided in the frame decoration drive amplifier board 194 and converting serial data into parallel data. This serial-to-parallel conversion circuit is used for electrical control of the dial drive motor 414 or the like provided in the door frame 5 from the peripheral I/O port for the frame decoration drive amplifier board motor of the peripheral control MPU 4150a of the peripheral control board 4140 via the peripheral control output circuit. Door side motor drive data (serial data) for outputting a drive signal to a static drive source is input, and this serial data can be converted into parallel data and a parallel signal can be output. The motor drive circuit can output a drive signal to the dial drive motor 414 or the like according to the parallel signal from the serial-parallel conversion circuit. If the motor drive circuit has a built-in serial-parallel conversion circuit, it is not necessary to dispose the serial-parallel conversion circuit in the preceding stage, so that the peripheral I/O port for the frame decoration drive amplifier board motor of the peripheral control MPU4150a is eliminated. It is possible to configure the circuit so that the door side motor drive data from is input.

In addition, +5V, +12V, and +24V, which are a total of three types of voltages supplied from the peripheral door relay terminal board 882, are supplied to the board and the like on which the door frame is mounted.

[8-2-1. Voltage supplied to payout control board]
As shown in FIG. 21, the payout control board 4110 includes a payout control filter circuit 4110a and the like in addition to the payout control MPU 4120a and the like. The payout control filter circuit 4110a is supplied with +5V from the power supply board 851, and removes noise from this +5V. The +5V is supplied to the capacitor BC1 of the power supply substrate 851 via the diode PD0, and is also supplied to, for example, the payout control MPU 4120a of the payout control unit 4120. +12V from the power supply board 851 is supplied to, for example, the payout control input circuit 4120b of the payout control unit 4120 and the like, and is also supplied to the external communication circuit 784a of the external terminal board 784 via the payout control board 4110. The external communication circuit 784a of the external terminal board 784 outputs a signal that conveys the number of gaming balls paid out by the pachinko gaming machine 1 and the game information of the pachinko gaming machine 1 to a hall computer installed in the gaming hall. Circuit. The hall computer monitors the game of the player by grasping the number of game balls paid out by the pachinko gaming machine 1 and the game information of the pachinko gaming machine 1 from the signal output from the external communication circuit 784a. .. Note that +24 from the power supply board 851 is not used in the payout control board 4110 at all, and is supplied to the main control board 4100 via the payout control board 4110.

[8-2-2. Voltage supplied to main control board]
As shown in FIG. 21, the main control board 4100 includes, in addition to the main control MPU 4100a and the like, a +5V generation circuit 4100g, a main control filter circuit 4100h, a power failure monitoring circuit 4100e and the like. The +5V creation circuit 4100g is supplied with +12V from the power supply board 851 via the payout control board 4110, and creates +5V, which is the control reference voltage of the main control MPU 4100a, from this +12V. In the main control board 4100, the power supply system created by the +5V creation circuit 4100g and supplied with +5V is a +5V power supply line. In this embodiment, the +5V power supply line created by the +5V power supply creation circuit 855db of the power supply creation circuit 855d and the +5V power supply line created by the +5V creation circuit 4100g of the main control board 4100 are electrically connected to each other in the power supply board 85. Since the circuit is configured not to be connected, the +5V power supply line created by the +5V power supply creation circuit 855db of the power supply creation circuit 855d in the power supply board 851 is electrically connected to various electronic components of the main control board 4100. Also, the +5V power supply line created by the +5V creation circuit 4100g of the main control board 4100 is not electrically connected to various electronic components such as other boards except the main control board 4100.

The main control filter circuit 4100h is supplied with +5V created by the +5V creation circuit 4100g, and removes noise from this +5V. This +5V is supplied to the capacitor BC0 of the power supply substrate 851 via the diode MD0, and is also supplied to, for example, the main control MPU 4100a. +12V from the payout control board 4110 is supplied to, for example, the main control input circuit 4100b, and +24V from the payout control board 4110 is supplied to, for example, the main control solenoid drive circuit 4100d.

The power failure monitoring circuit 4100e is supplied with +12V and +24V from the power supply board 851 through the payout control board 4110, and monitors the signs of power failure or momentary power failure of these +12V and +24V. The power failure monitoring circuit 4100e outputs a power failure notification signal to the main control MPU 4100a as a power failure notification when detecting signs of +12V and +24V power failure or momentary power failure. The power failure notice signal is input to the payout control MPU 4120a via the main control board 4100 and the payout control input circuit 4120b of the payout control board 4110. Further, the power failure notice signal is input to the peripheral control board 4140 via the main control board 4100. The power failure notice signal is input to the frame decoration drive amplifier board 194 through the peripheral control board 4140, the frame peripheral relay terminal board 868, and the peripheral door relay terminal board 882 as shown in FIG. At the same time, the data is input via the frame decoration drive amplifier board 194 to the board on which the door frame is mounted.

In the present embodiment, the power failure monitoring circuit 4100e applies the voltage to one of the +12V power line and the +24V power line by monitoring the voltage applied to each of the two power lines, the +12V power line and the +24V power line. Compared with the case of monitoring the generated voltage, it is possible to more accurately grasp the sign of power failure such as power failure or momentary power failure.

[9. Main control board circuit]
Next, the circuit of the main control board 4100 shown in FIG. 14 will be described with reference to FIGS. 24 is a circuit diagram showing a circuit of the main control board, FIG. 25 is a circuit diagram showing a power failure monitoring circuit, and FIG. 26 is a circuit showing a communication interface circuit between the main control board and the peripheral control board. It is a figure. First, the main control filter circuit 4100h shown in FIG. 21 will be described, and subsequently, the power supply created by the main control board 4100, the main control system reset, the main control crystal oscillator, the main control input circuit, the power failure monitoring circuit, and the main control MPU. Various input/output signals to and from the main control board 4100 and the peripheral control board 4140 will be described.

The main control board 4100 includes a main control MPU 4100a, a main control input circuit 4100b, a main control output circuit 4100c, a main control solenoid drive circuit 4100d, a power failure monitoring circuit 4100e, a +5V generation circuit 4100g, and a main control circuit 4100 shown in FIGS. In addition to the control filter circuit 4100h, as a peripheral circuit, as shown in FIG. 24, a main control system reset MIC1 that outputs a reset signal, and a main control crystal oscillator MX0 that outputs a clock signal (in the present embodiment, 24 MHz (MHz) )) is mainly composed.

[9-1. Main control filter circuit]
As shown in FIG. 24, the main control filter circuit 4100h mainly includes a main control 3-terminal filter MIC0. The main control three-terminal filter MIC0 is a T-type filter circuit and is magnetically shielded with ferrite and has excellent attenuation characteristics. The main control 3-terminal filter MIC0 is applied with +5V created by the +5V creating circuit 4100g at its 1st terminal, its 2nd terminal is grounded (GND), and the noise component is removed from its 3rd terminal. +5V is output. The +5V applied to the first terminal is first electrically connected to the other end of the capacitor MC0 whose one end is grounded (GND), so that the ripple (AC component superimposed on the voltage) is removed first. Have been smoothed.

The +5V output from the third terminal is electrically connected to the other ends of the capacitor MC1 and the electrolytic capacitor MC2 (electrostatic capacitance: 470 microfarads (μF) in this embodiment) whose one end is grounded to the ground (GND). By being connected to, the ripple is further removed and smoothed. The smoothed +5V is applied to the power supply terminal of the main control system reset MIC1, the VDD terminal which is the power supply terminal of the main control crystal oscillator MX0, the VDD terminal which is the power supply terminal of the main control MPU 4100a, and the like. In addition, in the VDD terminal which is a power supply terminal of the main control MPU 4100a, when a power failure or a momentary power failure occurs and the power supply from the pachinko island facility is shut off, the electric charge charged in the electrolytic capacitor MC2 causes a power failure or a momentary power failure. It is adapted to be applied as +5 V for a period of about 7 milliseconds (ms) after the generation.

The VDD terminal of the main control MPU 4100a is electrically connected to the other end of the capacitor MC3 whose one end is grounded (GND), and +5V applied to the VDD terminal is smoothed by further removing ripples. The VSS terminal which is the ground terminal of the main control MPU 4100a is grounded to the ground (GND).

The VDD terminal of the main control MPU 4100a is electrically connected to the capacitor MC3 and also to the anode terminal of the diode MD0. A cathode terminal of the diode MD0 is electrically connected to a VBB terminal which is a power supply terminal of a RAM (main control built-in RAM) built in the main control MPU 4100a, and one end of which is connected to the ground (GND) to form a capacitor MC4. Is electrically connected to the other end of. The VBB terminal of the RAM with built-in main control is electrically connected to the cathode terminal of the diode MD0 and the other end of the capacitor MC4, and is also connected to the plus side of the capacitor BC0 of the power supply substrate 851 shown in FIG. It is electrically connected to the terminal. That is, +5V, which has been smoothed by removing the noise component by the main control filter circuit 4100h, is applied to the VDD terminal of the main control MPU 4100a, and via the diode MD0, the VBB terminal of the main control internal RAM and the capacitor BC0. It is designed to be applied to the positive terminal of and. Thereby, as described above, +12V created by the +12V power supply creation circuit 855dc of the power supply creation circuit 855d in the power supply board 851 shown in FIG. When the +5V generation circuit 4100g cannot supply +5V because it is no longer supplied, the electric charge charged in the capacitor BC0 is supplied to the main control board 4100 as the main VBB. Although the current does not flow to the VDD terminal of the MPU 4100a by the diode MD0 and the main control MPU 4100a does not operate, the memory content is retained by applying the main VBB to the VBB terminal of the main control internal RAM. ing.

[9-2. Main control system reset]
As shown in FIG. 24, +5V in which the noise component is removed and smoothed by the main control filter circuit 4100h is applied to the power supply terminal of the main control system reset MIC1. The main control system reset MIC1 resets the main control MPU 4100a and the main control output circuit 4100ca with a reset function, and has a delay circuit built therein. One end of the main control system reset MIC1 is electrically connected to the other end of the capacitor MC5 whose one end is grounded (GND), and the delay time of the delay circuit is set by the capacitance of the capacitor MC5. You can do it. Specifically, the main control system reset MIC1 outputs a system reset signal from the output terminal after a delay time has elapsed when +5V input to the power supply terminal reaches a threshold value (for example, 4.25V).

The output terminal of the main control system reset MIC1 is electrically connected to the SRST terminal which is the reset terminal of the main control MPU 4100a and the reset terminal of the main control output circuit 4100ca with a reset function. The output terminal is an open collector output type, one end of which is electrically connected to the other end of the pull-up resistor MR1 electrically connected to the +5V power supply line, and one end of which is a capacitor grounded to the ground (GND). It is electrically connected to the other end of MC6. The ripple is removed and smoothed by this capacitor MC6. When the voltage input to the power supply terminal is higher than the threshold value, the output terminal is pulled up to +5V by the pull-up resistor MR1 and the logic becomes HI, and this logic becomes the SRST terminal of the main control MPU 4100a and the main control output with reset function. When the voltage input to the power supply terminal is smaller than the threshold value while being input to the reset terminal of the circuit 4100ca, the logic becomes LOW, and this logic is the SRST terminal of the main control MPU 4100a and the main control output circuit 4100ca with the reset function. Input to each reset terminal. Since the SRST terminal of the main control MPU 4100a and the reset terminal of the main control output circuit 4100ca with the reset function are negative logic inputs, when the voltage input to the power supply terminal is lower than the threshold value, the main control MPU 4100a and the reset function are activated. The associated main control output circuit 4100ca is reset. The power supply terminal is electrically connected to the other end of the capacitor MC7 whose one end is grounded to the ground (GND), and +5V input to the power supply terminal is smoothed by removing ripples. The ground terminal is grounded to the ground (GND), and the NC terminal is not electrically connected to the outside.

[9-3. Main control crystal oscillator]
As shown in FIG. 24, +5V in which the noise component is removed and smoothed by the main control filter circuit 4100h is applied to the VDD terminal which is the power supply terminal of the main control crystal oscillator MX0. The VDD terminal is electrically connected to the other end of the capacitor MC8 whose one end is grounded to the ground (GND), and +5V input to the VDD terminal is smoothed by further removing ripples. In addition to the VDD terminal, the smoothed +5V is also applied to the output frequency selection terminals A terminal, B terminal, C terminal and ST terminal. The main control crystal oscillator MX0 outputs a clock signal of 24 MHz from an F terminal, which is an output terminal, by applying +5 V to each of the A terminal, the B terminal, the C terminal, and the ST terminal.

The F terminal of the main control crystal oscillator MX0 is electrically connected to the CLK terminal which is the clock terminal of the main control MPU 4100a, and the clock signal of 24 MHz is input. The GND terminal, which is the ground terminal of the main control crystal oscillator MX0, is grounded to the ground (GND), and the D terminal for outputting the divided frequency of the F terminal of the main control crystal oscillator MX0 is not electrically connected to the outside. It is in a state.

[9-4. Main control input circuit]
The main control input circuit 4100b detects from the general winning a prize mouth switches 3020 and 3020, the first starting mouth switch 3022, the second starting mouth switch 2109, the magnetic detection switch 304, the count switch 2110, and the gate switch 2352 shown in FIG. In addition to the signals, this is a circuit to which an operation signal (RAM clear signal) from the operation switch 860a provided in the payout control board 4110 shown in FIG. 15 is input. Since the circuit configuration to which the detection signal from each switch is input is the same, the circuit to which the operation signal (RAM clear signal) from the operation switch 860a is input will be described here.

[9-4-1. Circuit to which operation signal (RAM clear signal) from operation switch is input]
First, as described above, the operation switch 860a includes the RAM (payout control built-in RAM) built in the payout control MPU 4120a of the payout control board 4110 and the main control board 4100 within a predetermined period after the power is turned on. It is operated to clear the RAM (RAM with built-in main control) built in the MPU 4100a, or to cancel the error when an error is reported after the power is turned on. A function to clear the RAM within a predetermined period after the power is turned on, and an error release after the power is turned on (after the period for performing the function as RAM clear has passed, that is, after the predetermined period has passed since the power was turned on) And the function of performing. Since the main control board 4100 does not have the function of canceling the error that the payout control board 4110 has, the main control board 4100 will not operate when an operation signal from the operation switch 860a is input within a predetermined period after the power is turned on. A process for clearing the main control built-in RAM is performed by judging it as a RAM clear signal for clearing the built-in RAM.

To the main control board 4100, when the operation switch 860a is not operated, an operation signal whose logic is LOW is input from the payout control board 4110, while when the operation switch 860a is operated, the logic is output from the payout control board 4110. The operation signal in which HI becomes HI is input from the payout control board 4110 (a detailed description of this point will be described later).

As shown in FIG. 24, the transmission line for transmitting the operation signal from the operation switch 860a provided on the payout control board 4110 within a predetermined period after the power is turned on has one end which is electrically connected to the +12V power line. It is electrically connected to the other end of the resistor MR2 and is electrically connected to the base terminal of the transistor MTR0 via the resistor MR3. The base terminal of the transistor MTR0 is electrically connected to the resistor MR3, and is also electrically connected to the other end of the resistor MR4 having one end grounded to the ground (GND). The emitter terminal of the transistor MTR0 is grounded to the ground (GND), and the collector terminal of the transistor MTR0 is electrically connected to the other end of the resistor MR5 whose one end is electrically connected to the +5V power supply line and also the non-inverting buffer. Main control via ICMIC10 (non-inverting buffer ICMIC10 is provided with eight non-inverting buffer circuits, and the logic of the signal waveform input to one of them (MIC10A) is shaped and output without being inverted). It is electrically connected to the input terminal PA0 of the input port PA of the MPU 4100a.

The circuit that outputs the operation signal from the operation switch 860a in the payout control board 4110 is configured as an open collector output type in which the emitter terminal is grounded to the ground (GND), and the operation signal transmitted from the operation switch 860a is transmitted. The line is pulled up to the +12V side by the pull-up resistor MR2. In the main control board 4100, when the operation switch 860a is not operated, the operation signal from the payout control board 4110 is pulled down to the ground (GND) side and the logic becomes LOW, and the operation switch 860a is operated. During this time, the operation signal from the payout control board 4110 is pulled up to the +12V side by the pull-up resistor MR2 and the logic becomes HI and is input.

The circuit composed of the resistors MR3 and MR4 and the transistor MTR0 is a switch circuit that is turned on/off by an operation signal from the operation switch 860a.

When the operation switch 860a is not operated, the operation signal whose logic becomes LOW is input to the base terminal of the transistor MTR0, whereby the transistor MTR0 turns off and the switch circuit also turns off. As a result, the voltage applied to the collector terminal of the transistor MTR0 is pulled up to the +5V side by the resistor MR5 and the logic becomes HI. The operation signal from the operation switch 860a is input to the input terminal PA0 of the input port PA of the main control MPU4100a. To be done. The main control MPU 4100a must instruct to perform the RAM clear for erasing the information stored in the main control internal RAM when the logical value of the operation signal from the operation switch 860a input to the input terminal PA0 is HI. to decide.

On the other hand, when the operation switch 860a is operated, the operation signal which is pulled up to +12V by the pull-up resistor MR2 and has the logic of HI is input to the base terminal of the transistor MTR0 to turn on the transistor MTR0, The circuit will also turn on. Accordingly, the voltage applied to the collector terminal of the transistor MTR0 is pulled down to the ground (GND) side, and the operation signal from the operation switch 860a whose logic becomes LOW is input to the input terminal PA0 of the input port PA of the main control MPU4100a. To be done. The main control MPU 4100a is for instructing to perform a RAM clear for erasing the information stored in the main control internal RAM when the logical value of the operation signal from the operation switch 860a input to the input terminal PA0 is LOW. To judge.

The operation signal from the operation switch 860a is pulled up to the +12V side by the pull-up resistor MR2. This is because the operation signal from the operation switch 860a is input through the payout control board 4110. That is, between the main control board 4100 and the payout control board 4110, in order to suppress the influence of noise that enters the wiring (harness) that electrically connects the boards, the voltage is higher than the control reference voltage of +5V. The signal reliability is enhanced by using +12V which is the voltage. Therefore, in the present embodiment, the detection signals from the general winning opening switch 3020, the first starting opening switch 3022, and the second starting opening switch 2109 that are directly input to the main control board 4100 are moved to the +5V side by the pull-up resistor. While being pulled up, the detection signals from the magnetic detection switch 3024, the count switch 2110, the general winning opening switch 3020, and the gate switch 2352, which are input via the panel relay terminal board 4161 shown in FIG. 14, are detected by the main control board 4100. Since it is not directly input to, the voltage is pulled up to the +12V side by the pull-up resistor like the operation signal from the operation switch 860a.

[9-5. Blackout monitoring circuit]
As shown in FIG. 21, the main control board 4100 is supplied with two types of voltages of +12V and +24V from the power supply board 851 through the payout control board 4110, and +12V and +24V are input to the power failure monitoring circuit 4100e. ing. The power outage monitoring circuit 4100e monitors the signs of +12V and +24V power outages or instantaneous blackouts, and when the signs of the power outages or instantaneous blackouts are detected, a power outage notification signal is issued as a power outage notice in addition to the main control MPU 4100a and the payout control board. It is output to the payout control MPU 4120a of 4110 and the peripheral control board 4140. Here, first, the configuration of the power failure monitoring circuit will be described, and then the power failure or instantaneous power failure of +24V, the power failure or instantaneous power failure of +12V, and the output of the power failure warning signal will be described.

[9-5-1. Configuration of power failure monitoring circuit]
As shown in FIG. 25, the power failure monitoring circuit 4100e mainly includes a shunt type stabilized power supply circuit MIC20, an open collector output type comparator MIC21, a D type flip-flop MIC22, and transistors MTR20 to MTR23.

The REF terminal which is the reference voltage input terminal and the K terminal which is the cathode terminal of the shunt-type stabilized power supply circuit MIC20 are electrically connected to the other end of the resistor MR20 whose one end is electrically connected to the +5V power supply line. +5V is applied, and the current input to the REF terminal is limited by the resistor MR20. The K terminal outputs a reference voltage Vref (2.495 V is set in the present embodiment) which is a comparison reference voltage of the comparator MIC21. The K terminal is electrically connected to the other end of the capacitor MC20 whose one end is grounded to the ground (GND), and the reference voltage Vref output from the K terminal is rippled by the capacitor MC20 (multiplied by the voltage). AC component) is removed and smoothed. The A terminal which is the anode terminal of the shunt-type stabilized power supply circuit MIC20 is grounded to the ground (GND).

The comparator MIC21 includes two voltage comparison circuits, one of which (MIC21A) is used for comparing the monitor voltage V1 of +24V and the reference voltage Vref, and the other one (MIC21B). , +12V monitor voltage V2 and reference voltage Vref are used for comparison. The monitoring voltage V1 of +24V is applied to the third terminal which is the positive terminal of the MIC21A, and the reference voltage Vref is applied to the second terminal which is the negative terminal of the MIC21A. The monitoring voltage V2 of +12V is applied to the 5th terminal which is the plus terminal of the MIC 21B, and the reference voltage Vref is applied to the 6th terminal which is the minus terminal of the MIC 21B. The results of these comparisons are input to the D type flip-flop MIC22. The D-type flip-flop MIC22 includes two D-type flip-flop circuits, one of which (MIC22A) is used in this embodiment. The Vcc terminal which is the power supply terminal of the comparator MIC21 is electrically connected to the other end of the capacitor MC21 whose one end is grounded (GND), and +5 V applied to the Vcc terminal which is the power supply terminal of the comparator MIC21 is The ripple is removed and smoothed by the capacitor MC21, and the GND terminal which is the ground terminal of the comparator MIC21 is grounded to the ground (GND).

[9-5-2. +24V power failure or momentary power failure monitoring]
As described above, the +24V power failure or the instantaneous blackout is monitored by the MIC 21A of the comparator MIC21 comparing the +24V monitoring voltage V1 with the reference voltage Vref. As shown in FIG. 25, the third terminal, which is the plus terminal of the MIC21A of the comparator MIC21 to which the monitoring voltage V1 of +24V is applied, has one end and the other end of the resistor MR21 electrically connected to the +24V power supply line. Is electrically connected to the other end of the resistor MR22 that is grounded to the ground (GND), the other ends of the resistors MR21 and MR22, and the other end of the capacitor MC23 whose one end is grounded to the ground (GND). Are electrically connected. The +24V monitoring voltage V1 applied to the third terminal, which is the positive terminal of the MIC21A of the comparator MIC21, is +24V divided by the resistance ratio of the resistors MR21 and MR22, and smoothed by removing the ripple by the capacitor MC23. .. The values of the resistors MR21 and MR22 are set to a preset power failure detection voltage V1pf (21.40V in the present embodiment) when the voltage of +24V or a momentary power failure causes the voltage to start to drop from +24V. Then, the monitor voltage V1 of +24V is set to have the same value as the reference voltage Vref.

The first terminal, which is the output terminal of the MIC21A of the comparator MIC21, is an open collector output, and is electrically connected to the other end of the pull-up resistor MR23 whose one end is electrically connected to the +5V power supply line, and One end is electrically connected to the other end of the capacitor MC24, which is grounded to the ground (GND), and is electrically connected to the PR terminal which is the preset terminal of the D type flip-flop MIC22. The capacitor MC24 plays a role as a low-pass filter.

When the voltage of +24V is higher than the power failure detection voltage V1pf, the monitoring voltage V1 of +24V becomes higher than the reference voltage Vref, and the voltage applied to the first terminal which is the output terminal of the MIC21A of the comparator MIC21 is +5V by the pull-up resistor MR23. The signal that is pulled up to the side and the logic becomes HI is input to the PR terminal which is the preset terminal of the D type flip-flop MIC22.

On the other hand, when the voltage of +24V is smaller than the power failure detection voltage V1pf, the monitoring voltage V1 of +24V becomes smaller than the reference voltage Vref, and the voltage applied to the first terminal which is the output terminal of the MIC21A of the comparator MIC21 is the ground (GND). The signal that is pulled down to the logic level and becomes LOW is input to the PR terminal which is the preset terminal of the D type flip-flop MIC22.

[9-5-3. +12V power failure or momentary power failure monitoring]
As described above, the +12V power failure or the instantaneous blackout is monitored by the MIC 21B of the comparator MIC21 comparing the +12V monitoring voltage V2 with the reference voltage Vref. As shown in FIG. 25, the fifth terminal, which is the plus terminal of the MIC21B of the comparator MIC21 to which the +12V monitoring voltage V2 is applied, has one end and the other end of the resistor MR24 electrically connected to the +12V power line. Is electrically connected to the other end of the resistor MR25 that is grounded to the ground (GND), the other ends of the resistors MR24 and MR25, and the other end of the capacitor MC25 whose one end is grounded to the ground (GND). Are electrically connected. The +12V monitoring voltage V2 applied to the 5th terminal, which is the positive terminal of the MIC21B of the comparator MIC21, is +12V divided by the resistance ratio of the resistors MR24 and MR25, and ripples are removed and smoothed by the capacitor MC25. .. The values of the resistors MR24 and MR25 are set to a preset power failure detection voltage V2pf (set to 10.47V in this embodiment) when the voltage of +12V starts a power failure or an instantaneous power failure and the voltage starts to drop from +12V. In this case, the monitor voltage V2 of +12V is set to have the same value as the reference voltage Vref.

The output terminal of the MIC21B of the comparator MIC21, the 7th terminal, is an open collector output and is electrically connected to the 1st terminal which is the output terminal of the MIC 21A described above. Of the D-type flip-flop MIC22 by being electrically connected to the other end of the pull-up resistor MR23 which is electrically connected and also electrically connected to the other end of the capacitor MC24 which is grounded to the ground (GND). It is electrically connected to the PR terminal which is a terminal. The capacitor MC24 plays a role as a low-pass filter as described above.

When the voltage of +12V is higher than the power failure detection voltage V2pf, the monitoring voltage V2 of +12V becomes higher than the reference voltage Vref, and the voltage applied to the 7th terminal which is the output terminal of the MIC21B of the comparator MIC21 is +5V by the pull-up resistor MR23. The signal that has been pulled to the side and whose logic has become HI is input to the PR terminal which is the preset terminal of the D type flip-flop MIC22.

On the other hand, when the +12V voltage is lower than the power failure detection voltage V2pf, the +12V monitoring voltage V2 becomes lower than the reference voltage Vref, and the voltage applied to the 7th terminal which is the output terminal of the MIC21B of the comparator MIC21 is the ground (GND). The signal that is pulled down to the logic level and becomes LOW is input to the PR terminal which is the preset terminal of the D type flip-flop MIC22.

[9-5-4. Output of power failure warning signal]
The D-type flip-flop MIC22 stores the value (logic) of the signal input to the 1D terminal, which is the D input terminal, according to the change in the edge of the clock signal input to the 1CK terminal, which is the clock input terminal. (Logic) is output from the output terminal 1Q terminal, and a value obtained by inverting the stored value (logic) is output from the output terminal negative logic 1Q terminal. Further, the D-type flip-flop MIC22 releases the latch state when the signal whose logic becomes LOW is input to the CLR terminal which is the clear terminal, and outputs the logic of the signal input to the PR terminal which is the preset terminal. The inverted signal is output from the 1Q terminal which is the output terminal (at this time, the same logic as that of the signal which is obtained by inverting the logic of the signal output from 1Q, that is, the signal input to the PR terminal which is the preset terminal. On the other hand, when the signal having the logic HI is input to the CLR terminal which is the clear terminal, the latched state is set. Further, when the D type flip-flop MIC22 is set to the latch state by inputting the signal whose logic is HI to the CLR terminal which is the clear terminal, the logic is LOW to the PR terminal which is the preset terminal. When this signal is input, a state in which a signal whose logic is HI is output from the output terminal 1Q is maintained (at this time, a signal obtained by inverting the logic of the signal output from 1Q is negative logic). Maintain the status output from the 1Q terminal).

In the D-type flip-flop MIC22, in the present embodiment, since the 1D terminal which is the D input terminal and the 1CK terminal which is the clock input terminal are respectively grounded to the ground (GND), they are connected to the 1CK terminal which is the clock input terminal. The circuit is configured so that the edge of the input clock signal does not change and the value (logic) of the signal input to the 1D terminal, which is the D input terminal, is not stored and output from the 1Q terminal, which is the output terminal. ing. As described above, the D type flip-flop MIC22 has a signal from the first terminal, which is the output terminal of the MIC21A of the comparator MIC21 that monitors the power failure or the instantaneous power failure of +24V, and the power failure of +12V, to the PR terminal which is the preset terminal. Alternatively, the signal from the terminal 7 which is the output terminal of the MIC 21B of the comparator MIC21 that monitors the instantaneous power failure is input, and based on these signals, the signal is output from the 1Q terminal which is the output terminal. The Vcc terminal which is the power supply terminal is electrically connected to the other end of the capacitor MC22 whose one end is grounded (GND) and is applied to the Vcc terminal which is the power supply terminal of the D type flip-flop MIC22. +5V is smoothed by removing ripples by the capacitor MC22, the GND terminal which is the ground terminal is grounded to the ground (GND), and the negative logic 1Q terminal which inverts the logic of the 1Q terminal which is the output terminal is electrically connected to the outside. Is not connected.

In the D-type flip-flop MIC22, in the present embodiment, the power failure clear signal from the main control MPU 4100a is input to the CLR terminal which is a clear terminal through the main control output circuit 4100ca with a reset function. This power failure clear signal is started to be output and stopped after a lapse of a predetermined time in a main control side power-on process, which will be described later, performed by the main control MPU 4100a. Since the CLR terminal is a negative logic input, the logic of the power failure clear signal from the main control MPU 4100a becomes LOW and is input to the CLR terminal via the main control output circuit with reset function 4100ca. The D-type flip-flop MIC22 is designed to release the latched state when a power failure clear signal is input to the CLR terminal. At this time, the logic input to the PR terminal, which is a preset terminal, is inverted to an output terminal. Output from the 1Q terminal.

On the other hand, when the output of the power failure clear signal from the main control MPU 4100a is stopped, the logic becomes HI and is input to the CLR terminal via the main control output circuit with reset function 4100ca. The D type flip-flop MIC22 sets a latch state when the power failure clear signal is not input to the CLR terminal, and latches the input state in which the logic is LOW at the PR terminal.

The 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, is electrically connected to the input terminal PA1 of the input port PA of the main control MPU 4100a via the main control input circuit 4100b, and is the output terminal of the D-type flip-flop MIC22. The signal output from the 1Q terminal is input to the input terminal PA1 of the input port PA of the main control MPU4100a as a power failure notice signal. The 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, is electrically connected to the main control output circuit 4100cb without the reset function, and resets the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22. The functionless main control output circuit 4100cb outputs it to the payout control board 4110 as a payout blackout warning signal, and also outputs it to the peripheral control board 4140 as a peripheral blackout warning signal.

As shown in FIG. 25, the main control input circuit 4100b that electrically connects the 1Q terminal, which is the output terminal of the D type flip-flop MIC22, and the input terminal PA1 of the input port PA of the main control MPU 4100a. The 1Q terminal, which is the output terminal of the MIC22, is electrically connected to the other end of the resistor MR26 whose one end is electrically connected to the +5V power supply line, and is electrically connected to the base terminal of the transistor MTR20 via the resistor MR27. It is connected. The base terminal of the transistor MTR20 is electrically connected to the resistor MR27, and is also electrically connected to the other end of the resistor MR28 having one end grounded to the ground (GND). The emitter terminal of the transistor MTR20 is grounded to the ground (GND), and the collector terminal of the transistor MTR20 is electrically connected to the other end of the resistor MR29 whose one end is electrically connected to the +5V power supply line and also has a non-inverting buffer. Main control via ICMIC23 (non-inverting buffer ICMIC23 is provided with eight non-inverting buffer circuits, and the logic of the signal waveform input to one of them (MIC23A) is shaped and output without inverting). It is electrically connected to the input terminal PA1 of the input port PA of the MPU 4100a.

The circuit composed of the resistors MR27 and MR28 and the transistor MTR20 is a switch circuit which is turned on/off by a signal output from the 1Q terminal which is the output terminal of the D-type flip-flop MIC22.

When the logic of the signal output from the 1Q terminal which is the output terminal of the D-type flip-flop MIC22 is LOW, the voltage applied to the base terminal of the transistor MTR20 is pulled down to the ground (GND) side and the transistor MTR20 turns off. , The switch circuit is also turned off. On the other hand, when the logic of the signal output from the 1Q terminal which is the output terminal of the D-type flip-flop MIC22 is HI, the voltage applied to the base terminal of the transistor MTR20 is pulled up to +5V and the transistor MTR20 is turned on. The switch circuit is also turned on.

When both the condition that the voltage of +24V is higher than the power failure detection voltage V1pf and the condition that the voltage of +12V is higher than the power failure detection voltage V2pf are satisfied, the signal whose logic becomes HI is preset in the D type flip-flop MIC22. Since the signal is output to the PR terminal, which is a terminal, the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, has its logic level LOW and is input to the base terminal of the transistor MTR20. Turn off. As a result, the voltage applied to the collector terminal of the transistor MTR20 is pulled up to the +5V side by the resistor MR29 and the logic becomes HI via the non-inverting buffer ICMIC23. Input to PA1.

On the other hand, when one of the conditions that the voltage of +24V is lower than the power failure detection voltage V1pf and the condition that the voltage of +12V is lower than the power failure detection voltage V2pf is satisfied, the signal whose logic becomes LOW is D. Since it is input to the PR terminal, which is the preset terminal of the type flip-flop MIC22, the signal output from the 1Q terminal, which is the output terminal of the D type flip-flop MIC22, has its logic set to HI and is input to the base terminal of the transistor MTR20. This turns on the transistor MTR20. As a result, the voltage applied to the collector terminal of the transistor MTR20 is lowered to the ground (GND) side, and the power failure warning signal whose logic becomes LOW via the non-inverting buffer ICMIC23 is the input terminal of the input port PA of the main control MPU4100a. Input to PA1.

Further, as shown in FIG. 25, the main control output circuit 4100cb without a reset function, which outputs the signal output from the 1Q terminal which is the output terminal of the D type flip-flop MIC22 to the payout control board 4110 as a payout power failure notice signal, is open. The circuit is configured as a collector output type, the 1Q terminal which is the output terminal of the D type flip-flop MIC22 is electrically connected to the resistor MR26 of the main control input circuit 4100b described above, and the transistor MTR21 of the preceding stage is connected via the resistor MR30. It is electrically connected to the base terminal. The base terminal of the preceding-stage transistor MTR21 is electrically connected to the resistor MR30, and is also electrically connected to the other end of the resistor MR31 whose one end is grounded to the ground (GND). The emitter terminal of the previous-stage transistor MTR21 is grounded to the ground (GND), and the collector terminal of the previous-stage transistor MTR21 is electrically connected to the other end of the resistor MR32 whose one end is electrically connected to the +5V power supply line. At the same time, it is electrically connected to the base terminal of the transistor MTR22 in the subsequent stage through the resistor MR33. The base terminal of the transistor MTR22 in the subsequent stage is electrically connected to the resistor MR33, and is also electrically connected to the other end of the resistor MR34 whose one end is grounded to the ground (GND). The emitter terminal of the transistor MTR22 in the subsequent stage is grounded to the ground (GND), and the collector terminal of the transistor MTR22 in the subsequent stage is electrically connected to the other end of the capacitor MC26 whose one end is grounded to the ground (GND), and wiring. It is electrically connected to the payout control board 4110 via a (harness). When the collector terminal of the transistor MTR22 in the subsequent stage is electrically connected to the payout control board 4110 via a wiring (harness), the payout control input of the payout control section 4120 shown in FIG. In the circuit 4120b, one end is electrically connected to the other end of a pull-up resistor (not shown) that is electrically connected to the +12V power supply line, and the output terminal MPU4120a shown in FIG. Connected to each other.

The circuit composed of the resistors MR30 and MR31 and the transistor MTR21 in the preceding stage is a switch circuit in the preceding stage, and the circuit composed of the resistors MR33 and MR34 and the transistor MTR22 in the following stage is a switch circuit in the subsequent stage, and is a D type flip-flop. It is turned on/off by a signal output from the 1Q terminal which is an output terminal of the MIC 22.

When the logic of the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, is LOW, the voltage applied to the base terminal of the transistor MTR21 in the previous stage is pulled down to the ground (GND) side, and The MTR21 is turned off and the switch circuit in the previous stage is also turned off, and the voltage applied to the collector terminal of the transistor MTR21 in the previous stage, which is the voltage applied to the base terminal of the transistor MTR22 in the subsequent stage, is increased to +5V by the resistor MR32. As a result, the transistor MTR22 in the subsequent stage is turned on, and the switch circuit in the subsequent stage is also turned on. On the other hand, when the logic of the signal output from the 1Q terminal which is the output terminal of the D-type flip-flop MIC22 is HI, the voltage applied to the base terminal of the transistor MTR21 is pulled up to +5V and the transistor MTR21 is turned on, The switch circuit in the preceding stage is also turned on, and the voltage applied to the collector terminal of the transistor MTR21 in the preceding stage, which is the voltage applied to the base terminal of the transistor MTR22 in the following stage, is lowered to the ground (GND) side, so that The transistor MTR22 is turned off, and the switch circuit in the subsequent stage is also turned off.

When both the condition that the voltage of +24V is higher than the power failure detection voltage V1pf and the condition that the voltage of +12V is higher than the power failure detection voltage V2pf are satisfied, the signal whose logic becomes HI is preset in the D type flip-flop MIC22. Since the signal is output to the PR terminal, which is a terminal, the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, has its logic set to LOW and is input to the base terminal of the transistor MTR21 in the previous stage. Transistor MTR21 turns off. As a result, the voltage applied to the collector terminal of the transistor MTR21 in the preceding stage is pulled up to +5 V by the resistor MR32 and applied to the base terminal of the transistor MTR22 in the following stage, so that the transistor MTR22 in the subsequent stage is turned on. As a result, the voltage applied to the collector terminal of the transistor MTR22 in the subsequent stage is pulled down to the ground (GND) side in the payout control board 4110 via the wiring (harness), and the payout power failure notice signal whose logic becomes LOW is paid out. It is input to the control board 4110.

On the other hand, when one of the conditions that the voltage of +24V is lower than the power failure detection voltage V1pf and the condition that the voltage of +12V is lower than the power failure detection voltage V2pf is satisfied, the signal whose logic becomes LOW is D. Since it is input to the PR terminal, which is the preset terminal of the type flip-flop MIC22, the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, has the logic HI and is applied to the base terminal of the transistor MTR21 at the preceding stage. By the input, the transistor MTR21 in the previous stage is turned on. As a result, the voltage applied to the collector terminal of the transistor MTR21 in the previous stage is pulled down to the ground (GND) and applied to the base terminal of the transistor MTR22 in the subsequent stage, so that the transistor MTR22 in the subsequent stage is turned off. As a result, the voltage applied to the collector terminal of the transistor MTR22 in the subsequent stage is pulled up to +12V by the pull-up resistor in the payout control input circuit 4120b of the payout control unit 4120 in the payout control board 4110 via the wiring (harness). The withdrawal power failure notice signal whose logic is HI is input to the withdrawal control board 4110.

Further, as shown in FIG. 25, the main control output circuit 4100cb without a reset function that outputs the signal output from the 1Q terminal which is the output terminal of the D type flip-flop MIC22 to the peripheral control board 4140 as the peripheral power failure notice signal is opened. The circuit is configured as a collector output type, the 1Q terminal which is the output terminal of the D type flip-flop MIC22 is electrically connected to the resistor MR26 of the main control input circuit 4100b described above, and the base terminal of the transistor MTR23 via the resistor MR35. Is electrically connected to. The base terminal of the transistor MTR23 is electrically connected to the resistor MR35, and is also electrically connected to the other end of the resistor MR36 whose one end is grounded to the ground (GND). The emitter terminal of the transistor MTR23 is grounded to the ground (GND), and the collector terminal of the transistor MTR23 is electrically connected to the peripheral control board 4140 via a wiring (harness). When the collector terminal of the transistor MTR23 is electrically connected to the peripheral control board 4140 via a wiring (harness), a peripheral control input circuit (not shown) of the peripheral control unit 4150 in the peripheral control board 4140 shown in FIG. 17, one end is electrically connected to the other end of a pull-up resistor (not shown) electrically connected to the +12V power supply line, and is electrically connected to an input terminal of a predetermined input port of the peripheral control MPU 4150a shown in FIG. Connected.

The circuit composed of the resistors MR35 and MR36 and the transistor MTR23 is a switch circuit which is turned on/off by a signal output from the 1Q terminal which is the output terminal of the D type flip-flop MIC22.

When the logic of the signal output from the 1Q terminal which is the output terminal of the D type flip-flop MIC22 is LOW, the voltage applied to the base terminal of the transistor MTR23 is pulled down to the ground (GND) side and the transistor MTR23 turns off. , The switch circuit is also turned off. On the other hand, when the logic of the signal output from the 1Q terminal which is the output terminal of the D-type flip-flop MIC22 is HI, the voltage applied to the base terminal of the transistor MTR23 is pulled up to +5V and the transistor MTR23 is turned on, The switch circuit is also turned on.

When both the condition that the voltage of +24V is higher than the power failure detection voltage V1pf and the condition that the voltage of +12V is higher than the power failure detection voltage V2pf are satisfied, the signal whose logic becomes HI is preset in the D type flip-flop MIC22. Since the signal is output to the PR terminal, which is the terminal, the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, becomes LOW in logic and is input to the base terminal of the transistor MTR23. Turn off. As a result, the voltage applied to the collector terminal of the transistor MTR23 is pulled up to +12V by the pull-up resistor in the payout control input circuit of the peripheral control unit 4150 in the peripheral control board 4140 via the wiring (harness). The peripheral power failure notice signal that has become is input to the peripheral control board 4140.

On the other hand, when one of the conditions that the voltage of +24V is lower than the power failure detection voltage V1pf and the condition that the voltage of +12V is lower than the power failure detection voltage V2pf is satisfied, the signal whose logic becomes LOW is D. Since it is input to the PR terminal which is the preset terminal of the type flip-flop MIC22, the signal output from the 1Q terminal which is the output terminal of the D type flip-flop MIC22 has its logic level of HI and is input to the base terminal of the transistor MTR23. This turns on the transistor MTR23. Accordingly, the voltage applied to the collector terminal of the transistor MTR23 is pulled down to the ground (GND) side in the peripheral control board 4140 via the wiring (harness), and the peripheral power failure notice signal whose logic becomes LOW is the peripheral control board. 4140 is input.

In this way, the main control input circuit 4100b that transmits the signal output from the 1Q terminal, which is the output terminal of the D type flip-flop MIC22, to the main control MPU 4100a as a power failure notice signal, and the 1Q terminal that is the output terminal of the D type flip-flop MIC22. The main control output circuit 4100cb without a reset function that outputs the signal output from the peripheral control board 4140 as a peripheral power failure warning signal has one transistor each, and the power failure warning signal input to the main control MPU 4100a and the peripheral While the logic of the peripheral power failure notice signal input to the control board 4140 is the same, the signal output from the 1Q terminal which is the output terminal of the D type flip-flop MIC22 is output to the output control board 4110. The main control output circuit 4100cb without a reset function that outputs as a power failure warning signal has two transistors, a front stage and a rear stage, and the logic of the payout power failure warning signal is the logic of the power failure warning signal input to the main control MPU 4100a and the peripherals. The logic of the peripheral power failure advance notice signal input to the control board 4140 is inverted, and is different from the logic of the power failure advance notice signal and the peripheral power failure advance notice signal.

Further, the collector terminal of the transistor MTR20 of the main control input circuit 4100b is electrically connected to the other end of the resistor MR29 whose one end is electrically connected to the +5V power supply line, and is also connected via the non-inverting buffer ICMIC23 to the main control MPU4100a. While it is electrically connected to the input terminal PA1 of the input port PA, the collector terminal of the transistor MTR22 at the rear stage of the main control output circuit 4100cb without the reset function is connected to the payout control board via wiring (harness). In the payout control input circuit 4120b of the payout control unit 4120 in 4110, one end is electrically connected to the other end of the pull-up resistor electrically connected to the +12V power supply line, and the main control output circuit 4100cb without reset function is provided. The collector terminal of the transistor MTR23 is electrically connected to a pull-up resistor whose one end is electrically connected to the +12V power supply line in the payout control input circuit of the peripheral control unit 4150 in the peripheral control board 4140 via a wiring (harness). It is connected to the. This means that between the collector terminal of the transistor MTR20 of the main control input circuit 4100b and the input terminal PA1 of the input port PA of the main control MPU 4100a, the transistor MTR20 of the main control input circuit 4100b and the main control MPU 4100a are connected to each other. Since it is mounted on the 4100, the main control MPU 4100a uses the control reference voltage of +5V to notify the power outage by the logic (ON/OFF signal) of the power outage notification signal, while the main control board 4100 and the payout control board are provided. In order to suppress the influence of noise entering the wiring (harness) that electrically connects the boards, the main control MPU 4100a and the main control MPU 4100a between the board 4100 and the main control board 4100 and the peripheral control board 4140. The power outage notification is performed by the logic (ON/OFF signal) of the power outage notification signal using +12V which is a voltage higher than the control reference voltage +5V of the payout control MPU 4120a and the peripheral control MPU 4150a.

[9-6. Various input/output signals to main control MPU]
Next, various input/output signals to/from the main control MPU 4100a will be described with reference to FIG. The RXA terminal, which is the serial data input terminal of the serial input port of the main control MPU 4100a, receives the serial data from the payout control board 4110 shown in FIG. 14 as a payer serial data reception signal via the main control input circuit 4100b. .. On the other hand, the TXA terminal and the TXB terminal, which are serial data output terminals of the serial output port of the main control MPU 4100a, use the serial data transmitted from the TXA terminal to the payout control board 4110 as a main pay serial data transmission signal and do not have a reset function main control output. The main control output circuit 4100cb which does not have a reset function and transmits the main payment serial data transmission signal to the payout control board 4110, and the serial data which is transmitted to the peripheral control board 4140 shown in FIG. A main serial output signal 4100cb having no reset function is transmitted as a serial serial data transmission signal, and a main serial output signal 4100cb having no reset function is transmitted to the peripheral control board 4140.

The operation signal (RAM clear signal) described above is input to each input terminal of a predetermined input port of the main control MPU 4100a, and, for example, a payout for notifying the normal reception completion of the main payment serial data reception signal described above. The payer ACK signal from the control board 4110 is input via the main control input circuit 4100b, and the detection signals from various switches such as the first starting port switch 3022 shown in FIG. 14 are input via the main control input circuit 4100b. They are input respectively.

On the other hand, from each output terminal of the predetermined output port of the main control MPU 4100a, for example, the main payment ACK signal indicating the normal reception completion of the above-mentioned payment main serial data reception signal is output to the main control output circuit 4100ca with a reset function. Then, the main control output circuit 4100ca with a reset function outputs a main pay ACK signal to the payout control board 4110, or a drive signal to the main control output circuit 4100ca with a reset function for the starting opening solenoid 2105 shown in FIG. To output a drive signal from the main control output circuit 4100ca with a reset function to the starting opening solenoid 2105 via the main control solenoid drive circuit 4100d, and various indicators such as the upper special symbol display 1185 shown in FIG. On the other hand, the main control output circuit 4100ca with a reset function outputs a drive signal to each, and the main control output circuit 4100ca with a reset function outputs a drive signal to each display, or various information (game information) about a game. It outputs to the main control output circuit 4100ca with a reset function, and outputs various information (game information) about a game from the main control output circuit 4100ca with a reset function to the payout control board 4110.

[9-7. Interface circuit for communication between main control board and peripheral control board]
Next, a communication interface circuit between the main control board 4100 and the peripheral control board 4140 will be described with reference to FIG. The main control board 4100 is supplied with +12V from the power supply board 851 shown in FIG. 21 via the payout control board 4110, and the +5V creation circuit 4100g creates +5V which is the control reference voltage of the main control MPU 4100a from this +12V. ing. The main-circulation serial data transmission signal transmitted from the main control board 4100 to the peripheral control board 4140 is affected by noise that enters a wiring (harness) that electrically connects the main control board 4100 and the peripheral control board 4140. In order to suppress the noise, the reliability is improved by transmitting by using +12V which is a voltage higher than the control reference voltage of +5V of the main control MPU 4100a.

Specifically, the main control board 4100 causes the main control output circuit 4100cb without a reset function to function as a communication interface circuit, and the communication interface circuit mainly includes a resistor MR50, resistors MR51 and MR52, and a transistor MTR50. Has been done. On the other hand, in the peripheral control board 4140, a diode AD10, an electrolytic capacitor AC10 (capacitance: 47 μF in this embodiment), a photocoupler AIC10 (infrared LED and photo IC are built in as a communication interface circuit. It is mainly composed of.

+12V supplied from the power supply substrate 851 is applied to the anode terminal of the diode MD50 of the main control board 4100 via the payout control board 4110, and the negative terminal of the diode MD50 is grounded to the ground (GND). The electrolytic capacitor MC50 (in the present embodiment, the capacitance: 220 microfarads (μF)) is electrically connected to the plus terminal. The cathode terminal of the diode MD50 is electrically connected to the positive terminal of the electrolytic capacitor MC50 and electrically connected to the anode terminal (terminal 1) of the photocoupler AIC10 in the peripheral control board 4140 via a wiring (harness). It is connected to the. As a result, when the power from the power supply board 851 is no longer supplied to the main control board 4100 via the payout control board 4110 due to, for example, a power failure or an instantaneous blackout, the electric charge charged in the electrolytic capacitor MC50 is reduced. +12V can be continuously applied from the main control board 4100 to the anode terminal of the photocoupler AIC10 in the peripheral control board 4140.

As described above, the VDD terminal, which is the power supply terminal of the main control MPU 4100a, is charged to the electrolytic capacitor MC2 (electrostatic capacitance: 470 μF in this embodiment) shown in FIG. 24 when a power failure or an instantaneous blackout occurs. Since the electric charge is applied as +5V, the main peripheral serial transmission port 4100ae built in the main control MPU 4100a serially manages at least the command set by the main control CPU core 4100aa in the transmission buffer register 4100aeb. The unit 4100aec can transfer the data to the transmission shift register 41eaa and complete the transmission from the transmission shift register 4100ea as main-circle serial data.

The main circumference serial data transmission signal transmitted from the main control board 4100 to the peripheral control board 4140 is transmitted to the wiring (harness) that electrically connects the main control board 4100 and the peripheral control board 4140 to each other, as described above. In order to suppress the influence of intruding noise, the reliability is enhanced by transmitting by using +12V which is a voltage higher than +5V which is the control reference voltage of the main control MPU 4100a.

Therefore, in the present embodiment, when a power failure or an instantaneous blackout occurs, the electric charge charged in the electrolytic capacitor MC50 is applied as +12 V from the main control board 4100 to the anode terminal of the photocoupler AIC10 in the peripheral control board 4140. Therefore, the main loop serial transmission port 4100ae built in the main control MPU 4100a transfers the command set by the main control CPU core 4100aa to the transmission buffer register 4100aeb to the transmission shift register 41eaa by the serial management unit 4100aec. When the shift register 4100ea transmits the main serial data, the main serial data transmission signal whose logic is HI can be transmitted from the collector terminal of the transistor MTR50 by +12V.

In this embodiment, the storage capacity of the transmission buffer register 4100aeb of the main serial transmission port 4100ae built in the main control MPU 4100a has 32 bytes, and one packet is composed of 3 bytes of data. Therefore, a maximum of 10 packets of data is stored in the transmission buffer register 4100aeb. Further, in the present embodiment, the transfer bit rate of the main circumference serial data transmitted from the main control MPU 4100a is set to 19200 bps.

The cathode terminal (3rd terminal) of the photocoupler AIC10 is electrically connected to the collector terminal of the transistor MTR50 of the main control board 4100 via the resistor AR10 and its wiring (harness). The resistor AR10 in the peripheral control board 4140 is a limiting resistor for limiting the current flowing through the built-in infrared LED of the photocoupler AIC10.

The TXB terminal that outputs the main-circulation serial data transmission signal from the main control MPU 4100a shown in FIG. 24 is electrically connected to the other end of the resistor MR50 whose one end is electrically connected to the +5V power supply line, and is also connected to the resistor MR51. It is electrically connected to the base terminal of the transistor MTR50 via. The base terminal of the transistor MTR50 is electrically connected to the resistor MR51, and is also electrically connected to the other end of the resistor MR52 having one end grounded to the ground (GND). The emitter terminal of the transistor MTR50 is grounded to the ground (GND).

The circuit composed of the resistors MR51 and MR52 and the transistor MTR50 is a switch circuit, and when the logic of the main-cycle serial data transmission signal is HI, the voltage applied to the base terminal of the transistor MTR50 is on the ground (GND) side. As a result, the transistor MTR50 is turned off and the switch circuit is also turned off. As a result, no forward current flows through the built-in infrared LED of the photocoupler AIC10 in the peripheral control board 4140, and the photocoupler AIC10 is turned off. On the other hand, when the logic of the main-cycle serial data transmission signal is LOW, the voltage applied to the base terminal of the transistor MTR50 is pulled up to +5V by the resistor MR50, the transistor MTR50 turns on, and the switch circuit also turns on. .. As a result, a forward current flows through the built-in infrared LED of the photocoupler AIC10 in the peripheral control board 4140, so that the photocoupler AIC10 is turned on.

+5V supplied from the power supply substrate 851 is applied to the anode terminal of the diode AD10 in the peripheral control board 4140 via the frame peripheral relay terminal plate 868, and the cathode terminal of the diode AD10 and the negative terminal are ground (GND). It is electrically connected to the positive terminal of the electrolytic capacitor AC10 which is grounded. The cathode terminal of the diode AD10 is electrically connected to the positive terminal of the electrolytic capacitor AC10, and is also electrically connected to the Vcc terminal (6th terminal) which is the power supply terminal of the photocoupler AIC10. The emitter terminal (4th terminal) of the photocoupler AIC10 is grounded to the ground (GND), and the collector terminal (5th terminal) of the photocoupler AIC10 is a pull-up resistor electrically connected to the positive terminal of the electrolytic capacitor AC10. It is pulled up to the +5 V side by AR11 and electrically connected to the input terminal of the main control board serial I/O port of the peripheral control MPU4150a. When the photocoupler AIC10 is turned on/off, the logic of the signal output from the collector terminal of the photocoupler AIC10 changes, and the signal is used as the main-circulation serial data transmission signal for the main control board serial I/O port of the peripheral control MPU4150a. Input to the input terminal of.

Accordingly, as described above, when +5V supplied from the power supply board 851 is not supplied to the peripheral control board 4140 via the frame peripheral relay terminal board 868 due to, for example, a power failure or an instantaneous blackout, The electric charge charged in the electrolytic capacitor AC10 can be continuously applied as +5 V to the Vcc terminal of the photocoupler AIC10. When +5V is applied from the electrolytic capacitor AC10 when an electric power or an instantaneous blackout occurs, the main-circulation serial data transmission signal transmitted from the TXB terminal of the main control MPU 4100a to the peripheral control board 4140 is transmitted to the main control MPU 4100a. The data set in the transmission buffer register 4100aeb of the built-in main circumference serial transmission port 4100ae can be completed for transmission, and the main circumference serial data transmission signal during transmission, that is, the main circumference serial data is cut off. The peripheral control board 4140 can surely receive the data without any loss.

When the logic of the main circumference serial data transmission signal transmitted from the TXB terminal of the main control MPU 4100a to the peripheral control board 4140 is HI, the voltage applied to the base terminal of the transistor MTR50 is pulled down to the ground (GND) side and Since the photocoupler AIC10 is turned off when the MTR50 is turned off, the voltage applied to the collector terminal of the photocoupler AIC10 is pulled up to +5V by the pull-up resistor AR11 and the logic becomes HI. While the serial data transmission signal is input to the input terminal of the main control board serial I/O port of the peripheral control MPU 4150a, the logic of the main circumference serial data transmission signal transmitted from the TXB terminal of the main control MPU 4100a to the peripheral control board 4140. Is LOW, the voltage applied to the base terminal of the transistor MTR50 is pulled up to +5V by the resistor MR50 and the transistor MTR50 is turned on to turn on the photocoupler AIC10. The voltage applied to the collector terminal is pulled down to the ground (GND) side, and the main circumference serial data transmission signal whose logic becomes LOW is input to the input terminal of the main control board serial I/O port of the peripheral control MPU4150a. .. As described above, the logic of the main circumference serial data transmission signal output from the collector terminal of the photocoupler AIC10 is the same as the logic of the main circumference serial data transmission signal transmitted from the TXB terminal of the main control MPU 4100a to the peripheral control board 4140. Is the logic of.

As described above, in the present embodiment, the +5V power supply line to which the control reference voltage +5V of the main control MPU 4100a is applied and the +12V power supply line to which the communication voltage +12V applied via the diode MD50 are applied. In this case, measures are taken when the control reference voltage and the communication voltage drop due to a power failure or an instantaneous power failure. That is, with respect to the main circumference serial transmission port 4100ae built in the main control MPU 4100a, the +5V power supply line and the positive terminal of the electrolytic capacitor MC2 using the electrolytic capacitor MC2 of the main control filter circuit 4100h as the first auxiliary power supply, Are electrically connected in parallel to each other, the electrolytic capacitor of the main control filter circuit 4100h, which is the first auxiliary power supply, even if a control reference voltage applied from the +5V power supply line drops due to a power failure or an instantaneous blackout. By applying the control reference voltage from the positive terminal of MC2, the state in which the control reference voltage is applied can be maintained, and is composed of the resistor MR50, the resistors MR51 and MR52, and the transistor MTR50. For the main control output circuit 4100cb having no reset function to function as a communication interface circuit, +12V applied to the +12V power supply line is applied as a communication voltage to the anode terminal of the diode MD50 and the cathode terminal of the diode MD50. And a positive terminal of the electrolytic capacitor MC50, which is the second auxiliary power source, are electrically connected in parallel, so that a power failure or a momentary power failure occurs and the voltage is applied from the +12V power source line through the diode MD50 for communication. Even if the voltage drops, the communication voltage is applied from the positive terminal of the electrolytic capacitor MC50, which is the second auxiliary power supply, so that the state in which the communication voltage is applied can be maintained. There is. As a result, it is possible to prevent the command from being interrupted during transmission from the main control board 4100 to the peripheral control board 4140 and to prevent the command from being lost. Therefore, the peripheral control board 4140 reliably receives the command during transmission. can do. Therefore, it is possible to eliminate the missed command immediately after the occurrence of the power failure or at the time of the instantaneous power failure.

In addition, a plurality of commands set in the transmission buffer register 4100aeb of the main-circulation serial transmission port 4100ae built in the main control MPU 4100a are used as main-circulation serial data, and are composed of resistors MR50, MR51, MR52, and a transistor MTR50. 470 μF is set as the electrostatic capacity of the electrolytic capacitor MC2 of the main control filter circuit 4100h so that the transmission to the peripheral control board 4140 can be completed via the main control output circuit 4100cb without the reset function that functions as a communication interface circuit. 220 μF is set as the capacitance of the electrolytic capacitor MC50. As a result, even if a power failure or an instantaneous power failure occurs during transmission from the main control board 4100 to the peripheral control board 4140, a reset that causes all the commands set in the transmission buffer register 4100aeb to function as interface circuits as main-cycle serial data. Since it is possible to complete the transmission to the peripheral control board 4140 via the functionless main control output circuit 4100cb, the peripheral control board 4140 does not cut off a plurality of commands set in the transmission buffer register 4100aeb and also drop them. It can be received without fail.

[10. Circuit of payout control board]
Next, the circuit of the payout control board 4110 shown in FIG. 15 will be described with reference to FIGS. 27 to 32. 27 is a circuit diagram showing a circuit of the payout control unit, FIG. 28 is a circuit diagram showing a payout control input circuit, FIG. 29 is a circuit diagram showing a continuation of FIG. 28, and FIG. 30 is a payout motor drive. 31 is a circuit diagram showing a circuit, FIG. 31 is a circuit diagram showing a CR unit input/output circuit, and FIG. 32 is an input/output diagram showing various input/output signals to/from a main control board and various output signals to an external terminal board. Is. First, the payout control filter circuit will be described, and subsequently, the circuit of the payout control unit, various input/output signals to/from the main control board, and various output signals to the external terminal board will be described.

[10-1. Discharge control filter circuit]
As shown in FIG. 27, the payout control filter circuit 4110a mainly includes a payout control three-terminal filter PIC0. This pay-out control three-terminal filter PIC0 is a T-type filter circuit, and is magnetically shielded with ferrite and has excellent attenuation characteristics. The first terminal of the payout control 3-terminal filter PIC0 is applied with +5V from the power supply board 851 shown in FIG. 21, and is electrically connected to the other end of the capacitor PC0 whose one end is grounded (GND). Therefore, +5V from the power supply board 851 is smoothed by the capacitor PC0 by first removing the ripple (AC component superimposed on the voltage). The 2nd terminal of the payout control 3 terminal filter PIC0 is grounded to the ground (GND), and the 3rd terminal of the payout control 3 terminal filter PIC0 outputs +5V with the noise component removed.

The third terminal of the payout control three-terminal filter PIC0 is connected to the other end of the capacitor PC1 and the electrolytic capacitor PC2 (capacitance: 180 microfarads (μF) in this embodiment) whose one end is grounded to the ground (GND). By being electrically connected to each other, ripples are further removed and smoothed from +5 V output from the third terminal of the payout control three-terminal filter PIC0. The smoothed +5V is applied to a power supply terminal of the payout control system reset PIC1, a VCC terminal which is a power supply terminal of the payout control crystal oscillator PX0, a VDD terminal which is a power supply terminal of the payout control MPU4120a, and the like, which will be described later. .. In addition, in the VDD terminal which is the power supply terminal of the payout control MPU4120a, when the power from the pachinko island facility is cut off due to a power failure or a momentary power failure, the electric charge charged in the electrolytic capacitor PC2 is subject to a power failure or a momentary power failure. It is adapted to be applied as +5 V for a period of about 7 milliseconds (ms) after the generation.

The VDD terminal of the payout control MPU 4120a is electrically connected to the other end of the capacitor PC3 whose one end is grounded (GND), and +5V applied to the VDD terminal is further smoothed by removing the ripple by the capacitor PC3. ing. The VSS terminal which is the ground terminal of the payout control MPU 4120a is grounded to the ground (GND).

The VDD terminal of the payout control MPU 4120a is electrically connected to the capacitor PC3 and also to the anode terminal of the diode PD0. A cathode terminal of the diode PD0 is electrically connected to a VBB terminal which is a power supply terminal of a RAM (dispensing control built-in RAM) built in the payout control MPU 4120a, and one end of which is connected to a ground (GND) to a capacitor PC4. Is electrically connected to the other end of. The VBB terminal of the payout control built-in RAM is electrically connected to the cathode terminal of the diode PD0 and the other end of the capacitor PC4, and is also connected to the plus side of the capacitor BC1 of the power supply substrate 851 shown in FIG. It is electrically connected to the terminal. That is, +5V, which has been smoothed by removing the noise component by the payout control filter circuit 4110a, is applied to the VDD terminal of the payout control MPU 4120a, and via the diode PD0, the VBB terminal of the payout control internal RAM and the capacitor BC1. It is designed to be applied to the positive terminal of and. As a result, as described above, when the +5V generated by the +5V power supply creation circuit 855db of the power supply creation circuit 855d in the power supply board 851 shown in FIG. 21 is not supplied to the payout control board 4110, the capacitor BC1 is charged. Since the discharged electric charge is supplied to the payout control board 4110 as the payout VBB, current does not flow to the VDD terminal of the payout control MPU 4120a due to the diode PD0 and the payout control MPU 4120a does not operate. The stored contents are held by applying the payout VBB to the VBB terminal of the built-in RAM.

[10-2. Circuit of payout controller]
In addition to the payout control MPU 4120a, the payout control input circuit 4120b, the payout control output circuit 4120c, the payout motor drive circuit 4120d, and the CR unit input/output circuit 4120e, the payout control unit 4120 is reset as a peripheral circuit as shown in FIG. A payout control system reset PIC1 that outputs a signal and a payout control crystal oscillator PX0 (8 megahertz (MHz) in this embodiment) that outputs a clock signal are mainly configured. Here, the payout control system reset will be described first, and then the payout control crystal oscillator, the payout control input circuit, the payout motor drive circuit, the CR unit input/output circuit, and various input/output signals to the payout control MPU will be described.

[10-2-1. Discharge control system reset]
As shown in FIG. 27, +5V in which the noise component is removed and smoothed by the payout control filter circuit 4110a is applied to the power supply terminal of the payout control system reset PIC1. The payout control system reset PIC1 resets the payout control MPU 4120a and the payout control output circuit 4120ca with the reset function, and includes a delay circuit. The payout control system reset PIC1 has a delay capacitance terminal electrically connected to the other end of a capacitor PC5 whose one end is grounded (GND), and the delay time of the delay circuit is set by the capacitance of the capacitor PC5. You can do it. Specifically, the payout control system reset PIC1 outputs a system reset signal from the output terminal after a delay time has elapsed when +5V input to the power supply terminal reaches a threshold value (for example, 4.25V).

The output terminal of the payout control system reset PIC1 is electrically connected to the SRT0 terminal which is the reset terminal of the payout control MPU 4120a and the reset terminal of the payout control output circuit 4120ca with the reset function. The output terminal is an open collector output type, one end of which is electrically connected to the other end of the pull-up resistor PR1 electrically connected to the +5V power supply line, and one end of which is grounded to a capacitor (GND). It is electrically connected to the other end of the PC 6. The capacitor PC6 plays a role as a low pass filter. When the voltage input to the power supply terminal is higher than the threshold value, the output terminal is pulled up to +5V by the pull-up resistor PR1 and the logic becomes HI. This logic is the SRT0 terminal of the payout control MPU4120a and the payout control output with the reset function. When the voltage input to the power supply terminal is smaller than the threshold value while being input to the reset terminal of the circuit 4120ca, the logic becomes LOW, and this logic is the SRT0 terminal of the payout control MPU 4120a and the payout control output circuit 4120ca with the reset function. Input to each reset terminal. Since the SRT0 terminal of the payout control MPU 4120a and the reset terminal of the payout control output circuit 4120ca with the reset function are negative logic inputs, when the voltage input to the power supply terminal becomes lower than the threshold value, the payout control MPU 4120a and the reset function The payout control output circuit 4120ca is reset. The power supply terminal is electrically connected to the other end of the capacitor PC7 whose one end is grounded to the ground (GND), and +5V input to the power supply terminal is smoothed by removing ripples. The ground terminal is grounded to the ground (GND), and the NC terminal is not electrically connected to the outside.

[10-2-2. Discharge control crystal oscillator]
As shown in FIG. 27, +5V in which the noise component is removed and smoothed by the payout control filter circuit 4110a is input to the VCC terminal which is the power supply terminal of the payout control crystal oscillator PX0. The VCC terminal is electrically connected to the other end of the capacitor PC8, one end of which is grounded to the ground (GND), and +5V input to the VCC terminal is further smoothed by removing ripples. The smoothed +5V is also applied to the OE terminal which is the output enable (Output Enable) terminal of the payout control crystal oscillator PX0, in addition to the VCC terminal. The payout control crystal oscillator PX0 outputs a clock signal of 8 MHz from an OUT terminal which is an output terminal when +5 V is applied to its OE terminal.

The OUT terminal of the payout control crystal oscillator PX0 is electrically connected to the MCLK terminal that is the clock terminal of the payout control MPU 4120a, and a clock signal of 8 MHz is input to the payout control MPU 4120a. The GND terminal, which is the ground terminal of the payout control crystal oscillator PX0, is grounded to the grant (GND).

[10-2-3. Dispensing control input circuit]
The payout control input circuit 4120b receives a payout power failure notice signal from the door frame opening switch 618, the main body frame opening switch 619 shown in FIG. 15, and the power failure monitoring circuit 4100e provided in the main control board 4100 shown in FIG. The circuit, the handle relay terminal plate 192 shown in FIG. 15, and a circuit to which a detection signal from the full switch 550 is input via the power supply substrate 851, a circuit to which an operation signal from the operation switch 860a is input, and the like. First, the circuit to which the detection signal from the door frame opening switch is input, the circuit to which the detection signal from the main body frame opening switch is input, the circuit to which the payout power failure notice signal from the power failure monitoring circuit is input, A circuit to which the detection signal from the full switch is input and a circuit to which the operation signal from the operation switch is input will be described. It should be noted that various detection switches such as the full switch 550 and the out-of-ball switch 750, the counting switch 751, and the rotation angle switch 752 shown in FIG. 15 have an output terminal of an open collector output type. Since the circuit configuration to which the detection signal of 1 is input is almost the same, a circuit to which the detection signal from the full tank switch is input will be described here.

[10-2-3(a). Circuit to which the detection signal from the door frame opening switch is input]
The door frame opening switch 618 uses a normally closed type (normally closed (NC)). When the door frame 5 is opened from the main body frame 3 as shown in FIG. The switch is turned off (disconnected) in a state in which the body frame 5 is closed. The second terminal of the door frame opening switch 618 is grounded to the ground (GND), while the first terminal of the door frame opening switch 618 has a pull-up resistor PR20 whose one end is electrically connected to the +5V power line. It is electrically connected to the end and also electrically connected to the base terminal of the transistor PTR20 via the resistor PR21. The base terminal of the transistor PTR20 is electrically connected to the resistor PR21, and is also electrically connected to the other end of the resistor PR22 whose one end is grounded to the ground (GND). Further, the first terminal of the door frame opening switch 618 is electrically connected to the pull-up resistor PR20, and is also electrically connected to the other end of the capacitor PC20 whose one end is grounded (GND). .. The emitter terminal of the transistor PTR20 is grounded to the ground (GND), and the collector terminal of the transistor PTR20 is electrically connected to the other end of the resistor PR23 whose one end is electrically connected to the +5V power supply line and also the non-inverting buffer. The payout control is performed via the ICPIC 20 (the non-inverting buffer ICPIC 20 includes eight non-inverting buffer circuits, and the logic of the signal waveform input to one (PIC 20A) is shaped and output without being inverted). It is electrically connected to the input terminal PA0 of the input port PA of the MPU 4120a. When the transistor PTR20 is turned ON/OFF, the logic of the signal output from the collector terminal of the transistor PTR20 changes, and the signal is input to the input terminal PA0 of the input port PA of the payout control MPU4120a as a door opening signal.

Further, the first terminal of the door frame opening switch 618 is pulled up to +5V side by the pull-up resistor PR20 and electrically connected to the base terminal of the transistor PTR20 via the resistor PR21. And is electrically connected to the base terminal of the transistor PTR21 via the resistor PR24. The base terminal of the transistor PTR21 is electrically connected to the resistor PR24, and is also electrically connected to the other end of the resistor PR25 whose one end is grounded to the ground (GND). The emitter terminal of the transistor PTR21 is grounded to the ground (GND), and the collector terminal of the transistor PTR21 is electrically connected to the external terminal board 784 via a wiring (harness). When the collector terminal of the transistor PTR21 is electrically connected to the external terminal board 784 via a wiring (harness), one end of the external terminal board 784 is electrically connected to the +12V power source line, which is not shown. It is electrically connected to the other end of the up resistor. When the transistor PTR21 is turned ON/OFF, the logic of the signal output from the collector terminal of the transistor PTR21 changes, and the signal is input to the external terminal board 784 as an outer end frame door opening information output signal.

Further, the first terminal of the door frame opening switch 618 is pulled up to +5V side by the pull-up resistor PR20 and electrically connected to the base terminal of the transistor PTR20 via the resistor PR21, and is also +5V side by the pull-up resistor PR20. And is electrically connected to the base terminal of the transistor PTR21 via the resistor PR24, and is also pulled up to +5V side by the pull-up resistor PR20 and electrically connected to the base terminal of the transistor PTR22 via the resistor PR26. ing. The base terminal of the transistor PTR22 is electrically connected to the resistor PR26, and is also electrically connected to the other end of the resistor PR27 whose one end is grounded to the ground (GND). The emitter terminal of the transistor PTR22 is grounded to the ground (GND), and the collector terminal of the transistor PTR22 is electrically connected to the main control board 4100 shown in FIG. 14 via a wiring (harness). When the collector terminal of the transistor PTR22 is electrically connected to the main control board 4100 via a wiring (harness), one end of the main control input circuit 4100b of the main control board 4100 shown in FIG. It is electrically connected to the other end of a pull-up resistor (not shown) that is electrically connected to the line. When the transistor PTR22 is turned on/off, the logic of the signal output from the collector terminal of the transistor PTR22 changes, and the signal is input to the main control board 4100 as a main frame door opening signal.

The circuit composed of the pull-up resistor PR20 and the capacitor PC20 is a switch signal generation circuit, and when the door frame 5 is opened from the main body frame 3 or when the door frame 5 is closed by the main body frame 3, The door frame opening switch 618 is configured as a circuit that also has a function of absorbing a change in voltage from the door frame opening switch 618 due to a flapping phenomenon in which ON/OFF is repeated for a short time.

A circuit formed of the resistors PR21 and PR22 and the transistor PTR20, a circuit formed of the resistors PR24 and PR25 and the transistor PTR21, and a circuit formed of the resistors PR26 and PR27 and the transistor PTR22 are door frame opening switches. It is a switch circuit that is turned on/off by a detection signal from 618.

When the door frame 5 is opened from the main body frame 3, the door frame opening switch 618 is ON, so that the voltage applied to the base terminal of the transistor PTR20 is lowered to the ground (GND) side, so that the transistor PTR20 is turned on. It turns off and the switch circuit also turns off. As a result, the voltage applied to the collector terminal of the transistor PTR20 is pulled up to the +5V side by the pull-up resistor PR23, and the door open signal whose logic becomes HI is input to the input terminal PA0 of the input port PA of the payout control MPU4120a. .. Further, when the door frame 5 is opened from the main body frame 3, the door frame opening switch 618 is ON, so that the voltage applied to the base terminal of the transistor PTR21 is pulled down to the ground (GND) side, so that the transistor The PTR 21 turns off and the switch circuit also turns off. As a result, the voltage applied to the collector terminal of the transistor PTR21 is pulled up to +12V by the pull-up resistor of the external terminal board 784 via the wiring (harness) and the logic becomes HI. Is input to the external terminal board 784. Further, when the door frame 5 is opened from the main body frame 3, the door frame opening switch 618 is ON, so that the voltage applied to the base terminal of the transistor PTR22 is pulled down to the ground (GND) side, so that the transistor The PTR 22 turns off and the switch circuit also turns off. As a result, the voltage applied to the collector terminal of the transistor PTR22 is pulled up to +12V by the pull-up resistor of the main control input circuit 4100b of the main control board 4100 via the wiring (harness), and the logic becomes HI. A door open signal is input to the main control board 4100.

On the other hand, when the door frame 5 is closed from the main body frame 3, the door frame opening switch 618 is off, so that the voltage applied to the base terminal of the transistor PTR20 is pulled up to +5V by the pull-up resistor PR20. Then, the transistor PTR20 is turned on and the switch circuit is also turned on. As a result, the door opening signal in which the voltage applied to the collector terminal of the transistor PTR20 is pulled down to the ground (GND) side and the logic becomes LOW is input to the input terminal PA0 of the input port PA of the payout control MPU4120a. Further, when the door frame 5 is closed from the main body frame 3, the door frame opening switch 618 is OFF, so that the voltage applied to the base terminal of the transistor PTR21 is pulled up to +5V, so that the transistor PTR21 is turned ON. However, the switch circuit is also turned on. As a result, the voltage applied to the collector terminal of the transistor PTR21 is lowered to the ground (GND) side, and the outer end frame door opening information output signal whose logic becomes LOW is input to the external terminal board 784. Further, when the door frame 5 is closed from the main body frame 3, the door frame opening switch 618 is OFF, so that the voltage applied to the base terminal of the transistor PTR22 is pulled up to +5V, so that the transistor PTR22 is turned ON. However, the switch circuit is also turned on. As a result, the main frame door opening signal in which the voltage applied to the collector terminal of the transistor PTR22 is lowered to the ground (GND) side and the logic becomes LOW is input to the main control board 4100.

As described above, when the door frame 5 is opened from the main body frame 3, the door frame opening switch 618 is turned on, and the door opening signal whose logic becomes HI causes the input terminal PA0 of the input port PA of the payout control MPU 4120a. Is input to the external terminal board 784 and the main frame door open signal whose logic is HI is input to the main control board 4100. When the frame 5 is closed to the main body frame 3, the door frame opening switch 618 is turned off, so that the door opening signal whose logic becomes LOW is input to the input terminal PA0 of the input port PA of the payout control MPU 4120a, and the logic Is output to the external terminal board 784, and the main frame door open signal whose logic is LOW is input to the main control board 4100.

[10-2-3(b). Circuit to which the detection signal from the main frame opening switch is input]
The body frame opening switch 619 uses a normally closed type (normally closed (NC)). When the body frame 3 is opened from the outer frame 2 shown in FIG. The switch is adapted to be turned off (disconnected) while the outer frame 3 is closed. The second terminal of the body frame opening switch 619 is grounded to the ground (GND), while the first terminal of the body frame opening switch 619 has a pull-up resistor PR28 whose one end is electrically connected to the +5V power line. It is electrically connected to the end and also electrically connected to the base terminal of the transistor PTR23 via the resistor PR29. The base terminal of the transistor PTR23 is electrically connected to the resistor PR29, and is also electrically connected to the other end of the resistor PR30 whose one end is grounded to the ground (GND). The first terminal of the body frame opening switch 619 is electrically connected to the pull-up resistor PR28, and is also electrically connected to the other end of the capacitor PC21 whose one end is grounded (GND). .. The emitter terminal of the transistor PTR23 is grounded to the ground (GND), the collector terminal of the transistor PTR23 is electrically connected to the collector terminal of the transistor PTR21 described above, and is also connected to the external terminal board 784 via a wiring (harness). It is electrically connected. When the collector terminal of the transistor PTR23 is electrically connected to the external terminal board 784 through a wiring (harness), one end of the external terminal board 784 is electrically connected to the +12V power source line, which is not shown. It is electrically connected to the other end of the up resistor. When the transistor PTR23 is turned ON/OFF, the logic of the signal output from the collector terminal of the transistor PTR23 changes, and the signal is input to the external terminal board 784 as an outer end frame door opening information output signal.

Further, the first terminal of the body frame opening switch 619 is pulled up to +5V side by the pull-up resistor PR28 and electrically connected to the base terminal of the transistor PTR23 via the resistor PR29. And is electrically connected to the base terminal of the transistor PTR24 via the resistor PR31. The base terminal of the transistor PTR24 is electrically connected to the resistor PR31 and is also electrically connected to the other end of the resistor PR32 whose one end is grounded to the ground (GND). The emitter terminal of the transistor PTR24 is grounded to the ground (GND), the collector terminal of the transistor PTR24 is electrically connected to the collector terminal of the transistor PTR22 described above, and is shown in FIG. 14 via a wiring (harness). It is electrically connected to the main control board 4100. When the collector terminal of the transistor PTR24 is electrically connected to the main control board 4100 via a wiring (harness), one end of the main control input circuit 4100b of the main control board 4100 shown in FIG. It is electrically connected to the other end of a pull-up resistor (not shown) that is electrically connected to the line. When the transistor PTR24 is turned ON/OFF, the logic of the signal output from the collector terminal of the transistor PTR24 changes, and the signal is input to the main control board 4100 as a main frame door opening signal.

The circuit composed of the pull-up resistor PR28 and the capacitor PC21 is a switch signal generation circuit, and when the body frame 3 is opened from the outer frame 2 or when the body frame 3 is closed by the outer frame 2. It is configured as a circuit that also has a function of absorbing a variation in the voltage from the main body frame opening switch 619 due to a flapping phenomenon in which contacts constituting the main body frame opening switch 619 repeat ON/OFF for a short time.

A circuit composed of the resistors PR29 and PR30 and the transistor PTR23 and a circuit composed of the resistors PR31 and PR32 and the transistor PTR24 are switch circuits which are turned on/off by a detection signal from the main frame opening switch 619.

When the body frame 3 is opened from the outer frame 2, the body frame opening switch 619 is turned on, so that the voltage applied to the base terminal of the transistor PTR23 is pulled down to the ground (GND) side, so that the transistor PTR23 is opened. It turns off and the switch circuit also turns off. As a result, the voltage applied to the collector terminal of the transistor PTR23 is pulled up to +12V by the pull-up resistor of the external terminal board 784 via the wiring (harness) and the logic becomes HI. Is input to the external terminal board 784. Further, when the body frame 3 is opened from the outer frame 2, the body frame opening switch 619 is turned on, so that the voltage applied to the base terminal of the transistor PTR24 is pulled down to the ground (GND) side, so that the transistor The PTR 24 turns off and the switch circuit also turns off. Thus, the voltage applied to the collector terminal of the transistor PTR24 is pulled up to +12V by the pull-up resistor of the main control input circuit 4100b of the main control board 4100 via the wiring (harness), and the logic becomes HI. A door open signal is input to the main control board 4100.

On the other hand, when the body frame 3 is closed by the outer frame 2, the body frame opening switch 619 is off, and therefore the voltage applied to the base terminal of the transistor PTR23 is pulled up to +5V by the pull-up resistor PR28. Then, the transistor PTR23 is turned on and the switch circuit is also turned on. As a result, the voltage applied to the collector terminal of the transistor PTR23 is pulled down to the ground (GND) side in the external terminal board 784 via the wiring (harness), and the outer end frame door opening information output signal whose logic becomes LOW is output. It is input to the external terminal board 784. Further, when the body frame 3 is closed by the outer frame 2, the body frame opening switch 619 is off, so that the voltage applied to the base terminal of the transistor PTR24 can be pulled up to +5V by the pull-up resistor PR28. Then, the transistor PTR24 is turned on and the switch circuit is also turned on. As a result, the voltage applied to the collector terminal of the transistor PTR24 is pulled down to the ground (GND) side in the main control board 4100 via the wiring (harness), and the main frame door opening signal whose logic becomes LOW is the main control board. 4100 is input.

As described above, when the main body frame 3 is released from the outer frame 2, the main frame opening switch 619 is turned on, and the outer end frame door open information output signal whose logic becomes HI is input to the external terminal board 784. The main frame door opening signal whose logic is HI is input to the main control board 4100, while the main frame opening switch 619 is turned off when the main frame 3 is closed by the outer frame 2, Is output to the external terminal board 784, and the main frame door open signal whose logic is LOW is input to the main control board 4100.

In the present embodiment, as described above, one or both of the state in which the door frame 5 is closed by the main body frame 3 and the state in which the main body frame 3 is opened from the outer frame 2 are either one or both. In this case, since the main frame door open signal is input to the main control board 4100, the main control MPU 4100a of the main control board 4100 shown in FIG. It is impossible to determine whether the door frame 5 is open from the main body frame 3 or the main body frame 3 is open from the outer frame 2 based on the above, but the door frame 5 and/or The player can determine that the main frame 3 is open, which is a condition that does not occur during normal play, and the outer end frame door open information output signal is sent to the external terminal board 784. Since the outer end frame door opening information output signal is transmitted to the hall computer via the external terminal board 784, the hall computer, based on the outer end frame door opening information output signal, receives the door frame. Although it is not possible to determine whether the frame 5 is opened from the main frame 3 or the main frame 3 is opened from the outer frame 2, the door frame 5 and/or the main frame 3 are opened. It is possible for the player to judge that a state that does not occur during the normal game has occurred.

Further, in the present embodiment, as described above, the door frame opening switch 618 and the main body frame opening switch 619 are normally closed switches, so that the door frame opening switch 618 is short-circuited and the switch is turned ON ( Even if the door frame 5 is opened from the main body frame 3 even when the main frame opening switch 619 is short-circuited and the switch is turned on (conducts) for some reason, the main frame 3 is released from the outer frame 2. Thus, by adopting the normally closed switches for the door frame opening switch 618 and the main body frame opening switch 619, the main frame door opening signal can be output to the main control board 4100 even at the time of a short circuit, and the outer end The frame door opening information output signal can be transmitted to the hall computer via the external terminal board 784.

If the door frame opening switch 618 and the main body frame opening switch 619 are changed from a normally closed switch to a normally open (normally open (NO)) switch (door frame opening switch 618′ and main body frame opening switch 619′). The door frame opening switch 618′ is turned on (conducts) when the door frame 5 is closed from the main body frame 3, and is turned off (disconnected) when the door frame 5 is opened to the main body frame 3. .. The body frame opening switch 619' is turned on (conducts) when the body frame 3 is closed from the outer frame 2, and is turned off (disconnected) when the body frame 3 is opened to the outer frame 2. Then, even if the door frame opening switch 618′ is disconnected for some reason and the switch is turned off (disconnected), the door frame 5 remains open from the main body frame 3, and for some reason, the main body is opened. Even when the frame opening switch 619′ is disconnected and the switch is turned off (disconnected), the main body frame 3 is opened from the outer frame 2. Thus, even if the door frame opening switch 618' and the main body frame opening switch 619' are normally open switches, the main frame door opening signal can be output to the main control board 4100 even when the wire is broken. The outer edge frame door opening information output signal can be transmitted to the hall computer via the external terminal board 784.

[10-2-3(c). Circuit to which the power failure notice signal from the power failure monitoring circuit is input]
The transmission line for transmitting the payout power failure notice signal from the power failure monitoring circuit 4100e provided in the main control board 4100 is electrically connected to the other end of the pull-up resistor PR40 whose one end is electrically connected to the +12V power supply line and also has resistance. It is electrically connected to the base terminal of the transistor PTR40 via PR41. The base terminal of the transistor PTR40 is electrically connected to the resistor PR41, and is also electrically connected to the other end of the resistor PR42 whose one end is grounded to the ground (GND). The emitter terminal of the transistor PTR40 is grounded to the ground (GND), and the collector terminal of the transistor PTR40 is electrically connected to the other end of the resistor PR43 whose one end is electrically connected to the +5V power supply line and also the non-inverting buffer. The payout control is performed via the ICPIC 40 (the non-inverting buffer ICPIC 40 includes eight non-inverting buffer circuits, and the logic of the signal waveform input to one of them (PIC 40A) is shaped and output without being inverted). It is electrically connected to the input terminal PA1 of the input port PA of the MPU 4120a. When the transistor PTR40 is turned on/off, the logic of the signal output from the collector terminal of the transistor PTR40 changes, and the signal is input to the input terminal PA1 of the input port PA of the payout control MPU4120a as a payout power failure notice signal.

The circuit including the resistors PR41 and PR42 and the transistor PTR40 is a switch circuit that is turned on/off by a power failure monitoring circuit 4100e provided in the main control board 4100 and a power failure notice signal.

As described above, the power failure monitoring circuit 4100e monitors the signs of power failure or momentary power failure of two types of voltage of +12V and +24V from the power supply board 851, and when detecting the power failure or momentary power failure, there is no reset function. A payout power failure notice signal is output to the payout control board 4110 as a power failure notice via the main control output circuit 4100cb. The power failure monitoring circuit 4100e monitors the signs of power failure or momentary power failure of the voltages of +12V and +24V, and as described above, the condition that the voltage of +24V is higher than the power failure detection voltage V1pf, and the voltage of +12V is higher than the power failure detection voltage V2pf. When both conditions of being large are satisfied, the voltage applied to the collector terminal of the transistor MTR22 in the subsequent stage is pulled down to the ground (GND) side in the payout control board 4110 via the wiring (harness) and the logic becomes LOW. While the payout power failure notice signal is input to the payout control board 4110, one of the condition that the voltage of +24V is lower than the power failure detection voltage V1pf and the condition that the voltage of +12V is lower than the power failure detection voltage V2pf. When the condition is satisfied, the voltage applied to the collector terminal of the transistor MTR22 in the subsequent stage is pulled up to +12V by the pull-up resistor PR40 through the wiring (harness), and the logic becomes HI. Is input to the payout control board 4110.

When both the condition that the voltage of +24V is higher than the power failure detection voltage V1pf and the condition that the voltage of +12V is higher than the power failure detection voltage V2pf are satisfied, that is, there is no sign of power failure or momentary power failure of the voltage of +12V and +24V. At this time, since the withdrawal power failure notice signal whose logic is LOW is input to the withdrawal control board 4110, the voltage applied to the base terminal of the transistor PTR40 is lowered to the ground (GND) side, and the transistor PTR40 is turned off. The voltage applied to the collector terminal of the transistor PTR40 is pulled up to the +5V side by the resistor PR43. As a result, the payout power failure notice signal whose logic becomes HI is input from the collector terminal of the transistor PTR40 to the input terminal PA1 of the input port PA of the payout control MPU 4120a.

On the other hand, when one of the conditions that the voltage of +24V is lower than the power failure detection voltage V1pf and the condition that the voltage of +12V is lower than the power failure detection voltage V2pf is satisfied, that is, the voltage of +12V and/or +24V When there is a sign of power failure or momentary power failure, the withdrawal power failure notice signal whose logic becomes HI is input to the withdrawal control board 4110, and therefore is applied to the base terminal of the transistor PTR40 by the withdrawal power failure notice signal from the power failure monitoring circuit 4100e. The voltage applied to the transistor PTR40 is turned on by pulling up the voltage to the +12V side by the pull-up resistor PR40, and the voltage applied to the collector terminal of the transistor PTR40 is lowered to the ground (GND) side. As a result, the payout power failure notice signal in which the logic of the collector terminal of the transistor PTR40 is LOW is input to the input terminal PA1 of the input port PA of the payout control MPU 4120a.

Thus, when there is a sign of a power failure or an instantaneous power failure of the voltage of +12V and/or +24V, the withdrawal power failure notice signal whose logic is HI is input to the input terminal PA1 of the input port PA of the withdrawal control MPU4120a, When there is no sign of a power failure or a momentary power failure of +12V and +24V, the payout power failure notice signal whose logic is LOW is input to the input terminal PA1 of the input port PA of the payout control MPU 4120a. As described above, when there is a sign of a power failure or a momentary power failure of the voltage of +12V and/or +24V, the power failure notice signal whose logic becomes HI is input to the input terminal PA1 of the input port PA of the main control MPU4100a. On the other hand, when there is no sign of a power failure or a momentary power failure of +12V and +24V, the power failure notice signal is input to the input terminal PA1 of the input port PA of the main control MPU 4100a. The logic of the payout power failure notification signal input to the payout control MPU 4120a and the logic of the power failure notification signal input to the main control MPU 4100a according to the power failure notification are the same logic.

[10-2-3(d). Circuit to which detection signal from full tank switch is input]
The detection signal from the full tank switch 550 provided in the foul cover unit 540 shown in FIG. 1 is sent to the payout control board 4110 via the handle relay terminal plate 192 shown in FIG. 1 and the power supply board 851 shown in FIG. It has been entered. The output terminal of the full tank switch 550 is configured as an open collector output type in which the emitter terminal is grounded to the ground (GND), and one end of the payout control board 4110 is electrically connected to the +12V power supply line. It is electrically connected to the other end of the pull-up resistor PR44a and is also electrically connected to the first terminal of the full-tank switch three-terminal filter PIC50. The three-terminal filter PIC50 for a full-tank switch is a T-type filter circuit, which is magnetically shielded with ferrite and has excellent attenuation characteristics.

The 2nd terminal of the 3-terminal filter PIC50 for full tank switch is grounded to the ground (GND), and the 3rd terminal of the 3-terminal filter PIC50 for full tank switch is connected to the 3-terminal filter PIC50 for full tank switch via the resistor PR44b. Of the transistor PTR41 and is electrically connected to the base terminal of the transistor PTR41 via the resistor PR45. As a result, the detection signal of the full tank switch 550 is input to the base terminal of the transistor PTR41 after the noise component is removed by the full terminal switch three-terminal filter PIC50. The base terminal of the transistor PTR41 is electrically connected to the resistor PR45, is electrically connected to the other end of the resistor PR46 whose one end is grounded to the ground (GND), and is connected to the ground (GND) at one end. It is electrically connected to the other end of the capacitor PC40 which is electrically connected. The capacitor PC40 plays a role as a low-pass filter. The emitter terminal of the transistor PTR41 is grounded to the ground (GND), and the collector terminal of the transistor PTR41 is electrically connected to the other end of the resistor PR47 whose one end is electrically connected to the +5V power supply line and also the non-inverting buffer. The payout control is performed via the ICPIC 40 (the non-inverting buffer ICPIC 40 includes eight non-inverting buffer circuits, and the logic of the signal waveform input to one of them (PIC 40B) is shaped and output without being inverted). It is electrically connected to the input terminal PA2 of the input port PA of the MPU 4120a. When the transistor PTR41 is turned on/off, the logic of the signal output from the collector terminal of the transistor PTR41 changes, and the signal is input to the input terminal PA2 of the input port PA of the payout control MPU4120a as a full signal.

The circuit composed of the resistors PR45 and PR46 and the transistor PTR41 is a switch circuit which is turned on/off by a detection signal from the full tank switch 550.

As described above, the full tank switch 550 is for detecting whether or not the game ball in which the accommodation space in the second ball passage of the foul cover unit 540 is stored is full. In the present embodiment, when the game ball in which the accommodation space is stored is not full, the voltage applied to the output terminal of the full tank switch 550 is paid out through the handle relay terminal plate 192 and the power supply board 851. In the control board 4110, when the pull-up resistor 44a pulls the signal to the +12V side and the logic becomes HI, the signal is input to the payout control board 4110, and when the accommodation space is full of game balls, The voltage applied to the output terminal of the full tank switch 550 is pulled down to the ground (GND) side in the payout control board 4110 via the handle relay terminal board 192 and the power supply board 851, and the signal whose logic becomes LOW is paid out. It is input to the control board 4110.

When the accommodation space is not full with the stored game balls, the voltage applied to the output terminal of the full tank switch 550 is pulled in the payout control board 4110 via the handle relay terminal board 192 and the power board 851. The signal that is pulled up to +12V by the up resistor 44a and has the logic of HI is input to the base terminal of the transistor PTR41 described above, so that the transistor PTR41 is turned on and the switch circuit is also turned on. As a result, the voltage applied to the collector terminal of the transistor PTR41 is lowered to the ground (GND) side and the full signal whose logic becomes LOW is input to the input terminal PA2 of the input port PA of the payout control MPU4120a.

On the other hand, when the game space in which the accommodation space is stored is full, the voltage applied to the output terminal of the full tank switch 550 is passed through the handle relay terminal plate 192 and the power supply board 851, and the payout control board 4110. In this case, the signal that is pulled down to the ground (GND) side and the logic becomes LOW is input to the base terminal of the transistor PTR41 described above, so that the transistor PTR41 is turned off and the switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor PTR41 is pulled up to the +5 V side by the resistor PR47 and the full signal whose logic becomes HI is input to the input terminal PA2 of the input port PA of the payout control MPU4120a.

In the present embodiment, the detection signal from the full tank switch 550 is input to the switch circuit including the resistors PR45, PR46, and the transistor PTR41 via the full terminal switch three-terminal filter PIC50. However, the detection signals from the various detection switches such as the ball break switch 750, the counting switch 751, and the rotation angle switch 752 shown in FIG. 15 are T-type filter circuits such as the three-terminal filter PIC50 for full tank switch. The circuit configuration is such that it is directly input to each switch circuit without going through. Since the full tank switch 550 is provided in the foul cover unit 540 attached to the door frame 5, the out-of-ball switch 750, the counting switch 751, and the rotation angle switch 752 provided in the prize ball device 740 attached to the main body frame 3. Compared with the above, the path for transmitting the detection signal becomes extremely long, and it is very susceptible to noise.

The full tank switch 550 is for detecting whether or not the accommodation space in the second ball passage of the foul cover unit 540 is full of game balls stored, and the payout control MPU 4120a detects from the full tank switch 550. When it is determined that the accommodation space is full with the stored game balls based on the detection signal of, the driving control of the payout motor 744 is forcibly stopped to control the payout rotating body to stop the payout of the game balls. I am supposed to do it. That is, when noise enters the transmission path (transmission line) that transmits the detection signal from the full tank switch 550, the payout control MPU 4120a drives the payout motor 744 even though the game ball in which the accommodation space is stored is not full. In some cases, control is forcibly stopped to stop the payout of the game ball by the payout rotating body, and the payout motor 744 is driven and controlled even if the game space in which the accommodation space is stored is full. Then, when the payout rotating body is rotated and the payout of the game balls is continued to fill the upstream side of the prize ball passage with the game balls, the payout rotating body itself cannot rotate and the payout motor 744 is set. The load may be abnormally applied, and the payout motor 744 may be overloaded and abnormally generate heat to cause a failure, or a mechanism or the like that transmits the rotary shaft of the payout motor 744 to the rotational movement of the payout rotor may fail. .. Therefore, in the present embodiment, in order to prevent such a problem, the circuit configuration is adopted so that the detection signal from the full tank switch 550 is first removed by the noise component in the full terminal switch three-terminal filter PIC50. ..

[10-2-3(e). Circuit to which operation signal from operation switch is input]
The output terminals 1 and 2 of the operation switch 860a are grounded to the ground (GND), and the output terminals 3 and 4 of the operation switch 860a are connected to the +5V side by the pull-up resistor PR48. It is pulled up and electrically connected to the base terminal of the transistor PTR42 at the preceding stage through the resistor PR49. The base terminal of the transistor PTR42 at the preceding stage is electrically connected to the resistor PR49, and is also electrically connected to the other end of the resistor PR50 whose one end is grounded to the ground (GND). The fourth terminal, which is the output terminal of the operation switch 860a, is electrically connected to the pull-up resistor PR48, and also electrically connected to the other end of the capacitor PC41 whose one end is grounded (GND). ing. The emitter terminal of the transistor PTR42 in the preceding stage is grounded to the ground (GND), and the collector terminal of the transistor PTR42 in the preceding stage is electrically connected to the other end of the resistor PR51 whose one end is electrically connected to the +5V power supply line. At the same time, it is electrically connected to the base terminal of the transistor PTR43 in the subsequent stage through the resistor PR52. The base terminal of the latter-stage transistor PTR43 is electrically connected to the resistor PR52, and is also electrically connected to the other end of the resistor PR53 whose one end is grounded to the ground (GND). The emitter terminal of the rear-stage transistor PTR43 is grounded to the ground (GND), and the collector terminal of the rear-stage transistor PTR43 is electrically connected to the other end of the resistor PR54 whose one end is electrically connected to the +5V power supply line. At the same time, the non-inverting buffer ICPIC40 (the non-inverting buffer ICPIC40 is provided with eight non-inverting buffer circuits, shapes and outputs the logic of the signal waveform input to one of them (PIC40C) without inverting it). It is electrically connected to the input terminal PA3 of the input port PA of the payout control MPU4120a via. The logic of the signal output from the collector terminal of the transistor PTR43 in the subsequent stage is changed by turning ON/OFF the transistors PTR42 and PTR43 in the previous stage and the signal is changed as the RWMCLR signal to the input terminal PA3 of the input port PA of the payout control MPU4120a. To be entered.

Further, the output terminals of the operation switch 860a, that is, the third terminal and the fourth terminal, are pulled up to the +5V side by the pull-up resistor PR48 and electrically connected to the base terminal of the transistor PTR42 of the preceding stage via the resistor PR49. It is pulled up to the +5V side by the pull-up resistor PR48 and electrically connected to the base terminal of the transistor PTR44 via the resistor PR55. The base terminal of the transistor PTR44 is electrically connected to the resistor PR55, and is also electrically connected to the other end of the resistor PR56 whose one end is grounded to the ground (GND). The emitter terminal of the transistor PTR44 is grounded to the ground (GND), and the collector terminal of the transistor PTR44 is electrically connected to the main control board 4100 via a wiring (harness). When the collector terminal of the transistor PTR44 is electrically connected to the main control board 4100 via a wiring (harness), one end of the main control input circuit 4100b of the main control board 4100 shown in FIG. 24 is +12V. It is electrically connected to the other end of the pull-up resistor MR2 electrically connected to the power supply line. When the transistor PTR44 is turned on/off, the logic of the signal output from the collector terminal of the transistor PTR44 changes, and the signal is input to the input terminal PA0 of the input port PA of the main control MPU4100a as a RAM clear signal.

The circuit composed of the pull-up resistor PR48 and the capacitor PC41 is a switch signal generation circuit, and when the operation switch 860a is pressed, the contact that constitutes the operation switch 860a repeats ON/OFF for a short period of time. It is configured as a circuit that also has a function of absorbing fluctuations in the voltage from the operation switch 860a.

A circuit including the resistors PR49 and PR50 and the transistor PTR42 is a switch circuit in the preceding stage, and a circuit including the resistors PR52 and PR53 and the transistor PTR43 is a switch circuit in the subsequent stage, and the resistors PR55 and PR56 and the transistor PTR44. Is a switch circuit, which is turned on/off by an operation signal from the operation switch 860a.

As described above, the operation switch 860a is provided in the RAM (RAM with built-in payout control) incorporated in the payout control MPU 4120a of the payout control board 4110 and the main control MPU 4100a of the main control board 4100 within a predetermined period after the power is turned on. It is designed to be operated when clearing the built-in RAM (main control built-in RAM), and when an error is reported after the power is turned on, it is operated to clear the error. The function to clear the RAM within a predetermined period from the time and the error release after the power is turned on (after the period for performing the function as the RAM clear has passed, that is, after the predetermined period has passed since the power was turned on) And has the function. The operation signal from the operation switch 860a becomes a RAM clear signal in the function of performing the RAM clear within a predetermined period after the power is turned on, while it is after the power is turned on (after a predetermined period has elapsed since the power was turned on). In the function for canceling the error in ), it becomes an error canceling signal.

When the operation switch 860a is not operated, the output terminals of the operation switch 860a, that is, the third terminal and the fourth terminal, are pulled up to the +5V side by the pull-up resistor PR48, and the operation signal whose logic becomes HI is the transistor of the previous stage. It is input to the base terminal of the PTR42, the front-stage transistor PTR42 is turned on, and the front-stage switch circuit is also turned on, which is the voltage applied to the base of the rear-stage transistor PTR43, which is applied to the collector terminal of the front-stage transistor PTR43. By lowering the voltage to the ground (GND) side, the transistor PTR43 in the subsequent stage is turned off, and the switch circuit in the subsequent stage is also turned off. As a result, the voltage applied to the collector terminal of the transistor PTR43 in the subsequent stage is pulled up to the +5 V side by the resistor PR54, and the RWMCLR signal whose logic becomes HI is input to the input terminal PA3 of the input port PA of the payout control MPU4120a. The payout control MPU 4120a performs a RAM clear for erasing the information stored in the payout control internal RAM when the logic of the RWMCLR signal input to the input terminal PA3 is HI within a predetermined period after the power is turned on. It is determined that the instruction is not given, and after the power is turned on (after a predetermined period has elapsed since the power was turned on), when the logic of the RWMCLR signal input to the input terminal PA3 is HI, error cancellation is performed. Judge that it is not an instruction.

When the operation switch 860a is not operated, the output signal of the operation switch 860a, that is, the output terminals No. 3 and No. 4 are pulled up to the +5V side by the pull-up resistor PR48, and the operation signal whose logic becomes HI is the transistor PTR44. Is input to the base terminal of the transistor PTR44, and the transistor PTR44 is turned on, and the switch circuit is also turned on. As a result, the voltage applied to the collector terminal of the transistor PTR44 is pulled down to the ground (GND) side in the main control board 4100 via the wiring (harness), and the RAM clear signal whose logic becomes LOW is sent to the main control board 4100. Is entered. The main control MPU 4100a of the main control board 4100, when the RAM clear signal whose logic is LOW is input within a predetermined period after the power is turned on, as described above, this logic is LOW. When the RAM clear signal is input to the base terminal of the transistor MTR0, the transistor MTR0 turns off and the switch circuit also turns off. As a result, the RAM clear signal in which the voltage applied to the collector terminal of the transistor MTR0 is pulled up to +5 V by the resistor MR5 and the logic becomes HI is input to the input terminal PA0 of the input port PA of the main control MPU4100a. When the logic of the RAM clear signal input to the input terminal PA0 is HI, the main control MPU 4100a determines that it does not instruct to perform the RAM clear to erase the information stored in the main control built-in RAM.

On the other hand, when the operation switch 860a is operated, the operation signal whose logic becomes LOW by pulling down the output terminal 3 and 4 of the operation switch 860a to the ground (GND) side is the transistor of the previous stage. It is input to the base terminal of the PTR42, the transistor PTR42 of the previous stage is turned off, and the switch circuit of the previous stage is also turned off. The voltage that rises to the +5V side by the resistor PR51 turns on the transistor PTR43 in the subsequent stage and turns on the switch circuit in the subsequent stage. As a result, the voltage applied to the collector terminal of the transistor PTR43 in the subsequent stage is lowered to the ground (GND) side, and the RWMCLR signal whose logic becomes LOW is input to the input terminal PA3 of the input port PA of the payout control MPU4120a. The payout control MPU 4120a performs a RAM clear that erases information stored in the payout control internal RAM when the logic of the RWMCLR signal input to the input terminal PA3 is LOW within a predetermined period after the power is turned on. It is determined that the instruction is given, and after the power is turned on (after a predetermined period has elapsed since the power was turned on), when the logic of the RWMCLR signal input to the input terminal PA3 is LOW, error cancellation is performed. Judge that it is an instruction.

Further, when the operation switch 860a is operated, the output terminals of the operation switch 860a, that is, the third terminal and the fourth terminal are pulled down to the ground (GND) side by the pull-up resistor PR48, so that the logic becomes LOW. A signal is input to the base terminal of the transistor PTR44, the transistor PTR44 turns off, and the switch circuit also turns off. As a result, the voltage applied to the collector terminal of the transistor PTR44 is pulled up to +12V by the pull-up resistor MR2 of the main control input circuit 4100b of the main control board 4100 via the wiring (harness), and the logic becomes HI. The clear signal is input to the main control board 4100. The main control MPU 4100a of the main control substrate 4100 receives the RAM clear signal whose logic is HI within a predetermined period after the power is turned on, and as described above, this logic shown in FIG. When the RAM clear signal is input to the base terminal of the transistor MTR0, the transistor MTR0 turns on and the switch circuit also turns on. As a result, the RAM clear signal in which the voltage applied to the collector terminal of the transistor MTR0 is pulled down to the ground (GND) side and the logic becomes LOW is input to the input terminal PA0 of the input port PA of the main control MPU4100a. When the logic of the RAM clear signal input to the input terminal PA0 is LOW, the main control MPU 4100a determines that the instruction is to perform the RAM clear for erasing the information stored in the main control built-in RAM.

[10-2-4. Discharge motor drive circuit]
Next, a payout motor drive circuit 4120d for outputting a drive signal to the payout motor 744 of the prize ball device 740 shown in FIG. 5 will be described. As shown in FIG. 30, the payout motor drive circuit 4120d mainly includes a voltage switching circuit 4120da and a drive ICPIC 60. The power supply input terminals 1 and 2 of the voltage switching circuit 4120da are electrically connected to the +12V power supply line and the +5V power supply line, respectively, and +12V and +5V are applied, respectively, and the ground terminal of the voltage switching circuit 4120da is grounded (GND). It is grounded. A voltage switching signal is input to the power supply switching input terminal of the voltage switching circuit 4120da. This voltage switching signal is output from the output terminal of the predetermined output port of the payout control MPU 4120a to the payout control output circuit 4120ca with reset function, and is output from the payout control output circuit 4120ca with reset function to the power supply switching input terminal of the voltage switch circuit 4120da. It is supposed to be done. The power supply output terminal of the voltage switching circuit 4120da is electrically connected to the cathode terminal 3 and terminal 10 of the drive IC PIC60 via the Zener diode PZD60, and is electrically connected to the power supply terminal of the payout motor 744. No. 3 which is the cathode terminal of the drive IC PIC60 via the Zener diode PZD60 with +12V or +5V as the motor drive voltage based on the voltage switching signal input to the voltage switching input terminal of the voltage switching circuit 4120da. It supplies to the terminal and the 10th terminal, respectively, and supplies to the payout motor 744.

The drive ICPIC 60 includes four Darlington power transistors. In this embodiment, the 6th and 7th terminals, which are the emitter terminals of the drive ICPIC 60, are grounded to the ground (GND), respectively, and are the base terminals of the drive ICPIC 60. The payout motor drive signal is input to the certain terminals 1, 5, 8, and 12 through the resistors PR60 to PR63, respectively. The 2nd terminal, 4th terminal, 9th terminal and 11th terminal which are collector terminals of the drive ICPIC 60 are the 1st terminal, 5th terminal, 8th terminal and 12th terminal which are the base terminals of the drive ICPIC 60 respectively. Correspondingly, when the payout motor drive signal is input to the 1st terminal, the 5th terminal, the 8th terminal, and the 12th terminal, which are the base terminals of the drive ICPIC60, through the resistors PR60 to PR63, respectively, an excitation signal is generated. A drive pulse is output to each phase (/B phase, B phase, A phase, /A phase) corresponding to the payout motor 744. This payout motor drive signal is output from the output terminal of a predetermined output port of the payout control MPU 4120a to the payout control output circuit 4120ca with a reset function, and from the payout control output circuit 4120ca with a reset function to the drive ICPIC 60 via the resistors PR60 to PR63. The signals are output to the first terminal, the fifth terminal, the eighth terminal, and the twelfth terminal, which are base terminals. These drive pulses are performed by switching the excitation currents flowing in the respective phases (/B phase, B phase, A phase, /A phase) of the payout motor 744, and rotate the payout motor 744. In addition, when the drive pulse (excitation signal) of each phase (/B phase, B phase, A phase, /A phase) is cut off by this switching, a back electromotive force is generated. When the back electromotive force exceeds the withstand voltage of the drive ICPIC 60, the drive ICPIC 60 is damaged. Therefore, as a protection, the Zener diode PZD0 described above is electrically connected to the cathode IC of the drive ICPIC 60 in front of the 3rd terminal and the 10th terminal. Adopted a circuit configuration that does.

[10-2-5. CR unit input/output circuit]
Next, the CR unit input/output circuit 4120e for inputting/outputting various signals to/from the CR unit 6 shown in FIG. 16 will be described. From the CR unit 6, the payout control board 4110, via the game ball lending device connection terminal plate 869, as described above, is a ball rental request signal BRDY and a one-time payout operation start request signal BRQ. , And a predetermined voltage VL (+12V) and a ground LG created from AC24V supplied from the power supply board 851 shown in FIG. 16 are supplied, while the payout control board 4110 is connected to a lending device such as a game ball. Through the terminal board 869, an EXS signal indicating that one payout operation has started or ended, and a PRDY signal indicating that the payout operation for paying out a rental ball is possible or impossible. And output. As shown in FIG. 31, the input/output circuit for inputting/outputting these various signals mainly includes photocouplers PIC70 to PIC74 (incorporating infrared LEDs and phototransistors).

The predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC70 via the resistor PR70. The cathode terminal of the photocoupler PIC70 is electrically connected to the ground LG from the CR unit 6. The resistor PR60 is a limiting resistor for limiting a current flowing through the built-in infrared LED of the photocoupler PIC70. When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC70, the photocoupler PIC70 is turned on, while the predetermined voltage VL from the CR unit 6 is not applied to the anode terminal of the photocoupler PIC70. At times, the photo coupler PIC70 is turned off. The emitter terminal of the photocoupler PIC70 is grounded to the ground (GND), the collector terminal of the photocoupler PIC70 is electrically connected to the base terminal of the transistor PTR70 via the resistor PR71, and the transistor is also connected via the resistor PR72. It is electrically connected to the base terminal of the PTR 71. The collector terminal of the photocoupler PIC70 is electrically connected to the resistor PR71, and is also electrically connected to the other end of the pull-up resistor PR73 whose one end is electrically connected to the +5V power supply line.

The base terminal of the transistor PTR70 is electrically connected to the resistor PR71 and is also electrically connected to the other end of the resistor PR74 whose one end is grounded to the ground (GND). The emitter terminal of the transistor PTR70 is grounded to the ground (GND), and the collector terminal of the transistor PTR70 is electrically connected to the other end of the resistor PR75 whose one end is electrically connected to the +5V power supply line and also the non-inverting buffer. 27 through the ICPIC 80 (the non-inverting buffer ICPIC80 includes eight non-inverting buffer circuits, and the logic of the signal waveform input to one of them (PIC80A) is shaped and output without being inverted). It is electrically connected to the input terminal of a predetermined input port of the payout control MPU 4120a shown in FIG. When the transistor PTR70 is turned ON/OFF, the logic of the signal output from the collector terminal of the transistor PTR70 changes, and the signal is input as the CR connection signal 1 to the input terminal of a predetermined input port of the payout control MPU 4120a.

On the other hand, the base terminal of the transistor PTR71 is electrically connected to the resistor PR72 and is also electrically connected to the other end of the resistor PR76 whose one end is grounded to the ground (GND). The emitter terminal of the transistor PTR71 is grounded to the ground (GND), and the collector terminal of the transistor PTR71 is electrically connected to the power supply board 851 via a wiring (harness). When the collector terminal of the transistor PTR71 is electrically connected to the power supply board 851 via a wiring (harness), one end of the power supply board 851 is electrically connected to a +12V power supply line, and is a pull-up resistor (not shown). Is electrically connected to the other end of. When the transistor PTR71 is turned on/off, the logic of the signal output from the collector terminal of the transistor PTR71 changes, and the signal is input to the power supply substrate 851 as a CR connection signal.

The circuit composed of the resistors PR71 and PR74 and the transistor PTR70 is a switch circuit that is turned on/off by turning on/off the photocoupler PIC70.

When the predetermined voltage VL from the CR unit 6 is not applied to the anode terminal of the photocoupler PIC70, the photocoupler PIC70 is turned off and the pull-up resistor PR73 pulls it to the +5V side to turn on the transistor PTR70 and the switch circuit also. It will be turned on. As a result, the voltage applied to the collector terminal of the transistor PTR70 is pulled down to the ground (GND) side, and the CR connection signal 1 whose logic becomes LOW is input to the input terminal of a predetermined input port of the payout control MPU 4120a.

On the other hand, when the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC70, the photocoupler PIC70 is turned on and the voltage applied to the base terminal of the transistor PTR70 is pulled down to the ground (GND) side. As a result, the transistor PTR70 is turned off and the switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor PTR70 is pulled up to +5 V by the pull-up resistor PTR75, and the CR connection signal 1 whose logic becomes HI is input to the input terminal of a predetermined input port of the payout control MPU4120a. It

The circuit composed of the resistors PR72 and PR76 and the transistor PTR71 is also a switch circuit that is turned on/off by turning on/off the photocoupler PIC70.

When the predetermined voltage VL from the CR unit 6 is not applied to the anode terminal of the photocoupler PIC70, the photocoupler PIC70 is turned off, and the transistor PTR71 is turned on by being pulled up to +5V by the pull-up resistor PR73, and the switch circuit is also turned on. It will be turned on. As a result, the voltage applied to the collector terminal of the transistor PTR71 is pulled down to the ground (GND) side in the power supply board 851 via the wiring (harness), and the CR connection signal whose logic becomes LOW is input to the power supply board 851. It

On the other hand, when the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC70, the photocoupler PIC70 is turned on and the voltage applied to the base terminal of the transistor PTR71 is pulled down to the ground (GND) side. As a result, the transistor PTR71 is turned off and the switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor PTR71 is pulled up to +12V by the pull-up resistor of the power supply board 851 via the wiring (harness), and the CR connection signal whose logic becomes HI is input to the power supply board 851. To be done.

The predetermined voltage VL from the CR unit 6 is applied not only to the anode terminal of the photocoupler PIC70 but also to the anode terminal of the photocoupler PIC71 via the resistor PR77. BRDY from the CR unit 6 is input to the cathode terminal of the photocoupler PIC71. The resistor PR77 is a limiting resistor for limiting the current flowing to the built-in infrared LED of the photocoupler PIC71. When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC71 and the logic of BRDY from the CR unit 6 is LOW, the photocoupler PIC71 is turned on while the photocoupler PIC71 is turned on. When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the coupler PIC71 and the logic of BRDY from the CR unit 6 is HI, the photocoupler PIC71 is turned off. There is. The emitter terminal of the photocoupler PIC71 is grounded to the ground (GND), and the collector terminal of the photocoupler PIC71 is electrically connected to the other end of the pull-up resistor PR78 whose one end is electrically connected to the +5V power supply line. At the same time, the non-inverting buffer ICPIC80 (the non-inverting buffer ICPIC80 is provided with eight non-inverting buffer circuits, and the logic of the signal waveform input to one (PIC80B) is shaped and output without being inverted). It is electrically connected to the input terminal of a predetermined input port of the payout control MPU 4120a via. The photocoupler PIC71 is turned on/off to change the logic of the signal output from the collector terminal of the photocoupler PIC71, and the signal is input as a BRDY signal to the input terminal of a predetermined input port of the payout control MPU4120a.

When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC71 and the BRDY logic from the CR unit 6 is LOW, the photocoupler PIC71 is turned on. The BRDY signal whose logic is LOW by pulling down the voltage applied to the collector terminal of the coupler PIC71 to the ground (GND) side is input to the input terminal of a predetermined input port of the payout control MPU 4120a. On the other hand, when the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC71 and the logic of BRDY from the CR unit 6 is HI, the photocoupler PIC71 is turned off. The voltage applied to the collector terminal of the photocoupler PIC71 is pulled up to +5V by the pull-up resistor PR78, and the BRDY signal whose logic becomes HI is input to the input terminal of a predetermined input port of the payout control MPU 4120a. As described above, the logic of the BRDY signal output from the collector terminal of the photocoupler PIC71 is the same as the logic of BRDY from the CR unit 6.

The predetermined voltage VL from the CR unit 6 is applied not only to the anode terminal of the photocoupler PIC70 and the anode terminal of the photocoupler PIC71 but also to the anode terminal of the photocoupler PIC72 via the resistor PR79. The BRQ from the CR unit 6 is input to the cathode terminal of the photocoupler PIC72. The resistor PR79 is a limiting resistor for limiting the current flowing to the built-in infrared LED of the photocoupler PIC72. When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC72 and the logic of BRQ from the CR unit 6 is LOW, the photocoupler PIC72 is turned on while the photocoupler PIC72 is turned on. When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the coupler PIC72 and the logic of BRQ from the CR unit 6 is HI, the photocoupler PIC72 is turned off. There is. The emitter terminal of the photocoupler PIC72 is grounded to the ground (GND), and the collector terminal of the photocoupler PIC72 is electrically connected to the other end of the pull-up resistor PR80 whose one end is electrically connected to the +5V power supply line. At the same time, the non-inverting buffer ICPIC80 (the non-inverting buffer ICPIC80 is provided with eight non-inverting buffer circuits, shapes and outputs the logic of the signal waveform input to one (PIC80C) without inverting it). It is electrically connected to the input terminal of a predetermined input port of the payout control MPU 4120a via. The photocoupler PIC72 is turned on/off to change the logic of the signal output from the collector terminal of the photocoupler PIC72, and the signal is input as a BRQ signal to the input terminal of a predetermined input port of the payout control MPU4120a.

When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC72 and the logic of BRQ from the CR unit 6 is LOW, the photocoupler PIC72 is turned on. The BRQ signal whose logic is LOW when the voltage applied to the collector terminal of the coupler PIC72 is pulled down to the ground (GND) side is input to the input terminal of a predetermined input port of the payout control MPU 4120a. On the other hand, when the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC72 and the logic of BRQ from the CR unit 6 is HI, the photocoupler PIC72 turns off. , The voltage applied to the collector terminal of the photocoupler PIC72 is pulled up to +5 V by the pull-up resistor PR80, and the BRQ signal whose logic becomes HI is input to the input terminal of a predetermined input port of the payout control MPU4120a. Thus, the logic of the BRQ signal output from the collector terminal of the photocoupler PIC 72 is the same as the logic of the BRQ from the CR unit 6.

The EXS signal that indicates that one payout operation has started or ended from the output terminal of the predetermined output port of the payout control MPU 4120a is output to the payout control output circuit 4120cb without the reset function and the payout control output circuit without the reset function. It is input from the 4120cb to the cathode terminal of the photocoupler PIC73 via the resistor PR81. The anode terminal of the photocoupler PIC73 is electrically connected to the other end of the resistor PR82 whose one end is electrically connected to the +12V power supply line. The resistor PR82 is a limiting resistor for limiting the current flowing to the built-in infrared LED of the photocoupler PIC73. When +12V is applied to the anode terminal of the photocoupler PIC73 via the resistor PR82, the EXS output from the output terminal of the predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cb without the reset function. When the signal logic is LOW, while the photocoupler PIC73 is turned on, +12V is applied to the anode terminal of the photocoupler PIC73 through the resistor PR82, and the predetermined output port of the payout control MPU4120a The photo coupler PIC73 is turned off when the logic of the EXS signal that is output from the output terminal of the above through the payout control output circuit 4120cb without the reset function is HI. The emitter terminal of the photocoupler PIC73 is grounded to the ground LG from the CR unit 6, and the collector terminal of the photocoupler PIC73 is inside the CR unit 6 via the game ball lending device connection terminal plate 869 by the pull-up resistor PR83. At a predetermined voltage VL and is electrically connected to the built-in control device. When the photocoupler PIC73 is turned ON/OFF, the logic of the signal output from the collector terminal of the photocoupler PIC73 changes, and the signal is input as EXS to the built-in control device of the CR unit 6.

When +12V is applied to the anode terminal of the photocoupler PIC73 via the resistor PR82, the EXS output from the output terminal of the predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cb without the reset function. When the signal logic is LOW, the photocoupler PIC73 is turned on, so the voltage applied to the collector terminal of the photocoupler PIC73 is lowered to the ground (GND) side and the EXS whose logic is LOW is the CR unit. 6 to the built-in control device. On the other hand, when +12V is applied to the anode terminal of the photocoupler PIC73 through the resistor PR82, it is output from the output terminal of the predetermined output port of the payout control MPU 4120a through the payout control output circuit 4120cb without the reset function. When the logic of the EXS signal is HI, the photocoupler PIC73 is turned off. Therefore, the voltage applied to the collector terminal of the photocoupler PIC73 is pulled up to the predetermined voltage VL by the pull-up resistor PR83 and the logic becomes HI. EXS is input to the built-in control device of the CR unit 6. As described above, the logic of EXS output from the collector terminal of the photocoupler PIC73 is the same as the logic of the EXS signal output from the output terminal of the predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cb without the reset function. It has the same logic.

The PRDY signal indicating that the payout operation for paying out the ball from the output terminal of the predetermined output port of the payout control MPU 4120a is possible or impossible is the cathode terminal of the photocoupler PIC74 via the resistor PR84. Has been entered in. The anode terminal of the photocoupler PIC74 is electrically connected to the other end of the resistor PR85 whose one end is electrically connected to the +12V power supply line. The resistor PR85 is a limiting resistor for limiting the current flowing to the built-in infrared LED of the photocoupler PIC74. When +12V is applied to the anode terminal of the photocoupler PIC74 via the resistor PR85, PRDY output from the output terminal of the predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cb without the reset function. When the signal logic is LOW, the photocoupler PIC74 is turned on, while +12V is applied to the anode terminal of the photocoupler PIC74 through the resistor PR85, and the predetermined output port of the payout control MPU4120a. The photocoupler PIC74 is turned off when the logic of the PRDY signal output from the output terminal of No. 4 through the payout control output circuit 4120cb without the reset function is HI. The emitter terminal of the photocoupler PIC74 is grounded to the ground LG from the CR unit 6, and the collector terminal of the photocoupler PIC74 is inside the CR unit 6 via the game ball lending device connection terminal plate 869 by the pull-up resistor PR86. At a predetermined voltage VL and is electrically connected to the built-in control device. When the photocoupler PIC74 is turned ON/OFF, the logic of the signal output from the collector terminal of the photocoupler PIC74 changes, and the signal is input to the built-in control device of the CR unit 6 as PRDY.

When +12V is applied to the anode terminal of the photocoupler PIC74 via the resistor PR85, PRDY output from the output terminal of the predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cb without the reset function. When the signal logic is LOW, the photocoupler PIC74 is turned on, so the voltage applied to the collector terminal of the photocoupler PIC74 is lowered to the ground (GND) side and the logic becomes LOW. 6 to the built-in control device. On the other hand, when +12V is applied to the anode terminal of the photocoupler PIC74 via the resistor PR85, the output is output from the output terminal of the predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cb without the reset function. When the logic of the PRDY signal is HI, the photocoupler PIC74 is turned off. Therefore, the voltage applied to the collector terminal of the photocoupler PIC74 is pulled up to the predetermined voltage VL by the pull-up resistor PR86 and the logic becomes HI. PRDY is input to the built-in control device of the CR unit 6. As described above, the logic of PRDY output from the collector terminal of the photocoupler PIC74 is the same as the logic of the PRDY signal output from the output terminal of the predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cb without the reset function. It has the same logic.

[10-2-6. Various input/output signals to payout control MPU]
Next, various input/output signals input/output from the input/output terminals of various input/output ports of the payout control MPU 4120a will be described.

As shown in FIG. 27, the RXD terminal which is the serial data input terminal of the serial input port of the payout control MPU 4120a receives the serial data from the main control board 4100 as the main pay serial data reception signal via the payout control input circuit 4120b. To be done. On the other hand, from the TXD terminal which is the serial data output terminal of the serial output port of the payout control MPU 4120a, the serial data to be transmitted to the main control board 4100 is sent to the payout control output circuit 4120cb without the reset function as a payer serial data transmission signal. The payout control output circuit 4120cb without the reset function transmits a payer serial data transmission signal to the main control board 4100.

To each input terminal of the predetermined input port of the payout control MPU 4120a, the above-mentioned RWMCLR signal, payout blackout notice signal, door open signal, full signal, various signals from the CR unit 6 (BRQ signal, BRDY signal, CR connection) Signal 1 etc.), for example, the main payment ACK signal from the main control board 4100 for notifying the completion of the normal reception of the above-mentioned payment main serial data reception signal is sent via the payout control input circuit 4120b. 15, the detection signals from the out-of-ball switch 750, the counting switch 751, the rotation angle switch 752, and the like shown in FIG. 15 are respectively input via the payout control input circuit 4120b, and the potentiometer shown in FIG. The operation signal from the meter 512 and the detection signals from the touch switch 516, the firing stop switch 518, the full tank switch 550, and the like shown in FIG. 15 are passed through the power supply board 851 and the payout control input circuit 4120b of the payout control board 4100. Are input respectively.

On the other hand, from each output terminal of a predetermined output port of the payout control MPU 4120a, the above-mentioned EXS signal and PRDY signal are output to the payout control output circuit 4120cb without reset function to output the EXS signal from the payout control output circuit 4120cb without reset function. The PRDY signal is output to the CR unit input/output circuit 4120e, or the above-mentioned voltage switching signal is output to the payout control output circuit 4120ca with reset function to output the voltage switching signal from the payout control output circuit 4120ca with reset function to the voltage switching circuit 4120da. Or output a payout motor drive signal to the payout control output circuit 4120ca with reset function and output a payout motor drive signal from the payout control output circuit 4120ca with reset function to the payout motor 744 via the payout motor drive circuit 4120d. In addition to the above, for example, the payer ACK signal indicating that the above-described main pay serial data reception signal has been normally received is output to the payout control output circuit 4120ca with reset function and the payout control output circuit 4120ca with reset function is used. The ACK signal is output to the main control board 4100, or the drive signal of the error LED indicator 860b shown in FIG. 15 is output to the payout control output circuit 4120ca with reset function to output the drive signal from the payout control output circuit 4120ca with reset function. A control signal for outputting to the error LED indicator 860b or for adjusting the drive current to the firing solenoid drive circuit 858 shown in FIG. 15 is output to the payout control output circuit 4120ca with reset function to output the payout control output circuit 4120ca with reset function. Output a drive current to the firing solenoid 654 or output a control signal for adjusting the drive current to the ball feeding solenoid drive circuit 859 shown in FIG. 15 to the payout control output circuit 4120ca with a reset function to output the payout control with a reset function. A drive current is output from the output circuit 4120ca to the ball feeding solenoid 585, and so on.

[10-3. Various input/output signals to/from the main control board and various output signals to the external terminal board]
Next, various input/output signals between the payout control board 4110 and the main control board 4100 and various output signals from the payout control board 4110 to the external terminal board 784 will be described with reference to FIG. 32.

[10-3-1. Various input/output signals with main control board]
The payout control board 4110 exchanges various input/output signals with the main control board 4100. Specifically, as shown in FIG. 32A, the payout control board 4110 has the above-mentioned payer serial data transmission signal, payer ACK signal, operation signal (RAM clear signal), main frame door opening signal, etc. Is output to the main control board 4100. These output signals are pulled up to the +12V side by the pull-up resistor of the main control input circuit 4100b of the main control board 4100.

On the other hand, the payout control board 4110 has a 15-round big hit information output signal, a 2-round big hit information output signal, etc. in addition to the main pay serial data reception signal, the main pay ACK signal, and the operation signal (RAM clear signal) described above. Big hit information output signal, probability fluctuation information output signal, special symbol display information output signal, normal symbol display information output signal, time saving medium information output signal, starting mouth winning information output signal, etc. Signals and the like are input from the main control board 4100. These input signals are pulled up to the +12V side by the pull-up resistor of the payout control input circuit 4120b of the payout control unit 4120 of the payout control board 4110.

[10-3-2. Various output signals to external terminal board]
The payout control board 4110 outputs various signals to the external terminal board 784. Specifically, as shown in FIG. 32B, in addition to the above-mentioned outer end frame door opening information output signal, the number of game balls actually paid out as prize balls by the payout motor 744 reaches 10 balls. The number-of-prize-balls information output signal output for each, the jackpot information output signal of the 15-round jackpot information output signal and the 2-round jackpot information output signal from the main control board 4100 through the payout control board 4110, and the information output during probability fluctuation A game information signal such as a signal, a special symbol display information output signal, a normal symbol display information output signal, a time saving medium information output signal, and a starting opening winning information output signal is output to the external terminal board 784. These output signals are pulled up to the +12V side by the pull-up resistor of the external terminal board 784.

In addition to the various signals described above being input to the external terminal board 784, as shown in FIG. 32B, a main prize ball number information output signal and a power saving mode information output signal from the peripheral control board 4140. Has been entered. This main prize ball number information output signal will be briefly described. The main control board 4100 is provided on the game board 4 and has the first start opening 2101, the second start opening 2102, and the general winning openings 2104 and 2201 shown in FIG. , And the number of game balls planned to be paid out as prize balls based on the game balls that have entered the various winning holes such as the special winning hole 2103 (in the present embodiment, it is set to 10 balls). The main prize ball number information output command, which will be described later, is transmitted to the peripheral control board 4140, and the peripheral control board 4140 is based on the received main prize ball number information output command. Of the game balls that are to be paid out as prize balls based on the game balls that have entered the various winning openings such as the first starting opening 2101, the second starting opening 2102, the general winning openings 2104, 2201, and the special winning opening 2103. Every time the number of balls reaches a predetermined number of balls (in the present embodiment, it is set to 10 balls), a main award ball number information output signal is output to the external terminal board 784 with that effect as the main award ball number information. And then tells the hall computer. The main prize ball number information output signal is pulled up to the +12V side by the pull-up resistor of the external terminal board 784.

Next, the power saving mode information output signal will be briefly described. The peripheral control board 4140, based on the power consumption status history information stored and held in the power consumption status RAM 4150f illustrated in FIG. 17, at the time of power recovery. When the power is cut off (immediately before the power is cut off), the status of power consumed by the pachinko gaming machine 1 is grasped at the time of power recovery, and the power consumption at the pachinko gaming machine 1 is suppressed. It is transmitted to the hall computer via the terminal board 784. Specifically, the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 shown in FIG. 17 uses power in the power recovery mode power saving mode transition determination process in the peripheral control unit power-on process, which will be described later and is executed at the time of power recovery. Based on the power consumption status history information stored and held in the consumption status history RAM 4150f, the power status consumed by the pachinko gaming machine 1 at the time of power shutdown (immediately before power shutdown) (power consumption suppression stage described later) is specified. Determines whether or not to switch to power saving mode at power recovery. The peripheral control MPU 4150a outputs a power saving mode information output signal to the external terminal board 784 as power saving mode information to notify the hall computer when the result of the determination is that the power saving mode does not shift to the power recovery mode. When the power is to be switched to the power saving mode at the time of power recovery, the power saving mode information output signal is output to the external terminal board 784 as power saving mode information and transmitted to the hall computer. This power saving mode information output signal is pulled up to the +12V side by the pull-up resistor of the external terminal board 784.

That is, two signals, that is, an outer end frame door opening information output signal and a prize ball number information output signal from the payout control board 4110 side are output to the external terminal board 784, and a 15-round big hit from the main control board 4100 side. Information output signal, 2 round jackpot information output signal, probability fluctuation information output signal, special symbol display information output signal, normal symbol display information output signal, time saving medium information output signal, and starting mouth winning information output signal 7 signals Two signals, that is, the main prize ball number information output signal and the power saving mode information output signal from the peripheral control board 4140 side are output through (passing through) the payout control board 4110.

A signal output from the external terminal board 784 is transmitted to a hall computer installed in a game hall (hole) (not shown), and the hall computer monitors the game and the like of the player. When the 15-round jackpot information output signal or the 2-round jackpot information output signal is output to the hall computer as one jackpot information output signal, the hall computer outputs the number of jackpots in which the number of rounds is two (2 round jackpot). The number of jackpots of the pachinko gaming machine 1 is the sum of the number of jackpots) and the number of jackpots in which the round has reached 15 times (the number of jackpots in 15 rounds). For this reason, since the hall computer cannot grasp the number of occurrences of the two-round jackpot and the number of 15-land jackpots from the total number of jackpots, the number of jackpots actually generated in the pachinko gaming machine 1 is large. However, it is impossible to know whether it is a 2-round jackpot or a 15-round jackpot. In addition, a data counter (not shown) is arranged above the pachinko gaming machine 1, and it is possible for some players to refer to the number of occurrences of the jackpot gaming state displayed on the data counter to determine whether or not to play the game. Some choose.

However, the number of times of occurrence of the jackpot game state displayed on the data counter may be biased to the number of occurrences of the two rounds of jackpots in practice, so even if the player starts the game, only two rounds of jackpots occur. In some cases, a 15-round jackpot does not occur easily. As described above, although the number of times of occurrence of the big hit game state displayed on the data counter can give the player a sense of expectation, the player may be more excited than necessary.

Therefore, in the present embodiment, as the big hit information output signal, the 15-round big hit information output signal and the 2-round big hit information output signal are separately output to the hall computer, so that the hall computer generates the number of occurrences of the 2-round big hit. It is possible to accurately grasp the number of times of 15 rounds of big hits. Therefore, the hall computer can grasp whether the number of big hits actually generated in the pachinko gaming machine 1 is the two-round big hit or the 15-round big hit. The number of round jackpot occurrences and the number of 2 round jackpots can be displayed separately or only the number of 15 round jackpots can be displayed as the number of jackpot gaming states, so that the player's ambitions are increased more than necessary. Nor.

In the present embodiment, the 2-round big hit information output signal is in a state of being output to the hall computer during the period until the 2-round big hit occurs and is ended, and the 15-round big hit information output signal is also the 15-round big hit. It is in the state of being output to the hall computer during the period from the occurrence to the end. In addition to the method of outputting the 2-round jackpot information output signal and the 15-round jackpot information output signal to the hall computer as in the present embodiment, for example, when the 2-round jackpot is generated, the 2-round jackpot information output signal is output for a predetermined period. When the 15 round big hit information is output to the hall computer, the 15 round big hit information output signal is output to the hall computer only for a predetermined period. Such a 2 round big hit information output signal and the 15 round big hit information A method of outputting the output signal to the hall computer for the same predetermined period can also be mentioned.

[11. Array of output terminals on external terminal board]
Next, the arrangement of the output terminals of the external terminal board 784 for outputting various signals to the hall computer installed in the game hall (hall) will be described with reference to FIG. The external terminal board 784 is attached to the rear surface of the prize ball base 710 attached to the rear surface of the main body frame base 600 shown in FIG. 3, and the rear side thereof is covered with the external terminal board cover 786. FIG. 33 is a diagram showing the arrangement of the output terminals of the external terminal board.

As described above, the external terminal board 784 receives the outer edge frame door opening information output signal, the award ball number information output signal, the 15 round jackpot information output signal and the 2 round jackpot information output signal, and the probability is changing. The information output signal, the special symbol display information output signal, the normal symbol display information output signal, the time saving medium information output signal, and the starting mouth winning information output signal are input from the payout control board 4110, and the main prize ball number information output signal, A power saving mode information output signal is input from the peripheral control board 4140, and these various signals are output to the outside of the pachinko gaming machine 1. The hall computer is electrically connected to the external terminal board 784 so that a signal larger than the minimum detection signal width (for example, a signal width of 60 ms) can be detected as various signals from the external terminal board 784. Is becoming

These various signals will be briefly described. The outer end frame door opening information output signal does not occur during the normal game by the player that the door frame 5 and/or the main body frame 3 shown in FIG. 1 is open. The prize ball number information output signal is a signal indicating that the state has occurred, and the prize motor number information output signal is output every time the number of game balls actually paid out as prize balls by the payout motor 744 reaches 10 balls. The main prize ball number information output signal, which is a signal to that effect, includes various winning openings such as the first starting opening 2101, the second starting opening 2102, the general winning openings 2104 and 2201, and the big winning opening 2103 shown in FIG. It is a signal that informs that the number of game balls scheduled to be paid out as a prize ball based on the game balls that entered into the ball reaches 10 balls. The power saving mode information output signal is when the power is turned off (immediately before the power is turned off. ) Is a signal that conveys the state of transition to the power saving mode at power recovery in which the power status consumed by the pachinko gaming machine 1 is grasped at the time of power recovery and the power consumed by the pachinko gaming machine 1 is suppressed. The information output signal is a signal that conveys that a 15 round jackpot has occurred, and the 2 round jackpot information output signal is a signal that indicates that a 2 round jackpot has occurred. The changing information output signal is a signal that conveys a state in which a probability change has occurred, and the special symbol display information output signal is a special symbol display 1185 or lower on the function display substrate 1191 shown in FIG. The special symbol display 1186 is a signal indicating that the variable display of the special symbol is finished (stopped), and the normal symbol display information output signal is the normal symbol display 1189 of the function display board 1191 shown in FIG. It is a signal that informs that the variable display of the normal symbol is finished (stopped), the time saving information output signal is a signal that the time saving state has occurred, and the starting mouth winning information output signal is , Is a signal that notifies each time a game ball enters the first starting port 2101 or the second starting port 2102 shown in FIG.

On the external terminal board 784, as shown in FIG. 33, the output terminals PT1 to PT11 are arranged horizontally in a line. The output terminal PT1 is provided in white and outputs a prize ball number information output signal. As described above, the prize ball number information output signal is a signal that conveys that fact whenever the number of game balls actually paid out as prize balls by the payout motor 744 shown in FIG. 5 reaches 10 balls. In the present embodiment, 0.106 seconds from the output terminal PT1 (since 2 ms is set as the interrupt cycle when the payout control unit timer interrupt process described later is performed, the output period of 0.106 seconds (that is, The signal width of the prize ball number information output signal output from the output terminal PT1) is output during a period in which the payout control unit timer interrupt process is repeated 53 times based on an interrupt cycle of 2 ms). ing. When the prize ball number information output signal from the external terminal board 784 is input to the hall computer, the hall computer causes the payout motor 744 of the pachinko gaming machine 1 as a prize ball each time the prize ball number information output signal is input. It is possible to know that the game balls of 10 balls have been paid out as prize balls, and it is possible to count the number of the game balls paid out to grasp the total number of the game balls paid out by the pachinko gaming machine 1. it can.

The output terminal PT2 is provided in green and outputs the outer end frame door opening information output signal. As described above, the outer edge frame door opening information output signal is in a state where the door frame 5 and/or the main body frame 3 shown in FIG. 1 is not opened during the normal game by the player. In this embodiment, the signal is transmitted, and is output from the output terminal PT2 while the door frame 5 and/or the main body frame 3 is open. When the outer edge frame door opening information output signal from the external terminal board 784 is input to the hall computer, the hall computer holds the door frame 5 of the pachinko gaming machine 1 while the outer edge frame door opening information output signal is being input. And/or it can be understood that the body frame 3 is open.

The output terminal PT3 is provided in gray to output a special symbol display information output signal. As described above, the special symbol display information output signal is in a state in which the variable display of the special symbol is ended (stopped) on the upper special symbol display device 1185 or the lower special symbol display device 1186 shown in FIG. In the present embodiment, it is a signal indicating that there is 0.128 at the end (stop) of the variable display of the special symbol on the upper special symbol display 1185 or the lower special symbol display 1186 from the output terminal PT3 to the function display substrate 1191. It is designed to be output for a second. When the special symbol display information output signal from the external terminal board 784 is input to the hall computer, the hall computer receives the special symbol display information output signal, and the special symbol on the function display board 1191 of the pachinko gaming machine 1 It is possible to grasp that the variable display of the special symbol has ended (stopped) on the display device 1185 and the lower special symbol display device 1186, and the number of times is counted, and the special symbol on the function display board 1191 of the pachinko gaming machine 1 It is possible to grasp the total number of times the special symbols are variably displayed on the display device 1185 or the lower special symbol display device 1186.

The output terminal PT4 is colored yellow and outputs a starting opening winning information output signal. As described above, the start-port winning information output signal is a signal that notifies each time a game ball enters the first starting port 2101 or the second starting port 2102 shown in FIG. 8, and in the present embodiment. Each time a game ball enters the first starting port 2101 or the second starting port 2102 from the output terminal PT4, it is output for 0.128 seconds. When the start-port winning information output signal from the external terminal board 784 is input to the hall computer, the hall computer receives the start-port winning information output signal each time the first start-port 2101 or the first start-port 2101 of the pachinko gaming machine 1 is input. 2 It is possible to grasp that a game ball has entered the starting port 2102 and count the number of times the starting port winning information output signal is input to count the first starting port 2101 or the second starting port of the pachinko gaming machine 1. The total number of game balls entered in 2102 can be grasped.

The output terminal PT5 is provided in black and outputs a 15-round big hit information output signal. As described above, the 15-round jackpot information output signal is a signal indicating that the 15-round jackpot has occurred, and in the present embodiment, while the 15-round jackpot is generated from the output terminal PT5, It is supposed to be output. When the 15-round jackpot information output signal from the external terminal board 784 is input to the hall computer, the hall computer generates a 15-round jackpot for the pachinko gaming machine 1 while the 15-round jackpot information output signal is being input. It is possible to grasp that it is in the state where it is, and to count the number of times the 15 round jackpot information output signal is input to grasp the total number of 15 round jackpots that have occurred in the pachinko gaming machine 1.

The output terminal PT6 is provided in pink and outputs a 2-round big hit information output signal. As described above, the 2-round jackpot information output signal is a signal for notifying that the 2-round jackpot is being generated. In the present embodiment, while the 2-round jackpot is being generated from the output terminal PT6, It is supposed to be output. When the 2-round jackpot information output signal from the external terminal board 784 is input to the hall computer, the hall computer generates a 2-round jackpot for the pachinko gaming machine 1 while the 2-round jackpot information output signal is being input. It is possible to grasp that it is in a state where it is in the state of being, and to count the number of times the 2-round jackpot information output signal is input to grasp the total number of times that the 2-round jackpot has occurred in the pachinko gaming machine 1.

The output terminal PT7 is a terminal which is colored blue and outputs a normal symbol display information output signal. The normal symbol display information output signal is, as described above, a signal indicating that it is in a state of ending (stopping) the variable display of the normal symbol on the normal symbol display device 1189 of the function display substrate 1191 shown in FIG. In the present embodiment, the output from the output terminal PT7 for 0.128 seconds at the end (stop) of the variable display of the normal symbol on the normal symbol display 1189 of the function display substrate 1191, is adapted to be output. When the normal symbol display information output signal from the external terminal board 784 is input to the hall computer, the hall computer, when the normal symbol display information output signal is input, the normal symbol display on the function display board 1191 of the pachinko gaming machine 1. It is possible to grasp that the variable display of the normal symbol is ended (stopped) in the device 1189, and the number of times is counted to display the variable variable in the normal symbol display 1189 of the function display board 1191 of the pachinko gaming machine 1. It is possible to grasp the total number of times.

The output terminal PT8 is provided in red and outputs a time saving/medium time information output signal. As described above, the time saving/time saving information output signal is a signal for notifying that the time saving state has occurred, and in the present embodiment, it is output from the output terminal PT8 while the time saving state is occurring. ing. When the time saving/medium time information output signal from the external terminal board 784 is input to the hall computer, the hall computer recognizes that the pachinko gaming machine 1 is in the time saving state when the time saving/medium time information output signal is input. Besides, it is possible to grasp the total number of times that the pachinko gaming machine 1 is in the time saving state by counting the number of times the time saving information output signal is input.

The output terminal PT9 is provided in orange and outputs the information output signal during probability variation. As described above, the information signal during probability change is a signal indicating that the probability change is occurring, and in the present embodiment, it is output from the output terminal PT9 while the probability change is occurring. It has become so. When the probability variation information output signal from the external terminal board 784 is input to the hall computer, the hall computer receives the probability variation information output signal, and the probability change occurs in the pachinko gaming machine 1. It is possible to grasp that the total number of times that the probability variation has occurred in the pachinko gaming machine 1 by counting the number of times the information output signal during the probability variation has been input.

The output terminal PT10 is light blue and outputs a main prize ball number information output signal. The main prize ball number information output signal is, as described above, based on the command (main prize ball number information output command described later) from the main control board 4100, the first starting port 2101 and the second start shown in FIG. Each time the number of game balls to be paid out reaches 10 balls, which is to be paid out as a prize ball based on the game balls that have entered the various prize holes such as the mouth 2102, the general prize holes 2104, 2201, and the big prize hole 2103. Is output from the output terminal PT10 for 0.128 seconds (as an interrupt cycle when a peripheral control unit 1 ms timer interrupt process described later is performed, a payout control unit timer interrupt process described later in the present embodiment). Since it is set to 1 ms, which is different from the interrupt cycle (2 ms) at the time of performing, the output period of 0.128 seconds (that is, the signal width of the main prize ball number information output signal output from the output terminal PT10) is 1 ms. Based on the interrupt period, the peripheral control unit 1 ms timer interrupt process is output 128 times). When the main prize ball number information output signal from the external terminal board 784 is input to the hall computer, the hall computer causes the pachinko gaming machine 1 to receive 10 balls as a prize ball each time the main prize ball number information output signal is input. It is possible to understand that the game balls are to be paid out as prize balls, and the total number of game balls to be paid out by the pachinko gaming machine 1 by counting the number of game balls to be paid out. Can be grasped. In addition, based on a command (main prize number information output command described later) from the main control board 4100, for example, the first starting opening 2101, the second starting opening 2102, the general winning opening 2104, 2201, the big winning opening 2103, etc. When the number of game balls scheduled to be paid out as a prize ball based on the game balls that have entered the various winning holes of 20 has reached 20 or more and the main prize ball number information output signal is output multiple times, the main prize The peripheral control board 4140 and the external terminal board 784 are spaced at intervals of 0.128 seconds so that the ball count information output signal is one continuous signal for 0.256 (=0.128 seconds×2 times) seconds. It is designed to be output to.

The output terminal PT11 is provided in yellow green and outputs a power saving mode information output signal. As described above, the power-saving mode information output signal is output when the power is cut off (immediately before the power is cut off) based on the power consumption status history information stored and held in the power consumption status RAM 4150f illustrated in FIG. Peripheral control MPU4150a shown in FIG. 17 grasps the power status consumed by the pachinko gaming machine 1 at the time of power recovery, and notifies the state of transition to the power saving mode at power recovery in which the power consumed by the pachinko gaming machine 1 is suppressed. This is a signal, and in the present embodiment, in the state of transition to the power saving mode at power recovery, the output terminal PT11 has an upper limit time of 5 minutes of a power saving mode at power recovery mode, which will be described later (peripheral control unit 1 ms timer interrupt described later. In the present embodiment, the interrupt period when the process is performed is set to 1 ms, which is different from the interrupt period (2 ms) when the payout control unit timer interrupt process described later is performed, and thus the output period of 5 minutes (300 seconds). (That is, the signal width of the power saving mode information output signal output from the output terminal PT11) is output during the period in which the peripheral control unit 1 ms timer interrupt process is repeated 300,000 times based on the interrupt cycle of 1 ms. It has become.

Of the output terminals PT1 to PT11 of the external terminal board 784, the output terminals PT1 and PT2 output various signals output on the payout control board 4110 side, and the output terminals PT3 to PT9 output on the main control board 4100 side. Various signals are output (passed) through the payout control board 4110, and the output terminals PT10 and PT11 are arranged so that the signals output on the peripheral control board 4140 side are output. The output terminals PT1 to PT11 are respectively colored, and by electrically connecting wirings having connectors colored in the same colors to the output terminals PT1 to PT11 respectively, other wirings are erroneously electrically connected. It is possible to prevent the physical connection. Then, the payout control board 4110 is so arranged that various signals output on the payout control board 4110 side, various signals output on the main control board 4100 side, and signals output on the peripheral control board 4140 side do not mix. Side output terminals PT1 and PT2 for transmitting various signals output to the hall computer are arranged in a line on the left side of the external terminal board 784 to transmit various signals output on the main control board 4100 side to the hall computer. The output terminals PT3 to PT9 are arranged in a line from the left side of the center of the external terminal board 784 to the right side, and the output terminals PT10 and PT11 for transmitting the signals output on the peripheral control board 4140 side to the hall computer are external terminal boards. By arranging the output terminals PT1 to PT11 in a line by arranging them on the right side of 784, in this respect as well, wiring for transmitting various signals output on the payout control board 4110 side to the hall computer, The wiring for transmitting various signals output on the main control board 4100 side to the hall computer and the wiring for transmitting signals output on the peripheral control board 4140 side to the hall computer are mistakenly electrically connected. Can be prevented.

In the present embodiment, the award ball number information output signal output on the payout control board 4110 side and the main award ball number information output signal output on the peripheral control board 4140 side are respectively holes from the external terminal board 784. It is configured to communicate to a computer. This is, for example, the game balls stored in the prize ball tank 720 when the game balls from the pachinko island equipment side are not supplied to the prize ball tank 720 shown in FIG. 1 due to some trouble in the pachinko island equipment. When the 15 round big hit happens to the pachinko gaming machine 1 at the time when the remaining amount is low, the number of game balls stored in the prize ball tank 720 for paying out the game balls as prize balls is insufficient, so the payout is made. It becomes impossible to take out (or, if, for example, a ball clogging or a ball spot occurs in the prize ball device 740, the game ball cannot be paid out unless it can be eliminated). Then, the prize ball number information output signal output on the payout control board 4110 side, as described above, the number of game balls actually paid out as prize balls by the payout motor 744 shown in FIG. 5 reaches 10 balls. Since this is a signal that conveys that fact, the payout control board 4110 can output a prize ball number information output signal to the hall computer via the external terminal board 784 when the game balls cannot be paid out. become unable. When the game balls are not paid out, the player calls a clerk in the hall. The clerk of the hall or the like, for example, checks the hose-shaped supply nozzle or the like for supplying game balls from the pachinko island facility to the prize ball tank 720 and specifies the position of the ball clogging (in addition, for example, in the prize ball device 740). By identifying and eliminating the position of the ball clogging or the position of the ball clogging that has occurred, the game ball will be returned to the payout state.

However, even when the staff in the hall is working on the game, since the game by the main control board 4100 is in progress, the game balls are paid out by the staff in the hall after the 15 rounds of big hits are completed. When the state returns to the state in which the payout control board 4110 returns, the payout control board 4110 sequentially pays out unpaid gaming balls, and the payout control board 4110 is in spite of the fact that the 15 round big hit ends and the 15 round big hit does not occur. Is output every time the number of game balls actually paid out by the payout motor 744 as a prize ball reaches 10 and outputs a prize ball number information output signal to that effect and transmits it to the hall computer via the external terminal board 784. It will be. Then, despite the fact that the 15th round jackpot has not occurred, an extremely large number of game balls will be paid out. Therefore, the gaming state of the pachinko gaming machine 1 and the gaming balls paid out by the pachinko gaming machine 1 There arises a problem that the hall computer cannot accurately grasp the relationship between the number of balls and the number of balls.

Therefore, in the present embodiment, regardless of whether or not the payout motor 744 is drive-controlled by the payout control board 4110 to actually pay out as a prize ball, that is, it is different from the prize ball number information output signal output from the payout control board 4110. As a signal of, the main control board 4100 is a game ball that has entered various winning openings such as the first starting opening 2101, the second starting opening 2102, the general winning openings 2104 and 2201, and the big winning opening 2103 shown in FIG. Each time the number of game balls to be paid out as a prize ball reaches 10 balls based on the above, a command (main prize ball number information output command described later) is transmitted to the peripheral control board 4140, and the peripheral control board is sent. Based on the received command (main prize ball number information output command described later) 4140, various winning prizes such as the first starting opening 2101, the second starting opening 2102, the general winning openings 2104 and 2201, and the big winning opening 2103. Whenever the number of game balls to be paid out as a prize ball based on the game ball that entered the mouth reaches 10, the main prize ball number information output signal is used as the main prize ball number information to output the external terminal board 784. We adopted the mechanism to output to and send it to the hall computer. As a result, even if the above-described trouble (a trouble such as a ball clogging in the supply nozzle or the like, a ball clogging in the prize ball device 740, a ball scatter, etc.) occurs, the gaming state of the pachinko gaming machine 1 and this gaming state The relationship between the number of game balls to be paid out in and the number of game balls can be accurately transmitted to the hall computer. Therefore, the hall computer can accurately grasp the relationship between the gaming state of the pachinko gaming machine 1 and the number of gaming balls to be paid out in the gaming state.

[12. LCD output board circuit]
Next, a circuit of the liquid crystal output substrate 3420 shown in FIG. 19 will be described with reference to FIGS. 34 to 37. First, the configuration of the liquid crystal output substrate will be described, and subsequently, the configurations of various light guide plate control circuits and game board side VDP control target decoration LED control circuits will be described. 34 is a block diagram of the liquid crystal output substrate, FIG. 35 is a diagram showing a correspondence relationship between various serial controllers and output destinations in the game board side signal separation control circuit, and FIG. 36 is a block diagram of various light guide plate control circuits. FIG. 37 is a block diagram of the game board side VDP control target decoration LED control circuit.

[12-1. Configuration of LCD output board]
The liquid crystal in the peripheral control board 4140 and the sound source built-in VDP 4160a of the sound control unit 4160 are used for the light guide plate information and the illumination on the game board side drawing data of the screen drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). Drawing data is generated in the game board side display area VRGN1 provided on the built-in VRAM as information provided according to a predetermined game board side generation rule, and is output from the channel CH1. As described above, when the drawing data output from the channel CH1 is transmitted to the liquid crystal output substrate 3420 by the LVDS system, the RGB conversion circuit 3420f of the liquid crystal output substrate 3420 is based on the signal transmitted by the LVDS system. Are converted into parallel signals. As described above, this parallel signal is composed of three video signals of a red video signal, a green video signal, and a blue video signal, and three sync signals of a horizontal sync signal, a vertical sync signal, and a clock signal. ing.

The RGB conversion circuit 3420f converts the drawing data output from the channel CH1 into a parallel signal based on a signal transmitted by the LVDS system (that is, a red video signal which is drawing data output from the channel CH1 of the sound source built-in VDP 4160a, 3 video signals of a green video signal and a blue video signal, and 3 sync signals of a horizontal sync signal, a vertical sync signal, and a clock signal), and output to the game board side signal separation control circuit 3420g.

As shown in FIG. 34, the game board side signal separation control circuit 3420g includes a signal separation unit 3420ga, a buffer memory 3420gb, a distribution output control unit 3420gc, a first serial controller 3420gd1 to an eleventh serial controller 3420gd11. .. When the parallel signal converted by the RGB conversion circuit 3420f is input, it is input to the signal separation unit 3420ga.

The signal separation unit 3420ga includes a first resolution conversion unit 3420gaa and a second resolution conversion unit 3420gab. The first resolution conversion unit 3420gaa uses the drawing data converted into the parallel signals to draw the game board side drawing data for the game board side effect display unit 1900 (liquid crystal panel 5000e), that is, the red video signal, the green video signal, and the blue video. By cutting out three video signals called signals and three sync signals called horizontal sync signals, vertical sync signals, and clock signals, the game board side drawing data is separated from the drawing data converted into parallel signals, and the liquid crystal is displayed. While outputting to the game board side liquid crystal drive circuit 3420h of the output board 3420, the second resolution conversion unit 3420gab selects from among the plurality of light guide plates included in the game board side effect display unit 1900 from the drawing data converted into the parallel signal. Light guide plate information for selecting one light guide plate, and a plurality of decorative boards of the game board 4 provided on each of the plurality of game board-side VDP control target decorative boards that are directly controlled by the sound source built-in VDP 4160a By cutting out the electric decoration information for the LED (ornamental LED) and the drawing data converted into the parallel signal, the light guide plate information and the electric decoration information are separated and output to the buffer memory 3420gb to perform the writing operation.

In other words, the first resolution conversion unit 3420gaa is generated from the drawing data converted into the parallel signal in the game board side drawing data area VRGN1a of the game board side display area VRGN1 provided in the built-in VRAM of the sound source built-in VDP4160a. By cutting out the drawing data on the game board side, the drawing data on the game board side can be separated from the drawing data converted into parallel signals and output to the driving circuit 3420h for the liquid crystal output board 3420. The second resolution conversion unit 3420gab generates drawing data in the game board side accompanying information area VRGN1b of the game board side display area VRGN1 provided on the built-in VRAM of the sound source built-in VDP 4160a from the drawing data converted to the parallel signal. By cutting out the light guide plate information and the electric decoration information that are generated, the light guide plate information and the electric decoration information can be separated from the drawing data converted into the parallel signal and output to the buffer memory 3420gb to perform the writing operation. is there.

In the present embodiment, the game board side drawing data generated in the game board side drawing data area VRGN1a of the game board side display area VRGN1 provided in the built-in VRAM of the sound source built-in VDP 4160a is provided in the game board side effect display unit 1900. Since it matches the resolution of the liquid crystal panel 5000e (12 inches having an image size of 800×600 dots), the first resolution conversion unit 3420gaa cuts out the game board side drawing data without performing the enlargement or reduction processing. It is output to the game board side liquid crystal drive circuit 3420h of the liquid crystal output substrate 3420 as it is. The game board side drawing data generated in the game board side drawing data area VRGN1a of the game board side display area VRGN1 provided in the built-in VRAM of the sound source built-in VDP 4160a includes the liquid crystal panel 5000e provided in the game board side effect display unit 1900. If it does not match the resolution of (12 inches having an image size of 800×600 dots), the first resolution conversion unit 3420gaa enlarges or reduces the cut game board side drawing data so as to match. After processing, the liquid crystal output board 3420 outputs to the game board side liquid crystal drive circuit 3420h.

In the present embodiment, the light guide plate information and the electric decoration information generated as drawing data in the game board side accompanying information area VRGN1b of the game board side display area VRGN1 provided on the built-in VRAM of the sound source built-in VDP 4160a are buffer memory 3420gb. The second resolution conversion unit 3420gab outputs the cut-out light guide plate information and the electric decoration information as they are to the buffer memory 3420gb without performing the enlarging or reducing process, and thus performs the writing operation.

The buffer memory 3420gb is configured as a double buffer memory composed of a first buffer memory 3420gb1 and a second buffer memory 3420gb2, and one of the first buffer memory 3420gb1 and the second buffer memory 3420gb2 writes data. When operating, the contents already written in the other buffer memory are read from the distribution output control unit 3420gc. The distribution output control unit 3420gc distributes the light guide plate information and the electric decoration information read from the buffer memory to the first serial controller 3420gd1 and the second serial controller 3420gd2 according to a predetermined game board side generation rule. , And distributes the illumination information to the third serial controller 3420gd3 to the eleventh serial controller 3420gd11.

The first serial controller 3420gd1 and the second serial controller 3420gd2 output the light guide plate information to the first light guide plate control circuit 3420k1 to the sixth light guide plate control circuit 3420k6 that configure the various light guide plate control circuits 3420k, and the third serial controller 3420gd1. The controller 3420gd3 to the eleventh serial controller 3420gd11 are the game board side VDP control target decoration LED control circuit 3420i that constitutes the game board side VDP control target decoration LED control circuit 3420i1 to the game board side VDP control target 27th. The decoration information is output to the decoration LED control circuit 3420i27.

More specifically, as shown in FIG. 35, the first serial controller 3420gd1 uses the first light guide plate control circuit 3420k1 and the second light guide plate control circuit 3420k1, which will be described later, based on the clock signal SCLK1 as the light guide plate information as serial data SDAT1. It outputs to the light guide plate control circuit 3420k2 and the third light guide plate control circuit 3420k3. The first light guide plate control circuit 3420k1, the second light guide plate control circuit 3420k2, and the third light guide plate control circuit 3420k3 are electrically connected as one serial connection (one serial system). There is.

As shown in FIG. 35, the second serial controller 3420gd2 uses a light guide plate information as serial data SDAT2 based on the clock signal SCLK2, and a fourth light guide plate control circuit 3420k4, a fifth light guide plate control circuit 3420k5, which will be described later. Output to the sixth light guide plate control circuit 3420k6. The fourth light guide plate control circuit 3420k4, the fifth light guide plate control circuit 3420k5, and the sixth light guide plate control circuit 3420k6 are electrically connected as one serial connection (one serial system). There is.

As shown in FIG. 35, the third serial controller 3420gd3, based on the clock signal SCLK3 as the electric decoration information as the serial data SDAT3, the game board side VDP control target first decorative LED control circuit 3420i1, the game board, which will be described later. Output to the side VDP control target second decoration LED control circuit 3420i2 and the game board side VDP control target third decoration LED control circuit 3420i3. The game board side VDP control target first decoration LED control circuit 3420i1, the game board side VDP control target second decoration LED control circuit 3420i2, the game board side VDP control target third decoration LED control circuit 3420i3 is 1 It has a circuit configuration that is electrically connected as one serial connection (one serial system).

As shown in FIG. 35, the fourth serial controller 3420gd4, based on the clock signal SCLK4 as the electric decoration information as the serial data SDAT4, will be described later, the game board side VDP control target fourth decorative LED control circuit 3420i4, the game board. It outputs to the side VDP control target fifth decoration LED control circuit 3420i5 and the game board side VDP control target sixth decoration LED control circuit 3420i6. The game board side VDP control target fourth decoration LED control circuit 3420i4, the game board side VDP control target fifth decoration LED control circuit 3420i5, the game board side VDP control target sixth decoration LED control circuit 3420i6 is 1 It has a circuit configuration that is electrically connected as one serial connection (one serial system).

As shown in FIG. 35, the fifth serial controller 3420gd5 is a game board side VDP control target seventh decorative LED control circuit 3420i7 and a game board, which will be described later, based on the clock signal SCLK5 as the electric decoration information as serial data SDAT5. It outputs to the side VDP control target eighth decoration LED control circuit 3420i8 and the game board side VDP control target ninth decoration LED control circuit 3420i9. The game board side VDP control target seventh decoration LED control circuit 3420i7, the game board side VDP control target eighth decoration LED control circuit 3420i8, the game board side VDP control target ninth decoration LED control circuit 3420i9 is 1 The circuit is electrically connected as one serial connection (one serial system).

As shown in FIG. 35, the sixth serial controller 3420gd6, based on the clock signal SCLK6 as the electric decoration information as the serial data SDAT6, will be described later on the game board side VDP control target tenth decorative LED control circuit 3420i10 and the game board. It outputs to the side VDP control target eleventh decoration LED control circuit 3420i11 and the game board side VDP control target twelfth decoration LED control circuit 3420i12. The game board side VDP control target tenth decoration LED control circuit 3420i10, the game board side VDP control target eleventh decoration LED control circuit 3420i11, and the game board side VDP control target twelfth decoration LED control circuit 3420i12 are 1 It has a circuit configuration that is electrically connected as one serial connection (one serial system).

As shown in FIG. 35, the seventh serial controller 3420gd7, based on the clock signal SCLK7 as the electric decoration information as the serial data SDAT7, will be described later, the game board side VDP control target thirteenth decorative LED control circuit 3420i13, the game board. It outputs to the side VDP control target fourteenth decoration LED control circuit 3420i14 and the game board side VDP control target fifteenth decoration LED control circuit 3420i15. The game board side VDP control target thirteenth decoration LED control circuit 3420i13, the game board side VDP control target fourteenth decoration LED control circuit 3420i14, and the game board side VDP control target fifteenth decoration LED control circuit 3420i15 are 1 The circuit is electrically connected as one serial connection (one serial system).

As shown in FIG. 35, the eighth serial controller 3420gd8, based on the clock signal SCLK8 as the electric decoration information as the serial data SDAT8, will be described later, the game board side VDP control target sixteenth decorative LED control circuit 3420i16, the game board. It outputs to the side VDP control target 17th decoration LED control circuit 3420i17 and the game board side VDP control target 18th decoration LED control circuit 3420i18. The game board side VDP control target 16th decoration LED control circuit 3420i16, the game board side VDP control target 17th decoration LED control circuit 3420i17, the game board side VDP control target 18th decoration LED control circuit 3420i18 is 1 The circuit is electrically connected as one serial connection (one serial system).

As shown in FIG. 35, the ninth serial controller 3420gd9, based on the clock signal SCLK9 as the electric decoration information as the serial data SDAT9, will be described later on the game board side VDP control target nineteenth decorative LED control circuit 3420i19 and the game board. It outputs to the side VDP control target 20th decoration LED control circuit 3420i20 and the game board side VDP control target 21st decoration LED control circuit 3420i21. The game board side VDP control target 19th decoration LED control circuit 3420i19, the game board side VDP control target 20th decoration LED control circuit 3420i20, and the game board side VDP control target 21st decoration LED control circuit 3420i21 are 1 The circuit is electrically connected as one serial connection (one serial system).

As shown in FIG. 35, the tenth serial controller 3420gd10 is a game board side VDP control target twenty-second decoration LED control circuit 3420i22, a game board, which will be described later, based on the clock signal SCLK10 as the electrical decoration information as serial data SDAT10. It outputs to the side VDP control target 23rd decoration LED control circuit 3420i23 and the game board side VDP control target 24th decoration LED control circuit 3420i24. The game board side VDP control target 22nd decoration LED control circuit 3420i22, the game board side VDP control target 23rd decoration LED control circuit 3420i23, the game board side VDP control target 24th decoration LED control circuit 3420i24 is 1 The circuit is electrically connected as one serial connection (one serial system).

As shown in FIG. 35, the eleventh serial controller 3420gd11, based on the clock signal SCLK11 as the electric decoration information as the serial data SDAT11, will be described later on the game board side VDP control target twenty-fifth decorative LED control circuit 3420i25, the game board. It outputs to the side VDP control target 26th decoration LED control circuit 3420i26 and the game board side VDP control target 27th decoration LED control circuit 3420i27. The game board side VDP control target 25th decoration LED control circuit 3420i25, the game board side VDP control target 26th decoration LED control circuit 3420i26, the game board side VDP control target 27th decoration LED control circuit 3420i27 is 1 The circuit is electrically connected as one serial connection (one serial system).

The game board side VDP control target first decoration LED control circuit 3420i1 to the game board side VDP control target 27th decoration LED control circuit 3420i27 is directly controlled by the sound source built-in VDP 4160a in each of the decoration boards of the game board 4. It is a circuit that can adjust the brightness (grayscale) of a plurality of LEDs (decorative LEDs) provided on each of the plurality of game board side VDP control target decorative substrates that are control targets.

As described above, the drawing data output from the liquid crystal in the peripheral control board 4140 and the channel CH1 of the sound source built-in VDP 4160a of the sound control unit 4160 is displayed (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). Although the light guide plate information and the electric decoration information are added to the game board side drawing data in accordance with the predetermined game board side generation rule, the game board side display area VRGN1 is provided on the VRAM. In this "predetermined game board side generation rule", in the game board side signal separation control circuit 3420g of the liquid crystal output substrate 3420, the first resolution conversion unit 3420gaa of the signal separation unit 3420ga is provided in the built-in VRAM of the sound source built-in VDP 4160a. The game board side drawing data generated in the game board side drawing data area VRGN1a of the game board side display area VRGN1 is configured to be accurately cut out, and the second resolution conversion of the signal separation unit 3420ga is performed. The part 3420gab can accurately cut out the light guide plate information and the electric decoration information generated as drawing data in the game board side accompanying information area VRGN1b of the game board side display area VRGN1 provided on the built-in VRAM of the sound source built-in VDP 4160a. And the distribution output control unit 3420gc is configured to accurately distribute the light guide plate information read from the buffer memory 3420gb to the first serial controller 3420gd1 and the second serial controller 3420gd2, respectively. In addition, the electric decoration information read from the buffer memory 3420gb can be accurately distributed to the corresponding third serial controller 3420gd3 to eleventh serial controller 3420gd11.

Specifically, in the game board side signal separation control circuit 3420g of the liquid crystal output board 3420, the distribution output control unit 3420gc reads the first light guide plate control circuit 3420k1 and the second light guide plate control circuit from the buffer memory 3420gb. 3420k2, and the light guide plate information for the first light guide plate control circuit 3420k1 and the second light guide plate so that the light guide plate information for the third light guide plate control circuit 3420k3 can be accurately distributed to the first serial controller 3420gd1. The light guide plate information for the control circuit 3420k2 and the light guide plate information for the third light guide plate control circuit 3420k3 are attached to the game board side drawing data of the screen drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). It is generated in the game board side accompanying information area VRGN1b of the game board side display area VRGN1 provided on the VRAM.

Also, the distribution output control unit 3420gc outputs the light guide plate information for the fourth light guide plate control circuit 3420k4, the fifth light guide plate control circuit 3420k5, and the sixth light guide plate control circuit 3420k6 read from the buffer memory 3420gb to the second serial controller. The light guide plate information for the fourth light guide plate control circuit 3420k4, the light guide plate information for the fifth light guide plate control circuit 3420k5, and the light guide plate for the sixth light guide plate control circuit 3420k6 so that they can be accurately distributed to 3420gd2. Information related to the game board side of the game board side display area VRGN1 provided on the VRAM as information attached to the game board side drawing data of the screen on which the information is drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e) It is generated in the information area VRGN1b.

Also, the distribution output control unit 3420gc reads the electric decoration information for the game board side VDP control target first decoration LED control circuit 3420i1 to the game board side VDP control target third decoration LED control time 3420i3 read from the buffer memory 3420gb. The illumination information for the gaming board side VDP control target first decoration LED control circuit 3420i1 and the gaming board side VDP control target second decoration LED so that they can be accurately distributed to the corresponding third serial controller 3420gd3. On the screen where the electric decoration information for the control circuit 3420i2 and the electric decoration information for the game board side VDP control target third decorative LED control circuit 3420i3 are drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). It is generated in the game board side accompanying information area VRGN1b of the game board side display area VRGN1 provided on the VRAM as the data added to the game board side drawing data.

Further, the distribution output control unit 3420gc reads the electric decoration information for the game board side VDP control target fourth decoration LED control circuit 3420i4 to the game board side VDP control target sixth decoration LED control time 3420i6 read from the buffer memory 3420gb. Gaming information for the gaming board side VDP control target fourth decoration LED control circuit 3420i4, gaming board side VDP control target fifth decoration LED so that it can be accurately distributed to the corresponding fourth serial controller 3420gd4. On the screen where the electric decoration information for the control circuit 3420i5 and the electric decoration information for the game board side VDP control target sixth decorative LED control circuit 3420i6 are drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). It is generated in the game board side accompanying information area VRGN1b of the game board side display area VRGN1 provided on the VRAM as the data added to the game board side drawing data.

In addition, the distribution output control unit 3420gc reads the electric decoration information for the game board side VDP control target seventh decoration LED control circuit 3420i7 to the game board side VDP control target ninth decoration LED control time 3420i9 read from the buffer memory 3420gb. Gaming information for the gaming board side VDP control target seventh decoration LED control circuit 3420i7, gaming board side VDP control target eighth decoration LED so that the fifth serial controller 3420gd5 can be accurately distributed. On the screen where the electric decoration information for the control circuit 3420i8 and the electric decoration information for the game board side VDP control target ninth decorative LED control circuit 3420i9 are drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). It is generated in the game board side accompanying information area VRGN1b of the game board side display area VRGN1 provided on the VRAM as the data added to the game board side drawing data.

Also, the distribution output control unit 3420gc reads the electric decoration information for the game board side VDP control target tenth decorative LED control circuit 3420i10 to the game board side VDP control target twelfth decorative LED control time 3420i12 read from the buffer memory 3420gb. Gaming information for the gaming board side VDP control target tenth decorative LED control circuit 3420i10, and gaming board side VDP control target eleventh decorative LED so that it can be accurately distributed to the corresponding sixth serial controller 3420gd6. The electric decoration information for the control circuit 3420i11 and the electric decoration information for the game board side VDP control target twelfth decorative LED control circuit 3420i12 are drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). It is generated in the game board side accompanying information area VRGN1b of the game board side display area VRGN1 provided on the VRAM as the data added to the game board side drawing data.

Also, the distribution output control unit 3420gc reads the electric decoration information for the game board side VDP control target thirteenth decoration LED control circuit 3420i13 to the game board side VDP control target fifteenth decoration LED control time 3420i15 read from the buffer memory 3420gb. Gaming information for the gaming board side VDP control target thirteenth decoration LED control circuit 3420i13, and gaming board side VDP control target fourteenth decoration LED so that it can be accurately distributed to the corresponding seventh serial controller 3420gd7. On the screen where the electric decoration information for the control circuit 3420i14 and the electric decoration information for the game board side VDP control target fifteenth decorative LED control circuit 3420i15 are drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). It is generated in the game board side accompanying information area VRGN1b of the game board side display area VRGN1 provided on the VRAM as the data added to the game board side drawing data.

Also, the distribution output control unit 3420gc reads the electric decoration information for the game board side VDP control target sixteenth decorative LED control circuit 3420i16 to the game board side VDP control target eighteenth decorative LED control time 3420i18 read from the buffer memory 3420gb. Lighting distribution information for the gaming board side VDP control target 16th decoration LED control circuit 3420i16, 17th decoration LED for the game board side VDP control target so that it can be accurately distributed to the corresponding eighth serial controller 3420gd8. On the screen where the electric decoration information for the control circuit 3420i17 and the electric decoration information for the game board side VDP control target eighteenth LED control circuit 3420i18 are drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). It is generated in the game board side accompanying information area VRGN1b of the game board side display area VRGN1 provided on the VRAM as the data added to the game board side drawing data.

Further, the distribution output control unit 3420gc reads the electric decoration information for the game board side VDP control target 19th decorative LED control circuit 3420i19 to the game board side VDP control target 21st decorative LED control time 3420i21 read from the buffer memory 3420gb. The illumination information for the gaming board side VDP control target 19th decoration LED control circuit 3420i19, and the gaming board side VDP control target 20th decoration LED so that it can be accurately distributed to the corresponding ninth serial controller 3420gd9. On the screen where the electric decoration information for the control circuit 3420i20 and the electric decoration information for the game board side VDP control target 21st decorative LED control circuit 3420i21 are drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). It is generated in the game board side accompanying information area VRGN1b of the game board side display area VRGN1 provided on the VRAM as the data added to the game board side drawing data.

Further, the distribution output control unit 3420gc reads the electric decoration information for the game board side VDP control target 22nd decoration LED control circuit 3420i22 to the game board side VDP control target 24th decoration LED control time 3420i24 read from the buffer memory 3420gb. The illumination information for the gaming board side VDP control target 22nd decoration LED control circuit 3420i22, and the gaming board side VDP control target 23rd decoration LED so that it can be accurately distributed to the corresponding 10th serial controller 3420gd10. The electric decoration information for the control circuit 3420i23 and the electric decoration information for the game board side VDP control target 24th decorative LED control circuit 3420i24 are drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). It is generated in the game board side accompanying information area VRGN1b of the game board side display area VRGN1 provided on the VRAM as the data added to the game board side drawing data.

Further, the distribution output control unit 3420gc reads the electric decoration information for the game board side VDP control target 25th decorative LED control circuit 3420i25 to the game board side VDP control target 27th decorative LED control time 3420i27 read from the buffer memory 3420gb. The illumination information for the gaming board side VDP control target 25th decorative LED control circuit 3420i25, and the gaming board side VDP control target 26th decorative LED so that it can be accurately distributed to the corresponding 11th serial controller 3420gd11. The electric decoration information for the control circuit 3420i26 and the electric decoration information for the game board side VDP control target 27th decorative LED control circuit 3420i27 are drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). It is generated in the game board side accompanying information area VRGN1b of the game board side display area VRGN1 provided on the VRAM as the data added to the game board side drawing data.

As described above, the drawing data output from the liquid crystal in the peripheral control board 4140 and the channel CH1 of the sound source built-in VDP 4160a of the sound control unit 4160 is displayed (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). First, by generating in the game board side display area VRGN1 provided in the built-in VRAM, the light guide plate information and the electric decoration information are added to the game board side drawing data according to a predetermined game board side generation rule. The serial controller 3420gd1 outputs the light guide plate information as serial data SDAT1 to the first light guide plate control circuit 3420k1, the second light guide plate control circuit 3420k2, and the third light guide plate control circuit 3420k3 based on the clock signal SCLK1. The second serial controller 3420gd2 outputs the light guide plate information as serial data SDAT2 to the fourth light guide plate control circuit 3420k4, the fifth light guide plate control circuit 3420k5, and the sixth light guide plate control circuit 3420k6 based on the clock signal SCLK2. By outputting, a plurality of LEDs mounted on the LED boards respectively arranged on the upper side and the lower side of the plurality of light guide plates included in the game board side effect display unit 1900 are driven. By the control by this driving, the brightness of the LEDs mounted on the LED board in a plurality of rows is adjusted.

The third serial controller 3420gd3 to the eleventh serial controller 3420gd11 use the decoration information as the serial data SDAT3 to serial data SDAT11, based on the clock signals SCLK3 to SCLK11, for the game board side VDP control target first decoration. LED control circuit 3420i1 to VDP control target on the game board side By outputting to the 27th decorative LED control circuit 3420i27, a plurality of control targets directly controlled by the sound source built-in VDP 4160a of each decorative board of the game board 4 are output. The plurality of LEDs (decorative LEDs) provided on each of the game board side VDP control target decorative substrates are driven. The brightness (gradation) of the decorative LED is adjusted by the control by this driving.

In addition, the first serial controller 3420gd1 to the eleventh serial controller 3420gd11 select a common mode in which the respective output timings can be the same timing and an individual mode in which the respective output timings can be different timings. You can do it. When the output timing of the first serial controller 3420gd1 to the eleventh serial controller 3420gd11 is set to the common mode in which the output timing is the same, the output from the first serial controller 3420gd1 to the eleventh serial controller 3420gd11 causes an extremely short period of time to be controlled. There may be a case where even if a large current flows as an inrush current, the current is insufficient and an instantaneous blackout does not occur. On the other hand, when the output modes of the first serial controller 3420gd1 to the eleventh serial controller 3420gd11 are set to the individual mode in which the output timings are different from each other, the output is controlled by the first serial controller 3420gd1 to the eleventh serial controller 3420gd11. If a large current flows as an inrush current to the target in an extremely short period of time, there is a risk of power shortage and an instantaneous blackout may occur.

In the present embodiment, the individual modes in which the output timings of the first serial controller 3420gd1 to the eleventh serial controller 3420gd11 are set to different timings are set. When the game board 4 is mounted on a dedicated frame (outer frame 2, main body frame 3, and door frame 5) that expresses the world view expressed by the effect, it is provided on the game board 4 or the dedicated frame side. A power supply board 851 of the board unit 800 attached to the main body frame 3 so as to be commensurate with the electric power supplied to an electric drive source such as a plurality of LEDs (decorative LEDs) and a plurality of movable bodies for operating a movable body. The power generation circuit is designed so that a sufficient power supply will not occur even if a plurality of LEDs (ornamental LEDs) are turned on and the movable body is activated by an electric drive source such as a motor or solenoid. Has capacity.

However, the game board mounted on the main body frame 3 of the outer frame 2 already installed in the hall (a game board of another model different from the game board 4 (for example, the world view expressed by the production is different, LED (decorative) The number of LEDs), the presence or absence of movable bodies operated by an electric drive source such as a motor or a solenoid, and the number thereof are different.) Therefore, if the game board 4 is simply replaced, a plurality of LEDs ( If the movable body starts to operate due to the lighting of the decorative LED) or the electric drive source such as a motor or a solenoid, a momentary power failure may occur.

Therefore, in the present embodiment, by setting the output timings of the first serial controller 3420gd1 to the eleventh serial controller 3420gd11 to different timings, the output is controlled by the first serial controller 3420gd1 to the eleventh serial controller 3420gd11. It is possible to prevent the occurrence of an instantaneous power failure due to power shortage due to a large current flowing as an inrush current for an extremely short period of time with respect to the target. There is no need to bother to provide it. This makes it possible to suppress the load on the power supply board 851 of the board unit 800 attached to the main body frame 3 of the outer frame 2 already installed in the hole, which is different from the above-described dedicated frame.

Since the liquid crystal in the peripheral control board 4140 and the sound source built-in VDP 4160a of the sound control unit 4160 are set to the frame frequency of 30 fps as described above (about every 33.3 ms), they are generated in the built-in VRAM. Since the drawing data is output from the channels CH1 and CH2, the drawing data output from the channel CH1 of the VDP4160a with a built-in sound source is also input to the game board side signal separation control circuit 3420g of the liquid crystal output substrate 3420 about every 33.3 ms. The Rukoto. Therefore, a screen (effect image) drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e) separated by the first resolution conversion unit 3420gaa of the signal separation unit 3420ga in the game board side signal separation control circuit 3420g. ) Of the game board side drawing data is output to the game board side effect display unit 1900 (liquid crystal panel 5000e) through the game board side liquid crystal drive circuit 3420h every about 33.3 ms, and the game board side signal separation control circuit is output. The light guide plate information and the electric decoration information separated by the second resolution conversion unit 3420gab of the signal separation unit 3420g in 3420g are serial data SDAT1 to serial data SDAT11 from the first serial controller 3420gd1 to eleventh serial controller 3420gd11 and clock signals SCLK1 to SCLK11. Based on the above, all are output every about 33.3 ms, so that it is possible to realize synchronization of effects by a plurality of control targets respectively output from the first serial controller 3420gd1 to the eleventh serial controller 3420gd11, and at the same time, Since it is possible to prevent the deviation in the production of the effects by the plurality of control targets, it is possible to suppress the decrease in the interest.

[12-2. Configuration of various light guide plate control circuits and LED control circuits for VDP control target decoration on the game board side]
Next, the configurations of the various light guide plate control circuits and the LED control circuit for the game board side VDP control target decoration will be described. The liquid crystal output substrate 3420 is, as various light guide plate control circuits, a first light guide plate control circuit 3420k1 capable of dimming and turning on light emitted by the first light guide plate 5000d provided in the game board side effect display unit 1900, and a game board. Second light guide plate control circuit 3420k2 capable of dimming and lighting the light emitted by the second light guide plate 5000f included in the side effect display unit 1900, and light emission by the third light guide plate 5000g included in the game board side effect display unit 1900. A third light guide plate control circuit 3420k3 capable of dimming and lighting, and a fourth light guide plate control circuit capable of dimming and lighting the light emitted by the fourth light guide plate 5000h provided in the game board side effect display unit 1900. 3420k4, a fifth light guide plate control circuit 3420k5 capable of dimming and turning on light emitted by the fifth light guide plate 5000i included in the game board side effect display unit 1900, and a sixth light guide plate control circuit 3420 included in the game board side effect display unit 1900. And a sixth light guide plate control circuit 3420k6 capable of dimming and lighting the light emitted by the light guide plate 5000k.

In addition, the liquid crystal output board 3420 serves as a game board side VDP control target decoration LED control circuit 3420i, and among the decoration boards of the game board 4, a plurality of game board sides that are control targets directly controlled by the sound source built-in VDP 4160a. VDP control target VDP control target for game board side VDP control target capable of dimming light emission by a plurality of LEDs (ornamental LEDs) provided on each decorative substrate 1st LED control circuit for decoration 3420i1 VDP control target for game board side The twenty-seventh decorative LED control circuit 3420i27 (27 circuits in total) is provided.

In the present embodiment, in the game board side effect display unit 1900, the high-luminance LEDs 5000d6 and the second light guide plate mounted on the light guide plate upper decoration substrate 5000d1 and the light guide plate lower decoration substrate 5000d2 of the first light guide plate 5000d, respectively. High-luminance LED 5000f6 mounted on the light guide plate upper decorative substrate 5000f1 and the light guide plate lower decorative substrate 5000f2 of 5000f, respectively, and mounted on the light guide plate upper decorative substrate 5000d1 and the light guide lower decorative substrate 5000d2 of the third light guide plate 5000g, respectively. High-brightness LED 5000g6, high-brightness LED 5000h6 mounted on the light guide plate upper decorative substrate 5000h1 and the light guide plate lower decorative substrate 5000h2 of the fourth light guide plate 5000h, respectively, and a light guide plate upper decorative substrate of the fifth light guide plate 5000i. High brightness LED 5000i6 mounted on 5000i1 and light guide plate lower decorative substrate 5000i2 respectively, and high brightness LED 5000k6 mounted on light guide plate upper decorative substrate 5000k1 and light guide plate lower decorative substrate 5000k2 of sixth light guide plate 5000k, etc. The light guide plate LEDs are managed by being divided into a plurality of groups.

The first light guide plate control circuit 3420k1 can dimming the light emitted from the first light guide plate 5000d by an LED 5000d6, and the second light guide plate control circuit 3420k2 can dimming the light emitted by the second light guide plate 5000f. The LED 5000f6 capable of performing light control and the LED 5000g6 capable of dimming the light emitted by the third light guide plate 5000g by the third light guide plate control circuit 3420k3 are managed as a first group for light guide plates. Further, an LED 5000h6 capable of dimming and lighting the light emitted by the fourth light guide plate 5000h by the fourth light guide plate control circuit 3420k4, and a dimming lighting of light emission by the fifth light guide plate 5000i by the fifth light guide plate control circuit 3420k5. The LED 5000i6 that can be turned on and the LED 5000k6 that can dimming the light emitted by the sixth light guide plate 5000k by the sixth light guide plate control circuit 3420k6 are managed as a second group for the light guide plate.

Further, in the present embodiment, what is dimmed by the game board side VDP control target first decoration LED control circuit 3420i1 to the game board side VDP control target third decoration LED control circuit 3420i3 is the game board side decoration. It is managed as the first group for use. Also, what is dimmed by the game board side VDP control target fourth decoration LED control circuit 3420i4 to the game board side VDP control target sixth decoration LED control circuit 3420i6 is the game board side decoration second group. It is managed. In addition, what is dimmed by the game board side VDP control target seventh decoration LED control circuit 3420i7 to the game board side VDP control target ninth decoration LED control circuit 3420i9 is the game board side decoration third group. It is managed. Also, the 10th decoration LED control circuit 3420i10 for VDP control on the game board side and the 12th decoration LED control circuit 3420i12 for VDP control on the game board side are those that are dimmed and turned on as the fourth decoration group for the game board. It is managed.

In addition, what is dimmed and turned on by the game board side VDP control target thirteenth decoration LED control circuit 3420i13 to the game board side VDP control target fifteenth decoration LED control circuit 3420i15 is the game board side decoration fifth group. It is managed. Further, the 16th decorative LED control circuit 3420i16 for the VDP control target on the game board side to the 18th decorative LED control circuit 3420i18 for the VDP control target on the game board side is the sixth control group for the decorative decoration on the game board side. It is managed. In addition, the game board side VDP control target 19th decoration LED control circuit 3420i19 to the game board side VDP control target 21st decoration LED control circuit 3420i21 is dimmed and turned on as the game board side decoration 7th group. It is managed. Also, what is dimmed by the game board side VDP control target 22nd decoration LED control circuit 3420i22 to the game board side VDP control target 24th decoration LED control circuit 3420i24 is the game board side decoration 8th group. It is managed. In addition, what is dimmed by the game board side VDP control target 25th decoration LED control circuit 3420i25 to the game board side VDP control target 27th decoration LED control circuit 3420i27 is the game board side decoration 9th group. It is managed.

As the power source for the first light guide plate control circuit 3420k1, the liquid crystal output substrate 3420 is dedicated to the first light guide plate power source (+12V) from the first light guide plate power source circuit of the game board side various light guide plate power source circuit 3420e. The second light guide plate power supply (+12V) is supplied as a power supply to the second light guide plate control circuit 3420k2 from the second light guide plate power supply circuit of the game board side light guide plate power supply circuit 3420e. As a power source for the third light guide plate control circuit 3420k3, a third light guide plate power source (+12V) is exclusively supplied from the third light guide plate power source circuit of the game board side light guide plate power source circuit 3420e, and a fourth power source. As a power source for the light guide plate control circuit 3420k4, the fourth light guide plate power source (+12V) is exclusively supplied from the fourth light guide plate power source circuit of the game board side light guide plate power source circuit 3420e, and the fifth light guide plate control is performed. As a power supply for the circuit 3420k5, a fifth light guide plate power supply (+12V) is exclusively supplied from the fifth light guide plate power supply circuit of the game board side various light guide plate power supply circuits 3420e, and to the sixth light guide plate control circuit 3420k6. As the power source, the sixth light guide plate power source (+12V) is exclusively supplied from the sixth light guide plate power source circuit of the game board side various light guide plate power source circuits 3420e.

In addition to its own control power source, the liquid crystal output substrate 3420 serves as a power source for the game board side VDP control target first decoration LED control circuit 3420i1 to the game board side VDP control target 27th decoration LED control circuit 3420i27. The illumination power supply (+5V) is supplied from the power supply board 851 through the frame peripheral relay terminal board 868, the peripheral door frame relay terminal board 882, and the peripheral control board 4140.

The first light guide plate control circuit 3420k1 mainly includes an LED driver IC 4810, a first light guide plate PWM (Pulse Width Modulation) control circuit 4950, peripheral circuits, and the like. The second light guide plate control circuit 3420k2 mainly includes an LED driver IC 4830, a second light guide plate PWM control circuit 4960, peripheral circuits, and the like. The third light guide plate control circuit 3420k3 mainly includes an LED driver IC 4850, a third light guide plate PWM control circuit 4970, peripheral circuits, and the like. The fourth light guide plate control circuit 3420k5 mainly includes an LED driver IC 4815, a fourth light guide plate PWM control circuit 4955, peripheral circuits, and the like. The fifth light guide plate control circuit 3420k5 mainly includes an LED driver IC 4835, a fifth light guide plate PWM control circuit 4965, peripheral circuits, and the like. The sixth light guide plate control circuit 3420k6 mainly includes an LED driver IC 4855, a sixth light guide plate PWM control circuit 4975, peripheral circuits, and the like.

The LED driver IC 4810 of the first light guide plate control circuit 3420k1 is based on the first light guide plate PWM signal from the first light guide plate PWM control circuit 4950 of the first light guide plate control circuit 3420k1. The light emission by 5000d is turned off, and the brightness range from low brightness (minimum brightness) to high brightness (maximum brightness) can be adjusted by 1% at a time, and the brightness is adjusted to one of the brightness ranges. It can be illuminated. The first PWM signal for light guide plate includes a light guide plate upper decorative substrate 5000d1 provided on the upper end surface of the first light guide plate 5000d, a light guide plate lower decorative substrate 5000d2 provided on the lower end surface of the first light guide plate 5000d, It is possible to instruct the light emission of a plurality of LEDs 5000d6 mounted in each. As described above, the LED driver IC 4810 can finely adjust the brightness of the LED 5000d6, and thus can finely control the dimming of the first light guide plate 5000d.

The LED driver IC 4830 of the second light guide plate control circuit 3420k2 receives the second light guide plate PWM signal from the second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2. The light emission by 5000f is turned off, and the brightness range from low brightness (minimum brightness) to high brightness (maximum brightness) can be adjusted by 1%, and the brightness is adjusted to one of the brightness ranges. It can be illuminated. The second PWM signal for light guide plate includes a light guide plate upper decoration substrate 5000f1 provided on the upper end surface of the second light guide plate 5000f, a light guide plate lower decoration substrate 5000f2 provided on the lower end surface of the second light guide plate 5000f, It is possible to instruct the light emission of the LEDs 5000f6 that are respectively mounted in the plurality. As described above, the LED driver IC 4830 is capable of finely adjusting the brightness of the LED 5000f6, and thus can finely control the dimming lighting of the second light guide plate 5000f.

The LED driver IC 4850 of the third light guide plate control circuit 3420k3 uses the third light guide plate PWM signal from the third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3. The light emission by 5000g is turned off, and the brightness range from low brightness (minimum brightness) to high brightness (maximum brightness) can be adjusted by 1% at a time, and the brightness is adjusted to one of the brightness ranges. It can be illuminated. The third PWM signal for light guide plate includes a light guide plate upper decorative substrate 5000g1 provided on the upper end surface of the third light guide plate 5000g, a light guide plate lower decorative substrate 5000g2 provided on the lower end surface of the third light guide plate 5000g, It is possible to instruct the light emission of the LEDs 5000g6, which are respectively mounted in a plurality. As described above, the LED driver IC 4850 can finely adjust the brightness of the LED 5000g6, and thus can finely control the dimming lighting of the third light guide plate 5000g.

The LED driver IC 4815 of the fourth light guide plate control circuit 3420k4 uses the fourth light guide plate PWM signal from the fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4. The light emission by 5000h is turned off, and the brightness range from low brightness (minimum brightness) to high brightness (maximum brightness) can be adjusted by 1% at a time, and the brightness is adjusted to one of the brightness ranges. It can be illuminated. The fourth PWM signal for the light guide plate includes a light guide plate upper decorative substrate 5000h1 provided on the upper end surface of the fourth light guide plate 5000h, a light guide plate lower decorative substrate 5000h2 provided on the lower end surface of the fourth light guide plate 5000h, and It is possible to instruct the light emission of the LEDs 5000h6 that are respectively mounted in the plurality. As described above, the LED driver IC 4815 is capable of finely adjusting the brightness of the LED 5000h6, and thus can finely control the fourth light guide plate 5000h such as dimming lighting.

The LED driver IC 4835 of the fifth light guide plate control circuit 3420k5 is based on the fifth light guide plate PWM signal from the fifth light guide plate PWM control circuit 4965 of the fifth light guide plate control circuit 3420k5. The 5000i emission is turned off, and the brightness range from low brightness (minimum brightness) to high brightness (maximum brightness) can be adjusted in 1% increments, and the brightness is adjusted to one of the brightness ranges. It can be illuminated. The fifth PWM signal for the light guide plate includes a light guide plate upper decorative substrate 5000i1 provided on the upper end surface of the fifth light guide plate 5000i, a light guide plate lower decorative substrate 5000i2 provided on the lower end surface of the fifth light guide plate 5000i, It is possible to instruct the emission of a plurality of LEDs 5000i6 mounted in each. As described above, the LED driver IC 4835 is capable of finely adjusting the brightness of the LED 5000i6, and thus can finely control the dimming lighting of the fifth light guide plate 5000i.

The LED driver IC 4855 of the sixth light guide plate control circuit 3420k6 operates based on the sixth light guide plate PWM signal from the sixth light guide plate PWM control circuit 4975 of the sixth light guide plate control circuit 3420k6. The light emission by 5000k is turned off, and the brightness range from low brightness (minimum brightness) to high brightness (maximum brightness) can be adjusted by 1% at a time, and the brightness is adjusted to one of the brightness ranges. It can be illuminated. The sixth PWM signal for light guide plate includes a light guide plate upper decorative substrate 5000k1 provided on the upper end surface of the sixth light guide plate 5000k, a light guide plate lower decorative substrate 5000k2 provided on the lower end surface of the sixth light guide plate 5000k, It is possible to instruct the emission of a plurality of LEDs 5000k6 mounted in each. As described above, the LED driver IC 4855 can finely adjust the brightness of the LEDs 5000k6, and thus can finely control the sixth light guide plate 5000k such as dimming lighting.

The game board side VDP control target first decoration LED control circuit 3420i1 to the game board side VDP control target twenty-seventh decoration LED control circuit 3420i27 are respectively configured from the same decoration LED driver IC. The decoration LED driver IC includes a plurality of LEDs (decoration) provided on each of the plurality of game board side VDP control target decoration boards, which are control objects to be directly controlled by the sound source built-in VDP 4160a, among the respective decoration boards of the game board 4. It is possible to individually control the light emission of each LED) from off to high brightness (maximum brightness) in a total of 128 steps from gradation 0 (zero) to gradation 127, and gradation 0 (zero). The display is turned off at, and the brightness can be adjusted to the maximum brightness at the gradation 127. Thus, the game board side VDP control target first decoration LED control circuit 3420i1 to the game board side VDP control target twenty-seventh decoration LED control circuit 3420i27 can individually finely adjust the brightness of the decoration LEDs. Therefore, it is possible to perform fine control such as dimming lighting of the decorative LED.

The peripheral control MPU 4150a of the peripheral control unit 4150 on the peripheral control board 4140 controls the sound source built-in VDP 4160a of the liquid crystal and sound control unit 4160. The sound source built-in VDP 4160a is a control target which is directly controlled by the sound source built-in VDP 4160a of each decorative board of the game board 4 and screen data which defines the configuration of the screen drawn on the game board side effect display unit 1900 (liquid crystal panel 5000e). When the peripheral control MPU 4150a inputs the light emission data that defines the light emission mode of the plurality of LEDs (decorative LEDs) provided on each of the plurality of game board side VDP control target decoration substrates, the above-mentioned pre-processing According to the determined game board side generation rule, based on the input screen data, the game board side character data for drawing in the display area of the game board side effect display unit 1900 is extracted from the liquid crystal and sound control ROM 4160b, and sprite is extracted. Data is created and game board side drawing data is generated in the game board side drawing data area VRGN1a of the game board side display area VRGN1 provided on the built-in VRAM, and liquid crystal and liquid crystal are generated based on the input light emission data. From the sound control ROM 4160b to each of the decorative boards of the game board 4, a plurality of LEDs (ornamental LEDs) provided on each of the plurality of game board-side VDP controlled decoration boards that are directly controlled by the sound source built-in VDP 4160a. The game board side for setting the light emitting mode of the game board side of the game board side display area VRGN1 provided on the built-in VRAM by extracting the light emitting mode setting image data as drawing data to be described later and drawing information. It is generated in the accompanying information area VRGN1b. Then, the sound source built-in VDP 4160a outputs the drawing data generated from the channel CH1 to the game board side display area VRGN1 to the liquid crystal output substrate 3420 by the LVDS method.

As described above, the drawing data output from the channel CH1 of the sound source built-in VDP 4160a is a parallel signal (that is, the channel CH1 of the sound source built-in VDP 4160a channel) based on the signal transmitted by the RGB conversion circuit 3420f of the liquid crystal output substrate 3420. Drawing data output from the three video signals of a red video signal, a green video signal, and a blue video signal, and three sync signals of a horizontal sync signal, a vertical sync signal, and a clock signal. Then, the signal is input to the signal separation unit 3420ga in the game board side signal separation control circuit 3420g of the liquid crystal output substrate 3420. The signal separation unit 3420ga converts the drawing data converted into the parallel signal into the game board side drawing data for the game board side effect display unit 1900 (the liquid crystal panel 5000e) in the first resolution conversion unit 3420gaa and the second resolution conversion unit 3420gab. The light guide plate information and the electric decoration information are separated. The first resolution conversion unit 3420gaa draws game board side drawing data for the separated game board side effect display unit 1900 (liquid crystal panel 5000e) through the game board side liquid crystal drive circuit 3420h of the liquid crystal output board 3420 to the game board side. Output to the effect display unit 1900 (liquid crystal panel 5000e), the second resolution conversion unit 3420gab outputs the separated light guide plate information and electrical decoration information to the buffer memory 3420gb in the game board side signal separation control circuit 3420g to perform the writing operation. To do.

The distribution output control unit 3420gc in the game board side signal separation control circuit 3420g uses the light guide plate information and the electric decoration information read from the buffer memory 3420gb as the first serial light guide plate information according to the above-described predetermined game board side generation rule. It is distributed to the controller 3420gd1 and the second serial controller 3420gd2, and the illumination information is distributed to the third serial controller 3420gd3 to the eleventh serial controller 3420gd11. As described above, the first serial controller 3420gd1 and the second serial controller 3420gd2 use the first light guide plate control circuit 3420k1 to the sixth light guide plate control circuit 3420k1 as the serial data SDAT1 and SDAT2 based on the clock signals SCLK1 and SCLK2. Output to the light plate control circuit 3420k6. As described above, the third serial controller 3420gd3 to the eleventh serial controller 3420gd11 use the decoration information as the serial data SDAT3 to the serial data SDAT11 based on the clock signals SCLK3 to SCLK11 to determine the brightness (gradation) of the decoration LED. ) Can be adjusted to the game board side VDP control target first decoration LED control circuit 3420i1 to the game board side VDP control target 27th decoration LED control circuit 3420i27.

The serial data SDAT1 and the clock signal SCLK1 from the first serial controller 3420gd1 are output from the first light guide plate PWM control circuit 4950 of the first light guide plate control circuit 3420k1 and the second light guide plate control circuit 3420k2 as described above. A circuit in which the second light guide plate PWM control circuit 4960 and the third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3 are electrically connected as one serial connection (one serial system). It is composed. In addition, as described above, the serial data SDAT2 and the clock signal SCLK2 from the second serial controller 3420gd2 are the fourth light guide plate PWM control circuit 4955 and the fifth light guide plate control circuit of the fourth light guide plate control circuit 3420k4. The fifth light guide plate PWM control circuit 4965 of 3420k5 and the sixth light guide plate PWM control circuit 4975 of the sixth light guide plate control circuit 3420k6 are electrically connected as one serial connection (one serial system). It has a circuit configuration. As described above, the third serial controller 3420gd3 to the eleventh serial controller 3420gd11 are also electrically connected as one serial connection (one serial system).

By adopting such a method of making one serial connection respectively, for example, the first light guide plate PWM signal, the second light guide plate PWM signal, and the third light guide plate PWM signal from the peripheral control board 4140. In the liquid crystal output substrate 3420, the LED driver IC 4810 of the first light guide plate control circuit 3420k1, the LED driver IC 4830 of the second light guide plate control circuit 3420k2, the LED driver IC 4850 of the third light guide plate control circuit 3420k3, and the fourth driver. The parallel connection for outputting to the LED driver IC 4815 of the light plate control circuit 3420k4, the LED driver IC 4835 of the fifth light guide plate control circuit 3420k5, and the LED driver IC 4855 of the sixth light guide plate control circuit 3420k6, and the above-mentioned decoration Since the LEDs are individually dimmed and turned on, the number of wires can be significantly reduced as compared with the method of parallel connection in which control signals are individually output from the peripheral control board 4140 to the decorative LEDs individually. Therefore, the degree of freedom in routing the wiring can be increased. In addition, in the method using one serial connection, it is easy to cope with the external noise from entering the wiring by reducing the number of wires, and the influence of the external noise can be reduced compared to the method using the parallel connection. Can be suppressed.

The first light guide plate PWM control circuit 4950 of the first light guide plate control circuit 3420k1, the second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2, and the third light guide plate control circuit 3420k3 of the third light guide plate control circuit 3420k3. 3 light guide plate PWM control circuit 4970, fourth light guide plate control circuit 3420k4 fourth light guide plate PWM control circuit 4955, fifth light guide plate control circuit 3420k5 fifth light guide plate PWM control circuit 4965, The sixth light guide plate PWM control circuit 4975 of the sixth light guide plate control circuit 3420k6 has an ID setting circuit (for example, one of a plurality of ID setting terminals among the plurality of ID setting terminals) that does not show an ID that can identify each individual. By electrically connecting the ID setting terminal of (1) to the control power supply side (DC power supply, +5V) (or electrically connecting with a pull-up resistor), and grounding the other ID setting terminal to the ground (GND) side. , ID can be set without duplication.) Further, in the game board side VDP control target first decoration LED control circuit 3420i1 to the game board side VDP control target twenty-seventh decoration LED control circuit 3420i27, an ID for identifying each individual is set later. It is set by each department without duplication.

Accordingly, the first light guide plate PWM control circuit 4950 of the first light guide plate control circuit 3420k1, the second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2, and the third light guide plate control circuit. A third light guide plate PWM control circuit 4970 of 3420k3, a fourth light guide plate PWM control circuit 4955 of a fourth light guide plate control circuit 3420k4, and a fifth light guide plate PWM control circuit of a fifth light guide plate control circuit 3420k5. 4965, the sixth light guide plate PWM control circuit 4975 of the sixth light guide plate control circuit 3420k6, the game board side VDP control target first decoration LED control circuit 3420i1 to the game board side VDP control target 27th decoration The LED control circuit 3420i27 and the ID can be set in advance without overlapping.

The serial data SDAT1 to serial data SDAT11 from the first serial controller 3420gd1 to the eleventh serial controller 3420gd11 in the game board side signal separation control circuit 3420g convey the light guide plate information and the electric decoration information as described above. Here, the light guide plate information and the electric decoration information will be described.

The “light guide plate information” designates one of the plurality of light guide plates included in the game board side effect display unit 1900 that uses the light guide plate as a backlight (in other words, provided in the game board side effect display unit 1900). It is information for selecting (switching) one light guide plate among a plurality of light guide plates, and is composed of light guide plate designation information and luminance information. The light guide plate designation information includes the first light guide plate PWM control circuit 4950 of the first light guide plate control circuit 3420k1, the second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2, and the third light guide plate control. Third light guide plate PWM control circuit 4970 of circuit 3420k3, fourth light guide plate PWM control circuit 4955 of fourth light guide plate control circuit 3420k4, fifth light guide plate PWM control circuit 4965 of fifth light guide plate control circuit 3420k5. , And information indicating which of the sixth light guide plate PWM control circuits 4975 of the sixth light guide plate control circuit 3420k6 is to be designated, and the above-mentioned ID is set. is there. The brightness information is information indicating which brightness is to be specified in the brightness range from low brightness (minimum brightness) to high brightness (maximum brightness), and the brightness can be set in units of 1%. it can.

The "illumination information" is information for designating the light emission mode, and is composed of electrical LED designation information and gradation information. The illumination LED designation information is any game board side VDP control target decoration among the game board side VDP control target first decoration LED control circuit 3420i1 to game board side VDP control target 27th decoration LED control circuit 3420i27. It is information indicating whether or not the LED control circuit for use is designated, and the above-mentioned ID is set. The gradation information is information indicating which of the gradation 0 (zero) to the gradation 127 is to be specified.

The liquid crystal output substrate 3420 includes the luminance of light emitted by the first light guide plate 5000d, the luminance of light emitted by the second light guide plate 5000f, the luminance of light emitted by the third light guide plate 5000g, and the fourth luminance in the game board side effect display unit 1900. The integrated brightness setting switch 4880 is provided to collectively set the brightness of light emitted by the light guide plate 5000h, the brightness of light emitted by the fifth light guide plate 5000i, and the brightness of light emitted by the sixth light guide plate 5000k. A signal for the brightness integrated setting from the brightness integrated setting switch 4880 is the first light guide plate PWM control circuit 4950 of the first light guide plate control circuit 3420k1, and the second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2. , A third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3, a fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4, and a fifth of the fifth light guide plate control circuit 3420k5. To the sixth light guide plate PWM control circuit 4965 of the sixth light guide plate control circuit 3420k6.

Since the liquid crystal output substrate 3420 is arranged on the back surface side of the game board 4 as described above, a clerk such as a store clerk in the hall closes the main body frame 3 with respect to the outer frame 2 installed in the hall. The brightness overall setting switch 4880 can be operated by opening the switch from the above.

When the brightness integrated setting switch 4880 is operated to the setting A by rotating operation (100% setting), the brightness in the serial data SDAT1 from the first serial controller 3420gd1 in the game board side signal separation control circuit 3420g. The brightness set in the information can be set to be used as it is, and to that effect, the first light guide plate PWM control circuit 4950 and the second light guide plate of the first light guide plate control circuit 3420k1 can be used as a signal for the brightness integrated setting. It is input to the second light guide plate PWM control circuit 4960 of the control circuit 3420k2 and the third light guide plate PWM control circuit 497 of the third light guide plate control circuit 3420k3, respectively, and at the same time in the game board side signal separation control circuit 3420g. 2 The brightness set in the brightness information in the serial data SDAT2 from the serial controller 3420gd2 can be set to be used as it is, and that effect is used as a signal for the brightness integrated setting by the fourth guide of the fourth light guide plate control circuit 3420k4. The light is inputted to the light plate PWM control circuit 4955, the fifth light guide plate PWM control circuit 4965 of the fifth light guide plate control circuit 3420k5, and the sixth light guide plate PWM control circuit 4975 of the sixth light guide plate control circuit 3420k6.

When the brightness integrated setting switch 4880 is rotated to the setting B (85% setting), the brightness in the serial data SDAT1 from the first serial controller 3420gd1 in the game board side signal separation control circuit 3420g. The first light guide plate of the first light guide plate control circuit 3420k1 can be set to be used by forcibly setting the brightness to 85% of the brightness set in the information. While being input to the PWM control circuit 4950, the second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2, and the third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3, respectively, It is possible to forcibly set the luminance to 85% of the luminance set in the luminance information in the serial data SDAT2 from the second serial controller 3420gd2 in the game board side signal separation control circuit 3420g, and to that effect. As a signal of the brightness integrated setting, the fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4, the fifth light guide plate PWM control circuit 4965 of the fifth light guide plate control circuit 3420k5, and the sixth light guide plate PWM control circuit 4965. It is input to the sixth light guide plate PWM control circuit 4975 of the light plate control circuit 3420k6.

When the brightness integrated setting switch 4880 is rotated to the setting C (70% setting), the brightness in the serial data SDAT1 from the first serial controller 3420gd1 in the game board side signal separation control circuit 3420g. The setting can be performed by forcibly setting the brightness to 70% of the brightness set in the information, and that effect can be used as a signal of the brightness integrated setting by the first light guide plate of the first light guide plate control circuit 3420k1. While being input to the PWM control circuit 4950, the second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2, and the third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3, respectively, The brightness can be set to 70% of the brightness set in the brightness information in the serial data SDAT2 from the second serial controller 3420gd2 in the game board side signal separation control circuit 3420g, and can be set to be used. As a signal for the brightness integrated setting, the fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4, the fifth light guide plate PWM control circuit 4965 of the fifth light guide plate control circuit 3420k5, and the sixth light guide plate PWM control circuit 4965. It is input to the sixth light guide plate PWM control circuit 4975 of the light plate control circuit 3420k6.

When the first light guide plate PWM control circuit 4950 of the first light guide plate control circuit 3420k1 receives the serial data SDAT1 from the first serial controller 3420gd1 in the game board side signal separation control circuit 3420g based on the clock signal SCLK1, the serial When the light guide plate designating information in the data SDAT1 includes its own ID, the brightness information in the serial data SDAT1 is taken in, and based on the integrated brightness signal from the brightness integrated setting switch 4880, The light emission by the first light guide plate 5000d provided in the game board side effect display unit 1900 is turned off, or adjusted to one brightness in the brightness range from low brightness (minimum brightness) to high brightness (maximum brightness). A first light guide plate PWM signal that can be turned on is created and output to the LED driver IC 4810 of the first light guide plate control circuit 3420k1. In the present embodiment, the first light guide plate PWM control circuit 4950 receives the serial data SDAT1 from the first serial controller 3420gd1 in the game board side signal separation control circuit 3420g based on the clock signal SCLK1 and outputs the serial data SDAT1. When the light guide plate designation information in 1 does not include its own ID, the brightness information in the serial data SDAT1 is not captured, and the output of the first light guide plate PWM signal created based on the previously captured brightness information is maintained.

When the second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2 receives the serial data SDAT1 from the first serial controller 3420gd1 in the game board side signal separation control circuit 3420g based on the clock signal SCLK1, the serial When the light guide plate designating information in the data SDAT1 includes its own ID, the brightness information in the serial data SDAT1 is taken in, and based on the integrated brightness signal from the brightness integrated setting switch 4880, The light emission by the second light guide plate 5000f provided in the game board side effect display unit 1900 is turned off, or adjusted to one brightness in the brightness range from low brightness (minimum brightness) to high brightness (maximum brightness). A second light guide plate PWM signal that can be turned on is created and output to the LED driver IC 4830 of the second light guide plate control circuit 3420k2. In the present embodiment, the second light guide plate PWM control circuit 4960 receives the serial data SDAT1 from the first serial controller 3420gd1 in the game board side signal separation control circuit 3420g based on the clock signal SCLK1 and outputs the serial data SDAT1. When the light guide plate designation information in 1 does not include its own ID, the luminance information in the serial data SDAT1 is not captured, and the output of the second light guide plate PWM signal created based on the previously captured luminance information is maintained.

When the third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3 receives the serial data SDAT1 from the first serial controller 3420gd1 in the game board side signal separation control circuit 3420g based on the clock signal SCLK1, the serial When the light guide plate designating information in the data SDAT1 includes its own ID, the brightness information in the serial data SDAT1 is taken in, and based on the integrated brightness signal from the brightness integrated setting switch 4880, The light emission by the third light guide plate 5000g provided in the game board side effect display unit 1900 is turned off, or adjusted to one brightness in the brightness range from low brightness (minimum brightness) to high brightness (maximum brightness). A third light guide plate PWM signal that can be turned on is created and output to the LED driver IC 4850 of the third light guide plate control circuit 3420k3. In addition, in the present embodiment, when the third light guide plate PWM control circuit 4970 receives the serial data SDAT1 from the first serial controller 3420gd1 in the game board side signal separation control circuit 3420g based on the clock signal SCLK1, the serial data SDAT1. When the light guide plate designation information in 1 does not include its own ID, the brightness information in the serial data SDAT1 is not captured, and the output of the third PWM signal for the light guide plate created based on the previously captured brightness information is maintained.

When the fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4 receives the serial data SDAT2 from the second serial controller 3420gd2 in the game board side signal separation control circuit 3420g based on the clock signal SCLK2, the serial When the light guide plate designation information in the data SDAT2 includes its own ID, the brightness information in the serial data SDAT2 is taken in, and based on the integrated brightness signal from the integrated brightness setting switch 4880, from the acquired brightness information, The light emission by the fourth light guide plate 5000h provided in the game board side effect display unit 1900 is turned off, or the brightness is adjusted to one brightness in the brightness range from low brightness (minimum brightness) to high brightness (maximum brightness). A PWM signal for the fourth light guide plate that can be turned on is created and output to the LED driver IC 4815 of the fourth light guide plate control circuit 3420k4. In the present embodiment, the fourth light guide plate PWM control circuit 4955 receives the serial data SDAT2 from the second serial controller 3420gd2 in the game board side signal separation control circuit 3420g based on the clock signal SCLK2, and outputs the serial data SDAT2. When the light guide plate designation information in 1 does not include its own ID, the brightness information in the serial data SDAT2 is not captured, and the output of the fourth light guide plate PWM signal created based on the previously captured brightness information is maintained.

When the fifth light guide plate PWM control circuit 4965 of the fifth light guide plate control circuit 3420k5 receives the serial data SDAT2 from the second serial controller 3420gd2 in the game board side signal separation control circuit 3420g based on the clock signal SCLK2, the serial data is serialized. When the light guide plate designation information in the data SDAT2 includes its own ID, the brightness information in the serial data SDAT2 is taken in, and based on the integrated brightness signal from the integrated brightness setting switch 4880, from the acquired brightness information, The light emission by the fifth light guide plate 5000i included in the game board side effect display unit 1900 is turned off, or adjusted to one brightness in the brightness range from low brightness (minimum brightness) to high brightness (maximum brightness). A fifth PWM signal for the light guide plate capable of turning on the light is created and output to the LED driver IC 4835 of the fifth light guide plate control circuit 3420k5. In the present embodiment, the fifth light guide plate PWM control circuit 4965 receives the serial data SDAT2 from the second serial controller 3420gd2 in the game board side signal separation control circuit 3420g based on the clock signal SCLK2, and outputs the serial data SDAT2. When the ID of the light guide plate is not included in the light guide plate designation information, the brightness information in the serial data SDAT2 is not captured, and the output of the fifth PWM signal for the light guide plate created based on the previously captured brightness information is maintained.

When the sixth light guide plate PWM control circuit 4975 of the sixth light guide plate control circuit 3420k6 receives the serial data SDAT2 from the second serial controller 3420gd2 in the game board side signal separation control circuit 3420g based on the clock signal SCLK2, the serial When the light guide plate designation information in the data SDAT2 includes its own ID, the brightness information in the serial data SDAT2 is taken in, and based on the integrated brightness signal from the integrated brightness setting switch 4880, from the acquired brightness information, The light emitted by the sixth light guide plate 5000k provided in the game board side effect display unit 1900 is turned off, or adjusted to one brightness in the brightness range from low brightness (minimum brightness) to high brightness (maximum brightness). A sixth PWM signal for light guide plate that can be turned on is created and output to the LED driver IC 4855 of the sixth light guide plate control circuit 3420k6. In the present embodiment, the sixth light guide plate PWM control circuit 4975 receives the serial data SDAT2 from the second serial controller 3420gd2 in the game board side signal separation control circuit 3420g based on the clock signal SCLK2, and outputs the serial data SDAT2. When the ID of the light guide plate is not included in the light guide plate designation information in, the brightness information in the serial data SDAT2 is not captured, and the output of the sixth PWM signal for the light guide plate created based on the previously captured brightness information is maintained.

Game board side VDP control target first decoration LED control circuit 3420i1 to game board side VDP control target 27th decoration LED control circuit 3420i27 is the third serial controller 3420gd3 to 11th in the game board side signal separation control circuit 3420g. When serial data SDAT3 to serial data SDAT11 from the serial controller 3420gd11 are respectively received based on the clock signals SCLK3 to SCLK11, when the own LED is included in the illumination LED designation information in the serial data SDAT3 to serial data SDAT11. , The gradation information in the serial data SDAT3 to the serial data SDAT11 is fetched, and the dimming lighting control is performed on the corresponding decorative LEDs so that the gradation degree is the fetched gradation information. In the present embodiment, the game board side VDP control target first decoration LED control circuit 3420i1 to the game board side VDP control target 27th decoration LED control circuit 3420i27 is the first in the game board side signal separation control circuit 3420g. 3 serial controller 3420gd3 to 11th serial controller 3420gd11 receive the serial data SDAT3 to serial data SDAT11 based on the clock signal SCLK3 to clock signal SCLK11, the serial ID SDAT3 to serial data SDAT11 in the illumination LED designating information, own ID. Is not included, the gradation information in the serial data SDAT3 to the serial data SDAT11 is not taken in, and the gradation degree, which is the previously taken in gradation information, is maintained for the corresponding decoration LED.

As described above, the LED driver IC 4810 of the first light guide plate control circuit 3420k1 is based on the first light guide plate PWM signal from the first light guide plate PWM control circuit 4950 of the first light guide plate control circuit 3420k1. The light emission by the first light guide plate 5000d can be turned off, and the brightness range from low brightness (minimum brightness) to high brightness (maximum brightness) can be adjusted by 1%, and one of the brightness ranges can be adjusted. The light can be adjusted and turned on. Specifically, the LED driver IC 4810 includes a light guide plate upper decoration substrate 5000d1 provided on the upper end surface of the first light guide plate 5000d, a light guide plate lower decoration substrate 5000d2 provided on the lower end surface of the first light guide plate 5000d, It is possible to adjust the brightness by varying the current flowing through the LEDs 5000d6, which are respectively mounted in a plurality.

As described above, the LED driver IC 4830 of the second light guide plate control circuit 3420k2 is based on the second light guide plate PWM signal from the second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2. The light emission by the second light guide plate 5000f can be turned off, and the brightness range from low brightness (minimum brightness) to high brightness (maximum brightness) can be adjusted by 1%, and one of the brightness ranges can be adjusted. The light can be adjusted and turned on. Specifically, the LED driver IC 4830 includes a light guide plate upper decorative substrate 5000f1 provided on the upper end face of the second light guide plate 5000f, a light guide plate lower decorative substrate 5000f2 provided on the lower end face of the second light guide plate 5000f, The brightness can be adjusted by varying the current flowing through the LEDs 5000f6, which are respectively mounted on the plurality of LEDs.

As described above, the LED driver IC 4850 of the third light guide plate control circuit 3420k3 is based on the third light guide plate PWM signal from the third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3. The light emission by the third light guide plate 5000g is turned off, and the brightness range from low brightness (minimum brightness) to high brightness (maximum brightness) can be adjusted by 1%, and at the same time, the brightness of one of the brightness ranges can be adjusted. The light can be adjusted and turned on. Specifically, the LED driver IC 4850 includes a light guide plate upper decorative substrate 5000g1 provided on the upper end surface of the third light guide plate 5000g, a light guide plate lower decorative substrate 5000g2 provided on the lower end surface of the third light guide plate 5000g, The brightness can be adjusted by varying the current flowing through the LEDs 5000g6 mounted in plural numbers.

As described above, the LED driver IC 4815 of the fourth light guide plate control circuit 3420k4 is based on the fourth light guide plate PWM signal from the fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4. The light emission by the fourth light guide plate 5000h can be turned off, and the brightness range from low brightness (minimum brightness) to high brightness (maximum brightness) can be adjusted by 1%, and one of the brightness ranges can be adjusted. The light can be adjusted and turned on. Specifically, the LED driver IC 4815 includes a light guide plate upper decorative substrate 5000h1 provided on the upper end surface of the fourth light guide plate 5000h, a light guide plate lower decorative substrate 5000h2 provided on the lower end surface of the fourth light guide plate 5000h, It is possible to adjust the brightness by varying the current flowing through the LEDs 5000h6, which are respectively mounted in a plurality.

As described above, the LED driver IC 4835 of the fifth light guide plate control circuit 3420k5 is based on the fifth light guide plate PWM signal from the fifth light guide plate PWM control circuit 4965 of the fifth light guide plate control circuit 3420k5. The light emission by the fifth light guide plate 5000i can be turned off, and the brightness range from low brightness (minimum brightness) to high brightness (maximum brightness) can be adjusted by 1%, and one of the brightness ranges can be adjusted. The light can be adjusted and turned on. Specifically, the LED driver IC 4835 includes a light guide plate upper decorative substrate 5000i1 provided on the upper end surface of the fifth light guide plate 5000i, a light guide plate lower decorative substrate 5000i2 provided on the lower end surface of the fifth light guide plate 5000i, The brightness can be adjusted by changing the currents flowing through the LEDs 5000i6, which are respectively mounted in a plurality.

As described above, the LED driver IC 4855 of the sixth light guide plate control circuit 3420k6 is based on the sixth light guide plate PWM signal from the sixth light guide plate PWM control circuit 4975 of the sixth light guide plate control circuit 3420k6. The light emission by the sixth light guide plate 5000k is turned off, and the brightness range from low brightness (minimum brightness) to high brightness (maximum brightness) can be adjusted by 1%, and one of the brightness ranges The light can be adjusted and turned on. Specifically, the LED driver IC 4855 includes a light guide plate upper decorative substrate 5000k1 provided on the upper end surface of the sixth light guide plate 5000k, and a light guide plate lower decorative substrate 5000k2 provided on the lower end surface of the sixth light guide plate 5000k. The brightness can be adjusted by changing the currents flowing through the LEDs 5000k6, which are respectively mounted in a plurality.

In the first light guide plate 5000d, the light guide plate decoration substrate 5000d1 has three LED rows in which six LEDs 5000d6 are electrically connected in series, and a total of 18 LEDs 5000d6 are mounted in one row. The light guide plate lower decorative substrate 5000d2 has three LED rows in which six LEDs 5000d6 are electrically connected in series, and a total of 18 LEDs 5000d6 are mounted in one row. That is, in the first light guide plate 5000d, 18 LEDs 5000d6 are mounted in a line on the upper end surface of the first light guide plate 5000d, and 18 LEDs 5000d6 are arranged in a line on the lower end surface of the first light guide plate 5000d. By being mounted, the light emitting area 500d4 can be surface-emitted by 36 LEDs 5000d6 as a whole.

In the second light guide plate 5000f, the light guide plate decoration substrate 5000f1 has three LED rows in which six LEDs 5000f6 are electrically connected in series, and a total of 18 LEDs 5000f6 are mounted in one row, The decorative substrate below the light guide plate 5000f2 has three LED rows in which six LEDs 5000f6 are electrically connected in series, and a total of 18 LEDs 5000f6 are mounted in one row. That is, in the second light guide plate 5000f, 18 LEDs 5000f6 are mounted in a line on the upper end surface of the second light guide plate 5000f, and 18 LEDs 5000f6 are arranged in a line on the lower end surface of the second light guide plate 5000f. By being mounted, the light emitting area 5000f4 can be surface-emitted by the total of 36 LEDs 5000f6.

In the third light guide plate 5000g, the light guide plate decorative substrate 5000g1 has three LED rows in which six LEDs 5000g6 are electrically connected in series, and a total of 18 LEDs 5000g6 are mounted in one row, The decorative substrate below the light guide plate 5000g2 has three LED rows in which six LEDs 5000g6 are electrically connected in series, and a total of 18 LEDs 5000g6 are mounted in one row. That is, in the third light guide plate 5000g, 18 LEDs 5000g6 are mounted in a line on the upper end surface of the third light guide plate 5000g, and 18 LEDs 5000g6 are arranged in a line on the lower end surface of the third light guide plate 5000g. By being mounted, the light emitting area 5000g4 can be surface-emitted by 36 LEDs 5000g6 as a whole.

In the fourth light guide plate 5000h, the light guide plate decoration substrate 5000h1 has three LED rows in which six LEDs 5000h6 are electrically connected in series, and a total of 18 LEDs 5000h6 are mounted in one row. The decorative substrate below the light guide plate 5000h2 has three LED rows in which six LEDs 5000h6 are electrically connected in series, and a total of 18 LEDs 5000h6 are mounted in one row. That is, in the fourth light guide plate 5000h, 18 LEDs 5000h6 are mounted in a line on the upper end surface of the fourth light guide plate 5000h, and 18 LEDs 5000h6 are arranged in a line on the lower end surface of the fourth light guide plate 5000h. By being mounted, the light emitting region 500h4 is configured to be able to emit surface light by 36 LEDs 5000h6 as a whole.

In the fifth light guide plate 5000i, the light guide plate decorative substrate 5000i1 has three LED rows in which six LEDs 5000i6 are electrically connected in series, and a total of 18 LEDs 5000i6 are mounted in one row, and The lower light guide plate decorative substrate 5000i2 has three LED rows in which six LEDs 5000i6 are electrically connected in series, and a total of 18 LEDs 5000i6 are mounted in one row. That is, in the fifth light guide plate 5000i, 18 LEDs 5000i6 are mounted in a line on the upper end surface of the fifth light guide plate 5000i, and 18 LEDs 5000i6 are mounted in a line on the lower end surface of the fifth light guide plate 5000i. By being mounted, the light emitting area 5000i4 can be surface-emitted by a total of 36 LEDs 5000i6.

In the sixth light guide plate 5000k, the light guide plate decoration substrate 5000k1 has three LED rows in which six LEDs 5000k6 are electrically connected in series, and a total of 18 LEDs 5000k6 are mounted in one row, The decorative substrate below the light guide plate 5000k2 has three LED rows in which six LEDs 5000k6 are electrically connected in series, and a total of 18 LEDs 5000k6 are mounted in one row. That is, in the sixth light guide plate 5000k, 18 LEDs 5000k6 are mounted in a line on the upper end surface of the sixth light guide plate 5000k, and 18 LEDs 5000k6 are arranged in a line on the lower end surface of the sixth light guide plate 5000k. By being mounted, the light emitting area 5000k4 can be surface-emitted by the 36 LEDs 5000k6 as a whole.

LED driver IC 4810 of the first light guide plate control circuit 3420k1, LED driver IC 4830 of the second light guide plate control circuit 3420k2, LED driver IC 4850 of the third light guide plate control circuit 3420k3, LED driver of the fourth light guide plate control circuit 3420k4. The IC 4815, the LED driver IC 4835 of the fifth light guide plate control circuit 3420k5, and the LED driver IC 4855 of the sixth light guide plate control circuit 3420k6 electrically connect up to 12 LEDs (white LEDs) to one LED row. Can be connected in series and can drive LEDs of 6 LED strings (72 LEDs (=12 LEDs×6 LED strings)).

The LED driver IC 4810 of the first light guide plate control circuit 3420k1, the LED driver IC 4830 of the second light guide plate control circuit 3420k2, the LED driver IC 4850 of the third light guide plate control circuit 3420k3, and the fourth light guide plate control circuit 3420k4. The LED driver IC 4815, the LED driver IC 4835 of the fifth light guide plate control circuit 3420k5, and the LED driver IC 4855 of the sixth light guide plate control circuit 3420k6 are PWM type DC/DC converters capable of increasing the voltage to a predetermined upper limit voltage. Section and a current driver section capable of flowing a constant current up to a predetermined upper limit current, and for each first light guide plate input to a POWCTL terminal which is a power control terminal described later. LEDs based on the PWM signal, the second light guide plate PWM signal, the third light guide plate PWM signal, the fourth light guide plate PWM signal, the fifth light guide plate PWM signal, and the sixth light guide plate PWM signal The brightness lighting can be performed with high accuracy.

As described above, in the present embodiment, the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 controls the LED driver IC 4810 of the first light guide plate control circuit 3420k1 capable of dimming and lighting the first light guide plate 5000d. Instead of directly outputting the first light guide plate PWM signal, the first light guide plate PWM control circuit 4950 of the first light guide plate control circuit 3420k1 which is a circuit different from the peripheral control MPU 4150a outputs the first light guide plate PWM control circuit 4950 to the LED driver IC 4810. By directly outputting the PWM signal for the light guide plate, the delicate control of the dimming lighting of the first light guide plate 5000d, which requires a fine processing load, is separated from the control by the peripheral control MPU4150a and left to the first light guide plate control circuit 3420k1. We adopted the control method. Further, in the present embodiment, the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 controls the LED driver IC 4830 of the second light guide plate control circuit 3420k2 that can dimming the second light guide plate 5000f. The second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2, which is a circuit different from the peripheral control MPU4150a, does not directly output the light guide plate PWM signal of the second light guide plate PWM control circuit 4960 to the LED driver IC 4830. Control for directly outputting the PWM signal for the light plate to separate the dimming lighting of the second light guide plate 5000f from which the processing load is applied to the second light guide plate control circuit 3420k2 separately from the control by the peripheral control MPU4150a. Adopted the method. Further, in the present embodiment, the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 controls the LED driver IC 4850 of the third light guide plate control circuit 3420k3 that can dimming the third light guide plate 5000g. Instead of directly outputting the PWM signal for the light guide plate, the third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3, which is a circuit different from the peripheral control MPU4150a, transmits the third light guide plate PWM control circuit 4970 to the LED driver IC 4850. Control for directly outputting the PWM signal for the light plate to separate the light-dimming lighting of the third light guide plate 5000g from the control by the peripheral control MPU4150a to the third light guide plate control circuit 3420k3. Adopted the method.

In addition, in the present embodiment, the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 controls the LED driver IC 4815 of the fourth light guide plate control circuit 3420k4 that can dimming and turn on the fourth light guide plate 5000h. Instead of directly outputting the PWM signal for the light guide plate, the fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4, which is a circuit different from the peripheral control MPU 4150a, transmits the fourth light guide plate PWM control circuit 4955 to the LED driver IC 4815. Control that directly outputs the PWM signal for the light plate and decouples the light control lighting of the fourth light guide plate 5000h that requires a detailed processing load from the control by the peripheral control MPU 4150a and leaves it to the fourth light guide plate control circuit 3420k4. Adopted the method. Further, in the present embodiment, the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 controls the LED driver IC 4835 of the fifth light guide plate control circuit 3420k5 that can dimming and turn on the fifth light guide plate 5000i. Instead of directly outputting the PWM signal for the light guide plate, the fifth light guide plate PWM control circuit 4965 of the fifth light guide plate control circuit 3420k5, which is a circuit different from the peripheral control MPU4150a, outputs the fifth signal to the LED driver IC 4835. A control in which the fifth light guide plate control circuit 3420k5 is decoupled from the control by the peripheral control MPU4150a by directly outputting the PWM signal for the light plate to dimming and lighting the fifth light guide plate 5000i and subjecting it to a processing load. Adopted the method. Further, in the present embodiment, the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 controls the sixth LED driver IC 4855 of the sixth light guide plate control circuit 3420k6 capable of dimming and lighting the sixth light guide plate 5000k. Instead of directly outputting the PWM signal for the light guide plate, the sixth light guide plate PWM control circuit 4975 of the sixth light guide plate control circuit 3420k6, which is a circuit different from the peripheral control MPU4150a, transmits the sixth light guide plate PWM control circuit 4975 to the LED driver IC 4855. A control in which the sixth light guide plate control circuit 3420k6 is decoupled from the control by the peripheral control MPU4150a, which is a dimming lighting of the sixth light guide plate 5000k by directly outputting the light plate PWM signal, and is controlled by the peripheral control MPU4150a. Adopted the method.

As described above, the light guide plate information and the electric decoration information are applied to each of the plurality of game board side VDP control target decoration boards, which are control objects to be directly controlled by the sound source built-in VDP 4160a, among the respective decoration boards of the game board 4. Plural stored in the liquid crystal and sound control ROM 4160b in advance as game board side light emission mode setting image data for setting the light emission modes of the provided LEDs (decorative LEDs). Then, the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 controls the light guide lighting of the plurality of light guide plates included in the game board side effect display unit 1900, which is delicate and requires a processing load, to control the first light guide plate. To the circuit 3420k1, the second light guide plate control circuit 3420k2, the third light guide plate control circuit 3420k3, the fourth light guide plate control circuit 3420k4, the fifth light guide plate control circuit 3420k5, and the sixth light guide plate control circuit 3420k6. Since it is possible to leave it to the peripheral control MPU 4150a, it is possible to reduce the processing load of the light emission control of the dimming lighting. Accordingly, the dimming lighting of the first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000g, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k is performed. Even if the number of variations of the effect due to the image (screen) of the liquid crystal panel 5000e provided in the game board side effect display unit 1900 is increased, the processing load of the light emission control of the dimming lighting on the peripheral control MPU 4150a does not increase. , There are no restrictions on the variations of production. That is, in the present embodiment, it is possible to increase the variation of the effects while reducing the processing load of the light emission control on the peripheral control MPU 4150a, and thus it is possible to make it difficult for the player to lose interest in the effects. .. Therefore, it is possible to contribute to suppressing a decrease in interest.

Further, in the present embodiment, as described above, the first light guide plate PWM control circuit 4950 of the first light guide plate control circuit 3420k1, the second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2, The third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3, the fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4, and the fifth light guide plate control circuit 3420k5 of the fifth light guide plate control circuit 3420k5. The light guide plate PWM control circuit 4965 and the sixth light guide plate PWM control circuit 4975 of the sixth light guide plate control circuit 3420k6 are output from the first serial controller 3420gd1 and the second serial controller 3420gd2 in the game board side signal separation control circuit 3420g. When the serial data SDAT1 and the serial data SDAT2 are received based on the clock signal SCLK1 and the clock signal SCLK2, when the ID of the light guide plate in the serial data SDAT1 and the serial data SDAT2 does not include its own ID, the serial data SDAT1 and the serial data The LED driver IC 4810 of the first light guide plate control circuit 3420k1, the LED driver IC 4830 of the second light guide plate control circuit 3420k2, and the LED driver IC 4850 of the third light guide plate control circuit 3420k3, which do not capture the luminance information in SDAT2, respectively. Based on the luminance information previously captured to the LED driver IC 4815 of the fourth light guide plate control circuit 3420k4, the LED driver IC 4835 of the fifth light guide plate control circuit 3420k5, and the LED driver IC 4855 of the sixth light guide plate control circuit 3420k6. It is configured to maintain the outputs of the first to sixth light guide plate PWM signals created as described above. Further, in the present embodiment, as described above, since the frame frequency is set to 30 fps (about every 33.3 ms), the drawing data is output to the liquid crystal output substrate 3420 from the channel CH1 of the sound source built-in VDP 4160a. There is.

Accordingly, the first light guide plate PWM control circuit 4950, the second light guide plate PWM control circuit 4960, the third light guide plate PWM control circuit 4970, the fourth light guide plate PWM control circuit 4955, and the fifth light guide plate PWM control. Since the circuit 4965 and the sixth light guide plate PWM control circuit 4975 can repeatedly update the luminance information about every 33.3 ms, it is tentatively output from the channel CH1 of the sound source built-in VDP 4160a. Even if the brightness information in the drawing data is changed to something different from the regular content due to some electrical reason, it is possible to obtain an opportunity to capture the regular content next time, that is, after about 33.3 ms has passed. Thus, in an extremely short period of about 33.3 ms, the LED driver IC 4810 emits light from the first light guide plate 5000d, the LED driver IC 4830 emits light from the second light guide plate 5000f, and the LED driver IC 4850 emits light from the third light guide plate 5000g. Light emission mode of the fourth light guide plate 5000h by the LED driver IC 4815, the light emission mode of the fifth light guide plate 5000i by the LED driver IC 4835, and the light emission mode of the sixth light guide plate 5000k by the LED driver IC 4855 are regular light emission. Even if the mode changes to an unintended light emitting mode, the player can correct the normal light emitting mode (that is, the normal light emitting mode) without noticing the change.

[12-2-1. LED driver ICs for various light guide plate control circuits]
In this embodiment, the first light guide plate control circuit 3420k1, the second light guide plate control circuit 3420k2, the third light guide plate control circuit 3420k3, the fourth light guide plate control circuit 3420k4, the fifth light guide plate control circuit 3420k5, And the sixth light guide plate control circuit 3420k6 are adopted as the same circuit configuration. Here, the first light guide plate control circuit 3420k1 will be described in detail below, and the second light guide plate control circuit 3420k2, the third light guide plate control circuit 3420k3, the fourth light guide plate control circuit 3420k4, and the fifth light guide plate control circuit 3420k4. Detailed descriptions of the light plate control circuit 3420k5 and the sixth light guide plate control circuit 3420k6 are omitted.

As shown in FIG. 36, the first light guide plate control circuit 3424k1 mainly includes an LED driver IC 4810. The LED driver IC 4810 includes a regulator unit 4810a, an error amplifier unit 4810b, a PWM comparator unit 4810c, a current detection unit 4810d, an oscillating unit (OSC) 4810e, a control unit 4810f, an SR flip-flop unit 4810g, an output buffer unit 4810h, a current driver unit 4810i. The input buffer unit 4810k is mainly configured.

The PWM type DC/DC converter unit capable of boosting the voltage to the predetermined upper limit voltage in the LED driver IC 4810 includes an error amplifier unit 4810b, a PWM comparator unit 4810c, a current detection unit 4810d, an oscillation unit (OSC) 4810e, and a control unit. The current driver unit, which is a circuit configured by the unit 4810f, the SR flip-flop unit 4810g, and the output buffer unit 4810h, can flow a constant current up to the above-described predetermined upper limit current in the LED driver IC 4810. It is a circuit composed of 4810i.

The regulator unit 4810a is supplied with power through a Vin terminal that is a power supply terminal, and also receives power from the first light guide plate PWM control circuit 4950 through the POWCTL terminal that is a power control terminal and the input buffer unit 4810k. The PWM signal 1 for the light guide plate is input. The regulator unit 4810a can generate or stop (stop) the internal power supply Vreg for supplying various circuit units in the LED driver IC 4810 based on the first light guide plate PWM signal. It is configured.

The error amplifier unit 4810b has six inverting input terminals (described as "-" in the figure), that is, a first inverting input terminal to a sixth inverting input terminal and one non-inverting input terminal (in the figure, "-"). +"). As described above, the light guide plate decoration substrate 5000d1 included in the game board side effect display unit 1900 has three LED rows in which six LEDs 5000d6 are electrically connected in series, and a total of 18 LEDs 5000d6 are in one row. As described above, the decorative substrate 5000d2 below the light guide plate has three LED rows in which six LEDs 5000d6 are electrically connected in series, and a total of 18 LEDs 5000d6 are mounted in one row. There is.

In the present embodiment, the cathode terminal of the LED 5000d6 at the final stage of the first LED row (that is, the sixth LED 5000d6) of the three LED rows of the decorative substrate 5000d1 on the light guide plate is the first through the LED1 terminal. Is electrically connected to the non-inverting input terminal of, and the cathode terminal of the LED 5000d6 (that is, the sixth LED 5000d6) at the final stage of the second LED row of the three LED rows of the light guide plate decoration substrate 5000d1 is It is electrically connected to the second non-inverting input terminal via the LED2 terminal, and among the three LED rows of the light guide plate decoration substrate 5000d1, the LED 5000d6 (that is, the sixth LED) at the final stage of the third LED row is The cathode terminal of the LED 5000d6) is electrically connected to the third non-inverting input terminal via the LED3 terminal. That is, the voltage applied to the cathode terminal of the LED 5000d6 at the final stage of each LED row is applied to the LED terminals 1 to 3.

In addition, in the present embodiment, the cathode terminal of the LED 5000d6 (that is, the sixth LED 5000d6) at the final stage of the first LED row among the three LED rows of the light guide plate lower decorative substrate 5000d2 is connected to the LED4 terminal via the LED4 terminal. The cathode terminal of the LED 5000d6 (that is, the sixth LED 5000d6) in the final stage of the second LED row of the three LED rows of the light guide plate lower decorative substrate 5000d2, which is electrically connected to the non-inverting input terminal 4 of FIG. Is electrically connected to the fifth non-inverting input terminal via the LED5 terminal, and among the three LED rows of the light guide plate lower decorative substrate 5000d2, the LED 5000d6 (that is, six LEDs) at the final stage of the third LED row is The cathode terminal of the eye LED 5000d6) is electrically connected to the sixth non-inverting input terminal via the LED6 terminal. That is, the voltage applied to the cathode terminal of the LED 5000d6 at the final stage of each LED row is applied to the LED terminals 4 to 6.

On the other hand, the reference voltage Vref generated from the internal power supply Vreg is applied to the non-inverting input terminal.

The error amplifier unit 4810b compares and compares the lowest voltage among the voltages applied to the first inverting input terminal to the sixth inverting input terminal with the reference voltage Vref applied to the non-inverting input terminal. It is configured to output the result as an error voltage Ver to the PWM comparator unit 4810c. The error amplifier unit 4810b is a voltage applied to the anode terminal of the LED 5000d6 (that is, the first LED 5000d6) in the first stage of the first LED row among the three LED rows of the light guide plate decorative substrate 5000d1, the light guide plate. Of the three LED rows of the upper decorative substrate 5000d1, the voltage applied to the anode terminal of the LED 5000d6 of the first stage of the second LED row (that is, the first LED 5000d6) and the three rows of the light guide plate upper decorative substrate 5000d1. Of the LED row, the voltage applied to the anode terminal of the first-stage LED 5000d6 of the third LED row (that is, the first LED 5000d6) and the first of the three LED rows of the light guide plate lower decorative substrate 5000d2 The voltage applied to the anode terminal of the first-stage LED 5000d6 of the LED row (that is, the first LED 5000d6) and the first-stage LED 5000d6 of the second LED row (that is, the third LED row of the light guide plate lower decorative substrate 5000d2) The voltage applied to the anode terminal of the first LED 5000d6) and the LED 5000d6 in the first stage of the third LED row among the three LED rows of the light guide plate lower decorative substrate 5000d2 (that is, the first LED 5000d6). The error voltage Ver is increased as the difference between the voltage applied to the anode terminal and the output voltage Vout described later is increased.

As described above, the error amplifier unit 4810b applies the voltage applied to the LED1 terminal to the LED6 terminal (the voltage applied to the cathode terminal of the LED5000d6 at the final stage of each LED 5000d6 of the light guide plate upper decoration substrate 5000d1 and the light guide plate lower decoration substrate 5000d2). ) Is being monitored.

The PWM comparator unit 4810c has one inverting input terminal (denoted by “−” in the figure) and one non-inverting input terminal (denoted by “+” in the figure). The error voltage Ver, which is the comparison result of the error amplifier unit 4810b, is applied to the inverting input terminal, while the voltage of the detection signal from the current detecting unit 4810d and the oscillating unit (OSC) 4810e are applied to the inverting input terminal. The voltage (hereinafter, referred to as “addition voltage”) Vad obtained by adding the voltage of the triangular wave signal of No.

The PWM comparator unit 4810c compares the error voltage Ver applied to the inverting input terminal with the added voltage Vad applied to the non-inverting input terminal to create a comparison signal of the duty ratio according to the comparison result, and the control unit 4810f. It is configured to output to.

The current detection unit 4810d has two terminals (RP terminal, for detecting a terminal voltage of a resistor LR1 described later, which is electrically connected to the LED driver IC 4810 separately (that is, as an external attachment of the LED driver IC 4810). The current flowing through the resistor LR1 is detected based on the voltage applied via the RN terminal), and the detection result can be output as a detection signal to the PWM comparator unit 4810c.

The oscillating unit (OSC) 4810e is configured to generate a triangular wave voltage and output it as a triangular wave signal to the PWM comparator unit 4810c and to the control unit 4810f.

The control unit 4810f is configured to generate a set signal and a reset signal based on the comparison signal from the PWM comparator unit 4810c and output the set signal and the reset signal to the SR flip-flop unit 4810g. The control unit 4810f controls ON/OFF of an N-channel field effect transistor LTr1 described later that is electrically connected to the SW terminal that is a switching terminal, and the comparison signal logic from the PWM comparator unit 4810c is LOW ( When it is a logic L), a set signal and a reset signal can be created and output to the SR flip-flop unit 4810g in order to control the N-channel field effect transistor LTr1 to be ON, while the PWM comparator unit 4810c outputs the set signal and the reset signal. When the logic of the comparison signal is HI (logic H), a set signal and a reset signal can be created and output to the SR flip-flop unit 4810g in order to control the N-channel field effect transistor LTr1 to OFF. Is configured. That is, the control unit 4810f is configured to perform switching control capable of turning on/off the N-channel field effect transistor LTr1 via the SR flip-flop unit 4810g.

The SR flip-flop unit 4810g has an S terminal that is a set terminal, an R terminal that is a reset terminal, a Q terminal that is an output terminal, and the like. A set signal from the control unit 4810f is input to the S terminal, and a reset signal from the control unit 4810f is input to the R terminal. The SR flip-flop unit 4810g outputs a switching signal from the Q terminal which is an output terminal based on the set signal from the control unit 4810f input to the S terminal and the reset signal from the control unit 4810f input to the R terminal. Output to the output buffer unit 4810h. The switching signal is output to the N-channel field effect transistor LTr1 via the output buffer unit 4810h and the SW terminal which is a switching terminal.

The voltage applied to the first inverting input terminal to the sixth inverting input terminal of the error amplifier section 4810b is applied to the current driver section 4810i. In other words, the current driver unit 4810i has a voltage applied to the anode terminal of the first-stage LED 5000d6 (that is, the first LED 5000d6) of the first LED row among the three LED rows of the light guide plate decoration substrate 500d1. The voltage applied to the anode terminal of the LED 5000d6 (that is, the first LED 5000d6) in the first stage of the second LED row among the three LED rows of the decorative board 5000d1 on the light guide plate, 3 of the decorative board 5000d1 on the light guide plate. Of the LED rows of the third row, the voltage applied to the anode terminal of the first-stage LED 5000d6 of the third LED row (that is, the first LED 5000d6), the LED row of the three rows of the lower light guide plate decorative substrate 5000d2, The voltage applied to the anode terminal of the first-stage LED 5000d6 of the first LED row (that is, the first LED 5000d6) and the first-stage LED 5000d6 of the second LED row among the three-row LED row of the light guide plate lower decorative substrate 5000d2. (That is, the voltage applied to the anode terminal of the first LED 5000d6) and the first LED 5000d6 of the third LED row (that is, the first LED 5000d6) among the three LED rows of the light guide plate lower decorative substrate 5000d2. The voltage applied to the anode terminal of the LED 5000d6) is applied.

The current driver unit 4810i is electrically connected to one end of a resistor LR2 provided outside the LED driver IC 4810 separately via an Is terminal which is a current setting terminal. The other end of the resistor LR2 is grounded to the ground (GND). The current driver unit 4810i can set the current flowing through each LED 5000d6 of the light guide plate upper decorative substrate 5000d1 and the light guide plate lower decorative substrate 5000d2 according to the resistance value of the resistor LR2. The resistance value set to 20 milliamperes (mA) is preset.

The LED driver IC 4810 has a GND terminal, which is a ground terminal of the ground (GND), grounded to the ground (GND) of the liquid crystal output substrate 3420.

Next, a peripheral circuit of the DC/DC converter unit provided separately from the LED driver IC 4810 that operates together with the PWM type DC/DC converter unit in the LED driver IC 4810 will be described. The first light guide plate control circuit 3420k1 is a peripheral circuit of the DC/DC converter unit, and is a coil LL1, a Schottky barrier diode LD1 (hereinafter, referred to as “diode LD1”), and N as an external attachment of the LED driver IC 4810. A chopper type booster circuit composed of electric components such as a channel type field effect transistor LTr1 (hereinafter referred to as “transistor LTr1”), a resistor LR1, capacitors LC1 and LC2 is provided.

This chopper type booster circuit drives the coil LL1 by turning on/off the transistor LTr1 to drive the game board side VDP control target first light guide plate power supply circuit out of the game board side various light guide plate power supply circuits 3420e. The output voltage Vout is created by boosting the voltage Vp1 of the first light guide plate power supply.

More specifically, the first light guide plate power supply (voltage Vp1) from the game board side VDP control target first light guide plate power supply circuit of the game board side various light guide plate power supply circuits 3420e is supplied. The light guide plate power supply line is electrically connected to one end of the coil LL1, and the other end of the coil LL1 is electrically connected to the drain of the transistor LTr1. The other end of the coil LL1 is electrically connected to the drain of the transistor LTr1 and is also electrically connected to the anode terminal of the diode LD1 and has one end grounded to the ground (GND). Is electrically connected to the other end of the LED driver IC 4810 and is electrically connected to a Vin terminal which is a power supply terminal of the LED driver IC 4810.

The cathode terminal of the diode LD1 is electrically connected to the other end of the capacitor LC2 whose one end is grounded to the ground (GND), and is connected to the anode terminals of the three LED columns on the light guide plate decorative substrate 5000d1 (that is, each In the LED row, six LEDs 5000d6 are electrically connected in series to the leading LED 5000d6 anode terminal) and the light guide plate lower decorative substrate 5000d2 has three LED row anode terminals (that is, 6 LEDs in each LED row). LED 5000d6 is electrically connected in series with the anode terminal of the leading LED 5000d6 electrically connected in series.

The gate terminal of the transistor LTr1 is electrically connected to the SW terminal which is a switching terminal of the LED driver IC 4810, and the source terminal of the transistor LTr1 is grounded to the ground (GND) via the resistor LR1.

One end of the resistor LR1 electrically connected to the source terminal of the transistor LTr1 is electrically connected to the RP terminal of the LED driver IC 4810 and the other end of the resistor LR1 (that is, grounded to the ground (GND)). Side) is electrically connected to the RN terminal.

The transistor LTr1 is turned on/off by an ON/OFF signal from the SW terminal which is a switching terminal of the LED driver IC 4810. When the transistor LTr1 is turned on, a switch current is generated by the first light guide plate power supply from the game board side VDP control target first light guide plate power supply circuit of the game board side various light guide plate power supply circuits 3420e and the coil LL1. , Through the transistor LTr1 and the resistor LR1 toward the ground (GND), and electric energy is stored in the coil LL1. As a result, the voltage applied to the anode terminal of the diode LD1 is pulled down to the ground (GND) side by the transistor LTr1. At this time, when the capacitor LC2 is charged so that the transistor LTr1 is turned on, the voltage applied to the cathode terminal of the diode LD1 is the voltage applied to the anode terminal of the diode LD1 (here, almost the ground (GND) level). The reverse bias is applied to the diode LD1 and the current discharged from the capacitor LC2 is blocked from flowing toward the transistor LTr1 side. Then, the three LED rows on the light guide plate upper decoration substrate 5000d1 and the three LED rows on the light guide plate lower decoration substrate 5000d2 flow toward the LED light guide plate upper decoration board 5000d1.

On the other hand, when the transistor LTr1 is turned off, the counter electromotive voltage is generated in the coil LL1 by discharging the electric energy stored in the coil LL1. As a result, the voltage applied to the anode terminal of the diode LD1 becomes higher than the voltage applied to the cathode terminal of the diode LD1 when the capacitor LC2 is discharged, and a forward bias is applied to the diode LD1. In the state, the current from the first light guide plate power supply circuit from the game board side VDP control target first light guide plate power supply circuit of the game board side various light guide plate power supply circuits 3420e is 3 in the light guide plate decoration board 5000d1. Therefore, the light will flow toward the LED rows of three rows and the three LED rows of the lower light guide plate decorative substrate 5000d2. As a result, the capacitor LC2 can be charged and the voltage applied to the capacitor LC2 can be boosted.

In this way, the LED driver IC 4810 outputs an ON/OFF signal from the SW terminal, which is a switching terminal, to the transistor LTr1 to turn on/off the transistor LTr1, thereby storing and releasing electrical energy in the coil LL1. In this way, a counter electromotive voltage is generated in the coil LL1, rectified by the diode LD1 and the capacitor LC2, and from the game board side various light guide plate power supply circuits 3420e, from the game board side VDP control target first light guide plate power supply circuit. The predetermined voltage (DC voltage) higher than the voltage Vp1 of the first light guide plate power supply is used as the output voltage Vout, and the three LED columns on the light guide plate upper decorative substrate 5000d1 and the three light guide plate lower decorative substrate 5000d2 are arranged. The LED rows of the rows can be respectively supplied.

Since the resistor LR1 can detect the switch current flowing in the transistor LTr1, the current detection unit 4810d in the LED driver IC 4810 monitors the switch current flowing in the transistor LTr1.

As described above, in the first light guide plate control circuit 3420k1, in the LED driver IC 4810, as described above, the voltage applied to the LED1 terminal to the LED6 terminal (each of the light guide plate upper decorative substrate 5000d1 and the light guide lower decorative substrate 5000d2). The voltage applied to the cathode terminal of the LED 5000d6 at the final stage of the LED 5000d6) is monitored by the error amplifier 4810b, and the switch current flowing through the transistor LTr1 is monitored by the current detector 4810d. As a result, the control unit 4810f can perform switch control for turning on/off the transistor LTr1. As a result, it becomes difficult for the control unit 4810f to follow the above-described error voltage Ver because the voltage fluctuations of the LED1 terminal to the LED6 terminal applied to the inverting input terminal of the error amplifier unit 4810b become sharp. In that case, since the transistor LTr1 can be turned on/off in accordance with the result of monitoring the switch current flowing through the transistor LTr1 by the current detection unit 4810d, fluctuations in the output voltage Vout can be suppressed. By suppressing such a variation in the output voltage Vout, it is not necessary to employ a large-sized capacitor having a large capacity as the capacitor LC2, which can contribute to cost reduction and a liquid crystal output substrate 3420 of the capacitor LC2. It is also possible to contribute to the layout of arranging other electronic components on the liquid crystal output substrate 3420 by reducing the mounting area in the.

[12-2-2. LED control circuit for various decorations on the game board side]
In the present embodiment, the game board side VDP control target first decoration LED control circuit 3420i1 to the game board side VDP control target 27th decoration LED control circuit 3420i27 is the same decoration LED driver IC as described above. Of each of the decorative boards of the game board 4, a plurality of LEDs (decoration) provided on each of the plurality of game board-side VDP controlled decorative boards that are directly controlled by the sound source built-in VDP 4160a. The light emitted by the LED) can be dimmed and turned on. Here, the game board side VDP control target first decoration LED control circuit 3420i1 will be briefly described below, and the game board side VDP control target second decoration LED control circuit 3420i2 to the game board side VDP control target twenty-seventh. The description of the decorative LED control circuit 3420i27 will be omitted.

As shown in FIG. 37, the decoration LED driver IC that constitutes the first decoration LED control circuit 3420i1 on the game board side VDP control has 24 output channels (ch), and a maximum of 80 mA (mA) for each channel. ) Is a constant current LED driver IC of 24ch that can output the current of (4). The decorative LED driver IC mainly includes an address setting unit 3420i1a, a logic processing unit 3420i1b, a clock generating unit 3420i1c, a data buffer unit 3420i1d, a PWM unit 3420i1e, and a constant current driving unit 3420i1f.

The address setting unit 3420i1a can set 64 types of addresses as its own ID (ID capable of identifying an individual) depending on the magnitude of the voltage applied to three address setting terminals (not shown). There is. The voltage applied to the three address setting terminals is one of the control voltage (+5V) DVp, 2/3DVp, 1/3DVp, and ground (GND), and the 2/3DVp and 1/3DVp are the control power source DVp. And a ground (GND) are divided by a plurality of resistors (not shown) electrically connected in series, and taken out.

For example, the control power DVp is supplied to one end of the first resistor, the other end of the first resistor is electrically connected to one end of the second resistor, and the other end of the second resistor is connected to the third resistor. The one end is electrically connected to the other end, and the other end of the third resistor is grounded to the ground (GND) so that the three resistors have the same resistance value. As a result, the voltage at which the other end of the second resistor and the one end of the third resistor are electrically connected becomes ⅓ DVp, which is a voltage that is ⅓ of the control voltage DVp. The voltage at which the other end of the second resistor and one end of the second resistor are electrically connected is ⅔ DVp, which is a two-third voltage of the control voltage DVp.

In this way, the ID that can identify the individual ornamental LED driver ICs that constitute the game board side VDP control target first ornamental LED control circuit 3420i1 is the hardware that is the voltage applied to the three address setting terminals. The address setting unit 3420i1a is set in advance according to the configuration of the ware, and is not set appropriately by receiving the data by the software.

The logic processing unit 3420i1b receives the serial data SDAT3 from the third serial controller 3420gd3 in the game board side signal separation control circuit 3420g based on the clock signal SCLK3 and transmits it to the data buffer unit 3420i1d. When the data buffer unit 3420i1d includes its own ID in the electric LED designation information in the serial data SDAT3 from the logic processing unit 3420i1b based on the address which is its own ID set by the address setting unit 3420i1a, the logic buffer It is determined that the serial data SDAT3 from the processing unit 3420i1b is for itself, and the gradation degree, which is the gradation information in the serial data SDAT3, is fetched, and the gradation degree is the fetched gradation information in each channel. While controlling to set the gradation degree in the PWM unit 3420i1e, when the illumination LED designation information in the serial data SDAT3 from the logic processing unit 3420i1b does not include its own ID, the serial data SDAT3 from the logic processing unit 3420i1b is It is determined that it is not for itself, the gradation degree which is the gradation information in the serial data SDAT3 is not captured, and control is performed to maintain the current contents set in the PWM unit 3420i1e.

The PWM unit 3420i1e is capable of controlling the brightness (gradation level) of the LED in each channel in a total of 128 steps from gradation off to lighting (maximum brightness) from gradation 0 (zero) to gradation 127. Therefore, the gradation control is performed by one PWM gradation control unit for one channel. That is, in the PWM unit 3420i1e, the gradation control is performed by the PWM gradation control unit 1 for the decoration LED on 1ch, the gradation control is performed by the PWM gradation control unit 2 for the decoration LED on 2ch,... The PWM gradation control unit 24 controls the gradation of the decorative LED on the 24ch, and is composed of a total of 24 PWM gradation control units 1 to 24. When the gradation levels are respectively set, the PWM gradation control section 1 to the PWM gradation control section 24, based on the clock signal from the clock generating section 3420i1c, apply a constant current so that a current having the set gradation level flows. The drive unit 3420i1f is controlled.

The constant current driving unit 3420i1f is a full-color LED that is a decorative LED with one constant current driver for one channel so that the gradation level is set in the PWM gradation control unit 1 to the PWM gradation control unit 24. The constant current driver 1 to the constant current driver 24 are provided in total for supplying a constant current to the LED elements constituting the.

The constant current driver 1 to the constant current driver 8 are electrically connected to one end of a resistor Rr1 that sets the maximum current flowing through the decorative LED in eight channels from 1ch to 8ch, and the other end of the resistor Rr1 is grounded. The constant current driver 9 to the constant current driver 16 are grounded to (GND), and one end of a resistor Rg1 that sets the maximum current flowing through the decorative LED in the eight channels from 9ch to 16ch is electrically connected to the constant current driver 9 to the constant current driver 16. The other end of the resistor Rg1 is grounded to the ground (GND), and the constant current driver 17 to the constant current driver 24 have one end of the resistor Rb1 that sets the maximum current flowing through the decorative LED in the eight channels from 17ch to 24ch. It is electrically connected and the other end of the resistor Rb1 is grounded to the ground (GND).

The anode terminal of the red LED element, the anode terminal of the green LED element, and the anode terminal of the blue LED element, which compose the full-color LEDs corresponding to the constant current driver 1 to the constant current driver 24, respectively, are the power supply for illumination ( Control power supply). The cathode terminals of the red LED elements forming the full-color LEDs corresponding to the constant current driver 1 to the constant current driver 8 are electrically connected to the LR1 terminal to the LR8 terminal, respectively, and the constant current driver 9 to the constant current driver 16 respectively. The cathode terminal of the green LED element that constitutes the corresponding full-color LED is electrically connected to the LG1 terminal to LG8 terminal, and the blue LED element that constitutes the corresponding full-color LED with the constant current driver 17 to constant current driver 24, respectively. The cathode terminal of is electrically connected to the LB1 terminal to the LB8 terminal.

Then, the constant current driver 1 to the constant current driver 8 set the constant currents individually set to the red LED elements constituting the full-color LEDs, which are the decorative LEDs corresponding to the eight channels from 1ch to 8ch, respectively, to LR1. Each of the constant current driver 9 to the constant current driver 16 is individually supplied to a green LED element forming a full-color LED which is a decorative LED corresponding to 8 channels from 9ch to 16ch. The constant currents set to 1 are flowed through the LG1 terminal to the LG8 terminal, respectively, and the constant current driver 17 to the constant current driver 24 constitute a full-color LED that is a decorative LED corresponding to each of eight channels from 17ch to 24ch. A constant current set individually for each blue LED element is supplied via the LB1 to LB8 terminals.

In addition, by applying a control voltage DVp to the power supply terminal of the decoration LED driver IC that constitutes the game board side VDP control target first decoration LED control circuit 3420i1, various internal parts of the decoration LED driver IC are used as the internal power supply Vreg. When the GND terminal, which is a ground terminal, is supplied to the circuit and is grounded to the ground (GND), the ground in various internal circuits of the decorative LED driver IC is grounded to the ground (GND) of the liquid crystal output substrate 3420.

In this way, the decoration LED driver ICs configuring each of the game board side VDP control target first decoration LED control circuit 3420i1 to the game board side VDP control target 27th decoration LED control circuit 3420i27 have 24 LED elements. That is, since eight full-color LEDs, which are decorative LEDs, can be individually dimmed and turned on, such dimming and lighting can turn off, turn on one gradation, and blink one gradation. it can. Further, the decoration LED driver ICs configuring the first VDP control target decoration LED control circuit 3420i1 to the game board side VDP control target 27th decoration LED control circuit 3420i27 are 216 decorative LEDs ( = 8 full-color LEDs x 27 full-color LEDs of decorative LED control circuit (decorative LED driver IC), that is, 648 (= 3 LED elements of red, green, and blue x 216 full-color LEDs) It is possible to perform dimming lighting of a large number of decorative LEDs, which are the above-mentioned LED elements.

Further, the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 does not directly output the signals for individually performing the dimming lighting to the plurality of LEDs provided on each decorative board of the game board 4, respectively. The peripheral control MPU 4150a is a circuit different from the game board side VDP control target first decoration LED control circuit 3420i1 to the game board side VDP control target 27th decoration LED control circuit 3420i27 on each decoration board of the game board 4. By directly outputting the signals for individually performing the dimming lighting to the plurality of provided LEDs, the delicate dimming lighting of the plurality of LEDs, which is delicate and has a heavy processing load, is separated from the control by the peripheral control MPU4150a. The gaming board side VDP control target first decoration LED control circuit 3420i1 to the gaming board side VDP control target 27th decoration LED control circuit 3420i27 can be entrusted to each.

As described above, the light guide plate information and the electric decoration information are applied to each of the plurality of game board side VDP control target decoration boards, which are control objects to be directly controlled by the sound source built-in VDP 4160a, among the respective decoration boards of the game board 4. Plural stored in the liquid crystal and sound control ROM 4160b in advance as game board side light emission mode setting image data for setting the light emission modes of the provided LEDs (decorative LEDs). Then, the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140, among the decorative boards of the game board 4, a plurality of game board side VDP control target decorative boards which are control targets directly controlled by the sound source built-in VDP 4160a. The control with delicate processing load such as the dimming lighting of a plurality of LEDs (decorative LEDs) provided in each of the game board side VDP control target first decoration LED control circuit 3420i1 to game board side VDP control target Since it can be left to each of the 27 decorative LED control circuits 3420i27, it is possible to reduce the processing load of the light emission control of the dimming lighting on the peripheral control MPU 4150a. Thereby, even if the variation of the effect by the game board side VDP control target first decoration LED control circuit 3420i1 to the game board side VDP control target 27th decoration LED control circuit 3420i27 is increased, the peripheral control MPU4150a Since the processing load of light emission control such as dimming lighting does not increase, there are no restrictions on the variation of production. That is, in the present embodiment, it is possible to increase the variation of the effects while reducing the processing load of the light emission control on the peripheral control MPU 4150a, and thus it is possible to make it difficult for the player to lose interest in the effects. .. Therefore, it is possible to contribute to suppressing a decrease in interest.

Further, in the present embodiment, as described above, the game board side VDP control target first decoration LED control circuit 3420i1 to the game board side VDP control target 27th decoration LED control circuit 3420i27 is the game board side signal separation. When the serial data SDAT3 to serial data SDAT11 from the third serial controller 3420gd3 to the eleventh serial controller 3420gd11 in the control circuit 3420g are received based on the clock signal SCLK3 to the clock signal SCLK11, the illuminated LED designation in the serial data SDAT3 to serial data SDAT11 is performed. When the information does not include one's own ID, the gradation information in the serial data SDAT3 to the serial data SDAT11 is not taken in, and the control object directly controlled by the sound source built-in VDP 4160a among the respective decorative boards of the corresponding game board 4. The plurality of LEDs (ornamental LEDs) provided on each of the plurality of game board side VDP control target decorative boards are configured to maintain the gradation level, which is the gradation information captured last time.

Further, in the present embodiment, as described above, since the frame frequency is set to 30 fps (about every 33.3 ms), the drawing data is output to the liquid crystal output substrate 3420 from the channel CH1 of the sound source built-in VDP 4160a. There is. As a result, the game board side VDP control target first decoration LED control circuit 3420i1 to the game board side VDP control target twenty-seventh decoration LED control circuit 3420i27 is a gradation degree that is gradation information about every 33.3 ms. Since it is possible to repeatedly update, the gradation information in the drawing data output from the channel CH1 of the sound source built-in VDP 4160a is assumed to have changed from the normal content due to some electrical reason. Even if it is captured this time, the next time, that is, after about 33.3 ms has elapsed, the opportunity to capture the regular contents can be obtained, so that the sound source of each of the decorative boards of the game board 4 can be reproduced in an extremely short period of about 33.3 ms. The light emission mode of the plurality of LEDs (decorative LEDs) provided on each of the plurality of game board side VDP control target decorative substrates which are the control targets directly controlled by the built-in VDP 4160a is changed from the regular light emission mode to the unintended light emission mode. Even if the player does not notice the change, the normal light emission mode (that is, the normal light emission mode) can be corrected.

The game board side VDP control target first decoration LED control circuit 3420i1 to the game board side VDP control target 27th decoration LED control circuit 3420i27 is a back box of the back unit 3000 of the game board 4 shown in FIG. It is provided around the game board side VDP control target decorative substrate provided in the rotary light emitting device 3100 in 3001, and the rotary light emitting device 3100, the model 3400 imitating the detonator, and the model 3500 imitating dynamite in the back box 3001. The rotary type light emitting device 3100 emits light (decorative light emission mode) by performing dimming lighting of a plurality of LEDs (decorative LEDs) provided on the game board side VDP control target decorative substrate provided in each of the plurality of decorative members. In addition to the above, a plurality of decorative members are light-emitted.

In the embodiment, all the decoration LEDs whose emission mode is controlled by the game board side VDP control target first decoration LED control circuit 3420i1 to the game board side VDP control target 27th decoration LED control circuit 3420i27 are full color. Although the red LED element, the green LED element and the blue LED element which compose the LED are used, a single LED different from the full color LED (the same color LED may be used or different color LEDs) Alternatively, one group may be a full-color LED, and the other group may be a single LED (LEDs of the same color or LEDs of different colors). It is also possible to combine a plurality of one group and another group.

[12-2-3. Light guide plate information]
Here, a method for selecting one of the light guide plates included in the game board side effect display unit 1900 will be briefly described. As described above, the game board side effect display unit 1900 includes the first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000g, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and The sixth light guide plate 5000k is provided with a plurality of light guide plates.

As described above, the VDP 4160a including the liquid crystal in the peripheral control board 4140 and the sound control unit 4160 has screen data defining the configuration of the screen drawn on the game board side effect display unit 1900 (liquid crystal panel 5000e), and the game board. Of the four decorative boards, the light emitting modes of a plurality of LEDs (decorative LEDs) provided on each of the plurality of game board side VDP controlled decorative boards that are directly controlled by the sound source built-in VDP 4160a are defined. When the light emission data is input from the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140, the peripheral control board 4140 is based on the input screen data according to the predetermined game board side generation rule described above. From the liquid crystal and sound control ROM 4160b of the liquid crystal and sound control unit 4160, game board side character data for drawing in the display area of the game board side effect display unit 1900 is extracted to create sprite data and provided on the built-in VRAM. The game board side drawing data is generated in the game board side drawing data area VRGN1a of the game board side display area VRGN1, and based on the input light emission data, the liquid crystal and sound control ROM 4160b to each decorative board of the game board 4. Of these, the game board side for setting the light emission mode of the plurality of LEDs (decorative LEDs) provided on each of the plurality of game board side VDP control target decoration boards that are directly controlled by the sound source built-in VDP 4160a The light emission mode setting image data is extracted and the light guide plate information and the electric decoration information are generated as drawing data in the game board side accompanying information area VRGN1b of the game board side display area VRGN1 provided on the built-in VRAM.

As described above, the light guide plate information designates one of the plurality of light guide plates included in the game board side effect display unit 1900 that uses the light guide plate as a backlight (in other words, the game board side effect display unit 1900). It is information for selecting (switching) one light guide plate among the plurality of light guide plates provided in, and includes light guide plate designation information and luminance information.

[12-2-3a. Light Guide Plate Information When Selecting First Light Guide Plate]
For example, when the first light guide plate 5000d is selected (switched to the first light guide plate 5000d), the LEDs 5000d6 on the light guide plate upper decoration substrate 5000d1 and the light guide plate lower decoration substrate 5000d2 in the first light guide plate 5000d are turned on. Therefore, as the light guide plate information, the ID of the first light guide plate PWM control circuit 4950 of the first light guide plate control circuit 3420k1 included in the liquid crystal output substrate 3420 is set in the light guide plate designation information, and the brightness information is set. Is set as the maximum luminance (100%). At this time, the guides provided on the upper and lower end surfaces of the second light guide plate 5000f, the third light guide plate 5000g, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k, respectively. In order to turn off the respective LEDs 5000f6, 5000g6, 5000h6, 5000i6, 5000k6 of the decorative substrate on the light plate 5000f1, 5000g1, 5000h1, 5000i1, 5000k1 and the decorative substrate under the light guide plate 5000f2, 5000g2, 5000h2, 5000i2, 5000k2, as light guide plate information. In the light guide plate designation information, the second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2 provided in the liquid crystal output substrate 3420, and the third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3. A fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4, a fifth light guide plate PWM control circuit 4965 of the fifth light guide plate control circuit 3420k5, and a sixth light guide plate control circuit 3420k6 of the sixth light guide plate control circuit 3420k6. The ID of the light guide plate PWM control circuit 4975 of No. 6 is set, and the data for turning off the LED is set as the brightness information.

The sound source built-in VDP 4160a is a predetermined game board side generation rule in which the light guide plate information and the illumination information are added to the game board side drawing data of the screen drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). The drawing data generated in the game board side display area VRGN1 is output from the channel CH1.

The drawing data output from the channel CH1 is, as described above, in the game board side effect display unit 1900 (the liquid crystal display) in the first resolution conversion unit 3420gaa of the signal separation unit 3420ga in the game board side signal separation control circuit 3420g of the liquid crystal output substrate 3420. A plurality of pieces which are separated into the game board side drawing data for the panel 5000e) and are provided in the game board side effect display unit 1900 in the second resolution conversion section 3420gab of the signal separation section 3420ga in the game board side signal separation control circuit 3420g of the liquid crystal output substrate 3420. The light guide plate information for selecting one light guide plate among the light guide plates, and of each of the decoration boards of the game board 4, the plurality of game board side VDP control target decoration boards that are directly controlled by the sound source built-in VDP 4160a. It is separated into electric decoration information for a plurality of LEDs (decorative LEDs) provided for each. Based on the clock signal SCLK1 from the first serial controller 3420gd1 as serial data SDAT1, the separated light guide plate information is controlled by the first light guide plate PWM control circuit 4950 and the second light guide plate control circuit 3420k1. The second light guide plate PWM control circuit 4960 of the circuit 3420k2 and the third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3 output the clock signal SCLK2 as serial data SDAT2 from the second serial controller 3420gd2. Based on the fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4, the fifth light guide plate PWM control circuit 4965 of the fifth light guide plate control circuit 3420k5, and the sixth light guide plate control circuit 3420k6. Output to the sixth light guide plate PWM control circuit 4975.

Accordingly, the first light guide plate PWM control circuit 4950 of the first light guide plate control circuit 3420k1 sets the duty ratio of the first light guide plate PWM signal so that the brightness of the LED becomes the maximum brightness (100%). Control to output to the LED driver IC 4810 of the first light guide plate control circuit 3420k1, and the second light guide plate PWM control circuit 4960 and the third light guide plate control circuit 3420k3 of the second light guide plate control circuit 3420k2. Third light guide plate PWM control circuit 4970, fourth light guide plate control circuit 3420k4 fourth light guide plate PWM control circuit 4955, fifth light guide plate control circuit 3420k5 fifth light guide plate PWM control circuit 4965 and sixth The sixth light guide plate PWM control circuit 4975 of the light guide plate control circuit 3420k6 of the second light guide plate PWM control circuit 4975 sets the duty ratios of the second light guide plate PWM signal to the sixth light guide plate PWM signal to 0%, respectively. LED driver IC 4830 of light plate control circuit 3420k2, LED driver IC 4850 of third light guide plate control circuit 3420k3, LED driver IC 4815 of fourth light guide plate control circuit 3420k4, LED driver IC 4835 of fifth light guide plate control circuit 3420k5, sixth The output control is performed to the LED driver IC 4855 of the light guide plate control circuit 3420k6.

[12-2-3b. Light Guide Plate Information When Selecting Second Light Guide Plate]
For example, when the second light guide plate 5000f is selected (switched to the second light guide plate 5000f), the LEDs 5000f6 of the light guide plate upper decoration substrate 5000f1 and the light guide plate lower decoration substrate 5000f2 of the second light guide plate 5000f are turned on. Therefore, as the light guide plate information, the ID of the second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2 included in the liquid crystal output substrate 3420 is set in the light guide plate designation information, and the brightness information is set. Is set as the maximum luminance (100%). At this time, the guides provided on the upper and lower end surfaces of the first light guide plate 5000d, the third light guide plate 5000g, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k, respectively. In order to turn off each LED 5000d6, 5000g6, 5000h6, 5000i6, 5000k6 of the decorative substrate 5000d1, 5000g1, 5000h1, 5000i1, 5000k1 on the light plate and the decorative substrate 5000d2, 5000g2, 5000h2, 5000i2, 5000k2 under the light guide plate, as light guide plate information. In the light guide plate designation information, the first light guide plate PWM control circuit 4950 of the first light guide plate control circuit 3420k1 and the third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3 included in the liquid crystal output substrate 3420. A fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4, a fifth light guide plate PWM control circuit 4965 of the fifth light guide plate control circuit 3420k5, and a sixth light guide plate control circuit 3420k6 of the sixth light guide plate control circuit 3420k6. The ID of the light guide plate PWM control circuit 4975 of No. 6 is set, and the data for turning off the LED is set as the brightness information.

The sound source built-in VDP 4160a is a predetermined game board side generation rule in which the light guide plate information and the illumination information are added to the game board side drawing data of the screen drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). The drawing data generated in the game board side display area VRGN1 is output from the channel CH1.

The drawing data output from the channel CH1 is, as described above, in the game board side effect display unit 1900 (the liquid crystal display) in the first resolution conversion unit 3420gaa of the signal separation unit 3420ga in the game board side signal separation control circuit 3420g of the liquid crystal output substrate 3420. A plurality of pieces which are separated into the game board side drawing data for the panel 5000e) and are provided in the game board side effect display unit 1900 in the second resolution conversion section 3420gab of the signal separation section 3420ga in the game board side signal separation control circuit 3420g of the liquid crystal output substrate 3420. The light guide plate information for selecting one light guide plate among the light guide plates, and of each of the decoration boards of the game board 4, the plurality of game board side VDP control target decoration boards that are directly controlled by the sound source built-in VDP 4160a. It is separated into electric decoration information for a plurality of LEDs (decorative LEDs) provided for each. Based on the clock signal SCLK1 from the first serial controller 3420gd1 as serial data SDAT1, the separated light guide plate information is controlled by the first light guide plate PWM control circuit 4950 and the second light guide plate control circuit 3420k1. The second light guide plate PWM control circuit 4960 of the circuit 3420k2 and the third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3 output the clock signal SCLK2 as serial data SDAT2 from the second serial controller 3420gd2. Based on the fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4, the fifth light guide plate PWM control circuit 4965 of the fifth light guide plate control circuit 3420k5, and the sixth light guide plate control circuit 3420k6. Output to the sixth light guide plate PWM control circuit 4975.

As a result, the second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2 sets the duty ratio of the second light guide plate PWM signal so that the LED brightness becomes the maximum brightness (100%). And controls the output to the LED driver IC 4830 of the second light guide plate control circuit 3420k2, and controls the first light guide plate PWM control circuit 4950 and the third light guide plate control circuit 3420k3 of the first light guide plate control circuit 3420k1. Third light guide plate PWM control circuit 4970, fourth light guide plate control circuit 3420k4 fourth light guide plate PWM control circuit 4955, fifth light guide plate control circuit 3420k5 fifth light guide plate PWM control circuit 4965 and sixth The sixth light guide plate PWM control circuit 4975 of the light guide plate control circuit 3420k6 is configured so that the duty ratio of the first light guide plate PWM signal, the third light guide plate PWM signal to the sixth light guide plate PWM signal is 0%. To the LED driver IC 4810 of the first light guide plate control circuit 3420k2, the LED driver IC 4850 of the third light guide plate control circuit 3420k3, the LED driver IC 4815 of the fourth light guide plate control circuit 3420k4, and the fifth light guide plate control. The output control is performed to the LED driver IC 4835 of the circuit 3420k5 and the LED driver IC 4855 of the sixth light guide plate control circuit 3420k6.

[12-2-3c. Light Guide Plate Information When Selecting Third Light Guide Plate]
For example, when the third light guide plate 5000g is selected (switched to the third light guide plate 5000g), each LED 5000g6 of the light guide plate upper decorative substrate 5000g1 and the light guide plate lower decorative substrate 5000g2 in the third light guide plate 5000g is turned on. Therefore, as the light guide plate information, the ID of the third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3 included in the liquid crystal output substrate 3420 is set in the light guide plate designation information, and the brightness information is set. As data, the data that sets the brightness of the LED to the maximum brightness (100%) is set. At this time, the first light guide plate 5000d, the second light guide plate 5000f, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k are provided on the respective upper and lower end surfaces. In order to turn off the respective LEDs 5000d6, 5000f6, 5000h6, 5000i6, 5000k6 of the decorative substrate 5000d1, 5000f1, 5000h1, 5000i1, 5000k1 on the light plate and the decorative substrates 5000d2, 5000f2, 5000h2, 5000i2, 5000k2 under the light guide plate, as light guide plate information. In the light guide plate designation information, the first light guide plate PWM control circuit 4950 of the first light guide plate control circuit 3420k1 and the second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2 included in the liquid crystal output substrate 3420. A fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4, a fifth light guide plate PWM control circuit 4965 of the fifth light guide plate control circuit 3420k5, and a sixth light guide plate control circuit 3420k6 of the sixth light guide plate control circuit 3420k6. The ID of the light guide plate PWM control circuit 4975 of No. 6 is set, and the data for turning off the LED is set as the brightness information.

The sound source built-in VDP 4160a is a predetermined game board side generation rule in which the light guide plate information and the illumination information are added to the game board side drawing data of the screen drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). The drawing data generated in the game board side display area VRGN1 is output from the channel CH1.

The drawing data output from the channel CH1 is, as described above, in the game board side effect display unit 1900 (the liquid crystal display) in the first resolution conversion unit 3420gaa of the signal separation unit 3420ga in the game board side signal separation control circuit 3420g of the liquid crystal output substrate 3420. A plurality of pieces which are separated into the game board side drawing data for the panel 5000e) and are provided in the game board side effect display unit 1900 in the second resolution conversion section 3420gab of the signal separation section 3420ga in the game board side signal separation control circuit 3420g of the liquid crystal output substrate 3420. The light guide plate information for selecting one light guide plate among the light guide plates, and of each of the decoration boards of the game board 4, the plurality of game board side VDP control target decoration boards that are directly controlled by the sound source built-in VDP 4160a. It is separated into electric decoration information for a plurality of LEDs (decorative LEDs) provided for each. Based on the clock signal SCLK1 from the first serial controller 3420gd1 as serial data SDAT1, the separated light guide plate information is controlled by the first light guide plate PWM control circuit 4950 and the second light guide plate control circuit 3420k1. The second light guide plate PWM control circuit 4960 of the circuit 3420k2 and the third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3 output the clock signal SCLK2 as serial data SDAT2 from the second serial controller 3420gd2. Based on the fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4, the fifth light guide plate PWM control circuit 4965 of the fifth light guide plate control circuit 3420k5, and the sixth light guide plate control circuit 3420k6. Output to the sixth light guide plate PWM control circuit 4975.

Thereby, the third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3 sets the duty ratio of the third light guide plate PWM signal so that the brightness of the LED becomes the maximum brightness (100%). And controls the output to the LED driver IC 4850 of the third light guide plate control circuit 3420k3, and controls the first light guide plate PWM control circuit 4950 and the second light guide plate control circuit 3420k2 of the first light guide plate control circuit 3420k1. Second light guide plate PWM control circuit 4960, fourth light guide plate control circuit 3420k4 fourth light guide plate PWM control circuit 4955, fifth light guide plate control circuit 3420k5 fifth light guide plate PWM control circuit 4965 and sixth The sixth light guide plate PWM control circuit 4975 of the light guide plate control circuit 3420k6 includes a first light guide plate PWM signal, a second light guide plate PWM signal, a fourth light guide plate PWM signal to a sixth light guide plate. The duty ratio of the PWM signal for use is set to 0% and the LED driver IC 4810 of the first light guide plate control circuit 3420k2, the LED driver IC 4830 of the second light guide plate control circuit 3420k2, and the LED of the fourth light guide plate control circuit 3420k4 are set. Output control is performed to the driver IC 4815, the LED driver IC 4835 of the fifth light guide plate control circuit 3420k5, and the LED driver IC 4855 of the sixth light guide plate control circuit 3420k6.

[12-2-3d. Light Guide Plate Information When Selecting Fourth Light Guide Plate]
For example, when the fourth light guide plate 5000h is selected (switched to the fourth light guide plate 5000h), the LEDs 5000h6 of the light guide plate upper decorative substrate 5000h1 and the light guide plate lower decorative substrate 5000h2 in the fourth light guide plate 5000h are turned on. Therefore, as the light guide plate information, the ID of the fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4 provided in the liquid crystal output substrate 3420 is set in the light guide plate designation information, and the brightness information is set. As data, the data that sets the brightness of the LED to the maximum brightness (100%) is set. At this time, the first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000g, the fifth light guide plate 5000i, and the sixth light guide plate 5000k are provided on the respective upper and lower end surfaces. In order to turn off each LED 5000d6, 5000f6, 5000g6, 5000i6, 5000k6 of the decorative substrate on the light plate 5000d1, 5000f1, 5000g1, 5000i1, 5000k1, and the decorative substrate under the light guide plate 5000d2, 5000f2, 5000g2, 5000i2, 5000k2, as light guide plate information. In the light guide plate designation information, the first light guide plate PWM control circuit 4950 of the first light guide plate control circuit 3420k1 and the second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2 included in the liquid crystal output substrate 3420. A third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3, a fifth light guide plate PWM control circuit 4965 of the fifth light guide plate control circuit 3420k5, and a sixth light guide plate control circuit 3420k6 of the sixth light guide plate control circuit 3420k6. The ID of the light guide plate PWM control circuit 4975 of No. 6 is set, and the data for turning off the LED is set as the brightness information.

The sound source built-in VDP 4160a is a predetermined game board side generation rule in which the light guide plate information and the illumination information are added to the game board side drawing data of the screen drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). The drawing data generated in the game board side display area VRGN1 is output from the channel CH1.

The drawing data output from the channel CH1 is, as described above, in the game board side effect display unit 1900 (the liquid crystal display) in the first resolution conversion unit 3420gaa of the signal separation unit 3420ga in the game board side signal separation control circuit 3420g of the liquid crystal output substrate 3420. A plurality of pieces which are separated into the game board side drawing data for the panel 5000e) and are provided in the game board side effect display unit 1900 in the second resolution conversion section 3420gab of the signal separation section 3420ga in the game board side signal separation control circuit 3420g of the liquid crystal output substrate 3420. The light guide plate information for selecting one light guide plate among the light guide plates, and of each of the decoration boards of the game board 4, the plurality of game board side VDP control target decoration boards that are directly controlled by the sound source built-in VDP 4160a. It is separated into electric decoration information for a plurality of LEDs (decorative LEDs) provided for each. Based on the clock signal SCLK1 from the first serial controller 3420gd1 as serial data SDAT1, the separated light guide plate information is controlled by the first light guide plate PWM control circuit 4950 and the second light guide plate control circuit 3420k1. The second light guide plate PWM control circuit 4960 of the circuit 3420k2 and the third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3 output the clock signal SCLK2 as serial data SDAT2 from the second serial controller 3420gd2. Based on the fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4, the fifth light guide plate PWM control circuit 4965 of the fifth light guide plate control circuit 3420k5, and the sixth light guide plate control circuit 3420k6. Output to the sixth light guide plate PWM control circuit 4975.

Accordingly, the fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4 sets the duty ratio of the fourth light guide plate PWM signal so that the brightness of the LED becomes the maximum brightness (100%). Then, while controlling to output to the LED driver IC 4815 of the fourth light guide plate control circuit 3420k4, the first light guide plate PWM control circuit 4950 and the second light guide plate control circuit 3420k2 of the first light guide plate control circuit 3420k1 are controlled. Second light guide plate PWM control circuit 4960, third light guide plate control circuit 3420k3 third light guide plate PWM control circuit 4970, fifth light guide plate control circuit 3420k5 fifth light guide plate PWM control circuit 4965 and sixth The sixth light guide plate PWM control circuit 4975 of the light guide plate control circuit 3420k6 includes a first light guide plate PWM signal to a third light guide plate PWM signal, a fifth light guide plate PWM signal, and a sixth light guide plate PWM signal. The duty ratio of the PWM signal for use is set to 0% and the LED driver IC 4810 of the first light guide plate control circuit 3420k2, the LED driver IC 4830 of the second light guide plate control circuit 3420k2, and the LED of the third light guide plate control circuit 3420k3 are set. The output control is performed to the driver IC 4850, the LED driver IC 4835 of the fifth light guide plate control circuit 3420k5, and the LED driver IC 4855 of the sixth light guide plate control circuit 3420k6.

[12-2-3e. Light Guide Plate Information When Selecting Fifth Light Guide Plate]
For example, when the fifth light guide plate 5000i is selected (switched to the fifth light guide plate 5000i), each LED 5000i6 of the light guide plate upper decorative substrate 5000i1 and the light guide plate lower decorative substrate 5000i2 in the fifth light guide plate 5000i is turned on. Therefore, as the light guide plate information, the ID of the fifth light guide plate PWM control circuit 4965 of the fifth light guide plate control circuit 3420k5 provided in the liquid crystal output substrate 3420 is set in the light guide plate designation information, and the brightness information is set. Is set as the maximum luminance (100%). At this time, the first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000g, the fourth light guide plate 5000h, and the sixth light guide plate 5000k are respectively provided on the upper end surface and the lower end surface thereof. In order to turn off the respective LEDs 5000d6, 5000f6, 5000g6, 5000h6, 5000k6 of the decorative substrate 5000d1, 5000f1, 5000g1, 5000h1, 5000k1 on the light plate and the decorative substrate 5000d2, 5000f2, 5000g2, 5000h2, 5000k2 under the light guide plate, as light guide plate information. In the light guide plate designation information, the first light guide plate PWM control circuit 4950 of the first light guide plate control circuit 3420k1 and the second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2 included in the liquid crystal output substrate 3420. , A third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3, a fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4, and a sixth light guide plate control circuit 3420k6. The ID of the light guide plate PWM control circuit 4975 of No. 6 is set, and the data for turning off the LED is set as the brightness information.

The sound source built-in VDP 4160a is a predetermined game board side generation rule in which the light guide plate information and the illumination information are added to the game board side drawing data of the screen drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). The drawing data generated in the game board side display area VRGN1 is output from the channel CH1.

The drawing data output from the channel CH1 is, as described above, in the game board side effect display unit 1900 (the liquid crystal display) in the first resolution conversion unit 3420gaa of the signal separation unit 3420ga in the game board side signal separation control circuit 3420g of the liquid crystal output substrate 3420. A plurality of pieces which are separated into the game board side drawing data for the panel 5000e) and are provided in the game board side effect display unit 1900 in the second resolution conversion section 3420gab of the signal separation section 3420ga in the game board side signal separation control circuit 3420g of the liquid crystal output substrate 3420. The light guide plate information for selecting one light guide plate among the light guide plates, and of each of the decoration boards of the game board 4, the plurality of game board side VDP control target decoration boards that are directly controlled by the sound source built-in VDP 4160a. It is separated into electric decoration information for a plurality of LEDs (decorative LEDs) provided for each. Based on the clock signal SCLK1 from the first serial controller 3420gd1 as serial data SDAT1, the separated light guide plate information is controlled by the first light guide plate PWM control circuit 4950 and the second light guide plate control circuit 3420k1. The second light guide plate PWM control circuit 4960 of the circuit 3420k2 and the third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3 output the clock signal SCLK2 as serial data SDAT2 from the second serial controller 3420gd2. Based on the fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4, the fifth light guide plate PWM control circuit 4965 of the fifth light guide plate control circuit 3420k5, and the sixth light guide plate control circuit 3420k6. Output to the sixth light guide plate PWM control circuit 4975.

Thereby, the fifth light guide plate PWM control circuit 4965 of the fifth light guide plate control circuit 3420k5 sets the duty ratio of the fifth light guide plate PWM signal so that the brightness of the LED becomes the maximum brightness (100%). Then, the control is performed to output to the LED driver IC 4835 of the fifth light guide plate control circuit 3420k5, and the first light guide plate PWM control circuit 4950 and the second light guide plate control circuit 3420k2 of the first light guide plate control circuit 3420k1 are operated. Second light guide plate PWM control circuit 4960, third light guide plate control circuit 3420k3 third light guide plate PWM control circuit 4970, fourth light guide plate control circuit 3420k4 fourth light guide plate PWM control circuit 4955 and sixth The sixth light guide plate PWM control circuit 4975 of the light guide plate control circuit 3420k6 is configured so that the duty ratio of the first light guide plate PWM signal to the fourth light guide plate PWM signal and the sixth light guide plate PWM signal is 0%. To the LED driver IC 4810 of the first light guide plate control circuit 3420k2, the LED driver IC 4830 of the second light guide plate control circuit 3420k2, the LED driver IC 4850 of the third light guide plate control circuit 3420k3, and the fourth light guide plate control. The output control is performed to the LED driver IC 4815 of the circuit 3420k4 and the LED driver IC 4855 of the sixth light guide plate control circuit 3420k6.

[12-2-3f. Light Guide Plate Information When Selecting Sixth Light Guide Plate]
For example, when the sixth light guide plate 5000k is selected (switched to the sixth light guide plate 5000k), each LED 5000k6 of the light guide plate upper decoration substrate 5000k1 and the light guide plate lower decoration substrate 5000k2 in the sixth light guide plate 5000k is turned on. Therefore, as the light guide plate information, the ID of the sixth light guide plate PWM control circuit 4975 of the sixth light guide plate control circuit 3420k6 included in the liquid crystal output substrate 3420 is set in the light guide plate designation information, and the brightness information is set. Is set as the maximum luminance (100%). At this time, the first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000g, the fourth light guide plate 5000h, and the fifth light guide plate 5000i are provided on the respective upper and lower end surfaces. In order to turn off each LED 5000d6, 5000f6, 5000g6, 5000h6, 5000i6 of the decorative substrate 5000d1, 5000f1, 5000g1, 5000h1, 5000i1 on the light plate, and the decorative substrate 5000d2, 5000f2, 5000g2, 5000h2, 5000i2 under the light guide plate, as light guide plate information. In the light guide plate designation information, the first light guide plate PWM control circuit 4950 of the first light guide plate control circuit 3420k1 and the second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2 included in the liquid crystal output substrate 3420. , A third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3, a fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4, and a fifth light guide plate control circuit 3420k5 of the fifth light guide plate control circuit 3420k5. 5, the ID of the light guide plate PWM control circuit 4965 is set, and the data for turning off the LED is set as the brightness information.

The sound source built-in VDP 4160a is a predetermined game board side generation rule in which the light guide plate information and the illumination information are added to the game board side drawing data of the screen drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). The drawing data generated in the game board side display area VRGN1 is output from the channel CH1.

The drawing data output from the channel CH1 is, as described above, in the game board side effect display unit 1900 (the liquid crystal display) in the first resolution conversion unit 3420gaa of the signal separation unit 3420ga in the game board side signal separation control circuit 3420g of the liquid crystal output substrate 3420. A plurality of pieces which are separated into the game board side drawing data for the panel 5000e) and are provided in the game board side effect display unit 1900 in the second resolution conversion section 3420gab of the signal separation section 3420ga in the game board side signal separation control circuit 3420g of the liquid crystal output substrate 3420. The light guide plate information for selecting one light guide plate among the light guide plates, and of each of the decoration boards of the game board 4, the plurality of game board side VDP control target decoration boards that are directly controlled by the sound source built-in VDP 4160a. It is separated into electric decoration information for a plurality of LEDs (decorative LEDs) provided for each. Based on the clock signal SCLK1 from the first serial controller 3420gd1 as serial data SDAT1, the separated light guide plate information is controlled by the first light guide plate PWM control circuit 4950 and the second light guide plate control circuit 3420k1. The second light guide plate PWM control circuit 4960 of the circuit 3420k2 and the third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3 output the clock signal SCLK2 as serial data SDAT2 from the second serial controller 3420gd2. Based on the fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4, the fifth light guide plate PWM control circuit 4965 of the fifth light guide plate control circuit 3420k5, and the sixth light guide plate control circuit 3420k6. Output to the sixth light guide plate PWM control circuit 4975.

Accordingly, the sixth light guide plate PWM control circuit 4975 of the sixth light guide plate control circuit 3420k6 sets the duty ratio of the sixth light guide plate PWM signal so that the brightness of the LED becomes the maximum brightness (100%). Then, the control is performed to output to the LED driver IC 4855 of the sixth light guide plate control circuit 3420k6, and the first light guide plate PWM control circuit 4950 and the second light guide plate control circuit 3420k2 of the first light guide plate control circuit 3420k1 are controlled. Second light guide plate PWM control circuit 4960, third light guide plate control circuit 3420k3 third light guide plate PWM control circuit 4970, fourth light guide plate control circuit 3420k4 fourth light guide plate PWM control circuit 4955 and fifth The fifth light guide plate PWM control circuit 4965 of the light guide plate control circuit 3420k5 of the first light guide plate PWM control circuit 4965 sets the duty ratios of the first light guide plate PWM signal to the fifth light guide plate PWM signal to 0%, and sets the first light guide plate PWM signal to 0%. LED driver IC 4810 of light plate control circuit 3420k2, LED driver IC 4830 of second light guide plate control circuit 3420k2, LED driver IC 4850 of third light guide plate control circuit 3420k3, LED driver IC 4815 of fourth light guide plate control circuit 3420k4, fifth Output control to the LED driver IC 4835 of the light guide plate control circuit 3420k5.

[12-2-4. Light guide plate for power recovery]
Here, when the power is turned on, when a power failure occurs and the power is restored after that, and when the power is restored momentarily due to a power failure (at a momentary power failure), the game board side effect The point that a specific light guide plate is selected as the power recovery time light guide plate among the plurality of light guide plates included in the display unit 1900 will be briefly described.

The peripheral control board 4140 surface-emits the first light guide plate 5000d so that the first light guide plate 5000d is selected as the power recovery light guide plate, while the other light guide plates (the second light guide plate 5000f, The control for turning off all of the third light guide plate 5000g, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k is performed on the VDP 4160a with a built-in sound source. That is, as described above, when the first light guide plate 5000d is selected (switched to the first light guide plate 5000d), the light guide plate upper decorative substrate 5000d1 and the light guide plate lower decorative substrate 5000d2 in the first light guide plate 5000d. In order to turn on each of the LEDs 5000d6, the ID of the first light guide plate PWM control circuit 4950 of the first light guide plate control circuit 3420k1 provided in the liquid crystal output substrate 3420 is set in the light guide plate designation information as the light guide plate information. In addition, as the brightness information, data that sets the brightness of the LED to the maximum brightness (100%) is set. At this time, the second light guide plate 5000f, the third light guide plate 5000g, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k are provided on the respective upper and lower end surfaces. In order to turn off the respective LEDs 5000f6, 5000g6, 5000h6, 5000i6, 5000k6 of the decorative substrate on the light plate 5000f1, 5000g1, 5000h1, 5000i1, 5000k1 and the decorative substrate under the light guide plate 5000f2, 5000g2, 5000h2, 5000i2, 5000k2, as light guide plate information. In the light guide plate designation information, the second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2 provided in the liquid crystal output substrate 3420 and the third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3. A fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4, a fifth light guide plate PWM control circuit 4965 of the fifth light guide plate control circuit 3420k5, and a sixth light guide plate control circuit 3420k6 of the sixth light guide plate control circuit 3420k6. The ID of the light guide plate PWM control circuit 4975 of No. 6 is set, and the data for turning off the LED is set as the brightness information.

The sound source built-in VDP 4160a is a predetermined game board side generation rule in which the light guide plate information and the illumination information are added to the game board side drawing data of the screen drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). The drawing data generated in the game board side display area VRGN1 is output from the channel CH1.

The drawing data output from the channel CH1 is, as described above, in the game board side effect display unit 1900 (the liquid crystal display) in the first resolution conversion unit 3420gaa of the signal separation unit 3420ga in the game board side signal separation control circuit 3420g of the liquid crystal output substrate 3420. A plurality of pieces which are separated into the game board side drawing data for the panel 5000e) and are provided in the game board side effect display unit 1900 in the second resolution conversion section 3420gab of the signal separation section 3420ga in the game board side signal separation control circuit 3420g of the liquid crystal output substrate 3420. The light guide plate information for selecting one light guide plate among the light guide plates, and of each of the decoration boards of the game board 4, the plurality of game board side VDP control target decoration boards that are directly controlled by the sound source built-in VDP 4160a. It is separated into electric decoration information for a plurality of LEDs (decorative LEDs) provided for each. Based on the clock signal SCLK1 from the first serial controller 3420gd1 as serial data SDAT1, the separated light guide plate information is controlled by the first light guide plate PWM control circuit 4950 and the second light guide plate control circuit 3420k1. The second light guide plate PWM control circuit 4960 of the circuit 3420k2 and the third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3 output the clock signal SCLK2 as serial data SDAT2 from the second serial controller 3420gd2. Based on the fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4, the fifth light guide plate PWM control circuit 4965 of the fifth light guide plate control circuit 3420k5, and the sixth light guide plate control circuit 3420k6. Output to the sixth light guide plate PWM control circuit 4975.

Accordingly, the first light guide plate PWM control circuit 4950 of the first light guide plate control circuit 3420k1 sets the duty ratio of the first light guide plate PWM signal so that the brightness of the LED becomes the maximum brightness (100%). Then, the output control to the LED driver IC 4810 of the first light guide plate control circuit 3420k1 is performed. The first light guide plate 5000d and other light guide plates (second light guide plate 5000f, third light guide plate 5000g, fourth light guide plate 5000h, fifth light guide plate 5000i, and sixth light guide plate 5000k) are included. In contrast, since the entire surface is formed as the light emitting area 5000d4, the non-light emitting area is not formed, and the area behind the non-light emitting area of the first light guide plate 5000d cannot be visually recognized.

The second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2, the third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3, and the fourth light guide plate control circuit 3420k4 of the fourth light guide plate control circuit 3420k4. The fourth light guide plate PWM control circuit 4955, the fifth light guide plate control circuit 3420k5, the fifth light guide plate PWM control circuit 4965, and the sixth light guide plate control circuit 3420k6, the sixth light guide plate PWM control circuit 4975, LED driver IC 4830 of the second light guide plate control circuit 3420k2 and the LED driver of the third light guide plate control circuit 3420k3 by setting the duty ratios of the light guide plate PWM signal to the sixth light guide plate PWM signal to 0%. Control is performed to output to the IC 4850, the LED driver IC 4815 of the fourth light guide plate control circuit 3420k4, the LED driver IC 4835 of the fifth light guide plate control circuit 3420k5, and the LED driver IC 4855 of the sixth light guide plate control circuit 3420k6.

Light emitting area 5000f4 of second light guide plate 5000f, light emitting area 5000g4 of third light guide plate 5000g, light emitting area 5000h4 of fourth light guide plate 5000h, light emitting area 5000i4 of fifth light guide plate 5000i, and sixth light guide plate Since all the light emitting areas 5000k4 of 5000k are extinguished, the rear can be visually recognized in the entire light emitting area 5000f4 and the non-light emitting area 5000f3 of the second light guide plate 5000f, and the light emitting area of the third light guide plate 5000g. The rear can be made visible in the entire area of 5000g4 and the non-light emitting area 5000g3, and the rear can be made visible in the entire area of the light emitting area 5000h4 and the non-light emitting area 5000h3 of the fourth light guide plate 5000h. , The rear can be visually recognized in the entire area of the light emitting area 5000i4 and the non-light emitting area 5000i3 of the fifth light guide plate 5000i, and the entire area of the light emitting area 5000k4 and the non-light emitting area 5000k3 of the sixth light guide plate 5000k. The rear can be visually recognized in.

At this time, the game board side drawing data separated in the first resolution converter 3420gaa of the signal separator 3420ga is transferred to the game board side effect display unit 1900 (liquid crystal panel) via the game board side liquid crystal drive circuit 3420h in the liquid crystal output substrate 3420. It is output to 5000e). As a result, in the liquid crystal panel 5000e, in a region corresponding to the light emitting region 5000d4 of the first light guide plate 5000d described above, the background color of the entire region is black as a power-on effect image for power recovery. The white letters are displayed.

In the present embodiment, when one light guide plate is selected from the plurality of light guide plates included in the game board side effect display unit 1900, the light guide plate upper decorative board and the light guide plate lower decorative board in the one light guide plate are selected. In order to turn on each of the LEDs, data that sets the brightness of the LED to the maximum brightness (100%) is set, but the brightness of the LED is set in advance from the maximum brightness (100%) to the minimum brightness (1%). It may be data for dimming to one high brightness in the determined high brightness side range (for example, 100% to 75%).

Further, in the present embodiment, when one light guide plate is selected from the plurality of light guide plates included in the game board side effect display unit 1900, the other light guide plates are guided so as to turn off the other light guide plates that are not selected. The LEDs on the decorative board above the light plate and the decorative board below the light guide plate are turned off, but the brightness of the LEDs is set to a predetermined low brightness side range from the minimum brightness (1%) to the maximum brightness (100%) (for example, 1% to 5%), it may be data for dimming to one low luminance. In this way, even if one light guide plate is selected from the plurality of light guide plates included in the game board side effect display unit 1900, each of the light guide plate upper decorative substrate and the light guide plate lower decorative substrate in the selected one light guide plate is selected. Although the brightness of the LED is different from the brightness of each LED on the light guide plate upper decorative substrate and the light guide plate lower decorative substrate in the other light guide plates that are not selected, a plurality of guides included in the game board side effect display unit 1900 are provided. Since the LEDs of the light guide plate upper decoration substrate and the light guide plate lower decoration substrate in the light plate can be configured to be turned on, the first light guide plate 5000d, the second light guide plate 5000f, and the third light guide plate 5000g. , The fourth light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k, the light guide plate is selected exclusively for the light guide plate. Even if the time when each LED of the lower decorative substrate is turned on becomes long, the first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000g, the fourth light guide plate 5000h, and the fifth light guide plate. It is possible to match the life times of the respective LEDs of the light guide plate upper decoration substrate and the light guide plate lower decoration substrate in the 5000i and the sixth light guide plate 5000k.

In addition, among the first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000g, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k, the light guide plate not selected is selected. The light plate is not selected because the brightness of the LED is adjusted to the minimum brightness (1%) or one of the predetermined low brightness side ranges in order to perform standby lighting in the standby state. The light emitted by the light guide plate appears to the user as a state in which it is difficult for the user to visually recognize it, that is, the light guide plate that is not selected is turned off and can be visually recognized by the user as a transparent state in which the rear side thereof can be visually recognized.

[13. Circuit of lamp drive board]
Next, the circuit of the lamp driving substrate 4170 shown in FIG. 17 will be described with reference to FIG. FIG. 38 is a block diagram of a game board side peripheral control MPU control target decoration LED control circuit. As shown in FIG. 38, the lamp drive board 4170 has a gaming board side peripheral control MPU control target decoration LED control circuit 4170k, the gaming board side peripheral control MPU control target first decoration LED control circuit 4170k1 to gaming board side. Peripheral control MPU control target Eighth decoration LED control circuit 4170k8 (8 circuits in total) is provided.

As described above, the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 outputs the game board side light emission data SL-DAT from the game board side decoration board serial I/O port to the game board side light emission clock signal SL-. Output to the lamp driving board 4170 in synchronization with CLK.

The game board side light emission data SL-DAT and the game board side light emission clock signal SL-CLK from the game board side decoration board serial I/O port of the peripheral board MPU4150a are the game board side peripheral control MPU control object decoration LED control. The game board side peripheral control MPU control object 1st decoration LED control circuit 4170k1 to the game board side peripheral control MPU control object 8th decoration LED control circuit 4170k8 which comprise the circuit 4170k are input, respectively. Game board side peripheral control MPU control target first decoration LED control circuit 4170k1 to game board side peripheral control MPU control target eighth decoration LED control circuit 4170k8 is electrically connected as one serial connection (one serial system) The circuit configuration is connected to.

In the present embodiment, the game board side peripheral control MPU control target first decoration LED control circuit 4170k1 to the game board side peripheral control MPU control target eighth decoration LED control circuit 4170k8 are from the same decoration LED driver IC. Of each of the decorative boards of the game board 4, a plurality of LEDs provided on each of the plurality of gaming board-side peripheral control MPU control target decorative boards that are directly controlled by the peripheral control MPU 4150a. Light emitted by a decorative LED can be dimmed and turned on. Here, the game board side peripheral control MPU control target first decoration LED control circuit 4170k1 will be briefly described below, and the game board side peripheral control MPU control target second decoration LED control circuit 4170k1 to game board side peripheral The description of the control MPU control target eighth decorative LED control circuit 4170k8 is omitted.

First, the game board side light emission data SL-DAT will be described. The "gaming board side light emission data" is information for designating the light emission mode, and is composed of illumination LED designation information and gradation information. The illumination LED designation information is the gaming board side peripheral control MPU control target first decoration LED control circuit 4170k1 to gaming board side peripheral control MPU control target eighth decoration LED control circuit 4170k8, which gaming board side Peripheral control MPU is information indicating whether or not to specify an LED control circuit for decorative decoration, and an address (ID described later) for identifying an individual LED control circuit for peripheral control MPU controlled object decoration on the game board side It is set. The gradation information is information indicating which of the gradation 0 (zero) to the gradation 127 is to be specified.

As shown in FIG. 38, the decoration LED driver IC that constitutes the first decoration LED control circuit 4170k1 for the game board side peripheral control MPU control target has 24 output channels (ch), and a maximum of 80 mA for each channel. It is a constant current LED driver IC of 24ch that can output a current of (milliampere). This decorative LED driver IC mainly includes an address setting unit 4170k1a, a logic processing unit 4170k1b, a clock generating unit 4170k1c, a data buffer unit 4170k1d, a PWM unit 4170k1e, and a constant current driving unit 4170k1f.

The address setting unit 4170k1a can set 64 types of addresses as its own IDs (IDs that can identify the individual) by the voltages applied to six device address selection terminals (not shown). The voltage applied to the six device address selection terminals is either one of the voltage pulled up to the control voltage (+5V) side and the voltage pulled down to the ground (GND) side.

In this way, the ID for identifying the individual ornamental LED driver ICs constituting the game board side peripheral control MPU control target first ornamental LED control circuit 4170k1 is applied to the six device address selection terminals. The voltage is preset by the address setting unit 4170k1a depending on the hardware configuration, and is not appropriately set by receiving data by software.

The logic processing unit 4170k1b receives the game board side light emission data SL-DAT from the game board side decorative board serial I/O port of the peripheral control MPU 4150a based on the game board side light emission clock signal SL-CLK and receives the data buffer unit. It is transmitted to 4170k1d. The data buffer unit 4170k1d includes its own ID in the illuminated LED designation information in the game board side light emission data SL-DAT from the logic processing unit 4170k1b, based on the address that is its own ID set by the address setting unit 4170k1a. When it is, it is judged that the game board side light emission data SL-DAT from the logic processing unit 4170k1b is for itself, and the gradation degree which is the gradation information in the game board side light emission data SL-DAT is taken in and taken in. While controlling to set the gradation degree in each channel to the PWM unit 4170k1e so as to become the gradation degree which is the gradation information, the lighting LED designation information in the game board side light emission data SL-DAT from the logic processing unit 4170k1b is used. When the own ID is not included, it is determined that the game board side light emission data SL-DAT from the logic processing unit 4170k1b is not for itself, and the gradation degree which is the gradation information in the game board side light emission data SL-DAT is set. The control for maintaining the current contents set in the PWM unit 4170k1e without taking in is performed.

The PWM unit 4170k1e is capable of controlling the brightness (gradation level) of the LED in each channel in a total of 128 steps from gradation off to lighting (maximum brightness) from gradation 0 (zero) to gradation 127. Therefore, the gradation control is performed by one PWM gradation control unit for one channel. That is, in the PWM unit 4170k1e, gradation control is performed by the PWM gradation control unit 1 for the decoration LED on 1ch, gradation control is performed by the PWM gradation control unit 2 for the decoration LED on 2ch,... The PWM gradation control unit 24 controls the gradation of the decorative LED on the 24ch, and is composed of a total of 24 PWM gradation control units 1 to 24. When the gradation levels are respectively set, the PWM gradation control section 1 to the PWM gradation control section 24 set a constant current so as to flow a current having the set gradation level based on the clock signal from the clock generation section 4170k1c. The drive unit 4170k1f is controlled.

The constant current driving unit 4170k1f is a full-color LED that is a decorative LED by one constant current driver for one channel so that the gradation level is set in the PWM gradation control unit 1 to the PWM gradation control unit 24. The constant current driver 1 to constant current driver 24 are provided in total for supplying a constant current to the LED elements constituting the.

The constant current driver 1 to the constant current driver 24 are electrically connected to one end of a resistor Rp1 that sets the maximum current flowing through the decorative LED in all channels from 1ch to 24ch, and the other end of the resistor Rp1 is grounded. It is grounded to (GND).

The anode terminal of the red LED element, the anode terminal of the green LED element, and the anode terminal of the blue LED element, which compose the full-color LEDs corresponding to the constant current driver 1 to the constant current driver 24, respectively, are the power supply for illumination ( Control power supply). The cathode terminals of the red LED elements forming the full-color LEDs corresponding to the constant current driver 1 to the constant current driver 8 are electrically connected to the LR1 terminal to the LR8 terminal, respectively, and the constant current driver 9 to the constant current driver 16 respectively. The cathode terminal of the green LED element that constitutes the corresponding full-color LED is electrically connected to the LG1 terminal to LG8 terminal, and the blue LED element that constitutes the corresponding full-color LED with the constant current driver 17 to constant current driver 24, respectively. The cathode terminal of is electrically connected to the LB1 terminal to the LB8 terminal.

Then, the constant current driver 1 to the constant current driver 8 set the constant currents individually set to the red LED elements constituting the full-color LEDs, which are the decorative LEDs corresponding to the eight channels from 1ch to 8ch, respectively, to LR1. Each of the constant current driver 9 to the constant current driver 16 is individually supplied to a green LED element forming a full-color LED which is a decorative LED corresponding to 8 channels from 9ch to 16ch. The constant currents set to 1 are flowed through the LG1 terminal to the LG8 terminal, respectively, and the constant current driver 17 to the constant current driver 24 constitute a full-color LED that is a decorative LED corresponding to each of eight channels from 17ch to 24ch. A constant current set individually for each blue LED element is supplied via the LB1 to LB8 terminals.

Note that the control voltage LVp is applied to the power supply terminal of the decoration LED driver IC that constitutes the first decoration LED control circuit 4170k1 for the game board side peripheral control MPU control target, and the decoration LED driver IC is used as the internal power supply Vreg. The GND terminal, which is a ground terminal, is supplied to various internal circuits and grounded to the ground (GND), so that the grounds in various internal circuits of the decorative LED driver IC are grounded to the ground (GND) of the lamp drive substrate 4170.

In this manner, the decorative LED driver ICs configuring the game board side peripheral control MPU control target first decoration LED control circuit 4170k1 to the game board side peripheral control MPU control target eighth decoration LED control circuit 4170k8 are LEDs. Since 24 elements, that is, 8 full-color LEDs, which are decorative LEDs, can be individually dimmed and turned on, such dimming turns off, turns on one gradation, blinks one gradation, etc. It can be performed. Further, the decoration LED driver ICs configuring the game board side peripheral control MPU control target first decoration LED control circuit 4170k1 to the game board side peripheral control MPU control target eighth decoration LED control circuit 4170k8 are decoration LEDs. As 64 full color LEDs (=8 full color LEDs x 8 decorative LED control circuits (decorative LED driver ICs)), that is 192 (= 3 LED elements of red, green and blue x 64) The dimming lighting of the LED element of the full color LED can be performed.

The game board side peripheral control MPU control target first decoration LED control circuit 4170k1 and the game board side peripheral control MPU control target second decoration LED control circuit 417021 are provided in the attacker unit 2100 shown in FIG. The attacker unit 2100 is illuminated and decorated by dimming and lighting a plurality of LEDs (decorative LEDs) provided on the game board side peripheral control MPU control target decorative substrate PM1. The game board side peripheral control MPU control target third decoration LED control circuit 4170k3 is a plurality of LEDs (decoration) provided on the game board side peripheral control MPU control target decoration substrate PM2 included in the side winning opening member 2200 shown in FIG. The side winning opening member 2200 is illuminated and illuminated by performing the dimming lighting of the LED for use). Game board side peripheral control MPU control target fourth decoration LED control circuit 4170k4 to game board side peripheral control MPU control target eighth decoration LED control circuit 4170k8 is a game board provided in the center role object 2300 shown in FIG. The side accessory control MPU control target decoration substrate PM3 is provided with a plurality of LEDs (decorative LEDs) that are dimmed and lit so that the center accessory 2300 is illuminated and decorated.

Here, in this embodiment, as described above, each decorative board of the game board 4 includes a plurality of game board-side peripheral control MPU control target decorative boards that are directly controlled by the peripheral control MPU 4150a, and a sound source. There is a plurality of game board-side VDP control target decoration boards that are directly controlled by the built-in VDP 4160a, and the plurality of decoration LEDs provided on the game board 4 are controlled to emit light by the peripheral control MPU 4150a. , Which is controlled by the VDP 4160a with a built-in sound source. This is because a plurality of LEDs (decorative LEDs) provided on each of the plurality of gaming board-side peripheral control MPU control target decorative boards that are controlled by the peripheral control MPU 4150a directly have the light emission mode of the production progress. That changes slowly along with (e.g., the light-emission mode fluctuates like a gentle wave, the light-emission mode continues for a predetermined time, or the light-emission mode blinks at a speed at which a person blinks even if the light-emission mode is fast ( Blinking), which is less likely to cause a processing load, while a plurality of game board side VDP control target decorative substrates that are directly controlled by the sound source built-in VDP 4160a are provided on each of the plurality of decorative substrates. LED (decorative LED) whose light emitting mode changes rapidly according to the progress of the production (for example, as if lightning was expressed as a light emitting mode in dot display using LED (decorative LED). That blinks at high speed (blinks), expresses fireworks, expresses explosions, scrolls like patterns, displays moving images of people and vehicles) and becomes processing load (These light emitting modes can be quickly changed according to the progress of the effect displayed in the display area of the game board side effect display unit 1900 provided in the game board 4 shown in FIG. It is possible to work together). That is, in the present embodiment, in the light emission control of the plurality of decorative LEDs provided on the game board 4, the peripheral control MPU 4150a takes charge of the ones that are hard to become the processing load, whereas the peripheral control MPU 4150a takes charge of the processing load. Instead, the VDP4160a with a built-in sound source is in charge. Game board side peripheral control of the lamp drive board 4170 MPU control target first decoration LED control circuit 4170k1 to game board side peripheral control MPU control target eighth decoration LED control circuit 4170k8 is, as described above, the game board side When the light emission data SL-DAT is not for itself, the current light emission mode is maintained by maintaining the current content. In other words, if the light emission mode changes slowly along with the production, the time for which the light emission mode is the same becomes long, so when the light emission mode changes, the peripheral control MPU4150a is the game board. Since the side emission data SL-DAT is output, it is difficult for the peripheral control MPU 4150a to become a processing load.

As described above, in the present embodiment, for the plurality of LEDs (decorative LEDs) provided on each of the plurality of gaming board side VDP control target decorative boards that are directly controlled by the sound source built-in VDP 4160a, Peripheral control MPU4150a directly controls a plurality of gaming board side peripheral control MPU control target compared to the plurality of LEDs (decorative LED) provided on each of the decorative substrate, the effect of changing the light emission mode is faster. It is assigned. The peripheral control MPU 4150a also directly controls the plurality of LEDs (decorative LEDs) provided on each of the plurality of gaming board side VDP control target decorative boards that are controlled by the sound source built-in VDP 4160a. In the same manner as the light emitting modes of the plurality of LEDs (decorative LEDs) provided on each of the plurality of game board side peripheral control MPU control target decorative boards, the light emitting mode changes slowly along with the production process. Therefore, in this case, peripheral control is performed for a plurality of LEDs (decorative LEDs) provided on each of the plurality of gaming board side VDP control target decorative boards that are directly controlled by the sound source built-in VDP 4160a. Compared with a plurality of LEDs (decorative LEDs) provided on each of a plurality of gaming board side peripheral control MPU control target decorative substrates that are directly controlled by the MPU 4150a, the effect that the change in the light emission mode is the same is achieved. Will be assigned.

In the present embodiment, the game board side peripheral control MPU control target first decoration LED control circuit 4170k1 to game board side peripheral control MPU control target eighth decoration LED control circuit 4170k8 is used to control the light emission mode. The LEDs for use all used a red LED element, a green LED element, and a blue LED element that compose a full-color LED, but a single LED different from the full-color LED (the same color LED may be used, or a plurality of different LEDs may be used). LED of the game board side peripheral control MPU control target decoration LED control circuit is full color LED and other game board side peripheral control MPU control target decoration LED control circuit Can be a single LED (may be an LED of the same color or an LED of a plurality of different colors), such a game board side peripheral control MPU control target decoration LED control circuit and other games It is also possible to combine a plurality of panel side peripheral control MPU control target decoration LED control circuits.

[14. Frame decoration drive amplifier circuit]
Next, the circuit of the frame decoration drive amplifier board 194 shown in FIG. 19 will be described with reference to FIGS. 39 to 43. First, the configuration of the frame decoration drive amplifier board will be described, and subsequently, the configuration of the frame side VDP control target decoration LED control circuit and the configuration of the frame side peripheral control MPU control target decoration LED control circuit will be described. 39 is a block diagram of a frame decoration drive amplifier board, FIG. 40 is a diagram showing a correspondence relationship between various serial controllers and output destinations in the frame side signal separation control circuit, and FIG. 41 is a frame side VDP control object decoration FIG. 43 is a diagram showing a correspondence relationship between an LED control circuit and a plurality of LEDs (decorative LEDs) provided on a frame-side VDP control target decoration board, and FIG. 42 is a block diagram of a frame-side VDP control target decoration LED control circuit. 43 is a block diagram of a frame side peripheral control MPU control target decoration LED control circuit.

[14-1. Frame decoration drive amplifier board configuration]
As shown in FIG. 39, the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 transmits the frame side light emission data STL-DAT from the frame side decoration board serial I/O port to the frame side light emission clock signal STL-CLK. In synchronization with the frame peripheral relay terminal plate 868 and the peripheral door relay terminal plate 882 to output to the frame decoration drive amplifier board 194. The frame side light emission data STL-DAT and the frame side light emission clock signal STL-CLK from the frame side decoration substrate serial I/O port of the peripheral control MPU 4150a constitute a frame side peripheral control MPU control target decoration LED control circuit 194k. The frame side peripheral control MPU control target first decoration LED control circuit 194k1 to the frame side peripheral control MPU control target seventh decoration LED control circuit 194k7 are input. Frame-side peripheral control MPU control target first decoration LED control circuit 194k1 to frame-side peripheral control MPU control target seventh decoration LED control circuit 194k7 are electrically connected as one serial connection (one serial system) It has a circuit configuration.

The liquid crystal in the peripheral control board 4140 and the sound source built-in VDP 4160a of the sound control unit 4160 have the above-described predetermined screens (in the present embodiment, red (R): 50%, green (G): 50%, blue (B): The door frame side drawing data (gray screen having 50%) is added to the door frame side drawing data according to a predetermined door frame side generation rule to generate drawing data in the door frame side display area VRGN2 provided on the VRAM. And outputs from channel CH2. As described above, the drawing data output from the channel CH2 includes three video signals which are parallel signals, that is, a red video signal, a green video signal, and a blue video signal, a horizontal synchronizing signal, a vertical synchronizing signal, and a clock. The three synchronous signals called signals are serialized into a differential serial signal (serial data) called "V-by-One (registered trademark)" by THine Electronics Co., Ltd., which is a kind of clockless transmission method, and differential 1 When these various signals are output (transmitted) from the peripheral control board 4140 to the frame peripheral relay terminal plate 868, the peripheral door relay terminal plate 882, and the frame decoration drive amplifier 194 and transmitted by only the pair cable, the frame decoration drive is performed. In the receiver IC 194f of the amplifier board 194, parallel signals (that is, three video signals, which are drawing data output from the channel CH2 of the VDP 4160a with a built-in sound source, that is, a red video signal, a green video signal, and a blue video signal, and a horizontal synchronization signal. , A vertical synchronization signal, and a clock signal.

The receiver IC 194f restores the drawing data output from the channel CH2 and outputs it to the frame-side signal separation control circuit 194g. This frame side signal separation control circuit 194g is the same circuit as the game board side signal separation control circuit 3420g of the liquid crystal output substrate 3420 shown in FIG.

As shown in FIG. 39, the frame-side signal separation control circuit 194g includes a signal separation unit 194ga, a buffer memory 194gb, a distribution output control unit 194gc, a first serial controller 194gd1 to an eleventh serial controller 194gd11. When the parallel signal restored by the receiver IC 194f is input, it is input to the signal separation unit 194ga.

The signal separation unit 194ga includes a first resolution conversion unit 194gaa and a second resolution conversion unit 194gab. The first resolution conversion unit 194gaa uses a predetermined screen (in this embodiment, red (R): 50%, green (G): 50%, blue (B): 50 from the drawing data restored to the parallel signal. (Gray screen with%), which is the door frame side drawing data, three video signals of a red video signal, a green video signal, and a blue video signal, and three synchronizations of a horizontal synchronization signal, a vertical synchronization signal, and a clock signal. By cutting out the signal and, the door frame side drawing data is separated from the drawing data restored to the parallel signal, while the second resolution conversion unit 194gab decorates the door frame 5 from the drawing data restored to the parallel signal. Parallel signals can be obtained by cutting out electrical decoration information for a plurality of LEDs (decorative LEDs) provided on each of a plurality of frame-side VDP control target decorative substrates that are control targets that are directly controlled by the sound source built-in VDP 4160a. Of the decorative boards of the door frame 5 based on the drawing data restored to the plurality of LEDs provided on each of the frame-side VDP control target decorative boards that are directly controlled by the sound source built-in VDP 4160a. The electric decoration information for the LED) is separated and output to the buffer memory 194gb to perform the writing operation.

In other words, the first resolution conversion unit 194gaa is generated in the door frame side drawing data area VRGN2a of the door frame side display area VRGN2 provided in the built-in VRAM of the sound source built-in VDP 4160a from the drawing data restored to the parallel signal. By cutting out the door frame side drawing data, the door frame side drawing data can be separated from the drawing data restored to the parallel signal (no output to other electronic parts or other boards). The second resolution converter 194gab generates drawing data in the door frame side accompanying information area VRGN2b of the door frame side display area VRGN2 provided on the built-in VRAM of the sound source built-in VDP 4160a from the drawing data restored to the parallel signal. A plurality of frame-side VDP control target decorations, which are control targets to be directly controlled by the sound source built-in VDP 4160a, of each of the decoration substrates of the door frame 5 from the drawing data restored to the parallel signal by cutting out the generated electric decoration information. The electric decoration information for a plurality of LEDs (decorative LEDs) provided on each of the substrates can be separated and output to the buffer memory 194gb to perform the writing operation.

In the present embodiment, the door frame side drawing data generated in the door frame side drawing data area VRGN2a of the door frame side display area VRGN2 provided in the built-in VRAM of the sound source built-in VDP 4160a is cut out by the first resolution conversion unit 194gaa. However, nothing is output to other electronic components or other substrates.

In the present embodiment, the electric decoration information generated as drawing data in the door frame side accompanying information area VRGN2b of the door frame side display area VRGN2 provided on the built-in VRAM of the sound source built-in VDP 4160a is information written in the buffer memory 194gb. Since it is itself, the second resolution conversion unit 194gab outputs the cut out electrical decoration information as it is to the buffer memory 194gb without performing the enlargement or reduction processing, and performs the writing operation.

The buffer memory 194gb is configured as a double buffer memory including a first buffer memory 194gb1 and a second buffer memory 194gb2, and one of the first buffer memory 194gb1 and the second buffer memory 194gb2 is a write buffer memory. When it is in operation, the contents already written in the other buffer memory are read from the distribution output control unit 194gc. The distribution output control unit 194gc distributes the illumination information read from the buffer memory to the first serial controller 194gd1 to the eleventh serial controller 194gd11 according to a predetermined door frame side generation rule.

The first serial controller 194gd1 to the eleventh serial controller 194gd11 are the frame-side VDP control target decorative LED control circuits 194i that form the frame-side VDP control target decorative LED control circuit 194i1 to the frame-side VDP control target 143th. The decoration information is output to the decoration LED control circuit 194i143.

More specifically, the first serial controller 194gd1 uses the decoration information as serial data SDAT1′ based on the clock signal SCLK1′ as shown in FIG. It outputs to the LED control circuit 194i1 to the frame side VDP control target thirteenth decorative LED control circuit 194i13. The frame side VDP control target first decoration LED control circuit 194i1 to the frame side VDP control target thirteenth decoration LED control circuit 194i13 are electrically connected as one serial connection (one serial system). Has become.

As shown in FIG. 40, the second serial controller 194gd2 uses the decoration information as serial data SDAT2′ based on the clock signal SCLK2′, and will be described later on the frame side VDP control target fourteenth decorative LED control circuit 194i14 to frame. The side VDP control target is output to the 26th decorative LED control circuit 194i26. The frame-side VDP control target fourteenth decoration LED control circuit 194i14 to the frame-side VDP control target twenty-sixth decoration LED control circuit 194i26 are electrically connected as one serial connection (one serial system). Has become.

As shown in FIG. 40, the third serial controller 194gd3 uses the decoration information as serial data SDAT3′ based on the clock signal SCLK3′, and will be described later on the frame side VDP control target 27th decorative LED control circuit 194i27 to frame. The side VDP control target is output to the 39th decorative LED control circuit 194i39. The frame side VDP control target 27th decorative LED control circuit 194i27 to the frame side VDP control target 39th decorative LED control circuit 194i39 are electrically connected as one serial connection (one serial system). Has become.

As shown in FIG. 40, the fourth serial controller 194gd4, based on the clock signal SCLK4′ as the electrical decoration information as serial data SDAT4′, the frame side VDP control target fortyth decorative LED control circuit 194i40 to frame which will be described later. The side VDP control target is output to the 52nd decorative LED control circuit 194i52. The frame side VDP control target 40th decoration LED control circuit 194i40 to the frame side VDP control target 52nd decoration LED control circuit 194i52 are electrically connected as one serial connection (one serial system). Has become.

As shown in FIG. 40, the fifth serial controller 194gd5 uses the decoration information as serial data SDAT5′ based on the clock signal SCLK5′, and will be described later, based on the frame side VDP control target 53rd decorative LED control circuit 194i53 to frame Output to the side VDP control target 65th decorative LED control circuit 194i65. The frame side VDP control target 53rd decoration LED control circuit 194i53 to the frame side VDP control target 65th decoration LED control circuit 194i65 are electrically connected as one serial connection (one serial system). Has become.

As shown in FIG. 40, the sixth serial controller 194gd6, based on the clock signal SCLK6′ as the electrical decoration information as serial data SDAT6′, the frame side VDP control target 66th decorative LED control circuit 194i66 to frame, which will be described later. Output to the side VDP control target 78th decorative LED control circuit 194i78. The frame side VDP control target 66th decorative LED control circuit 194i66 to the frame side VDP control target 78th decorative LED control circuit 194i78 are electrically connected as one serial connection (one serial system). Has become.

As shown in FIG. 40, the seventh serial controller 194gd7 uses the decoration information as serial data SDAT7′ based on the clock signal SCLK7′, and will be described later, based on the frame side VDP control target 79th decorative LED control circuit 194i79 to frame. The side VDP control target is output to the 91st decorative LED control circuit 194i91. The frame side VDP control target 79th decorative LED control circuit 194i79 to the frame side VDP control target 91st decorative LED control circuit 194i91 are electrically connected as one serial connection (one serial system). Has become.

As shown in FIG. 40, the eighth serial controller 194gd8, based on the clock signal SCLK8′ as the electric decoration information as serial data SDAT8′, the frame side VDP control target 92nd decorative LED control circuit 194i92 to the frame described later. It is output to the side VDP control target 104th decorative LED control circuit 194i104. The frame side VDP control target 92nd decoration LED control circuit 194i92 to the frame side VDP control target 104th decoration LED control circuit 194i104 are electrically connected as one serial connection (one serial system). Has become.

As shown in FIG. 40, the ninth serial controller 194gd9, based on the clock signal SCLK9′ as the electrical decoration information as serial data SDAT9′, the frame side VDP control target 105th decorative LED control circuit 194i105 to frame, which will be described later. It is output to the decorative LED control circuit 194i117 of the side VDP control target 117. The frame side VDP control target 105th decorative LED control circuit 194i105 to the frame side VDP control target 117th decorative LED control circuit 194i117 are electrically connected as one serial connection (one serial system). Has become.

As shown in FIG. 40, the tenth serial controller 194gd10 uses the decoration information as serial data SDAT10′ based on the clock signal SCLK10′, and will be described later, based on the frame side VDP control target 118th decorative LED control circuit 194i118 to frame. It is output to the side VDP control target 130th decorative LED control circuit 194i130. The frame side VDP control target 118th decorative LED control circuit 194i118 to the frame side VDP control target 130th decorative LED control circuit 194i130 are electrically connected as one serial connection (one serial system). Has become.

As shown in FIG. 40, the eleventh serial controller 194gd11 uses the decoration information as serial data SDAT11′ based on the clock signal SCLK11′, and will be described later, on the frame side VDP control target 131st decorative LED control circuit 194i131 to frame. It is output to the decorative LED control circuit 194i143 of the side VDP control target 143th. The frame side VDP control target 131 decoration LED control circuit 194i131 to the frame side VDP control target 143 decoration LED control circuit 194i143 are electrically connected as one serial connection (one serial system). Has become.

The frame-side VDP control target first decoration LED control circuit 194i1 to the frame-side VDP control target 143 decoration LED control circuit 194i143 is a control target that is directly controlled by the sound source built-in VDP 4160a in each of the decoration boards of the door frame 5. It is a circuit that can adjust the brightness (grayscale) of a plurality of LEDs (decorative LEDs) provided on each of the plurality of frame-side VDP control target decorative substrates.

As described above, the drawing data output from the liquid crystal in the peripheral control board 4140 and the channel CH2 of the sound source built-in VDP 4160a of the sound control unit 4160 is the predetermined screen described above (in the present embodiment, red (R): 50%, It is provided on the VRAM as the door frame side drawing data of green (G): 50% and blue (B): 50%) with the electric decoration information attached according to a predetermined door frame side generation rule. Although it is generated in the door frame side display area VRGN2, the "predetermined door frame side generation rule" is that the first resolution conversion unit 194gaa of the signal separation unit 194ga includes the built-in VRAM of the sound source built-in VDP 4160a. The door frame side drawing data VRGN2 provided in the door frame side display area VRGN2 is configured so that the door frame side drawing data generated in the door frame side drawing data area VRGN2a can be accurately cut out, and the second part of the signal separation unit 194ga is configured. The resolution conversion unit 194gab can accurately cut out the electric decoration information generated as drawing data in the door frame side accompanying information area VRGN2b of the door frame side display area VRGN2 provided on the built-in VRAM of the sound source built-in VDP 4160a. In the frame side signal separation control circuit 194g of the frame decoration drive amplifier board 194, the distribution output control unit 194gc transfers the electric decoration information read from the buffer memory 194gb to the first serial controller 194gd1 to the eleventh serial controller 194gd11. Each is configured for accurate distribution.

More specifically, in the frame-side signal separation control circuit 194g of the frame decoration drive amplifier board 194, the distribution output control unit 194gc reads the frame-side VDP control target first decoration LED control circuit 194i1 from the buffer memory 194gb. For the frame side VDP control target first decoration LED control circuit 194i1 so that the electric decoration information for the frame side VDP control target thirteen decoration LED control circuit 194i13 can be accurately distributed to the first serial controller 194gd1. The decoration information, the decoration information for the frame-side VDP control target second decoration LED control circuit 194i2,... And the decoration information for the frame-side VDP control target thirteen decoration LED control circuit 194i13 are predetermined. On the built-in VRAM as attached to the door frame side drawing data of the screen (gray screen having red (R): 50%, green (G): 50%, blue (B): 50% in this embodiment) Is generated in the door frame side associated information area VRGN2b of the door frame side display area VRGN2.

In addition, the distribution output control unit 194gc outputs the illumination information for the frame-side VDP control target fourteenth decoration LED control circuit 194i14 to the frame-side VDP control target twenty-sixth decoration LED control circuit 194i26 read out from the buffer memory 194gb to the second. Illumination information for the frame-side VDP control target fourteenth decorative LED control circuit 194i14, and illumination for the frame-side VDP control target fifteenth decorative LED control circuit 194i15 so that the serial controller 194gd2 can be accurately distributed. Information,..., And a screen in which the electrical decoration information for the frame-side VDP control target 26th decorative LED control circuit 194i26 is predetermined (in the present embodiment, red (R): 50%, green (G): 50). %, blue (B): gray screen with 50%) is generated in the door frame side incidental information area VRGN2b of the door frame side display area VRGN2 provided on the built-in VRAM as attached to the door frame side drawing data. To be done.

Further, the distribution output control unit 194gc corresponds to the illumination information for the frame side VDP control target 27th decorative LED control circuit 194i27 to the frame side VDP control target 39th decorative LED control time 194i39 read from the buffer memory 194gb. To enable accurate distribution to the third serial controller 194gd3, the electric decoration information for the frame side VDP control target 27th decorative LED control circuit 194i27, the frame side VDP control target 28th decorative LED control circuit 194i28 A screen in which the electric decoration information,..., And the electric decoration information for the frame-side VDP control target 39th decorative LED control circuit 194i39 is predetermined (in the present embodiment, red (R): 50%, green (G)). : Gray frame having 50% and blue (B): 50%) door frame side display information VRGN2b of the door frame side display area VRGN2 provided on the built-in VRAM as attached to the door frame side drawing data. Is generated.

Further, the distribution output control unit 194gc corresponds to the illumination information for the frame-side VDP control target 40th decorative LED control circuit 194i40 to the frame-side VDP control target 52nd decorative LED control circuit 194i52 read from the buffer memory 194gb. For the correct distribution to the fourth serial controller 194gd4, the electrical decoration information for the frame-side VDP control target 40th decorative LED control circuit 194i40 and the frame-side VDP control target 41st decorative LED control circuit 194i41 are provided. A screen in which the electric decoration information,..., And the electric decoration information for the frame-side VDP control target 52nd decorative LED control circuit 194i52 is predetermined (in the present embodiment, red (R): 50%, green (G)). : Gray frame having 50% and blue (B): 50%) door frame side display information VRGN2b of the door frame side display area VRGN2 provided on the built-in VRAM as attached to the door frame side drawing data. Is generated.

Further, the distribution output control unit 194gc corresponds to the illumination information for the frame side VDP control target 53rd decorative LED control circuit 194i53 to the frame side VDP control target 65th decorative LED control circuit 194i65 read from the buffer memory 194gb. The electric decoration information for the frame side VDP control target 53rd decoration LED control circuit 194i53 and the frame side VDP control target 54th decoration LED control circuit 194i54 so that the fifth serial controller 194gd5 can be accurately distributed. A screen in which the electric decoration information,..., And the electric decoration information for the frame-side VDP control target 65th decorative LED control circuit 194i65 is predetermined (in the present embodiment, red (R): 50%, green (G)). : Gray frame having 50% and blue (B): 50%) door frame side display information VRGN2b of the door frame side display area VRGN2 provided on the built-in VRAM as attached to the door frame side drawing data. Is generated.

Further, the distribution output control unit 194gc corresponds to the illumination information for the frame side VDP control target 66th decorative LED control circuit 194i66 to the frame side VDP control target 78th decorative LED control time 194i78 read from the buffer memory 194gb. For accurate distribution to the sixth serial controller 194gd6, electric decoration information for the frame side VDP control target 66th decorative LED control circuit 194i66, and frame side VDP control target 67th decorative LED control circuit 194i67 The screen in which the electric decoration information,..., And the electric decoration information for the frame-side VDP control target 78th decorative LED control circuit 194i78 is predetermined (in the present embodiment, red (R): 50%, green (G)). : Gray frame having 50% and blue (B): 50%) door frame side display information VRGN2b of the door frame side display area VRGN2 provided on the built-in VRAM as attached to the door frame side drawing data. Is generated.

In addition, the distribution output control unit 194gc corresponds to the illumination information for the frame side VDP control target 79th decorative LED control circuit 194i79 to the frame side VDP control target 91st decorative LED control time 194i91 read from the buffer memory 194gb. To enable accurate distribution to the seventh serial controller 194gd7, the electric decoration information for the frame side VDP control target 79th decorative LED control circuit 194i79, the frame side VDP control target 80th decorative LED control circuit 194i80 The screen in which the electric decoration information,..., And the electric decoration information for the frame side VDP control target 91st decorative LED control circuit 194i91 is predetermined (in the present embodiment, red (R): 50%, green (G)). : Gray frame having 50% and blue (B): 50%) door frame side display information VRGN2b of the door frame side display area VRGN2 provided on the built-in VRAM as attached to the door frame side drawing data. Is generated.

In addition, the distribution output control unit 194gc corresponds to the illumination information for the frame-side VDP control target 92nd decoration LED control circuit 194i92 to the frame-side VDP control target 104th decoration LED control circuit 194i104 read from the buffer memory 194gb. The electric decoration information for the frame side VDP control target 92nd decoration LED control circuit 194i92 and the frame side VDP control target 93rd decoration LED control circuit 194i93 for accurate distribution to the eighth serial controller 194gd8. Illumination information,... And a screen in which the illumination information for the frame side VDP control target 104th decorative LED control circuit 194i104 is predetermined (in the present embodiment, red (R): 50%, green (G)). : Gray frame having 50% and blue (B): 50%) door frame side display information VRGN2b of the door frame side display area VRGN2 provided on the built-in VRAM as attached to the door frame side drawing data. Is generated.

Further, the distribution output control unit 194gc corresponds to the decoration information for the decorative LED control circuit 194i117 of the frame-side VDP control target 105th decorative LED control circuit 194i105 to the frame-side VDP control target 117 read from the buffer memory 194gb. The illumination information for the frame-side VDP control target 105th decorative LED control circuit 194i105 and the frame-side VDP control target 106th decorative LED control circuit 194i106 so that they can be accurately distributed to the ninth serial controller 194gd9. A screen in which the electric decoration information,..., And the electric decoration information for the decorative LED control circuit 194i117 of the frame-side VDP control target 117 is predetermined (in the present embodiment, red (R): 50%, green (G)). : Gray frame having 50% and blue (B): 50%) door frame side display information VRGN2b of the door frame side display area VRGN2 provided on the built-in VRAM as attached to the door frame side drawing data. Is generated.

Further, the distribution output control unit 194gc corresponds to the illumination information for the frame-side VDP control target 118th decorative LED control circuit 194i118 to the frame-side VDP control target 130th decorative LED control time 194i130 read from the buffer memory 194gb. Electricity information for the frame side VDP control target 118th decorative LED control circuit 194i118, and for the frame side VDP control target 119th decorative LED control circuit 194i119 so that it can be accurately distributed to the tenth serial controller 194gd10. The screen in which the illumination information,..., And the illumination information for the frame-side VDP control target 130th decorative LED control circuit 194i130 are predetermined (in the present embodiment, red (R): 50%, green (G)). : Gray frame having 50% and blue (B): 50%) door frame side display information VRGN2b of the door frame side display area VRGN2 provided on the built-in VRAM as attached to the door frame side drawing data. Is generated.

In addition, the distribution output control unit 194gc corresponds to the decoration information for the decoration LED control circuit 194i143 of the frame side VDP control target 131st decoration LED control circuit 194i131 to the frame side VDP control target 143 read from the buffer memory 194gb. For accurate distribution to the eleventh serial controller 194gd11, the electric decoration information for the frame-side VDP control target 131st decorative LED control circuit 194i131 and the frame-side VDP control target 132nd decorative LED control circuit 194i132 The screen in which the electric decoration information,..., And the electric decoration information for the decorative LED control circuit 194i143 of the frame side VDP control target 143 is predetermined (in the present embodiment, red (R): 50%, green (G)). : Gray frame having 50% and blue (B): 50%) door frame side display information VRGN2b of the door frame side display area VRGN2 provided on the built-in VRAM as attached to the door frame side drawing data. Is generated.

As described above, the drawing data output from the liquid crystal in the peripheral control board 4140 and the channel CH2 of the sound source built-in VDP 4160a of the sound control unit 4160 has predetermined screens (in the present embodiment, red (R): 50%, green ( G): Door provided on the built-in VRAM as the door frame side drawing data of 50%, blue (B): 50% gray frame) with the electric decoration information attached according to a predetermined door frame side generation rule By being generated in the frame side display area VRGN2, the first serial controller 194gd1 to the eleventh serial controller 194gd11 use the clock signal SCLK1′ to the clock signal SCLK11′ as the electrical decoration information as the serial data SDAT1′ to the serial data SDAT11′. Based on the frame-side VDP control target first decoration LED control circuit 194i1 to the frame-side VDP control target first 143 decoration LED control circuit 194i143 to output a sound source from among the decoration boards of the door frame 5. The built-in VDP 4160a drives a plurality of LEDs (decorative LEDs) provided on each of the plurality of frame-side VDP control target decorative substrates that are directly controlled. The brightness (gradation) of the decorative LED is adjusted by the control by this driving.

The first serial controller 194gd1 to the eleventh serial controller 194gd11 select a common mode in which the output timings can be the same timing and an individual mode in which the output timings can be different timings. You can do it. In the case where the output timings of the first serial controller 194gd1 to the eleventh serial controller 194gd11 are set to the common mode in which the output timings are the same, the output from the first serial controller 194gd1 to the eleventh serial controller 194gd11 causes an extremely short period to be controlled. There may be a case where even if a large current flows as an inrush current, the current is insufficient and an instantaneous blackout does not occur. On the other hand, when the output modes of the first serial controller 194gd1 to the eleventh serial controller 194gd11 are set to the individual mode in which the output timings are different from each other, the output is controlled by the first serial controller 194gd1 to the eleventh serial controller 194gd11. If a large current flows as an inrush current to the target during an extremely short period of time, there is a risk of power shortage and an instantaneous blackout may occur.

In the present embodiment, the individual serial modes are set such that the output timings of the first serial controller 194gd1 to the eleventh serial controller 194gd11 are different timings. When the game board 4 is mounted on a dedicated frame (outer frame 2, main body frame 3, and door frame 5) that expresses the world view expressed by the effect, it is provided on the game board 4 or the dedicated frame side. A power supply board 851 of the board unit 800 attached to the main body frame 3 so as to be commensurate with the electric power supplied to an electric drive source such as a plurality of LEDs (decorative LEDs) and a plurality of movable bodies for operating a movable body. The power generation circuit is designed so that a sufficient power supply will not occur even if a plurality of LEDs (ornamental LEDs) are turned on and the movable body is activated by an electric drive source such as a motor or solenoid. Has capacity.

However, the game board mounted on the main body frame 3 of the outer frame 2 already installed in the hall (a game board of another model different from the game board 4 (for example, the world view expressed by the production is different, LED (decorative) The number of LEDs), the presence or absence of movable bodies operated by an electric drive source such as a motor or a solenoid, and the number thereof are different.) Therefore, if the game board 4 is simply replaced, a plurality of LEDs ( If the movable body starts to operate due to the lighting of the decorative LED) or the electric drive source such as a motor or a solenoid, a momentary power failure may occur.

Therefore, in the present embodiment, by setting the output timings of the first serial controller 194gd1 to the eleventh serial controller 194gd11 to different individual modes, the output is controlled by the first serial controller 194gd1 to the eleventh serial controller 194gd11. It is possible to prevent the occurrence of an instantaneous power failure due to power shortage due to a large current flowing as an inrush current for an extremely short period of time with respect to the target. There is no need to bother to provide it. This makes it possible to suppress the load on the power supply board 851 of the board unit 800 attached to the main body frame 3 of the outer frame 2 already installed in the hole, which is different from the above-described dedicated frame.

Since the liquid crystal in the peripheral control board 4140 and the sound source built-in VDP 4160a of the sound control unit 4160 are set to the frame frequency of 30 fps as described above (about every 33.3 ms), they are generated in the built-in VRAM. Since the drawing data is output from the channels CH1 and CH2, the drawing data output from the channel CH2 of the sound source built-in VDP 4160a is also input to the frame-side signal separation control circuit 194g of the frame decoration drive amplifier board 194 about every 33.3 ms. Will be done. Therefore, a predetermined screen (red (R): 50%, green (G): 50%, blue in the present embodiment is set in the first resolution conversion unit 194gaa of the signal separation unit 194ga in the frame-side signal separation control circuit 194g. (B): Door frame side drawing data of (gray screen having 50%) is separated every about 33.3 ms, and in the second resolution conversion unit 194gab of the signal separation unit 194ga in the frame side signal separation control circuit 194g. All of the separated illumination information is output from the first serial controller 194gd1 to the eleventh serial controller 194gd11 based on the clock signals SCLK1' to SCLK11' and the serial data SDAT1' to serial data SDAT11' are all output at about every 33.3 ms. By this, it is possible to realize the synchronization of the effects by the plurality of control targets respectively output from the first serial controller 194gd1 to the eleventh serial controller 194gd11, and to prevent the progress of the effects by the plurality of control targets from shifting. By doing so, it is possible to suppress a decrease in interest.

[14-2. Frame-side VDP control target decoration LED control circuit configuration]
Next, the configuration of the frame side VDP control target decoration LED control circuit will be described. The frame decoration drive amplifier board 194 serves as a frame-side VDP control target decoration LED control circuit 194i, and controls a plurality of frame-side VDP controls that are directly controlled by the sound source built-in VDP 4160a in each of the decoration boards of the door frame 5. Frame-side VDP control target first decoration LED control circuit 194i1 to frame-side VDP control target first 143, which is capable of dimming and turning on light emitted from a plurality of LEDs (decorative LEDs) provided on each target decoration substrate For LED control circuit 194i143 (total, 143 circuits).

In the present embodiment, what is dimmed by the frame-side VDP control target first decoration LED control circuit 194i1 to the frame-side VDP control target thirteen decoration LED control circuit 194i13 is the frame-side decoration first group. It is managed. As shown in FIG. 41, the frame side VDP control target first decoration LED control circuit 194i1 to the frame side VDP control target thirteen decoration LED control circuit 194i13 are frame sides in the right side decoration unit 200 of the door frame 5. A plurality of LEDs (104 LEDs (decorative LEDs)) provided on the VDP control target decorative substrate RV1 are dimmed to lighten the entire first light emission decoration area RTV1.

In addition, what is dimmed by the frame-side VDP control target fourteenth decoration LED control circuit 194i14 to the frame-side VDP control target twenty-sixth decoration LED control circuit 194i26 is managed as the frame-side decoration second group. There is. The frame side VDP control target fourteenth decoration LED control circuit 194i14 to the frame side VDP control target twenty-sixth decoration LED control circuit 194i26 are, as shown in FIG. 41, the frame side in the right side decoration unit 200 of the door frame 5. A plurality of LEDs (87 LEDs (decorative LEDs)) provided on the VDP controlled decorative substrate RV2 and a plurality of LEDs (116 LEDs (decorative LEDs)) provided on the frame side VDP controlled decorative substrate RV3 Among them, a predetermined number of LEDs (17 LEDs (decorative LEDs)) are dimmed to turn on the entire second light emission decoration area RTV2 and a part of the lower side of the third light emission decoration area RTV3. Luminous decoration.

Further, what is dimmed by the frame-side VDP control target 27th decorative LED control circuit 194i27 to the frame-side VDP control target 39th decorative LED control circuit 194i39 is managed as the frame-side decorative third group. There is. The frame side VDP control target 27th decoration LED control circuit 194i27 to the frame side VDP control target 39th decoration LED control circuit 194i39 are, as shown in FIG. 41, the frame side in the right side decoration unit 200 of the door frame 5. A predetermined number of LEDs (99 LEDs (decorative LEDs)) out of the plurality of LEDs (116 LEDs (decorative LEDs)) provided on the VDP control decorative substrate RV3, and the upper decorative unit 280 of the door frame 5. A predetermined number of LEDs (5 LEDs (decorative LEDs)) out of the plurality of LEDs (265 LEDs (decorative LEDs)) provided on the frame-side VDP controlled decorative substrate RV4 in FIG. All the other parts except the lower part of the third light emission decoration region RTV3 and the lower part of the fourth light emission decoration region RTV4 are light-emitted.

In addition, what is dimmed by the frame-side VDP control target 40th decoration LED control circuit 194i40 to the frame-side VDP control target 52nd decoration LED control circuit 194i52 is managed as the frame-side decoration fourth group. There is. The frame side VDP control target 40th decoration LED control circuit 194i40 to the frame side VDP control target 52nd decoration LED control circuit 194i52 are, as shown in FIG. 41, the frame side VDP in the upper decoration unit 280 of the door frame 5. A predetermined number of LEDs (104 LEDs (decorative LEDs)) among a plurality of LEDs (265 LEDs (decorative LEDs)) provided on the control target decorative substrate RV4 are dimmed to turn on the fourth light emission decorative area. The area from the lower part of the RTV4 to the central part is illuminated and decorated.

In addition, what is dimmed by the frame-side VDP control target 53rd decoration LED control circuit 194i53 to the frame-side VDP control target 65th decoration LED control circuit 194i65 is managed as the frame-side decoration 5th group. There is. The frame side VDP control target 53rd decoration LED control circuit 194i53 to the frame side VDP control target 65th decoration LED control circuit 194i65 are the frame side VDP in the upper decoration unit 280 of the door frame 5, as shown in FIG. A predetermined number of LEDs (104 LEDs (decorative LEDs)) among a plurality of LEDs (265 LEDs (decorative LEDs)) provided on the control target decorative substrate RV4 are dimmed to turn on the fourth light emission decorative area. The central part of the RTV 4 to the part excluding a part on the upper side is illuminated and decorated.

In addition, the light controlled by the frame side VDP control target 66th decoration LED control circuit 194i66 to the frame side VDP control target 78th decoration LED control circuit 194i78 is managed as the frame side decoration 6th group. There is. The frame-side VDP control target 66th decoration LED control circuit 194i66 to the frame-side VDP control target 78th decoration LED control circuit 194i78 are, as shown in FIG. 41, the frame-side VDP in the upper decoration unit 280 of the door frame 5. A predetermined number of LEDs (52 LEDs (decorative LEDs)) out of the plurality of LEDs (265 LEDs (decorative LEDs)) provided on the control object decorative substrate RV4 and the frame-side VDP-controlled decorative substrate LV4. A predetermined number of LEDs (52 LEDs (decorative LEDs)) among a plurality of provided LEDs (265 LEDs (decorative LEDs)) are dimmed and turned on, and the upper side of the fourth light emission decorative area RTV4 is displayed. The part and the upper part of the fourth light emission decoration area LTV4 are light-emitted.

In addition, the light controlled by the frame-side VDP control target 79th decoration LED control circuit 194i79 to the frame-side VDP control target 91st decoration LED control circuit 194i91 is managed as the frame-side decoration 7th group. There is. The frame side VDP control target 79th decoration LED control circuit 194i79 to the frame side VDP control target 91st decoration LED control circuit 194i91 are the frame side VDPs in the upper decoration unit 280 of the door frame 5, as shown in FIG. A predetermined number of LEDs (104 LEDs (decorative LEDs)) out of the plurality of LEDs (265 LEDs (decorative LEDs)) provided on the control target decorative substrate LV4 are dimmed to turn on the fourth light emission decorative area. The part of the LTV 4 except the upper part to the central part is illuminated and decorated.

In addition, what is dimmed by the frame side VDP control target 92nd decoration LED control circuit 194i92 to the frame side VDP control target 104th decoration LED control circuit 194i104 is managed as the frame side decoration 8th group. There is. The frame-side VDP control target 92nd decoration LED control circuit 194i92 to the frame-side VDP control target 104th decoration LED control circuit 194i104 are, as shown in FIG. 41, the frame-side VDP in the upper decoration unit 280 of the door frame 5. A predetermined number of LEDs (104 LEDs (decorative LEDs)) out of the plurality of LEDs (265 LEDs (decorative LEDs)) provided on the control target decorative substrate LV4 are dimmed to turn on the fourth light emission decorative area. The area from the center of the LTV 4 to the part excluding the lower part is illuminated and decorated.

Further, what is dimmed and turned on by the frame-side VDP control target 105th decorative LED control circuit 194i105 to the frame-side VDP control target 117th decorative LED control circuit 194i117 is managed as the frame-side decorative 9th group. There is. As shown in FIG. 41, the frame side VDP control target 105th decoration LED control circuit 194i105 to the frame side VDP control target 117 decoration LED control circuit 194i117 is the frame side VDP in the upper decoration unit 280 of the door frame 5. A predetermined number of LEDs (5 LEDs (decorative LEDs)) among the plurality of LEDs (265 LEDs (decorative LEDs)) provided on the control target decorative substrate LV4, and the left side decorative unit 240 of the door frame 5 A predetermined number of LEDs (99 LEDs (decorative LEDs)) among the plurality of LEDs (116 LEDs (decorative LEDs)) provided on the frame-side VDP control target decorative substrate LV3 in FIG. Then, the lower part of the fourth light emission decoration area LTV4 and all the other parts except the lower part of the third light emission decoration area LTV3 are light-emitted.

In addition, what is dimmed by the frame-side VDP control target 118th decoration LED control circuit 194i118 to the frame-side VDP control target 130th decoration LED control circuit 194i130 is managed as the frame-side decoration 10th group. There is. The frame-side VDP control target 118th decoration LED control circuit 194i118 to the frame-side VDP control target 130th decoration LED control circuit 194i130 are, as shown in FIG. 41, the frame side in the left side decoration unit 240 of the door frame 5. A predetermined number of LEDs (17 LEDs (decorative LEDs)) out of the plurality of LEDs (116 LEDs (decorative LEDs)) provided on the VDP controlled decorative substrate LV3, and the frame-side VDP controlled decorative substrate LV2 A plurality of LEDs (87 LEDs (decorative LEDs)) provided in the dimming lighting, and a lower part of the third light emitting decoration area LTV3 and the entire second light emitting decoration area LTV2. Luminous decoration.

Further, what is dimmed and turned on by the frame-side VDP control target 131th decoration LED control circuit 194i131 to the frame-side VDP control target 143 decoration LED control circuit 194i143 is managed as the frame-side decoration 11th group. There is. As shown in FIG. 41, the frame side VDP control target 131th decoration LED control circuit 194i131 to the frame side VDP control target 143 decoration LED control circuit 194i143 is the frame side in the left side decoration unit 240 of the door frame 5. A plurality of LEDs (104 LEDs (decorative LEDs)) provided on the VDP control target decorative substrate LV1 are dimmed to lighten the entire first light emission decoration area LTV1.

In addition to its own control power source, the frame decoration drive amplifier board 194 is used as a power source for the frame side VDP control target first decoration LED control circuit 194i1 to frame side VDP control target 143 decoration LED control circuit 194i143. The power supply (+5V) is supplied from the power supply board 851 through the frame peripheral relay terminal plate 868 and the peripheral door frame relay terminal plate 882.

The frame-side VDP control target first decorative LED control circuit 194i1 to the frame-side VDP control target 143th decorative LED control circuit 194i143 are each configured from the same decorative LED driver IC. The frame side VDP control target first decoration LED control circuit 194i1 to the frame side VDP control target first 143 decoration LED control circuit 194i143 is the game board side VDP control target first of the liquid crystal output substrate 3420 shown in FIG. It is the same circuit as the LED control circuit for decoration 3420i1 to the VDP control target 27th decoration LED control circuit 3420i27 for the game board side.

The decorative LED driver IC includes a plurality of LEDs (for decoration) provided on each of a plurality of frame-side VDP control target decorative substrates which are control targets to be directly controlled by the sound source built-in VDP 4160a among the decorative substrates of the door frame 5. It is possible to individually control the light emission of each LED (LED) from the extinction to high brightness (maximum brightness) in a total of 128 steps from gradation 0 (zero) to gradation 127, and with gradation 0 (zero). The light is turned off, and the brightness can be adjusted to the maximum brightness with the gradation 127. As described above, the decoration LED control circuits 194i143 of the frame-side VDP control target first decoration LED control circuit 194i1 to the frame-side VDP control target 143 can individually and finely adjust the brightness of the decoration LED. Therefore, it is possible to perform fine control such as dimming lighting of the decorative LED.

The peripheral control MPU 4150a of the peripheral control unit 4150 on the peripheral control board 4140 controls the sound source built-in VDP 4160a of the liquid crystal and sound control unit 4160. The sound source built-in VDP 4160a defines the configuration of the above-described predetermined screen (in the present embodiment, a gray screen having red (R): 50%, green (G): 50%, and blue (B): 50%). Screen data to be displayed and a plurality of LEDs (decorative LEDs) provided on each of the plurality of frame-side VDP control target decorative boards that are directly controlled by the sound source built-in VDP 4160a among the respective decorative boards of the door frame 5. When the light emission data defining the light emission mode of No. 4 is input from the peripheral control MPU 4150a, the predetermined data is generated from the liquid crystal and sound control ROM 4160b based on the input screen data according to the predetermined door frame side generation rule described above. Sprite data by extracting dummy data for drawing a different screen (gray screen having red (R): 50%, green (G): 50%, blue (B): 50% in the present embodiment) To generate door frame side drawing data in the door frame side drawing data area VRGN2a of the door frame side display area VRGN2 provided on the built-in VRAM, and generate liquid crystal and sound based on the input light emission data. From the control ROM 4160b to the decoration boards of the door frame 5, a plurality of LEDs (decorative LEDs) provided on each of the frame-side VDP control object decoration boards that are directly controlled by the sound source built-in VDP 4160a. The door frame side light emission mode setting image data for setting the mode is extracted and the electric decoration information is generated as drawing data in the door frame side accompanying information area VRGN2b of the door frame side display area VRGN2 provided on the built-in VRAM. .. Then, the sound source built-in VDP 4160a has three video signals, that is, a red video signal, a green video signal, and a blue video signal, which are parallel signals of the drawing data generated from the channel CH2 in the door frame side display area VRGN2, and a horizontal synchronization signal. , A vertical synchronizing signal, and three synchronizing signals of a clock signal, and a differential type serial signal (serial data) of "V-by-One (registered trademark)" of THine Electronics Co., Ltd., which is a kind of clockless transmission method. These various signals are serialized into a differential 1 pair cable and output from the peripheral control board 4140 to the frame peripheral relay terminal plate 868, the peripheral door relay terminal plate 882, and the frame decoration drive amplifier 194.

As described above, the drawing data output from the channel CH2 of the sound source built-in VDP 4160a is a parallel signal (that is, the drawing data output from the channel CH2 of the sound source built-in VDP 4160a, in the receiver IC 194f of the frame decoration drive amplifier board 194, as described above. When restored to three video signals of a red video signal, a green video signal, and a blue video signal, and three sync signals of a horizontal sync signal, a vertical sync signal, and a clock signal, the frame decoration drive amplifier board 194 Is input to the signal separation unit 194ga in the frame-side signal separation control circuit 194g. The signal separation unit 194ga displays the drawing data restored to the parallel signal on a screen (in this embodiment, red (R): 50%, green (G): 50%, blue that is predetermined in the first resolution conversion unit 194gaa. (B): Door frame side drawing data (gray screen having 50%) and the electric decoration information in the second resolution conversion unit 194gab. The first resolution conversion unit 194gaa uses the above-described separated predetermined screen (in the present embodiment, a gray screen having red (R): 50%, green (G): 50%, and blue (B): 50%). ) Door frame side drawing data is not output to other electronic components or other boards. The second resolution conversion unit 194gab outputs the separated electric decoration information to the buffer memory 194gb in the frame-side signal separation control circuit 194g to perform the writing operation.

The distribution output control unit 194gc in the frame-side signal separation control circuit 194g outputs the electric decoration information read from the buffer memory 194gb to the first serial controller 194gd1 to 11th according to the predetermined door frame side generation rule described above. It is distributed to the serial controller 194gd11. As described above, the first serial controller 194gd1 to the eleventh serial controller 194gd11 use the decoration LED as the serial data SDAT1′ to the serial data SDAT11′ based on the clock signal SCLK1′ to the clock signal SCLK11′. It outputs to the frame side VDP control target first decoration LED control circuit 194i1 to frame side VDP control target 143 decoration LED control circuit 194i143 capable of adjusting the brightness (gradation).

The serial data SDAT1′ to the serial data SDAT11′ and the clock signal SCLK1′ to the clock signal SCLK11′ from the first serial controller 194gd1 to the eleventh serial controller 194gd11 are each one serial connection (one serial system), as described above. Has a circuit configuration that is electrically connected.

By adopting such a system in which one serial connection is used, among the decorative boards of the door frame 5, a plurality of frame-side VDP control object decorative boards that are directly controlled by the sound source built-in VDP 4160a can be used. In order to individually dimming and lighting a plurality of LEDs (decorative LEDs) provided in each, a parallel connection is performed in which control signals are individually output to the decorative LEDs, for example, from the frame decorative drive amplifier board 194. Compared with the method, the number of wirings can be extremely reduced, so that the degree of freedom in routing the wirings can be increased. In addition, in the method using one serial connection, it is easy to cope with the external noise from entering the wiring by reducing the number of wires, and the influence of the external noise can be reduced compared to the method using the parallel connection. Can be suppressed.

The frame-side VDP control target first decoration LED control circuit 194i1 to the frame-side VDP control target first 143 decoration LED control circuit 194i143 are overlapped by IDs that can identify each individual by an address setting unit described later. Is set without.

The serial data SDAT1' to serial data SDAT11' from the first serial controller 194gd1 to the eleventh serial controller 194gd11 in the frame-side signal separation control circuit 194g are used to transmit the illumination information, as described above. Here, the electric decoration information separated in the second resolution converter 194gab of the signal separator 194ga of the frame-side signal separation control circuit 194g will be described.

The "illumination information" has the same content as the illumination information separated in the second resolution conversion unit 3420gab of the signal separation unit 3420ga of the game board side signal separation control circuit 3420g in the liquid crystal output substrate 3420 shown in FIG. The information is information for designating the light emission mode, and is composed of illumination LED designation information and gradation information. The decorative LED designation information is used for any frame side VDP control target decoration LED control among the frame side VDP control target first decoration LED control circuit 194i1 to frame side VDP control target 143 decoration LED control circuit 194i143. This is information indicating whether or not a circuit is designated, and the above-mentioned ID is set. The gradation information is information indicating which of the gradation 0 (zero) to the gradation 127 is to be specified.

[14-2-1. Frame side VDP control object decoration LED control circuit]
In the present embodiment, the decorative LED control circuits 194i143 of the frame-side VDP control target first decoration LED1 to the frame-side VDP control target 143i are respectively supplied from the same decorative LED driver IC as described above. Here, the frame-side VDP control target first decoration LED control circuit 194i1 will be briefly described below, and the frame-side VDP control target second decoration LED control circuit 194i2 to the frame-side VDP control target The description of the 143rd decorative LED control circuit 194i 143 is omitted.

As shown in FIG. 42, the decoration LED driver IC that constitutes the frame-side VDP control target first decoration LED control circuit 194i1 has 24 output channels (ch), and each channel has a maximum of 80 mA (milliamperes). It is a 24ch constant current LED driver IC that can output the current of. The decorative LED driver IC mainly includes an address setting unit 194i1a, a logic processing unit 194i1b, a clock generating unit 194i1c, a data buffer unit 194i1d, a PWM unit 194i1e, and a constant current driving unit 194i1f.

The address setting unit 194i1a can set 64 types of addresses as its own ID (ID capable of identifying an individual) according to the magnitude of the voltage applied to three address setting terminals (not shown). There is. The voltage applied to the three address setting terminals is one of the control voltage (+5V) DVp, 2/3DVp, 1/3DVp, and ground (GND), and the 2/3DVp and 1/3DVp are the control power source DVp. And a ground (GND) are divided by a plurality of resistors (not shown) electrically connected in series, and taken out.

For example, the control power DVp is supplied to one end of the first resistor, the other end of the first resistor is electrically connected to one end of the second resistor, and the other end of the second resistor is connected to the third resistor. The one end is electrically connected to the other end, and the other end of the third resistor is grounded to the ground (GND) so that the three resistors have the same resistance value. As a result, the voltage at which the other end of the second resistor and the one end of the third resistor are electrically connected becomes ⅓ DVp, which is a voltage that is ⅓ of the control voltage DVp. The voltage at which the other end of the second resistor and one end of the second resistor are electrically connected is ⅔ DVp, which is a two-third voltage of the control voltage DVp.

As described above, the ID that can identify the individual decorative LED driver ICs configuring the first decorative LED control circuit 194i1 for the frame side VDP control is the hardware that is the voltage applied to the three address setting terminals. The address setting unit 194i1a is configured in advance by the above configuration, and is not appropriately set by receiving data by software.

The logic processing unit 194i1b receives the serial data SDAT1' from the first serial controller 194gd3 in the frame side signal separation control circuit 194g based on the clock signal SCLK1' and transmits it to the data buffer unit 194i1d. When the data buffer unit 194i1d includes its own ID in the electric LED designation information in the serial data SDAT1′ from the logic processing unit 194i1b based on the address which is the ID of its own set by the address setting unit 194i1a, It is determined that the serial data SDAT1′ from the logic processing unit 194i1b is for itself, and the gradation degree, which is the gradation information in the serial data SDAT1′, is fetched, and the gradation degree is the fetched gradation information. While controlling to set the gradation degree in each channel in the PWM unit 194i1e, when the own LED is not included in the illumination LED designation information in the serial data SDAT1′ from the logic processing unit 194i1b, the logic processing unit 194i1b outputs It is determined that the serial data SDAT1' is not for itself, and the gradation level which is the gradation information in the serial data SDAT1' is not taken in, and control is performed to maintain the current contents set in the PWM unit 194i1e.

That is, when the frame-side VDP control target first decoration LED control circuit 194i1 receives the serial data SDAT1′ from the first serial controller 194gd3 in the frame-side signal separation control circuit 194g based on the clock signal SCLK1′, the serial data When the electric LED designation information in SDAT1' does not include its own ID, the gradation information in serial data SDAT1' is not taken in, and the VDP4160a with a built-in sound source directly controls among the corresponding decorative boards of the door frame 5. For the plurality of LEDs (decorative LEDs) provided on each of the plurality of frame-side VDP control target decorative substrates that are control targets, the gradation level that is the gradation information that was previously captured is maintained. The frame-side VDP control target second decoration LED control circuit 194i2 to the frame-side VDP control target first 143 decoration LED control circuit 194i143 are similar to the frame-side VDP control target first decoration LED control circuit 194i1. In addition, when the serial data SDAT1′ to the serial data SDAT11′ from the first serial controller 194gd1 to the eleventh serial controller 194gd11 in the frame side signal separation control circuit 194g are received based on the clock signal SCLK1′ to the clock signal SCLK11′, the serial data When the electric LED designation information in SDAT1' to serial data SDAT11' does not include its own ID, the gradation information in serial data SDAT1' to serial data SDAT11' is not taken in and each decoration of the corresponding door frame 5 is not captured. Among the boards, the gradation information acquired last time is applied to a plurality of LEDs (decorative LEDs) provided on each of a plurality of frame-side VDP control target decorative boards that are directly controlled by the sound source built-in VDP 4160a. Maintain a certain gradation.

The PWM unit 194i1e is capable of controlling the brightness (gradation level) of the LEDs in each channel in a total of 128 gradation levels from 0 (zero) to 127 (luminance) from turning off to lighting (maximum brightness). Therefore, the gradation control is performed by one PWM gradation control unit for one channel. That is, in the PWM unit 194i1e, the gradation control is performed by the PWM gradation control unit 1 for the decoration LED on 1ch, the gradation control is performed by the PWM gradation control unit 2 for the decoration LED on 2ch,... The PWM gradation control unit 24 controls the gradation of the decorative LED on the 24ch, and is composed of a total of 24 PWM gradation control units 1 to 24. When the gradation levels are set, the PWM gradation control section 1 to the PWM gradation control section 24 set a constant current based on the clock signal from the clock generation section 194i1c so that a current having the set gradation level flows. The drive unit 194i1f is controlled.

The constant current driving unit 194i1f is a full-color LED that is a decorative LED by one constant current driver for one channel so that the gradation level is set in the PWM gradation control unit 1 to the PWM gradation control unit 24. The constant current driver 1 to the constant current driver 24 are provided in total for supplying a constant current to the LED elements constituting the.

The constant current driver 1 to the constant current driver 8 are electrically connected to one end of a resistor Rr1′ that sets the maximum current flowing through the decorative LED in the eight channels from 1ch to 8ch and the other end of the resistor Rr1′. Is grounded to the ground (GND), and one end of a resistor Rg1′ that sets the maximum current flowing through the decorative LED in the 8 channels from 9ch to 16ch is electrically connected to the constant current driver 9 to the constant current driver 16. At the same time, the other end of the resistor Rg1' is grounded to the ground (GND), and the constant current driver 17 to constant current driver 24 is a resistor for setting the maximum current flowing through the decorative LED in the eight channels from 17ch to 24ch. One end of Rb1' is electrically connected and the other end of the resistor Rb1' is grounded to the ground (GND).

The anode terminal of the red LED element, the anode terminal of the green LED element, and the anode terminal of the blue LED element, which compose the full-color LEDs corresponding to the constant current driver 1 to the constant current driver 24, respectively, are the power supply for illumination ( Control power supply). The cathode terminals of the red LED elements forming the full-color LEDs corresponding to the constant current driver 1 to the constant current driver 8 are electrically connected to the LR1 terminal to the LR8 terminal, respectively, and the constant current driver 9 to the constant current driver 16 respectively. The cathode terminal of the green LED element that constitutes the corresponding full-color LED is electrically connected to the LG1 terminal to LG8 terminal, and the blue LED element that constitutes the corresponding full-color LED with the constant current driver 17 to constant current driver 24, respectively. The cathode terminal of is electrically connected to the LB1 terminal to the LB8 terminal.

Then, the constant current driver 1 to the constant current driver 8 set the constant currents individually set to the red LED elements constituting the full-color LEDs, which are the decorative LEDs corresponding to the eight channels from 1ch to 8ch, respectively, to LR1. Each of the constant current driver 9 to the constant current driver 16 is individually supplied to a green LED element forming a full-color LED which is a decorative LED corresponding to 8 channels from 9ch to 16ch. The constant currents set to 1 are flowed through the LG1 terminal to the LG8 terminal, respectively, and the constant current driver 17 to the constant current driver 24 constitute a full-color LED that is a decorative LED corresponding to each of eight channels from 17ch to 24ch. A constant current set individually for each blue LED element is supplied via the LB1 to LB8 terminals.

Note that various internal circuits of the decorative LED driver IC are used as the internal power supply Vreg by applying the control voltage DVp to the power supply terminal of the decorative LED driver IC that constitutes the frame-side VDP control target first decorative LED control circuit 194i1. To the ground (GND) of the decorative LED driver IC 194 by grounding the GND terminal, which is a ground terminal, to the ground (GND).

As described above, the decorative LED driver ICs configuring the frame-side VDP control target first decorative LED control circuit 194i1 to the frame-side VDP control target 143 decorative LED control circuit 194i143 respectively include 24 LED elements, that is, Since eight full-color LEDs, which are decorative LEDs, can be individually dimmed and turned on, such dimming and lighting can turn off, turn on one gradation, and blink one gradation. Further, the decoration LED driver ICs configuring the frame-side VDP control target first decoration LED control circuit 194i1 to the frame-side VDP control target 143 decoration LED control circuit 194i143 are 1144 (=8) as decoration LEDs. Full-color LEDs x 143 full-color LEDs of decorative LED control circuits (decorative LED driver ICs), that is, 3432 (= three LED elements of red, green, and blue x 1144 full-color LEDs) LEDs It is possible to perform dimming lighting of a large number of decorative LEDs called elements.

In addition, the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 selects, from among the decorative boards of the door frame 5, a plurality of frame-side VDP control target decorative boards that are directly controlled by the sound source built-in VDP 4160a. Instead of directly outputting the signals for individually performing the dimming lighting to a plurality of LEDs (decorative LEDs) provided in each, the peripheral side MDP4150a and the frame side VDP control target first circuit which is a different circuit Decorative LED control circuit 194i1 to frame-side VDP control target A plurality of frame-side VDPs that are directly controlled by the sound source built-in VDP 4160a in each decorative substrate of the door frame 5 by the 143rd decorative LED control circuit 194i143 By directly outputting a signal for individually performing dimming lighting to a plurality of LEDs (decorative LEDs) provided on each of the control target decorative substrates, the dimming lighting of the plurality of LEDs is performed in detail. The load control can be separated from the control by the peripheral control MPU 4150a and given to the decoration LED control circuit 194i143 of the frame side VDP control target first decoration LED control circuit 194i1 to frame side VDP control target 143i143, respectively.

As described above, the electric decoration information includes a plurality of LEDs provided on each of the plurality of frame-side VDP control target decorative boards, which are control targets directly controlled by the sound source built-in VDP 4160a, among the respective decorative boards of the door frame 5. A plurality of door frame side light emission mode setting image data for setting the light emission mode of the (decorative LED) is stored in advance in the liquid crystal and sound control ROM 4160b. Then, the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 selects, from among the decorative boards of the door frame 5, a plurality of frame-side VDP control target decorative boards that are directly controlled by the sound source built-in VDP 4160a. The control with delicate processing load, such as dimming lighting of a plurality of LEDs (decorative LEDs) provided for each, is performed by the frame side VDP control target first decoration LED control circuit 194i1 to the frame side VDP control target first 143 decoration. Since it can be left to each LED control circuit 194i143, it is possible to reduce the processing load of the light emission control of dimming lighting on the peripheral control MPU 4150a. Thereby, even if the variation of the effect by the decoration LED control circuit 194i143 of the frame side VDP control target first decoration LED control circuit 194i1 to the frame side VDP control target 143 is increased, the peripheral control MPU 4150a is dimmed. Since there is no increase in the processing load of the light emission control of lighting, there is no restriction on the variation of the effect. That is, in the present embodiment, it is possible to increase the variation of the effects while reducing the processing load of the light emission control on the peripheral control MPU 4150a, and thus it is possible to make it difficult for the player to lose interest in the effects. .. Therefore, it is possible to contribute to suppressing a decrease in interest.

Further, in the present embodiment, as described above, the decoration LED control circuit 194i143 of the frame-side VDP control target first decoration LED control circuit 194i1 to the frame-side VDP control target 143i includes the frame-side signal separation control circuit 194g. When the serial data SDAT1' to serial data SDAT11' from the first serial controller 194gd1 to the eleventh serial controller 194gd11 are received based on the clock signals SCLK1' to SCLK11', the data in the serial data SDAT1' to serial data SDAT11' are received. When the decoration LED designation information does not include its own ID, the gradation information in the serial data SDAT1' to serial data SDAT11' is not taken in, and the sound source built-in VDP4160a is directly connected to each of the decoration boards of the corresponding door frame 5. The gradation level, which is the gradation information captured last time, is maintained for a plurality of LEDs (decorative LEDs) provided on each of a plurality of frame-side VDP control target decorative substrates that are control targets to be controlled. Has been done.

Further, in the present embodiment, as described above, since the frame frequency is set to 30 fps (about every 33.3 ms), the drawing data is transmitted from the channel CH2 of the VDP4160a with a built-in sound source to the frame peripheral relay terminal board 868, and It is output to the frame decoration drive amplifier board 194 via the peripheral relay terminal board 882. As a result, the frame-side VDP control target first decoration LED control circuit 194i1 to the frame-side VDP control target first 143 decoration LED control circuit 194i143 repeats the gradation degree, which is gradation information, about every 33.3 ms. Since it can be updated, it is assumed that the gradation information in the drawing data output from the channel CH2 of the sound source built-in VDP 4160a has changed to something different from the normal content due to some electrical reason. Even so, the next time, that is, after the elapse of about 33.3 ms, the opportunity to take in the legitimate content can be obtained, so that the light emission mode of the decorative LED is intended to be changed from the normal light emission mode in an extremely short period of about 33.3 ms. Even if the change is made to the non-emissive mode, the player can correct the normal luminescent mode (that is, the normal luminescent mode) without noticing the change.

The frame-side VDP control target first decoration LED control circuit 194i1 to the frame-side VDP control target 143 decoration LED control circuit 194i143 are provided in the right side decoration unit 200 of the door frame 5 shown in FIG. The right side VDP control target first light emission decoration region RTV1 to the right side VDP control target third light emission decoration is performed by dimming and lighting a plurality of LEDs (decorative LEDs) provided on the side VDP control target decoration substrates RV1 to RV3, respectively. The region RTV3 is illuminated and decorated, and a plurality of LEDs (decorative LEDs) provided on the frame side VDP control target decorative substrate RV4 provided in the upper decorative unit 280 of the door frame 5 shown in FIG. The side VDP control target fourth light emission decoration area RTV4 is light-emitted and a plurality of LEDs (decoration) provided on the frame-side VDP control object decoration substrates LV1 to LV3 provided in the left side decoration unit 240 of the door frame 5 shown in FIG. The first side light emitting decoration area LTV1 to the left side VDP control target to the third light emitting decoration area LTV3 to the left side VDP control are light-emitted by performing the dimming lighting of the LED (for LED), and the upper decoration of the door frame 5 shown in FIG. By dimming and lighting a plurality of LEDs (decorative LEDs) provided on the frame-side VDP control object decoration substrate LV4 provided in the unit 280, the left side VDP control object fourth light emission decoration area LTV4 is illuminated and decorated. ing.

In the present embodiment, all the decoration LEDs whose light emission mode is controlled by the frame-side VDP control target first decoration LED control circuit 194i1 to the frame-side VDP control target 143 decoration LED control circuit 194i143 are full-color LEDs. Although the red LED element, the green LED element, and the blue LED element that compose the above are used, a single LED different from the full-color LED (the same color LED may be used, or a plurality of different color LEDs) may be used. Alternatively, one group may be a full-color LED and the other group may be a single LED (LEDs of the same color or LEDs of different colors). It is also possible to combine one group and a plurality of other groups.

[14-3. Configuration of LED control circuit for frame side peripheral control MPU control target decoration]
Next, the configuration of the frame side peripheral control MPU control target decoration LED control circuit will be described. As shown in FIG. 43, the frame decoration drive amplifier board 194 defines the frame side peripheral control MPU control target decoration LED control circuit 194k as the frame side peripheral control MPU control target first decoration LED control circuit 194k1 to frame side peripheral. The control MPU includes a seventh decorative LED control circuit 194k7 (total of 7 circuits) to be controlled.

As described above, the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 synchronizes the frame side light emission data STL-DAT with the frame side light emission clock signal STL-CLK from the frame side decoration board serial I/O port. Then, the signal is output to the frame decoration drive amplifier board 194 via the frame peripheral relay terminal board 868 and the peripheral door relay terminal board 882.

As shown in FIG. 43, the frame side light emission data STL-DAT and the frame side light emission clock signal STL-CLK from the frame side decoration board serial I/O port of the peripheral control MPU 4150a are, as shown in FIG. The frame-side peripheral control MPU control target first decoration LED control circuit 194k1 to the frame-side peripheral control MPU control target seventh decoration LED control circuit 194k7, which form the LED control circuit 194k.

In the present embodiment, the frame-side peripheral control MPU control target first decoration LED control circuit 194k1 to the frame-side peripheral control MPU control target seventh decoration LED control circuit 194k7 are each composed of the same decoration LED driver IC. Among the decorative boards of the door frame 5, a plurality of LEDs (decorative LEDs) provided on each of the frame-side peripheral control MPU control target decorative boards that are directly controlled by the peripheral control MPU 4150a. The light emission by () can be dimmed and turned on. Here, the frame side peripheral control MPU control target first decoration LED control circuit 194k1 will be briefly described below, and the frame side peripheral control MPU control target second decoration LED control circuit 194k1 to frame side peripheral control MPU control The description of the target seventh decorative LED control circuit 194k7 is omitted.

First, the frame side light emission data STL-DAT will be described. The “frame-side light emission data” is information for designating the light emission mode, and is composed of illumination LED designation information and gradation information. The decorative LED designation information is any frame side peripheral control MPU among the frame side peripheral control MPU control target first decoration LED control circuit 194k1 to frame side peripheral control MPU control target seventh decoration LED control circuit 194k7. It is information indicating whether the LED control circuit for decoration of the control object is designated, and an address (ID described later) for identifying the individual LED control circuit for the frame side peripheral control MPU control object decoration is set. Is. The gradation information is information indicating which of the gradation 0 (zero) to the gradation 127 is to be specified.

The frame side peripheral control MPU control target The decoration LED driver IC that constitutes the first decoration LED control circuit 194k1 has 24 output channels (ch) as shown in FIG. 43, and a maximum of 80 mA ( It is a constant current LED driver IC of 24ch that can output a current of milliampere). The decorative LED driver IC mainly includes an address setting unit 194k1a, a logic processing unit 194k1b, a clock generating unit 194k1c, a data buffer unit 194k1d, a PWM unit 194k1e, and a constant current driving unit 194k1f.

The address setting unit 194k1a can set 64 types of addresses as its own IDs (IDs that can identify the individual) by the voltages applied to six device address selection terminals (not shown). The voltage applied to the six device address selection terminals is either one of the voltage pulled up to the control voltage (+5V) side and the voltage pulled down to the ground (GND) side.

As described above, the ID for identifying the individual ornamental LED driver ICs configuring the first ornamental LED control circuit 194k1 for the frame side peripheral control MPU control target is the voltage applied to the six device address selection terminals. The address setting unit 194k1a is set in advance by such a hardware configuration, and is not set appropriately by receiving data by software.

The logic processing unit 194k1b receives the frame side light emission data STL-DAT from the frame side decoration substrate serial I/O port of the peripheral control MPU4150a based on the frame side light emission clock signal STL-CLK and transmits it to the data buffer unit 194k1d. To do. The data buffer unit 194k1d includes its own ID in the illumination LED designation information in the frame side light emission data STL-DAT from the logic processing unit 194k1b based on the address that is its own ID set by the address setting unit 194k1a. When it is determined that the frame side light emission data STL-DAT from the logic processing unit 194k1b is for itself, the gradation degree which is the gradation information in the frame side light emission data STL-DAT is fetched, and the fetched gradation information While controlling to set the gradation degree in each channel in the PWM unit 194k1e so that the gradation degree becomes, the own ID is added to the illumination LED designation information in the frame side light emission data STL-DAT from the logic processing unit 194k1b. When it is not included, it is determined that the frame side light emission data STL-DAT from the logic processing unit 194k1b is not for itself, and the gradation degree which is the gradation information in the frame side light emission data STL-DAT is not fetched, and the PWM unit 194k1e. Control is performed to maintain the current contents set in.

The PWM unit 194k1e is capable of controlling the brightness (gradation level) of the LED in each channel in a total of 128 steps from gradation off to lighting (maximum brightness) from gradation 0 (zero) to gradation 127. Therefore, the gradation control is performed by one PWM gradation control unit for one channel. That is, in the PWM unit 194k1e, gradation control is performed by the PWM gradation control unit 1 for the decoration LED on 1ch, gradation control is performed by the PWM gradation control unit 2 for the decoration LED on 2ch,... The PWM gradation control unit 24 controls the gradation of the decorative LED on the 24ch, and is composed of a total of 24 PWM gradation control units 1 to 24. When the gradation levels are respectively set, the PWM gradation control section 1 to the PWM gradation control section 24 set a constant current so as to flow a current having the set gradation level based on the clock signal from the clock generation section 194k1c. The drive unit 194k1f is controlled.

The constant current drive unit 194k1f is a full-color LED that is a decorative LED by one constant current driver for one channel so that the gradation level is set in the PWM gradation control unit 1 to the PWM gradation control unit 24. The constant current driver 1 to the constant current driver 24 are provided in total for supplying a constant current to the LED elements constituting the.

The constant current driver 1 to the constant current driver 24 are electrically connected to one end of a resistor Rp1 that sets the maximum current flowing through the decorative LED in all channels from 1ch to 24ch, and the other end of the resistor Rp1 is grounded. It is grounded to (GND).

The anode terminal of the red LED element, the anode terminal of the green LED element, and the anode terminal of the blue LED element, which compose the full-color LEDs corresponding to the constant current driver 1 to the constant current driver 24, respectively, are the power supply for illumination ( Control power supply). The cathode terminals of the red LED elements forming the full-color LEDs corresponding to the constant current driver 1 to the constant current driver 8 are electrically connected to the LR1 terminal to the LR8 terminal, respectively, and the constant current driver 9 to the constant current driver 16 respectively. The cathode terminal of the green LED element that constitutes the corresponding full-color LED is electrically connected to the LG1 terminal to LG8 terminal, and the blue LED element that constitutes the corresponding full-color LED with the constant current driver 17 to constant current driver 24, respectively. The cathode terminal of is electrically connected to the LB1 terminal to the LB8 terminal.

Then, the constant current driver 1 to the constant current driver 8 set the constant currents individually set to the red LED elements constituting the full-color LEDs, which are the decorative LEDs corresponding to the eight channels from 1ch to 8ch, respectively, to LR1. Each of the constant current driver 9 to the constant current driver 16 is individually supplied to a green LED element forming a full-color LED which is a decorative LED corresponding to 8 channels from 9ch to 16ch. The constant currents set to 1 are flowed through the LG1 terminal to the LG8 terminal, respectively, and the constant current driver 17 to the constant current driver 24 constitute a full-color LED that is a decorative LED corresponding to each of eight channels from 17ch to 24ch. A constant current set individually for each blue LED element is supplied via the LB1 to LB8 terminals.

Note that various types of decorative LED driver ICs are used as the internal power supply Vreg by applying the control voltage DVp to the power supply terminals of the decorative LED driver ICs that constitute the frame side peripheral control MPU control target first decorative LED control circuit 194k1. The ground in various internal circuits of the LED driver IC for decoration is grounded to the ground (GND) of the frame decoration drive amplifier board 194 by being supplied to the internal circuit and grounding the GND terminal, which is a ground terminal, to the ground (GND). ..

In this way, the decoration LED driver ICs configuring the frame-side peripheral control MPU control target first decoration LED control circuit 194k1 to the frame-side peripheral control MPU control target eighth decoration LED control circuit 194k8 respectively include LED elements. Since 24 pieces, that is, 8 full-color LEDs that are decoration LEDs can be individually dimmed and turned on, such dimming turns off, turns on one gradation, and blinks one gradation. be able to. Further, the decoration LED driver ICs configuring the frame-side peripheral control MPU control target first decorative LED control circuit 194k1 to the frame-side peripheral control MPU control target seventh decorative LED control circuit 194k7 are 56 decorative LEDs. (=8 full-color LEDs x 7 decorative LED control circuits (decorative LED driver ICs)) full-color LEDs, that is, 168 (= 3 LED elements of red, green, and blue x 56 full-color LEDs) It is possible to perform dimming lighting of the LED element of (LED).

The frame-side peripheral control MPU control target first decorative LED control circuit 194k1 is provided in plural on the frame-side peripheral control MPU control target decorative board RM1 provided in the right side decoration unit 200 of the door frame 5 shown in FIG. By performing dimming lighting of the LED (decorative LED), the right side peripheral control MPU control target first light emission decoration area RTM1 is light-emitted and the right side of the door frame 5 shown in FIG. The right side peripheral control MPU control target second light emission decoration region RTM2 emits light by performing dimming lighting of a plurality of LEDs (decorative LEDs) provided on the frame side peripheral control MPU control target decoration substrate RM2 provided in the side decoration unit 200. It is designed to be decorated.

The frame-side peripheral control MPU control target second decorative LED control circuit 194k2 includes a plurality of LEDs provided on the frame-side peripheral control MPU control target decorative substrate RM3 provided in the right side decoration unit 200 of the door frame 5 shown in FIG. By performing the dimming lighting of the (decoration LED), the right side peripheral control MPU control target third light emission decoration region RTM3 is light-emitted and the upper decoration unit of the door frame 5 shown in FIG. The right side peripheral control MPU control target fourth light emission decoration region RTM4 is light-emitted by performing the dimming lighting of a plurality of LEDs (decorative LEDs) provided on the frame side peripheral control MPU control target decoration substrate RM4 provided in 280. It is like this.

The frame side peripheral control MPU control target third decoration LED control circuit 194k3 is a plurality of LEDs provided on the frame side peripheral control MPU control target decorative substrate LM1 provided in the left side decoration unit 240 of the door frame 5 shown in FIG. By performing the dimming lighting of the (decorative LED), the left side peripheral control MPU control target first light emission decoration area LTM1 is light-emitted and the left side decoration of the door frame 5 shown in FIG. By dimming and lighting a plurality of LEDs (decorative LEDs) provided on the frame-side peripheral control MPU control target decorative substrate LM2 included in the unit 240, the left side peripheral control MPU control target second light emission decoration region LTM2 is light-emitted. It has become so.

The frame side peripheral control MPU control target fourth decoration LED control circuit 194k4 is a plurality of LEDs provided on the frame side peripheral control MPU control target decorative substrate LM3 provided in the left side decoration unit 240 of the door frame 5 shown in FIG. By performing the dimming lighting of the (decorative LED), the left side peripheral control MPU control target third light emission decoration area LTM3 is configured to emit light, and the upper decoration unit of the door frame 5 shown in FIG. The left side peripheral control MPU control target fourth light emission decoration area LTM4 is light-emitted by performing the dimming lighting of a plurality of LEDs (decorative LEDs) provided on the frame side peripheral control MPU control target decoration substrate LM4 provided in 280. It is like this.

Frame-side peripheral control MPU control target fifth decoration LED control circuit 194k5 to frame-side peripheral control MPU control target seventh decoration LED control circuit 194k7 is provided in the dish unit 300 and the operation unit 400 shown in FIG. The entire dish unit 300 is illuminated and decorated by dimming and lighting a plurality of LEDs (ornamental LEDs) provided on each of the frame-side peripheral control MPU control target decorative substrates, and the operation unit is also provided. The dial operation unit 401 and the pressing operation unit 405 of 400 are decorated with light emission.

Here, in the present embodiment, as described above, each decorative board of the door frame 5 includes a plurality of frame-side peripheral control MPU control target decorative boards that are control targets that the peripheral control MPU 4150a directly controls, and a sound source built-in. There is a plurality of frame-side VDP control target decoration substrates that are directly controlled by the VDP 4160a, and a plurality of decorative LEDs provided on the door frame 5 are those whose light emission is controlled by the peripheral control MPU 4150a. It is divided into one in which light emission is controlled by the built-in VDP 4160a. This is because the plurality of LEDs (decorative LEDs) provided on each of the plurality of frame-side peripheral control MPU control target decorative boards that are controlled by the peripheral control MPU 4150a directly change the light emission mode of the production process. Those that change slowly along the line (for example, the light emission mode fluctuates like a gentle wave, the light emission mode continues for a predetermined time, and even if the light emission mode is fast, it blinks at a speed at which a person blinks (blinks). A plurality of LEDs provided on each of the plurality of frame-side VDP control target decorative boards that are directly controlled by the sound source built-in VDP 4160a. The (decorative LED) has a light emitting mode that changes rapidly in accordance with the progress of the production (for example, as a light emitting mode in dot display using an LED (decorative LED), high speed as if lightning is expressed. Blinking (blinking), expressing fireworks, expressing explosions, scrolling patterns, displaying moving images of people and vehicles), which is a processing load. (These light emitting modes can be changed promptly according to the progress of the effect displayed in the display area of the game board side effect display unit 1900 included in the game board 4 shown in FIG. 8, and are linked to the effect. You can do that). That is, in the present embodiment, in the light emission control of the plurality of decorative LEDs provided on the door frame 5, the peripheral control MPU 4150a takes charge of the one that is less likely to become the processing load, whereas the peripheral control MPU 4150a takes charge of the one that becomes the processing load. Instead, the VDP4160a with a built-in sound source is in charge. The frame side peripheral control MPU control target of the frame decoration drive amplifier board 194 is the first decoration LED control circuit 194k1 to the frame side peripheral control MPU control target The seventh decoration LED control circuit 194k7 is the frame side light emission as described above. When the data STL-DAT is not for itself, the current content is maintained to maintain the current light emission mode. In other words, for a light emission mode that slowly changes as the production progresses, the same light emission mode is used for a longer period of time, so when the light emission mode changes, the peripheral control MPU 4150a moves toward the frame side. Since the emission data STL-DAT is output, it is difficult for the peripheral control MPU 4150a to become a processing load.

As described above, in the present embodiment, the periphery of the plurality of LEDs (decorative LEDs) provided on each of the plurality of frame-side VDP control target decorative substrates that are directly controlled by the sound source built-in VDP 4160a Compared with a plurality of LEDs (decorative LEDs) provided on each of a plurality of frame-side peripheral control MPU control target decorative substrates that are controlled directly by the control MPU 4150a, an effect in which the light emission mode changes faster is assigned. ing. It should be noted that even in the plurality of LEDs (decorative LEDs) provided on each of the plurality of frame-side VDP control target decorative boards that are the control targets that the sound source built-in VDP 4160a directly controls, the peripheral control MPU 4150a also controls the plurality of LEDs (decorative LEDs) that are directly controlled. Similar to the light emission mode of the plurality of LEDs (decorative LEDs) provided on each of the plurality of frame-side peripheral control MPU control target decoration substrates, the light emission mode may change slowly along with the production. Therefore, in this case, the peripheral control MPU 4150a directly operates on the plurality of LEDs (decorative LEDs) provided on each of the plurality of frame-side VDP control target decorative substrates that are controlled by the sound source built-in VDP 4160a. Compared with a plurality of LEDs (decorative LEDs) provided on each of a plurality of frame-side peripheral control MPU control target decorative substrates that are control targets to be controlled, effects that have the same change in light emission mode are assigned. Become.

In the present embodiment, the frame-side peripheral control MPU control target first decorative LED control circuit 194k1 to the frame-side peripheral control MPU control target seventh decorative LED control circuit 194k7 is a decorative LED whose light emission mode is controlled. Used a red LED element, a green LED element, and a blue LED element, all of which compose a full-color LED, but a single LED different from the full-color LED (the same color LED may be used, or a plurality of different colors may be used). LED), and one frame side peripheral control MPU control target decoration LED control circuit is a full color LED and the other frame side peripheral control MPU control target decoration LED control circuit is a single color LED. It is also possible to use LEDs (LEDs of the same color or LEDs of different colors), and such one frame side peripheral control MPU control target decorative LED control circuit and other frame side peripheral control MPU control It is also possible to combine a plurality of target decoration LED control circuits.

[15. Commands related to transmission/reception of main control board]
Next, various commands transmitted from the main control board 4100 to the payout control board 4110 and various commands transmitted from the main control board 4100 to the peripheral control board 4140 will be described with reference to FIGS. 44 to 47. 44 is a table showing an example of various commands transmitted from the main control board to the payout control board, and FIG. 45 is a table showing an example of various commands transmitted from the main control board to the peripheral control board. Is a table showing a continuation of various commands transmitted from the main control board to the peripheral control board in FIG. 45, and FIG. 47 is a table showing an example of various commands from the payout control board received by the main control board. First, the prize ball command which is a command related to payout transmitted from the main control board to the payout control board will be described, and subsequently, various commands transmitted from the main control board to the peripheral control board will be described and received by the main control board. Various commands from the payout control board will be described.

[15-1. Various commands sent from the main control board to the payout control board]
The main control MPU 4100a of the main control board 4100 detects from various winning switches such as the general winning opening switches 3020 and 3020, the first starting opening switch 3022, the second starting opening switch 2109, and the count switch 2110 shown in FIG. When signals are input, a prize ball command for paying out a predetermined number of game balls as prize balls is transmitted to the payout control board based on these detection signals. This prize ball command is a command having a storage capacity of 1 byte (8 bits). In the present embodiment, the pachinko gaming machine 1 and the CR unit 6 (communicating with the pachinko gaming machine 1 to drive the payout motor 744 of the pachinko gaming machine 1 (prize ball device 740) to store the upper tray 301, When the lower plate 302 is electrically connected to a device for paying out game balls as a rental ball (such a pachinko gaming machine is referred to as a "CR machine"), as shown in FIG. 44(a). In the prize ball command transmitted from the main control board 4100 to the payout control board 4110, commands 10H to 1EH (“H” represents a hexadecimal number) are prepared. In the command 10H, one prize ball is provided. The command 11H specifies two prize balls, and the command 1EH specifies 15 prize balls. The payout control board 4110 controls the payout motor 744 to pay out the game balls by the designated number of prize balls.

In addition, a pachinko gaming machine 1 and a ball lending machine (a device that directly pays out the game balls to the upper plate 301 and the lower plate 302, which are storage plates, as rental balls) are installed adjacent to the game hall (hall). When the gaming machine 1 and the ball lending machine are electrically connected (such a pachinko gaming machine is referred to as "general machine"), as shown in FIG. 44(b), payout from the main control board 4100. Command 20H to command 2EH are prepared as prize ball commands to be transmitted to the control board 4110. One prize ball is designated by the command 20H, two prize balls are designated by the command 21H,..., Command In 2EH, 15 prize balls are designated. The payout control board 4110 controls the payout motor 744 to pay out the game balls by the designated number of prize balls.

As shown in FIG. 44(c), a command 30H is prepared as a command common to CR machines and general machines, and self-check is designated in this command 30H. By transmitting the command 30H and checking whether or not the ACK signal is input, the transmitting side transmits the command 30H when the ACK signal to be output as confirmation of receipt of the command is not input from the receiving side for a predetermined period after transmitting the command. Check the connection status. In the case of the CR machine according to the present embodiment, the payout control board 4110 confirms the connection state with the CR unit 6.

[15-2. Various commands sent from the main control board to the peripheral control board]
Next, various commands transmitted from the main control board 4100 to the peripheral control board 4140 will be described. The main control MPU 4100a of the main control board 4100 transmits various commands to the peripheral control board 4140 based on the progress of the game. These various commands are commands having a storage capacity of 2 bytes (16 bits). As shown in FIGS. 45 and 46, a status indicating the type of command having a storage capacity of 1 byte (8 bits), And a mode showing a variation of the effect having a storage capacity of 1 byte (8 bits).

As shown in FIGS. 45 and 46, various commands include special figure 1 synchronization effect related, special figure 2 synchronization effect related, jackpot related, power-on, general figure synchronization effect related, normal electric figure effect related, notification display, status It is divided into display and other.

[15-2-1. Special figure 1 synchronization production related]
The special figure 1 tuning effect-related is based on the detection signal from the first starting opening switch 3022 shown in FIG. 14, and the division thereof is, as shown in FIG. 45, the function display substrate 1191 shown in FIG. Concerning the above special symbol display 1185, it is composed of commands named special figure 1 synchronization effect start, special symbol 1 designation, special figure 1 synchronization effect end, and fluctuation state designation. To these various commands, "A*H" is assigned as the status, and "**H"("H" represents a hexadecimal number) is assigned as the mode ("*" is a specific hexadecimal number). It indicates that it is predetermined according to the specifications of the pachinko gaming machine 1).

The special figure 1 entrainment effect start command is for instructing the special figure entrainment effect start in the effect pattern specified by the mode, and the special symbol 1 specification command is for specifying a deviant, a specific big hit, or a non-specific big hit. The special figure 1 entrainment effect end command is for instructing the end of the special figure 1 entrainment effect, and the fluctuation state designation command is for instructing the probability and the time saving state. The probability and the time saving state include a low probability time saving state that indicates a low probability state and a time saving state, a high probability time saving state that indicates a high probability state that is a time saving state, and a low probability. It is composed of a low-probability non-time saving state that indicates a state that is not a time saving state, and a high probability non-time saving state that indicates that a state is a high probability state that is not a time saving state (as a normal gaming state, Low probability non-time saving state is set). Here, the high-probability state is a state in which the probability of a big hit is set higher than the low-probability state (normal game state), and the short-time state is, for example, the normal symbol display 1189 shown in FIG. Compared to the non-time saving state (normal gaming state), the time for displaying symbols in a variable manner is shortened and stopped and displayed in the light emission pattern corresponding to the ordinary lottery result, so that the ordinary lottery result by the ordinary lottery described later in the predetermined time can be displayed. In addition to increasing the number of times of stop display as compared with the non-time saving state, the period during which the movable piece 2106 shown in FIG. 8 is opened and closed is made longer than that in the non-time saving state (normal game state) and shown in FIG. A state in which a lottery opportunity for special symbols can be obtained without reducing the number of balls held by increasing the acceptance rate (entering rate) of game balls into the second starting opening 2102 (in other words, compared with the non-time saving state, A game ball to the second starting opening 2102 by increasing the number of decisions as to whether to open/close the movable piece 2106 and lengthening the period of opening/closing operation of the movable piece 2106 when opening/closing the movable piece 2106. Is a state of increasing the acceptance rate (ball entry rate).

As the transmission timing of these various commands, the special figure 1 tuning effect start command is sent at the time of starting the special symbol 1 variation, the special symbol 1 designation command is sent immediately after the start of the special figure 1 tuning effect, and the special figure 1 tuning The production end command is transmitted when the special symbol 1 variation time elapses (when the special symbol 1 is confirmed), and the variation state designation command is transmitted immediately after the special symbol winning information designation. Note that these various commands are actually transmitted in the peripheral control board command transmission process of step S120 in the main control side timer interrupt process described later.

[15-2-2. Special figure 2 synchronization performance related]
The special figure 2 tuning effect-related is based on the detection signal from the second starting port switch 2109 shown in FIG. 14, and the function display substrate 1191 shown in FIG. Regarding the lower special symbol display device 1186, the special symbol 2 synchronization effect start, special symbol 2 designation, and special command 2 synchronization effect end is composed of commands. To these various commands, “B*H” is assigned as the status, and “**H” (“H” represents a hexadecimal number) is assigned as the mode (“*” is a specific hexadecimal number). It indicates that it is predetermined according to the specifications of the pachinko gaming machine 1).

The special figure 2 entrainment effect start command is for instructing the special figure entrainment effect start in the effect pattern specified by the mode, and the special symbol 2 specifying command is for specifying the deviating, a specific jackpot, or a non-specific jackpot. The special figure 2 entrainment effect end is an instruction to end the special figure 2 entrainment effect.

As the transmission timing of these various commands, the special figure 2 tuning effect start command is sent at the time of starting the special symbol 2 variation, the special symbol 2 designation command is sent immediately after the start of the special figure 2 tuning effect, and the special figure 2 tuning The production end command is transmitted when the special symbol 2 variation time has elapsed (when the special symbol 2 is confirmed). Note that these various commands are actually transmitted in the peripheral control board command transmission process of step S120 in the main control side timer interrupt process.

[15-2-3. Jackpot related]
As shown in FIG. 45, in the category of big hit related, big hit opening, big winning opening 1 open N times display, big winning opening 1 closed display, big winning opening 1 count display, big hit ending, big hit symbol display, small hit opening , Small hit open display, small hit count display, and small hit ending command. To these various commands, "C*H" is assigned as the status, and "**H"("H" represents a hexadecimal number) is assigned as the mode ("*" is a specific hexadecimal number). It indicates that it is predetermined according to the specifications of the pachinko gaming machine 1).

The big hit opening command is an instruction to start the big hit opening, and the big winning opening 1 opening N-th display command starts during the big winning opening 1 opening of the 1st to 16th rounds (shown in FIG. 8 of the attacker unit 2100). It is for instructing to open or start opening the Nth round of the special winning opening 2103, and the special winning opening 1 closing display command starts during the closing of the special winning opening 1 (the big winning opening of the attacker unit 2100). 2103 is being closed or is being closed), and the special winning opening 1 count display command indicates that the number of 0 to 10 gaming balls has been counted (the count switch shown in FIG. 14). The number of gaming balls that entered the jackpot 2103 detected by 2110) is transmitted, the jackpot ending command is an instruction to start the jackpot ending, and the jackpot symbol display command is a jackpot symbol information. The display is instructed.

The small hit opening command is for instructing to start the small hit opening, and the small hit opening display command is for starting the small hit opening (during the small hit, the big winning opening 2103 of the attacker unit 2100 is open or open). The small hit count display command is for a small hit medium big winning opening winning effect (when a game ball that entered the big winning opening 2103 during the small hit is detected by the count switch 2110). The small hitting ending command is an instruction to start the small hitting ending.

As the transmission timing of these various commands, the big hit opening command is sent at the start of the big hit opening, and the big winning opening 1 opening N-th display command is the big winning opening 1 opening of the 1st to 16th rounds (the big hit of the attacker unit 2100). When the winning opening 2103 is opened), the special winning opening 1 closing display command is sent when the special winning opening 1 is closed (closing of the special winning opening 2103 of the attacker unit 2100 is started). The mouth 1 count display command is used when the special winning opening 1 is opened and when the count to the special winning opening 1 is changed (when the special winning opening 2103 of the attacker unit 2100 is opened and the game ball entering the big winning opening 2103 is a count switch). 2110), the big hit ending command is sent when the big hit ending starts, and the big hit symbol display command is sent when the special winning opening is opened (when the special winning opening 2103 of the attacker unit 2100 is opened). It

The small hit opening command is transmitted at the start of the small hit opening, and the small hit opening display command is transmitted when the small hit is opened (when the special winning opening 2103 of the attacker unit 2100 is opened during the small hit). The hit count display command is transmitted at the time of winning the small hit medium-large winning opening (when the game ball that entered the big winning opening 2103 during the small hit is detected by the count switch 2110), and the small hit ending command is It is sent when the small hit ending starts. Note that these various commands are actually transmitted in the peripheral control board command transmission process of step S120 in the main control side timer interrupt process.

[15-2-4. Power on]
As shown in FIG. 45, the category of power-on is composed of a command named power-on state, power-on main control return destination, and power-on main prize ball number information output determination counter notification. .. A status of "D*H" and a mode of "**H"("H" represents a hexadecimal number) are assigned to these various commands ("*" is a specific hexadecimal number). It indicates that it is predetermined according to the specifications of the pachinko gaming machine 1).

The power-on state command is for instructing the RAM clear effect start and the game state. The power-on state command is for the payout control board 4110 shown in FIG. 15 at the time of power-on (including power-on, power recovery when power failure or momentary power failure occurs and power is restored). Information indicating that when the operation switch 860a is operated to clear the RAM, and information at the time of power-on (including power-on and power-recovery when power is restored due to a power failure or momentary power failure) .), information indicating which of the above-mentioned low-probability time-saving state, high-probability time-saving state, low-probability non-time-saving state, and high-probability non-time-saving state (probability and time-saving state) is used for recovery. , Information indicating the model code of the pachinko gaming machine. The model code of this pachinko machine is, for example, when creating so-called max type, middle type, and sweet digital type, which game is the copyright for, what kind of game specification (for example, probability variation is When it occurs, in addition to the game specification that the state is continued until the next big hit game state occurs, the probability variation occurs in a state where the number of times the special symbol changes is limited (for example, 30 times or 70 times). It is for specifying whether it is a specification (so-called ST machine) or the like. In other words, the model code information of the pachinko gaming machine specifies the series code for specifying which type is the max type, the middle type, and the sweet digital type indicating the model type, and the copyright of the work. Copyright code for, and game specifications (for example, if probability changes occur, in addition to the game specifications that the state will continue until the next big hit game state occurs, probability in the state where the number of changes of special symbols is limited It mainly consists of a game specification code for specifying a game specification (ST machine, etc.) in which fluctuation occurs.

The power-on main control return destination command instructs the return destination of the main control board 4100 itself. The power-on main control return destination command is mainly composed of information for instructing the driving state of the starting opening solenoid 2105 shown in FIG. 14 and information for instructing the driving state of the attacker solenoid 2108 shown in FIG. ing.

When the power is turned on, the main prize ball number information output determination counter notification command includes a first starting opening 2101, a second starting opening 2102, a general winning opening 2104, 2201, and a large winning opening in which the main control board 4100 is provided on the game board 4. The main control is used to instruct the value of the main prize ball number information output determination counter that counts the number of game balls that are to be paid out as prize balls based on the game balls that have entered the various winning holes such as 2103. It is stored and held (backed up) as one of the game backup information in the built-in RAM. When the power is turned on, the main award ball number information output determination counter notification command is mainly issued when the power is turned on (including when the power is turned on, and when the power is restored after a power failure or momentary power failure occurs). The value of the main prize ball number information output determination counter is read out from the game backup information stored (backed up) in the control built-in RAM and created. When the operation switch 860a of the payout control board 4110 shown in FIG. 15 is operated to clear the RAM, the game backup information stored and held (backed up) in the main control built-in RAM is initialized to cause the main operation. The value of the prize ball number information output determination counter is set to an initial value of 0 (zero) (that is, when the operation switch 860a of the payout control board 4110 shown in FIG. 15 is operated and the RAM is cleared. Is forcibly set to zero as the number of game balls to be paid out as prize balls).

As the transmission timing of the power-on status command, the power-on main control return destination command, and the power-on main prize ball number information output determination counter notification command, when the main control board power-on (in addition to power-on, Including power recovery when power is restored due to power failure or momentary power failure). Specifically, when the pachinko gaming machine 1 is powered on, when returning from a power failure or momentary power failure, a main control side power-on process described below is executed, and the peripheral control board of step S120 in the main control side timer interrupt process. In the command transmission process, a power-on state command, a power-on main control return destination command, and a power-on main prize ball number information output determination counter notification command are transmitted.

[15-2-5. Normal figure synchronization production related]
The general figure synchronization effect-related is based on the detection signal from the gate switch 2352 shown in FIG. 14, and the division thereof is, as shown in FIG. 45, the normal pattern display of the function display substrate 1191 shown in FIG. Concerning the device 1189, it is composed of commands named general figure synchronization effect start, general figure designation, general figure synchronization effect end, and fluctuation state designation. These various commands are assigned status "E*H" and mode "**H"("H" represents a hexadecimal number) ("*" is a specific hexadecimal number). It indicates that it is predetermined according to the specifications of the pachinko gaming machine 1).

The universal figure synchronization effect start command is for instructing to start the universal figure synchronization effect in the effect pattern specified by the mode, and the universal pattern specification command is for specifying a falling edge, a specific jackpot, or a non-specific jackpot. The figure synchronization effect end command is for instructing the end of the normal figure synchronization effect, and the variation state designation command is for instructing the probability and the time saving state. As described above, the probability and the time saving state are a low probability time saving state that indicates a low probability state and a time saving state, and a high probability time saving that indicates a high probability state and a time saving state. State, a low-probability non-time saving state that indicates a low-probability state that is not a short-time state, and a high-probability non-time-saving state that indicates a high-probability state that is not a short-time state (normally As the gaming state, a low probability non-time saving state is set).

As the transmission timing of these various commands, the universal figure synchronization effect start command is transmitted at the time of the start of the normal symbol 1 variation, the universal symbol specification command is transmitted immediately after the start of the universal figure synchronization effect, and the universal figure synchronization effect end command is , Ordinary symbol variation time elapses (ordinary symbol is determined), the state change command at the time of variation is transmitted immediately after the universal symbol winning information designation. Note that these various commands are actually transmitted in the peripheral control board command transmission process of step S120 in the main control side timer interrupt process.

[15-2-6. Normal electric role production related]
The normal electric role effect-related relates to the movable piece 2106 shown in FIG. 8 which is opened and closed by driving the starting opening solenoid 2105 shown in FIG. 14, and is divided into sections as shown in FIG. It consists of a command called the opening, the opening of the public train, and the end of the map. These various commands are assigned status "F*H" and mode "**H"("H" represents a hexadecimal number) ("*" is a specific hexadecimal number). It indicates that it is predetermined according to the specifications of the pachinko gaming machine 1).

The universal figure opening command is for instructing the opening of the universal figure, and the universal battery open display command is for starting the universal battery open (a state in which the movable piece 2106 is opened in the left-right direction by driving the starting opening solenoid 2105). , Or at the time of expansion), and the ending command per universal figure is an instruction to start ending per universal figure.

As the transmission timing of these various commands, the opening command for a universal figure is transmitted at the start of the opening for a universal figure, and the opening command for universal communication is opened when the universal communication is opened (the movable piece 2106 is driven in the left-right direction by driving the starting opening solenoid 2105). The ending command per universal figure is transmitted at the start of ending per universal figure. Note that these various commands are actually transmitted in the peripheral control board command transmission process of step S120 in the main control side timer interrupt process.

[15-2-7. Notification display]
As shown in FIG. 46, the notification display category is made up of commands such as winning abnormality display, connection abnormality display, disconnection/short circuit abnormality display, magnetic detection switch abnormality display, door opening, and door closing. A status of "6*H" and a mode of "**H"("H" represents a hexadecimal number) are assigned to these various commands ("*" is a specific hexadecimal number). It indicates that it is predetermined according to the specifications of the pachinko gaming machine 1).

The winning abnormality display command is for a game ball to enter the special winning opening 2103 of the attacker unit 2100 when the special winning opening is won other than during the big hit (condition device is operating). When the count switch 2110 detects), the start of the prize abnormality notification is instructed, and the connection abnormality display command is, for example, an electrical connection in a path between the main control board 4100 and the payout control board 4110. When there is an abnormality, it is for instructing to start the connection abnormality notification, and the disconnection/short-circuit abnormality display command includes, for example, the main control board 4100, the first starting port switch 3022, the second starting port switch 2109, and the count switch 2110. When the disconnection/short circuit of the electrical connection with the magnetic detection switch 3024 shown in FIG. 14 is detected, the magnetic detection switch abnormality display command is used to instruct the start of the disconnection/short circuit abnormality display. When it occurs, the magnetic detection switch abnormality notification is instructed to start.

Further, the door opening command is issued to the main body frame 3 by the door frame 5 based on the detection signal (opening signal) from the door frame opening switch 618 input through the payout control board 4110 shown in FIG. When the door is opened, the door opening is instructed, and the door closing command closes the door frame 5 to the main body frame 3 based on the detection signal from the door frame opening switch 618. When it is in the open state, the end of the door opening notification is instructed.

As for the transmission timing of these various commands, the prize abnormality display command is transmitted when the prize is won in the special winning opening other than during the big hit (condition device is operating), and the connection abnormality display command is sent from the main control board 4100 to the payout control board 4110. Is sent when there is no ACK reply (ACK signal) from the payout control board 4110 at the time of sending the command to the first start opening switch 3022, the second starting opening switch 2109, the count switch 2110, etc. One of them is sent when a wire break or short circuit occurs, and the magnetic detection switch abnormality display command is sent when an abnormality of the magnetic detection switch 3024 is detected. Further, the door opening command is transmitted when the door opening is detected (when the door frame 5 is in the state of being opened with respect to the main body frame 3 based on the detection signal from the door frame opening switch 618), The closing command is transmitted when the door closing is detected (when the door frame 5 is closed with respect to the main body frame 3 based on the detection signal from the door frame opening switch 618). Note that these various commands are actually transmitted in the peripheral control board command transmission process of step S120 in the main control side timer interrupt process.

[15-2-8. Status display]
As shown in FIG. 46, the status display section is composed of commands named frame status 1 command, error cancel navigation command, and frame status 2 command. A status of “7*H” and a mode of “**H” (“H” represents a hexadecimal number) are assigned to these various commands (“*” is a specific hexadecimal number). It means that it is predetermined according to the specifications of the pachinko gaming machine 1).

The frame state 1 command, the error release navigation command, and the frame state 2 command are commands each having a storage capacity of 1 byte (8 bits) transmitted from the payout control board 4110, and a detailed description thereof will be given later. .. When the main control MPU 4100a of the main control board 4100 receives the frame state 1 command, the error release navigation command, and the frame state 2 command from the payout control board 4110, as shown in FIG. 46, “7*H” is set. The status is set as well as the received command is set as the mode as it is. That is, when the main control MPU 4100a receives the frame state 1 command, the error release navigation command, and the frame state 2 command from the payout control board 4110, it adds the additional information “7*H” to these received commands. Is shaped into a command having a storage capacity of 2 bytes (16 bits).

The trimmed frame status 1 command is sent when power is restored, when the frame status is changed, and when the error is cleared, the error clear navigation command is sent when the error is cleared, and the frame status 2 command is created when the power is restored. , And when the frame status changes. The shaped frame state 1 command, the error release navigation command, and the frame state 2 command are actually transmitted in the peripheral control board command transmission process of step S120 in the main control side timer interrupt process.

[15-2-9. Test related]
As shown in FIG. 46, the test-related section is made up of various commands named test. This test command is assigned a status of "8*H" and a mode of "**H"("H" represents a hexadecimal number) ("*" is a specific hexadecimal number. And is predetermined according to the specifications of the pachinko gaming machine 1).

The test command instructs various inspections of the peripheral control board 4140 (for example, the peripheral control section 4150, the liquid crystal and sound control section 4160, the motor drive board 4180, and the frame decoration drive amplifier board 194 shown in FIG. 17). It is to inspect various boards such as).

As the transmission timing of the test command, the RAM is transmitted when the main control board power is turned on, and is transmitted at times other than RAM clear. Specifically, when the pachinko gaming machine 1 is powered on, at the time of returning from a power failure or momentary power failure, and when the operation switch 860a of the payout control board 4110 is operated, a main control side power-on process described later. Is executed and the test command is transmitted in the peripheral control board command transmission process of step S120 in the main control side timer interrupt process.

[15-2-10. Other]
In the other categories, as shown in FIG. 46, starting mouth winning, variation shortening operation end designation, high probability end designation, special symbol 1 storage, special symbol 2 storage, normal symbol storage, special symbol 1 storage prefetch effect, special It is composed of a command called a symbol 2 memory prefetching effect and a main prize ball number information output. A status of "9*H" and a mode of "**H"("H" represents a hexadecimal number) are assigned to these various commands ("*" is a specific hexadecimal number). It means that it is predetermined according to the specifications of the pachinko gaming machine 1).

The start mouth winning command is for instructing the start of the start winning effect, and the start of the effect when the game ball enters the first starting opening 2101 based on the detection signal from the first starting opening switch 3022. , The start of the effect when a game ball enters the second starting opening 2102 based on the detection signal from the second starting opening switch 2109, and the fluctuation shortening operation end designating command is a fluctuation. It is for instructing the state transition from the shortened operating state to the fluctuation shortening non-operating state, and the high probability end designation command is for instructing the state transition from the high probability state to the low probability state, and the special symbol 1 storage command Is 0-4 special symbols 1 hold (the game ball enters the first starting port 2101 shown in FIG. 8 and is still used for the variable display of special symbols on the special symbol display 1185 on the function display board 1191. Not to convey the number of balls (the number of reserves), special symbol 2 storage command, special symbol 2 hold 0-4 (the game ball enters the second starting port 2102 shown in FIG. 8 and functions. The special symbol display 1186 below the display board 1191 conveys the number of balls that have not yet been used for the variable display of the special symbol (the number of reserves)), and the normal symbol storage command is 0-4 normal symbols 1 reserve ( A game ball passes through the gate portion 2150 shown in FIG. 8 and conveys the number of balls not yet used for the variable display of the ordinary symbol on the ordinary symbol display 1189 of the function display substrate 1191 (the number of reserves), Special symbol 1 storage prefetch effect command, before the special symbol 1 hold is used for the variable display of the special symbol on the special symbol display 1185 on the function display board 1191, the pre-reading is based on the special symbol 1 hold It is to instruct the pre-reading effect start to notify the advance notice of the display result by the symbol display device 1185, and the special symbol 2 storage pre-reading effect command is the special symbol 2 hold special symbol display device 1186 under the special symbol display device 1186. Before it is used for variable display, it pre-reads and instructs the pre-reading effect start to notify the advance notice of the display result by the lower special symbol display device 1186 based on the holding of the special symbol 2 and outputs the main prize ball number information. The command is paid as a prize ball based on the game balls that the main control board 4100 enters into various winning openings such as the first starting opening 2101, the second starting opening 2102, the general winning openings 2104 and 2201, and the big winning opening 2103. Every time the number of game balls to be issued reaches 10, the main prize ball number information output signal is output to the external terminal board 78 with that effect as the main prize ball number information. It is to instruct to transmit to the hall computer via 4.

As the transmission timing of these various commands, the starting opening winning command is a starting opening winning a prize (when a game ball enters the first starting opening 2101 based on a detection signal from the first starting opening switch 3022, or a second opening). When a game ball enters the second starting opening 2102 based on the detection signal from the starting opening switch 2109), a speaker housed in the speaker box 820 provided in the main body frame 3 shown in FIG. 5 and FIG. The variation reduction operation end designation command, which is transmitted mainly by voice from the speaker 130 provided in the door frame 5 shown in FIG. The high-probability end designation command is transmitted at the end of the suspension period (after the passage of the discontinuation stop period) after the fluctuation has been determined, which has exhausted the high-probability number in the case of "high probability N times". , Special symbol 1 storage command, when the number of special symbol 1 operation holding balls changes (the game ball enters the first starting port 2101 and the special symbol indicator 1185 on the function display substrate 1191 has not yet been displayed as a variable symbol of the special symbol. In the state where there is a number of reserves that are not used, when the game ball enters the first starting port 2101 and the number of reserves increases, or from the number of reserves to the variable display of the special symbol on the upper special symbol display 1185. When the number of holdings is reduced to be used), the special symbol 2 storage command is a special symbol 2 operation holding ball number change (a game ball enters the second starting port 2102 and the function display board 1191). In the state where there is a pending number that is not yet used in the variable display of the special symbol on the lower special symbol display device 1186, when the game ball enters the second starting opening 2102 and the pending number increases, or the pending number. From the lower special symbol display device 1186 is used for the variable display of the special symbol when the number of holding is reduced), the normal symbol memory command is a normal symbol 1 operation holding ball number change (gate unit 2150 game In the state where there is a number of holdings not yet used in the variable display of the normal symbol on the normal symbol display 1189 of the function display substrate 1191 after the ball passes, the game ball further passes through the gate portion 2150 and the number of holdings increases. At the time, or when the number of holding decreases when the number of holdings is reduced by using the normal symbol display 1189 for the variable display of the normal symbol, the special symbol 1 storage prefetch effect command is the special symbol 1 operation holding number of balls. At the time of increase (when the game ball enters the first starting port 2101 and the number of holdings increases), the special symbol 2 memory prefetching effect command is when the number of special symbols 2 operation holding balls increases (second starting port When the game ball enters 2102 and the number of holdings increases, the main prize ball number information output command is the first command based on the detection signal from the first start mouth switch 3022 when various prize holes are won. When the game ball enters the starting opening 2101, when the game ball enters the second starting opening 2102 based on the detection signal from the second starting opening switch 2109, the detection signal from the general winning opening switches 3020, 3020 When the game ball enters the general winning openings 2104 and 2201 based on the above, and when the game ball enters the special winning opening 2103 based on the detection signal from the count switch 2110, the game balls enter the various winning openings. When you enter the ball) will be sent. Note that these various commands are actually transmitted in the peripheral control board command transmission process of step S120 in the main control side timer interrupt process.

By the way, as described above, the starting opening winning command is, when the starting opening winning (when the game ball enters the first starting opening 2101 based on the detection signal from the first starting opening switch 3022, or the second starting opening). When a game ball enters the second starting opening 2102 based on a detection signal from the switch 2109), a speaker housed in a speaker box 820 provided in the main body frame 3 and a speaker 130 provided in the door frame 5 are mainly used. However, how the peripheral control board 4140 shown in FIG. 17 uses the starting mouth winning command may differ depending on the specifications of the pachinko gaming machine. For example, in the pachinko gaming machine 1 according to the present embodiment, in addition to the voice notification from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, the presence or absence of fraud is monitored. It is also designed to be used for On the other hand, in other pachinko game machines, the peripheral control board 4140 simply receives the start opening winning command, and the speaker accommodated in the speaker box 820 provided in the main body frame 3 and the speaker provided in the door frame 5 There is also a specification that does not notify by voice from 130.

[15-3. Various commands from the payout control board received by the main control board]
Next, various commands from the payout control board 4110 received by the main control board 4100 will be described.

As shown in FIG. 47, the classification of various commands from the payout control board 4110 is made up of commands named frame state 1, error release navigation and frame state 2, and frame state 1, error release navigation, and The priority order is set in the order of the frame state 2.

The frame status 1 command provides a ball out, full tank, over 50 stocks, abnormal connection, and no CR connection, and bit 0 (B0, "B" represents a bit) when the ball is out. Value 1 is set, value 1 is set to bit 1 (B1) when the tank is full, value 1 is set to bit 2 (B2) in 50 or more stocks, and value is set to bit 3 (B3) when the connection is abnormal. 1 is set, and the value 1 is set in bit 4 (B4) when CR is not connected. A value 1 is set in B5, a value 0 is set in B6, and a value 0 is set in B7 in bits 5 (B5) to 7 (B7) of the frame state 1 command.

The error clear navigation command has a ball gaze, a counting switch error, and a retry error. For a ball gaze, the bit 1 (B2) is set to the value 1, and for the counting switch error, the bit 3 (B3) is set to the value. 1 is set, and the bit 1 (B4) is set to the value 1 in the case of a retry error. Here, the "count switch error" indicates whether or not the malfunction of the count switch 751 shown in FIG. 15 has occurred. The "retry error" indicates that the payout of game balls that are not consistent due to the retry operation has been repeatedly performed. The bit (B0), the bit (B1), and the bit 5 (B5) to the bit 7 (B7) of the error canceling navigation command have a value 0 for B0, a value 0 for B1, a value 0 for B5, and a value 1 for B6. The value 0 is set in B7.

In the frame state 2 command, a launch ball sending control circuit error is prepared, and the value 1 is set to bit 0 (B0) in the launch ball sending control circuit error. In bit 1 (B1) to bit 7 (B7) of the frame state 2 command, B1 has a value of 0, B2 has a value of 0, B3 has a value of 0, B4 has a value of 0, B5 has a value of 1, B6 has a value of 1, and The value 0 is set in B7.

As the transmission timing of these various commands, the frame state 1 command is transmitted at the time of power restoration, when the frame state is changed, and at the time of error cancellation navigation, and the error cancellation navigation command is transmitted at the time of error cancellation navigation and the frame status 2 command. Is transmitted when the power is restored and when the frame status changes. Note that these various commands are actually transmitted in the command transmission process of step S558 in the payout control unit main process of the payout control unit power-on process described later.

[16. Various control processing of main control board]
Next, various control processes performed by the main control board 4100 shown in FIG. 14 according to the progress of the game of the pachinko gaming machine 1 will be described with reference to FIGS. 48 to 50. FIG. 48 is a flowchart showing an example of the main control side power-on process, FIG. 49 is a flowchart showing the continuation of the main control side power-on process, and FIG. 50 is an example of the main control side timer interrupt process. It is a flowchart showing. First, various random numbers used in game control will be described, and subsequently, the operation of the initial value updating type counter, the main control side power-on process, and the main control side timer interrupt process will be described.

[16-1. Various random numbers]
As various random numbers used for game control, a big hit determination random number used for determining whether or not to generate a big hit game state, and whether or not to generate a reach when the big hit game state is not generated Reach determination random number to be used for the determination, and the variable display pattern for use in determining the variable display pattern of the special symbol that is variably displayed on the upper special symbol display device 1185 and the lower special symbol display device 1186 shown in FIG. For random numbers, big hit symbol random numbers for use in determining big hit symbols derived and displayed on the upper special symbol display 1185 and the lower special symbol display 1186 when generating the big hit game state, and this big hit symbol random number Random number for initial value determination for the big hit symbol to be used for determining the initial value, to determine the small hit symbol that is derived and displayed on the upper special symbol display device 1185 and the lower special symbol display device 1186 when generating the small hit game state. Random numbers for small hit symbols to be used, random numbers for determining initial value for small hit symbols to be used for determining the initial value of the random numbers for small hit symbols, and the like are prepared. In addition to these random numbers, a random number for determining a normal symbol to be used for determining whether to open/close the movable piece 2106 shown in FIG. 8 and an initial value for the random number for determining a normal symbol are determined. Ordinary symbol per use determination initial value determination random number for use, and normal symbol variation display pattern random number for use in determining the variation display pattern of the ordinary symbol that is variably displayed on the ordinary symbol display device 1189 shown in FIG. Is prepared.

Among various random numbers used for such game control, the big hit determination random number is updated by hardware, whereas other various random numbers are updated by software.

For example, the big hit determination random number is directly updated by hardware by the main control built-in hard random number circuit 4100an built in the main control MPU 4100a shown in FIG. As described above, when the main control MPU 4100a is reset, the main control built-in hard random number circuit 4100an first sets the clock signal input to the main control MPU 4100a as one value within a predetermined numerical range as an initial value. Based on (the clock signal output from the main control crystal oscillator MX0 shown in FIG. 24), other values within a predetermined numerical range are extracted at high speed one after another, and all the values within the predetermined numerical range are extracted. When the extraction is completed, one value within the predetermined numerical range is extracted again, and other values within the predetermined numerical range are extracted one after another at high speed based on the clock signal input to the main control MPU 4100a. To do. The main control built-in hard random number circuit 4100an repeatedly performs such a high-speed lottery, and the main control MPU 4100a makes a big hit with the value extracted by the main control built-in hard random number circuit 4100an at the time of obtaining the value from the main control built-in hard random number circuit 4100an. It is set as a random number for judgment.

On the other hand, the counter for updating the random number for normal symbol determination is updated within a predetermined fixed numerical value range from the minimum value to the maximum value, and the range from the minimum value to the maximum value will be described later. Each time the main control side timer interrupt processing is performed, the value is incremented by one and the count is incremented. This counter normally counts up from the random number for initial value determination for symbol hit determination toward the maximum value, and then counts from the minimum value to random numbers for initial value determination for normal symbol hit determination. When the counter finishes counting up the range from the minimum value to the maximum value of the normal symbol hit determination random number, the normal symbol hit determination initial value determination random number is updated. Such a counter updating method is called an “initial value updating type counter”. The random number for determining the initial value for normal symbol hit determination can be obtained by executing an initial value lottery process for randomly selecting a value from the fixed numerical range of the counter that updates the random number for symbol hit determination. ..

In the present embodiment, when the operation switch 860a of the payout control board 4110 shown in FIG. 15 is operated when the power is turned on, or in the main control side power-on process, which will be described later, of the main control MPU 4100a shown in FIG. The checksum value (sum value) obtained by regarding the various information stored in the main control built-in RAM as numerical values and calculating the sum is stored in the main control side power cutoff process (power cutoff). When clearing the entire area of the main control built-in RAM, such as when the checksum value (sum value) does not match, the random number for determining the initial value for the normal symbol is usually the main control MPU4100a shown in FIG. Takes out the ID code from the built-in non-volatile RAM, and usually derives the same fixed value from the fixed numerical value range of the counter that updates the random number for symbol determination based on the taken-out ID code. It is executed and the derived fixed value is set. That is, as for the random number for determining the initial value for determining the normal symbol, the same fixed value derived based on the ID code by the execution of the initial value deriving process is always overwritten and updated. As described above, the value set in the random number for determining the initial value for the normal symbol determination is derived using the ID code, and the nonvolatile RAM built in the main control MPU 4100a by the manufacturer of the main control MPU 4100a. The first security measure that the ID code is not rewritten even if an external device is used when the ID code is stored in the ID code, and the ID code is executed by executing the initial value derivation process when clearing the entire area of the main control internal RAM. The second security measure of deriving the same fixed value on the basis of the above and the two-step security measure of are prevented from being analyzed.

Here, an advantage will be described in which the ID code is taken out from the nonvolatile RAM built in the main control MPU 4100a, and the taken ID code is used as the random number for determining the initial value for normal symbol determination. For example, a person who attempts to illegally obtain a game ball to be paid out as a prize ball obtains the game board 4 by some method and disassembles it. Even if it is possible to grasp the timing at which the value of the counter for updating the random number for normal symbol hit determination and the normal symbol hit determination value are obtained illegally, its ID code is unique for identifying an individual. Since they are provided with reference numerals, they are completely different from the ID code stored in advance in the non-volatile RAM incorporated in the main control MPU 4100a' provided in the other game board 4'. In other words, in the other game board 4', the timing at which the value of the counter for updating the normal symbol hit determination random number and the normal symbol hit determination value match is completely different from that of the game board 4 obtained. In other words, the ID code obtained by disassembling and analyzing the obtained game board 4 is completely useless in the other game board 4′, that is, the other pachinko machine 1′, and therefore is disassembled and analyzed. Even if a momentary blackout is generated at each of the obtained predetermined intervals and the game ball is passed through the gate portion 2150 shown in FIG. 8 at each of the predetermined intervals, the movable piece 2106 shown in FIG. 8 is opened and closed. It is not possible to generate a game state in which a game ball can be received in the second starting opening 2102.

[16-2. Main control side power-on processing]
First, when the pachinko game machine 1 is powered on, the main control MPU 4100a is configured so that the stack pointer is set to a predetermined address as a default. This stack pointer indicates, for example, the address stacked on the stack to temporarily store the contents of the storage element (register) in use, or the return address of this routine when returning from this routine after ending the subroutine. It also indicates the address stacked on the stack for temporary storage, and the stack pointer advances each time the stack is stacked.

Then, the main control program described above performs the main control side power-on process as shown in FIGS. 48 and 49 under the control of the main control MPU 4100a of the main control board 4100. When the main control side power-on process is started, the main control program sets the RAM access permission under the control of the main control MPU 4100a (step S10). By setting the RAM access permission, the main control built-in RAM (game storage section) can be updated.

Subsequent to step S10, the main control program performs initial value setting and startup setting of the main control built-in WDT 4100af shown in FIG. 14 (step S12). Here, in order to set an initial value in the main control built-in WDT 4100af that monitors whether or not the operation (system) of the main control MPU 4100a is operating normally, a watchdog timer control register (hereinafter referred to as " WDT control register”) to set a timer setting value to activate the main control built-in WDT 4100af and reset the main control MPU 4100a. When the main control built-in WDT 4100af is activated, the main control built-in WDT 4100af starts timing, and by the time the counted time reaches the time set by the timer set value, the watchdog timer clear register ( Hereinafter, when the timer clear set value is not set in the "WDT clear register"), the main control built-in WDT 4100af forcibly resets the main control MPU 4100a. On the other hand, when the main control built-in WDT 4100af is activated and time measurement is started, if the timer clear set value is set in the WDT clear register before the time measured reaches the time set by the timer set value, The timing by the main control built-in WDT 4100af is cleared and the timing is restarted. In this way, the operation (system) of the main control MPU4100a operates normally by repeating the process of clearing the time measurement by the main control built-in WDT4100af until the time set by the timer setting value is reached and restarting the time measurement again. Can be monitored.

Following step S12, the main control program performs a power outage clear process (step S14). In the electric power clear processing, first, the output of the power failure clear signal to the power failure monitoring circuit 4100e shown in FIG. 25 is started. The power failure monitoring circuit 4100e includes a comparator MIC21 which is a voltage comparison circuit and a D-type flip-flop MIC22. The comparator MIC21, which is a voltage comparison circuit, outputs the comparison result by comparing the voltage between +24V and the reference voltage or by comparing the voltage between +12V and the reference voltage. This comparison result shows that when no power failure or momentary power failure has occurred, its logic becomes HI and is input to the PR terminal, which is the preset terminal of the D type flip-flop MIC22, while when a power failure or momentary power failure occurs. The logic becomes LOW and is input to the PR terminal which is the preset terminal of the D type flip-flop MIC22.

In the electric power clear processing, first, the output of the power failure clear signal to the power failure monitoring circuit 4100e is started, thereby starting the output of the power failure clear signal to the CLR terminal which is the clear terminal of the D type flip-flop MIC22. This power failure clear signal is input to the CLR terminal, which is the clear terminal of the D type flip-flop IC, from the output terminal of the predetermined output port of the main control MPU 4100a, by setting its logic to LOW, through the main control output circuit 4100ca with a reset function. To be done. As a result, the main control MPU 4100a can release the latched state of the D type flip-flop MIC22, and until the latched state is set, the logic input to the PR terminal which is the preset terminal of the D type flip-flop MIC22 can be applied. The signal can be inverted and output from the 1Q terminal which is the output terminal, and the signal from the 1Q terminal can be monitored.

Subsequently, in the electric power clearing process, a wait timer process is performed to determine whether or not the power failure advance notice signal is input. The voltage does not rise immediately after the power is turned on until it reaches the specified voltage. On the other hand, when there is a power failure or an instantaneous power failure (a phenomenon in which the power supply is temporarily stopped), the voltage drops, and when the voltage becomes lower than the power failure warning voltage, the power failure warning circuit 4100e inputs a power failure warning signal as a power failure warning. Similarly, when the voltage becomes lower than the power failure warning voltage from the time when the power is turned on to the predetermined voltage, the power failure monitoring circuit 4100e inputs the power failure warning signal. Therefore, the wait timer process is a process for waiting until the voltage becomes larger than the power failure warning voltage and becomes stable after the power is turned on. In the present embodiment, the waiting time (wait timer) is set to 200 milliseconds (ms). Has been done. Whether or not the power failure notice signal is input is determined based on the signal output from the 1Q terminal, which is the output terminal of the D type flip-flop MIC22, as the power failure notice signal.

If the power failure warning signal is not input even after waiting until the voltage becomes higher than the power failure warning voltage and becomes stable after the power is turned on, the main control program outputs the power failure clear signal to the CLR terminal which is the clear terminal of the D type flip-flop MIC22. Stop output. Here, the power failure clear signal is a clear terminal of the D-type flip-flop IC, which is a clear terminal of the D-type flip-flop IC, via the main control output circuit 4100ca with a reset function by setting the logic of the output terminal of the predetermined output port of the main control MPU 4100a to HI. To be entered. As a result, the main control MPU 4100a can set the D type flip-flop MIC22 in the latched state. The D type flip-flop MIC22 outputs a power failure notice signal from the output terminal 1Q terminal when the state in which the logic is LOW is input to the PR terminal which is the preset terminal thereof is latched.

Subsequent to step S14, the main control program sets a state in which a RAM clear process for initializing the main control internal RAM (game storage unit) can be executed for a predetermined time after the power is turned on. Specifically, the main control program first determines whether or not the operation switch 860a of the payout control board 4110 shown in FIG. 15 is operated (step S16). In this determination, the main control program determines whether or not an error cancellation navigation command based on an operation signal (detection signal) associated with the operation of the operation switch 860a of the payout control board 4110 is input to the main control MPU 4100a. Based on the logical value of the operation signal, the main control program determines that it does not instruct to perform the RAM clear when the logical value of the operation signal from the operation switch 860a is HI, and the operation switch 860a is operated. On the other hand, when the logical value of the operation signal from the operation switch 860a is LOW, it is determined that the RAM clear is instructed and it is determined that the operation switch 860a is operated.

In step S16, the main control program sets the RAM clear notification flag RCL-FLG to the value 1 when the operation switch 860a is operated (step S18). On the other hand, the main control program sets the value 0 to the RAM clear notification flag RCL-FLG when the operation switch 860a is not operated in step S16 (step S20). That is, the main control program can execute a RAM clear process for initializing the RAM built in the main control MPU 4100a (that is, the main control built-in RAM (game storage unit)) for a predetermined time after the power is turned on. State. The RAM clear notification flag RCL-FLG described above is stored in the main control built-in RAM (game storage unit) of the main control MPU 4100a, game information related to games such as probability fluctuations, unpaid prize balls, and other information (for example, , A flag indicating whether or not to erase various information including a value of a counter for determining the main prize ball number information output). Is set to each. The value of the RAM clear notification flag RCL-FLG set in step S18 and step S20 is stored in the general-purpose storage element (general-purpose register) of the main control MPU 4100a.

Subsequent to step S18 or step S20, the main control program performs wait time standby processing (step S22). In the wait time standby process, the system waits until the system for performing the drawing control of the game board side effect display unit 1900 by the liquid crystal and sound control unit 4160 in the peripheral control board 4140 shown in FIG. 17 is activated (booted). In this embodiment, 2.5 seconds (s) is set as the standby time (boot timer) until booting.

Subsequent to step S22, the main control program determines whether or not a power failure advance notice signal is input (step S24). As described above, when the power of the pachinko gaming machine 1 is shut off, or a power failure or momentary power failure occurs, when the voltage becomes equal to or lower than the power failure notification voltage, the power failure notification signal is input from the power failure monitoring circuit 4100e as a power failure notification. The determination in step S24 is made based on this power failure notice signal. When the power failure notification signal is input in the determination in step S24, the main control program returns to the determination in step S24 again, and repeats the determination in step S24 as long as the power failure notification signal is continuously input. As a result, the timer clear set value is set in the WDT clear register built in the main control MPU 4100a for the main control built-in WDT 4100af started in step S12, and the time count by the main control built-in WDT 4100af is cleared and the time measurement is restarted. As a result, the main control built-in WDT 4100af forcibly resets the main control MPU 4100a. After that, the main control program performs this main control side power-on process again under the control of the main control MPU 4100a of the main control board 4100. A detailed description will be given later of the point that the determination in step S24 is performed after the wait time waiting process in step S22.

When the power failure notice signal is not input in the determination of step S24, the main control program determines whether or not the RAM clear notification flag RCL-FLG is 0 (step S26). As described above, the RAM clear notification flag RCL-FLG is set to a value of 1 when erasing various information and a value of 0 when not erasing various information. When the RAM clear notification flag RCL-FLG has a value of 0 in step S26, that is, when various information is not erased, a checksum is calculated (step S28). This checksum regards various information stored in the main control built-in RAM as numerical values and calculates the sum thereof.

Subsequent to step S28, the main control program determines that the calculated checksum value (sum value) is the checksum value (sum value) stored in the main control-side power-off processing (power-off) described later. It is determined whether they match (step S30). When they match, the main control program determines whether the backup flag BK-FLG has a value of 1 (step S32). This backup flag BK-FLG stores various information, a checksum value (sum value), and game backup information such as the value of the backup flag BK-FLG in the main control built-in RAM in the main control side power-off processing to be described later. It is a flag indicating whether or not it has been done, and is set to a value 1 when the main control side power-off process is normally completed, and a value 0 when the main control side power-off process is not normally completed. In the inspection process of the manufacturing line of the main control board 4100, when the main control board 4100 is first powered on after being manufactured for inspection, calculation of the checksum in step S28 and determination in step S30 are performed. , Will be described later in detail.

When the backup flag BK-FLG has a value of 1 in step S32, that is, when the main-control-side power-off process is normally completed, the main control program sets the work area of the main control internal RAM as the power recovery time ( Step S34). In this setting, the power recovery information is read from the ROM (that is, the main control built-in ROM) built in the main control MPU 4100a, and the power recovery information is set in the work area of the main control built-in RAM. As a result, various information is read from the game backup information and various commands corresponding to the various information are stored in a predetermined storage area of the main control built-in RAM. Note that "power recovery" refers to the state in which the power is turned on after being turned off, the state in which power is restored after a power failure or momentary power failure, and fraudulent means (for example, fraudulent person A state in which the main control board 4100 is irradiated with a high frequency from a hidden high frequency output device) to reset the main control MPU 4100a itself and then returned is also included.

Following step S34, the main control program sets the backup flag BK-FLG to the value 0 (step S36). As a result, various information, checksum value (sum value), etc. are changed by performing various processes thereafter, so that the main control side power-off process, which will be described later, is normally terminated and the backup flag BK- If the value 1 is not set in FLG, the entire area of the main control internal RAM is cleared, as will be described later.

On the other hand, when the RAM clear notification flag RCL-FLG is not 0 (value 1) in step S26, that is, when various information is erased, or when the checksum value (sum value) does not match in step S30. , Or when the backup flag BK-FLG is not value 1 (value 0) in step S32, that is, when the power-off process on the main control side is not normally terminated, the main control program executes all the data in the main control internal RAM. The area is cleared (step S38). That is, the main control program executes the game control side RAM clear processing triggered by the input of the detection signal accompanying the operation of the operation switch 860a described above. Specifically, the main control program is executed by writing the value 0 into the main control built-in RAM. Alternatively, the main control program may read and set a predetermined value as an initial value from the ROM with built-in main control. In addition, the main control MPU 4100a performs the processing when the logical value of the operation signal from the operation switch 860a indicates RAM clear and erases various information, when the sum values do not match, or when the main control side power is turned off. When not normally completed, the unique ID code stored in advance in the non-volatile RAM of the main control MPU4100a is taken out, and the fixed numerical value range of the counter for updating the normal symbol per determination judgment random number based on the taken out ID code. Always perform the initial value derivation process that derives the same fixed value from, and set this fixed value to the random number for determining the initial value for the normal symbol per determination, which is used to determine the initial value of the above random number for the ordinary symbol. To do.

Following step S38, the main control program sets the work area of the main control internal RAM as an initial setting (step S40). This setting is performed by reading the initial information from the ROM with built-in main control and setting this initial information in the work area of the RAM with built-in main control. As a result, the game backup information is initialized, and for example, the value of the main prize ball number information output determination counter is set (set) to the initial value 0 (zero).

Following step S36 or step S40, the main control program performs interrupt initialization (step S42). This setting sets the interrupt cycle when the main control side timer interrupt process described later is performed. In this embodiment, it is set to 4 milliseconds (ms).

Subsequent to step S42, the main control program performs serial communication initialization (step S44). Here, various serial input/output ports built into the main control MPU 4100a (for example, serial input/output ports (reception channel and transmission channel) for the payout control board 4110, serial input/output ports (reception channel and transmission channel for the peripheral control board 4140). ), the communication serial speed prescaler and the presence/absence of parity are set, and the transmission serial port control register is set to initialize the transmission circuit and set transmission permission.

Subsequent to step S44, the main control program performs test signal output port initialization setting (step S46). Here, in a gaming machine testing facility, a test signal output port (not shown) for outputting various inspection information is initialized (set to OFF data output) when the power is turned on.

Subsequent to step S46, the main control program sets the activation of the main control built-in hard random number circuit 4100an shown in FIG. 14 (step S48). Here, of the various random numbers related to the game, a big hit determination random number used for determining whether or not to generate the big hit game state, a hard random number control register built in the main control MPU 4100a for updating by hardware. In addition to performing settings such as latching and obtaining a random number, the startup of the main control built-in hard random number circuit 4100an is set in the hard random number setting register. When the main control built-in hard random number circuit 4100an is activated by these settings, it is predetermined at a high speed based on the clock signal input to the main control MPU 4100a (clock signal output from the main control crystal oscillator MX0 shown in FIG. 24). Extract other values in the numerical range one after another without duplication, and once all the values within the predetermined numerical range have been extracted, again extract one value within the predetermined numerical range, Based on the clock signal input to the main control MPU 4100a, other values within a predetermined numerical range are extracted at high speed one after another without duplication. The main control MPU 4100a outputs a latch signal to the main control built-in hard random number circuit 4100an when acquiring a random number (random number value) from the main control built-in hard random number circuit 4100an, and the main control when the latch signal is input. The random number (random number value) extracted by the built-in hard random number circuit 4100an is acquired from the hard random number latch register built in the main control built-in main control MPU 4100a. The main control MPU 4100a sets the acquired random number value as a big hit determination random number.

Subsequent to step S48, the main control program sets the reservation of the command to be transmitted when the power is turned on (step S50). Here, in order to notify that the power is turned on (power recovery) based on the power recovery information set in the work area of the main control built-in RAM in the setting of the work area of the main control built-in RAM in step S34, FIG. Create a power-on status command, a power-on main control return destination command, and a power-on main award ball number information output determination counter notification command that are classified into the power-on shown in the above, and send it as transmission information. Stored in the transmission information storage area. In the transmission information storage area of the main control built-in RAM, in the setting of the work area of the main control built-in RAM in step S34, various information may be read from the game backup information and various commands corresponding to the various information may be stored. is there. In such a case, first after completion of transmission of various commands according to game information among various information, then power-on state command, power-on main control return destination command, and power-on main prize ball number information The output determination counter notification command will be transmitted. These commands are transmitted in the main control side timer interrupt process described later. It should be noted that a detailed description will be given later of the fact that the reservation setting of the command to be transmitted when the power is turned on is performed in step S50.

Subsequent to step S50, the main control program sets an interrupt permission (step S52). With this setting, the main control side timer interrupt process described later is repeatedly performed at the interrupt cycle set at step S42, that is, every 4 ms.

Subsequent to step S52, when a predetermined time has passed since the power was turned on, that is, when the main processing on the main control side is started, the main control program outputs an error release navigation command associated with the operation of the operation switch 860a (operation switch). Execution of the game control side RAM clear processing triggered by the reception will be restricted. As described above, the main control program uses the concept of time sharing to detect the detection signal input in accordance with the operation of the operation switch 860a, as described above, from the time of power-on to a predetermined time from the time when the power is turned on to the error cancellation navigation command. To execute the RAM clear process triggered by the input, or to control the execution of the RAM clear process even if the error clear navigation command is input after the predetermined time has elapsed, and cancel the error notification associated with the error that has occurred. It is used as a release switch. That is, the operation switch 860a (error canceling unit), which was originally supposed to be used for canceling the error that occurred with respect to the payout operation, is used as the game storage unit instead of the power-on for a predetermined time. Of the main control built-in RAM (and a payout control built-in RAM as a payout storage unit described later) is caused to function as an operation unit for executing a RAM clear process for starting initialization, or after a predetermined time has elapsed, a game is played. It can be made to function as an operation unit for canceling an error that has occurred in the ball payout operation.

Next, the main control program determines whether or not the power failure notice signal is input (step S54). As described above, when the power of the pachinko gaming machine 1 is shut off, or a power failure or momentary power failure occurs, when the voltage becomes equal to or lower than the power failure notification voltage, the power failure notification signal is input from the power failure monitoring circuit 4100e as a power failure notification. The determination in step S54 is made based on this power failure notice signal.

When no power failure notice signal is input in step S54, the main control program performs a non-winning random number updating process (step S56). In the non-win/win random number updating process, the reach determination random number, the variable display pattern random number, the big hit symbol initial value determining random number, the small hit symbol initial value determining random number, and the like are updated. As described above, in the non-winning random number updating process, the random numbers that are not involved in the winning/judging determination (big hit determination) are updated by software. The random number for normal symbol hit determination, the random number for initial value determination for normal symbol hit determination, the random number for normal symbol variation display pattern, and the like described above are also updated by this non-win/win random number updating process.

Subsequent to step S56, the process returns to step S54 again, and the main control program determines whether or not the power outage notice signal is input. Then, step S54 to step S56 are repeated. The processing of steps S54 to S56 is referred to as "main control side main processing".

On the other hand, when the power failure notice signal is input in step S54, the main control program sets the interrupt prohibition (step S58). By this setting, the main control side timer interrupt process described later is not performed, writing to the main control internal RAM is prevented, and rewriting of various information including the game information and other information described above is protected.

Following step S58, the main control program starts outputting the power failure clear signal (step S60). Here, the same processing as the processing that started the output of the power failure clear signal in the power failure clearing processing in step S14 is performed. Thereby, the main control program can release the latched state of the D type flip-flop MIC22 under the control of the main control MPU 4100a.

Subsequent to step S60, the main control program is the starting port solenoid 2105, attacker solenoid 2108, upper special symbol display 1185, lower special symbol display 1186, upper special symbol storage display 1184, and lower special shown in FIG. The drive signal output to the symbol storage display 1187, the normal symbol display 1189, the normal symbol storage display 1188, the game state display 1183, the round display 1190, etc. is stopped (step S62).

Subsequent to step S62, the main control program calculates the checksum and stores the calculated value (step S64). This checksum regards the game information in the work area of the main control internal RAM as a numerical value, excluding the storage area of the above-mentioned checksum value (sum value) and the value of the backup flag BK-FLG, and calculates the total thereof.

Following step S64, the main control program sets the backup flag BK-FLG to the value 1 (step S66). This completes the storage of the game backup information.

Subsequent to step S66, the main control program sets the RAM access prohibition (step S68). This RAM access prohibition setting prevents access to the main control built-in RAM (game storage section), so that the contents of the main control built-in RAM (game storage section) can be prevented from being updated.

Following step S68, an infinite loop is entered. In this infinite loop, the timer clear set value is set in the WDT clear register built in the main control MPU4100a for the main control built-in WDT4100af started in step S12, the time count by the main control built-in WDT4100af is cleared, and the time measurement is restarted. As a result, the main control MPU 4100a is forcibly reset by the main control built-in WDT 4100af. After that, the main control program performs this main control side power-on process again under the control of the main control MPU 4100a of the main control board 4100. The process of steps S58 to S68 and the infinite loop are referred to as "main control side power-off process".

The pachinko gaming machine 1 (main control MPU 4100a) is reset when a power failure or momentary power failure occurs, and the main control side power-on process is performed by subsequent power recovery.

In step S30, it is checked whether or not the game backup information stored in the main control built-in RAM is normal, and in step S32, whether or not the main control side power-off processing is normally ended. Are inspecting. In this way, by double checking the game backup information stored in the main control built-in RAM, it is inspected whether or not the game backup information is stored by fraud.

Here, description will be made on the point that the presence/absence of a power failure advance notice signal in step S24 is determined following the wait time standby process in step S22. First, regarding the problem in the case where the presence or absence of the power failure warning signal is not determined in step S24, that is, when the wait time standby process in step S22 is determined and the value of the RAM clear flag is determined in step S26, and the subsequent process is performed. Described below are the problems.

As described above, the VDD terminal which is the power supply terminal of the main control MPU 4100a is charged in the electrolytic capacitor MC2 shown in FIG. 24 when the power supply from the pachinko island facility is cut off due to the power failure or the instantaneous power failure. The electric charge is applied as +5 V for a period of about 7 milliseconds (ms) after a power failure or an instantaneous blackout occurs. In other words, even if the power from the pachinko island equipment is cut off due to a momentary power failure or power failure, the electric charge charged to the hardware of the electrolytic capacitor MC2 as +5 V causes the power from the pachinko island equipment to be applied. The main control-side power-off processing can be completed within a period of about 7 ms after the power is cut off. This is because when a player is playing a game, that is, while performing main control side main processing or main control side timer interrupt processing, which will be described later, a power outage or momentary power outage occurs from pachinko island equipment. When the power is shut off, the main control side power shutoff process can be reliably completed.

However, as an extremely rare phenomenon, the drawing control of the game board side effect display unit 1900 by the liquid crystal and sound control unit 4160 in the peripheral control board 4140 shown in FIG. 17 is performed in the wait time standby process of step S22 when power is restored. A standby time (boot timer: 2.5 seconds is set in the present embodiment) until the system is activated (booted) is started, and immediately before the standby time is reached, an instantaneous power failure or a power failure occurs. Occurs, the charge charged in the hardware of the electrolytic capacitor MC2 is applied as +5 V to the VDD terminal which is the power supply terminal of the main control MPU4100a, but the interrupt initialization is performed in step S42 within a period of about 7 ms. Then, after that, the interrupt permission setting is performed in step S52, so that the main control side timer interrupt process, which will be described later, is performed and the main control side power-on process is performed even if the contents of the main control internal RAM are updated. It may not be possible to complete the processing when the side power is turned off. For this reason, the value when the checksum is calculated based on the content of the RAM with built-in main control is not stored, and the power-on process on the main control side is started again when power is restored.

Then, at the time of power recovery this time, the main control side power-on process is started, the wait time standby process of step S22 is completed without the occurrence of an instantaneous power failure or a power failure, and then, in step S28, the main control built-in RAM If the value calculated as the checksum based on the contents of the above is compared with the value stored in the main control built-in RAM immediately before the momentary power failure or the power failure occurs in step S30, the checksum value should match. Instead, the entire area of the main control built-in RAM is cleared in step S38. In other words, when the power is restored, the operation switch 860a is operated by the hall clerk or the like, and the above-mentioned game backup information is forcibly stored in the main control built-in RAM even if there is no intention of the hall clerk to clear the RAM. There is a problem that will be erased (cleared).

In view of this, in the present embodiment, immediately after the wait time standby process of step S22, a process for determining whether or not the power failure notice signal is input is provided as step 24, and when the power cut notice signal is input, Returning to the determination of step S24 again, the determination of step S24 is repeated as long as the power failure advance notice signal continues to be input. As a result, the timer clear set value is set in the WDT clear register built in the main control MPU 4100a for the main control built-in WDT 4100af started in step S12, and the time count by the main control built-in WDT 4100af is cleared and the time measurement is restarted. As a result, the main control MPU 4100a can be forcibly reset by the main control built-in WDT 4100af. Although the RAM clear notification flag RCL-FLG is set to a value in step S18 or step S20 before the wait time waiting process of step S22 is performed, the value of the RAM clear notification flag RCL-FLG is set to the main value as described above. Since it is stored in the general-purpose storage element (general-purpose register) of the control MPU 4100a, even if the RAM access permission is set in step S10, the content of the main control built-in RAM (game information) is not changed at all.

As described above, immediately after the wait time waiting process in step S22, a process for determining whether or not the power failure notice signal is input is provided as step 24, and when the power failure notice signal is input (that is, the step When the power supply to the pachinko gaming machine 1 is cut off after waiting in the wait time waiting process in S22 (when it is determined in the determination in step S24), the process returns to the determination in step S24 again, and as long as the power failure notice signal is continuously input. By repeating the determination in step S24, the main control MPU 4100a of the main control board 4100 can be forcibly reset and the main control board 4100 can be restarted, so that the game progresses. It is possible to prevent various information including game information and other information (for example, information indicating the value of the main prize ball number information output determination counter) from being updated, and the checksum is calculated. There is no fluctuation in the result. Accordingly, the main control MPU 4100a of the main control board 4100, when restarted, determines that the checksum calculation result of step S28 and the checksum calculation and storage value of step S64 match. Therefore, the game information immediately before a momentary power failure or a power failure that is stored and retained in the main control built-in RAM is not initialized. Therefore, at the time of power recovery, it is possible to prevent the game information immediately before the occurrence of a momentary power failure or a power failure from being initialized.

Immediately after the wait time standby process of step S22, a process of determining whether or not the power failure notice signal is input is provided as step 24, and when the power failure notice signal is not input (that is, in step S22). When it is determined in step S24 that the power to the pachinko gaming machine 1 is not shut off after waiting in the wait time standby process), the main control MPU 4100a of the main control board 4100 is in progress of the game. Even if the power supply to the gaming machine 1 is cut off, by supplying power to the VDD terminal, which is the power supply terminal of the main control MPU 4100a, by the electrolytic capacitor MC2 shown in FIG. 24, game information based on the progress of this game, and other information Main control side power supply configured by the processing of steps S58 to S68, which is a backup processing for storing various information including (for example, information indicating the value of the counter for determining the number of main prize ball information output determination), and an infinite loop Since the main control MPU 4100a of the main control board 4100 can complete the disconnection process, the main control MPU 4100a of the main control MPU 4100a, when restarted, calculates the checksum in step S28 and In the backup process, it is determined that the checksum calculation result (that is, the checksum calculated and stored in step S64) matches, so that the momentary power failure or power failure that is stored and retained in the main control internal RAM. There is no need to initialize the game information immediately before the occurrence of. That is, the main control board 4100 can be activated by being restored to the game information immediately before the momentary power failure or the power failure.

Immediately after the wait time waiting process in step S22, when it is determined in step S24 that the power failure advance notice signal is input, the main control built-in WDT 4100af forcibly resets the main control MPU 4100a to reset the contents of the main control built-in RAM. While the main control-side power-off processing can be started again without updating at all, while immediately after the wait time standby processing in step S22, when it is determined in step S24 that the power failure advance notice signal has not been input, As described above, it is possible to surely complete the main control side power-off processing within the "instantaneous power failure or power failure power supply securing period" of about 7 ms by hardware. That is, in the present embodiment, when the power supply from the pachinko island equipment is cut off due to an instantaneous power failure or a power failure during the power-on process at the time of main control side power recovery, the main control MPU 4100a The electric charge charged in the electrolytic capacitor MC2 shown in FIG. 24 is applied to the VDD terminal which is the power supply terminal as +5 V for a period of about 7 milliseconds (ms) after the occurrence of the power failure or the instantaneous blackout. Therefore, if the main control side power-off process cannot be completed within the “instantaneous power interruption or power supply securing period” of about 7 ms by the hardware of the electrolytic capacitor MC2, the wait time waiting process of step S22 is performed. Immediately after that, in step 24, it is determined whether or not the power outage notice signal is input. When the power outage notice signal is input, the process returns to the determination in step S24 again, and as long as the power outage notice signal continues to be input, step S24 By repeating the above determination, the timer clear set value is set in the WDT clear register built in the main control MPU4100a for the main control built-in WDT4100af activated in step S12, and the time count by the main control built-in WDT4100af is cleared and then again. Since it becomes impossible to start timing, the main control MPU 4100a can be forcibly reset by the main control built-in WDT 4100af. Since the main control MPU 4100a is forcibly reset by the main control built-in WDT 4100af by such software, a step after step S24 (specifically, interrupt initialization is performed in step S42, and then in step S52). The contents of the main control built-in RAM (game information and other information (for example, the number of main prize balls) are set by blocking the progress of the control flow of starting the timer interrupt processing on the main control side described later by setting the interrupt permission. It is possible to avoid updating various information) including information indicating the value of the information output determination counter). When the power from the pachinko island equipment is cut off due to such a power failure or momentary power failure, the contents of the main control internal RAM (game information and other information (for example, the main prize ball number information output determination counter) Various information including the value indicating the value of) is covered by software so that it is not changed at all, and the contents of main control internal RAM (game information and other The information (for example, various information including the information indicating the value of the main prize ball number information output determination counter) is partly provided by hardware so that it is not changed at all. It is possible to reliably prevent the contents of the control built-in RAM (various information including game information and other information (for example, information indicating the value of the main prize ball number information output determination counter)) from being changed. It is like this.

Next, description will be made on the point that the reservation of the command to be transmitted when the power is turned on is set in step S50. In step S50, as described above, based on the power recovery information set in the work area of the main control internal RAM in the setting of the work area of the main control internal RAM in step S34, the fact that the power is turned on (power recovery) is performed. In order to convey, a power-on state command classified into power-on shown in FIG. 45, a power-on main control return destination command, and a power-on main prize number information output determination counter notification command are created and transmitted. Information is stored in the transmission information storage area of the main control built-in RAM. As described above, the power-on main control return destination command is mainly composed of information indicating the driving state of the starting opening solenoid 2105 and information indicating the driving state of the attacker solenoid 2108 shown in FIG. There is. Here, first, when the power-on main control return destination command does not include the information indicating the driving state of the starting opening solenoid 2105 and the information indicating the driving state of the attacker solenoid 2108 shown in FIG. The problem in step S50, that is, the problem when the reservation of the command to be transmitted when the power-on main control return destination command is turned on at step S50 is not set will be described.

For example, while the peripheral control board 4140 is controlling the display of the big hit game state screen (for example, the big hit game effect screen) in the display area of the game board side effect display unit 1900 shown in FIG. 8, the main control board 4100. When the attacker solenoid 2108 is driven and the special winning opening 2103 shown in FIG. 8 is opened by the opening/closing member 2107, a momentary power failure or a power failure occurs, and then the power is restored, the main control board 4100 executes the steps. Based on the power recovery information set in the work area of the main control built-in RAM in the setting of the work area of the main control built-in RAM in S34, the attacker is restored to the game state immediately before the momentary power failure or power failure occurs. The driving of the solenoid 2108 is started, and the state where the special winning opening 2103 is closed by the opening/closing member 2107 is changed to the opened state.

However, when a momentary power failure or a power failure occurs, the peripheral control board 4140 receives various commands from the main control board 4100 and returns when the power is restored. Then, when power is restored after that, the peripheral control board 4140 can return based on the probability and the shortened state indicated by the power-on state command received from the main control board 4100 at the time of power restoration. However, when the main control board 4100 is generating a big hit game state as a game state, if a momentary power failure or a power failure occurs, and then power is restored, the peripheral control board 4140 will cause the main control board 4100 to restore power. Based on the probability and the time saving state indicated by the power-on state command received from, even if the screen can be displayed and returned in the display area of the game board side effect display unit 1900 according to the probability and the time saving state, It is not possible to display at all which round of the jackpot gaming state. That is, for example, a game ball enters the special winning opening 2103 and is detected by the count switch 2110 shown in FIG. 14, and a special winning opening 1 count display command which conveys the number of balls of the game ball entering the special winning opening 2103 is displayed. Even if the main control board 4100 transmits to the peripheral control board 4140 and the peripheral control board 4140 receives the peripheral control board 4140, the peripheral control board 4140 enters the large winning opening 2103 on the screen according to the probability and the time saving state. Although the number can be displayed in the display area of the game board side effect display unit 1900, it is impossible to display at all which round of the big hit game state (that is, what round).

In such a situation, the main control board 4100 stops driving the attacker solenoid 2108 and opens the special winning opening 2103 by the opening/closing member 2107, for example, when finishing four rounds (fourth round) of the big hit game state. From the main control board 4100 to the peripheral control board, a special winning opening 1 closing display command for instructing the transition from the closed state to the closed state (that is, closing start of the special winning opening 2103 of the attacker unit 2100 between rounds). 4140 and when the main control board 4100 starts the big hit game state of the fifth round (fifth round), the attacker solenoid 2108 is started to drive and the special winning opening 2103 is closed by the opening/closing member 2107. From the main control board 4100 to the peripheral control board 4140, a special winning opening opening fifth display command for instructing to shift to the open state (that is, opening of the fifth winning round of the special winning opening 2103) is transmitted. .. As a result, the peripheral control board 4140 finally switches the screen for starting 5 rounds of the big hit game state from the screen corresponding to the above-mentioned probability and time saving state and displays it in the display area of the game board side effect display unit 1900. Become.

Further, for example, a screen informing that a game state in which a game ball can be received in the second starting opening 2102 is advantageous to the player (for example, a player is notified that the movable piece is open). Screen is transmitted to the peripheral control board 4140 in the display area of the game board side effect display unit 1900, the main control board 4100 drives the starting opening solenoid 2105 to move the movable piece 2106 shown in FIG. Is moved from the advanced position to the retracted position and the second starting port 2102 is opened, a momentary power failure or a power failure occurs, and when power is restored after that, the main control board 4100 proceeds to step S34. Based on the power recovery information set in the work area of the main control built-in RAM in the setting of the work area of the main control built-in RAM, by restoring to the game state immediately before the momentary power failure or power failure occurs, the starting opening The driving of the solenoid 2105 is started, the movable piece 2106 is moved from the retracted position to the advanced position, and the second starting port 2102 is closed.

However, when a momentary power failure or a power failure occurs, the peripheral control board 4140 receives various commands from the main control board 4100 and returns when the power is restored. Then, when power is restored thereafter, the peripheral control board 4140 can be restored based on the power-on state command received from the main control board 4100 at the time of power restoration. However, when the main control board 4100 is in a game state and is in a game state in which a game ball can be received in the second starting opening 2102, and a game state that is advantageous to the player is generated, a momentary power failure or a power failure occurs. Then, when power is restored after that, the peripheral control board 4140 displays the screen according to the probability and the time saving state based on the probability and the time saving state indicated by the power-on state command received from the main control board 4100 at the time of the power recovery. Even if it can be displayed and returned to the display area of the game board side effect display unit 1900, a game state in which a game ball can be received in the second starting opening 2102 is set and a game state advantageous to the player is set. The peripheral control board 4140 cannot display the screen indicating that the game board side effect display unit 1900 is displayed at all. Therefore, the player sitting on the front of the pachinko gaming machine is surprised that a momentary power failure or a power failure has occurred, and when the power is restored, the game ball is sent to the second starting opening 2102 immediately before the momentary power failure or the power failure. In some cases, it may be forgotten that the game state is acceptable, and in such a case, the game state at the time of power recovery is returned to the game state in which the game ball can be accepted into the second starting opening 2102. Despite that, the screen for instructing the game (that is, the screen for instructing to enter the game ball into the second starting opening 2102) is not displayed in the display area of the game board side effect display unit 1900 when the power is restored. As a result, there is a problem that the player does not know what kind of game he or she plays.

As described above, in the above-described two examples, there is a problem that the game state immediately before the momentary power failure or the power failure cannot be promptly restored after the power restoration. In other words, the player sitting on the front of the pachinko gaming machine, after a momentary power failure or power failure, and then restoring power, the pachinko gaming machine system appears to have collapsed, appearing to be in a so-called frozen state. There was a problem of misunderstanding.

Therefore, in the present embodiment, when the main control board 4100 is powered on (including power restoration, power restoration is also performed when a power failure or momentary power failure occurs and power is restored). In order to send the power-on main control return destination command to the peripheral control board 4140, in step S50, the power-on state command and power-on main control return destination command classified into the power-on shown in FIG. 45. A power-on main prize ball number information output determination counter notification command is created and stored as transmission information in the transmission information storage area of the main control built-in RAM. Then, these commands are transmitted in the main control side timer interrupt process described later.

Thereby, the peripheral control board 4140, based on the power-on state command and the power-on main control return destination command received from the main control board 4100, for example, in the above example, in the 4 rounds of the jackpot gaming state, When a momentary power failure or a power failure occurs and then the power is restored, the drive of the attacker solenoid 2108 is started and the special winning opening 2103 is released from the state closed by the opening/closing member 2107 as the return destination of the main control board 4100. Since it is possible to notify the peripheral control board 4140 of the shift to the state in which it is in the state, the peripheral control board 4140 is a screen that specifies that it is four rounds of the big hit game state (that is, a screen showing how many rounds it is). ) Cannot be displayed in the display area of the game board side effect display unit 1900, but in a big hit game state, the drive of the attacker solenoid 2108 is started, and the special winning opening 2103 is opened by the opening/closing member 2107. A screen that tells that there is a message (for example, a screen that tells the player that "It is a big hit. The big winning opening is open. Please play the game ball so that it enters the big winning opening.") It is possible to display in the display area of the game board side effect display unit 1900 and instruct the player sitting on the front of the pachinko gaming machine to play a game ball into the special winning opening 2103 after power recovery. In addition, for example, in the above-described example, in the state where the game ball can be received in the second starting opening 2102 and the game state is advantageous to the player, a momentary power failure or a power failure occurs, and then When the power is restored, as a return destination of the main control board 4100, the driving of the starting port solenoid 2105 is started to move the movable piece 2106 from the advanced position to the retracted position and the second starting port 2102 is opened. The peripheral control board that displays the message that tells the player that it is playing (eg, the screen that tells the player that the movable piece is open. Please play the game ball so that it enters the second starting opening) 4140 can be displayed in the display area of the game board side effect display unit 1900 to instruct the player sitting on the front of the pachinko gaming machine to play the game ball into the second starting opening 2102 after power recovery. it can. This allows the main control board 4100 side to finely instruct the return destination of the peripheral control board 4140 when the power is restored after an instantaneous blackout or power failure. Therefore, it is possible to quickly return to the game state immediately before the momentary power failure or power failure after the power is restored. In other words, the player sitting on the front of the pachinko gaming machine, after a momentary power failure or power failure, and then restoring power, the pachinko gaming machine system appears to be in a lumped state, a so-called frozen state, and breaks down. It is possible to prevent misunderstanding.

Next, in the main control board inspecting step which is an inspection step of the manufacturing line of the main control board 4100, when the main control board 4100 is first powered on after being manufactured for inspection, the checksum in step S28 is checked. The calculation and the determination in step S30 will be described. In the main control board inspection process, when the main control board 4100 is first turned on after being manufactured for inspection, the main control board 4100 is constituted by the above-described backup processing of steps S58 to S68 and an infinite loop. Since the main control MPU 4100a of the main control board 4100 has never executed the control-side power-off processing, even if the checksum based on the content of the main control internal RAM is calculated in step S28, In the comparison judgment, the checksum values cannot match, and the entire area of the main control built-in RAM must be cleared in step S38. As a result, when the command transmission to be transmitted at power-on is set in step S50, the power-on state command classified into power-on shown in FIG. 45, power-on main control return destination command, and power-on By creating a counter notification command for determining the main prize ball number information output and storing it as transmission information in the transmission information storage area of the main control internal RAM, a power-on status command, a power-on main control return destination command, and a power supply Only three commands, that is, the notification command counter notification command for determining the main prize ball number information output at the time of throwing in, are stored in the transmission information storage area of the main control built-in RAM as transmission information. In the main control timer interrupt processing described below, these commands are first sent a power-on state command, then a power-on main control return destination command, and then a power-on main prize ball count. The information output determination counter notification command is transmitted. Utilizing this, in the main control board inspection process, when the main control board 4100 is first powered on after being manufactured for inspection, the main control board 4100 sends a power-on state command as the first command. It will be transmitted to the inspection device in the main control board inspection process.

By the way, as described above, the power-on state command is shown in FIG. 15 at the time of power-on (in addition to the case of power-on, also at the time of power recovery when power failure or momentary power failure occurs and power is restored). Information indicating that when the operation switch 860a of the payout control board 4110 shown in the figure is operated to perform the RAM clear, and when the power is turned on (in addition to the case where the power is turned on, a power failure or a momentary power failure occurs and the power is reduced). (Including when power is restored), in any of the above-mentioned low-probability time-saving state, high-probability time-saving state, low-probability non-time-saving state, and high-probability non-time-saving state (probability and time-saving state) It is composed of information indicating whether or not to play and information indicating a model code of a pachinko gaming machine. Here, a problem when the power-on state command does not include information indicating the model code of the pachinko gaming machine will be described.

As described above, the model code of the pachinko gaming machine is used for the pachinko gaming machine 1 (to be exact, the main control board 4100) when creating a so-called max type, middle type, or sweet digital type. Whether it is for copyright, what kind of game specification (for example, if probability change occurs, in addition to the game specification that the state continues until the next big hit game state occurs, the number of times the special symbol changes is limited ( For example, it is possible to specify whether the game specification (so-called ST machine) or the like) in which the probability variation occurs after being played 30 times or 70 times).

In the manufacturing line of the manufacturer that manufactures the pachinko gaming machine 1, when the main control board 4100 is manufactured, the main control boards 4100 for copyrights of a plurality of types of works may be mixed. Then, the worker on the production line is the main copyright holder for which of the copyrights of the plurality of types of works (for example, the copyrights of the works of movie A, movie B, drama C, movie D, comic E, and comic F). It is unclear whether the main control board 4100 is flowing to the manufacturing line to manufacture the control board 4100, or the main control board for one of the copyrights of a plurality of types of works (for example, the copyright of the work called movie D). Although the main control board 4100 is flowing to the manufacturing line to manufacture the 4100, the main control board 4100 may be manufactured to manufacture the main control board 4100 for another copyright (for example, the copyright of the work called Manga F). There are also beliefs and misunderstandings that it is flowing to the production line. Therefore, when the main control board 4100 is manufactured in the manufacturing line of the manufacturer that manufactures the pachinko gaming machine 1, if the main control boards 4100 for copyrights of a plurality of types of works are mixed, the operator of the manufacturing line is It is not possible to confirm which copyright the main control board 4100 manufactured in is for the copyright of the same artwork, and even for the copyright of the same artwork, which model type (max type, middle type, sweet digital type) It is also not possible to confirm whether the game specifications are the same as the type), and what kind of game specifications (the game specifications and ST machines that will continue until the next big hit game state occurs when the probability fluctuation occurs). .. Accordingly, when the main control board 4100 is manufactured in the production line of the manufacturer that manufactures the pachinko gaming machine 1, if the main control boards 4100 for copyrights of a plurality of types of works are mixed, the main control for copyrights of a plurality of types of works is performed. The boards 4100 are mixed and sent to the game board assembly line for attaching the main control board 4100 to the game board 4. Therefore, the operator of the game board assembly line may attach the main control board 4100, which does not correspond to the game board 4 for the copyright of the work, to the game board 4. As a result, there is a problem that the production efficiency of the game board 4 is reduced.

Therefore, in the present embodiment, when the main control board 4100 is turned on (in addition to the case where the power is turned on, it also includes the time of power restoration in which power is restored due to a power failure or momentary power failure). In order to transmit the power-on state command including information indicating the code to the peripheral control board 4140, in step S50, the power-on state command classified into the power-on shown in FIG. A command, and a counter notification command for determining the main prize ball number information output at power-on are created and stored as transmission information in the transmission information storage area of the main control built-in RAM. Then, these commands are transmitted in the main control side timer interrupt process described later.

As a result, the operator of the manufacturing line of the manufacturer who manufactures the pachinko gaming machine 1 turns on the main control board 4100 in the main control board inspection step, which is the inspection step of the manufacturing line, so that the inspection device is the main control board. Based on the information indicating the model code of the pachinko gaming machine included in the power-on state command received from the 4100, that is, configuring the information indicating the model code of the pachinko gaming machine, the above-described max type indicating the model type, A series code to identify which type is the middle type or the sweet digital type, a copyright code to identify the copyright of the work, and a game specification (for example, if probability variation occurs, next big hit) In addition to the game specification that the state is continued until the game state occurs, the game specification (ST machine etc.) that the probability variation occurs in the state where the number of changes of the special symbol is limited) By visually observing the detailed model information displayed on the inspection monitor based on the code, it is possible to determine which work the copyright of the main control board 4100 belongs to and the copyright of the same work. Also, which model type (which type among max type, middle type, and sweet digital type) is, and what kind of game specification (if probability fluctuation occurs, that state until the next big hit game state occurs) It is also possible to determine whether or not the game specifications and ST machines) are to be continued. As a result, when the main control board 4100 is manufactured in the manufacturing line of the manufacturer that manufactures the pachinko gaming machine 1, even if the main control boards 4100 for copyrights of a plurality of types of works are mixed, the main control board inspection of the manufacturing line is performed. The operator of the process can accurately determine the model type of the main control board 4100, the copyright of the work, and the game specification by visually observing the inspection monitor. Can be sent to the game board assembly line. Then, the operator of the game board assembly line can securely attach the main control board 4100 corresponding to the game board 4 for the copyright of the work to the game board 4, and the main control board not corresponding to the game board 4 for the copyright of the work. It is possible to prevent the production efficiency of the game board 4 from decreasing due to the work of mounting the 4100 on the game board 4. Therefore, it is possible to contribute to the improvement of the production efficiency of the game board 4.

[16-3. Main control timer interrupt processing]
Next, the main control side timer interrupt process will be described. The main control side timer interrupt process is repeated every interrupt period (4 ms in this embodiment) set in the main control side power-on process shown in FIGS. 48 and 49.

When the main control timer interrupt processing is started, in the main control board 4100, the main control program switches the register bank under the control of the main control MPU 4100a as shown in FIG. 50 (step S100). The general-purpose storage element (general-purpose register) of the main control MPU 4100a has two register banks including a first register bank and a second register bank. The first register bank is used in the main control main process in the main control side power-on process described above, while the second register bank is used in the main control side timer interrupt process of this routine. In step S100, since the second register bank is used in the main control side timer interrupt process of this routine, the first register bank to the second register bank used in the main control main process in the main control side power-on process is changed to the second register bank. Switch the register bank to the register tank. In this embodiment, when the main control side timer interrupt process, which is the present routine, is started, it is not necessary to save each register to the stack.

Subsequent to step S100, the main control program performs a timer subtraction process (step S102). In this timer subtraction process, for example, the time when the upper special symbol display device 1185 and the lower special symbol display device 1186 are turned on according to the variable display pattern determined by the special symbol and special electric auditors product control process described later, and the ordinary symbol described below and In addition to the time when the normal symbol display device 1189 lights according to the normal symbol variation display pattern determined by the ordinary electric accessory control process, the payout control substrate 4110 normally issues various commands transmitted by the main control substrate 4100 (main control MPU 4100a). When it is determined whether or not the payer ACK signal indicating that the ACK signal has been received is input, time management such as the ACK signal input determination time set as the determination condition is performed. Specifically, when the fluctuation time of the fluctuation display pattern or the normal symbol fluctuation display pattern is 5 seconds, the timer interruption period is set to 4 ms, so the fluctuation time is decremented by 4 ms each time this timer subtraction process is performed. Then, when the subtraction result becomes the value 0, the variation time of the variation display pattern or the normal symbol variation display pattern is accurately measured.

In this embodiment, the ACK signal input determination time is set to 100 ms. Each time this timer subtraction process is performed, the ACK signal input determination time is subtracted by 4 ms, and the subtraction result becomes the value 0, so that the ACK signal input determination time is accurately measured. Note that these various times and the ACK signal input determination time are stored as time management information in the time management information storage area of the main control built-in RAM.

Following step S102, the main control program performs a switch input process (step S104). In this switch input processing, various signals input to the input terminals of various input ports of the main control MPU 4100a are read and stored as input information in the input information storage area of the main control internal RAM. Specifically, this main control program is, for example, a detection signal from the general winning opening switches 3020, 3020 shown in FIG. 14 for detecting the game balls entering the general winning openings 2104, 2201 shown in FIG. The detection signal from the count switch 2110 shown in FIG. 14 that detects the game ball that entered the special winning opening 2103 shown in FIG. 8 and the game ball that entered the first starting opening 2101 shown in FIG. 8 are detected. The detection signal from the first starting port switch 3022 shown in FIG. 14, the detection signal from the second starting port switch 2109 shown in FIG. 14 for detecting the game ball entering the second starting port 2102 shown in FIG. , A detection signal from the gate switch 2352 shown in FIG. 14 that detects a game ball that has passed through the gate unit 2150 shown in FIG. 8 and a magnetic detection switch 3024 that detects fraudulent activity using the magnet shown in FIG. The payer ACK signal from the payout control board 4110, which informs that the payout control board 4110 shown in FIG. 14 has normally received the detection signal and the prize ball command transmitted in the prize ball control processing described later, is read and input information Is stored in the input information storage area. Further, the detection signal from the first starting opening switch 3022 that detects the game ball that entered the first starting opening 2101, the detection signal from the second starting opening switch 2109 that detects the game ball that entered the second starting opening 2102. When each of the signals is read, the corresponding starting opening winning command shown in FIG. 46 and corresponding thereto is stored in the above-mentioned transmission information storage area as transmission information. That is, when there is a detection signal from the first starting port switch 3022, the corresponding starting port winning command is stored as transmission information in the transmission information storage area, and there is a detection signal from the second starting port switch 2109. Then, the starting mouth winning command corresponding thereto is stored as transmission information in the transmission information storage area.

In this embodiment, the detection signals from the general winning opening switches 3020 and 3020 that detect the game balls that have entered the general winning openings 2104 and 2201, and the count switch 2110 that detects the game balls that entered the large winning opening 2103. Detection signal from, the detection signal from the first starting opening switch 3022 that detects the game ball that entered the first starting opening 2101, the second starting opening switch 2109 that detects the game ball that entered the second starting opening 2102 The detection signal from the gate switch 2352 and the detection signal from the gate switch 2352 for detecting the game ball that has passed through the gate unit 2150 are read as the first time, respectively, for a predetermined time (for example, 10 μs). 2) After the elapse of time, it is read again as the second time. Then, the result read in the second time is compared with the result read in the first time. It is determined whether or not some of the comparison results have the same result. If the result is not the same, it is read again as the third time, and the result read at the third time is compared with the result read at the second time. It is again determined whether or not some of the comparison results have the same result. If the result is not the same, it is read again as the fourth time, and the result read at the fourth time is compared with the result read at the third time. It is again determined whether or not some of the comparison results have the same result. If the result is not the same, it is treated as if there is no game ball.

As described above, in the switch input process, the main control program detects the detection signals from the general winning opening switches 3020 and 3020, the count switch 2110, the first starting opening switch 3022, the second starting opening switch 2109, and the gate switch 2352. Due to the effect of chattering, noise, etc., by performing a total of two double readings, the second reading for comparing the first to third times and the second reading for comparing for the second to fourth times. Since it is possible to avoid erroneous detection, the detection signals from the general winning opening switches 3020 and 3020, the count switch 2110, the first starting opening switch 3022, the second starting opening switch 2109, and the gate switch 2352 are detected. The reliability can be increased.

Subsequent to step S104, the main control program performs a winning random number updating process (step S106). In this winning random number update process, the above-mentioned big hit symbol random number and small hit symbol random number are updated. In addition to these random numbers, the big hit symbol initial value determination random number, which is updated in the non-winning random number updating process of step S56 in the main control side power-on process (main control side main process) shown in FIG. 49, And the random number for determining the initial value for the small hit symbol is also updated. These big hit symbol initial value determination random numbers and small hit symbol initial value determination random numbers are updated in the main control side main processing and this main control side timer interrupt processing, respectively, to further enhance randomness. .. On the other hand, the big hit symbol random number and the small hit symbol random number are random numbers related to the winning determination (big hit determination), so that each time the winning random number updating process is performed, each counter counts up. In addition, the random number for normal symbol hit determination and the random number for initial value determination for normal symbol hit determination described above are also updated by this winning random number update process.

For example, as described above, the counter for updating the random number for determining the normal symbol is an initial value update type counter, and is updated within a predetermined fixed numerical value range from the minimum value to the maximum value. The range from the maximum value to the maximum value is incremented by incrementing the value by one each time this main control side timer interrupt process is performed. The normal symbol hit determination initial value determination random number is counted up toward the maximum value, and then the normal symbol hit determination initial value determination random number is counted up. When the counter finishes counting up the range from the minimum value to the maximum value of the normal symbol per hit determination random number, the big hit determination initial value determination random number is updated by this winning random number update process. The random number for determining the initial value for normal symbol hit determination can be obtained by executing an initial value lottery process for randomly selecting a value from the fixed numerical range of the counter that updates the random number for symbol hit determination. ..

In the present embodiment, the random number for determining the initial value for the big hit symbol and the random number for determining the initial value for the small hit symbol are set in step S56 of the main control side power-on process (main control side main process) shown in FIG. The winning random number updating process and the winning random number updating process of step S106 in the main control side timer interrupt process, which is the present routine, are respectively updated. However, each time the interrupt timer occurs, unevenness occurs in the processing time of this routine. If the number of times the non-winning random number updating process in step S56 is executed by randomly executing the main control side main process within the remaining time until the interrupt timer of is generated, a big hit symbol initial value determining random number , And the small hit symbol initial value determining random number may be updated only in the non-winning random number updating process of step S56.

Subsequent to step S106, the main control program performs prize ball control processing (step S108). In this prize ball control processing, the input information is read from the above-mentioned input information storage area, and the prize ball command shown in FIG. 44 for paying out the game balls based on this input information is created, or with the main control board 4100. The self-check command shown in FIG. 44 for confirming the connection state between the payout control board 4110 and the board is created. Then, the created prize ball command and self-check command are transmitted to the payout control board 4110 as main payment serial data. For example, when one game ball enters the special winning opening 2103 shown in FIG. 8 and enters a ball, a prize ball command for paying out 15 balls as a prize ball is created and the number of game balls planned to be paid out as a prize ball. Since it has reached 10 balls, the output of the main prize ball number information output signal is set in order to notify that fact, stored in the output information storage area as output information, and the prize ball command is transmitted to the payout control board 4110. Alternatively, when the payer ACK signal indicating that the payout control board 4110 has normally received the prize ball command is not input within a predetermined time, the connection state between the main control board 4100 and the payout control board 4110 is confirmed. For example, a self-check command is created and transmitted to the payout control board 4110.

In the prize ball control process of step S108, when the input information is read from the input information storage area described above and the number of game balls to be paid out as prize balls reaches 10 based on the input information. In order to notify that fact, a main prize ball number information output command divided into other parts shown in FIG. 46 is created and stored as transmission information in the transmission information storage area. The main prize ball number information output command is created based on the value of the main prize ball number information output determination counter. The value of the main prize ball number information output determination counter is read based on this input information by reading the input information from the above-mentioned input information storage area, that is, the first start port 2101 and the second start port provided on the game board 4. The number of game balls to be paid out as prize balls is counted based on the game balls that have entered the various prize holes such as 2102, the general prize holes 2104, 2201, and the large prize hole 2103, and step S108. In the prize ball control process, the memory is updated in the prize ball schedule information storage area of the main control built-in RAM. In the prize ball control processing of step S108, the value of the main prize ball number information output determination counter stored in the prize ball schedule information storage area of the main control RAM is read, and the read main prize ball number information output determination counter. The input information is read from the input information storage area described above, and the number of game balls to be paid out as a prize ball is added based on the input information, and the value indicating the added number is 10 When the number of game balls scheduled to be paid out as a prize ball has reached 10 balls, the main prize ball number information output command is created to inform that fact, and as the transmission information. The value is stored in the output information storage area, and the value indicating the number of exceeded balls is stored and updated in the prize ball schedule information storage area of the main control built-in RAM described above as the value of the main prize ball number information output determination counter. It has become.

Following step S108, the main control program performs a frame command reception process (step S110). In the payout control board 4110, the payout control program has various 1-byte (8-bit) commands divided into the status displays shown in FIG. 47 (for example, frame status 1 command, error release navigation command, and frame status 2 command). To send. On the other hand, as will be described later, the payout control program outputs an error cancellation navigation command based on the detection signal of the operation switch 860a. In the frame command reception process described above, when the main control program normally receives these various commands as payer serial data, the information to the effect is sent to the payout control board 4110, and output information is stored in the output RAM of the main control built-in RAM. Store in the area. Further, the main control program formats the command normally received as the payer serial data into a 2-byte (16-bit) command (various commands classified into the status display of FIG. 46 (frame status 1 command, error cancellation) The navigation command and the frame state 2 command)) are stored in the transmission information storage area described above as transmission information.

Following step S110, the main control program performs a fraudulent activity detection process (step S112). In this fraudulent activity detection processing, an abnormal state regarding the prize ball is confirmed. For example, when the input information is read from the above-mentioned input information storage area and the detection signal from the count switch 2110 is input when the jackpot is not in the gaming state (when the game ball enters the special winning opening 2103), etc. A winning abnormality display command classified into the notification display shown in FIG. 46 is created as an abnormal state, and is stored in the above-mentioned transmission information storage area as transmission information.

Following step S112, the main control program performs a special symbol and special electric auditors product control process (step S114). In this special symbol and special electric auditors product control processing, a latch signal is output to the main control built-in hard random number circuit 4100an shown in FIG. 14, and the random number extracted by the main control built-in hard random number circuit 4100an when the latch signal is input. The (random number value) is acquired from the hard random number latch register built in the main control built-in main control MPU 4100a, and the acquired random number value is set as the big hit determination random number. Whether or not the big hit determination random number (that is, the random number value obtained from the hard random number latch register built in the main control built-in main control MPU4100a) and the big hit determination value stored in the main control built-in ROM in advance match. Whether or not to determine (whether to generate a jackpot gaming state (referred to as "special lottery")), or take out the value of the counter for updating the jackpot symbol random number is stored in advance in the main control ROM It is determined whether or not the probability variation hit determination value matches (determination as to whether or not a probability variation occurs). Here, the “probability change” means that the probability of a big hit changes to a high probability (probability change time) that is set higher than in a normal time (low probability). In the present embodiment, the value 32668 to the value 32767 are set in the low probability as the range of the above-described big hit determination value (big hit determination range), and the value is read from the normal time determination table, whereas the value 31768 is set in the high probability. A value 32767 is set and is read from the probability variation determination table. In this way, in the special symbol and special electric auditors product control processing of step S114, the big hit determination random number (that is, the random number value obtained from the hard random number latch register built in the main control built-in main control MPU4100a) and the main control built-in When determining whether or not the jackpot determination value stored in the ROM in advance matches, the jackpot determination random number (that is, the random number value obtained from the hard random number latch register built in the main control built-in main control MPU4100a). It is performed depending on whether or not is included in the jackpot determination range.

When these determination results are based on the first starting port switch 3022, various commands related to special figure 1 tuning effect shown in FIG. 45 are created, while the lottery result is based on the second starting port switch 2109. In some cases, various commands related to special figure 2 entrainment effect shown in FIG. 45 are created and stored in the transmission information storage area as transmission information, and the upper special symbol display device 1185 according to the determined variable display pattern of the special symbol. Alternatively, the output of the lighting signal to the upper special symbol display 1185 or the lower special symbol display 1186 is set so as to light the lower special symbol display 1186, and is stored in the above-mentioned output information storage area as output information. Further, depending on the game state to be generated, for example, when the big hit game state is reached, various commands classified as the big hit related ones shown in FIG. 45 (big hit opening command, big winning opening 1 opening N-th display command, big winning opening 1 A closing display command, a special winning opening 1 count display command, a big hit ending command, and a big hit symbol display command) are created and stored in the transmission information storage area as transmission information, or the opening/closing member 2107 shown in FIG. 8 is opened/closed. When the output of the drive signal to the attacker solenoid 2108 is set and stored as output information in the output information storage area, or when the special winning opening 2103 is changed from the closed state to the open state twice (round), The output of the lighting signal to the two-round display lamp 1190a is set so as to light the two-round display lamp 1190a of the round display device 1190 shown in FIG. 13, and is stored in the output information storage area as output information, or when the round is 15 times. At some time, the output of the lighting signal to the 15-round display lamp 1190b is set so as to light the 15-round display lamp 1190b of the round display 1190 shown in FIG. The output of the lighting signal to the game state indicator 1183 is set so as to light the presence/absence of fluctuation in a predetermined color, and is stored in the output information storage area as output information.

Subsequent to step S114, the main control program performs normal symbol and normal electric auditors product control processing (step S116). In this normal symbol and normal electric auditors product control process, the input information is read from the above-mentioned input information storage area, and the gate winning process is performed based on this input information. In this gate winning process, it is determined from the input information whether or not the detection signal from the gate switch 2352 has been input to the input terminal. Based on this determination result, when the detection signal is input to the input terminal, the value of the counter for updating the above-mentioned random number for normal symbol determination is extracted and the gate information is stored in the gate information storage area of the main control RAM. Remember.

The gate information storage area is provided with 0th to 3rd partitions (4 partitions), and gate information is stored in the order of 0th partition, 1st partition, 2nd partition, and 3rd partition. It is like this. For example, when the gate information is stored in the 0th section to the 2nd section of the gate information storage, when the detection signal from the gate switch 2352 is input to the input terminal, the gate information is stored in the third section of the gate information storage. To do.

The gate information stored in the 0th section of the gate information storage is set in the work area of the main control built-in RAM. When this gate information is set, the gate information of the first section of the gate information storage is set to the 0th section of the gate information storage, the gate information of the second section of the gate information storage is set to the first section of the gate information storage, and the gate information is set to the first section of the gate information storage. The gate information of the third section of information storage is shifted to the second section of gate information storage, and the third section of gate information storage becomes an empty area. For example, when the gate information is stored in the first section to the second section of the gate information storage, the gate information of the first section of the gate information storage is stored in the 0th section of the gate information storage and the gate information of the first section of the gate information storage is stored in the second section. The gate information of the two sections is respectively shifted to the first section of the gate information storage, and the second section of the gate information storage and the third section of the gate information storage become empty areas. Here, when the gate information is stored in the first to third sections of the gate information storage, the above-mentioned gate information is set so that the normal symbol storage display 1188 is turned on with the total number of the stored gate information as the reserved sphere. The output of the lighting signal of the normal pattern storage display 1188 is set based on the above, and is stored in the above-mentioned output information storage area as output information.

Subsequent to the gate winning process, the gate information set in the work area of the main control built-in RAM is read out, and the value of the random number for normal symbol determination is extracted from this read gate information and stored in advance in the main control built-in ROM. It is determined whether or not the normal symbol hit determination value matches (called "ordinary lottery"). Whether or not the movable piece 2106 is opened/closed is determined based on the result of this determination (the result of the ordinary lottery). When the opening/closing operation is performed by this determination, the movable piece 2106 is moved from the advanced position to the retracted position, whereby the game ball becomes receivable in the second starting opening 2102 and the player enters the game state. The game state is advantageous to. The variable display pattern of the normal symbol corresponding to this determination is determined based on the random number for the normal symbol variable display pattern described above, and various commands classified in relation to the universal symbol synchronization effect shown in FIG. 45 are created and used as transmission information. While storing in the transmission information storage area described above, the output of the lighting signal to the normal symbol display device 1189 is set to light the normal symbol display device 1189 according to the determined variable display pattern of the ordinary symbol, and the output information is described above. Stored in the output information storage area. Further, for example, when the value of the random number for normal symbol hit determination that has been taken out coincides with the normal symbol hit determination value stored in advance in the main control built-in ROM, various commands related to the normal electric power combination effect shown in FIG. 45. Is generated and stored as transmission information in the transmission information storage area, and the output of the drive signal to the starting opening solenoid 2105 is set so as to open and close the movable piece 2106, and stored as the output information in the output information storage area described above. On the other hand, when the value of the extracted normal symbol per determination random number does not match the normal symbol per determination value prestored in the main control built-in ROM, the normal symbol based on the above random symbol variation display pattern random symbol The variable display pattern is determined, various commands classified into related to the universal figure synchronization effect shown in FIG. 45 are created, and stored in the above-mentioned transmission information storage area as transmission information, and according to the determined normal symbol variation display pattern. The output of the lighting signal to the normal symbol display device 1189 is set so that the normal symbol display device 1189 is turned on, and is stored in the above-mentioned output information storage area as output information.

Following step S116, the main control program performs a port output process (step S118). In this port output processing, output information is read from the output information storage area described above from the output terminals of various output ports of the main control MPU 4100a, and various signals are output based on this output information. This main control program, for example, outputs the main payment ACK signal from the output terminal of the predetermined output port of the main control MPU 4100a based on the output information when the various commands from the payment control board 4110 are normally received. Or output a drive signal to an attacker solenoid 2108 that opens/closes the opening/closing member 2107 of the special winning opening 2103 when in the big hit game state, or a drive signal to a starting opening solenoid 2105 that opens/closes the movable piece 2106. In addition to outputting, 15 round big hit information output signal, 2 round big hit information output signal, probability fluctuation information output signal, special symbol display information output signal, normal symbol display information output signal, time saving medium information output signal, start Various information (game information) signals relating to the game, such as a mouth winning information output signal, are output to the payout control board 4110.

Following step S118, the main control program performs peripheral control board command transmission processing (step S120). In this peripheral control board command transmission processing, the main control program reads the transmission information from the above-mentioned transmission information storage area and transmits this transmission information to the peripheral control board 4140 as main circumference serial data. In this transmission information, various commands created in the main control side timer interrupt processing of this routine shown in FIG. 45 and classified into special figure 1 tuning effect-related and special figure 2 tuning effect-related Various commands classified into commands and big hits (for example, big winning based on a detection signal from a count switch 2110 (see FIG. 14) when a game ball entering a big winning opening 2103 (see FIG. 8) is detected) 46, a command for displaying a special winning opening 1 count corresponding to a mouth count command), various commands classified for turning on the power, various commands classified for general figure synchronization performance, various commands classified for normal electric-commodity performance, FIG. , Various commands classified into the notification display, various commands classified into the status display, various commands classified into the test-related and various other commands (for example, the main control board 4100 is the first start port). The number of game balls to be paid out as a prize ball is 10 based on the game balls that have entered the various winning holes such as 2101, the second starting opening 2102, the general winning openings 2104, 2201, and the special winning opening 2103. A main prize ball number information output command for instructing to transmit a main prize ball number information output signal to the hall computer via the external terminal board 784 as main prize ball number information each time it reaches) is stored. One packet of the main circumference serial data is composed of 3 bytes. Specifically, the main serial data includes a status indicating a type of command having a storage capacity of 1 byte (8 bits), a mode indicating a variation of an effect having a storage capacity of 1 byte (8 bits), and a status. And a sum value obtained by calculating the sum of the modes as numerical values, and the sum value is created at the time of transmission.

In this peripheral control board command transmission processing, the main control program transmits various commands as main circumference serial data to the peripheral control board 4140 in the order of status, mode, and sum value. As described above, the electric charge charged in the electrolytic capacitor MC2 shown in FIG. 24 is applied as +5 V to the VDD terminal which is the power supply terminal of the main control MPU 4100a, as described above. Therefore, the main-circulation serial transmission port 4100ae built in the main control MPU 4100a shown in FIG. The data can be transferred to the register 41eaa and the transmission can be completed from the transmission shift register 4100ea as the main serial data. At the time of turning on the power to the pachinko gaming machine 1 or at the time of power restoration when power is restored after a power failure or momentary power failure occurs after the power is turned on, at the time of turning on the power in step S50 in the main control side power-on process shown in FIG. In the reservation setting of the command to be transmitted, in order to inform that the power is restored, the power-on state command classified into the power-on shown in FIG. 45, the power-on main control return destination command, and the power-on main prize ball Since the counter notification command for determining the number information output is created and stored as transmission information in the transmission information storage area of the main control internal RAM, the power-on state command is configured as the main serial data, the status, the mode, Then, it is transmitted to the peripheral control board 4140 in the order of the sum value, and subsequently, to the peripheral control board 4140 in the order of the status, the mode, and the sum value forming the main control return destination command at power-on, and then the power is turned on. An hour main prize number information output determination counter notification command is transmitted to the peripheral control board 4140 in the order of status, mode, and sum value. In the transmission information storage area of the main control built-in RAM, various information is read from the game backup information and set according to the various information in the setting of the work area of the main control built-in RAM in step S34 in the main control side power-on process. There are also cases where various commands are stored. In such a case, first after completion of transmission of various commands according to game information among various information, then power-on state command, power-on main control return destination command, and power-on main prize ball number information The output determination counter notification command will be transmitted.

Following step S120, the main control program clears the main control built-in WDT 4100af shown in FIG. 14 (step S122), and ends this routine. The main control built-in WDT 4100af in step S22 is cleared by setting the timer clear set value in the WDT clear register built in the main control MPU 4100a. As a result, the timekeeping by the main control built-in WDT 4100af is cleared. Then, when the main control built-in WDT 4100af restarts timing, the main control built-in WDT 4100af does not force the main control MPU 4100a to be reset.

As described above, the main control board 4100 stores the game information based on the progress of the game before the power to the pachinko gaming machine 1 is shut off during the progress of the game. It can be completed by executing the backup process, and at the time of power recovery, as a destination of the progress of the game by the main control board 4100, based on the game information for which the backup process is executed, the power to the pachinko gaming machine 1 is turned on. Peripheral control of the power-on main control return destination command of FIG. 45 which instructs the drive state of the starting opening solenoid 2105 and the attacker solenoid 2108 which are electric drive sources by the port output processing of step S118 in this routine when shutting off It is possible to output to the substrate 4140. That is, in the main control board 4100, in the reservation setting of the command transmitted at power-on in step S50 in the main-control-side power-on process of FIG. 49, in the setting of the work area of the main control internal RAM in step S34 in the same process. Based on the power recovery information set in the work area of the built-in control RAM, the power-on status command and power-on main command classified into power-on in FIG. A control return destination command and a power-on main prize ball number information output determination counter notification command are created and stored as transmission information in the transmission information storage area of the main control internal RAM, and the peripheral control board command of step S120 in this routine. In the transmission processing, main-cycle serial data is transmitted to the peripheral control board 4140 in the order of the power-on state command, the status, the mode, and the sum value, and then the power-on main control return destination command is configured. , Status, mode, and sum value are transmitted to the peripheral control board 4140 in this order, and then the power-on main prize ball number information output determination counter notification command is configured. It is transmitted to the control board 4140. Therefore, the peripheral control board 4140, based on the power-on main control return destination command from the main control board 4100, the game board side effect display unit 1900 as the return destination of the progress of the game by the main control board 4100 at the time of power recovery. Can be displayed in the display area. As a result, when a player is playing a momentary power failure or power outage and then recovers power, the player immediately returns to the game state immediately before the power failure or power failure. In addition to being able to perform, the destination of the progress of the game by the main control board 4100 can be displayed in the display area of the game board side effect display unit 1900 for notification, so that the system of the pachinko gaming machine 1 is in a condensed state, so-called. It is possible to prevent the player from seeing the player in a frozen state and misunderstanding that the player is out of order. Therefore, by returning to the gaming state immediately before the momentary power failure or the power failure after the power is restored, it is possible to prevent the player from misunderstanding that the player is out of order.

Further, in the main control board inspecting step which is an inspection step of the manufacturing line of the main control board 4100, when the main control board 4100 is first powered on after being manufactured for inspection, as shown in FIG. In step S38 in the power-on process on the main control side, all areas of the main control internal RAM must be cleared. Accordingly, in the reservation setting of the command to be transmitted at power-on in step S50 in the same process, when the reservation setting of the command to be transmitted at power-on is performed, the power-on state command classified into the power-on shown in FIG. 45. When the power is turned on, a power-on main control return destination command and a power-on main prize ball number information output determination counter notification command are created and stored as transmission information in the transmission information storage area of the main control internal RAM. A state in which only three commands, a state command, a power-on main control return destination command, and a power-on main prize ball number information output determination counter notification command, are stored as transmission information in the transmission information storage area of the main control internal RAM. In the peripheral control board command transmission process of step S120 in this routine, the main control board inspection process is performed in the order of status, mode, and sum value, which constitutes a power-on state command as main circumference serial data. It is sent to the inspection device in the main control board inspection process in the order of status, mode, and sum value that make up the main control return destination command at power-on, and then the main prize ball number information output at power-on. The determination counter notification command is transmitted to the inspection device in the main control board inspection process in the order of status, mode, and sum value. The inspection device in the main control board inspection process, based on the information indicating the model code of the pachinko gaming machine included in the power-on state command received from the main control board 4100, that is, the information indicating the model code of the pachinko gaming machine. A series code for identifying which type of the above-mentioned Max type, a middle type, and a sweet digital type indicating the model type, and a copyright code for identifying the copyright of the work, Game specifications (for example, if probability changes occur, in addition to game specifications that the state continues until the next big hit game state occurs, game specifications that probability changes occur in a state where the number of changes of special symbols is limited. Based on the game specification code for specifying (ST machine, etc.), detailed model information is displayed on the inspection monitor of the main control board inspection process.

[17. Various control processing of payout control board]
Next, various control processes performed by the payout control board 4110 shown in FIG. 15 will be described with reference to FIGS. 51 to 67. 51 is a flowchart showing an example of the power-on process of the payout control unit, FIG. 52 is a flowchart showing the process at the power-on of the payout control unit of FIG. 51, and FIG. 53 is a payout control unit following FIG. 52. FIG. 54 is a flowchart showing a continuation of the power-on process, FIG. 54 is a flowchart showing an example of a payout control unit timer interrupt process, FIG. 55 is a flowchart showing an example of a rotation angle switch history creating process, and FIG. 56 is a sprocket. FIG. 57 is a flow chart showing an example of fixed position determination skip processing, FIG. 57 is a flow chart showing an example of ball deviation determination processing, and FIG. 58 is a flow chart showing an example of prize ball stock number addition processing for prize balls. 59 is a flow chart showing an example of a ball scoring award ball stock number addition processing, FIG. 60 is a flow chart showing an example of stock monitoring processing, and FIG. 61 is a flow chart showing an example of payout ball bending operation determination setting processing. FIG. 62 is a flowchart showing an example of payout setting processing, FIG. 63 is a flowchart showing an example of ball-bending operation setting processing, FIG. 64 is a flowchart showing an example of retry operation monitoring processing, and FIG. 66 is a flowchart showing an example of a mismatch counter reset determination process, FIG. 66 is a flowchart showing an example of an error cancellation operation determination process, and FIG. 67 is a signal process (a) at the time of a payout operation by a ball lending, from the CR unit. 5 is a timing chart showing the input signal confirmation processing (a) of FIG.

First, the payout control unit power-on process will be described, and then the payout control unit timer interrupt process, rotation angle switch history creation process, sprocket fixed position determination skip process, ball glide determination process, prize ball stock number addition for prize balls. Processing, award ball stock number addition processing for ball rental, stock monitoring processing, payout ball bending operation determination setting processing, payout setting processing, ball bending operation setting processing, retry operation monitoring processing, inconsistency counter reset determination processing, error cancellation The operation determination process will be described. In addition, rotation angle switch history creation processing, sprocket fixed position determination skip processing, ball deviation determination processing, prize ball award ball stock number addition processing, award ball award ball stock number addition processing, stock monitoring processing, payout ball observation The operation determination setting process, the retry operation monitoring process, the inconsistency counter reset determination process, and the error cancellation operation determination process are performed as one process of the main operation setting process of step S562 in the power-on process of the payout control unit, which will be described later. Switch history creation processing, sprocket fixed position determination skip processing, ball enlarging determination processing, retry operation monitoring processing, inconsistency counter reset determination processing, error cancellation operation determination processing, prize ball prize number addition processing, ball rental prize The priority order is set in the order of the ball stock number addition process, the stock monitoring process, and the payout ball scooping motion determination setting process.

[17-1. Discharge controller power-on process]
When the pachinko gaming machine 1 is powered on, in the payout control unit 4120 of the payout control board 4110, the payout control program is under the control of the payout control MPU 4120a, as shown in FIGS. Perform processing at the time of input. When this payout control unit power-on process is started, the payout control program causes the payout control MPU 4120a to set the interrupt mode (step S500). This interrupt mode sets the priority of interrupts of the payout control MPU 4120a. In the present embodiment, a payout control unit timer interrupt process, which will be described later, is set as the highest priority, and when an interrupt of the payout control unit timer interrupt process occurs, the process is preferentially performed.

Subsequent to step S500, the payout control program performs input/output setting (input/output setting of I/O) (step S502). In this I/O input/output setting, various input ports and various output ports of the payout control MPU 4120a are set.

Subsequent to step S502, the payout control program performs wait timer processing 1 (step S506) and determines whether or not a power failure advance notice signal is input (step S508). The voltage does not rise immediately after the power is turned on until it reaches the specified voltage. On the other hand, at the time of a power failure or an instantaneous power failure (a phenomenon in which the power supply is temporarily stopped), if the voltage drops and becomes lower than the power failure notification voltage, the power failure monitoring circuit 4100e of the main control board 4100 shown in FIG. A warning signal (payment blackout warning signal) is input. Similarly, when the voltage becomes lower than the power failure warning voltage from the time when the power is turned on to the predetermined voltage, a power failure warning signal (payout power failure warning signal) is input from the power failure monitoring circuit 4100e of the main control board 4100. Therefore, the wait timer process 1 of step S506 is a process for waiting until the voltage becomes larger than the power failure warning voltage and stabilizes after the power is turned on. In this embodiment, the wait time (wait timer) is 200 milliseconds (wait timer). ms) is set. The determination in step S508 is performed based on the power failure notice signal (payout power failure notice signal) from the power failure monitor circuit 4100e of the main control board 4100.

Following step S508, the payout control program determines whether or not the operation switch 860a is operated (step S512). This determination is based on the logical value of the operation signal from the operation switch 860a, and when the logical value of the operation signal from the operation switch 860a is HI, it is not an instruction to perform the RAM clear, and the operation switch is determined. While it is determined that the operation switch 860a is not operated, when the logical value of the operation signal from the operation switch 860a is LOW, it is determined that the instruction is to clear the RAM, and the operation switch 860a is operated. judge.

When the operation switch 860a is operated in step S512, the payout control program sets a value 1 to the payout RAM clear notification flag HRCL-FLG (step S514). That is, the payout control program can execute a RAM clear process for initializing a RAM (hereinafter referred to as “payout control built-in RAM”) built in the payout control MPU 4120a for a predetermined time after the power is turned on. It will be in a state. On the other hand, when the operation switch 860a is not operated in step S512, the payout control program sets a value 0 to the payout RAM clear notification flag HRCL-FLG (step S516). The payout RAM clear notification flag HRCL-FLG is stored in the payout control internal RAM (payout storage unit) of the payout control MPU 4120a, for example, various flags, various information stored in various information storage areas (for example, The award ball stock number PBS, the actual ball count PB, the drive command number DRV, the mismatch counter INCC, etc. stored in the award ball information storage area and the logic of the PRDY signal stored in the CR communication information storage area It is a flag indicating whether or not the payout information relating to the payout of the PRDY signal output setting information etc. for which the state is set is erased, and is set to a value 1 when the payout information is erased and a value 0 when the payout information is not erased. To be done. The payout RAM clear notification flag HRCL-FLG set in step S514 and step S516 is stored in the general-purpose storage element (general-purpose register) of the payout control MPU 4120a.

Subsequent to step S514 or step S516, the payout control program sets to permit access to the payout control internal RAM (step S518). With this setting, the payout control built-in RAM can be accessed, and for example, payout information can be written (stored) or read.

Following step S518, the payout control program sets the stack pointer (step S520). The stack pointer indicates, for example, the address stacked on the stack to temporarily store the contents of the storage element (register) being used, or the return address of this routine when exiting the subroutine and returning to this routine. It also indicates the address stacked on the stack for storage, and the stack pointer advances each time the stack is stacked. In step S520, the stack pointer is set to the initial address, and the contents of the register, the return address, etc. are stacked on the stack from the initial address. Then, the stack pointer returns to the initial address by sequentially reading from the stack stacked last to the stack stacked first.

Following step S520, the payout control program determines whether or not the payout RAM clear notification flag HRCL-FLG has a value of 0 (step S522). As described above, the payout RAM clear notification flag HRCL-FLG is set to a value of 1 when the payout information is erased and a value of 0 when the payout information is not erased.

When the payout RAM clear notification flag HRCL-FLG has a value of 0 in step S522, that is, when the payout information is not erased, the payout control program calculates a checksum (step S524). This checksum regards the payout information stored in the payout control built-in RAM as a numerical value and calculates the total thereof.

Subsequent to step S524, the payout control program determines whether or not the calculated checksum value matches the checksum value stored in the payout control unit power-off process (power-off) to be described later. (Step S526). When they match, the payout control program determines whether or not the payout backup flag HBK-FLG has a value of 1 (step S528). The payout backup flag HBK-FLG is a flag indicating whether or not payout backup information such as payout information and checksum value is stored and held in the payout control internal RAM in the power-off process of the payout control unit described later. The value is set to 1 when the control unit power-off process is normally completed, and is set to a value 0 when the payout control unit power-off process is not normally completed.

When the payout backup flag HBK-FLG has a value of 1 in step S528, that is, when the payout control unit power-off process is normally completed, the payout control program sets the work area of the payout control internal RAM as the time of power recovery. (Step S530). In this setting, the value 0 is set in the payout backup flag HBK-FLG, and the power recovery information is read from the ROM (hereinafter referred to as the “payout control built-in ROM”) built in the payout control MPU 4120a. Then, this power recovery information is set in the work area of the payout control built-in RAM. Thereby, the above-mentioned payout backup information stored in the payout control built-in RAM, various flags, various information stored in various information storage areas, etc. (for example, a prize stored in the prize ball information storage area, PRDY signal output setting information in which the logical state of the PRDY signal stored in the CR communication information storage area, such as the sphere stock number PBS, the actual sphere count PB, the drive command number DRV, the inconsistency counter INCC, and the like, Information used for various processes is set based on the payout information related to the payout of the inconsistency counter reset determination time and the like stored in the time management information storage area. It should be noted that the term "power recovery" includes not only the state in which the power is turned off and the state in which the power is turned on, but also the state in which the power is restored after a power failure or an instantaneous power failure.

On the other hand, when the payout RAM clear notification flag HRCL-FLG is not 0 (value 1) in step S522, that is, when the payout information is deleted, or when the checksum values do not match in step S526, or step In S528, when the payout backup flag HBK-FLG is not the value 1 (the value is 0), that is, when the payout control unit power-off process is not normally completed, the payout control program causes all areas of the payout control internal RAM to be filled. Clear (step S532). That is, the payout control program executes the payout control side RAM clearing process triggered by the detection of the operation signal of the operation switch 860a. As a result, the payout backup information stored in the payout control built-in RAM is cleared.

Following step S532, the payout control program sets the work area of the payout control internal RAM as an initial setting (step S534). In this setting, the initial information is read from the payout control built-in ROM and this initial information is set in the work area of the payout control built-in RAM.

Subsequent to step S530 or step S534, the payout control program performs interrupt initialization (step S536). This setting sets the interrupt cycle when the payout control unit timer interrupt process, which will be described later, is performed. In this embodiment, it is set to 2 ms.

Subsequent to step S536, the payout control program sets interruption permission (step S538). With this setting, the payout control unit timer interrupt process is repeatedly performed at the interrupt cycle set at step S536, that is, every 2 ms.

Following step S538, the payout control program sets the value A in the watchdog timer clear register HWCL (step S539). The watchdog timer is cleared by setting the value A, the value B and the value C in this watchdog timer clear register HWCL in order.

Subsequent to step S539, the payout control program determines whether or not the power failure notice signal (payment power failure notice signal) is input (step S540). As described above, when the power of the pachinko gaming machine 1 is cut off, or when the power is interrupted or momentarily stopped, when the voltage becomes equal to or lower than the power failure warning voltage, the power failure warning signal (payout power failure warning signal) is issued as the power failure warning as the main control board. It is input from the power failure monitoring circuit 4100e of 4100. The determination in step S540 is made based on this power failure notice signal.

When no power failure notice signal is input in step S540, the payout control program determines whether or not the 2 ms elapsed flag HT-FLG has a value of 1 (step S542). The 2 ms elapsed flag HT-FLG is a flag for measuring 2 ms in the payout control unit timer interrupt processing that is processed every 2 ms, which will be described later. Is set.

When the 2 ms elapsed flag HT-FLG has a value of 0 in step S542, that is, when 2 ms has not elapsed, the process returns to step S540, and the payout control program determines whether or not the power outage notice signal (payout power outage notice signal) is input. To judge.

On the other hand, when the 2 ms elapsed flag HT-FLG has the value 1 in step S542, that is, when 2 ms has elapsed, the payout control program sets the 2 ms elapsed flag HT-FLG to the value 0 (step S544).

Following step S544, the payout control program sets the value B in the watchdog timer clear register HWCL (step S546). At this time, the value B set after the value A set in step S539 is set in the watchdog timer clear register HWCL.

Following step S546, the payout control program performs a port output process (step S548). In this port output processing, various information is read from the output information storage area of the payout control built-in RAM, and various signals are output from the output terminals of various output ports of the payout control MPU 4120a based on this various information. In the output information storage area, for example, payer ACK information indicating that various commands related to payout from the main control board 4100 (the prize ball command and the self-check command shown in FIG. 44) are normally received, and the payout motor 744. Various information such as drive information for performing drive control to, award ball number information of the number of balls actually paid out by the payout motor 744, LED display information displayed on the error LED display 860b, and the like are stored. When various commands relating to the payout from the main control board 4100 are normally received from the output terminal of the predetermined output port of the payout control MPU 4120a based on the output information, the payer ACK signal is output to the main control board 4100 or the payout motor is issued. A driving signal is output to 744, or the number of balls actually paid out by the payout motor 744 is output to the external terminal board 784 as an award ball number information output signal (in the present embodiment, the payout motor 744 is actually Every time 10 gaming balls are paid out, the award ball number information output signal is output to the external terminal board 784. Specifically, the award ball number for determining whether or not to output the award ball number information. An information output determination counter is provided, and this award ball number information output determination counter indicates the number of game balls actually paid out by the payout motor 744 in FIG. 15 in the port input process of step S550 described later. Based on the detection signal from the counting switch 751, the payout motor 744 performs a payout ball with a payout control built-in RAM by a process (program) (not shown) for monitoring the number of game balls actually paid out by the payout motor 744. In the processing (program) (not shown) for monitoring the number of game balls actually paid out by the payout motor 744, the prize ball information storage in the payout control built-in RAM is performed. The payout motor 744 actually paid out to the value of the prize ball number information output determination counter stored in the area, based on the detection signal from the counting switch 751 shown in FIG. In the port output processing of step S548, the value of the award ball number information output determination counter is read from the award ball information storage area, and the read award ball number information output determination is performed. When the value of the counter for use exceeds the value 10 (that is, when the number of game balls actually paid out by the payout motor 744 has reached 10 balls), an award ball number information output signal is output to the external terminal board 784. Output and the number of balls exceeded Is stored in the prize ball information storage area of the payout control built-in RAM described above as the value of the prize ball number information output determination counter. ), and outputs a display signal to the error LED display 860b.

Subsequent to step S548, the payout control program performs a port input process (step S550). In this port input processing, various signals input to the input terminals of various input ports of the payout control MPU 4120a are read and stored as input information in the input information storage area of the payout control internal RAM. For example, an operation signal of the operation switch 860a, a detection signal from the rotation angle switch 752, a detection signal from the counting switch 751, a detection signal from the full tank switch 550, a BRQ signal from the CR unit 6, a BRDY signal and a CR connection signal, A main payment ACK signal from the main control board 4100 for notifying that the main control board 4100 has normally received the various commands transmitted in the command transmission processing described later is read and stored as input information in the input information storage area.

Subsequent to step S550, the payout control program performs timer updating processing (step S552). In this timer updating process, when determining whether or not the ball-blown state due to the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted is determined, the ball-blur determination is set as the determination condition. Time, skip determination time set when the fixed position determination of the payout rotating body is not performed, determination of whether or not the accommodation space of the foul cover unit 540 shown in FIG. 1 is full of game balls stored When the game is performed, whether the full tank determination time set as the determination condition and the number of game balls taken into the supply passage of the prize ball device 740 by the detection signal from the out-of-ball switch 750 are the predetermined number or more. In addition to performing time management such as the out-of-ball determination time set as the determination condition when determining whether or not, the number of balls of the game balls received and received in the recess of the payout rotating body, and the actual It is determined whether or not to reset the inconsistency counter INCC for monitoring whether or not the payout of game balls that are not consistent due to the inconsistency with the number of balls detected by the counting switch 751 is repeatedly performed. At that time, the discrepancy counter reset judgment time set as the judgment condition is managed. For example, when the ball-judging determination time is set to 5005 ms, the timer interrupt period is set to 2 ms, so the ball-judging determination time is subtracted by 2 ms each time this timer update processing is performed, and the subtraction result When the value becomes 0, the ball-blurring judgment time is accurately measured.

In this embodiment, the skip determination time is set to 22.75 ms, the full tank determination time is 504 ms, the out-of-ball determination time is 119 ms, and the inconsistency counter reset determination time is set to 7000 s (about 2 hours). Every time the process is performed, the full tank determination time, the out-of-ball determination time, and the inconsistency counter reset determination time are subtracted by 2 ms, and the subtraction result becomes the value 0. The full-tan determination time, the out-of-ball determination time, and the inconsistency counter reset Accurately measure the judgment time. The various determination times are stored in the time management information storage area of the payout control built-in RAM as time management information.

Following step S552, the payout control program performs CR communication processing (step S554). In this CR communication processing, it is determined whether or not various signals (BRQ signal, BRDY signal and CR connection signal) from the CR unit 6 are input based on the input information read from the above-mentioned input information storage area. To judge. Based on various signals from the CR unit 6, the payout control MPU 4120a exchanges various signals with the CR unit 6. In the process of setting the work area of the payout control built-in RAM in step S530, various flags, which are payout backup information stored in the payout control built-in RAM, and various information stored in various information storage areas, as described above. Etc. (eg, prize ball stock number PBS, actual ball count PB, drive command number DRV, inconsistency counter INCC, etc. stored in the prize ball information storage area, PRDY stored in the CR communication information storage area, etc. Information used for various processes is set based on payout information relating to payout of PRDY signal output setting information in which the signal logic state is set.

By this processing, for example, even after an instantaneous power failure or a power failure, the values of the prize ball stock number PBS, the actual ball count PB, the drive command number DRV, the inconsistency counter INCC, etc. at the time of power recovery are stored as payout backup information. It is possible to restore the values of the prize ball stock number PBS, the actual ball count PB, the drive command number DRV, the inconsistency counter INCC, etc. immediately before the momentary power failure or the power failure. As a result, even when the payout operation of the game balls by the prize ball device 740 is being executed, even if the payout operation cannot be continued due to a momentary power failure or a power failure, the payout operation can be continued when the power is restored. Therefore, the game balls can be paid out to the upper plate 301 and the lower plate 302 without excess or deficiency. In other words, the payout control MPU 4120a, in the CR communication process, exchanges various signals with the CR unit 6, while paying out the game ball to the upper plate 301 and the lower plate 302, a momentary power failure or a power failure and CR Even if the exchange of various signals with the unit 6 is interrupted and it becomes impossible to continue paying out game balls, the number of prize balls stock PBS, actual ball count PB, drive command number DRV, inconsistency counter INCC at power recovery By restoring the values such as, etc. to the values of the prize ball stock number PBS, the actual ball count PB, the drive command number DRV, the inconsistency counter INCC, etc., which are stored as the payout backup information immediately before the momentary power failure or the power failure. The exchange of various signals between the pachinko gaming machine 1 (payout control MPU4120a) and the CR unit 6 immediately before a momentary power failure or power failure can be continued from the time of power recovery, and the game balls can be continuously paid out. You can do it.

In this way, the exchange of various signals between the pachinko gaming machine 1 (payout control MPU 4120a) and the CR unit 6 is restored to the state immediately before the momentary power failure or stop even when the power is restored, even if the power is interrupted or stopped. The various signals by the pachinko gaming machine 1 (payout control MPU 4120a) and the CR unit 6 are not changed by the influence of the momentary power failure or stop. Therefore, the reliability of the exchange of various signals between the pachinko gaming machine 1 (payout control MPU 4120a) and the CR unit 6 can be improved.

Further, various information stored in the CR communication information storage area is included in the payout backup information as described above. In the CR communication process, when power is restored, the PRDY signal output setting information is read from the CR communication information storage area stored in the payout control RAM, which is set in the process of setting the work area of the payout control RAM in step S530. When the PRDY signal output setting information read out by the lever is set to the logical state of the PRDY signal indicating that the payout operation for paying out the rental ball is impossible, for example, the PRDY signal is controlled to be paid out. It outputs to the CR unit 6 from the output terminal of the predetermined output port of MPU4120a. The value of the inconsistency counter INCC of the prize ball information storage area, which is included in the payout backup information and is stored in the payout control built-in RAM, is included in the payout backup information, for example, in the retry operation monitoring process that is performed as one process of the main operation setting process. It is determined whether or not the value of the inconsistency counter INCC is smaller than the inconsistency threshold INCTH based on the above, and when the value of the inconsistency counter INCC is not smaller than the inconsistency threshold INCTH, the retry operation is abnormal operation. That is, that is, it is determined that the payout operation of the game ball by the prize ball device 740 is in an abnormal state, the retry error flag RTERR-FLG is set to a value 1, and the payout ball seeing operation determination setting process is performed. In the setting of the output of the error state to the CR unit 6, for example, when the communication with the CR unit 6 is not performed, the logical state of the PRDY signal (LOW) indicating that the payout operation for paying out the rental ball is impossible Is set in the PRDY signal output setting information and stored in the CR communication information storage area.

As a result, in the CR communication process, the logical state of the PRDY signal is read from the CR communication information storage area and the PRDY signal is output from the predetermined output port of the payout control MPU 4120a at the next timer interrupt from the power recovery. To the CR unit 6. Thus, for example, immediately before the momentary power failure, if the payout operation of the game balls by the prize ball device 740 is in an abnormal state, the state is restored at the time of power recovery, so it is extremely effective after power recovery. At an early stage, a PRDY signal indicating that the payout operation for paying out a rental ball is impossible can be output to the CR unit 6 from the output terminal of a predetermined output port of the payout control MPU 4120a, and the CR unit 6 can be output. It is possible to notify that the payout operation of the game balls by the prize ball device 740 is in an abnormal state. Accordingly, it is possible to prevent the useless ball rental request signal BRDY from being output from the CR unit 6 at an extremely early stage after power recovery.

In the CR communication process, in the port input process of step S550, the CR connection signal is read from the input information storage area of the payout control internal RAM, and based on this CR connection signal, when the logic is HI, that is, a pachinko game. When the machine 1 is powered on and the payout control board 4110 and the CR unit 6 are electrically connected to each other through the game ball etc. lending device connection terminal plate 869, to pay out the ball In order to convey that the payout operation is possible, the logic state of the PRDY signal is set to HI and is output from the output terminal of the predetermined output port of the payout control MPU 4120a to the CR unit 6, while the logic is LOW, In other words, when the pachinko gaming machine 1 is powered on and the payout control board 4110 and the CR unit 6 are not electrically connected to each other via the game ball lending device connection terminal plate 869, In order to notify that the payout operation for paying out is impossible, the logic state of the PRDY signal is set to LOW and output to the CR unit 6 from the output terminal of a predetermined output port of the payout control MPU 4120a. The logical state of the EXS signal that indicates that one payout operation has started or ended is stored in the CR communication information storage area of the payout control internal RAM as EXS signal output setting information, and is stored in the payout control board 4110. A CR connection signal indicating whether or not the CR unit 6 is electrically connected is stored in the state information storage area as CR connection information.

Subsequent to step S554, the payout control program performs full tank and out-of-ball check processing (step S556). In the full tank and out-of-ball check process, the input information is read from the input information storage area described above, and the accommodation space of the foul cover unit 540 described above is stored based on the input information by the detection signal from the full tank switch 550. It is determined whether or not the game balls are full, and the number of balls of the game balls taken into the supply passage of the prize ball device 740 described above becomes a predetermined number or more by the detection signal from the ball break switch 750. Or not. For example, to determine whether or not the accommodation space of the foul cover unit 540 is filled with the game balls stored, the timer interruption period of 2 ms is used to determine whether or not the tank is full and a full-ball switch is performed in the out-of-ball check process. The detection signal from 550 is ON, and when the detection signal from the full tank switch 550 is OFF in the previous (2 ms before) full tank and out-of-ball check processing, that is, the detection signal from the full tank switch 550 is from ON to ON. When the state transitions to, the time counting of the full tank determination time (504 ms) described above is started in the timer updating process of step S552. When the full tank determination time becomes 0 in the timer update processing, that is, when the full tank determination time comes, whether the detection signal from the full tank switch 550 is ON in the full tank and out-of-ball check processing. Determine whether. In this determination, when the detection signal from the full tank switch 550 is ON, the full tank information indicating that the gaming space in which the accommodation space of the foul cover unit 540 is stored is full is stored as the status information storage described above. Store in the area. On the other hand, when the detection signal from the full tank switch 550 is OFF, full tank information indicating that the gaming space in which the accommodation space of the foul cover unit 540 is stored is not full is stored in the state information storage area. ..

The determination of whether or not the number of balls of the game balls taken into the supply passage of the prize ball device 740 is equal to or more than a predetermined number is also made by using the timer interruption cycle of 2 ms in the current full tank and out-of-ball check processing. When the detection signal from the ball break switch is ON, and the detection signal from the ball break switch is OFF due to the previous full (2 ms before) and ball break check processing, that is, the detection signal from the ball break switch 750 is ON from OFF. When the state transitions to, the time counting of the out-of-ball determination time (119 ms) described above is started in the timer updating process of step S552. Then, when the out-of-ball determination time becomes 0 in the timer update process, that is, when the out-of-ball determination time is reached, it is determined whether the detection signal from the out-of-ball switch 750 is ON in the full tank and out-of-ball check process. Determine whether. In this determination, when the detection signal from the out-of-ball switch 750 is ON, the out-of-ball information indicating that the number of game balls taken into the supply passage of the prize ball device 740 is equal to or more than a predetermined number is in the state. While the information is stored in the information storage area, when the detection signal from the out-of-ball switch 750 is OFF, the out-of-ball notification indicating that the number of game balls taken into the supply passage of the prize ball device 740 is not more than a predetermined number is sent out. Information is stored in the status information storage area.

Subsequent to step S556, the payout control program performs a launch ball sending control circuit error check process (step S557). In this launch ball sending control circuit error check processing, status information is acquired from the launch ball sending failure monitoring circuit 4120ah shown in FIG. 15 and it is determined whether or not there is a failure in the launch ball sending control circuit 4120ag. As described above, the launch ball delivery failure monitoring circuit 4120ah determines whether or not there is a failure in the launch ball delivery control circuit 4120ag that performs the launch control by the launch solenoid 654 and the ball delivery control by the ball delivery solenoid 585. The monitoring result (whether or not a failure has occurred) can be stored and held as status information. The payout control program acquires status information from the launch ball delivery failure monitoring circuit 4120ah and determines whether or not there is a failure in the launch ball delivery control circuit 4120ag. When the payout control program acquires the status information from the launch ball sending failure monitoring circuit 4120ah and determines that there is no failure in the launch ball sending control circuit 4120ag, it controls the launch of the game ball by the launch ball sending control circuit 4120ag. In order to start, the shooting operation permission is set to the shooting ball sending control circuit 4120ag, and the shooting operation permission information indicating that the shooting operation allowing state is stored in the state information storage area, while the shooting ball sending control circuit 4120ag is started. When it is determined that there is a problem with the, the shooting operation is set to prohibit the shooting ball sending control circuit 4120ag to forcibly stop the game ball shooting control by the shooting ball sending control circuit 4120ag, and the shooting operation is set. The firing operation prohibition information for notifying the operation prohibition state is stored in the state information storage area.

Following step S557, the payout control program performs a command reception process (step S558). In this command reception process, various commands related to payout from the main control board 4100 (the prize ball command and the self-check command shown in FIG. 44) are received. When the various commands are normally received, the payer ACK information to that effect is stored in the output information storage area described above. On the other hand, when the various commands cannot be received normally, the connection abnormality is transmitted to inform that the connection between the main control board 4100 and the payout control board 4110 is abnormal (various command signals are abnormal). The information is stored in the above-mentioned state information storage area.

Following step S558, the payout control program performs a command analysis process (step S560). In this command analysis processing, the command received in step S558 is analyzed, and the analyzed command is stored as received command information in the received command information storage area of the payout control internal RAM.

Following step S560, the payout control program performs a main operation setting process (step S562). In this main action setting process, action settings such as prize balls, ball rental, ball removal, and ball scooping are performed, retry actions are determined, and the number of unpaid balls (number of prize balls stock) is monitored. To do.

Subsequent to step S562, the payout control program performs an LED display data creation process (step S564). In this LED display data creation processing, various kinds of information are read from the above-mentioned state information storage area, display data to be displayed on the error LED indicator 860b of the payout control board 4110 is created, and the display data is stored in the above-mentioned output information storage area as LED display information. Remember. For example, when the above-mentioned ball-out information is read out from the state information storage area, and based on this ball-out information, when the number of balls in the game balls taken into the supply passage of the prize ball device 740 is not a predetermined number or more, corresponding display data is displayed. (In the present embodiment, the display value 1 (the number "1") is created and the LED display information is stored in the output information storage area.

Following step S564, the payout control program performs a command transmission process (step S566). In this command transmission processing, various kinds of information are read from the above-mentioned status information storage area, and various commands (frame status 1 command, error release navigation command and frame status) classified into the status display shown in FIG. 47 based on the various information. 2 command) is created and transmitted to the main control board 4100. For example, when the out-of-ball information is read from the state information storage area, based on this out-of-ball information, when the number of balls of the game balls taken into the supply passage of the prize ball device 740 is not equal to or more than the predetermined number, the frame state 1 command is issued. When it is created and transmitted to the main control board 4100, or when the firing operation permission information is read from the state information storage area, based on the firing operation permission information, the frame state 2 command (in order to inform that there is no launch ball sending control circuit error) B0 is set to B0) and transmitted to the main control board 4100, or when the firing operation prohibition information is read from the state information storage area, based on the firing operation prohibition information, the frame state 2 command ( A value of 1 is set in B0 in order to convey that there is an error in the firing ball sending control circuit) and the data is sent to the main control board 4100. Further, in the command transmission process, the payout control program has described that the payout RAM clear notification flag HRCL-FLG has the value 1, that is, the operation signal corresponding to the operation of the operation switch 860a is detected. Output the error clear navigation command.

Following step S566, the payout control program sets the value C in the watchdog timer clear register HWCL (step S568). By setting the value C in the watchdog timer clear register HWCL in step S568, the value C is set in the watchdog timer clear register HWCL following the value B set in step S546. As a result, the value A, the value B, and the value C are sequentially set in the watchdog timer clear register HWCL, and the watchdog timer is set to be cleared.

After step S568, the process returns to step S539 again, and the payout control program sets the value A in the watchdog timer clear register HWCL, and checks in step S540 whether the power outage notice signal (payout outage notice signal) is input. If it is determined that this power failure notice signal (payout power failure notice signal) is not input, it is determined in step S542 whether or not the 2 ms elapsed flag HT-FLG has a value of 1, and the 2 ms elapsed flag HT-FLG has a value of 1. If it is, that is, when 2 ms has elapsed, the value 0 is set in the 2 ms elapsed flag HT-FLG in step S544, the value B is set in the watchdog timer clear register HWCL in step S546, and port output processing is performed in step S548. , Step S550 performs port input processing, step S552 performs timer update processing, step S554 performs CR communication processing, step S556 performs full tank and out-of-ball check processing, and step S558 performs command reception processing. Command analysis processing is performed in step S560, main operation setting processing is performed in step S562, LED display data creation processing is performed in step S564, command transmission processing is performed in step S566, and a value is stored in the watchdog timer clear register HWCL in step S568. C is set, and steps S539 to S568 are repeated. The process of steps S539 to S568 is referred to as "payout control unit main process".

The processing content of the payout control unit main processing varies depending on the progress of the game by the main control board 4100. Therefore, the time required for the processing of the payout control MPU 4120a varies. Therefore, in the port output process of step S548, the payout control MPU 4120a preferentially outputs to the main control board 4100 a payer ACK signal indicating that various commands related to payout from the main control board 4100 have been normally received. There is. As a result, the payout control MPU 4120a secures the processing time so that the other processing that fluctuates can be sufficiently performed.

On the other hand, when the power failure notice signal (payout power failure notice signal) is input in step S540, the interrupt prohibition setting is performed (step S570). With this setting, the payout control unit timer interrupt process described later is not performed, writing to the payout control built-in RAM is prevented, and rewriting of the above-mentioned payout information is protected.

Following step S570, the payout control program stops the output of the drive signal to the payout motor 744 (step S574). Thereby, the payout of the game balls is stopped.

Subsequent to step S574, the payout control program sets clearing of the watchdog timer (step S576). The clear setting is performed by sequentially setting the value A, the value B, and the value C in the watchdog timer clear register HWCL, as described above.

Following step S576, the payout control program calculates the checksum and stores the calculated value (step S578). For this checksum, the payout information of the work area of the payout control internal RAM, excluding the storage area of the checksum value and the payout backup flag HBK-FLG value calculated in step S524, is calculated as a numerical value, and the total is calculated.

Following step S578, the payout control program sets a value 1 to the payout backup flag HBK-FLG (step S580). This completes the storage of the payout backup information.

Subsequent to step S580, the payout control program sets the prohibition of access to the payout control internal RAM (step S582). By this setting, access to the payout control built-in RAM is prohibited, writing and reading are disabled, and payout backup information stored in the payout control built-in RAM is protected.

Following step S582, the payout control program enters an infinite loop. In this infinite loop, the value A, the value B, and the value C are not sequentially set in the watchdog timer clear register HWCL, so that the watchdog timer is not cleared. Therefore, the payout control MPU 4120a is reset, and then the payout control program performs the payout control unit power-on process again under the control of the payout control MPU 4120a. The processing of steps S570 to S582 and the infinite loop are referred to as "payout control unit power-off processing".

The pachinko gaming machine 1 (payout control MPU 4120a) is reset when a power failure or momentary power failure occurs, and the payout control unit power-on process is performed by subsequent power recovery.

In step S526, it is checked whether or not the payout backup information stored in the payout control built-in RAM is normal, and in step S528, whether or not the payout control unit power-off process is normally ended. Are inspecting. In this way, by double checking the payout backup information stored in the payout control built-in RAM, it is inspected whether or not the payout backup information is stored due to an illegal act.

[17-2. Payment control unit timer interrupt processing]
Next, the payout control unit timer interrupt process will be described. This payout control unit timer interrupt process is repeatedly performed at every interrupt period (2 ms in the present embodiment) set in the payout control unit power-on process shown in FIGS.

When the payout control unit timer interrupt process is started, in the payout control unit 4120 of the payout control board 4110, the payout control program sets the timer interrupt to be prohibited as shown in FIG. 54 under the control of the payout control MPU 4120a. Registers are switched (saved) (step S590). Here, the general-purpose storage element (general-purpose register) used in the above-mentioned payout control unit main process is switched to the auxiliary register. By using this auxiliary register in the payout control unit timer interrupt processing, the value of the general-purpose register will not be overwritten. This prevents the destruction of the contents of the general-purpose register used in the payout control unit main processing.

Following step S590, the payout control program sets the value 1 to the 2 ms elapsed flag HT-FLG (step S592). The 2 ms elapsed flag HT-FLG is a flag for measuring 2 ms every time the payout control unit timer interrupt processing is performed, that is, every 2 ms. Each is set.

Following step S592, the payout control program switches (returns) the register (step S594). This return is switched from the auxiliary register used in the payout control unit timer interrupt process to the general-purpose storage element (general-purpose register). By using this general-purpose register in the main processing of the payout controller, the value of the auxiliary register is prevented from being overwritten. This prevents the destruction of the contents of the auxiliary register used in the payout control unit timer interrupt processing.

Subsequent to step S594, the payout control program sets interruption permission (step S596), and ends this routine.

[17-3. Rotation angle switch history creation process]
Next, the rotation angle switch history creation process will be described. In this rotation angle switch history creation processing, a history of detection signals from the rotation angle switch 752 shown in FIG. 15 is created.

When the rotation angle switch history creation processing is started, in the payout control unit 4120 of the payout control board 4110, the payout control program is controlled by the payout control internal RAM as shown in FIG. 55 under the control of the payout control MPU 4120a. The switch detection history information RSW-HIST is read (step S610). This rotation angle switch detection history information RSW-HIST is 1 byte (8 bits: most significant bit B7, B6, B5, B4, B3, B2, B1, least significant bit B0, "B" represents a bit). It has a storage capacity, and the history of the detection signal from the rotation angle switch 752 is stored as rotation angle switch detection history information RSW-HIST in the rotation angle switch history information storage area of the payout control built-in RAM. In step S610, the rotation angle switch detection history information RSW-HIST is read from the rotation angle switch history information storage area.

Following step S610, the payout control program determines whether or not there is a detection signal from the rotation angle switch 752 (step S612). This determination is performed based on the detection signal from the rotation angle switch 752 in the port input process of step S550 in the power-on process of the payout control unit (main process of payout control unit) shown in FIG. Specifically, the detection signal is stored as input information in the input information storage area of the payout control built-in RAM. In step S612, the input information is read from this input information storage area and it is determined whether or not there is a detection signal from the rotation angle switch 752. When there is a detection signal from the rotation angle switch 752 in the input information, the payout control program detects that the rotation angle of the rotation shaft of the payout motor 744 is transmitted to the detection slit of the rotation angle switch 752. It is determined that the axis has transitioned from the blocked state to the non-blocked state. On the other hand, when there is no detection signal from the rotation angle switch 752 in the input information, the payout control program determines that the detection slit has transitioned the optical axis of the rotation angle switch 752 from the non-blocking state to the blocking state.

When the detection slit is in a state where the optical axis of the rotation angle switch 752 is transited from the blocking state to the non-blocking state in step S612, the payout control program performs a shift process of the rotation angle switch detection history information (step S614). In this shift processing of the rotation angle switch detection history information, the rotation angle switch detection history information RSW-HIST read in step S610 is used as the most significant bits B7←B6, B6←B5, B5←B4, B4←B3, B3←B2. , B2←B1, B1←least significant bit B0, and so on, shifting one bit at a time from the least significant bit B0 to the most significant bit B7.

Following step S614, the payout control program sets the value 1 to the least significant bit B0 of the rotation angle switch detection history information RSW-HIST (step S616), and ends this routine.

On the other hand, when the detection slit is in the state where the optical axis of the rotation angle switch 752 is transited from the non-blocking state to the blocking state in step S612, the payout control program shifts the rotation angle switch detection history information (step S618). .. In the shift processing of the rotation angle switch detection history information, the payout control program performs the same processing as the shift processing of the rotation angle switch detection history information in step S614, and the rotation angle switch detection history information RSW-HIST read in step S610. The most significant bit B7 ← B6, B6 ← B5, B5 ← B4, B4 ← B3, B3 ← B2, B2 ← B1, B1 ← least significant bit B0, and so on from the least significant bit B0 to the most significant bit B7. Shift 1 bit at a time.

Following step S618, the payout control program sets the value 0 to the least significant bit B0 of the rotation angle switch detection history information RSW-HIST (step S620), and ends this routine.

As described above, every time the rotation angle switch history creation process is performed, the rotation angle switch detection history information RSW-HIST is shifted by one bit from the least significant bit B0 to the most significant bit B7, and then the detection slit is rotated. The value 1 or the least significant bit B0 is set to the least significant bit B0 depending on the state in which the optical axis of the angle switch 752 transits from the blocking state to the non-blocking state or the detection slit transitions the optical axis of the rotation angle switch 752 from the non-blocking state to the blocking state. Since the value 0 is set, the history of the detection signal from the rotation angle switch 752 can be created.

[17-4. Sprocket fixed position determination skip processing]
Next, the sprocket fixed position determination skip processing will be described. This sprocket fixed position determination skip processing skips the determination of whether or not the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted is in a fixed position when a predetermined condition is satisfied. Note that the fixed position determination of the payout rotating body is also performed when the payout of the game balls by the prize ball device 740 is completed. As a result, the rotation of the rotation shaft of the payout motor 744 can be reliably started in the state where no ball is generated.

When the sprocket fixed position determination skip processing is started, in the payout control unit 4120 of the payout control board 4110, the payout control program is under the control of the payout control MPU 4120a, as shown in FIG. 56, the fixed position determination skip flag SKP-. It is determined whether FLG has a value of 0 (step S630). The fixed position determination skip flag SKP-FLG is a flag indicating whether or not to perform the fixed position determination of the payout rotating body, and when the fixed position determination of the payout rotating body is not performed (when skipping), the payout rotation is 1. The value is set to 0 when the body position determination is performed (when not skipped).

In step S630, when the fixed position determination skip flag SKP-FLG has a value of 0 (when not skipped), that is, when the fixed position determination of the payout rotating body is performed, the payout control program causes the rotation angle switch history information of the payout control built-in RAM. The rotation angle switch detection history information RSW-HIST is read from the storage area (step S632), and it is determined whether or not it matches the fixed position determination value (step S634). This fixed position determination value is stored in the payout built-in ROM, and is “00001111B (“B” represents a bit.”” in the present embodiment, and B7 to B4 of the upper 4 bits have a value of 0 and the lower 4 are. Bits B3 to B0 have a value of 1. In the determination of step S634, it is determined whether the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST and the lower 4 bits B3 to B0 of the fixed position determination value match.

Here, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST have the value 1, the above-mentioned detection slit is the optical axis of the rotation angle switch 752 continuously in four timer interrupt cycles. Means that the state has been changed from the cutoff state to the non-blocking state. When the timer interrupt cycle is generated four times, the payout motor 744 shown in FIG. 15 is rotated by four steps. The rotation of the payout motor 744 is the rotation of the payout rotating body of the rotation detection board via the first gear, the second gear, and the third gear. Since the first gear, the second gear, and the third gear have play (backlash), the payout rotating body rotates clockwise or counterclockwise, but the backlash causes the payout rotating body to rotate. Since the rotation is designed to correspond to the rotation of the payout motor 744 in about two steps, in the present embodiment, when the fixed position determination of the payout rotating body is performed, the rotation angle switch 752 is operated. The detection signal history, the rotation angle switch detection history information RSW-HIST is created by the rotation angle switch history creation processing shown in FIG. 55, and the lower 4 bits B3 to B0 of the created rotation angle switch detection history information RSW-HIST, that is, This is performed based on the detection signal from the rotation angle switch 752 generated by the latest four timer interrupt cycles. As a result, in the four timer interrupt cycles, the payout motor 744 is rotated by four steps, and therefore the rotation is larger than the rotation of the payout rotor due to the backlash, and the rotation of the payout rotor due to the backlash is absorbed. You can Therefore, it is possible to prevent erroneous detection of the fixed position of the payout rotating body due to backlash, so that the rotational position of the payout rotating body can be correctly managed by the rotational position of the payout motor 744. In the present embodiment, the four timer interrupt cycles are 8 ms (=2 ms×4 times), which is set as the backlash absorption time.

In step S634, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S632 and the lower 4 bits B3 to B0 of the fixed position determination value match, the payout control program is The fixed position determination skip flag SKP-FLG is set to the value 1 (step S636). Accordingly, it is possible to set not to perform (skip) the fixed position determination of the payout rotating body. The payout control MPU 4120a sets the rotational position of the payout rotating body in step S636 to the fixed position of the payout rotating body.

Following step S636, the payout control program sets the skip determination time to valid (step S638), and ends this routine. Here, the number of detection slits is three, which is the same number as the concave portions of the payout rotating body, and is formed at equal intervals (every 120 degrees) on the outer periphery of the rotation detection plate. Further, as described above, the rotation of the payout motor 744 is the rotation of the payout rotating body of the rotation detection board via the first gear, the second gear, and the third gear. In the present embodiment, the rotation between the respective detection slits (120 degrees) of the rotation detection board (dispensing rotor) is designed to correspond to the rotation of the dispensing motor 744 in 18 steps.

The payout control program manages the rotational position of the payout rotating body based on the number of steps of the payout motor 744 under the control of the payout control MPU 4120a. Specifically, (1) a transition state (referred to as an “edge detection state”) in which the detection slit causes the optical axis of the rotation angle switch 752 to transition from a blocking state to a non-blocking state, and (2) the detection slit has a rotation angle. A state in which the optical axis of the switch 752 transits from the blocking state to the non-blocking state (referred to as “fixed position confirmation state”), and (3) the detection slit transits the optical axis of the rotation angle switch 752 from the non-blocking state to the blocking state. The state is managed in three states, that is, a state (“fixed position determination skip state”). The edge detection state of (1) corresponds to one step rotation of the payout motor 744, the fixed position confirmation state of (2) corresponds to four rotations of the payout motor 744, and the fixed position determination skip state of (3). Corresponds to the rotation of the payout motor 744 in 13 steps, and the rotation position between the detection slits (120 degrees) of the rotation detection plate, that is, the rotation position of the payout rotating body is managed by a total of 18 rotations.

In the fixed position determination skip state of (3), since the detection slit is a state in which the optical axis of the rotation angle switch 752 has transited from the non-blocking state to the blocking state, the skip determination time is the time for rotating the payout motor 744 by 13 steps. Is set. As described above, since the timer interrupt period is set to 2 ms, the skip determination time is 26 ms (=2 ms×13 steps).

When the skip determination time becomes valid in step S638, the skip determination time is subtracted in the timer updating process of step S552 in the payout control unit power-on process (payout control unit main process) shown in FIG. The payout control MPU 4120a subtracts the skip determination time, and when the result of the subtraction is 0, the fixed position determination skip flag SKP-FLG is set to the initial value 0.

On the other hand, when the fixed position determination skip flag SKP-FLG is not 0 (value 1) in step S630 (when skipped), that is, when the fixed position determination of the payout rotating body is not performed, or in step S634, step S632. When the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step 3 and the lower 4 bits B3 to B0 of the fixed position determination value do not match, the payout control program directly ends this routine. .. The fixed position determination skip flag SKP-FLG set in step S636 is stored in the general-purpose storage element (general-purpose register) of the payout control MPU 4120a.

The game balls supplied from the pachinko island facility are stored in the prize ball tank 720 and the tank rail 731, taken into the supply passage of the prize ball device 740, and guided to the prize ball device 740. When the game balls are rubbed against each other and charged, they are electrostatically discharged and generate noise. For this reason, the prize ball device 740 is easily affected by noise and is in an environment. A rotation angle switch substrate 753 of the prize ball device 740 shown in FIG. 3 is provided with a rotation angle switch 752, and a detection signal from the rotation angle switch 752 is affected by noise due to electrostatic discharge of the game ball. Cheap. Further, the wiring (harness) connecting between the payout control board 4110 and the prize ball case inside board 754 in the prize ball device 740 shown in FIG. 3 is also affected by noise due to electrostatic discharge of the game balls. Cheap.

Therefore, in the present embodiment, in order to suppress erroneous detection due to the influence of noise, the above-described (3) fixed position determination skip state, that is, the detection slit changes the optical axis of the rotation angle switch 752 from the non-blocking state to the blocking state. In the transitioned state, the fixed position determination of the payout rotating body is not performed. This improves the accuracy of the fixed position determination of the payout rotating body. The cycle and period required to detect the fixed position of the payout rotating body can be calculated in advance as described above, and therefore the skip determination time can be easily set and adjusted.

[17-5. Ball Judgment Processing]
Next, the ball gaze determination processing will be described. In the ball-blurring determination process, it is determined whether or not the ball-blurred state due to the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted.

When the ball head determination process is started, the payout control MPU 4120a of the payout control unit 4120 of the payout control board 4110 causes the rotation angle switch history information storage area of the above-described payout control RAM to rotate from the rotation angle as shown in FIG. The switch detection history information RSW-HIST is read (step S640).

Following step S640, the payout control program determines whether or not there is a detection signal from the above-described rotation angle switch 752 (step S642). This determination determines whether or not the rotation angle switch detection history information RSW-HIST read in step S640 matches the fixed position determination value. As described above, this fixed position determination value is stored in the payout built-in ROM, and in the present embodiment, it is “000011111B (“B” represents a bit.)”, and the upper 4 bits B7 to B4. The value 0 and the lower 4 bits B3 to B0 are the value 1. In the determination of step S642, it is determined whether the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST and the lower 4 bits B3 to B0 of the fixed position determination value match.

In step S642, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S640 and the lower 4 bits B3 to B0 of the fixed position determination value match, the payout control program If the detection slit is in a state in which the optical axis of the rotation angle switch 752 is transited from the non-blocking state to the blocking state, that is, the payout rotating body is rotating, and the ball-bulging state does not occur, this routine is finished as it is. To do.

On the other hand, in step S642, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S640 do not match the lower 4 bits B3 to B0 of the fixed position determination value, the ball is seen. The value 1 is set to the medium flag PBE-FLG (step S644). The in-ball bleeding flag PBE-FLG is a flag indicating whether or not the out-of-ball state due to the payout rotating body has occurred, and is 1 when the payout motor 744 is performing an overturning operation. The value is set to 0 when no operation is performed.

Following step S644, the payout control program sets the ball entrainment determination time to valid (step S646), and ends this routine. When the ball gaze determination time becomes valid, the ball gaze determination time is subtracted in the timer updating process of step S552 in the payout control unit power-on process (payout control unit main process) shown in FIG. ..

[17-6. Various prize ball stock number addition processing]
Next, a process for adding various prize ball stock numbers will be described. The various prize ball stock number addition processing includes a prize ball stock number addition processing and a ball rental prize ball stock number addition processing. The prize ball stock number addition processing is performed from the main control board 4100. This is a process of adding the number of balls to be paid out based on a prize ball command, which will be described later. The process of adding the number of prize ball stock for ball rental is a process of adding the number of balls to be paid out based on a ball rental request signal from the CR unit 6. is there. First, the award ball stock number addition process for prize balls will be described, and subsequently, the award ball stock number addition process for ball rental will be described. In this embodiment, the award ball stock number addition process for award balls is set to be preferentially performed, and the award ball stock number addition process according to the award ball stock number addition process for an award ball is performed according to the number. After the game balls are paid out by the prize ball device 740, it is set to perform the prize ball stock number addition processing for ball rental.

[17-6-1. Prize ball stock number addition process for prize balls]
When the prize ball stock number addition processing for prize balls is started, in the payout control unit 4120 of the payout control board 4110, as shown in FIG. 58, the payout control program is controlled by the payout control MPU 4120a. It is determined whether there is any (step S650). This determination is performed based on the command analyzed in the command analysis process of step S560 in the payout control unit power-on process (payout control unit main process) shown in FIG. Specifically, the analyzed command is stored as received command information in the received command information storage area of the payout control built-in RAM. In step S650, the payout control program reads the received command information from the received command information storage area and determines whether the command is a prize ball command.

When the received command information is not the prize ball command in step S650, the payout control program ends this routine as it is, while when the received command information is the prize ball command in step S650, the payout control program changes to this prize ball command. The corresponding prize ball number PBV is read from the prize ball number information table (step S652). The award ball number information table, which will be described in detail later, is an information table stored in advance in the payout built-in ROM in association with the award ball command and the award ball number PBV.

Following step S652, the payout control program reads out the prize ball stock number PBS from the payout control internal RAM (step S654). The prize ball stock number PBS represents the number of game balls not yet paid out by the prize ball device 740, that is, the number of unpaid balls, and has a storage capacity of 2 bytes (16 bits) in the present embodiment. ing. As a result, the award ball stock number PBS can store the number of unpaid balls from the value 0 to the value 32767. The prize ball stock number PBS is stored in the prize ball information storage area of the payout control built-in RAM. In step S652, the prize ball stock number PBS is read from the prize ball information storage area.

The payout control program adds the prize ball number PBV read in step S652 to the prize ball stock number PBS read in step S654 (step S656), and ends this routine. Note that the prize ball command read out in step S650 after addition in step S656 is deleted from the received command information storage area.

[17-6-2. Addition processing for the number of award balls for ball rental]
Next, the award ball stock number addition process for renting a ball will be described. When the award ball stock number addition process for ball rental is started, in the payout control unit 4120 of the payout control board 4110, the payout control program is under the control of the payout control MPU 4120a, as shown in FIG. It is determined whether or not there is a signal (step S660). This determination is performed based on the ball rental request signal from the CR unit 6 in the port input process of step S550 in the payout control unit power-on process (payout control unit main process) shown in FIG. Specifically, the ball rental request signal is stored as input information in the input information storage area of the payout control built-in RAM. In step S660, the payout control program reads the input information from the input information storage area and determines whether or not there is a ball rental request signal.

When there is no ball-renting request signal in step S660, the payout control program terminates this routine as it is, while when there is a ball-renting request signal in step S660, the payout control program determines the prize ball information of the above-mentioned payout control RAM. The prize ball stock number PBS is read from the storage area (step S662), the number of lent balls RBV is added to the prize ball stock number PBS (step S664), and this routine is ended. The number of rented balls RBV is a fixed value and is stored in advance in the payout built-in ROM. In the present embodiment, the value 25 is set as the number of rented balls RBV. After the addition in step S664, the payout control program erases the ball rental request signal read in step S660 from the input information storage area. Further, in the present embodiment, since the award ball is prioritized (the award ball and the ball rental are distinguished and managed), the ball rental request signal is held even when there is a ball rental request signal. The payout of balls will be made upon completion of the payout of prize balls. Therefore, in the present embodiment, the payout of the ball to be paid is performed after the prize ball stock number PBS becomes 0.

[17-7. Stock monitoring process]
Next, the stock monitoring process will be described. In this stock monitoring process, it is monitored whether the player is continuing the game while the game is being performed in a state where the accommodation space of the foul cover unit 540 shown in FIG. It is a process to do.

When the stock monitoring process is started, in the payout control unit 4120 of the payout control board 4110, the payout control program is under the control of the payout control MPU 4120a, as shown in FIG. The prize ball stock number PBS is read from the storage area (step S670), and it is determined whether the read prize ball stock number PBS is equal to or greater than the caution threshold TH (step S672). The cautionary threshold value TH is a fixed value and is stored in advance in the payout built-in ROM. In this embodiment, the value 50 is set as the cautionary threshold value TH.

When the prize ball stock number PBS is equal to or greater than the caution threshold value TH in step S672, the payout control program sets the caution flag CA-FLG to the value 1 (step S674), and ends this routine. This caution flag CA-FLG indicates that the player has started stocking game balls in the accommodation space of the foul cover unit 540, and the number of unpaid game balls (the above-mentioned number of prize ball stocks) exceeds the caution threshold TH. It is a flag indicating that it has been reached, and is set to a value of 1 when it has reached the caution threshold TH or higher, and to a value of 0 when it has not reached the caution threshold TH or higher.

On the other hand, when the prize ball stock number PBS is less than the caution threshold value TH in step S672, the payout control program sets the caution flag CA-FLG to the value 0 (step S676), and ends this routine.

When the game state is a big hit and the player is relaxing and paying attention to the effect unfolded on the game board side effect display unit 1900 shown in FIG. 17, the player inadvertently wins the prize ball for one round. There is a case where the game ball dispensed as is not operated by operating the lower plate ball removing button 354 from the lower plate 302 shown in FIG. When the game is continued in this state, the lower plate 302 is filled with the game balls, and the game balls are collected in the accommodation space of the foul cover unit 540. When the accommodation space of the foul cover unit 540 is filled with game balls, as described above, the value of the prize ball stock number PBS increases and becomes equal to or greater than the caution threshold value TH, and each decoration of the door frame 5 as a caution effect. Among the boards, a plurality of LEDs (decorative LEDs) provided on each of the plurality of frame-side peripheral control MPU control target decorative boards that are controlled by the peripheral control MPU 4150a directly blink. By this blinking, it is possible to inform the clerk of the hall that the player is paying attention to the game. Thereby, the clerk of the hall can inform the player that the game ball is removed from the lower plate 302, and the player can fill the lower plate 302 (the accommodation space of the foul cover unit 540) with the game ball. It is possible to prevent the game from continuing.

In the present embodiment, the cautionary threshold value TH is set to a value 50, which is approximately one fifth of the upper limit value 255 that can be represented by 1 byte (8 bits). As a result, it is possible to notify the clerk of the hall that the player should pay attention to the game at the earliest possible stage.

[17-8. Dispensing Ball Gaze Movement Judgment Setting Process]
Next, the payout ball tilting motion determination setting process will be described. This payout ball gaze operation determination setting process is to pay out the game ball with the payout motor 744 to the upper plate 301 and the lower plate 302 shown in FIG. 7, perform a ball gaze motion, or such a payout. It is a process of setting whether to discharge or not to discharge.

When the pay-out ball gaze operation determination setting process is started, in the pay-out control unit 4120 of the pay-out control board 4110, the pay-out control program is under the control of the pay-out control MPU 4120a, as shown in FIG. The rotation angle switch detection history information RSW-HIST is read from the rotation angle switch history information storage area of the RAM (step S680).

Subsequent to step S680, the payout control program determines whether or not there is a detection signal from the rotation angle switch 752 shown in FIG. 15 (step S682). This determination determines whether or not the rotation angle switch detection history information RSW-HIST read in step S680 matches the fixed position determination value. As described above, this fixed position determination value is stored in the payout built-in ROM, and in the present embodiment, it is “000011111B (“B” represents a bit.)”, and the upper 4 bits B7 to B4. The value 0 and the lower 4 bits B3 to B0 are the value 1. In the determination of step S682, it is determined whether the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST and the lower 4 bits B3 to B0 of the fixed position determination value match.

In step S682, the payout control program, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S680 and the lower 4 bits B3 to B0 of the fixed position determination value match, It is determined whether or not the retry error flag RTERR-FLG is 1 (step S684). The retry error flag RTERR-FLG is a flag indicating whether or not a retry operation described later is abnormally operating, and has a value of 1 when the retry operation is abnormally operating and a value when the retry operation is not abnormally operating (retry The value is set to 0 when the operation is operating normally.

In step S682, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S680 do not match the lower 4 bits B3 to B0 of the fixed position determination value, or in step S684. , When the retry error flag RTERR-FLG is not 1 (value 0), that is, when the retry operation is not abnormal, the payout control program determines whether or not the in-bulb flag PBE-FLG has a value of 1. It is determined (step S686). The in-bulb flag PBE-FLG is a flag that indicates whether or not a bulging state due to a payout rotating body to which the rotation of the rotating shaft of the payout motor 744 is transmitted is generated, and the payout motor 744 causes the bulging in the ball. The value is set to 1 when the motion is performed, and the value is set to 0 when the ball glancing motion is not performed.

In step S686, when the in-bulb flag PEB-FLG is not 1 (value is 0), that is, when the inclining movement is not performed, the payout control program stores the prize ball information storage in the payout control internal RAM described above. The prize ball stock number PBS is read from the area (step S688), and it is determined whether or not the read prize ball stock number PBS is larger than 0 (step S690). In this determination, it is determined whether or not there are unpaid balls in the payout of game balls by the payout motor 744.

When the prize ball stock number PBS is larger than the value 0 in step S690, that is, when there is an unpaid ball number, the payout control program determines whether or not the accommodation space of the foul cover unit 540 is full of game balls. It is determined whether or not (step S692). This determination is performed on the basis of the full tank information and the full tank information stored in the out-of-ball check processing of step S556 in the power-on processing of the payout control unit (main processing of the payout control unit) illustrated in FIG. 53. Specifically, the full tank information is stored in the state information storage area of the payout control built-in RAM described above. In step S692, full tank information is read from this state information storage area and it is determined whether or not the game space in which the accommodation space of the foul cover unit 540 is stored is full.

When the accommodation space of the foul cover unit 540 is not full in the stored game balls in step S692, the payout control program performs a payout setting process described later (step S694), and this routine ends. In this payout setting process, a payout operation for paying out game balls to the upper plate 301 and the lower plate 302 is performed.

On the other hand, when the storage space of the foul cover unit 540 is full in the stored game balls in step S692, the payout control program ends this routine as it is. In the pachinko gaming machine 1 of the present embodiment, when the storage space of the foul cover unit 540 is filled with the stored game balls, the payout motor 744 is forcibly stopped. When prize balls are generated while the payout motor 744 is forcibly stopped, the number of unpaid balls by the payout motor 744 increases, and the prize ball stock number PBS is added by the prize ball stock number addition processing for prize balls shown in FIG. Will increase.

On the other hand, when the prize ball stock number PBS is not greater than the value 0 (value 0) in step S690, that is, when there is no unpaid number of balls, the payout control program ends this routine as it is. As a result, the game balls are not paid out.

On the other hand, in step S686, when the flag PBE-FLG is in the ball tilting state, that is, when the ball tilting motion is performed, the payout control program performs a ball tilting motion setting process described later (step S700), and this routine To finish. In the ball-bending operation setting process, a ball-bending operation for eliminating the ball-bending state by the payout rotating body of the prize ball device 740 is performed.

On the other hand, in step S684, when the retry error flag RTERR-FLG has a value of 1, that is, when the retry operation is abnormally performed, the payout control program sets the output stop (stop) of the drive signal to the payout motor 744. Yes (step S702). In this setting, drive information for stopping the drive signal is set in the payout motor 744 and stored in the output information storage area of the above-described payout control RAM.

Subsequent to step S702, the payout control program sets the output of the error state to the CR unit 6 (step S704), and ends this routine. In step S704, when the payout control program is not communicating with the CR unit 6 under the control of the payout control MPU 4120a in order to notify the CR unit 6 that the ball lending is not possible (CR unit 6). (When the logic of BRDY from is LOW, that is, when it is held after falling), the logic of the PRDY signal is kept LOW, that is, the state of falling is set, and the logic state of the PRDY signal is set in the PRDY signal output setting information. Then, it is stored in the CR communication information storage area. Thereby, in the CR communication process of step S554 in the payout control unit main process of the payout control unit power-on process of FIG. 53, the PRDY signal output setting information is read from the CR communication information storage area stored in the payout control built-in RAM. The PRDY signal output setting information read out from the lever, that is, the PRDY signal whose logic is LOW, is CR from the output terminal of the predetermined output port of the payout control MPU 4120a of the payout control unit 4120 via the game ball lending device connection terminal board 869. Output to unit 6. On the other hand, when communicating with the CR unit 6 (when the logic of BRDY from the CR unit 6 is HI, that is, when the logic is rising and held), the logic state of the EXS signal is maintained and the logic state of the EXS signal is maintained. Is set in the EXS signal output setting information and stored in the CR communication information storage area. As a result, the EXS signal output setting information is read from the CR communication information storage area stored in the payout control RAM in the CR communication process of step S554 in the payout control unit main process of the payout control unit power-on process of FIG. The read EXS signal output setting information, that is, the EXS signal whose logic is maintained, is output from the output terminal of the predetermined output port of the payout control MPU 4120a to the CR unit 6 through the game ball lending device connection terminal board 869. .. It should be noted that “maintaining the logic state of the EXS signal” means that when the logic of the EXS signal is LOW (the EXS signal falls and is held), the logic LOW is maintained, and the logic of the EXS signal is HI. At some time (the EXS signal is held rising), it is to maintain its logic HI.

[17-8-1. Payment setting process]
Next, the payout setting process will be described. In the payout setting process, the payout motor 744 is driven to set the payout of game balls.

When the payout setting process is started, in the payout control unit 4120 of the payout control board 4110, the payout control program sets the drive command number DRV from the payout control internal RAM as shown in FIG. 62 under the control of the payout control MPU 4120a. It is read (step S710). The drive command number DRV commands the number of game balls to be paid out by the payout motor 744, and has the same value as the prize ball stock number PBS. The drive command number DRV is stored in the prize ball information storage area of the payout control built-in RAM. In step S710, the drive command number DRV is read from the prize ball information storage area.

Following step S710, the payout control program determines whether or not the drive command number DRV is 0 (step S712). This determination is made based on the drive command number DRV as to whether or not the number of game balls to be paid out by the payout motor 744 remains.

When the drive command number DRV is 0 in step S712, that is, when the number of game balls to be paid out by the payout motor 744 is zero, the payout control program stops the output of the drive signal to the payout motor 744 (stop). ) Is set (step S714). In this setting, drive information for stopping the drive signal is set in the payout motor 744 and is stored in the output information storage area of the above-described payout control built-in RAM.

Following step S714, the payout control program reads the prize ball stock number PBS from the prize ball information storage area of the payout control internal RAM (step S716), and reads the actual ball count PB (step S718). The actual ball count PB is a count of the number of game balls actually paid out by the payout motor 744. This count will be described later in detail, but in the port input process of step S550 in the payout control unit power-on process (payout control unit main process) shown in FIG. Based on the detection signal. The actual ball count PB is stored in the prize ball information storage area of the payout control built-in RAM. In step S718, the actual sphere count PB is read from the prize sphere information storage area.

Subsequent to step S718, the payout control program sets a value obtained by subtracting the actual ball count PB read in step S718 from the prize ball stock number PBS read in step S716 to the prize ball stock number PBS and the drive command number DRV. (Step S720), the value 0 is set to the actual ball count PB (step S722), and this routine is ended. When the drive command number DRV and the actual ball count PB are 0, in step S722, the value of the prize ball stock number PBS read in step S716 is directly set as the drive command number DRV.

On the other hand, when the drive command number DRV is not 0 in step S712, that is, when the payout motor 744 has the number of game balls to be paid out, the payout control program sets the output of the drive signal to the payout motor 744. (Step S724). With this setting, drive information for stopping the drive signal is set in the payout motor 744 and stored in the output information storage area of the payout control internal RAM.

Following step S724, the payout control program subtracts 1 from the drive command number DRV (decrements, step S726), and determines whether or not there is a detection signal from the counting switch 751 (step S728). This determination is performed based on the detection signal from the counting switch 751 in the port input process of step S550 in the power-on process of the payout control unit (main process of payout control unit) shown in FIG. Specifically, the detection signal is stored as input information in the input information storage area of the payout control built-in RAM. In step S728, the payout control program reads the input information from the input information storage area and determines whether or not there is a detection signal from the counting switch 751.

When there is a detection signal from the counting switch 751 in step S728, the payout control program adds the value 1 to the actual ball count PB (increments, step S730), and ends this routine. The actual ball count PB is incremented by incrementing the actual ball count PB in step S730.

On the other hand, when there is no detection signal from the counting switch 751 in step S728, the payout control program ends this routine as it is. In this way, the payout control program is a case where the drive command number DRV is decremented in step S726 under the control of the payout control MPU 4120a, and when there is no detection signal from the counting switch 751 in the determination in step S728, that is, the actual When the ball count PB is not incremented, one game ball cannot be paid out because the game ball was not received in the recess of the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted. to decide. Therefore, the payout control program sets a value obtained by subtracting the actual ball count PB from the prize ball stock number PBS to the drive command number DRV in step S720 described above in order to pay out the one ball to be paid out again. Accordingly, when there is no detection signal from the counting switch 751 in the determination of step S728, that is, when the actual ball count PB is not incremented, the value 1 which is one ball to be paid out can be included in the prize ball stock number PBS. In other words, in other words, the value 1 which is the one ball to be paid out can be rounded up to the prize ball stock number PBS, so that the retry operation for paying out the one ball to be paid out again can be performed. By performing this retry operation, it is possible to extremely reduce the possibility that the game ball will not be paid out to the player, and it is possible to prevent the disadvantage of the player due to the unpaid game ball.

[17-8-2. Sphere movement setting process]
Next, the ball-bending motion setting process will be described. The ball-bending operation setting process is a process of setting to eliminate the ball-bending state by the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 of the prize ball device 740 is transmitted.

When the ball gaze operation setting process is started, in the payout control unit 4120 of the payout control board 4110, the payout control program causes the ball gaze judgment time to elapse as shown in FIG. 63 under the control of the payout control MPU 4120a. It is determined whether or not (step S750). This determination is performed on the basis of the ball deviation determination time subtracted in the timer updating process of step S552 in the power-on process of the payout control unit (main process of payout control unit) shown in FIG. Specifically, the ball gaze determination time is stored as time management information in the time management information storage area of the payout control built-in RAM described above. In step S750, the time management information is read from this time management information storage area and it is determined whether or not the ball-bending determination time has elapsed.

When the ball deflection determination time has not elapsed in step S750, the payout control program reads the rotation angle switch detection history information RSW-HIST from the rotation angle switch history information storage area of the above-described payout control built-in RAM (step S752). ..

Subsequent to step S752, the payout control program determines whether or not there is a detection signal from the above-described rotation angle switch 752 (step S754). In this determination, it is determined whether or not the rotation angle switch detection history information RSW-HIST read in step S752 matches the fixed position determination value. As described above, this fixed position determination value is stored in the payout built-in ROM, and in the present embodiment, it is “000011111B (“B” represents a bit.)”, and the upper 4 bits B7 to B4. The value 0 and the lower 4 bits B3 to B0 are the value 1. In the determination of step S754, it is determined whether or not the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST and the lower 4 bits B3 to B0 of the fixed position determination value match.

In step S754, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S752 do not match the lower 4 bits B3 to B0 of the fixed position determination value, the payout control program is The output of the drive signal to the dispensing motor 744 is set so as to perform the ball-bending operation (step S756), and this routine is ended. In this setting, drive information for outputting a drive signal to the payout motor 744 is set and stored in the output information storage area of the above-described payout control RAM.

On the other hand, in step S754, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S752 match the lower 4 bits B3 to B0 of the fixed position determination value, the payout control program Sets the stop of the drive signal to the payout motor 744 (step S758). With this setting, drive information for stopping the drive signal is set in the payout motor 744 and stored in the output information storage area of the payout control internal RAM.

Subsequent to step S758, the payout control program sets a value 0 to the in-ball entrainment flag PBE-FLG as the end of the ball entangling operation (step S760), and ends this routine. The in-ball bleeding flag PBE-FLG is a flag indicating whether or not the out-of-ball state due to the payout rotating body has occurred, and is 1 when the payout motor 744 is performing an overturning operation. When no motion is performed (end of the ball-bending motion), the value is set to 0.

On the other hand, when the ball entrainment determination time has elapsed in step S750, the payout control program sets stop of the drive signal to the payout motor 744 (step S762). In this setting, drive information for stopping the drive signal is set in the payout motor 744 and stored in the output information storage area of the payout control built-in RAM.

Following step S762, the payout control program sets the output of the error state to the CR unit 6 (step S764). Here, in order to notify the CR unit 6 that the ball lending is not possible, the payout control MPU 4120a is not communicating with the CR unit 6 (the BRDY logic from the CR unit 6 is LOW, that is, (When falling and held), the logic of the PRDY signal is set to LOW, that is, the lowered state is held, and the logic state of the PRDY signal is set in the PRDY signal output setting information and stored in the CR communication information storage area. To do. Thereby, in the CR communication process of step S554 in the payout control unit main process of the payout control unit power-on process of FIG. 53, the PRDY signal output setting information is read from the CR communication information storage area stored in the payout control built-in RAM. The PRDY signal output setting information read out from the lever, that is, the PRDY signal whose logic is LOW, is CR from the output terminal of the predetermined output port of the payout control MPU 4120a of the payout control unit 4120 via the game ball lending device connection terminal board 869. Output to unit 6. On the other hand, when communicating with the CR unit 6 (when the logic of BRDY from the CR unit 6 is HI, that is, when the logic is rising and held), the logic state of the EXS signal is maintained and the logic state of the EXS signal is maintained. Is set in the EXS signal output setting information and stored in the CR communication information storage area. As a result, the EXS signal output setting information is read from the CR communication information storage area stored in the payout control RAM in the CR communication process of step S554 in the payout control unit main process of the payout control unit power-on process of FIG. The read EXS signal output setting information, that is, the EXS signal whose logic is maintained, is output from the output terminal of the predetermined output port of the payout control MPU 4120a to the CR unit 6 through the game ball lending device connection terminal board 869. .. Note that "maintaining the logic state of the EXS signal" means that the logic LOW is maintained when the logic of the EXS signal is LOW (the EXS signal falls and is held) as described above, and the EXS signal is maintained. Is HI (the EXS signal is held rising), that logic HI is maintained.

Subsequent to step S764, the payout control program sets a value 0 to the in-ball entrainment flag PBE-FLG as the end of the ball entangling operation (step S766), and ends this routine.

[17-9. Retry operation monitoring process]
Next, the retry operation monitoring process will be described. In this retry operation monitoring process, it is a process of monitoring whether or not the retry operation for paying out the game ball to be paid out again is normally performed.

When the retry operation monitoring process is started, in the payout control unit 4120 of the payout control board 4110, the payout control program, under the control of the payout control MPU 4120a, as shown in FIG. 64, the rotation angle of the payout control built-in RAM described above. The rotation angle switch detection history information RSW-HIST is read from the switch history information storage area (step S770).

Following step S770, the payout control program determines whether or not there is a detection signal from the above-described rotation angle switch 752 (step S772). This determination determines whether or not the rotation angle switch detection history information RSW-HIST read in step S770 matches the fixed position determination value. As described above, the fixed position determination value is stored in the payout control built-in ROM, and is “000011111B (“B” represents a bit.)” in the present embodiment, and the upper four bits B7 to B4. Has a value of 0, and the lower 4 bits B3 to B0 have a value of 1. In the determination of step S772, it is determined whether the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST and the lower 4 bits B3 to B0 of the fixed position determination value match.

In step S772, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S770 and the lower 4 bits B3 to B0 of the fixed position determination value match, the payout control program is The value 1 is added to the mismatch counter INCC (increment, step S774). This inconsistency counter INCC, the number of balls of the game ball which is received in the concave portion of the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted, and the number of balls detected by the counting switch 751, Is a counter for calculating the difference, and usually, the number of balls of the game ball received and paid out in the recess of the payout rotating body and the number of balls detected by the counting switch 751 match. , The value becomes 0. The payout control program performs a retry operation in the payout setting process shown in FIG. 62. Therefore, by this retry operation, the number of balls of the game balls received by the recess of the payout rotating body and paid out, and the actual counting switch The number of balls detected in 751 and the discontinuity of the game balls due to the disagreement with each other are paid out, and it is determined by monitoring the inconsistency counter INCC. The inconsistency counter INCC is stored in the prize ball information storage area of the payout control built-in RAM. In step S774, the payout control program increments the inconsistency counter INCC stored in the prize ball information storage area.

Following step S774 or in step S772, the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S770 do not match the lower 4 bits B3 to B0 of the fixed position determination value. Sometimes, the payout control program determines whether or not there is a detection signal from the counting switch 751 (step S776). This determination is performed based on the detection signal from the counting switch 751 in the port input process of step S550 in the power-on process of the payout control unit (main process of payout control unit) shown in FIG. Specifically, as described above, the detection signal is stored as input information in the input information storage area of the payout control built-in RAM described above. In step S776, the payout control program reads the input information from the input information storage area and determines whether or not there is a detection signal from the counting switch 751.

When there is a detection signal from the counting switch 751 in step S776, the payout control program subtracts 1 from the inconsistency counter INCC stored in the prize ball information storage area of the payout control internal RAM (decrement, step S778). ..

Following step S778 or when there is no detection signal from the counting switch 751 in step S776, the payout control program determines whether or not the value of the mismatch counter INCC is smaller than the mismatch threshold INCTH (step S780). ). In the pachinko game machine 1, it is experimentally found that the probability that one unsatisfied game ball will be paid out by the retry operation is about several millionth, and in the present embodiment, the inconsistency threshold value is set. The value 5 is set as INCTH.

In the process of setting the work area of the payout control built-in RAM in step S530 in the payout control unit power-on process of FIG. 53, as described above, the payout backup information is stored in the payout control built-in RAM at power recovery. The information used for the retry operation monitoring process is set based on the inconsistency counter INCC stored in the prize ball information storage area. By this processing, for example, even if there is a momentary power failure or power failure, the value of the inconsistency counter INCC at the time of power recovery is restored to the value of the inconsistency counter INCC or the like immediately before the momentary power failure or power failure stored as payout backup information. You can do it. Thereby, in the determination of step S780, it is possible to continue the monitoring of the payout operation (retry operation) of the game balls by the prize ball device 740, which has been performed until immediately before the momentary power failure or the power failure, from the time of the power recovery. ing. Therefore, for example, immediately before a momentary power failure or a power failure, if the value of the inconsistency counter INCC is smaller than the inconsistency threshold INCTH in the determination of step S780, it is determined that the retry operation is normally performed, that is, the prize ball. It is possible to determine that the payout operation of the game balls by the device 740 is in a normal state, and even when the power is restored, it is possible to determine that the payout operation of the game balls by the prize ball device 740 is in a normal state by the determination in step S780. On the other hand, when the value of the inconsistency counter INCC is not smaller than the inconsistency threshold value INCTH in the determination of step S780, it is determined that the retry operation is abnormal, that is, the game ball payout operation by the prize ball device 740 is abnormal. Even when the power is restored, it is possible to determine that the payout operation of the game balls by the prize ball device 740 is in an abnormal state even when the power is restored.

When the value of the inconsistency counter INCC is smaller than the inconsistency threshold value INCTH in step S780, this routine is finished as it is. On the other hand, in step S780, when the value of the inconsistency counter INCC is not smaller than the inconsistency threshold INCTH, that is, when the value of the inconsistency counter INCC is greater than or equal to the inconsistency threshold INCTH, the payout control program displays the “retry error”. In order to inform that it is, the above-mentioned payout control built-in RAM is set by setting retry error information for displaying the number “5” on the error LED display 860b which is a segment display mounted on the payout control board 4110. Is set (stored) in the state information storage area (step S782). On the other hand, when notifying that the prize ball is being stocked, the payout control program sets the prize ball stock information in which the number "9" is displayed on the error LED display 860b and incorporates the payout control described above. It is set (stored) in the state information storage area of the RAM (step S782).

Following step S782, the payout control program sets a value 0 (initial value 0) to the inconsistency counter INCC stored in the prize ball information storage area of the payout control internal RAM (step S784). In step S784, the mismatch counter INCC determines that the value of the mismatch counter INCC is not smaller than the mismatch threshold INCTH in step S780, that is, the value of the mismatch counter INCC is greater than or equal to the mismatch threshold INCTH. Initialization is triggered by the occurrence of this internal factor. When the operation switch 860a is operated to clear the RAM when the power is turned on, the inconsistency counter INCC is initialized by the occurrence of this external factor. When the operation switch 860a is operated when the power is turned on, as described above, the operation signal corresponding to the operation is input to the main control MPU 4100a of the main control board 4100 shown in FIG. 14 as a RAM clear signal. The main control program described above, under the control of the main control MPU 4100a, erases all of the various information stored in the main control internal RAM as described above, and issues a RAM clear notification command to the peripheral control board shown in FIG. Output to 4140. As a result, the RAM clear notification sound is made to flow from the speaker accommodated in the speaker box 820 provided in the main body frame 3 shown in FIG. 5 and the speaker 130 provided in the door frame 5 shown in FIG.

Following step S784, the retry error flag RTERR-FLG is set to the value 1 (step S786), and this routine ends. The retry error flag RTERR-FLG is a flag indicating whether or not the retry operation is abnormally operating. The value is 1 when the retry operation is abnormally operating, and the retry operation is not abnormally operating (retry operation is When operating normally, the value is set to 0.

The payout control program shows the retry error information (or prize ball stock information) set (stored) in the output information storage area of the payout control internal RAM in step S782 under the control of the payout control MPU 4120a, as shown in FIG. In the pay-out control unit power-on process (payout control unit main process), a retry error status command is created in the command sending process in step S566 and sent to the main control board 4100, and LED display data creation in step S564 in the same process. In the processing, display data to be displayed on the error LED display 860b is created and stored in the output information storage area as LED display information, and the LED display information stored in the output information storage area in the port output processing of step S548 in the same processing is performed. Based on this, a drive signal is output to the error LED display 860b, and the number "5" is displayed on the error LED display 860b. In the main control board 4100 which has received the status command, the main control program transmits it to the peripheral control board 4140 in the peripheral control board command transmission processing of step S120 in the main control side timer interrupt processing shown in FIG. The peripheral control board 4140 includes a plurality of LEDs (provided on each of the plurality of frame-side peripheral control MPU control target decoration boards, which are control objects to be directly controlled by the peripheral control MPU 4150a, among the decoration boards of the door frame 5). In order to make the decoration LED) emit light in a predetermined color (red in the present embodiment), the frame-side light emission data described above is output to the frame decoration drive amplifier board 194 shown in FIG. Make it emit light in color. As described above, the clerk or the like in the hall who notices the light emission of the plurality of LEDs opens the main body frame 3 with respect to the outer frame 2 to display the number "" on the error LED display 860b mounted on the payout control board 4110. By visually observing that "5" is displayed, it can be confirmed that a "retry error" has occurred. Thereby, in order to investigate the cause of the occurrence, the clerk in the hall or the like checks the malfunction of the counting switch 751, disconnection of various harnesses extending from the counting switch 751 to the payout control board 4110, contact failure of various connectors, and the like. As compared with the case where the light emission of the plurality of LEDs and the display content of the error LED indicator 860b are not notified, the operation can be performed extremely quickly.

Further, by intentionally deactivating the counting switch 751, the gaming sphere that is received by the concave portion of the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted and is paid out is difficult to detect. Even if an illegal act of forcibly generating a retry operation and illegally acquiring a game ball paid out by this retry operation is performed, the value of the above-described inconsistency counter INCC becomes equal to or more than the inconsistency threshold INCTH. Among the decorative boards of the door frame 5, a plurality of LEDs (decorative LEDs) provided on each of the frame-side peripheral control MPU control target decorative boards that are controlled by the peripheral control MPU 4150a directly emit light. Therefore, a clerk or the like in the hall will rush to check the state of the pachinko gaming machine 1. Then, the player who commits the cheating is forced to interrupt the act so that the act is not discovered, and the player cannot continue to obtain the fraudulent gaming ball due to the cheating. Even if the value of the inconsistency counter INCC matches the inconsistency threshold INCTH, the number of game balls that can be acquired by the player who engages in cheating is the same as the inconsistency threshold INCTH, that is, 5 balls. Therefore, the damage to the hole due to the act of intentionally deactivating the counting switch 751 can be suppressed to an extremely small level.

Furthermore, as described above, the inconsistency counter INCC determines that the value of the inconsistency counter INCC is not smaller than the inconsistency threshold INCTH in step S780, that is, the value of the inconsistency counter INCC is greater than or equal to the inconsistency threshold INCTH. Initialization is triggered by the occurrence of the internal factor of becoming. As a result, the inconsistency counter INCC is not initialized, for example, when an external factor such as operating the operation switch 860a to cancel the error occurs. Therefore, even if the operation switch 860a or the like is tampered with and the operation signal is input to the payout control MPU 4120a, such injustice may forcibly initialize the inconsistency counter INCC. Absent.

[17-10. Mismatch counter reset judgment processing]
Next, the mismatch counter reset process will be described. In this inconsistency counter reset processing, the number of balls of the game balls that are received and paid out in the recess of the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted, and the number of balls detected by the counting switch 751. Is a process of determining whether or not to reset the inconsistency counter INCC that calculates the difference between the two.

When the inconsistency counter reset determination process is started, in the payout control unit 4120 of the payout control board 4110, the payout control program is controlled by the payout control MPU 4120a, as shown in FIG. It is determined whether the time has passed (step S790). This determination is performed based on the inconsistency counter reset determination time updated in the timer updating process of step S552 in the payout control unit power-on process (payout control unit main process) shown in FIG. Specifically, the inconsistency counter reset determination time is stored as time management information in the time management information storage area of the payout control built-in RAM described above. In step S790, the time management information is read from the time management information storage area and it is determined whether or not the mismatch counter reset determination time has elapsed.

If the mismatch counter reset determination time has not elapsed in step S790, the payout control program ends this routine as it is. On the other hand, when the inconsistency counter reset determination time has elapsed in step S790, the payout control program initializes the inconsistency counter reset determination time (step S792). By this initialization, the initial value 7000 s (about 2 hours) is set as the mismatch counter reset determination time.

Subsequent to step S792, the payout control program sets a value 0 (initial value 0) to the inconsistency counter INCC stored in the prize ball information storage area of the payout control internal RAM described above (step S794), and this routine To finish. As described above, the inconsistency counter INCC is detected by the counting switch 751 and the number of game balls that are paid out by being received in the recess of the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted. It is a counter for calculating the difference between the number of balls and the number of balls of a game ball received and paid out in the recess of the payout rotating body, and the number of balls detected by the counting switch 751 is usually one. As a result, the value becomes 0. The payout control program performs a retry operation in the payout setting process shown in FIG. 62 under the control of the payout control MPU 4120a. Therefore, by this retry operation, the ball of the game ball received in the concave portion of the payout rotating body and paid out. The number of balls actually detected by the counting switch 751 and the number of balls that are actually detected by the counting switch 751 do not match each other, so that the payout of unmatched game balls is repeatedly monitored and determined by the inconsistency counter INCC. With the pachinko game machine 1 of the present invention, it has been experimentally obtained that the probability that one unsatisfied game ball due to a retry operation will be paid out is about several millions.

Here, as described above, the pachinko gaming machine 1 includes the gaming board 4 and a frame body such as the main body frame 3 on which the gaming board 4 is mounted. By exchanging the gaming board 4 (replacement of a new machine). Since the game specification can be changed, the payout control board 4110 for controlling the prize ball device 740, the power supply board 851 for generating the driving power supply for the prize ball device 740 and the control power supply for the payout control board 4110 are common. It is equipped on the frame side as a function. In the payout control unit 4120 of the payout control board 4110, the payout control program, under the control of the payout control MPU 4120a, monitors the inconsistency counter INCC to determine whether or not the retry operation is repeated, as described above. The operation can be determined, and in the payout control unit power-off process in the payout control unit power-on process shown in FIG. 53, the inconsistency counter INCC immediately before shutoff is stored at the time of power cutoff, while In the process of step S530 in the power-on process of the payout control unit shown at 52 (setting at power recovery of the RAM work area), the process is restarted from the stored inconsistency counter INCC at power-on.

Then, when the power is cut off and the gaming board 4 mounted on the pachinko gaming machine 1 is replaced with a gaming board 4'having a different game specification from the gaming board 4 and the power is turned on, the payout control is performed. The payout control MPU 4120a of the payout control unit 4120 on the board 4110 starts the process again from the inconsistency counter INCC stored when the game board 4 is mounted on the pachinko gaming machine 1. In other words, when the player plays the pachinko gaming machine 1 with the gaming board 4 ′ mounted, the inconsistency counter INCC in the pachinko gaming machine 1 with the gaming board 4 before replacement is inherited as it is. Therefore, the player plays the pachinko gaming machine 1 on which the gaming board 4'is mounted, and by chance, there is a probability of one millionth of a million, and the number of unmatched gaming balls occurs and the inconsistency counter INCC is generated. When the mismatch counter INCC becomes equal to or more than the mismatch threshold value INCTH described above, the payout control MPU 4120a determines that the retry operation is an abnormal operation within a short period of time when the game board 4 is replaced with the game board 4′. May occur. That is, in a period shortly after the game board 4 is replaced with the game board 4', a malfunction of the counting switch 751, disconnection of various harnesses from the counting switch 751 to the payout control board 4110, contact failure of various connectors, etc. Although the error does not occur, there is a possibility that the retry operation is suddenly determined to be an abnormal operation.

In this way, if the game board 4 is replaced with the game board 4′ and it is determined that the retry operation is abnormal in a short period of time, the replacement game board 4′ is new, but the impression is that the game board 4′ is likely to malfunction. It may be given to the player. The probability that one inconsistent game ball will be paid out by the retry operation is one millionth of the probability when the pachinko game machine 1 is installed in the hall and continuously operated for one week during the business hours of the hall. , The probability that one inconsistent game ball due to the retry operation is paid out is the same as the probability that one ball is paid out, so in the processing of step S778 in the retry operation monitoring processing shown in FIG. With, the value 1 cannot be subtracted. Then, in one week, the inconsistency counter INCC is incremented by 1 and the inconsistency counter INCC becomes 1, and in two weeks the inconsistency counter INCC is further incremented by 1 and the inconsistency counter INCC becomes 2 by 3 In the week, the inconsistency counter INCC is further incremented by 1 to make the inconsistency counter INCC have the value 3, and in 4 weeks the inconsistency counter INCC is further incremented by 1 to make the inconsistency counter INCC the value 4 in 5 weeks. The inconsistency counter INCC is further incremented by 1 and the inconsistency counter INCC becomes a value of 5, which matches the above-described inconsistency threshold INCTH. That is, after 5 weeks have passed, the inconsistency counter INCC matches the inconsistency threshold INCTH, so that the payout control program is under the control of the payout control MPU 4120a, at step S776 in the retry operation monitoring process shown in FIG. In the determination, it is determined that there is no detection signal from the counting switch 751, and a malfunction of the counting switch 751, disconnection of various harnesses from the counting switch 751 to the payout control board 4110, contact failure of various connectors, and the like occur. In the process of step S782 in the retry operation monitoring process shown in FIG. 64, the segment display unit is mounted on the payout control board 4110 in order to notify that there is a “retry error”. The retry error information for displaying the number "5" on the error LED display 860b is set and set (stored) in the state information storage area of the payout control built-in RAM.

Therefore, when the payout control MPU 4120a determines in step S790 in this inconsistency counter reset determination process that the inconsistency counter reset determination time has elapsed, that is, every 7000 s (about 2 hours), the inconsistency counter reset is repeatedly performed. By forcibly setting the value 0 to the inconsistency counter INCC in the processing of step S794 in the determination process, that is, forcibly resetting it, the increment of the inconsistency counter INCC that occurs with a probability of a few millionths described above is performed. It is disabled. As a result, an error occurs in the retry operation although the malfunction of the counting switch 751, the disconnection of various harnesses from the counting switch 751 to the payout control board 4110, the contact failure of various connectors, etc. do not occur. It is possible to prevent the retry error information that conveys the message from being set (stored) in the state information storage area of the payout control RAM.

It is noted that by intentionally deactivating the counting switch 751, it is difficult to detect the game ball that is paid out by being received in the concave portion of the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted. Even if an illegal act of forcibly generating the retry operation and illegally acquiring the game ball paid out by this retry operation is performed and the counting switch 751 is intentionally repeatedly deactivated for a short time, the above-described operation is performed. As described above, when the value of the inconsistency counter INCC becomes equal to or higher than the inconsistency threshold INCTH, a plurality of frame-side peripheral control MPUs, which are the control targets to be directly controlled by the peripheral control MPU 4150a, of the decorative boards of the door frame 5. Since a plurality of LEDs (ornamental LEDs) provided on each of the control target decorative substrates emit light, a clerk in the hall or the like rushes to confirm the state of the pachinko gaming machine 1. Then, the player who commits the cheating is forced to interrupt the act so that the act is not discovered, and the player cannot continue to obtain the fraudulent gaming ball due to the cheating. On the other hand, when the counting switch 751 is intentionally repeatedly deactivated for a long time so that the value of the inconsistency counter INCC does not exceed the inconsistency threshold INCTH, the inconsistency counter INCC is changed every 7000 s (about 2 hours). Although it is reset, the number of game balls that can be acquired by the player who engages in cheating during this period is, as described above, the mismatch counter INCC is up to the mismatch threshold INCTH, and the counting switch 751 is intentionally set. The number of game balls that can be acquired by a player who commits an illegal act can be extremely reduced even when the game machine is repeatedly deactivated for a long time.

[17-11. Error release operation determination processing]
Next, the error cancellation operation determination process will be described. In this error release operation determination process, it is determined whether the operation switch 860a shown in FIG. 15 is operated.

When the error canceling operation determination process is started, in the payout control unit 4120 of the payout control board 4110, the payout control program causes the operation switch 860a to cancel the error as shown in FIG. 66 under the control of the payout control MPU 4120a. It is determined whether or not it is operated (step S800). This determination is performed based on the operation signal from the operation switch 860a in the port input process of step S550 in the power-on process of the payout control unit (payout control unit main process) shown in FIG. Specifically, the operation signal is stored as input information in the input information storage area of the payout control built-in RAM described above. In step S800, it is determined that the payout control program does not instruct to perform error cancellation by reading the input information from the input information storage area and when the logical value of the operation signal from the operation switch 860a is HI. It is determined that the operation switch 860a is not operated, and when the logical value of the operation signal from the operation switch 860a is LOW, it is determined that the operation switch 860a is instructed to perform error cancellation, and the operation switch 860a is operated. It is determined that

When the operation switch 860a is not operated in step S800, the payout control program ends this routine as it is, while when the operation switch 860a is operated in step S800, the payout control program performs the error flag state confirmation processing. Perform (step S802). In this error flag state determination processing, the state of the error flag corresponding to various error information regarding the prize ball device 740 is confirmed. For example, the state of the retry error flag RTERR-FLG indicating whether or not the retry operation is abnormal is confirmed. As described above, the retry error flag RTERR-FLG has a value of 1 when the retry operation is abnormal, and a value of 0 when the retry operation is not abnormal (the retry operation is normally operating). Since it is set, the payout control program confirms whether the value of the retry error flag RTERR-FLG is 0 or 1 under the control of the payout control MPU 4120a.

Following step S802, the payout control program performs state information setting processing (step S804). In this status information setting process, based on the error flag confirmed in step S802, if the status of the error flag indicates that an error has occurred, the status information corresponding to the error flag is set to It is set (stored) in the state information storage area of the payout control built-in RAM. As a result, in the command transmission process of step S566 in the payout control unit power-on process (payout control unit main process) shown in FIG. 53, various information (state information) is read from the state information storage area, and the read state is read. A status command is created based on the information and transmitted to the main control board 4100. For example, when the retry error flag RTERR-FLG indicating whether or not the above-described retry operation is abnormal, has a value of 1, that is, when the retry operation is abnormal, the error in the retry operation is indicated. When the retry error information to be transmitted is set (stored) in the state information storage area of the payout control internal RAM, the command transmission process of step S566 in the payout control unit power-on process (payout control unit main process) shown in FIG. A retry error status command is created and transmitted to the main control board 4100.

In the main control board 4100 that has received the retry error information, the main control program transmits it to the peripheral control board 4140 by the peripheral control board command transmission processing of step S120 in the main control side timer interrupt processing shown in FIG. In the control board 4140, the sub-control program performs a retry operation error notification process that notifies that an error has occurred in the retry operation. In this retry operation error notification processing, the error notification announcement of the retry operation of "Please check the prize ball unit." and "Please check the harness of the payout control board." (2 times.) Repeatedly notifies the clerk of the hall by flowing from the speaker accommodated in the speaker box 820 provided in the main body frame 3 shown in FIG. 5 and the speaker 130 provided in the door frame 5 shown in FIG. It is supposed to do. Upon receipt of the error notification announcement of the retry operation, the hall clerk or the like receives a malfunction of the counting switch 751 shown in FIG. Can be confirmed much earlier than when the error notification announcement of the retry operation does not flow from the speaker accommodated in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5. In the retry operation error notification process, among the decorative boards of the door frame 5, a plurality of LEDs provided on each of the frame-side peripheral control MPU control target decorative boards that are directly controlled by the peripheral control MPU 4150a. The (decorative LED) is forcibly set to a predetermined color (red in this embodiment) to emit light.

Subsequent to step S804, the payout control program performs a cancellation setting process (step S806). In this cancellation setting process, if the state of the error flag indicates that an error has occurred, based on the error flag corresponding to the various error information confirmed in step S802, the error flag is dealt with. The CR unit 6 indicates that the error is forcibly stopping the contents displayed by the error LED display 860b, which is the segment display already mounted on the payout control board 4110, or that the ball lending is ready. In order to convey to the above, the logic of the PRDY signal described above is kept at HI, that is, the activated state is held, and the game ball lending device connection terminal board 869 is connected from the output terminal of the predetermined output port of the payout control MPU 4120a of the payout control unit 4120. It outputs to the CR unit 6 via the. For example, when the retry error flag RTERR-FLG indicating whether or not the above-described retry operation is abnormal, is 1, that is, when the retry operation is abnormal, the error LED indicator 860b has already been displayed. In order to forcibly stop the number "5" for notifying that there is a "retry error", the retry error information stored in the state information storage area of the payout control internal RAM described above is "normal". The information to which the graphic "-" for notifying the effect is displayed is forcibly overwritten. Also, in order to inform the CR unit 6 that the ball can be lent, the logic of the PRDY signal is held at HI, that is, the state is raised, and the game ball is output from the output terminal of the predetermined output port of the payout control MPU 4120a. It outputs to the CR unit 6 through the equal lending device connection terminal board 869.

Following step S806, the payout control program performs error flag initialization processing (step S808), and this routine ends. In this error flag initialization processing, based on the error flags corresponding to the various error information confirmed in step S802, if the status of the error flag indicates that an error has occurred, that error flag is set. initialize. For example, when the retry error flag RTERR-FLG indicating whether or not the above-described retry operation is abnormally operated is the value 1, that is, when the retry operation is abnormally operated, the retry error flag RTERR-FLG is set to the value 0. Set and initialize. At this time, the logic of the PRDY signal described above is held at HI, that is, the rising state is held, and the logic state of the PRDY signal is set in the PRDY signal output setting information and stored in the CR communication information storage area. Thereby, in the CR communication process of step S554 in the payout control unit main process of the payout control unit power-on process of FIG. 53, the PRDY signal output setting information is read from the CR communication information storage area stored in the payout control built-in RAM. The PRDY signal output setting information read out by lever is output to the CR unit 6 from the output terminal of the predetermined output port of the payout control MPU 4120a via the gaming ball lending device connection terminal board 869. ..

As described above, the retry error flag RTERR-FLG indicates the internal factor when the value of the inconsistency counter INCC is greater than or equal to the inconsistency threshold INCTH in the determination of step S780 in the retry operation monitoring process shown in FIG. When the operation switch 860a is operated while the retry error flag RTERR-FLG is set to 1 in the process of step S786 of the same process when the occurrence of the error occurs, this external factor causes When the error occurs, the retry error flag RTERR-FLG is set to the value 0 and initialized. When the operation switch 860a is operated to clear the RAM when the power is turned on, the retry error flag RTERR-FLG is operated as a trigger, that is, the operation switch 860a is operated to clear the RAM to clear the error. Similar to the case where the switch 860a is operated, the initialization is triggered by the occurrence of this external factor.

As described above, in the pachinko game machine 1, the main control side main processing is executed from the time of power-on of the operation switch 860a (operation switch) that was originally supposed to be used to release the error that occurred in the payout operation. Instead, for a predetermined time until the operation is performed, an operation for demonstrating a RAM clear function for starting initialization of the main control internal RAM (game storage unit) and the payout control internal RAM (payout storage unit) It functions as a department. Further, the pachinko gaming machine 1 causes the operation switch 860a to function as an operation unit for canceling an error that has occurred in the payout operation of the game ball, after the predetermined time has elapsed. Here, even if the hall clerk is a person who is not accustomed to operating the pachinko machine, as long as he/she remembers the position of the operation switch 860a on the rear surface of the gaming machine, the operation switch 860a may be operated according to the timing. If a predetermined time has passed since the power was turned on, the function to release the error that has occurred with respect to the payout operation of the game ball is exerted, while the predetermined amount has been set since the power was turned on in accordance with the timing of operating the operation switch 860a. Within the time, the function of initializing the storage unit can be exerted. Therefore, even if an error occurs in such a gaming machine, the hall clerk can improve the efficiency of the switch operation at the time of dealing with the error and appropriately deal with the switch operation without hesitation, so that the game is interrupted. The player can resume the game before the player loses the willingness to play the game.

[17-12. Exchange of various signals with CR unit]
Next, the CR communication process of step S554 in the payout control unit main process of the payout control unit power-on process of FIG. 53 will be described using a timing chart. In this CR communication processing, various signals are exchanged between the payout control board 4110 and the CR unit 6 shown in FIG. First, the signal processing during the payout operation by the ball lending will be described, and subsequently, the input signal confirmation processing from the CR unit 6 will be described. Here, as the amount of money, the number of game balls corresponding to 200 yen (in the present embodiment, 50 balls and the amount of 25 balls corresponding to 100 yen is paid out twice) is used as the number of lent balls. A case of paying out to the upper plate 301 and the lower plate 302 shown in FIG. 7 will be described. The BRQ signal, the BRDY signal, and the CR connection signal from the CR unit 6 are read from the input information storage area of the payout control built-in RAM and stored in the read input information. Checks the logical state of the BRQ signal, the BRDY signal and the CR connection signal from the input information every 2 ms which is the interrupt timer period.

[17-12-1. Signal processing during payout operation by ball lending]
The payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110 reads the PRDY signal output setting information from the CR communication information storage area of the payout control internal RAM, and the read PRDY signal output setting information pays out the rented ball. In the case where the logical state of the PRDY signal that indicates that the payout operation is possible is set, as shown in FIG. 67(d), the payout operation for paying out the rental ball is possible. In order to convey the PRDY signal, the logic of the PRDY signal is set to HI, that is, raised and held, and output from the output terminal of a predetermined output port of the payout control MPU 4120a of the payout control unit 4120, and as PRDY, a game ball lending device connection terminal Output to the CR unit 6 via the plate 869 (timing H0). In this state, for example, when the player presses the ball lending button 361 of the ball lending unit 360 shown in FIG. 2, the ball lending switch 365b is turned on (turned on). The operation signal is input to the CR unit 6 as the TDS shown in FIG. 16 from the frequency display plate 365 through the game ball etc. lending device connection terminal plate 869. The CR unit 6 to which this TDS is input pays out the number of game balls for 200 yen as the amount of money to the upper plate 301 and the lower plate 302 as the number of lent balls, so as shown in FIG. 67(a), BRDY, which is a ball request signal, is output from the CR unit 6 to the payout control board 4110 (payout control MPU4120a) via the gaming ball etc. lending device connection terminal board 869, and the signal is raised and held (timing H1). .. This BRDY is input as a BRDY signal to the input terminal of a predetermined input port of the payout control MPU 4120a.

In the payout control MPU 4120a to which the BRDY signal is input, the payout control program, as shown in FIG. 67(b), changes from the timing H1 to the lending request monitoring time HA (in the present embodiment, from 20 milliseconds (ms) to 58 ms). By the time the set amount of time elapses, a predetermined number of balls to be leased (25 balls in the present embodiment, from the CR unit 6 through the lending device connection terminal plate 869 for gaming balls, etc., in one payout operation. , Which corresponds to 100 yen as the amount of money) is monitored for whether or not the BRQ, which is a one-time payout operation start request signal for paying out.

The CR unit 6 first pays out the number of game balls for 100 yen among the number of game balls for 200 yen as the amount of money to the upper plate 301 and the lower plate 302 as the number of lent balls. ), BRQ is output from the CR unit 6 to the CR unit 6 via the lending device connection terminal board 869 for playing balls etc. by the time the lending request monitoring time HA elapses from the timing H1. Start up and hold (timing H2). This BRQ is input as a BRQ signal to the input terminal of a predetermined input port of the payout control MPU 4120a.

As shown in FIG. 67(c), when the BRQ signal rises from the timing H1 until the lending request monitoring time HA elapses, the payout control MPU 4120a starts timing H2 and outputs the BRQ request acknowledgment ACK monitoring time HB (in the present embodiment, 20 ms±1 ms is set), the EXS signal logic is set to HI, that is, the startup state is held and the payout control MPU4120a is transmitted in order to notify that the one payout operation is started. Is output from the output terminal of the predetermined output port of, and is output as the EXS to the CR unit 6 through the lending device connection terminal plate 869 for gaming balls and the like (timing H3).

67(b), the CR unit 6 to which this EXS is input is from timing H3 until the lending instruction monitoring time HC (in the present embodiment, it is set to 20 ms to 58 ms). , BRQ which was started up and held from the timing H2 is output from the CR unit 6 to the payout control board 4110 via the game ball lending device connection terminal plate 869, and the signal is lowered and held (timing H4).

As shown in FIG. 67(c), the payout control MPU 4120a performs one payout operation from timing H4 until the payout monitoring time HD (in the present embodiment, the ball payout time is set). The predetermined number of lent balls, that is, the number of game balls for 100 yen, is paid out to the upper plate 301 and the lower plate 302 as the number of lent balls. Then, when the payout monitoring time HD has elapsed, the EXS signal that has been raised and held from the timing H3 is output from the output terminal of a predetermined output port of the payout control MPU 4120a with its logic being set to LOW, that is, in the lowered state. , EXS is output to the CR unit 6 through the game ball lending device connection terminal plate 869 (timing H5).

The CR unit 6 pays out the remaining 100 yen of the number of game balls out of the number of 200 yen balls as the amount of money to the upper plate 301 and the lower plate 302 as the number of lent balls. ), from timing H5 until the next request confirmation timing HE (in the present embodiment, the maximum is set to 268 ms), BRQ from the CR unit 6 to the game ball lending device connection terminal board. It outputs to the payout control board 4110 (payout control MPU 4120a) via 869, and raises and holds the signal (timing H6).

Similarly, when the payout control MPU 4120a pays out the remaining 100 yen of game balls as the number of lent balls to the upper plate 301 and the lower plate 302 using the method described above, as shown in FIG. 67(c). , The rising and holding EXS signal is output from the output terminal of a predetermined output port of the payout control MPU4120a with the logic thereof set to LOW, that is, in the lowered state, and the terminal is connected to a lending device such as a game ball as EXS. Output to the CR unit 6 through the plate 869 (timing H7).

The CR unit 6 rises from the timing H1 as shown in FIG. 67(a) until the CR unit lending completion monitoring time HF (set to 268 ms at maximum in this embodiment) elapses from the timing H7. The BRDY which is raised and held is output from the CR unit 6 to the payout control board 4110 (payout control MPU 4120a) through the game ball lending device connection terminal plate 869, and the signal is lowered and held (timing H8).

The above-mentioned lending request monitoring time HA, BRQ request approval ACK monitoring time HB, lending instruction monitoring time HC, payout monitoring time HD, next request confirmation timing HE, and CR unit lending completion monitoring time HF are the payout control shown in FIG. The time is counted by the timer updating process of step S552 in the process of turning on the power to the unit (main process of the payout control unit).

Note that the payout control MPU 4120a is not communicating with the CR unit 6 when there is a ball out, a ball is caught, a counting switch error, a retry error, a full tank, or the like (when the logic of BRDY from the CR unit 6 is Is LOW, that is, when it is held after falling, as shown in FIG. 67(d), the PRDY signal that was started and held from timing H1 is set to LOW, that is, the state of falling. It holds and outputs from the output terminal of the predetermined output port of the payout control MPU 4120a, and outputs it as the PRDY to the CR unit 6 via the lending device connection terminal plate 869 for gaming balls and the like (timing H9). On the other hand, while communicating with the CR unit 6 (when the logic of BRDY from the CR unit 6 is HI, that is, when the logic is rising and held), although not shown, the logic state of the EXS signal is maintained and the payout is performed. It is output from the output terminal of a predetermined output port of the control MPU 4120a, and is output to the CR unit 6 as EXS via the game ball lending device connection terminal plate 869. “Maintaining the logic state of the EXS signal” means that when the logic of the EXS signal is LOW (the EXS signal falls and is held), the logic LOW is maintained, and the logic of the EXS signal is HI ( The EXS signal is held at the rising edge) to maintain its logic HI.

In this way, the CR unit 6 exchanges various signals with the payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110, and the payout control MPU 4120a sets the number of game balls of 200 yen as the amount of money to 100. By performing the payout operation of 25 balls worth of yen twice, the game balls with the number of lent balls of 50 balls are paid out to the upper plate 301 and the lower plate 302. In addition, a setting staff (not shown) provided on the front side of the CR unit 6 is operated by a clerk in the hall or the like, and, for example, the number of game balls worth 100 yen is used as the number of balls to be rented, and the upper plate 301 or When the payout control MPU 4120a performs a payout operation of 25 balls for 100 yen once as the amount to be paid out to the lower plate 302, the number of game balls for 500 yen as the amount is set as the number of lent balls. When the upper plate 301 and the lower plate 302 are set to be paid out, the payout control MPU 4120a performs a payout operation of 25 balls for 100 yen as the amount of money 5 times, and the number of balls of the game ball for 1000 yen as the amount of money. When the number of lent balls is set to be paid out to the upper plate 301 and the lower plate 302, the payout control MPU 4120a performs a payout operation of 25 balls for 100 yen as the amount of money 10 times.

[17-12-2. Input signal confirmation processing from CR unit]
The payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110 allows the CR unit 6 to output the BRQ and the CR unit 6 via the game ball and other rental device connection terminal board 869 even after the above-described loan request monitoring time HA has elapsed. Then, the CR unit 6 outputs BRDY even if the signal is not output to the payout control board 4110 and the signal is not activated, or the lending instruction monitoring time HC described above has elapsed, and the CR unit 6 connects the game ball or other lending device. Through the terminal board 869, output to the payout control board 4110, when the signal is not lowered, or even when the above-described next request confirmation timing HE has elapsed, the CR unit 6 outputs the BRQ from the CR unit 6 The CR unit 6 outputs the signal to the payout control board 4110 via the ball lending device connection terminal board 869 and the signal is not raised, or even if the CR unit lending completion monitoring time HF described above elapses. Is output from the CR unit 6 to the payout control board 4110 through the game ball lending device connection terminal board 869, and when the signal is not dropped, the PRDY and EXS described above are used to set the BRQ and Confirm whether BRDY is normal or not. Specifically, as shown in FIGS. 67(e) and 67(f), the payout control MPU 4120a determines that BRQ and BRDY are not normal (timing J0), and then a predetermined period JA (in this embodiment, from this timing J0). , 200 ms±1 ms.), the logic of the PRDY signal is set to LOW, that is, the lowered state is held and output from the output terminal of the predetermined output port of the payout control MPU 4120a of the payout control unit 4120. Then, as PRDY, it is output to the CR unit 6 through the game ball lending device connection terminal board 869, and the logic of the EXS signal is set to LOW, that is, the lowered state is held and a predetermined output port of the payout control MPU 4120a. Output from the output terminal of, and output as EXS to the CR unit 6 via the terminal device connection terminal board 869 for playing game balls and the like (timing J1).

Subsequently, the payout control MPU 4120a sets the logic of the PRDY signal held at the timing J1 to HI after the predetermined period JB (200 ms±1 ms is set in this embodiment) from the timing J1. In other words, the output is held from the output terminal of a predetermined output port of the payout control MPU 4120a while being kept in the activated state, and is output to the CR unit 6 as PRDY via the terminal device connection terminal plate 869 for playing balls, etc. (timing J2). ).

Subsequently, the payout control MPU 4120a sets the logic of the PRDY signal started and held from the timing J2 to LOW after a lapse of a predetermined period JC (100 ms±1 ms in the present embodiment) from the timing J2. That is, the output is output from the output terminal of a predetermined output port of the payout control MPU 4120a while being held in the lowered state, and is output to the CR unit 6 as the PRDY via the terminal device connection terminal plate 869 for playing game balls and the like (timing J3). ).

Subsequently, the payout control MPU 4120a sets the logic of the PRDY signal, which is held and lowered from the timing J3, to HI after a predetermined period JD (100 ms±1 ms is set in the present embodiment) from the timing J3. That is, it is output from the output terminal of the predetermined output port of the payout control MPU 4120a while being kept in the activated state, and is output to the CR unit 6 as the PRDY via the terminal device connection terminal plate 869 for playing balls etc. (timing J4 ).

Subsequently, the payout control MPU 4120a sets the logic of the PRDY signal started and held from timing J4 to LOW after a predetermined period JE (100 ms±1 ms is set in the present embodiment) from timing J4. That is, the output is output from the output terminal of the predetermined output port of the payout control MPU 4120a while being held in the lowered state, and is output as PRDY to the CR unit 6 via the game ball lending device connection terminal plate 869 (timing J5. ).

Subsequently, the payout control MPU 4120a sets the logic of the PRDY signal held at the timing J5 to HI after falling for a predetermined period JF (set to 10000 ms±1 ms in this embodiment) from the timing J5. That is, the output is held from the output terminal of the predetermined output port of the payout control MPU 4120a while being kept in the activated state, and is output to the CR unit 6 as the PRDY via the terminal device connection terminal plate 869 for playing balls and the like (timing J6). ).

The above-described predetermined period JA to predetermined period JF are clocked by the timer updating process of step S552 in the payout control unit power-on process (payout control unit main process) shown in FIG.

[18. Various control processing of peripheral control board]
Next, various processes of the peripheral control board 4140 that receives various commands from the main control board 4100 (main control MPU 4100a) shown in FIG. 14 will be described with reference to FIGS. 68 to 79. 68 is a flowchart showing an example of the peripheral controller power-on process, FIG. 69 is a flowchart showing an example of the peripheral controller V blank interrupt process, and FIG. 70 is an example of the peripheral controller 1 ms timer interrupt process. 71 is a flowchart showing an example of peripheral control unit command reception interrupt processing, FIG. 72 is a flowchart showing an example of peripheral control unit power failure notice signal interrupt processing, and FIG. 73 is a transition to power saving mode at power recovery. FIG. 74 is a flowchart showing an example of determination processing, FIG. 74 is a flowchart showing an example of power consumption monitoring processing, and FIG. 75 shows a relationship between a value set as a master volume value for power suppression and a power consumption suppression stage. FIG. 76A is a diagram illustrating the relationship between the brightness set as the power suppression brightness and the power consumption suppression stage, and FIG. 76 is a flowchart illustrating an example of the LOCKN signal history creation process. 77 is a flow chart showing an example of connection failure determination processing, FIG. 78 is a flow chart showing an example of connection recovery processing, and FIG. 79 outputs a connection confirmation signal to the INIT terminal of the upper plate side liquid crystal transmitter IC. It is a timing chart explaining timing.

As shown in FIG. 17, the peripheral control board 4140 includes a peripheral control unit 4150 and a liquid crystal and sound control unit 4160. Here, various control processes of the peripheral control unit 4150 will be described. First, the peripheral control unit power-on processing will be described, followed by peripheral control unit V blank interrupt processing, peripheral control unit 1 ms timer interrupt processing, peripheral control unit command reception interrupt processing, peripheral control unit power failure notice signal interrupt processing, power recovery. The power saving mode transition determination processing, power consumption monitoring processing, LOCKN signal history creation processing, connection failure determination processing, and connection recovery processing will be described. The power saving mode transition determination process at the time of power recovery is the process of step S1004 in the peripheral control unit power-on process described later, and the power consumption monitoring process is the peripheral control unit steady process of the peripheral control unit power-on process described later. The LOCKN signal history creation process, which is the process of step S1027, is executed as one process of the drawing state information acquisition process of step S1110 in the peripheral controller 1 ms timer interrupt process, which will be described later. The peripheral control unit power-on process is executed as one process of the warning process of step S1024 in the peripheral control unit steady process, and the connection recovery process is executed subsequent to the connection failure determination process. In the present embodiment, the peripheral control unit power outage notice signal interrupt process is set to the highest priority as the priority of the interrupt process, followed by the power consumption suppression signal interrupt process, the peripheral control unit 1 ms timer interrupt process, and the peripheral control unit command reception. The interrupt processing and the peripheral control unit V blank interrupt processing are set in this order.

[18-1. Various control processes of peripheral control unit]
[18-1-1. Peripheral controller power-on processing]
First, the peripheral controller power-on process will be described with reference to FIG. When the pachinko gaming machine 1 is powered on, the peripheral control MPU 4150a of the peripheral controller 4150 shown in FIG. 17 performs peripheral controller power-on processing, as shown in FIG. When the peripheral control unit power-on process is started, the effect control program performs an initial setting process under the control of the peripheral control MPU 4150a (step S1000). In this initial setting process, the effect control program performs a process of initializing the peripheral control MPU 4150a itself, a hot start/cold start determination process, a process of setting a wait timer after reset, and the like. The peripheral control MPU 4150a first performs a process of initializing itself, but the time required for the process of initializing the peripheral control MPU 4150a is on the order of microseconds (μs), and the peripheral control MPU 4150a is initialized in an extremely short time. be able to. As a result, the peripheral control MPU 4150a enters a state in which the interrupt permission is set, so that the peripheral control MPU 4150a outputs from the main control board 4100 in the peripheral control unit command reception interrupt processing described later, for example, as shown in FIGS. 45 and 46. , It becomes a state in which various commands such as commands relating to control of game effects and commands relating to the state of the pachinko gaming machine 1 can be received.

In the hot start/cold start determination processing, for the peripheral control RAM 4150c shown in FIG. 18, effect backup information (1fr) which is the content backed up in Bank1 (1fr) and Bank2 (1fr) in the backup first area 4150cb thereof. ) And the production backup information (1 ms), which is the content backed up in Bank1 (1 ms) and Bank2 (1 ms), and Bank3 (1fr) and Bank4 (1fr) in the backup second area 4150cc. The production backup information (1fr) which is the content backed up to is compared with the production backup information (1ms) which is the content backed up to Bank3 (1ms) and Bank4 (1ms), and the comparison contents When the values match, the effect backup information (1fr), which is the content stored in Bank1 (1fr) with respect to Bank0 (1fr), which is the storage area normally used in the peripheral control RAM 4150c shown in FIG. 18, When the hot backup is performed by copying back the production backup information (1 ms), which is the content stored in Bank1 (1 ms) with respect to Bank0 (1 ms), when the compared contents do not match (that is, , (When they do not match), a value 0 is forcibly written to Bank0 (1fr) and Bank0 (1ms), which are the storage areas normally used in the peripheral control RAM 4150c, and cold start is performed.

Further, in the hot start/cold start determination processing, also for the peripheral control SRAM 4150d shown in FIG. 18, the effect backup information which is the content backed up in Bank1 (SRAM) and Bank2 (SRAM) in the backup first area 4150db. (SRAM) is compared, and the production backup information (SRAM) in the backup second area 4150dc, which is the content backed up in Bank3 (SRAM) and Bank4 (SRAM), is compared. When the compared contents match, the effect backup information (SRAM) which is the contents stored in Bank0 (SRAM) with respect to Bank0 (SRAM) which is a storage region which is normally used in peripheral control SRAM 4150d shown in FIG. ) Is copied back to perform a hot start, and when the compared contents do not match (that is, when they do not match), a value is set to Bank0 (SRAM) which is a storage area normally used by the peripheral control SRAM 4150d. Forcibly write 0 to start cold. Following such a hot start or cold start, the value 0 is forcibly written to the backup non-management target work area 4150cf of the peripheral control RAM 4150c shown in FIG. After performing the initialization setting process, the peripheral control MPU 4150a outputs a clear signal to the peripheral control built-in WDT 4150af shown in FIG. 18 and the peripheral control external WDT 4150e shown in FIG. 17 to reset the peripheral control MPU 4150a. I try not to get it covered.

Following step S1000, the effect control program performs current time information acquisition processing (step S1002). In this current time information acquisition processing, the calendar information for specifying the date and the time information for specifying the hour, minute, and second are acquired from the RTC internal RAM 4165aa of the RTC 41654a of the RTC control unit 4165 shown in FIG. In the RTC information acquisition storage area 4150cad of the peripheral control RAM 4150c shown in, the current calendar information is set in the calendar information storage section and the current time information is set in the time information storage section.

In this embodiment, the peripheral control MPU 4150a acquires the calendar information and the time information from the RTC built-in RAM 4165aa of the RTC 4165a only once when the power is turned on. In addition, the peripheral control MPU 4150a outputs a clear signal to the peripheral control internal WDT 4150af and the peripheral control external WDT 4150e after performing this current time information acquisition processing so that the peripheral control MPU 4150a is not reset.

Subsequent to step S1002, power saving mode transition determination processing at power recovery is performed (step S1004). In the power saving mode transition determination process at the time of power recovery, a detailed description thereof will be described later, but when the power is turned off (power source is turned on) based on the power consumption state history information stored and held in the power consumption state history RAM 4150f shown in FIG. Immediately before disconnection), the state of power consumed by the pachinko gaming machine 1 is grasped at the time of power recovery, and it is determined whether or not to shift to the power saving mode at power recovery in which the power consumed by the pachinko gaming machine 1 is suppressed. When shifting to the power saving mode at the time of power saving, the setting is made to reduce the volume of the effect sound played from the speaker accommodated in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, each of the door frame 5. Settings are made to reduce the brightness of the plurality of LEDs provided on the decorative board and the plurality of LEDs provided on each of the decorative boards of the game board 4.

After step S1004, the effect control program sets the value 0 to the V blank signal detection flag VB-FLG (step S1006). The V blank signal detection flag VB-FLG is a flag for determining whether or not to execute the peripheral control unit steady process, which will be described later. Is not set, the value is set to 0. The V blank signal detection flag VB-FLG is a peripheral control, which will be described later, triggered by the input of the V blank signal from the sound source built-in VDP 4160a, which indicates that the screen data from the peripheral control MPU 4150a can be received. The value 1 is set in the V blank signal interrupt process. In this step S1006, the V blank signal detection flag VB-FLG is set to the value 0 to initialize the V blank signal detection flag VB-FLG once. Also, the peripheral control MPU 4150a outputs a clear signal to the peripheral control internal WDT 4150af and the peripheral control external WDT 4150e after setting the value 0 to the V blank signal detection flag VB-FLG so that the peripheral control MPU 4150a is not reset. There is.

Following step S1006, the effect control program determines whether or not the V blank signal detection flag VB-FLG has a value of 1 (step S1008). When the V blank signal detection flag VB-FLG is not 1 (value 0), the process returns to step S1008 and it is repeatedly determined whether the V blank signal detection flag VB-FLG is 1 or not. By repeating such a determination, a standby state is entered until the peripheral control unit steady process is executed. The peripheral control MPU 4150a outputs a clear signal to the peripheral control internal WDT 4150af and the peripheral control external WDT 4150e after determining whether or not the V blank signal detection flag VB-FLG has a value of 1, and resets the peripheral control MPU 4150a. I try not to get it covered.

When the V blank signal detection flag VB-FLG has a value of 1 in step S1008, that is, when the peripheral controller steady processing is executed, first, the steady processing in-progress flag SP-FLG is set to a value of 1 (step S1009). The steady processing in-progress flag SP-FLG is set to a value of 1 when the peripheral control unit steady processing is being executed and to a value of 0 when the peripheral control unit steady processing is completed.

Subsequent to step S1009, the effect control program performs a 1 ms interrupt timer starting process (step S1010). In this 1ms interrupt timer activation process, the 1ms interrupt timer for executing the peripheral control unit 1ms timer interrupt process, which will be described later, is activated, and the number of times the 1ms interrupt timer is activated and the peripheral control unit 1ms timer interrupt process is executed. Also, the value 1 is set to the 1 ms timer interrupt execution count STN for counting the 1 ms timer interrupt execution count STN. The 1 ms timer interrupt execution count STN is updated by the peripheral controller 1 ms timer interrupt processing.

Following step S1010, the effect control program performs a lamp data output process (step S1012). In this lamp data output processing, the production control program DMAs to a plurality of game board side peripheral control MPU control target decorative boards which are control objects directly controlled by the peripheral control MPU 4150a among the decorative boards of the game board 4. Perform serial serial transmission. Here, the peripheral control DMA controller 4150ac of the peripheral control MPU 4150a shown in FIG. 18 is used to perform continuous transmission of the game board side decorative board serial I/O port. When the serial I/O port continuous transmission for the game board side decoration board is started, the game board side peripheral control MPU control target LED transmission data storage of the peripheral control RAM 4150c externally attached to the peripheral control MPU 4150a shown in FIG. In the area 4150caa, a gaming board side for outputting a lighting signal, a blinking signal, or a gradation lighting signal to a plurality of LEDs (decorative LEDs) provided on each of the plurality of gaming board side peripheral control MPU control target decorative boards The light emission data SL-DAT is in a state of being created and set by the lamp data creating process described later.

The peripheral control CPU core 4150aa of the peripheral control MPU 4150a shown in FIG. 18 specifies the transmission of the game board side decorative board serial I/O port as the request factor of the peripheral control DMA controller 4150ac, and the game board side peripheral control MPU control target The first 1 byte of the game board side light emission data SL-DAT stored in the head address of the LED transmission data storage area 4150caa is played through the external bus 4150h, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai. Transfer and write to the transmission buffer register of the serial I/O port for the board side decorative board. As a result, the game board side decorative board serial I/O port transfers the written data in the transmission buffer register to the transmission shift register, and the transmission shift register 1 is synchronized with the frame side light emission clock signal STL-CLK. Transmission of byte data is started bit by bit.

Each time the peripheral control DMA controller 4150ac generates a transmission interrupt request of the game board side decorative board serial I/O port, this triggers (in the present embodiment, the game board side decorative board serial I/O port This is triggered by the fact that the 1-byte data written in the transmission buffer register is transferred to the transmission shift register and the transmission buffer register is emptied of the 1-byte data.), the peripheral control CPU core 4150aa uses the bus. When the game board side peripheral control MPU control target LED transmission data storage area 4150caa is not used, the remaining game board side light emission data SL-DAT stored in the external board 4150h and peripheral control bus controller are byte by byte. The serial I/O port for the game board side decorative board is written by transferring and writing it to the transmission buffer register of the game board side decorative board serial I/O port via 4150ad and the peripheral bus 4150ai. The data of the transmission buffer register is transferred to the transmission shift register, and 1 byte of data of the transmission shift register is started to be transmitted bit by bit in synchronization with the frame side light emission clock signal STL-CLK. /O port is continuously transmitting.

Further, in the lamp data output process, the production control program DMA serializes a plurality of frame-side peripheral control MPU control target decorative substrates, which are control targets to be directly controlled by the peripheral control MPU 4150a, among the decorative substrates of the door frame 5. Performs continuous transmission processing. Also in this case, the peripheral control DMA controller 4150ac of the peripheral control MPU 4150a is used to perform serial transmission of the frame side decorative board serial I/O port. When this frame-side decorative substrate serial I/O port continuous transmission is started, the frame-side peripheral control MPU control target LED transmission data storage area 4150cab of the peripheral control RAM 4150c externally attached to the peripheral control MPU 4150a shown in FIG. In addition, frame-side light emission data STL-DAT for outputting a lighting signal, a blinking signal, or a gradation lighting signal to a plurality of LEDs (decorative LEDs) provided on each of the plurality of frame-side peripheral control MPU control target decoration boards Has been created and set in the lamp data creation process described later.

The peripheral control CPU core 4150aa of the peripheral control MPU 4150a specifies the transmission of the frame side decorative board serial I/O port as the request factor of the peripheral control DMA controller 4150ac, and the frame side peripheral control MPU control target LED transmission data storage area 4150cab The first 1 byte of the frame side light emission data STL-DAT stored in the top address of the frame side decorative board is serially I/O through the external bus 4150h, the peripheral control bus controller 4150ad and the peripheral bus 4150ai. Transfer to the port transmit buffer register and write. As a result, the frame side decorative board serial I/O port transfers the written data of the transmission buffer register to the transmission shift register, and synchronizes with the frame side light emission clock signal STL-CLK to transmit 1 byte of the transmission shift register. The data of 1 is started to be transmitted bit by bit.

The peripheral control DMA controller 4150ac triggers each time a transmission interrupt request of the frame-side decoration board serial I/O port occurs (in this embodiment, the frame-side decoration board serial I/O port transmission buffer). The peripheral control CPU core 4150aa uses the bus when the 1-byte data written in the register is transferred to the transmission shift register and the transmission buffer register is emptied of the 1-byte data.) If not, the remaining frame side light emission data STL-DAT stored in the frame side peripheral control MPU control target LED transmission data storage area 4150cab is byte by byte, the external bus 4150h, the peripheral control bus controller 4150ad, and the peripheral. By transferring and writing to the transmission buffer register of the frame side decoration board serial I/O port via the bus 4150ai, the frame side decoration board serial I/O port writes the written data of the transmission buffer register. Transfer to the transmission shift register, start transmitting 1-byte data of the transmission shift register bit by bit in synchronization with the frame side light emission clock signal STL-CLK, and continuously transmit by the frame side decoration board serial I/O port. Is going.

Following step S1012, the effect control program performs operation unit monitoring processing (step S1014). In this operation unit monitoring process, in the operation unit information acquisition process in the peripheral control unit 1ms timer interrupt process described later, the dial operation unit 401 is based on detection signals from various detection switches provided in the operation unit 400 shown in FIG. Rotation (rotation direction) and various information obtained by operating the pressing operation unit 405 (for example, rotation (rotation direction of dial operation unit 401 that is created based on detection signals from various detection switches provided in operation unit 400). ) History information, operation history information of the pressing operation section 405, etc.) are set based on the operation unit information acquisition storage area 4150cai of the peripheral control RAM 4150c shown in FIG. Whether or not the portion 405 is operated is monitored, and it is appropriately determined whether or not the rotational direction of the dial operation portion 401 and the operation state of the pressing operation portion 405 are reflected in the game effect.

Following step S1014, the effect control program performs a display data output process (step S1016). In this display data output process, one screen (one frame) of drawing data generated on the built-in VRAM of the sound source built-in VDP 4160a by the display data creation process described later is transferred from the channels CH1 and CH2 shown in FIG. 19 to the sound source built-in VDP 4160a. Output. Thereby, various screens (images) corresponding to one light guide plate used as a backlight among the plurality of light guide plates included in the game board side effect display unit 1900 shown in FIG. 10 are drawn (displayed) on the liquid crystal panel 5000e. In addition, among the decorative boards of the game board 4, a plurality of LEDs (ornamental LEDs) provided on each of the plurality of game board-side VDP controlled decorative boards that are directly controlled by the sound source built-in VDP 4160a Are emitted in various light emitting modes, and among the decorative substrates of the door frame 5, a plurality of LEDs provided on each of a plurality of frame-side VDP controlled decorative substrates that are directly controlled by the sound source built-in VDP 4160a. The (decorative LED) emits light in various emission modes. In the display data output process, if drawing is performed that exceeds the drawing capability of the sound source built-in VDP 4160a, the output of the generated drawing data for one screen (one frame) from the channels CH1 and CH2 is canceled. It has become. This makes it possible to prevent the processing time from being delayed, but although so-called frame drop occurs, it is accommodated in the speaker box 820 provided in the main body frame 3 shown in FIG. 5 by the sound data output processing described later. The speaker and the speaker 130 provided on the door frame 5 shown in FIG. 2 have a mechanism that can give priority to effects such as music and sound effects according to various effects.

Following step S1016, the effect control program performs a sound data output process (step S1018). In this sound data output processing, the effect control program outputs to the audio data transmission IC 4160c as serialized audio data of sound data such as music and sound effects set in the sound source built-in VDP 4160a in the sound data creation processing described later, In addition to music and sound effects, the sound data of the notification sound and the notification sound is output as serialized audio data to the audio data transmission IC 4160c. When the audio data transmission IC 4160c receives the serialized audio data from the VDP 4160a with a built-in sound source, the right audio data is sent to the frame decoration drive amplifier board 194 as serial data of a differential method in which a plus signal and a minus signal are used. At the same time as the transmission, the left audio data is transmitted toward the frame decoration drive amplifier board 194 as serial data of a differential method that is a plus signal and a minus signal. As a result, the music accommodated in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 are played back in stereo in addition to the music, sound effects, and the like in addition to the notification sound and the notification sound. Is also played in stereo.

Following step S1018, the effect control program performs a scheduler update process (step S1020). In this scheduler update process, the effect control program updates various schedule data set in the schedule data storage area 4150cae of the peripheral control RAM 4150c shown in FIG. For example, in the scheduler update process, of the screen data arranged in chronological order that forms the screen generation schedule data set in the schedule data storage area 4150cae, the screen data from the first screen data to the VDP 4160a with the built-in sound source. Update the pointer to indicate whether to output.

In addition, in the scheduler update process, of the emission data arranged in time series which configures the emission mode generation schedule data set in the schedule data storage area 4150cae, the emission data from the first emission data to the plurality of LEDs are output. The pointer is updated in order to instruct whether to use the light emission mode. Here, as described above, the emission mode generation schedule data is provided on each decorative board of the game board 4 (a plurality of game board side peripheral control MPU control target decorative boards, a plurality of game board side VDP control target decorative boards). The emission mode generation schedule data for the plurality of LEDs, and the plurality of LEDs provided on each of the decoration boards (the plurality of frame side peripheral control MPU control target decoration boards, the plurality of frame side VDP control target decoration boards) of the door frame 5 The light emission mode generation schedule data, the sequence of the bittern, and the light emission mode are defined. Further, the schedule data for light emission mode generation for the plurality of LEDs provided on each decorative board of the game board 4 includes, in addition to the content for defining the light emission mode, a plurality of light guide plates provided in the game board side effect display unit 1900. Among them, the content for specifying (designating) one light guide plate used as a backlight is included in the emission data and arranged in time series.

Further, in the scheduler update process, the sound data such as music and sound effects, and the sound data such as the notification sound and the notification sound, which are arranged in time series and constitute the sound generation schedule data set in the schedule data storage area 4150cae, are instructed. Of the sound command data, the pointer is updated in order to instruct which sound command data is output from the head sound command data to the sound source built-in VDP 4160a.

Further, in the scheduler update process, from the first drive data among the drive data of the electric drive sources such as the motors and solenoids arranged in chronological order which form the electric drive source schedule data set in the schedule data storage area 4150cae. The pointer is updated to instruct which drive data is to be output. The drive data of the electric drive sources such as motors and solenoids arranged in time series, which form the electric drive source schedule data, is the peripheral control unit 1ms timer interrupt, which is repeatedly executed every time a 1ms timer interrupt occurs, which will be described later. It is updated by the motor and solenoid drive processing in the processing. In the motor and solenoid drive processing that is repeatedly executed each time this 1 ms timer interrupt occurs, the electric drive sources such as the motor and solenoid are driven in accordance with the drive data designated by the pointer, and the next drive specified in time series is performed. The pointer is updated to the data, and the pointer is updated each time the own processing is executed. In other words, the drive data designated by the pointer updated in the motor/solenoid drive process is forcibly updated in the scheduler update process. Even if the other drive data is instructed from the drive data to be instructed, it is forcibly updated to instruct the drive data originally instructed in the scheduler update process.

Further, in the scheduler update processing, the number of game balls to be paid out as prize balls arranged in time series constituting the main prize ball information output signal schedule data set in the schedule data storage area 4150cae becomes 10 balls. Of the output waveform data for generating the main award sphere information output signal that informs the hall computer that it has reached the main award sphere information, the output waveform data from the first output waveform data Update the pointer to point. The output waveform data arranged in time series, which constitutes the main prize ball information output signal schedule data, is the number of main prize balls in the peripheral control unit 1 ms timer interrupt process, which is repeatedly executed every time a 1 ms timer interrupt occurs, which will be described later. Updated in the information output process. In the main prize sphere number information output processing which is repeatedly executed each time this 1 ms timer interrupt occurs, the main prize sphere information output signal is output to the external terminal board 784 in accordance with the output waveform data designated by the pointer, and is defined in time series. The pointer is updated to the next output waveform data that has been generated, and the pointer is updated each time the own processing is executed. In other words, the output waveform data pointed to by the pointer updated in the main prize ball number information output process is forcibly updated in the scheduler update process. Even if the output waveform data that should have been instructed is instructed to other output waveform data for some reason, it is forcibly updated to instruct the output waveform data that was originally instructed in the scheduler update process. It has become.

Following step S1020, the effect control program performs received command analysis processing (step S1022). In this received command analysis processing, the production control program receives various commands transmitted from the main control board 4100 in peripheral control unit command reception interrupt processing, which will be described later, and analyzes the received various commands. Various commands from the main control board 4100 are received by the peripheral control unit command reception interrupt processing and stored in the reception command storage area 4150cac of the peripheral control RAM 4150c. In this reception command analysis processing, the production control program is executed. Analyzes various commands stored in the received command storage area 4150cac. Based on the analyzed various commands, the effect control program stores the screen generation schedule data, the light emission mode generation schedule data, the sound generation schedule data, the electric drive source schedule data, and the like in the peripheral control ROM 4150b of the peripheral control unit 4150. Alternatively, it is extracted from various control data copy areas 4150ce of the peripheral control RAM 4150c and set in the schedule data storage area 4150cae of the peripheral control RAM 4150c.

In addition, the production control program, the command from the main control board 4100 received in the peripheral control unit command interrupt processing, for example, the start mouth winning command for instructing the start of the start mouth winning effect, the number of ordinary symbols held Normal symbol storage command for identifying (0 to 4), symbol synchronization effect start command for instructing the start of symbol synchronization effect, symbol storage command output when the number of starting suspension changes, special winning opening 2103 It is analyzed whether or not it is the special winning opening 1 count display command (big winning opening count command) output each time the game ball is accepted, or the frame state 1 command indicating the content of full tank shown in FIG. , Recognize which gaming state it is currently in.

Various commands from the main control board 4100 are received by the peripheral control unit command reception interrupt processing and are stored in the reception command storage area 4150cac of the peripheral control RAM 4150c shown in FIG. The effect control program analyzes various commands stored in the received command storage area 4150cac. The various commands are shown in FIG. 45, which are classified into special figure 1 tuning effect-related, various commands which are classified into special figure 2 tuning effect-related, various commands which are classified into jackpot-related, and classified into power-on. Shown in FIG. 46, various commands classified into notification display, and status display shown in FIG. 46. There are various commands, various commands related to test, and various other commands.

Following step S1022, the effect control program performs warning processing (step S1024). In this warning process, when the command analyzed by the reception command analysis process of step S1022 as described above includes various commands classified into the notification display shown in FIG. The peripheral control unit 4150 stores the screen generation schedule data, the light emission mode generation schedule data, the sound generation schedule data, the electric drive source schedule data, and the like, which are set in the abnormality display mode for executing the abnormality notification. It is extracted from various control data copy areas 4150ce of the peripheral control ROM 4150b or the peripheral control RAM 4150c and set in the schedule data storage area 4150cae of the peripheral control RAM 4150c. In the warning process, when a plurality of abnormalities occur at the same time, the abnormality notification is performed in order from the highest priority registered in advance, and the abnormality is automatically resolved and the other abnormalities are automatically notified. It is supposed to do. This allows multiple abnormalities to be monitored simultaneously without losing the information that one abnormality has occurred after another abnormality has occurred and before the abnormality has been resolved. You can

Next, following step S1024 described above, the effect control program performs main prize ball number information output determination processing (step S1025). In this main prize sphere number information output determination process, when the command analyzed by the received command analysis process of step S1022 is the main prize sphere number information output command classified into other shown in FIG. Based on the value of the peripheral control side main award ball number information output determination counter, the main award that informs the hall computer as the main award ball information that the number of game balls to be paid out as a prize ball has reached 10 It is determined whether to output the ball information output signal to the external terminal board 784. This peripheral control side main prize sphere number information output determination counter is determined as a prize sphere based on the other main prize sphere number information output commands shown in FIG. 46 analyzed by the received command analysis processing of step S1022. It counts the number of game balls to be paid out, and is stored and updated in a prize ball schedule information storage area (not shown) of the peripheral control RAM 4150c. As shown in FIG. 46, the main prize ball number information output command classified into other ones informs that the number of game balls to be paid out as prize balls has reached 10 balls, as described above. When this main prize ball number information output command is received, the value 10 is added to the value of the peripheral control side main prize ball number information output determination counter, and the value is stored and updated in the prize ball schedule information storage area (not shown) of the peripheral control RAM 4150c. It has become so.

In the main prize ball number information output determination process, the production control program is for power-on main prize ball number information output determination in which the command analyzed in the received command analysis process of step S1022 is classified into the power-on shown in FIG. 45. When it is a counter notification command, the main control board 4100 is provided on the game board 4 based on the content of the counter notification command for determining the main prize number information output at power-on. Main ball counting the number of game balls to be paid out as prize balls based on the game balls that have entered the various winning openings such as 2101, the second starting opening 2102, the general winning openings 2104, 2201, and the special winning opening 2103. The value of the prize ball number information output determination counter is set as the initial value of the peripheral control side main prize ball number information output determination counter, while the command analyzed by the received command analysis processing in step S1022 is shown in FIG. When the main award ball number information output command is classified into, the main award ball number information output command informs that the number of game balls to be paid out as a prize ball has reached 10 balls. The value 10 is added to the value of the peripheral control side main prize ball number information management counter.

In the main prize ball number information output determination process, the effect control program determines that the command analyzed by the received command analysis process of step S1022 is classified into the power-on shown in FIG. 45 when the power is turned on. When it is a counter notification command for use, the main control board 4100 is provided on the game board 4 based on the contents of the counter notification command for determining the main prize ball number information output at power-on. The number of game balls to be paid out as prize balls is counted based on the game balls that have entered the various winning holes such as the mouth 2101, the second starting hole 2102, the general winning holes 2104, 2201, and the special winning hole 2103. When the value of the main prize ball number information output determination counter is set as the initial value of the peripheral control side main prize ball number information output determination counter, it is acquired in the current time information acquisition process of step S1002 and shown in FIG. Based on the time information set in the time information storage unit in the RTC information acquisition storage area 4150cad of the peripheral control RAM 4150c, the pachinko gaming machine 1 is powered on (or the pachinko gaming machine 1 to start the business of the hall). When it is determined that the power has been turned on to the Pachinko Island facility where the is installed, the initial value is set by forcibly resetting the value of the peripheral control side main prize ball number information management counter and setting it to the default value. The value is returned to a value of 0 (zero) and updated in a prize ball schedule information storage area (not shown) of the peripheral control RAM 4150c (for example, the command analyzed by the received command analysis processing of step S1022 is turned on as shown in FIG. 45). This is a counter notification command for determining the power-on main prize ball number information output determination, and this power-on main prize ball number information output determination counter notification command indicates that the value of the main prize ball number information output determination counter is the value 9. When the value 9 is set as the initial value of the peripheral control side main prize ball number information output determination counter, it is reset and the default value 0 (value 0 When the command analyzed by the received command analysis processing of step S1022 is the main prize ball number information output command classified into other shown in FIG. Each time the information output command is received, the value of the peripheral control side main prize ball number information output determination counter is incremented by 10. That is, the main control board 4100 side The value of the main award sphere number information output determination counter updated by the same value as the value of the peripheral control side main award sphere number information output determination counter updated on the peripheral control board 4140 side. ) On the other hand, when it is determined that the power to the pachinko gaming machine 1 has not been turned on in order to start the business of the hall, but that the power is restored due to a power failure or a momentary interruption during the business of the hall. The value of the peripheral control side main award sphere number information management counter is not reset to the initial value 0 (zero) by forcibly resetting the value of the peripheral control side main award sphere number information management counter. (For example, the command analyzed by the received command analysis processing of step S1022 is a power-on main prize ball number information output determination counter notification command classified into power-on shown in FIG. 45. When the command for notifying the main prize ball number information output determination counter at the time of insertion indicates that the value of the main prize ball number information output determination counter is the value 9, this value 9 is the peripheral control side main prize ball. This is set as the initial value of the number information output determination counter, whereby the command analyzed by the received command analysis processing in step S1022 is the main prize ball number information output command classified into the other categories shown in FIG. Is set to the value 9 set as the value of the main prize ball number information output determination counter, which is the value of the peripheral control side main prize ball number information output determination counter, each time this main prize ball number information output command is received. The value is added to 10. That is, the value of the main prize ball number information output determination counter updated on the main control board 4100 side and the peripheral control side main prize ball number updated on the peripheral control board 4140 side. The value of the information output judgment counter does not become the same value).

Then, in the main prize ball number information output determination processing, the effect control program determines the value of the peripheral control side main prize ball number information management counter based on the added value of the peripheral control side main prize ball number information management counter. When the number exceeds 10 (that is, when the number of game balls to be paid out as a prize ball reaches 10 balls), a main prize ball information output signal for notifying the fact to the hall computer as main prize ball information. The main prize ball information output signal schedule data to be output to the external terminal board 784 is set in the schedule data storage area 4150cae of the peripheral control RAM 4150c shown in FIG. The value of the control-side main prize ball number information management counter is stored and updated in a prize ball schedule information storage area (not shown) of the peripheral control RAM 4150c.

Here, in the main prize ball number information output determination processing, a main prize ball information output signal is transmitted to the hall computer as main prize ball information that the number of game balls to be paid out as prize balls has reached 10 balls. The point of maintaining or resetting the value of the peripheral control side main prize ball number information output determination counter for determining whether to output to the external terminal board 784 will be described. First, at the time of power restoration, without judging whether the power is turned on from the power-off state or the power is restored from a power failure or a momentary power failure, at step S1022 If the command analyzed by the received command analysis processing is the counter notification command for power-on main prize ball number information output determination counter classified into power-on shown in FIG. 45, this power-on main prize ball number information output determination Based on the content indicated by the counter notification command for use, the main control board 4100 is provided on the game board 4 as shown in FIG. 8, the first starting opening 2101, the second starting opening 2102, the general winning openings 2104 and 2201, and the big winning. The value of the main prize ball number information output determination counter that counts the number of game balls that are to be paid out as prize balls based on the game balls that have entered the various prize holes such as the mouth 2103 is the peripheral control side main prize ball number. A problem in the case where the information output determination counter is directly set as the initial value will be described.

First, as described above, the main control MPU 4100a of the main control board 4100 enters the general winning openings 2104 and 2201 shown in FIG. 8 in the switch input processing of step S104 in the main control side timer interrupt processing shown in FIG. The detection signals from the general winning opening switches 3020 and 3020 shown in FIG. 14 that detect the game balls that have hit the ball, the count switch 2110 shown in FIG. 14 that detects the game balls that entered the special winning opening 2103 shown in FIG. The detection signal from, the detection signal from the first starting port switch 3022 shown in FIG. 14 which detects the game ball that has entered the first starting port 2101 shown in FIG. 8, the second starting port 2102 shown in FIG. Each of the detection signals and the like from the second starting port switch 2109 shown in FIG. 14 for detecting the game ball entered in is read and stored in the input information storage area of the main control internal RAM as input information, The input information is read from the input information storage area of the main control built-in RAM, and based on this input information, in the prize ball control processing of step S108 in the same processing, the number of game balls to be paid out as prize balls is counted. The value of the main prize ball number information output determination counter is updated and stored, and the value of the main prize ball number information output determination counter reaches the value 10 based on the value of the main prize ball number information output determination counter. (That is, when the number of game balls to be paid out as a prize ball has reached 10), the main prize ball number information output command shown in FIG. Is created and stored as transmission information in the transmission information storage area. Then, the main control MPU 4100a of the main control board 4100 transmits the main prize ball number information output command to the peripheral control board 4140 in the peripheral control board command transmission processing of step S120 in the same processing.

A staff member such as a clerk of the hall may perform maintenance with the power of the pachinko gaming machine 1 left on until midnight over the day after the hall is closed. In such a case, after the maintenance is completed, Even when the power supply to the pachinko island facility in which the pachinko gaming machine 1 is installed is cut off, the power is stored in the capacitor BC0 as a backup power supply provided in the power supply board 851 shown in FIG. However, power is supplied to the main control board 4100 for a predetermined time. As a result, the power (electric power) stored in the capacitor BC0 is completely discharged until the power to the pachinko island facility is turned off and the power to the pachinko island facility is turned on again to start the opening of the hall. If not, the capacitor BC0 causes the main control MPU 4100a to be in a state where various information is stored and held in the main control built-in RAM. Then, when an employee such as a store clerk in the hall does not operate the operation switch 860a of the payout control board 4110 to initialize the main control internal RAM (game storage unit) for a predetermined time after the power is turned on, In step S34 of the main control side power-on process shown in FIG. 48, various kinds of information are read from the game backup information and various commands corresponding to the various kinds of information are stored in a predetermined storage area of the main control built-in RAM. Since the state is restored and the value of the main prize ball number information output determination counter of yesterday is inherited as it is, in the peripheral control board command transmission process of step S120 in the main control side timer interrupt process shown in FIG. , The problem of transmitting the main prize ball number information output command to the peripheral control board 4140 occurs.

Therefore, in the present embodiment, the effect control program causes the command analyzed in the received command analysis processing in step S1022 in the main prize ball number information output determination processing in step S1025 to be classified as the power-on shown in FIG. When the command is a notification notification counter for determining the number of main prize ball information output at throw-in, the main control board 4100 is provided on the game board 4 based on the contents instructed by the counter notification command for determining the information output main prize ball count information at power-on. Scheduled to be paid out as prize balls based on the game balls that have entered the various winning openings such as the first starting opening 2101, the second starting opening 2102, the general winning openings 2104, 2201, and the big winning opening 2103 shown in FIG. At the time of setting the value of the main prize ball number information output determination counter that has counted the number of game balls as the initial value of the peripheral control side main prize ball number information output determination counter, the current time information acquisition process of step S1002 In accordance with the time information set in the time information storage unit in the RTC information acquisition storage area 4150cad of the peripheral control RAM 4150c shown in FIG. (In order to start the maintenance) in the pre-business period (in the present embodiment, the period is set from midnight to 9:00 and is stored in the peripheral control ROM 4150b in advance). , It is determined that the pachinko gaming machine 1 is powered on (or the pachinko island facility where the pachinko gaming machine 1 is installed is powered on) to start the hall business. In this case, the value of the peripheral control side main prize sphere number information management counter is forcibly reset and set to the default value to return to the initial value 0 (zero), and the prize sphere plan information (not shown) in the peripheral control RAM 4150c. While the information is updated in the storage area, this time information is not the pre-business start period for starting the business of the hall (or for starting the maintenance of the pachinko gaming machine 1) (in the present embodiment, the business period of the hall). If it is within ), it is not that the power to the pachinko gaming machine 1 has been turned on in order to start the business of the hall, but the power is restored due to a power outage or momentary interruption during the hall operation. When it is determined that the number of main prize balls on the peripheral control side is not reset to 0 (zero) as an initial value by forcibly resetting the value of the information management counter on the peripheral control side and setting it to the default value, We adopted a mechanism to maintain the value of the information management counter as it is.

This makes it extremely unlikely that a power outage or momentary blackout will actually occur before the opening and closing of the hall, but if a power outage or momentary blackout occurs, the hall is already open. When the power is restored, the main control board 4100 is provided on the game board 4 based on the content of the counter notification command for determining the main prize ball number information output at power-on from the main control board 4100. The number of game balls to be paid out as prize balls based on the game balls that have entered the various winning openings such as the first starting opening 2101, the second starting opening 2102, the general winning openings 2104, 2201, and the special winning opening 2103. When setting the value of the main prize ball number information output determination counter that has counted as the initial value of the peripheral control side main prize ball number information output determination counter, the number of game balls to be paid out as prize balls is 10 Peripheral control side main prize ball number information output determination counter for determining whether or not to output the main prize ball information output signal that informs the hall computer that the ball has been reached to the main computer as main prize ball information By maintaining that value without forcibly resetting the value of, the value of the main prize ball number information output judgment counter immediately before the occurrence of a power failure or momentary power failure At the time of power recovery due to recovery (recovery), it is succeeded and set as the value of the peripheral control side main prize ball number information output determination counter.

On the other hand, when the business of the hole is finished and the business of the hole is restarted, the fact that the number of game balls to be paid out as the prize balls has reached 10 is sent to the hall computer as the main prize ball information. To forcibly reset and set the default value of the peripheral control side main prize ball number information output determination counter for determining whether to output the transmitted main prize ball information output signal to the external terminal board 784. The initial value was returned to 0 (zero), and when the pachinko machine 1 was shut down after the hall was closed (or the pachinko island facility where the pachinko machine 1 was installed was shut down). At the time point), the value of the main prize ball number information output determination counter is restored at the time of power restoration by turning on the power to the pachinko gaming machine 1 to start the business of the hall (or the pachinko island facility where the pachinko gaming machine 1 is installed). When the power is turned on, the value of the peripheral control side main award sphere number information output determination counter does not continue even if it is set as the value of the peripheral control side main award sphere number information output determination counter. Is reset to the default value by forcibly resetting and resetting it to the initial value 0 (zero), so it is updated and memorized until the opening and closing of the hall business. The value of the peripheral control side main prize ball number information output determination counter is updated based on the main prize ball number information output command from the main control board 4100 transmitted based on the value of the prize ball number information output determination counter. This makes it possible to determine whether or not to output the main prize sphere number information to the external terminal board 784 based on the value of the peripheral control side main prize sphere number information output determination counter. Thereby, based on the value of the peripheral control side main prize ball number information output determination counter, accurate main prize ball information can be output from the peripheral control board 4140 to the hall computer via the external terminal board 784. As described above, the main prize ball number information is obtained from the light-colored output terminal PT10 of the external terminal board 784 to the first starting port 2101, the second starting port 2102, the general winning port 2104 shown in FIG. Main prize ball number information output that informs that the number of game balls planned to be paid out as a prize ball based on the game balls entered into various prize holes such as 2201 and the special prize hole 2103 reaches 10 balls It is output as a signal to the hall computer. Therefore, the hall computer can accurately grasp the number of game balls to be paid out until the opening and ending of the business of the hall.

Next, following step S1025 described above, the effect control program performs RCT acquisition information update processing (step S1026). In this RTC acquisition information update processing, the effect control program stores it in the calendar information storage unit which is acquired in the current time information acquisition processing in step S1002 and set in the RTC information acquisition storage area 4150cad of the peripheral control RAM 4150c shown in FIG. The calendar information and the time information stored in the time information storage unit are updated. By this RCT acquisition information update processing, the hour, minute, second, which is the time information stored in the time information storage unit, is updated, and the year, month, which is the calendar information stored in the calendar information storage unit based on the updated time information. The day is updated.

Following step S1026, the effect control program performs power consumption monitoring processing (step S1027). The power consumption monitoring process is a process for adjusting the volume and the brightness of various LEDs in order to suppress the power consumption in accordance with the power consumption of the pachinko gaming machine 1, and a detailed description thereof will be given later. To do.

Following step S1027, the effect control program performs lamp data creation processing (step S1028). In this lamp data creation process, the pointer is instructed by the pointer in the emission control program, in which the pointer is updated in the scheduler update process of step S1020, and the emission data is arranged in time series constituting the emission mode generation schedule data. Based on the light emission data, the plurality of LEDs provided on each of the plurality of gaming board side peripheral control MPU control target decorative boards, which are control objects to be directly controlled by the peripheral control MPU 4150a, of each decorative board of the game board 4. The game board side light emission data SL-DAT for outputting a lighting signal, a blinking signal, or a gradation lighting signal to the (decorative LED) is copied to various control data of the peripheral control ROM 4150b of the peripheral control unit 4150 or the peripheral control RAM 4150c. Created by extracting from the area 4150ce and setting it in the game board side peripheral control MPU control target LED transmission data storage area 4150caa of the peripheral control RAM 4150c, and of the decorative boards of the door frame 5, the peripheral control MPU 4150a directly controls. Frame-side light emission for outputting a lighting signal, a blinking signal, or a gradation lighting signal to a plurality of LEDs (decorative LEDs) provided on each of the plurality of frame-side peripheral control MPU control target decoration boards that are controlled The data STL-DAT is created by extracting from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c, and the frame side peripheral control MPU control target LED transmission data storage area 4150cab of the peripheral control RAM 4150c. Set to.

Following step S1028, the effect control program performs display data creation processing (step S1030). In this display data creation process, the effect control program updates the pointer in the scheduler update process of step S1020, and among the screen data arranged in time series that constitutes the screen generation schedule data, the screen data indicated by the pointer. Is output from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c and output to the sound source built-in VDP 4160a, and the pointer is updated in the scheduler update process of step S1020 to generate the light emission mode. Peripheral control ROM 4150b of peripheral control unit 4150 is controlled by the sound source built-in VDP 4160a to be directly controlled, based on the emission data pointed by the pointer, among the emission data arranged in time series constituting the schedule data. Alternatively, it is extracted from various control data copy areas 4150ce of the peripheral control RAM 4150c and output to the sound source built-in VDP 4160a.

When the screen data and the light emission data are input from the peripheral control MPU 4150a, the sound source built-in VDP 4160a, based on the input screen data and the light emission data, from the liquid crystal and sound control ROM 4160b shown in FIG. Game board side character data for drawing in the display area of the effect display unit 1900 and the above-mentioned predetermined screen (in the present embodiment, red (R): 50%, green (G): 50%, blue (B)). : Gray data having 50%) and dummy data for drawing and creating sprite data and drawing (displaying) on the game board side effect display unit 1900 (liquid crystal panel 5000e). Drawing data of one frame) and a predetermined screen (in the present embodiment, a gray screen having red (R): 50%, green (G): 50%, blue (B): 50%) Drawing data of one screen (one frame) to be (displayed) is generated in the built-in VRAM.

Specifically, the sound source built-in VDP 4160a is a VDP 4160a with a built-in sound source among screen data defining the configuration of a screen drawn on the game board side effect display unit 1900 (liquid crystal panel 5000e) and each decorative board of the game board 4. Is input from the peripheral control MPU4150a, and the light emission data defining the light emission mode of the plurality of LEDs (decorative LEDs) provided on each of the plurality of game board side VDP control target decoration substrates that are directly controlled by Then, according to the above-mentioned predetermined game board side generation rule, the game board side character for drawing from the liquid crystal and sound control ROM 4160b in the display area of the game board side effect display unit 1900 based on the input screen data. Data is extracted and sprite data is created to generate game board side drawing data in the game board side drawing data area VRGN1a of the game board side display area VRGN1 provided on the built-in VRAM, and this input light emission data is generated. On the basis of the above, from the liquid crystal and sound control ROM 4160b, among the respective decorative boards of the game board 4, a plurality of decorative boards provided on the respective game board side VDP control objects to be controlled by the sound source built-in VDP 4160a are directly provided. Game board side display area VRGN1 provided on the built-in VRAM by extracting the game board side light emission mode setting image data for setting the light emitting mode of the LED (decorative LED) and using the light guide plate information and the electric decoration information as drawing data. It is generated in the game board side accompanying information area VRGN1b. The effect control program is a predetermined game board in which the light guide plate information and the illumination information are added to the game board side drawing data of the screen drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e) in this way. The drawing data generated in the game board side display area VRGN1 is output from the channel CH1 of the sound source internal information VDP4160a shown in FIG. 19 in the display data output processing of step S1016, as attached according to the side generation rule.

Further, the sound source built-in VDP 4160a defines the configuration of a predetermined screen (a gray screen having red (R): 50%, green (G): 50%, and blue (B): 50% in this embodiment). Screen data and a plurality of LEDs (decorative LEDs) provided on each of a plurality of frame-side VDP control target decorative boards that are directly controlled by the sound source built-in VDP 4160a among the decorative boards of the door frame 5. When the light emission data defining the light emission mode of No. 4 is input from the peripheral control MPU 4150a, the predetermined control is performed from the liquid crystal and sound control ROM 4160b based on the input screen data according to the predetermined door frame side generation rule described above. Sprite data by extracting dummy data for drawing a different screen (gray screen having red (R): 50%, green (G): 50%, and blue (B): 50% in this embodiment) To generate door frame side drawing data in the door frame side drawing data area VRGN2a of the door frame side display area VRGN2 provided on the built-in VRAM, and generate liquid crystal and sound based on the input light emission data. Light emission from a plurality of LEDs (decorative LEDs) provided on each of a plurality of frame-side VDP control target decorative boards that are control targets that are directly controlled by the sound source built-in VDP 4160a among control boards from the control ROM 4160b to the door frame 5. The door frame side light emission mode setting image data for setting the mode is extracted and the electric decoration information is generated as drawing data in the door frame side accompanying information area VRGN2b of the door frame side display area VRGN2 provided on the built-in VRAM. .. The effect control program is a door frame of such a predetermined screen (in this embodiment, a gray screen having red (R): 50%, green (G): 50%, and blue (B): 50%). It is assumed that the side drawing data is attached with the electric decoration information according to the predetermined door frame side generation rule described above, and the drawing data generated in the door frame side display region VRGN2 is displayed in FIG. 19 by the display data output process of step S1016. It is output from the channel CH2 of the indicated sound source information VDP4160a.

Following step S1030, the effect control program performs sound data creation processing (step S1032). In this sound data creation process, the effect control program updates the pointer in the scheduler update process of step S1020, and the pointer indicates the sound command data arranged in time series that constitutes the sound generation schedule data. The sound command data is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c and output to the sound source built-in VDP 4160a. When the sound command data is input from the peripheral control MPU 4150a, the sound source built-in VDP 4160a extracts sound data such as music and sound effects stored in the liquid crystal and sound control ROM 4160b and controls the built-in sound source to generate a sound command. Sound data such as music and sound effects are incorporated according to the track number defined in the data, and the output channel to be used is set according to the output channel number.

In the sound data creation process, each time the sound data creation process is performed (that is, each time the peripheral control unit steady process is performed), the peripheral control A/D converter 4150ak shown in FIG. The voltage divided by the resistance value at the rotation position of the knob portion of 4140a is converted into a value of 1024 steps from value 0 to value 1023. In the present embodiment, the value of 1024 steps is divided into seven and managed as board volumes 0 to 6, and the board volume 0 is set to mute and the board volume 6 is set to the maximum volume. The volume is set to increase toward the volume 6. By controlling the liquid crystal and the sound source built-in VDP 4160a of the sound control unit 4160 so that the sound volume is set to the board volumes 0 to 6, the audio data is audio data that is serialized by the sound data output process of step S1018 described above. By outputting to the transmission IC 4160c, music and sound effects are made to flow from the speaker accommodated in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5.

In addition, the notification sound and the notification sound have a mechanism that flows without depending on the volume adjustment based on the turning operation of the knob portion at all, and the volume from the mute to the maximum volume is programmed to be the sound source of the liquid crystal and the sound control unit 4160. The built-in VDP 4160a can be controlled and adjusted. The volume adjusted by this program is different from the above-described seven levels of the substrate volume, and it is possible to smoothly change from mute to maximum volume. For example, even when a store clerk or the like in the hall rotates the knob of the volume adjusting volume 4140a to set the volume to a low level, the speaker and the door frame 5 housed in the speaker box 820 provided in the main body frame 3 will not be affected. Although the effect sound such as music and sound effects flowing from the provided speaker 130 is reduced, a large volume (in the present embodiment, when the pachinko gaming machine 1 is in trouble or when the player is conducting an illegal act). The notification sound set to (maximum volume) can be played. Therefore, even if the volume of the effect sound is reduced, it is possible to prevent the clerk or the like in the hall from becoming less likely to notice a malfunction or a player's cheating by the notification sound. Also, based on the current board volume set by the volume adjustment based on the turning operation of the knob, the volume of the advertising sound is reduced so as not to disturb the music or the sound effect, while There is a possibility of increasing the volume of the sound played to increase the volume of the music and sound effects, and also to produce a more powerful screen on the game board side effect display unit 1900, or to shift to a game state advantageous for the player. You can also announce that it is expensive.

Following step S1032, the effect control program performs a backup process (step S1034). In this backup process, the effect control program stores the contents stored in the peripheral control MPU 4150a and the external peripheral control RAM 4150c shown in FIG. 18 in the backup first area 4150cb and the backup second area 4150cc. The contents stored in the peripheral control MPU 4150a and the peripheral control SRAM 4150d externally attached are copied and backed up to the backup first area 4150db and the backup second area 4150dc, respectively.

More specifically, in the backup process, the peripheral control RAM 4150c is backed up every one frame (1 frame) in the backup target work area 4150ca shown in FIG. 18, that is, every time the peripheral control unit steady process is executed. The effect backup information (1fr), which is the content stored in the received command storage area 4150cac, the RTC information acquisition storage area 4150cad, and the schedule data storage area 4150cae, included in Bank 0 (1fr) 1fr), the peripheral control DMA controller 4150ac copies at high speed to Bank1 (1fr) and Bank2 (1fr) of the backup first area 4150cb, and peripheral control to Bank3 (1fr) and Bank4 (1fr) of the backup second area 4150cc. The DMA controller 4150ac copies at high speed.

The high-speed copy of the contents stored in Bank0 (1fr) by the peripheral control DMA controller 4150ac will be briefly described. The peripheral control MPU core 4150aa of the peripheral control MPU 4150a shown in FIG. The contents stored in Bank0(1fr) are designated to copy to the backup first area 4150cb to Bank1(1fr), and the contents stored in the start address of Bank0(1fr) are changed to the end address of Bank0(1fr). The stored contents are sequentially copied by a predetermined number of bytes (for example, 1 byte) in sequence from the start address of Bank 1 (1fr) of the backup first area 4150cb, and the peripheral control MPU core 4150aa makes the peripheral control DMA controller. The request cause of 4150ac specifies that the contents stored in Bank0 (1fr) are copied to Bank2 (1fr) of the backup first area 4150cb, and the contents stored in the start address of Bank0 (1fr) are changed to Bank0 (1fr). Up to the contents stored in the end address of (1) are successively copied by a predetermined number of bytes (for example, 1 byte) sequentially from the top address of Bank2 (1fr) of the backup first area 4150cb.

Then, the peripheral control MPU core 4150aa specifies the copy of the contents stored in Bank0 (1fr) as the request factor of the peripheral control DMA controller 4150ac to Bank3 (1fr) of the backup second area 4150cc, and Bank0 (1fr). ) To the content stored in the end address of Bank0 (1fr) continuously by a predetermined byte (for example, 1 byte), the start address of Bank3 (1fr) of the backup second area 4150cc. From the peripheral control MPU core 4150aa requesting the peripheral control DMA controller 4150ac to copy the contents stored in Bank0 (1fr) to the backup second area 4150cc to Bank4 (1fr). Then, from the content stored at the top address of Bank0 (1fr) to the content stored at the end address of Bank0 (1fr), a predetermined number of bytes (for example, 1 byte) are continuously contiguous by Bank4 (in the second area 4150cc). 1fr) are all copied in order from the start address.

In the backup process, the peripheral control SRAM 4150d is a backup target for each frame (1 frame) in the backup target work area 4150da shown in FIG. 18, that is, for each time the peripheral control unit steady process is executed. The peripheral control DMA controller 4150ac operates at high speed in the effect information (SRAM) stored in Bank0 (SRAM) as effect effect backup information (SRAM) in Bank1 (SRAM) and Bank2 (SRAM) of the backup first area 4150db. Then, the peripheral control DMA controller 4150ac copies at high speed to Bank3 (SRAM) and Bank4 (SRAM) of the backup second area 4150dc.

The high-speed copy of the contents stored in Bank 0 (SRAM) by the peripheral control DMA controller 4150ac will be briefly described. The peripheral control MPU core 4150aa of the peripheral control MPU 4150a shown in FIG. 18 is a request factor of the peripheral control DMA controller 4150ac. Specify the copy of the contents stored in Bank0 (SRAM) to Bank1 (SRAM) in the backup first area 4150db, and change the contents stored in the start address of Bank0 (SRAM) to the end address of Bank0 (SRAM). The stored contents are continuously copied by a predetermined byte (for example, 1 byte) in succession from the start address of Bank 1 (SRAM) of the backup first area 4150db, and the peripheral control MPU core 4150aa makes the peripheral control DMA controller. The request factor of 4150ac specifies that the contents stored in Bank0 (SRAM) are copied to Bank2 (SRAM) of the backup first area 4150db, and the contents stored in the first address of Bank0 (SRAM) are changed to Bank0 (SRAM). Up to the contents stored in the end address of (1) are sequentially copied by a predetermined number of bytes (for example, 1 byte) sequentially from the top address of Bank 2 (SRAM) of the backup first area 4150db.

Then, the peripheral control MPU core 4150aa specifies the copy of the content stored in Bank0 (SRAM) to the Bank3 (SRAM) of the backup second area 4150dc as the request factor of the peripheral control DMA controller 4150ac, and the Bank0 (SRAM). ) To the content stored in the end address of Bank0 (SRAM) continuously by a predetermined number of bytes (for example, 1 byte), the start address of Bank3 (SRAM) of the second area 4150dc. From the peripheral control MPU core 4150aa requesting the peripheral control DMA controller 4150ac to copy the contents stored in Bank0 (SRAM) to Bank4 (SRAM) of the backup second area 4150dc. Then, from the content stored at the start address of Bank0 (SRAM) to the content stored at the end address of Bank0 (SRAM), a predetermined number of bytes (for example, 1 byte) are continuously transferred to Bank4 (second) of backup second area 4150dc. (SRAM) are all copied in order from the start address.

Following step S1034, the effect control program performs a WDT clear process (step S1036). In this WDT clear processing, a clear signal is output to the peripheral control built-in WDT 4150af and the peripheral control external WDT 4150e so that the peripheral control MPU 4150a is not reset.

Subsequent to Step S1036, the effect control program sets the value 0 to the in-steady-state processing flag SP-FLG as completion of execution of the peripheral control unit regular processing (Step S1038), returns to Step S1006 again, and returns to the V blank signal detection flag VB. -FLG is set to the value 0 for initialization, and the determination in step S1008 is repeated until the V blank signal detection flag VB-FLG is set to the value 1 in the peripheral control unit V blank signal interrupt process described later. That is, in step S1008, the process waits until the V blank signal detection flag VB-FLG is set to the value 1, and when it is determined in step S1008 that the V blank signal detection flag VB-FLG is the value 1, steps S1009 to step S1009 to step S1009. The process of S1038 is performed, and the process returns to step S1006 again. In this way, when it is determined in step S1008 that the V blank signal detection flag VB-FLG has the value 1, the processes of steps S1009 to S1038 are performed. The processing of steps S1009 to S1038 is referred to as "peripheral control unit steady processing".

This peripheral control unit steady process starts with the production control program first setting the value 1 to the steady process in-progress flag SP-FLG on the assumption that the peripheral control unit steady process is being executed in step S1009, and 1 ms in step S1010. .., and then step S1036. Finally, in step S1038, the value 0 is set in the steady processing in-progress flag SP-FLG as completion of execution of the peripheral controller steady processing. , Will be completed. The peripheral controller steady processing is executed when the V blank signal detection flag VB-FLG has a value of 1 in step S1008. As described above, this V blank signal detection flag VB-FLG is executed when the V blank signal VDP4160a with a built-in sound source is input as a V blank signal indicating that the screen data from the peripheral control MPU 4150a can be accepted. The value 1 is set in the peripheral control unit V blank signal interrupt processing described later. In the present embodiment, the game board side effect display unit 1900 and the above-described predetermined screen (in the present embodiment, red (R): 50%, green (G): 50%, blue (B): 50% are provided. As described above, the frame frequency (the number of screen updates per second), which is the frequency at which the drawing data for one screen (one frame) with the gray screen) is updated, is set to approximately 30 fps per second. Therefore, the interval at which the V blank signal is input is about 33.3 ms (=1000 ms÷30 fps). That is, the peripheral control unit steady process is repeatedly executed about every 33.3 ms.

[18-1-2. Peripheral controller V blank signal interrupt processing]
Next, as shown in FIG. 17, a V blank signal indicating that the screen data from the peripheral control MPU 4150a of the peripheral control unit 4150 can be received is input from the liquid crystal and sound source built-in VDP 4160a of the sound control unit 4160. Peripheral control unit V blank signal interrupt processing that is executed in response to this will be described. When this peripheral control unit V blank signal interrupt processing is started, the peripheral control MPU 4150a of the peripheral control unit 4150 determines whether or not the steady processing in-progress flag SP-FLG has a value of 0 as shown in FIG. S1045). As described above, the steady processing in-progress flag SP-FLG has a value of 1 when the peripheral control unit steady process of steps S1009 to S1038 in the peripheral control unit power-on process of FIG. 68 is being executed, and the peripheral control unit steady state. The value is set to 0 when the processing is completed.

When the steady processing in-progress flag SP-FLG is not 0 (value 1) in step S1045, that is, when the peripheral control unit steady processing is being executed, this routine is ended as it is. On the other hand, when the steady processing in-progress flag SP-FLG is 0 in step S1045, that is, when the peripheral control steady processing is completed, the V blank signal detection flag VB-FLG is set to 1 (step S1050). This routine ends. As described above, the V blank signal detection flag VB-FLG is a flag for determining whether to execute the peripheral control unit steady process, and has a value of 1 when the peripheral control unit steady process is executed, and the peripheral control. The value is set to 0 when the partial steady process is not executed.

In the present embodiment, in step S1045, it is determined whether or not the steady processing in-progress flag SP-FLG has a value of 0, that is, whether the peripheral control unit steady processing has been completed, and the peripheral control unit steady processing has been completed. At step S1050, the V blank signal detection flag VB-FLG is sometimes set to a value of 1. However, this is because the V blank signal is input and the V blank signal is input while the peripheral control unit steady process is being executed. When the signal detection flag VB-FLG is set to the value 1, the peripheral control unit steady process which is currently being executed is assumed to be executed as the peripheral control unit steady process in the determination of step S1008 in the peripheral control unit power-on process. Since the peripheral control unit steady processing is forcibly canceled on the way and the peripheral control unit steady processing is started from the beginning, in order to prevent this, at step S1009 in the peripheral control unit power-on processing (peripheral control unit steady processing) shown in FIG. 68 is transmitted to the peripheral control unit V blank signal interrupt processing, which is this routine, to inform that the peripheral control unit steady processing is being executed by setting the processing flag SP-FLG to the value 1. The peripheral control unit V blank, which is this routine, indicates that the peripheral control unit steady process has been completed by setting the value 0 in the steady process in-progress flag SP-FLG in step S1038 of the closing process (peripheral control unit steady process). By notifying the signal interrupt process, whether or not the steady processing in-progress flag SP-FLG is 0 in the determination of step S1045 in the peripheral control unit V blank signal interrupt process which is this routine, that is, the peripheral control unit steady process is executed. It is designed to determine whether or not it has been completed. In other words, this is a measure in the case where the peripheral control unit steady processing cannot be completed by the time the V blank signal is input and the next V blank signal is input, and so-called processing is dropped.

As a result, in the peripheral control unit steady process this time, if the process cannot be completed in about 33.3 ms and the process is dropped, it is determined in step S1008 in the peripheral control unit power-on process in FIG. 68 next time. Then, a state of waiting until the V blank signal is input. In other words, the time required to execute the peripheral control unit steady processing of this time, which has been omitted, is about 66.6 ms. Normally, a peripheral control unit 1ms timer interrupt process, which will be described later, is repeatedly executed every time the 1ms interrupt timer is generated by the activation of the 1ms interrupt timer in step S1010 in the peripheral controller power-on process (peripheral controller steady process) of FIG. Is executed only 32 times for one peripheral control unit steady process, but when there is the peripheral control unit steady process of this time that has been dropped as described above, the peripheral control unit 1ms timer interrupt process is not performed 64 times. Instead, it is only executed 32 times. In other words, even if the peripheral control unit steady process is dropped, the consistency between the progress state of the effect by the peripheral control unit steady process and the progress state of the effect by the peripheral control unit 1ms timer interrupt process which is the timer interrupt control is consistent. It doesn't collapse. Therefore, even if the peripheral control unit steady process is omitted, the progress state of the effect can be surely matched.

[18-1-3. Peripheral controller 1ms timer interrupt processing]
Next, the peripheral controller 1ms timer interrupt process that is repeatedly executed every time the 1ms interrupt timer is generated by the activation of the 1ms interrupt timer in step S1010 in the peripheral controller steady process of the peripheral controller power-on process of FIG. 68 will be described. .. When the peripheral controller 1ms timer interrupt process is started, the peripheral control MPU 4150a of the peripheral controller 4150 shown in FIG. 17 determines whether the 1ms timer interrupt execution count STN is smaller than 33 times as shown in FIG. Is determined (step S1100). As described above, the 1 ms timer interrupt execution count STN is determined by this routine when the 1 ms interrupt timer is activated in the 1 ms interrupt timer activation process of step S1010 in the peripheral control unit steady process of the peripheral control unit power-on process of FIG. This is a counter that counts the number of times a certain peripheral control unit 1 ms timer interrupt process is executed. In the present embodiment, the game board side effect display unit 1900 and the above-described predetermined screen (in the present embodiment, red (R): 50%, green (G): 50%, blue (B): 50% are provided. As described above, the frame frequency (the number of screen updates per second), which is the frequency at which the drawing data for one screen (one frame) with the gray screen) is updated, is set to approximately 30 fps per second. Therefore, the interval at which the V blank signal is input is about 33.3 ms (=1000 ms÷30 fps). That is, since the peripheral control unit steady process is repeatedly executed about every 33.3 ms, after the 1 ms interrupt timer is started in step S1010 in the peripheral control unit steady process, the next peripheral control unit steady process is performed. The peripheral controller 1ms timer interrupt process is executed 32 times before the execution of. Specifically, when the 1 ms interrupt timer is activated in step S1010 in the peripheral control unit steady process, the first 1 ms timer interrupt occurs, the second,..., And the 32 1 ms timer interrupts sequentially. Will occur.

In step S1100, when the 1 ms timer interrupt execution count STN is not smaller than 33 times, that is, when the 33rd 1 ms timer interrupt occurs and the peripheral controller 1 ms timer interrupt processing is started, this routine is finished as it is. If the 33rd 1 ms timer interrupt happens to precede the next V blank signal, in the present embodiment, the peripheral control unit 1 ms timer interrupt process has the peripheral control unit V as the priority order of the interrupt processing. Although set higher than the blank interrupt processing, the start of the peripheral control unit 1 ms timer interrupt processing by the 33rd 1 ms timer interrupt is forcibly canceled. In other words, in the present embodiment, since the V blank signal is a signal that controls the entire system of the peripheral control board 4140, if the 33rd 1 ms timer interrupt happens to precede the next V blank signal occurrence. In order to execute the peripheral control unit V blank interrupt process, the start of the peripheral control unit 1 ms timer interrupt process by the 33rd 1 ms timer interrupt is forcibly canceled. Then, after the 1 ms interrupt timer is activated again in step S1010 in the peripheral control unit steady process due to the generation of the V blank signal, the peripheral control unit 1 ms timer interrupt process is newly started by the first generation of the 1 ms timer interrupt. ing.

On the other hand, when the 1 ms timer interrupt execution count STN is smaller than 33 times in step S1100, the value 1 is added to the 1 ms timer interrupt execution count STN (increment, step S1102). By adding the value 1 to the 1 ms timer interrupt execution count STN, the 1 ms interrupt timer is activated by the 1 ms interrupt timer activation process of step S1010 in the peripheral controller steady process of the peripheral controller power-on process of FIG. This means that the number of times the peripheral control unit 1 ms timer interrupt processing, which is this routine, is executed is increased by one.

Following step S1102, motor and solenoid drive processing is performed (step S1104). In this motor and solenoid drive processing, the electric drive source schedule data set in the schedule data storage area 4150cae of the peripheral control MPU 4150a and the external peripheral control RAM 4150c shown in FIG. 18 are arranged in time series. Among the drive data of the electric drive sources such as the motor and the solenoid, according to the drive data designated by the pointer, the electric drive sources such as the motor and the solenoid of the frame decoration drive amplifier board 194 and the motor drive board 4180 shown in FIG. Is driven, the pointer is updated to the next drive data defined in time series, and the pointer is updated each time this motor and solenoid drive processing is executed.

Specifically, in the motor and solenoid drive processing, for example, DMA serial continuous transmission processing to the frame decoration drive amplifier board 194 is performed. Here, the peripheral control DMA controller 4150ac of the peripheral control MPU 4150a shown in FIG. 18 is used to perform continuous transmission of the frame decoration drive amplifier substrate motor serial I/O port. When serial transmission of the frame decoration drive amplifier board motor serial I/O port is started, first, the electrical drive source schedule data set in the schedule data storage area 4150cae of the peripheral control MPU 4150a and the peripheral control RAM 4150c externally attached is loaded. A drive signal for the dial drive motor 414 of the operation unit 400 shown in FIG. The door-side motor drive data STM-DAT for outputting is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c and created, and the peripheral control RAM 4150c shown in FIG. The frame decoration drive amplifier board side motor transmission data storage area 4150caf is set. Then, the peripheral control CPU core 4150aa of the peripheral control MPU 4150a specifies the transmission of the frame decoration drive amplifier board motor serial I/O port as the request factor of the peripheral control DMA controller 4150ac, and stores the transmission data for the frame decoration drive amplifier board side motor. The first 1 byte of the door-side motor drive data STM-DAT stored in the start address of the area 4150caf is transferred to the frame decoration drive amplifier board motor via the external bus 4150h, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai. Transfer to the transmit buffer register of the serial I/O port for writing. As a result, the frame decoration drive amplifier substrate motor serial I/O port transfers the written data in the transmission buffer register to the transmission shift register, and in synchronization with the door side motor drive clock signal STM-CLK. 1-byte data is started to be transmitted bit by bit.

The peripheral control DMA controller 4150ac receives the transmission interrupt request of the serial I/O port for the frame decoration drive amplifier board motor as a trigger (in the present embodiment, the serial I/O for the frame decoration drive amplifier board motor). The peripheral control CPU core 4150aa is triggered by the fact that the 1-byte data written in the transmission buffer register of the port is transferred to the transmission shift register, and the transmission buffer register is emptied of the 1-byte data.). Is not using the bus, the remaining door side motor drive data STM-DAT stored in the frame decoration drive amplifier board side motor transmission data storage area 4150caf is byte by byte, the external bus 4150h, and the peripheral control bus controller. 4150ad and the peripheral bus 4150ai transfer and write to the transmission buffer register of the frame decoration drive amplifier board motor serial I/O port. The data of the transmitted transmission buffer register is transferred to the transmission shift register, and 1-byte data of the transmission shift register is started to be transmitted bit by bit in synchronization with the door-side motor drive clock signal STM-CLK. Continuous transmission is performed by the motor serial I/O port.

In the motor and solenoid drive processing, for example, DMA serial continuous transmission processing to the motor drive board 4180 is performed. Also here, the peripheral control DMA controller 4150ac of the peripheral control MPU 4150a shown in FIG. 18 is used to perform serial transmission of the motor drive board serial I/O port. When the serial I/O port continuous transmission for the motor drive board is started, first, when the electric drive source schedule data set in the schedule data storage area 4150cae of the peripheral control MPU 4150a and the peripheral control RAM 4150c externally attached is configured. A motor for moving various movable bodies provided in the game board 4 shown in FIG. 8 based on the drive data designated by the pointer among the drive data of the electric drive sources such as motors and solenoids arranged in series. And the game board side motor drive data SM-DAT for outputting a drive signal to the solenoid and the solenoid are extracted from the various control data copy areas 4150ce of the peripheral control ROM 4150b of the peripheral control unit 4150 or the peripheral control RAM 4150c, and created. It is set in the motor drive board side transmission data storage area 4150cag of the peripheral control RAM 4150c shown in FIG. Then, the peripheral control CPU core 4150aa of the peripheral control MPU 4150a designates the transmission of the motor drive board serial I/O port as the request factor of the peripheral control DMA controller 4150ac, and stores it in the head address of the motor drive board side transmission data storage area 4150cag. The first 1 byte of the game board side motor drive data SM-DAT is transmitted through the external bus 4150h, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai to the transmission buffer of the motor drive board serial I/O port. Transfer to a register and write. As a result, the motor drive board serial I/O port transfers the written data in the transmission buffer register to the transmission shift register and synchronizes with the game board side motor drive clock signal SM-CLK to set the transmission shift register to 1 Transmission of byte data is started bit by bit.

The peripheral control DMA controller 4150ac triggers each time a transmission interrupt request of the motor drive board serial I/O port is generated (in the present embodiment, the transmission buffer register of the motor drive board serial I/O port is stored). It is triggered when the written 1-byte data is transferred to the transmission shift register and the transmission buffer register is emptied of the 1-byte data.), and the peripheral control CPU core 4150aa uses the bus. If not, the remaining game board side motor drive data SM-DAT stored in the motor drive board side transmission data storage area 4150cag is byte by byte via the external bus 4150h, peripheral control bus controller 4150ad, and peripheral bus 4150ai. By transferring and writing to the transmission buffer register of the motor drive board serial I/O port, the motor drive board serial I/O port transfers the written data of the transmission buffer register to the transmission shift register, In synchronization with the game board side motor drive clock signal SM-CLK, 1 byte of data in the transmission shift register is started to be transmitted bit by bit, and continuous transmission is performed by the motor drive board serial I/O port.

Following step S1104, movable body information acquisition processing is performed (step S1106). In this movable body information acquisition processing, history information of detection signals from various detection switches (for example, original position history information) is determined by determining whether or not detection signals from various detection switches provided on the game board 4 are input. , Movable position history information, etc.) is created and set in the movable body information acquisition storage area 4150cah of the peripheral control MPU 4150a and the peripheral control RAM 4150c externally attached shown in FIG. From the history information of the detection signals from the various detection switches set in the movable body information acquisition storage area 4150cah, it is possible to acquire the original position and the movable position of the various movable bodies provided on the game board 4.

Following step S1106, operation unit information acquisition processing is performed (step S1108). In this operation unit information acquisition process, it is determined whether or not the detection signals from the various detection switches provided in the operation unit 400 are input, so that the history information of the detection signals from the various detection switches (for example, the dial operation unit). The rotation history information of 401 and the operation history information of the pressing operation unit 405 are created, and the operation unit information acquisition storage area of the peripheral control MPU 4150a and the peripheral control RAM 4150c externally attached shown in FIG. Set to 4150 cai. From the history information of the detection signals from the various detection switches set in the operation unit information acquisition storage area 4150cai, the rotation direction of the dial operation unit 401 and the presence/absence of operation of the pressing operation unit 405 can be acquired.

Following step S1108, drawing state information acquisition processing is performed (step S1110). In this drawing state information acquisition processing, history information of the LOCKN signal output from the LOCKN terminal of the receiver IC 194f included in the frame decoration drive amplifier board 194 shown in FIG. 19 is created, and the peripheral control MPU 4150a shown in FIG. It is set in the drawing state information acquisition storage area 4150cak of the attached peripheral control RAM 4150c. As described above, when the receiver IC 194f included in the frame decoration drive amplifier board 194 determines that the drawing data received from the transmitter IC 4160d included in the peripheral control board 4140 is abnormal data, the LOCKN signal is transmitted to that effect. This is a signal to be output. Specifically, the connection between the transmitter IC 4160d included in the peripheral control board 4140 and the receiver IC 194f included in the frame decoration drive amplifier board 194, that is, the connection between the transmitter and the receiver is confirmed (recovered). ) Is a signal output to request transmission of a predetermined data pattern (SYNC pattern). From the history information of the LOCKN signal set in the drawing state information acquisition storage area 4150cak, it is possible to acquire the frequency of defects and the occurrence state of defects between the connection between the peripheral control board 4140 and the frame decoration drive amplifier board 194.

Following step S1110, main prize ball number information output processing is performed (step S1112). In this main prize sphere number information output processing, when the schedule data for the main prize sphere information output signal set in the schedule data storage area 4150cae of the peripheral control MPU 4150a and the peripheral control RAM 4150c externally shown in FIG. Output waveform data for generating a main prize ball information output signal that informs the hall computer that the number of game balls planned to be paid out as prize balls has reached 10 balls arranged in series as main prize ball information Of these, the main prize ball information output signal is output to the external terminal board 784 shown in FIG. 33 according to the output waveform data designated by the pointer, and the pointer is updated to the next output waveform data specified in time series. The pointer is updated each time the main prize ball number information output process is executed.

Following step S1112, power consumption status history information creation processing is performed (step S1113). In this power consumption status history information creation processing, a value (power consumption suppression stage) transmitted by the power consumption suppression signal from the power supply board 851 is sampled and used as power consumption status history information for the power consumption of the peripheral controller 4150 shown in FIG. It is sequentially stored in the situation history RAM 4150f. As described above, the power consumption suppression signal is output from the power consumption monitoring circuit 855da. As shown in FIG. 22A, the power consumption monitoring circuit 855da includes a power measuring circuit 855daa and a power consumption suppression stage determination circuit 855dab. The +37V supplied from the smoothing circuit 855c is supplied to the +5V power generation circuit 855db, the +12V power generation circuit 855dc, and the +24V power generation circuit 855dd via the power measurement circuit 855daa. The power measurement circuit 855daa measures +37V of power consumption supplied from the smoothing circuit 855c in real time and outputs it to the power consumption suppression stage determination circuit 855dab. The power consumption suppression stage determination circuit 855dab determines a power consumption suppression stage indicating how much power consumption should be suppressed based on the power consumption amount measured by the power measurement circuit 855daa, and the determination result is determined by the three power consumption suppression stages. By setting the value of the power consumption suppression signal configured as the signal wiring and outputting it to the frame peripheral relay terminal plate 868, the power consumption suppression signal is input to the peripheral control unit 4150 via the frame peripheral relay terminal plate 868. It is supposed to be done. As described above, the power consumption suppression signal is configured as three signal wirings (that is, configured as three parallel signals) and transmits eight values from value 0 to value 7. You can do it.

As described above, when the power consumption amount of +37V measured by the power measurement circuit 855da is 0% or more and less than 10%, the power consumption suppression stage determination circuit 855dab determines that the power consumption suppression stage is stage 0 and the power consumption is reduced. When the value 0 is set as the value of the suppression signal and the power consumption amount of +37V measured by the power measurement circuit 855daa is 10% or more and less than 20%, it is determined that the power consumption suppression step is stage 1 and the power consumption suppression signal When the value 1 is set as the value and the power consumption amount of +37V measured by the power measuring circuit 855daa is 20% or more and less than 30%, it is determined that the power consumption suppressing step is the step 2 and the value is the value of the power consumption suppressing signal. 2 is set, and when the power consumption of +37V measured by the power measurement circuit 855daa is 30% or more and less than 40%, it is determined that the power consumption suppressing step is stage 3, and the value 3 is set as the value of the power consumption suppressing signal. Then, when the power consumption of +37V measured by the power measurement circuit 855daa is 40% or more and less than 50%, it is determined that the power consumption suppressing step is stage 4, and the value 4 is set as the value of the power consumption suppressing signal. When the power consumption of +37V measured by the measuring circuit 855daa is 50% or more and less than 60%, it is determined that the power consumption suppressing step is stage 5, and the value 5 is set as the value of the power consumption suppressing signal, and the power measuring circuit 855daa When the power consumption amount of +37V measured in step 6 is 60% or more and less than 70%, it is determined to be step 6 as the power consumption suppressing step, the value 6 is set as the value of the power consumption suppressing signal, and the value is measured by the power measuring circuit 855daa. When the power consumption of +37V is 70% or more, it is determined that the power consumption suppressing step is step 7, and the value 7 is set as the value of the power consumption suppressing signal.

As described above, in the power consumption status history information creation process, the value (value 0 to value 7) transmitted by the power consumption suppression signal from the power supply board 851 is sampled every time this routine is executed, that is, every 1 ms. The power consumption suppression stages (Stage 0 to Stage 7) are sequentially stored in the power consumption status history RAM 4150f of the peripheral control unit 4150 to arrange the power consumption suppression stages in time series as the power consumption status history information.

After step S1113, a backup process is performed (step S1114), and this routine ends. In this backup processing, the contents stored in the peripheral control MPU 4150a and the external peripheral control RAM 4150c shown in FIG. At the same time, the contents stored in the peripheral control MPU 4150a and the peripheral control SRAM 4150d attached externally are copied and backed up in the backup first area 4150db and the backup second area 4150dc, respectively.

Specifically, in the backup process, the peripheral control RAM 4150c executes the 1ms timer interrupt process of the peripheral control unit, which is this routine, every time the 1ms interrupt timer in the backup target work area 4150ca shown in FIG. 18 occurs. Each time it is performed, the frame decoration drive amplifier board side motor transmission data storage area 4150caf, the motor drive board side transmission data storage area 4150cag, and the movable body information acquisition storage area 4150cah included in the backup target Bank0 (1 ms) are included. , And the effect information (1 ms) that is the content stored in the operation unit information acquisition storage area 4150cai as the effect backup information (1 ms) in the backup first area 4150 cb in Bank 1 (1 ms) and Bank 2 (1 ms). The DMA controller 4150ac copies at high speed, and the peripheral control DMA controller 4150ac copies at high speed to Bank3 (1 ms) and Bank4 (1 ms) of the backup second area 4150cc.

The high-speed copy of the contents stored in Bank 0 (1 ms) by the peripheral control DMA controller 4150ac will be briefly described. The peripheral control MPU core 4150aa of the peripheral control MPU 4150a shown in FIG. Specify the copy of the contents stored in Bank0 (1ms) to Bank1 (1ms) of the backup first area 4150cb, and change the contents stored in the start address of Bank0 (1ms) to the end address of Bank0 (1ms). The stored contents are continuously copied by a predetermined byte (for example, 1 byte) in sequence from the start address of Bank 1 (1 ms) of the backup first area 4150cb, and the peripheral control MPU core 4150aa makes the peripheral control DMA controller. The contents stored in Bank0 (1 ms) as the request factor of 4150ac is designated to copy to the backup first area 4150cb to Bank2 (1ms), and the contents stored in the first address of Bank0 (1ms) are changed to Bank0 (1ms). Up to the contents stored in the end address of (1) are successively copied by a predetermined number of bytes (for example, 1 byte) consecutively from the start address of Bank2 (1 ms) of the backup first area 4150cb.

Subsequently, the peripheral control MPU core 4150aa specifies the copy of the content stored in Bank0 (1 ms) to the request factor of the peripheral control DMA controller 4150ac to Bank3 (1 ms) of the backup second area 4150cc, and Bank0 (1 ms). ) To the content stored in the end address of Bank0 (1 ms) consecutively by a predetermined byte (for example, 1 byte), the start address of Bank3 (1 ms) of the backup second area 4150cc. From the peripheral control MPU core 4150aa requesting the peripheral control DMA controller 4150ac to copy the contents stored in Bank0 (1ms) to the backup second area 4150cc to Bank4 (1ms). Then, from the content stored at the start address of Bank0 (1 ms) to the content stored at the end address of Bank0 (1 ms), a predetermined number of bytes (for example, 1 byte) are continuously contiguous by Bank4 (second) of the backup second area 4150cc. (1 ms), starting from the first address, all are copied in order.

As described above, in the peripheral control unit 1 ms timer interrupt process, various processes related to the effects of step S1104 to step S1108 described above as the progress of effects are executed within the period of 1 ms. On the other hand, in the peripheral control unit steady process in the peripheral control unit power-on process of FIG. 68, various processes related to the effect of step S1012 to step S1032 described above as the effect progress are executed within a period of about 33.3 ms. doing. In the peripheral controller 1ms timer interrupt process, when the 1ms timer interrupt execution count STN is not smaller than the value 33 in step S1100, that is, when the 33rd 1ms timer interrupt occurs and the peripheral controller 1ms timer interrupt process is started. Since this routine is terminated as it is, even if the 33rd 1ms timer interrupt happens to precede the next V blank signal occurrence, the peripheral control unit by the 33rd 1ms timer interrupt will occur. After the start of the 1ms timer interrupt process is forcibly canceled, the 1ms interrupt timer is restarted in step S1010 in the peripheral control unit steady process due to the occurrence of the V blank signal, and then the peripheral control is newly generated by the 1ms timer interrupt process. The 1ms timer interrupt processing is started. That is, the consistency between the progress state of the effect by the peripheral control unit steady process and the progress state of the effect by the peripheral control unit 1 ms timer interrupt process, which is the timer interrupt control, is maintained. Therefore, the progress state of the effect can be surely matched.

Further, as described above, the interval at which the V blank signal is output is the liquid crystal size of the game board side effect display unit 1900 or a predetermined screen (red (R): 50%, green (G) in this embodiment). : 50%, blue (B): gray screen having 50%), and a V blank signal even in the manufacturing lot of the peripheral control board 4140 in which the peripheral control MPU 4150a and the sound source built-in VDP 4160a are mounted. The interval at which is output may change slightly. In the present embodiment, since the V blank signal is a signal that controls the entire system of the peripheral control board 4140, if the 33rd 1 ms timer interrupt happens to precede the next generation of the V blank signal, the peripheral control is performed. In order to execute the section V blank interrupt process, the start of the peripheral controller 1ms timer interrupt process by the 33rd 1ms timer interrupt is forcibly canceled. In other words, in the present embodiment, even if the interval at which the V blank signal is output changes slightly, by forcibly canceling the start of the peripheral control unit 1ms timer interrupt process by the 33rd 1ms timer interrupt, It is possible to absorb a time lag caused by a slight change in the interval at which the V blank signal is output.

[18-1-4. Peripheral control block command reception interrupt processing]
Next, a peripheral control unit command reception interrupt process for receiving various commands from the main control board 4100 will be described. When the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 17 starts transmitting various commands from the main control board 4100 as serial data, the peripheral control MPU 4150a uses the peripheral control MPU 4150a as a main control to incorporate the main serial data into the peripheral control MPU 4150a. 1-byte (8-bit) information is fetched into the reception buffer by the board serial I/O port, and when this fetching is completed, an interrupt is triggered by this, and peripheral control unit command reception interrupt processing is performed. In the main serial data, one packet is composed of 3 bytes, the status is allocated as the 1st byte, the mode is allocated as the 2nd byte, and the status and mode are regarded as numerical values as the 3rd byte. The calculated sum value is assigned.

When the peripheral control unit command reception interrupt process is started, the peripheral control MPU 4150a of the peripheral control unit 4150 determines whether or not the 1-byte reception period timer has timed out (step S1200). The 1-byte reception period timer sets a period during which 1-byte (8-bit) information can be received in the main circumference serial data transmitted from the main control board 4100.

When the 1-byte reception period timer has not timed out in step S1200, that is, when the 1-byte (8-bit) information of the main-circulation serial data transmitted from the main control board 4100 can be received, The 1-byte information received from the reception buffer of the serial I/O port for the main control board built in the control MPU 4150a is fetched (step S1202), and the value 1 is added to the reception counter SRXC (increment, step S1204). The reception counter SRXC is a counter indicating the number of times the data is fetched from the reception buffer. When the status, which is the first byte of the main serial data, is fetched from the reception buffer, the value is 1, and the mode that is the second byte of the main serial data is set. The value is 2 when taken out from the receive buffer, and the value 3 is taken out when the sum value which is the third byte of the main serial data is taken out from the receive buffer. The reception counter SRXC is set to an initial value 0 when the power is turned on.

Following step S1204, it is determined whether or not the reception counter SRXC has a value of 3, that is, whether or not the sum value, which is the third byte of the main circumference serial data, has been extracted from the reception buffer (step S1206). In this determination, the status, which is the first byte of the main-cycle serial data, the mode, which is the second byte of the main-cycle serial data, and the sum value, which is the third byte of the main-cycle serial data, are sequentially output from the reception buffer. It is determined whether it has been taken out.

When the reception counter SRXC does not have the value 3 in step S1206, that is, the status which is the first byte of the main cycle serial data is followed by the mode which is the second byte of the main cycle serial data and the third byte of the main cycle serial data. When the sum value is not sequentially fetched from the reception buffer, the 1-byte reception period timer is set (step S1208), and this routine is ended. By setting the 1-byte reception period timer in step S1208, the period in which the mode that is the second byte of the main serial data or the sum value that is the third byte of the main serial data can be received is set.

On the other hand, when the reception counter SRXC has the value 3 in step S1206, that is, the status which is the first byte of the main circumference serial data, the mode which is the second byte of the main circumference serial data, and the status of 3 of the main circumference serial data. When the sum value at the byte is sequentially fetched from the reception buffer, the reception counter SRXC is set to the initial value 0 (step S1210), and the sum value is calculated (step S1212). This calculation regards the status, which is the first byte of the main-cycle serial data, and the mode, which is the second byte of the main-cycle serial data, which have already been extracted from the reception buffer in step S1202, as numerical values, and sums them (sum value ) Is calculated.

Subsequent to step S1212, it is determined whether or not the sum value which is the third byte of the main circumference serial data already fetched from the reception buffer in step S1202 and the sum value calculated in step S1212 match (step S1212). S1214). The sum value which is the third byte of the main circumference serial data already fetched from the reception buffer in step S1202 is the sum value assigned as the third byte of the main circumference serial data in the main circumference serial data from the main control board 4100. Therefore, it should match the sum value calculated in step S1212. However, the pachinko gaming machine 1 is supplied with gaming balls from the pachinko island facility, and when the gaming balls rub against each other and become charged, electrostatic discharge causes noise, so the pachinko gaming machine 1 is affected by noise. It is in a vulnerable environment. Therefore, in the present embodiment, on the peripheral control unit 4150 side, the status assigned as the first byte of the received main circumference serial data and the mode assigned as the second byte of the main circumference serial data are regarded as numerical values. Then, the sum (sum value) is calculated, and whether the calculated sum value matches the sum value assigned as the third byte of the main circumference serial data in the main circumference serial data from the main control board 4100. It is determined whether or not. As a result, the peripheral control MPU 4150a determines whether or not the main circumference serial data has been changed from the normal circumference data different from the normal one due to the noise between the main control board 4100 and the peripheral control board 4140. be able to.

In step S1214, when the sum value which is the third byte of the main circumference serial data already fetched from the reception buffer in step S1202 and the sum value calculated in step S1212 match, the received main circumference serial data is received. 18, the status allocated as the first byte and the mode allocated as the second byte of the main serial data are shown in FIG. (Step S1216), and this routine ends. This reception command storage area 4150cac is used as a ring buffer, and the status assigned as the first byte of the main circumference serial data and the mode assigned as the second byte of the main circumference serial data are It is stored in the peripheral control unit reception ring buffer of 4150 cac. The "peripheral control unit reception ring buffer" is a buffer that is used so that the end and the beginning of the buffer are connected. It stores data sequentially from the beginning of the buffer and returns to the beginning when the end of the buffer is reached. Remember. The peripheral control MPU 4150a allocates the status assigned as the first byte of the main circumference serial data and the second byte of the main circumference serial data received when the peripheral control MPU4150a stores the status in the peripheral control unit reception ring buffer in step S1216. The stored mode is stored in association with each other, and the sum value assigned as the third byte is discarded.

On the other hand, when the 1-byte reception period timer has not timed out in step S1200, that is, the period over which 1-byte (8-bit) information can be received in the main-circulation serial data transmitted from the main control board 4100 is exceeded. If, or, in step S1214, the sum value which is the third byte of the main circumference serial data already fetched from the reception buffer in step S1202 does not match the sum value calculated in step S1212, this routine is directly executed. finish.

[18-1-5. Peripheral control unit power failure notice signal interrupt processing]
Next, the peripheral control unit power failure notification signal executed when the power failure notification signal (peripheral power failure notification signal) from the power failure monitoring circuit 4100e of the main control board 4100 shown in FIG. 21 is input from the main control board 4100. The interrupt processing will be described. When the peripheral control unit power outage notice signal interrupt process is started, the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 17 first activates the 2 microsecond timer (step S1300), and the power outage notice signal (peripheral power outage notice). Signal) is input (step S1302). If the power failure warning signal (peripheral power failure warning signal) is not input in this determination, this routine is finished as it is.

On the other hand, when the power failure notice signal is input in step S1302, it is determined whether or not 2 microseconds have elapsed (step S1304). In this determination, it is determined whether the timer started in step S1300 has passed 2 microseconds. When 2 macroseconds have not elapsed in step S1304, the process returns to step S1302, and it is determined whether or not the power outage notice signal is input. When the power outage notice signal is not input, this routine is finished as it is, while the power outage notice is issued. When the signal is input, it is again determined in step S1304 whether or not 2 microseconds have elapsed. That is, in the determination of step S1304, it is determined whether or not the power failure advance notice signal has been continuously input for 2 microseconds since the peripheral control unit power failure advance notice interrupt processing, which is this routine, has been started.

In step S1304, when the peripheral control unit power outage notice signal interrupt process which is the main routine is started and the power outage notice signal is continuously input for 2 microseconds, the power saving process is performed (step S1306). In this power saving process, the backlight of the game board side effect display unit 1900 is turned off, the motors and solenoids provided on the game board 4 are turned off, and various LEDs are turned off. By suppressing the power consumption of, the stable operation is secured only for a period of 20 milliseconds, which is the time when the peripheral control MPU 4150a can operate even when the power of the pachinko gaming machine 1 is cut off.

Following step S1306, command reception standby processing is performed (step S1308). In this command reception standby process, assuming that there are various commands being transmitted by the main control board 4100, the peripheral control MPU 4150a can receive the commands being transmitted at least for a period of 17 milliseconds. It is supposed to wait. When the command is received, the peripheral control unit command reception interrupt processing described above is started, and the peripheral control MPU 4150a and the external control RAM 4150c externally attached peripheral command RAM storage area 4150cac (peripheral control unit reception ring buffer) shown in FIG. ) Stores the received command.

Following step S1308, command backup processing is performed (step S1310). In the backup process of this command, the contents stored in the received command storage area 4150cac included in Bank0 (1fr) in the backup target work area 4150ca shown in FIG. 18 are changed to Bank1 (1fr) and The peripheral control DMA controller 4150ac copies to Bank2 (1fr) at high speed, and the peripheral control DMA controller 4150ac copies to Bank3 (1fr) and Bank4 (1fr) of the backup second area 4150cc at high speed.

The high-speed copy of the contents stored in the received command storage area 4150cac included in Bank 0 (1fr) by the peripheral control DMA controller 4150ac will be briefly described. The peripheral control MPU core 4150aa of the peripheral control MPU 4150a shown in FIG. As a request factor of the control DMA controller 4150ac, the content stored in the received command storage area 4150cac included in Bank0 (1fr) is designated to be copied to the received command storage area included in Bank1 (1fr) of the backup first area 4150cb. However, from the content stored at the start address of the received command storage area 4150cac included in Bank0 (1fr) to the content stored at the end address of the received command storage area 4150cac included in Bank0 (1fr), a predetermined byte (for example, 1 byte) in succession, all are sequentially copied from the start address of the received command storage area included in Bank 1 (1fr) of the backup first area 4150cb, and the peripheral control MPU core 4150aa requests the peripheral control DMA controller 4150ac to request the cause. The contents stored in the received command storage area 4150cac included in Bank0 (1fr) are designated to be copied to the received command storage area included in Bank2 (1fr) of the backup first area 4150cb, and are stored in Bank0 (1fr). A predetermined number of bytes (for example, 1 byte) are continuously written from the content stored at the start address of the received command storage area 4150cac included to the content stored at the end address of the received command storage area 4150cac included in Bank0 (1fr). Then, all are sequentially copied from the start address of the received command storage area included in Bank2 (1fr) of the backup first area 4150cb.

Then, the peripheral control MPU core 4150aa includes the content stored in the received command storage area 4150cac included in Bank0 (1fr) in the request factor of the peripheral control DMA controller 4150ac in Bank3 (1fr) of the backup second area 4150cc. Specifying a copy to the received command storage area 4150cac included in Bank0 (1fr) from the content stored in the start address of the received command storage area 4150cac included in Bank0 (1fr) to the end address of the received command storage area 4150cac included in Bank0 (1fr) The contents up to this point are successively copied by a predetermined byte (for example, 1 byte) in sequence from the start address of the received command storage area included in Bank3 (1fr) of the backup second area 4150cc, and the peripheral control MPU core is copied. 4150aa transfers the contents stored in the received command storage area 4150cac included in Bank0 (1fr) to the request command area of the peripheral control DMA controller 4150ac to the received command storage area included in Bank4 (1fr) of the backup second area 4150cc. By specifying copy, the contents stored in the start address of the received command storage area 4150cac included in Bank0 (1fr) to the contents stored in the end address of the received command storage area 4150cac included in Bank0 (1fr) are specified. All bytes (for example, 1 byte) are continuously copied sequentially from the head address of the received command storage area included in Bank 4 (1fr) of the backup second area 4150cc.

Subsequent to step S1310, it is determined whether or not a power failure notice signal (peripheral power failure notice signal) is input (step S1312). If the power failure notice signal is input in this determination, WDT clear processing is performed (step S1314). In this WDT clear processing, the peripheral control MPU 4150a outputs a clear signal to the peripheral control internal WDT 4150af shown in FIG. 18 and the peripheral control external WDT 4150e shown in FIG. 17 so that the peripheral control MPU 4150a is not reset. ..

On the other hand, when the power failure advance notice signal is not input in step S1312 or following step S1314, the process returns to step S1312 again to determine whether the power cut advance notice signal is input. That is, whether or not the power failure notice signal (peripheral power failure notice signal) is input is continuously determined. By continuously determining in this way, when the power failure notice signal (peripheral power failure notice signal) is not input in step S1312, the peripheral control MPU4150a outputs the clear signal to the peripheral control internal WDT4150af and the peripheral control external WDT4150e. However, while the peripheral control MPU 4150a is reset, when the power failure notice signal is input in step S1312, the WDT clear processing is performed in step S1314, and the peripheral control MPU 4150a is not reset. When the peripheral control MPU 4150a is reset, the peripheral controller power-on process shown in FIG. 68 is restarted.

In this way, when the power failure warning signal (peripheral power failure warning signal) continues to be input in the endless loop in the determination in step S1312, the peripheral control is performed immediately before the power failure occurs by executing the WDT clear processing in step S1314. The MPU4150a is designed not to be reset. On the other hand, if the power failure notification signal is not continuously input and released in the infinite loop in the determination in step S1312, the WDT clear processing is not executed, so that the peripheral control built-in WDT 4150af and the peripheral control external WDT 4150e are not connected. The output of the clear signal is interrupted. As a result, even if the peripheral control unit power outage advance signal interrupt processing, which is the main routine, is erroneously started due to noise or the like and the noise is generated for a period of more than 2 microseconds and the determination at step S1302 is passed, If the input of the power failure notice signal (peripheral power failure notice signal) is canceled in the endless loop as determined by S1312, the peripheral control MPU4150a is reset because the WDT clear process of step S1314 is not executed. Therefore, such noise can be dealt with by automatically resetting and returning.

[18-1-6. Power saving mode transition judgment processing at power recovery]
Next, when the power is cut off (immediately before the power is cut off), the state of power consumed by the pachinko gaming machine 1 is grasped at the time of power recovery, and the mode is changed to the power saving mode during power recovery for suppressing the power consumed by the pachinko gaming machine 1. When determining whether or not to shift to the power saving mode at the time of power recovery, the volume of the effect sound flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 is reduced. The power saving mode transition determination processing at the time of power recovery will be described. The setting is performed, and the brightness of the plurality of LEDs provided on each decorative board of the door frame 5 and the plurality of LEDs provided on each decorative board of the game board 4 is reduced. .. This power recovery mode transition determination process at the time of power recovery is performed in the process of step S1004 in the peripheral control unit steady process of the peripheral control unit power-on process shown in FIG.

When the power saving mode transition determination process at the time of power recovery is started, the peripheral control MPU 4150a of the peripheral control unit 4150 illustrated in FIG. 17 specifies the power consumption suppression stage based on the power consumption status history information, as illustrated in FIG. Yes (step S1350). As described above, the power consumption status history information is the value transmitted by the power consumption suppression signal from the power supply board 851 in the power consumption status history information creation processing of step S1113 in the peripheral controller 1 ms timer interrupt processing shown in FIG. 70 ( The value 0 to the value 7) are sampled and sequentially stored in the power consumption status history RAM 4150f of the peripheral control unit 4150 shown in FIG. It is arranged in series. When the power is turned off, the power consumption status history RAM 4150f stores the power consumption status history information in the power consumption status history storage unit 4150f by supplying backup power from the battery 4150g of the peripheral control unit 4150 shown in FIG. It is supposed to be done.

In step S1350, among the power consumption status history information in which the values sampled and stored by the peripheral control MPU 4150a are arranged in time series, the pachinko gaming machine 1 is powered off (power outage or momentary interruption due to power consumption of the pachinko gaming machine 1). Not including, for example, power outages due to lightning strikes and momentary power outages due to lightning strikes, power outages to the halls and momentary power outages due to instability of power supplied to the halls, pachinko game machines by staff such as clerk in the hall. (Including power cutoff to 1.) The value stored by sampling immediately before is extracted, and the power consumption suppression stage immediately before power cut is specified. As a result, it is possible to grasp the power consumption suppression stage immediately before the power failure of the pachinko gaming machine 1.

Following step S1350, it is determined whether the power consumption suppression stage has reached the threshold value (step S1352). In this determination, it is determined whether or not the power consumption suppression stage just before the power-off of the pachinko gaming machine 1 specified in step S1350 has reached the threshold value. In this embodiment, step 7 is set as the threshold value.

When the power consumption suppression stage has not reached the threshold value in step S1352, the value 0 is set in the power recovery mode at power recovery mode ECO-FLG (step S1354), and this routine is terminated while the power consumption is reduced in step S1352. When the suppression stage has reached the threshold value, the value 1 is set in the power recovery mode at power recovery mode ECO-FLG (step S1356), and the power saving mode timer at power recovery is started (step S1358). To finish.

The power saving mode transition flag ECO-FLG at the time of power restoration indicates the effect sound that flows from the speaker accommodated in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 when the pachinko gaming machine 1 is restored. The power saving mode is set at the time of power restoration, in which setting is made to reduce the volume, setting to reduce the brightness of the plurality of LEDs provided on each decorative board of the door frame 5 and the plurality of LEDs provided on each decorative board of the game board 4, and the like. Whether or not the power saving mode at power recovery is not set, and the value 0 is set at power saving mode at power recovery.

The power recovery time power saving mode timer that is activated in step S1358 measures the power recovery time power saving mode state maintenance period in which the state in which the pachinko gaming machine 1 is activated as the power recovery time power saving mode is maintained. In the form, 5 minutes is set as the power saving mode state maintaining period during power recovery. When this power saving power saving mode timer is started and the time counting of the power saving power saving mode state maintaining period is started and the power saving power saving mode state maintaining period elapses, the power saving power saving mode timer is stopped, and as shown in FIG. In order to suppress the power consumption amount according to the power consumption amount in the pachinko gaming machine 1 by the power processing amount monitoring process of step S1027 in the peripheral control unit steady process of the peripheral control unit power-on process shown, The volume of the sound produced from the speaker housed in the speaker box 820 provided in FIG. 3 and the speaker 130 provided in the door frame 5, the plurality of LEDs provided on each decorative substrate of the door frame 5 and each decorative substrate of the game board 4. The brightness of the plurality of LEDs provided is adjusted.

[18-1-7. Power consumption monitoring process]
Next, a power consumption monitoring process for adjusting the volume and the brightness of various LEDs to suppress the power consumption according to the power consumption in the pachinko gaming machine 1 will be described. This power consumption monitoring process is performed in the process of step S1027 in the peripheral control unit steady process of the peripheral control unit power-on process shown in FIG.

When the power consumption monitoring process is started, the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 17 specifies the power consumption suppressing stage based on the power consumption suppressing signal (step S1400). ). As described above, the power consumption suppression signal is output from the power consumption monitoring circuit 855da. As shown in FIG. 22A, the power consumption monitoring circuit 855da includes a power measuring circuit 855daa and a power consumption suppression stage determination circuit 855dab. The +37V supplied from the smoothing circuit 855c is supplied to the +5V power generation circuit 855db, the +12V power generation circuit 855dc, and the +24V power generation circuit 855dd via the power measurement circuit 855daa. The power measurement circuit 855daa measures +37V of power consumption supplied from the smoothing circuit 855c in real time and outputs it to the power consumption suppression stage determination circuit 855dab. The power consumption suppression stage determination circuit 855dab determines a power consumption suppression stage indicating how much power consumption should be suppressed based on the power consumption amount measured by the power measurement circuit 855daa, and the determination result is determined by the three power consumption suppression stages. By setting the value of the power consumption suppression signal configured as the signal wiring and outputting it to the frame peripheral relay terminal plate 868, the power consumption suppression signal is input to the peripheral control unit 4150 via the frame peripheral relay terminal plate 868. It is supposed to be done. As described above, the power consumption suppression signal is configured as three signal wirings (that is, configured as three parallel signals) and transmits eight values from value 0 to value 7. You can do it.

As described above, when the power consumption amount of +37V measured by the power measurement circuit 855da is 0% or more and less than 10%, the power consumption suppression stage determination circuit 855dab determines that the power consumption suppression stage is stage 0 and the power consumption is reduced. When the value 0 is set as the value of the suppression signal and the power consumption amount of +37V measured by the power measurement circuit 855daa is 10% or more and less than 20%, it is determined that the power consumption suppression step is stage 1 and the power consumption suppression signal When the value 1 is set as the value and the power consumption amount of +37V measured by the power measuring circuit 855daa is 20% or more and less than 30%, it is determined that the power consumption suppressing step is the step 2 and the value is the value of the power consumption suppressing signal. 2 is set, and when the power consumption of +37V measured by the power measurement circuit 855daa is 30% or more and less than 40%, it is determined that the power consumption suppressing step is stage 3, and the value 3 is set as the value of the power consumption suppressing signal. Then, when the power consumption of +37V measured by the power measurement circuit 855daa is 40% or more and less than 50%, it is determined that the power consumption suppressing step is stage 4, and the value 4 is set as the value of the power consumption suppressing signal. When the power consumption of +37V measured by the measuring circuit 855daa is 50% or more and less than 60%, it is determined that the power consumption suppressing step is stage 5, and the value 5 is set as the value of the power consumption suppressing signal, and the power measuring circuit 855daa When the power consumption amount of +37V measured in step 6 is 60% or more and less than 70%, it is determined to be step 6 as the power consumption suppressing step, the value 6 is set as the value of the power consumption suppressing signal, and the value is measured by the power measuring circuit 855daa. When the power consumption of +37V is 70% or more, it is determined that the power consumption suppressing step is step 7, and the value 7 is set as the value of the power consumption suppressing signal.

It is possible to acquire the value of the power consumption suppression signal set by the power consumption suppression stage determination circuit 855dab in step S1400 and specify the power consumption suppression stage from the acquired value.

Subsequent to step S1400, it is determined whether or not the power recovery mode transition flag ECO-FLG at power recovery is 1 (step S1402). As described above, the power saving power saving mode shift flag ECO-FLG is set in the power saving power saving mode shift determination process of step S1004 in the peripheral control unit steady process of the peripheral control unit power-on process shown in FIG. When power is restored to the pachinko gaming machine 1, settings are made to reduce the volume of the effect sound that flows from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, and each decoration of the door frame 5. It sets whether or not to shift to the power saving mode at the time of power recovery, in which the brightness of the plurality of LEDs provided on the board and the plurality of LEDs provided on each decorative board of the game board 4 is set to be small. The value is set to 0 when the power saving mode is not entered, and is set to 0 when the power saving mode is entered.

In step S1402, when the power recovery mode at power recovery mode ECO-FLG is not 1 (value 0), that is, when the power saving mode at power recovery is not to be performed, the normal power suppression volume setting process is performed (step S1404). .. In this normal-time power suppression volume setting process, the master volume value for adjusting the volume of the output channel specified in the sound command data that constitutes the sound generation schedule data is forcibly changed to the master volume value for power suppression. Change to.

The value set as the master volume value for power suppression will be briefly described. The peripheral control MPU 4150a, as shown in FIG. Ratio to the master volume value (hereinafter referred to as “sound command data regulation master volume value”) for adjusting the volume of the output channel specified in the command data (that is, as the master volume value for power suppression When the power consumption suppressing step is step 0 or step 1, that is, when the power consumption suppressing step acquired in step S1400 is step 0 or step 1, the master volume for power suppression is set. As a value, a volume of 100% is set with respect to the master volume value of the sound command data regulation (in other words, the volume of the master volume value of the sound command data regulation itself is used as the master volume value for power suppression), and the power consumption suppression step is performed. When it is the stage 2 or the stage 3, that is, when the power consumption suppressing stage acquired in step S1400 is the stage 2 or the stage 3, the master volume value for power suppression is 90% of the master volume value of the sound command data. When the volume is set and the power consumption suppressing step is step 4, that is, when the power consumption suppressing step acquired in step S1400 is step 4, the master volume value for the sound command data is defined as the master volume value for power suppression. When the power consumption suppressing step is step 5, that is, when the power consumption suppressing step acquired in step S1400 is step 5, the master volume of the sound command data is defined as the master volume value for power suppression. When the volume of 70% is set for the volume value and the power consumption suppressing step is step 6, that is, when the power consumption suppressing step acquired in step S1400 is step 6, the sound command is set as the master volume value for power suppression. A volume of 60% is set for the master volume value specified in the data, and when the power consumption suppressing step is step 7, that is, when the power consumption suppressing step acquired in step S1400 is step 7, the power suppressing master volume is set. As a value, a volume of 50% is set with respect to the master volume value of the sound command data regulation.

To the plurality of output channels of the built-in sound source of the VDP4160a with built-in sound source, among the plurality of tracks of the built-in sound source of the VDP4160a with built-in sound source, the sound data of the effect sound incorporated in the track to be used and the effect sound incorporated in the track to be used are recorded. A sub-volume value for adjusting the volume is combined with the volume of the combined effect sound from the speaker accommodated in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5. A master volume value for power reduction that is a flowing volume is amplified, and the amplified effect sound is serialized and output as audio data to the audio data transmission IC 4160c. That is, when the normal power suppression volume setting process is performed, the effect sound does not change, but the effect sound volume is the master volume specified by the sound command data from the stage 0 to the stage 1 of the power consumption suppression stage. While the volume becomes the value itself, the volume set as the master volume value for power suppression is reduced as the power consumption suppression step progresses from step 2 to step 7, so the volume of the effect sound is increased. Is becoming smaller.

Returning to FIG. 74, following step S1404, normal-time power suppression brightness setting processing is performed (step S1406). In the normal power suppression brightness setting process, the brightness of the various LEDs in the light emitting mode of the various LEDs specified by the light emission data that constitutes the light emitting mode generation schedule data is forcibly changed and set to the power suppressing brightness.

The brightness set as the brightness for power suppression will be briefly described. The peripheral control MPU 4150a, as shown in FIG. When the ratio (that is, the luminance set as the luminance for power suppression) to the luminance of each LED in the light emission mode of each regulated LED (hereinafter, referred to as "luminance data regulation luminance") is taken as the vertical axis, When the power consumption suppression stage is one of stages 0, 1, 2, 3, and 4, that is, the power consumption suppression stage acquired in step S1400 is stage 0, stage 1, stage 2, When it is one of steps 3 and 4, the brightness is 100% of the brightness of the emission data regulation as the brightness for power reduction (in other words, the brightness itself of the emission data regulation is the brightness for power reduction). Is set, and when the power consumption suppressing step is step 5, that is, when the power consumption suppressing step acquired in step S1400 is step 5, 70% of the brightness for the power emission suppression is set as the brightness for power suppression. When the power consumption suppressing step is set to step 6, that is, when the power consumption suppressing step acquired in step S1400 is step 6, 60% of the brightness of the light emission data is set as the power suppressing brightness. However, when the power consumption suppressing step is step 7, that is, when the power consumption suppressing step acquired in step S1400 is step 7, 50% of the brightness of the light emission data is set as the power suppressing brightness. ..

When the normal-time power suppression brightness setting process is performed, the effect contents of the plurality of LEDs provided on each decorative board of the door frame 5 and the plurality of LEDs provided on each decorative board of the game board 4 do not change. , The brightness of each LED is set as the brightness for power suppression as the power consumption suppression step reaches the brightness of the emission data regulation from step 0 to step 4 while the power consumption suppression step progresses from step 5 to step 7. The luminance of various LEDs is reduced, so that the luminance of various LEDs is reduced.

Following step S1406, the power saving mode transition notification LED 4150k shown in FIG. 17 is set to the non-power saving notification mode (step S1407a). As described above, the power-saving mode transition notification LED 4150k is a high-luminance single-color LED that emits green light. The non-power saving notification mode informs a clerk such as a store clerk in the hall that the power saving mode is not restored at the time of power recovery, and is in a lighting state (that is, a lighting state of emitting green light). The non-power saving notification mode (that is, the lighting state in which the green light is emitted) of the power saving mode transition notification LED 4150k set in step S1407a is configured to be directly specified (set) every time this routine is executed. The difference is that the above-described light emission modes of the various LEDs are configured to be defined by the light emission data that constitutes the light emission mode generation schedule data. A staff member such as a store clerk in the hall inserts a key into the cylinder lock 1010 of the locking device 1000 shown in FIGS. 1 and 5 and rotates the unlocked state of the main body frame 3 with respect to the outer frame 2 to release the outer frame. By opening the main body frame 3 with respect to 2, and observing the non-power saving notification mode (that is, the lighting state of emitting green light) of the power saving mode transition notification LED 4150k, it is understood that the power saving mode does not shift to the power recovery mode. can do.

Following step S1407a, the output of the power saving mode information output signal is set to stop (step S1407b), and this routine ends. As described above, the power saving mode information output signal conveys the transition state to the power saving mode at power recovery to the hall computer via the external terminal board 784 shown in FIG. 17, and at step S1402 the power saving mode at power recovery. If the process does not move to step S1407b, the power saving mode information output signal is set to a state in which it is not output.

On the other hand, in step S1402, when the power recovery mode at power recovery mode ECO-FLG has a value of 1 (not 0), that is, when the power save mode at power recovery is performed, the power saving mode timer at power recovery reaches the upper limit time. It is determined whether or not (step S1408). As described above, the power recovery time power saving mode timer counts the power recovery time power saving mode state maintaining period in which the state in which the pachinko gaming machine 1 is activated in the power recovery time power saving mode is maintained. Then, 5 minutes is set as the power saving mode state maintaining period at the time of power recovery. The upper limit time used for the determination is 5 minutes of the power saving mode state maintaining period during power recovery.

When it is determined in step S1408 that the power saving power saving mode timer has not reached the upper limit time, that is, if the power saving power saving mode timer has not yet reached 5 minutes of the power saving power saving mode state maintaining period, the sound volume for power saving at power recovery is set. Setting processing is performed (step S1410). In this power-restoring-power-suppression-volume setting process, the volume of the output channel defined by the sound command data constituting the sound generation schedule data is set in the same manner as the normal power-suppressing volume setting process in step S1404 described above. Although the master volume value for adjustment is forcibly changed to the master volume value for power suppression, a volume of 50% is always set as the master volume value for power suppression with respect to the master volume value specified in the sound command data. The difference is that That is, in the power recovery volume setting process for power recovery, the master volume value for power suppression that is set when the power consumption suppression stage is step 7 in the normal power suppression volume setting process is always set. ing.

When the power-recovery-power-suppression-volume setting process is performed, the effect sound does not change in content, but the effect sound volume is set to the lowest level of the power consumption suppression step being step 7. (In other words, the volume of the effect sound is set such that the power consumption suppressing step is Step 7, which minimizes the power consumption).

Subsequent to step S1410, power restoration brightness setting processing for power recovery is performed (step S1412). In the power recovery brightness setting process for power recovery, similar to the normal power suppression brightness setting process in step S1406 described above, in the light emission mode of various LEDs specified in the light emission data forming the light emission mode generation schedule data. Although the brightness of various LEDs is forcibly changed and set to the brightness for power suppression, the difference is that the brightness for power suppression is always set to 50% of the brightness specified by the emission data. That is, in the power restoration brightness setting process for power restoration, the power suppression brightness set when the power consumption suppression step is step 7 in the normal power suppression brightness setting process is always set. ..

When the power-recovery-power-suppression brightness setting process is performed, the effect contents of the plurality of LEDs provided on each decorative board of the door frame 5 and the plurality of LEDs provided on each decorative board of the game board 4 do not change. However, the brightness of each type of LED is set to be the lowest in the power consumption suppressing step of step 7 (in other words, the brightness of each type of LED is the lowest in the power consumption suppressing step of step 7). It is set to be smaller).

Following step S1412, the power saving mode transition notification LED 4150k is set to the power saving notification mode (step S1413a). The power saving notification mode informs a clerk such as a store clerk of the hall that the power saving mode is to be set at the time of power recovery, and is turned off. The power saving mode transition notification LED 4150k set in step S1413a is configured such that the power saving notification mode (that is, the extinguished state) is directly specified (set) each time this routine is executed, and thus the above-described various LEDs are used. The light emitting mode is different from the light emitting mode in that the light emitting mode is configured to be defined by the light emitting data forming the light emitting mode generating schedule data. A staff member such as a store clerk in the hall inserts a key into the cylinder lock 1010 of the locking device 1000 shown in FIGS. 1 and 5 and rotates the unlocked state of the main body frame 3 with respect to the outer frame 2 to release the outer frame. 2, the main body frame 3 is opened and the light emission mode of the power saving mode transition notification LED 4150k is visually recognized to indicate that the power saving mode is being restored upon power recovery. it can. In the present embodiment, as the light emission mode of the power saving mode shift notification LED 4150k, the lighting state is set when the power saving mode is not restored, whereas the light is turned off when the power saving mode is restored. However, this is because it is necessary to suppress the power consumption in the power saving mode at power recovery, so when the power saving mode at power recovery is not in progress, the power saving mode transition notification LED 4150k is turned on, and When the power saving mode is being entered, the power saving mode transition notification LED 4150k is turned off.

Following step S1413a, the output of the power saving mode information output signal is set to start (step S1413b), and this routine ends. If the power saving mode information output signal is output in step S1413b when shifting to the power saving mode during power recovery in step S1402, the power saving mode timer during power recovery is set to the upper limit in step S1408 each time this routine is executed. Until the time elapses, that is, until the power saving power saving mode timer reaches 5 minutes of the power saving power saving mode state maintaining period, the state in which the power saving mode information output signal is output in step S1413b is maintained, and the power saving mode information output signal is output. Is output to the external terminal board 784 and transmitted to the hall computer via the external terminal board 784, and the hall computer recognizes that the pachinko gaming machine 1 is in the power saving mode at power recovery.

On the other hand, in step S1408, when the power saving power saving mode timer reaches the upper limit time, that is, when the power saving power saving mode timer reaches 5 minutes of the power saving power saving mode state maintaining period, the power saving power saving motor is restored. In order to end the shift of the power recovery mode, the value 0 is set to the power recovery mode at power recovery mode ECO-FLG (step S1414), the power saving mode timer at power recovery is stopped (step S1416), and this routine is terminated. The power-saving-time power-saving-mode timer stop processing only performs processing for stopping the power-saving-time power-saving mode timer, and does not include processing for initializing (resetting) the power-saving-time power saving mode timer. This is because even if the value of the power recovery mode transition flag ECO-FLG at power recovery changes from 0 to 1 for some reason (for example, due to the influence of noise) and the process proceeds to step S1408 in the determination of step S1402. , In the power saving power saving mode timer stop processing, the power saving power saving mode timer is the upper limit time, which is the upper limit time. By maintaining the state of having reached 5 minutes of the power saving power saving mode state maintaining period, the process always proceeds to the process of step S1414 in the determination of step S1408, and the power saving power saving mode transition flag in the process of step S1414. This is so that the value of ECO-FLG can be forcibly returned to the normal value 0. The power saving mode timer at power recovery is initialized (reset) in the initialization processing of step S1000 in the power-on processing of the peripheral controller shown in FIG.

Further, in step S1408, the power saving power saving mode timer reaches the upper limit time, and in step S1414, the value 0 is set in the power saving power saving mode shift flag ECO-FLG in order to end the shift of the power saving power saving mode in step S1414. As a result, when this routine is executed again, the process proceeds to the processes of steps S1404 to 1407b in the determination of step S1402, and the output state of the power saving mode information output signal is stopped in step S1407b. In other words, when the power recovery mode power saving mode timer reaches the upper limit time in step S1408, the output state of the power saving mode information output signal is maintained every time this routine is executed again, and the power saving mode is maintained. The state in which the information output signal is not output to the external terminal board 784 is transmitted to the hall computer via the external terminal board 784, and in the hall computer, the state in which the pachinko gaming machine 1 has transitioned to the power saving mode at the time of power recovery is completed. Will be understood. At the time of power recovery, if the determination at step S1402 does not shift to the power saving mode at power recovery, the state in which the power saving mode information output signal is not output to the external terminal board 784 is transmitted to the hall computer at step S1407b. In the hall computer, it is understood that the pachinko gaming machine 1 is not in the power saving mode at power recovery.

Thus, in the power saving mode transition determination process at the time of power recovery of step S1004 in the peripheral control unit steady process of the peripheral control unit power-on process shown in FIG. 68, when the pachinko gaming machine 1 restores power, the main frame 3 is displayed. Setting for reducing the volume of the effect sound that flows from the speaker housed in the provided speaker box 820 and the speaker 130 provided in the door frame 5, a plurality of LEDs provided on each decorative board of the door frame 5 and each decoration of the game board 4. If it is determined whether or not to shift to the power saving mode at power recovery that performs settings such as reducing the brightness of multiple LEDs provided on the board, and if the result of this determination is that it does not shift to the power saving mode at power recovery In the above-described step S1400, since the value of the power consumption suppression signal set by the power consumption suppression stage determination circuit 855dab can be acquired and the power consumption suppression stage can be specified from the acquired value, Depending on the amount of power consumption in the pachinko gaming machine 1, the power consumption suppressing stage is specified from among stages 0 to 7, and the normal power suppressing volume in step S1404 corresponding to each stage is specified. A master volume value for power suppression that is forcibly changed and set in the setting process, and a brightness for power suppression that is forcibly changed and set in the normal time power suppression brightness setting process in step S1406 described above corresponding to each stage; It is possible to control the progress of the production with less power consumption. Therefore, it is possible to prevent the power failure from occurring due to the power consumption of the pachinko gaming machine 1 itself. Further, it is possible to prevent the game from being interrupted due to a power outage due to the power consumption of the pachinko gaming machine 1 itself.

On the other hand, in the peripheral control unit steady process of the peripheral control unit power-on process shown in FIG. 68, in the power saving mode transition determination process at power recovery in step S1004, the pachinko gaming machine 1 is provided in the main body frame 3 at the time of power recovery. The setting is made to reduce the volume of the sound effect produced from the speaker housed in the speaker box 820 and the speaker 130 provided in the door frame 5, to the plurality of LEDs provided on each decorative substrate of the door frame 5 and each decorative substrate of the game board 4. When it is determined whether or not to shift to the power saving mode at the time of power recovery, in which the setting of reducing the brightness of the plurality of provided LEDs is performed, and if the result of the determination is that the power saving mode at the power recovery is to be performed, In step S1410, the master volume value for power suppression forcibly changed and set in the power recovery volume setting process at power recovery (that is, when the power consumption suppression step is step 7 in the normal power suppression volume setting process). The set power suppression master volume value) and the power suppression brightness forcibly changed and set in the power recovery brightness suppression brightness setting process in step S1412 described above (that is, the normal power suppression brightness setting process). The brightness for power suppression that is set when the power consumption suppression step is step 7) and the progress of the production by the smallest power consumption by the power recovery time at power recovery mode when the power recovery mode timer is at the upper limit time. The control can be performed until the state maintenance period reaches 5 minutes. As a result, instead of a power failure or momentary power failure due to power consumption of the pachinko gaming machine 1 to shut down the power, for example, a power failure due to a lightning strike or a momentary power failure due to a lightning strike causes the pachinko gaming machine 1 to shut down. In addition, when the pachinko gaming machine 1 is cut off due to a power failure of the power supplied to the hall or an unstable power supply to the hall, the pachinko gaming machine 1 is moved to the pachinko gaming machine 1 by an employee such as a clerk in the hall. Even when the power is cut off due to the power being cut off, it is possible to grasp the power status consumed by the pachinko gaming machine 1 when the power is cut off (immediately before the power is cut off). In step 7, the pachinko gaming machine 1 can be activated in a state where production can proceed with the smallest power consumption. Therefore, even when the power is restored, it is possible to prevent a power failure due to the power consumption of the pachinko gaming machine 1 itself. Further, it is possible to prevent the game from being interrupted due to a power outage due to the power consumption of the pachinko gaming machine 1 itself.

Further, in the present embodiment, when the normal-time power suppression volume setting process of step S1404 described above is performed, the effect sound does not change in content, but the effect sound volume varies from 0 to 0 in the power consumption suppression step. The volume of the master volume value of the sound command data itself becomes 1 up to 1, while the volume set as the master volume value for power reduction becomes substantially smaller as the power consumption suppressing step progresses from step 2 to step 7. Therefore, the volume of the effect sound is reduced, and when the normal power suppression brightness setting process in step S1406 described above is performed, a plurality of LEDs provided on each decorative board of the door frame 5 and the game board 4 are provided. Although the content of the effect by the light emission mode of the plurality of LEDs provided on each decorative substrate does not change, the brightness of each LED becomes the brightness specified by the light emission data in the power consumption suppression step from step 0 to step 4, while the power consumption suppression As the steps progress from step 5 to step 7, the brightness set as the brightness for power suppression becomes smaller, so that the brightness of various LEDs becomes smaller. In the present embodiment, when the power consumption suppressing step proceeds to step 2, the volume of the effect sound is controlled to be smaller first than the brightness of the various LEDs. This is because multiple types of pachinko game machines are installed in the hall and emit various production sounds at high volume, so even if the volume of the production sound is reduced, the player does not notice. It is possible to suppress the power consumption of the pachinko gaming machine 1 by reducing the sound volume of the effect sound without lowering the player's willingness to play the game due to the decreased volume.

[18-1-8. LOCKN signal history creation processing]
Next, the LOCKN signal history creation process executed as one process of the drawing state information acquisition process of step S1110 in the peripheral controller 1 ms timer interrupt process shown in FIG. 70 will be described. In this LOCKN signal history creation processing, a history of LOCKN signals output from the LOCKN terminal of the receiver IC 194f included in the frame decoration drive amplifier board 194 shown in FIG. 19 is created. As described above, when the receiver IC 194f included in the frame decoration drive amplifier board 194 determines that the drawing data received from the transmitter IC 4160d included in the peripheral control board 4140 illustrated in FIG. This is a signal output to convey that fact, and specifically, between the connection between the transmitter IC 4160d included in the peripheral control board 4140 and the receiver IC 194f included in the frame decoration drive amplifier board 194, that is, between the transmitter and the receiver. Is a signal output to request transmission of a predetermined data pattern (SYNC pattern) for confirming (restoring) the connection.

When the LOCKN signal history creating process is started, the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 17 is connected to the peripheral control MPU 4150a shown in FIG. The LOCKN signal detection history information LOCKN-HIST is read from the drawing state information acquisition storage area 4150cak (step S1500). This LOCKN signal detection history information LOCKN-HIST stores 1 byte (8 bits: most significant bit B7, B6, B5, B4, B3, B2, B1, least significant bit B0, "B" represents a bit). The history of the LOCKN signal which has a capacity and is output from the LOCKN terminal of the receiver IC 194f included in the frame decoration drive amplifier board 194 is stored in the drawing state information acquisition storage area 4150cak as LOCKN signal detection history information LOCKN-HIST. ..

Following step S1500, it is determined whether or not there is a LOCKN signal output from the LOCKN terminal of the receiver IC 194f included in the frame decoration drive amplifier board 194 (step S1502). In this determination, when there is a LOCKN signal from the receiver IC 194f, the receiver IC 194f determines that the drawing data received from the transmitter IC 4160d is abnormal data, and therefore, between the transmitter IC 4160d and the receiver IC 194f, that is, the transmitter and the receiver. While it is determined that a predetermined data pattern (SYNC pattern) for confirming (restoring) the connection with the receiver IC is requested, when there is no LOCKN signal from the receiver IC 194f, the receiver IC 194f receives from the transmitter IC 4160d. Predetermined data for determining (restoring) the connection between the transmitter IC 4160d and the receiver IC 194f, that is, the connection between the transmitter and the receiver, by determining that the drawn data is not abnormal data (normal data). It is determined that the pattern (SYNC pattern) is not requested to be transmitted.

If there is a LOCKN signal from the receiver IC 194f in step S1502, shift processing of LOCKN signal detection history information is performed (step S1504). In this shift processing of LOCKN signal detection history information, when there is a LOCKN signal from the receiver IC 194f, the most significant bits B7←B6, B6←B5, B5←B4 are set to the LOCKN signal detection history information LOCKN-HIST read in step S1500. , B4←B3, B3←B2, B2←B1, B1←least significant bit B0, and so on, shifting one bit at a time from the least significant bit B0 to the most significant bit B7.

When the LOCKN signal detection history information LOCKN-HIST is shifted in step S1504, the value 1 is set to the least significant bit B0 of the LOCKN signal detection history information LOCKN-HIST (step S1506), and this routine ends.

On the other hand, if there is no LOCKN signal from the receiver IC 194f in step S1502, shift processing of LOCKN signal detection history information is performed (step S1508). In this shift processing of the LOCKN signal detection history information, the same processing as the shift processing of the LOCKN signal detection history information in step S1504 is performed. When there is no LOCKN signal from the receiver IC 194f, the LOCKN signal detection history information LOCKN read in step S1500 is obtained. -HIST is the most significant bit B7 ← B6, B6 ← B5, B5 ← B4, B4 ← B3, B3 ← B2, B2 ← B1, B1 ← least significant bit B0, the least significant bit B0 to the most significant bit B7. 1 bit is shifted toward.

When the LOCKN signal detection history information LOCKN-HIST is shifted in step S1508, the value 0 is set to the least significant bit B0 of the LOCKN signal detection history information LOCKN-HIST (step S1510), and this routine ends.

Thus, every time this LOCKN signal history creation processing is executed, the LOCKN signal detection history information LOCKN-HIST is shifted by one bit from the least significant bit B0 to the most significant bit B7, and then to the least significant bit B0. Since the value 1 or the value 0 is set, the history of the LOCKN signal from the receiver IC 194f can be created.

[18-1-9. Connection failure judgment processing]
Next, the connection failure determination process executed as one process of the warning process of step S1024 in the peripheral control unit steady process of the peripheral control unit power-on process shown in FIG. 68 will be described. In this connection failure determination processing, based on the history of the LOCKN signal output from the LOCKN terminal of the receiver IC 194f included in the frame decoration drive amplifier board 194 shown in FIG. 19, the transmitter IC 4160d included in the peripheral control board 4140 and the frame decoration drive are included. It is determined whether or not there is a problem in the connection with the receiver IC 194f provided on the amplifier board 194, that is, the connection between the transmitter and the receiver.

When the connection failure determination process is started, the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 17 causes the peripheral control MPU 4150a shown in FIG. The LOCKN signal detection history information LOCKN-HIST is read from the drawing state information acquisition storage area 4150cak (step S1520). As described above, the history of the LOCKN signal output from the LOCKN terminal of the receiver IC 194f included in the frame decoration drive amplifier board 194 is stored in the LOCKN signal detection history information LOCKN-HIST. As described above, the LOCKN signal is transmitted to the receiver IC 194f included in the frame decoration drive amplifier board 194 when the receiver IC 194f determines that the drawing data received from the transmitter IC 4160d included in the peripheral control board 4140 is abnormal data. Signal to be output to the peripheral control board 4140, specifically, the connection between the transmitter IC 4160d included in the peripheral control board 4140 and the receiver IC 194f included in the frame decoration drive amplifier board 194, that is, the connection between the transmitter and the receiver is confirmed ( This signal is output to request transmission of a predetermined data pattern (SYNC pattern) for recovery.

Following step S1520, it is determined whether or not there is a LOCKN signal from the receiver IC 194f (step S1522). This determination determines whether or not the LOCKN signal detection history information LOCKN-HIST read in step S1520 matches the connection confirmation determination value. This connection confirmation determination value is stored in advance in the peripheral control ROM 4150b shown in FIG. 17, and is “000011111B (“B” represents a bit.)” in the present embodiment, and the upper four bits B7 to B4. Has a value of 0, and the lower 4 bits B3 to B0 have a value of 1. In the determination of step S1522, it is determined whether or not the lower 4 bits B3 to B0 of the LOCKN signal detection history information LOCKN-HIST and the lower 4 bits B3 to B0 of the connection confirmation determination value match.

In step S1522, when the lower 4 bits B3 to B0 of the LOCKN signal detection history information LOCKN-HIST read in step S1520 do not match the lower 4 bits B3 to B0 of the connection confirmation determination value, the peripheral control board 4140 is prepared. It is determined that there is no problem in the connection between the transmitter IC 4160d and the receiver IC 194f provided in the frame decoration drive amplifier board 194, that is, the connection between the transmitter and the receiver is determined, and this routine is ended as it is. ..

On the other hand, in step S1522, when the lower 4 bits B3 to B0 of the LOCKN signal detection history information LOCKN-HIST read in step S1520 match the lower 4 bits B3 to B0 of the connection confirmation determination value, the peripheral control board 4140. Of the transmitter IC 4160d included in the frame decoration drive amplifier board 194 and the receiver IC 194f included in the frame decoration drive amplifier board 194, that is, the communication check counter CC- The value 1 is added to CNT (increment, step S1524). Each time this routine is executed, the communication check counter CC-CNT counts up the number of times it is determined in step S1522 that the connection between the transmitter and the receiver is in a defective state. (Count the cumulative number). The communication check counter CC-CNT is set to 0 and reset when the pachinko gaming machine 1 is powered on, whereas it is not reset due to a momentary power failure or a power failure and is restored. It is adapted to be restored to the value of the communication check counter CC-CNT immediately before a power failure or power failure.

Following step S1524, it is determined whether the value of the communication check counter CC-CNT is smaller than the cumulative number upper limit value CC-LMT (step S1526). In this determination, when the value of the communication check counter CC-CNT is smaller than the cumulative number upper limit value CC-LMT, the cumulative number of times that it is determined that the connection between the transmitter and the receiver is defective is the cumulative number. When it is determined that the upper limit value CC-LMT has not been reached, but the value of the communication check counter CC-CNT is not smaller (larger) than the cumulative number upper limit value CC-LMT, a problem occurs in the connection between the transmitter and the receiver. It is determined that the cumulative number of times determined to be the current state has reached the cumulative number upper limit value CC-LMT.

When the value of the communication check counter CC-CNT is smaller than the cumulative count upper limit value CC-LMT in step S1526, that is, the cumulative count determined to be in a state in which the connection between the transmitter and the receiver has a malfunction is the cumulative count. When the upper limit value CC-LMT is not reached, the value 0 is set to the communication abnormality flag CC-FLG (step S1528), and this routine is ended. On the other hand, when the value of the communication check counter CC-CNT is not smaller (larger) than the cumulative number upper limit value CC-LMT in step S1526, that is, it is determined that there is a problem in the connection between the transmitter and the receiver. When the accumulated number of times reaches the accumulated number upper limit value CC-LMT, the value 1 is set to the communication abnormality flag CC-FLG (step S1530), and this routine is ended. The communication abnormality flag CC-FLG indicates that the connection between the transmitter and the receiver has reached the cumulative number upper limit value CC-LMT when the cumulative number of times that the connection between the transmitter and the receiver has been determined to be defective is reached. Is a flag that indicates whether or not there is a problem with the transmitter. Value is 1 when there is a problem with the connection between the transmitter and the receiver, and there is a problem with the connection between the transmitter and the receiver. When the cumulative number of times determined to be the current state has not reached the cumulative number upper limit value CC-LMT, each value is set to 0. The communication error flag CC-FLG is set to 0 and reset when the pachinko gaming machine 1 is powered on, whereas it is not reset due to a momentary power failure or a power failure and is restored. It is adapted to be restored to the value of the communication abnormality flag CC-FLG at the moment of power transmission or immediately before a power failure.

[18-1-10. Connection recovery processing]
Next, the connection recovery process executed as one process of the warning process of step S1024 in the peripheral control unit steady process of the peripheral control unit power-on process shown in FIG. 68 will be described. This connection recovery processing is executed subsequent to the connection failure determination processing shown in FIG. 77, and is performed between the connection between the transmitter IC 4160d included in the peripheral control board 4140 and the receiver IC 194f included in the frame decoration drive amplifier board 194, that is, the transmitter. A predetermined data pattern (SYNC pattern) is output in order to confirm (recover) the connection with the receiver, and the fact is notified when the connection between the transmitter and the receiver is abnormal.

When the connection recovery process is started, the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 17 performs the peripheral control unit steady process of the peripheral control unit power-on process shown in FIG. 68 as shown in FIG. In the scheduler update processing of step S1020, it is determined whether or not the screen generation schedule data is being activated among the various schedule data set in the schedule data storage area 4150cae of the peripheral control RAM 4150c shown in FIG. 18 (step S1540). In this determination, in the scheduler update process, in order to instruct which number of screen data from the first screen data to output to the sound source built-in VDP 4160a among the time-sequential screen data forming the screen generation schedule data First, it is determined whether or not the pointer has been updated. In other words, in the scheduler update process, while the pointer is being updated, since the effect is proceeding according to the screen generation schedule data, it is determined that the screen generation schedule data is being activated, while the screen generation schedule is being determined. When the effect is completed according to the data and the updating of all the pointers is completed, it is determined that the screen generation schedule data is not activated. In this determination, a demonstration is performed by the game board side effect display unit 1900 while the startup screen when the power of the pachinko game machine 1 is turned on is displayed on the game board side effect display unit 1900, or in a customer waiting state. It is possible to determine whether or not it is during the period based on the screen generation schedule data, and display the start screen when the power of the pachinko gaming machine 1 is turned on on the game board side effect display unit 1900. During the period in which the pachinko gaming machine 1 is powered on, the process proceeds to step S1542, which will be described later, during the period during which the pachinko gaming machine 1 is in a waiting state and during the demonstration by the game board side effect display unit 1900. When it is not the period displayed on the game board side effect display unit 1900, or the period in which the customer waits for the demonstration by the game board side effect display unit 1900 (simply in the waiting state for the customer) In this case, this routine is finished as it is.

When the production is proceeding according to the screen generation schedule data in step S1540, that is, when the screen generation schedule data is being activated, this routine is ended as it is, while in step S1540 the screen generation schedule data is followed. When the effect has been completed and the pointers have all been updated, that is, when the screen generation schedule data has not been activated, it is determined whether the value of the communication check counter CC-CNT is not 0 (step). S1542). As described above, this communication check counter CC-CNT includes a transmitter IC 4160d provided in the peripheral control board 4140, a frame, and a frame each time the connection failure determination process shown in FIG. 77 is executed in the determination of step S1522 in the process. The number of times when it is determined that there is a problem in the connection between the receiver IC 194f included in the decorative drive amplifier board 194, that is, the connection between the transmitter and the receiver is counted up (the cumulative number is counted). is there. In this determination, it is determined whether or not the number of times that it is determined that there is a problem in the connection between the transmitter and the receiver is once.

When the value of the communication check counter CC-CNT is 0 in step S1542, that is, when it is determined that the connection between the transmitter and the receiver is in a defective state, the number of times is not 1 On the other hand, when the value of the communication check counter CC-CNT is not 0 in step S1542 while ending the routine, that is, the number of times it is determined that the connection between the transmitter and the receiver is in a defective state is even once. If so, it is determined whether or not the value of the communication abnormality flag CC-FLG is 0 (step S1544). As described above, the communication abnormality flag CC-FLG indicates that the cumulative number of times when it is determined that the connection between the transmitter and the receiver has a failure reaches the cumulative number upper limit value CC-LMT, This is a flag that indicates whether or not the connection between the receiver and the receiver is definitely defective. When the connection between the transmitter and the receiver is definitely defective, the value is 1, and between the transmitter and the receiver. When the cumulative number of times determined to be in a state in which there is a failure in the connection has not reached the cumulative number upper limit value CC-LMT, the value is set to 0.

When the value of the communication abnormality flag CC-FLG is 0 in step S1544, that is, the cumulative number of times when it is determined that the connection between the transmitter and the receiver has a failure is the cumulative number upper limit value CC-LMT. If it has not reached, the SYNC pattern output processing is performed (step S1546), and this routine is ended. In this SYNC pattern output processing, the peripheral control MPU 4150a outputs a connection confirmation signal to the INIT terminal of the transmitter IC 4160d included in the peripheral control board 4140, so that the transmitter IC 4160d included in the peripheral control board 4140 causes the frame decoration drive amplifier board 194 to operate. A predetermined data pattern (SYNC pattern) is output to the provided receiver IC 194f. This predetermined data pattern (SYNC pattern) is stored in the transmitter IC 4160d in advance and is output to the receiver IC 194f, and is connected between the transmitter IC 4160d and the receiver IC 194f, that is, the transmitter and the receiver. It is to restore the connection between.

On the other hand, if the value of the communication abnormality flag CC-FLG is not 0 (value 1) in step S1544, that is, if the connection between the transmitter and the receiver is definitely defective, the communication error display processing is performed. (Step S1548), and this routine ends. In this communication error display processing, the display area of the game board side effect display unit 1900 included in the game board 4 shown in FIG. 8 is provided in order to notify that the connection between the transmitter and the receiver is definitely defective. The process of drawing is performed. For example, a message "A trouble has occurred between the transmitter and the receiver. Please call a clerk." is displayed in the display area of the game board side effect display unit 1900. Further, in the communication error display processing, a demonstration is performed by the game board side effect display unit 1900 during a period in which the start screen when the power of the pachinko game machine 1 is turned on is displayed on the game board side effect display unit 1900 or in a customer waiting state. In the period during which the operation is performed, whether there is a problem in the connection between the transmitter IC 4160d included in the peripheral control board 4140 and the receiver IC 194f included in the frame decoration drive amplifier board 194, that is, the connection between the transmitter and the receiver. In order to confirm whether the LOCKN signal output request data is transmitted from the LOCKN signal output request serial I/O port built in the peripheral control MPU4150a, the receiver IC 194f outputs the LOCKN signal output request data from the LOCKN terminal as a response signal to the transmission of the LOCKN signal output request data. A LOCKN signal is output to the peripheral control MPU 4150a, and when this LOCKN signal is not input, it is determined that there is a problem in the connection between the transmitter and the receiver, and a notification image (for example, "Transmitter" There was a problem between the receiver and the receiver. Please call the clerk.") performs the processing to display in the display area of the game board side effect display unit 1900, and also informs you (for example, "between transmitter and receiver. ") is repeatedly generated from the speaker 130 provided on the door frame 5. At this time, a process of turning on all of the plurality of LEDs provided on each decorative board of the door frame 5 and the plurality of LEDs provided on each decorative board of the game board 4 may be performed.

Next, the timing at which the peripheral control MPU 4150a outputs the connection confirmation signal to the INIT terminal of the transmitter IC 4160d included in the peripheral control board 4140 shown in FIG. 19 will be described with reference to the timing chart of FIG.

First, a brief description will be given of the decorative symbols that are variably displayed in the display area of the game board side effect display unit 1900 provided in the game board 4 shown in FIG. 8. Peripheral control of the peripheral controller power-on processing shown in FIG. 68. The variable display of the decorative symbol is executed by the unit steady process and the like. The main control side of the main control side power-on process shown in FIG. 49 by the main control MPU 4100a of the main control board 4100 shown in FIG. The first special lottery result selected by receiving the game balls into the first starting opening 2101 shown in FIG. 8 by the main processing or the main control side timer interrupt processing shown in FIG. 50, or the second shown in FIG. When the second special lottery result drawn by receiving the game balls into the starting opening 2102 becomes a "big hit", the number of times (round number) of opening/closing operation of the special winning opening 2103 shown in FIG. 8 is 1 to 15 rounds. Up to a total of 15 rounds, and in each round, a game ball enters the special winning opening 2103 within a predetermined time (for example, 30 seconds), and the number of balls reaches a predetermined number (for example, 9 balls), The round is designed to be exhausted, and a predetermined number (for example, 15 balls) of game balls are paid out each time one game ball enters the special winning opening 2103.

The first special lottery result drawn by receiving the game balls into the first starting opening 2101 or the second special lottery result drawn by receiving the game balls into the second starting opening 2102 is obtained from the main control board 4100. Based on the command, the peripheral control unit 4150 in the peripheral control board 4140 controls the liquid crystal and sound control unit 4160, so that the left side decorative pattern is on the left side of the display area of the game board side effect display unit 1900 and the central decoration is on the center. The design, and the variable display of the right decorative pattern is started on the right side, and after the predetermined time has passed, the variable display of the left decorative pattern, the central decorative pattern, and the right decorative pattern is stopped, and the first special lottery result or the second special lottery The result can be recognized by the player, and at this time, the first special symbol displayed on the upper special symbol display 1185 or the lower special symbol display 1186 shown in FIG. 13 on the function display unit 1180. Alternatively, the first special lottery result or the second special lottery result can be confirmed even in the second special symbol. When the left side decorative pattern, the central decorative pattern, and the right side decorative pattern are variably displayed, the left side decorative pattern, the central decorative pattern, and the right side decorative pattern are translucent to the extent that the background image is visible, and the left side decorative pattern is displayed. The reels rotate from the upper left side to the lower left side of the area, the central decorative pattern goes from the central upper side to the central lower side of the display area, and the right decorative pattern rotates from the upper right side to the lower right side of the display area. When the left decorative pattern, the central decorative pattern, and the right decorative pattern are displayed in a stopped manner while being variably displayed in an imaginary manner, the left displayed decorative pattern, the central decorative pattern, and the right decorative pattern are displayed in a stopped state. The left side decorative pattern, the central decorative pattern, and the right side decorative pattern are made opaque so that the background image at the position becomes difficult to be visually recognized. In this way, the first special symbol or the second special symbol that is started and stopped in the variable display start and stop display on the upper special symbol display 1185 or the lower special symbol display 1186 shown in FIG. 13 and the game board. The left side decorative design, the central decorative design, and the right decorative design, which start and stop variable display in the display area of the side effect display unit 1900, are synchronized.

The peripheral control unit 4150 in the peripheral control board 4140 is the first special lottery result selected by receiving the game ball into the first starting opening 2101 or the second special drawing that is received by receiving the game ball into the second starting opening 2102. When a command from the main control board 4100 that conveys the special lottery result is received, by controlling the liquid crystal and sound control section 4160 based on the received command, as shown in FIG. 79, the game board shown in FIG. When the variable display of the left side decorative design, the central decorative design, and the right side decorative design is started in the display area of the side effect display unit 1900 (timing K0), the peripheral control unit of the power-on process shown in FIG. In the scheduler update process of step S1020 in the steady process, the first of the screen data arranged in time series that constitutes the screen generation schedule data set in the schedule data storage area 4150cae of the peripheral control RAM 4150c shown in FIG. Since the pointer is updated in order to instruct which of the screen data is output to the sound source built-in VDP 4160a from the screen data, that is, in the scheduler update process, when the pointer is updated, according to the screen generation schedule data. Because the production is progressing, the screen generation schedule data is being activated, and while the screen generation schedule data is being activated, that is, the variable display of the left decorative pattern, the central decorative pattern, and the right decorative pattern is started. In the warning process of step S1024 in the peripheral control unit steady process of the peripheral control unit power-on process shown in FIG. 68, the connection restoration process shown in FIG. Also, the routine is forcibly terminated as it is in the determination of step S1540 in this connection recovery process.

Thereby, until the variable display of the left side decorative design, the central decorative design, and the right decorative design is started and stopped in the display area of the game board side effect display unit 1900, the communication check counter CC-CNT is displayed. Even when the value is not 0, that is, there is a problem between the connection between the transmitter IC 4160d included in the peripheral control board 4140 and the receiver IC 194f included in the frame decoration drive amplifier board 194 (that is, the connection between the transmitter and the receiver). Even if the number of times that it is determined that the state is occurring is even once, the process of recovering the connection between the transmitter and the receiver without performing the SYNC pattern output process of step S1546 in the connection recovery process. Is not performed, and the communication error display process of step S1548 in the connection recovery process is not performed. For example, in the display area of the game board side effect display unit 1900, "a problem occurs between the transmitter and the receiver. Since the message "Please call the clerk." is not displayed, the LOCKN signal from the receiver IC 194f that reports that the drawing data received from the transmitter IC 4160d is abnormal data is invalidated.

When the variable display of the left side decorative design, the central decorative design, and the right decorative design is started and stopped in the display area of the game board side effect display unit 1900 (timing K1), the peripheral controller power-on shown in FIG. 68 is turned on. In the scheduler update process of step S1020 in the peripheral control unit steady process of the time process, the effect is completed according to the screen generation schedule data set in the schedule data storage area 4150cae of the peripheral control RAM 4150c shown in FIG. Since all the updates have been completed, that is, while the screen generation schedule data has not been activated and the screen generation schedule data has not been activated in the scheduler update process, the peripheral controller power-on shown in FIG. 68 is turned on. 78 is executed as one process of the warning process of step S1024 in the peripheral control unit steady process of the time process, the process proceeds to the process of step S1542 in the connection recovery process shown in FIG. When the value of CNT is 0, that is, when the number of times when it is determined that the connection between the transmitter and the receiver is in a defective state is not once, the routine is ended as it is, while the communication check counter When the value of CC-CNT is not 0, that is, when the number of times the connection between the transmitter and the receiver has been determined to be defective is once, the process proceeds to step S1544 in the same process. When the value of the communication abnormality flag CC-FLG is 0, that is, the cumulative number of times when it is determined that there is a problem in the connection between the transmitter and the receiver becomes the cumulative number upper limit value CC-LMT. If not reached, the process proceeds to step S1546 in the same process, the above-mentioned SYNC pattern output process is performed, and the routine is ended, while the value of the communication abnormality flag CC-FLG is not 0 (value 1), That is, when the connection between the transmitter and the receiver is definitely defective, the process proceeds to step S1548 in the same process, the above-mentioned communication error display process is performed, and the routine is ended. In other words, while the left decorative design, the central decorative design, and the right decorative design are stopped and displayed in the display area of the game board side effect display unit 1900, the transmitter IC 4160d and the receiver IC 194f are connected, that is, the transmitter and the receiver. The cumulative number of times when it has been determined that there is a failure in the connection between the transmitter and the receiver even if there is a failure in the connection between the When the value CC-LMT is not reached, the SYNC pattern output process is performed without fail to perform the process of recovering the connection between the transmitter IC 4160d and the receiver IC 194f, that is, the connection between the transmitter and the receiver. When the cumulative number of times when it is determined that the connection between the receiver and the terminal is in a state of failure has reached the cumulative number upper limit value CC-LMT (that is, the connection between the transmitter and the receiver is definitely defective). In the display area of the game board side effect display unit 1900, for example, "A trouble has occurred between the transmitter and the receiver. Please call a clerk." The process of displaying and notifying a message is performed, and the LOCKN signal from the receiver IC 194f that reports that the drawing data received from the transmitter IC 4160d is abnormal data is validated.

In the display area of the game board side effect display unit 1900, the variable display of the left decorative pattern, the central decorative pattern, and the right decorative pattern is started and stopped, and the variable display of the left decorative pattern, the central decorative pattern, and the right decorative pattern is again displayed. In the interval period until the start, since the left side decorative design, the central decorative design, and the right decorative design are stopped and displayed in the display area of the game board side effect display unit 1900, as described above, The LOCKN signal from the receiver IC 194f, which notifies that the drawing data received from the transmitter IC 4160d is abnormal data, is enabled, and a problem occurs in the connection between the transmitter IC 4160d and the receiver IC 194f, that is, the connection between the transmitter and the receiver. In the case where the number of accumulated times is at least once and the accumulated number of times when it is determined that there is a problem in the connection between the transmitter and the receiver does not reach the accumulated number upper limit value CC-LMT. , SYNC pattern output processing must be performed to restore the connection between the transmitter IC 4160d and the receiver IC 194f, that is, the connection between the transmitter and the receiver, while the connection between the transmitter and the receiver has a problem. When the cumulative number of times determined to be in the state of reaching reaches the cumulative number upper limit value CC-LMT (that is, the connection between the transmitter and the receiver is definitely defective), a communication error display is displayed. By performing the processing without fail, for example, a processing of displaying a message "A trouble has occurred between the transmitter and the receiver. Please call a salesclerk." in the display area of the game board side effect display unit 1900 to notify. I am supposed to do it.

When the variable display of the left side decorative pattern, the central decorative pattern, and the right side decorative pattern is started again (timing K2), as described above, since the screen generation schedule data is being activated, the left side decorative pattern and the central decorative pattern. , And until the right decorative pattern is stopped and displayed (timing K3), even when the value of the communication check counter CC-CNT is not 0, that is, the transmitter IC 4160d provided in the peripheral control board 4140 and the frame. Even when the number of times that it is determined that there is a problem between the connection with the receiver IC 194f included in the decorative drive amplifier board 194 (that is, the connection between the transmitter and the receiver) is once, The SYNC pattern output process of step S1546 in the connection recovery process is not performed, the process of recovering the connection between the transmitter and the receiver is not performed, and the communication error display process of step S1548 in the connection recovery process is performed. No, for example, the message "A trouble has occurred between the transmitter and the receiver. Please call the store clerk." is not displayed in the display area of the game board side effect display unit 1900. Therefore, from the transmitter IC 4160d. The LOCKN signal from the receiver IC 194f that reports that the received drawing data is abnormal data is invalidated.

In this way, the variable display of the left side decorative design, the central decorative design, and the right decorative design is started and stopped in the display area of the game board side effect display unit 1900, and the left decorative design, the central decorative design, and the right decorative are again displayed. In the interval period until the variable display of the symbols is started, the LOCKN signal from the receiver IC 194f that informs that the drawing data received from the transmitter IC 4160d is abnormal data is enabled, while the game board side effect display unit In the display area of 1900, it is reported that the drawing data received from the transmitter IC 4160d is abnormal data until the variable display of the left decorative pattern, the central decorative pattern, and the right decorative pattern is started and stopped. The LOCKN signal from the receiver IC 194f is invalidated. This is because the combination result of the left decorative design, the central decorative design, and the right decorative design that are stopped and displayed in the display area of the game board side effect display unit 1900 is the information that is of most interest to the player, and is beneficial to the player. Since the player can determine whether or not the jackpot gaming state in which is given occurs, the left side decorative design, the central decorative design, and the right decorative design are variably displayed in the display area of the game board side effect display unit 1900. Then, until the left decorative pattern, the central decorative pattern, and the right decorative pattern are stopped and displayed, the process for recovering the connection failure between the transmitter and the receiver is not performed, but the game board side effect The left-side decorative pattern, the central decorative pattern, and the right-side decorative pattern are stopped and displayed in the display area of the display unit 1900, thereby completing the drawing of the information that the player is most interested in.

In this respect, a period during which the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 displays the startup screen when the power of the pachinko gaming machine 1 is turned on on the game board side effect display unit 1900, or a customer waiting state. During the demonstration by the game board side effect display unit 1900, the LOCKN signal output request data is transferred from the built-in LOCKN signal output request serial I/O port to the differential circuit 4160e provided in the peripheral control board 4140. It is very different from sending. This LOCKN signal output request data is a demonstration by the game board side effect display unit 1900 while the startup screen at the time of turning on the power of the pachinko game machine 1 is displayed on the game board side effect display unit 1900, or in a customer waiting state. During a period of time, the LOCKN signal output request serial I/O port built in the peripheral control MPU 4150a is transmitted, and the transmitter IC 4160d included in the peripheral control board 4140 and the receiver included in the frame decoration drive amplifier board 194 are included. It is transmitted in order to confirm whether or not there is a problem in the connection between the IC 194f and the IC 194f, that is, the connection between the transmitter and the receiver.

The LOCKN signal output request data, which is the serial data output from the LOCKN signal output request serial I/O port built in the peripheral control MPU 4150a, has a difference between the plus signal and the minus signal in the differential circuit 4160e included in the peripheral control board 4140. When activated, as described above, the two signals differentiated into the plus signal and the minus signal in the differential circuit 4160e are input to the forced switching circuit 4160f provided in the peripheral control board 4140. Since the forced switching circuit 4160f is connected to the circuit so as to transmit the two signals when the two signals that are differentiated into the plus signal and the minus signal in the differential circuit 4160e are input, One signal is transmitted from the peripheral control board 4140 to the frame decoration drive amplifier board 194 of the door frame 5. When the receiver IC 194f included in the frame decoration drive amplifier board 194 determines that the received two signals are LOCKN signal output request data from the LOCKN signal output request serial I/O port, in the first place, LOCKN signal output request data is received. Has a structure in which the data format is different from the signal output from the transmitter IC 4160d as described above, it is determined to be abnormal data, and the LOCKN signal is sent to the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140. Output. As a result, the peripheral control MPU 4150a can determine that the connection between the transmitter and the receiver is not defective when the LOCKN signal is input as the response signal to the transmission of the LOCKN signal output request data. , When the LOCKN signal is not input, it is determined that there is a problem in the connection between the transmitter and the receiver, and a notification image (for example, "A problem occurs between the transmitter and the receiver." "Please call a clerk.") is output to the game board side effect display unit 1900 by controlling the VDP 4160a with a built-in sound source, and at the same time, a notification sound (for example, "a trouble occurs between the transmitter and the receiver"). ") is output to the audio data transmission IC 4160c by controlling the VDP 4160a with a built-in sound source, and a notification sound is output from the speaker 130 provided in the door frame 5. As a result, the notification can be performed by the notification image displayed in the display area of the game board side effect display unit 1900 and the notification sound repeatedly played from the speaker 130 provided in the door frame 5. At this time, the plurality of LEDs provided on each decorative board of the door frame 5 and the plurality of LEDs provided on each decorative board of the game board 4 may all be turned on.

As described above, when the peripheral control MPU 4150a of the peripheral control unit 4150 transmits the LOCKN signal output request data, which is serial data, from the built-in LOCKN signal output request serial I/O port, the forced switching circuit 4160f causes the LOCKN signal output request data. Is connected to the receiver IC194f so that the receiver IC194f that receives the LOCKN signal output request data outputs the LOCKN signal from the LOCKN terminal of the receiver IC194f to the peripheral control MPU4150a as a response signal. , When the LOCKN signal is input, it can be determined that the connection between the transmitter and the receiver is not defective, while when the LOCKN signal is not input, the connection between the transmitter and the receiver is defective. Can be determined to have occurred. When the peripheral control MPU 4150a determines that a malfunction has occurred between the transmitter and the receiver, the peripheral control MPU 4150a can execute the communication error display process of step S1548 in the connection recovery process of FIG. 78 as the notification process. Is becoming In other words, when the peripheral control MPU 4150a finds a problem between the transmitter and the receiver, it can notify the clerk of the hall by performing a notification process. The store clerk can check whether or not there is a problem between the transmitter and the receiver before the player plays the game, and it does not take time to check. .. Therefore, the trouble between the transmitter and the receiver can be found without any trouble.

As described above, the LOCKN signal informs the receiver IC 194f included in the frame decoration drive amplifier board 194 that the drawing data received from the transmitter IC 4160d included in the peripheral control board 4140 is abnormal data. Is a signal to be output in order to confirm the connection between the transmitter IC 4160d included in the peripheral control board 4140 and the receiver IC 194f included in the frame decoration drive amplifier board 194, that is, the connection between the transmitter and the receiver. Since the signal is output to request the transmission of a predetermined data pattern (SYNC pattern) for (recovery), the receiver IC 194f has the receiver IC 194f and the transmitter IC 4160d when it cannot normally receive the image transmitted from the transmitter IC 4160d. The LOCKN signal can be output to the peripheral control MPU 4150a of the peripheral control unit 4150 in order to inform that the received drawing data becomes abnormal data due to a communication failure between the image communication. As a result, the peripheral control MPU 4150a to which the LOCKN signal is input outputs a connection confirmation signal to the transmitter IC 4160d notifying that transmission of a predetermined data pattern (SYNC pattern) is started from the transmitter IC 4160d to the receiver IC 194f. It is possible to solve the communication problem in. In other words, the peripheral control MPU 4150a can detect a defect between the transmitter and the receiver due to a communication defect during image communication at an early stage and can work on the transmitter IC 4160d so as to eliminate the defect. Therefore, it is possible to suppress a decrease in the player's willingness to play a game by finding and eliminating a defect between the transmitter and the receiver.

Further, when the receiver IC 194f receiving the image transmitted from the transmitter IC 4160d cannot normally receive the image transmitted from the transmitter IC 4160d, the receiver IC 194f informs that there is a communication failure between the image communication between the receiver IC 194f and the transmitter IC 4160d. Since the LOCKN signal, which is a communication failure occurrence signal, can be output to the peripheral control MPU 4150a of the peripheral control unit 4150, which is a production control microprocessor, the peripheral control MPU 4150a to which the LOCKN signal is input is the liquid crystal and the sound. Generates the message "There was a problem between the transmitter and the receiver. Please call the store clerk.", which is an image that controls the VDP 4160a with a built-in sound source of the control unit 4160 and reports that there is a communication problem. The generated image can be displayed and notified in the display area of the game board side effect display unit 1900. In other words, the peripheral control MPU 4150a finds a defect between the transmitter and the receiver due to a communication defect during image communication at an early stage, and notifies the player sitting on the front of the pachinko gaming machine 1 to that effect, and Since the player can inform the store clerk of the hall or directly notify the store clerk of the hall who happened to pass in front of the pachinko gaming machine 1, the store clerk of the hall will be in trouble. You can start work to resolve the problem at an early stage. Therefore, it is possible to suppress a decrease in the player's willingness to play a game by early detecting and eliminating a defect between the transmitter and the receiver.

Furthermore, the peripheral control MPU 4150a of the peripheral control unit 4150 connects the transmitter IC 4160d included in the peripheral control board 4140 and the receiver IC 194f included in the frame decoration drive amplifier board 194 during the period (interval period) from timing K1 to timing K2. If the connection between the transmitter and the receiver has failed at least once, that is, it is determined that the connection between the transmitter and the receiver has failed. When the cumulative number does not reach the cumulative number upper limit value CC-LMT, start transmission of a predetermined data pattern (SYNC pattern) from the transmitter IC 4160d to the receiver IC 194f for enabling the LOCKN signal and eliminating communication failure between image communication. It is possible to continue to output the connection confirmation signal to the transmitter IC 4160d repeatedly to the effect that the accumulated number reaches the accumulated number upper limit value CC-LMT. Thereby, the peripheral control MPU4150a of the peripheral control unit 4150, the main control MPU4100a of the main control board 4100 starts the first special symbol or the second special symbol game in the upper special symbol display 1185 or the lower special symbol display 1186. Since the connection confirmation signal can be repeatedly output only during the period in which the game is stopped and displayed and the progress of the game is not executed, it is possible to move toward the direction in which the communication failure is eliminated.

The peripheral control MPU 4150a of the peripheral control unit 4150 connects the transmitter IC 4160d included in the peripheral control board 4140 and the receiver IC 194f included in the frame decoration drive amplifier board 194 during the connection between the timing K1 and the timing K2 (interval period). In other words, if the connection between the transmitter and the receiver has been in trouble at least once, and the connection between the transmitter and the receiver is in trouble When the number of times does not reach the cumulative number upper limit value CC-LMT, the LOCKN signal is validated to start transmitting a predetermined data pattern (SYNC pattern) from the transmitter IC 4160d to the receiver IC 194f in order to eliminate the communication failure between the image communication. The main control MPU 4100a of the main control board 4100 is the upper special symbol display device 1185 while continuously outputting the connection confirmation signal to the effect to the transmitter IC 4160d until the cumulative number reaches the cumulative number upper limit value CC-LMT. Or, the output of the connection confirmation signal is stopped when the first special symbol or the second special symbol is started to change and the progress of the game is started again on the lower special symbol display 1186, and the transmitter IC 4160d is output from the peripheral control MPU 4150a. When the connection confirmation signal is stopped and the connection confirmation signal is not input, the transmission of a predetermined data pattern (SYNC pattern) to the receiver IC 194f is stopped, and the sound source built-in VDP 4160a of the liquid crystal and sound control unit 4160 generates it. The image can be output to the receiver IC 194f. Thereby, the peripheral control MPU4150a of the peripheral control unit 4150, the main control MPU4100a of the main control board 4100 starts the first special symbol or the second special symbol game in the upper special symbol display 1185 or the lower special symbol display 1186. By continuing to output the connection confirmation signal, which is the defect resolution signal, only during the period when the game is stopped and the game progress is not executed, it becomes possible to move toward the direction where the communication defect is resolved. Therefore, the main control MPU4100a of the main control board 4100 starts the variation by starting and stopping the first special symbol or the second special symbol game on the upper special symbol display 1185 or the lower special symbol display 1186 to display the progress of the game. Only during the period of not being executed, while continuing to output the connection confirmation signal repeatedly, the main control MPU 4100a of the main control board 4100 has the first special symbol on the upper special symbol display 1185 or the lower special symbol display 1186. Even if the variation of the second special symbol game is started and the progress of the game is started again, the problem between the transmitter and the receiver is terminated by the main control MPU 4100a of the main control board 4100 starting the progress of the game again. Every time it is performed (every time period (interval period) of timing K1 to timing K2), it is possible to move toward the elimination direction.

[19. Screen displayed in the display area of the game board side effect display unit]
Next, a screen displayed in the display area of the game board side effect display unit 1900 included in the game board 4 shown in FIG. 8 will be briefly described with reference to FIGS. 80 to 84. The screen displayed in the display area of the game board side effect display unit 1900 is the periphery of the peripheral control unit power-on process shown in FIG. 68 by the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 shown in FIG. It is displayed by executing the control unit steady process. As a result, various effects are advanced in the display area of the game board side effect display unit 1900. Here, first, an example of the effect of the variable display displayed in the display area of the game board side effect display unit 1900 will be described, and subsequently, the display area of the game board side effect display unit 1900 is displayed with switching of the light guide plate. An example of the effect produced will be described. 80 is a diagram showing an example of the variable display effect displayed in the display area of the game board side liquid crystal display device, and FIG. 81 is displayed in the display area of the game board side effect display unit with switching of the light guide plate. 82 is a diagram showing an example of an effect, FIG. 82 is a diagram showing an example of an effect continued from FIG. 81, FIG. 83 is a diagram showing an example of an effect continued from FIG. 82, and FIG. 84 is an effect continued from FIG. It is a figure showing an example of the production of.

[19-1. Effect of variable display displayed in the display area of the game board side effect display unit]
First, the effect of variable display displayed in the display area of the game board side effect display unit 1900 will be described with reference to FIG. 80. 8 by the main control side main processing of the main control side power-on processing shown in FIG. 49 by the main control MPU 4100a of the main control board 4100 shown in FIG. 14 and the main control side timer interrupt processing shown in FIG. The first special lottery result drawn by receiving the game balls into the first starting opening 2101 or the second special lottery result drawn by receiving the game balls into the second starting opening 2102 shown in FIG. When it becomes a "big hit", the number of times of repeating the opening/closing operation of the special winning opening 2103 shown in FIG. 8 (the number of rounds) is 15 rounds in total from 1 round to 15 rounds, and in each round, within a predetermined time (for example, 30 seconds). In, when a game ball enters the special winning opening 2103 and the number of the balls reaches a predetermined number (for example, 9 balls), the round is exhausted, and the game ball 1 enters the special winning opening 2103. Every time a ball is entered, a predetermined number (for example, 15 balls) of game balls are paid out.

The first special lottery result drawn by receiving the game balls into the first starting opening 2101 or the second special lottery result drawn by receiving the game balls into the second starting opening 2102 is obtained from the main control board 4100. The peripheral control unit 4150 of the peripheral control board 4140 shown in FIG. 17 controls the liquid crystal and sound control unit 4160 based on the effect commands relating to the game effect which are the various commands shown in FIG. As shown in FIG. 5, the variable display of the decorative design 1950a on the left side of the display area of the game board side effect display unit 1900, the decorative design 1950b on the center, and the decorative design 1950c on the right side is started, and after a predetermined time elapses, decoration is performed. The variable display of the symbols 1950a to 1950c is stopped so that the player can recognize the first special lottery result or the second special lottery result. At this time, the first special lottery result or the second special symbol also in the first special symbol or the second special symbol displayed on the upper special symbol display 1185 or the lower special symbol display 1186 shown in the function display unit 1180 shown in FIG. You can check the lottery results. When the decorative patterns 1950a to 1950c are variably displayed, the decorative patterns 1950a to 1950c become translucent to such an extent that the background image can be visually recognized. Is displayed from the center upper side to the center lower side of the display area, and the decorative pattern 1950c is variably displayed as if the reels are rotating from the upper right side to the lower right side of the display area. There is.

Specifically, in the peripheral control unit command reception interrupt processing of FIG. 71, the effect control program executed by the peripheral control MPU 4150a receives various commands from the main control board 4100. Then, in the received command analysis process of step S1022 in the peripheral control unit steady process of the peripheral control unit power-on process of FIG. 68, the effect control program analyzes the various commands received in the peripheral control unit command reception interrupt process of FIG. I do. If the analyzed command is, for example, the special figure 1 entrainment effect start command classified into the special figure 1 entrainment effect related command shown in FIG. 45, the effect control program is displayed in the effect pattern designated in this mode as shown in FIG. ), the peripheral control unit sets the screen generation schedule data, the light emission mode generation schedule data, the sound generation schedule data, the electric drive source schedule data, etc., which are set in the variable display mode of the decorative patterns 1950a to 1950b. It is extracted from various control data copy areas 4150ce of the peripheral control ROM 4150b or peripheral control RAM 4150c of 4150 and set in the schedule data storage area 4150cae of the peripheral control RAM 4150c.

For example, the screen generation schedule data set in the variable display mode of the decorative patterns 1950a to 1950b is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or the various control data copy area 4150ce of the peripheral control RAM 4150c, and the schedule of the peripheral control RAM 4150c is extracted. When set in the data storage area 4150cae, the pointer is updated in the scheduler update process of step S1020 in the peripheral controller steady process of the peripheral controller power-on process of FIG. 68, and in the display data creation process of step S1030 in the same process. Of the screen data arranged in time series constituting the screen generation schedule data, the screen data indicated by the pointer is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or the various control data copy areas 4150ce of the peripheral control RAM 4150c. And outputs it to the sound source built-in VDP 4160a.

When the screen data and the light emission data are input from the peripheral control MPU 4150a, the sound source built-in VDP 4160a causes the game board side effect display unit 1900 from the liquid crystal and sound control ROM 4160b based on the input screen data and the light emission data. The game board side character data for drawing in the display area of the liquid crystal panel 5000e (display area of the game board side effect display unit 1900) and the above-mentioned predetermined screen (red (R): 50% in the present embodiment, Sprite data is created by extracting dummy data for drawing green (G): 50%, blue (B): 50% gray screen), and game board side effect display unit 1900 (liquid crystal panel). Drawing data for one screen (one frame) drawn (displayed) on 5000e) and a predetermined screen (in the present embodiment, red (R): 50%, green (G): 50%, blue (B)). : Drawing data for one screen (one frame) for drawing (displaying) a gray screen having 50% is generated in the built-in VRAM.

Specifically, the sound source built-in VDP 4160a is screen data that defines the configuration of the screen drawn on the game board side effect display unit 1900 (liquid crystal panel 5000e), and the sound source built-in VDP 4160a of each decorative board of the game board 4 is The light emission data that defines the light emission mode of the plurality of LEDs (decorative LEDs) provided on each of the plurality of game board side VDP control target decoration substrates that are directly controlled, is input from the peripheral control MPU 4150a. Then, according to a predetermined game board side generation rule, based on the input screen data, game board side character data for drawing in the display area of the game board side effect display unit 1900 is extracted from the liquid crystal and sound control ROM 4160b. Then, sprite data is created to generate game board side drawing data in the game board side drawing data area VRGN1a of the game board side display area VRGN1 provided on the built-in VRAM, and based on the input light emission data. , The liquid crystal and sound control ROM 4160b, among the decorative boards of the game board 4, a plurality of LEDs (decoration) provided on each of the plurality of game board-side VDP controlled decoration boards that are directly controlled by the sound source built-in VDP 4160a. Game board side light emitting mode setting image data for setting the light emitting mode of the game LED side, and the game board side display area VRGN1 provided on the built-in VRAM as the light guide plate information and the electric decoration information as drawing data. It is generated in the side incidental information area VRGN1b.

Here, as the light guide plate information, the first light guide plate 5000d shown in FIG. 10 is selected from the plurality of light guide plates included in the game board side effect display unit 1900, and the content of surface emission is specified, and other information is specified. The light-guiding plates (the second light-guiding plate 5000f, the third light-guiding plate 5000g, the fourth light-guiding plate 5000h, the fifth light-guiding plate 5000i, and the sixth light-guiding plate 5000k) that do not emit surface light and are turned off are designated. There is.

Then, in the display data output process of step S1016 in the same process, the effect control program outputs the drawing data for one screen (one frame) generated in the built-in VRAM of the sound source built-in VDP 4160a in the above-described display data creation process. .. That is, the light guide plate information and the illumination information are added to the game board side drawing data of the screen drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e) according to the above-mentioned predetermined game board side generation rule. As a result, the sound source built-in VDP 4160a outputs the drawing data generated in the game board side display area VRGN1 to the game board side effect display unit 1900 from the channel CH1 shown in FIG. As a result, in the display area of the game board side effect display unit 1900, the variable display screen of the decorative symbols 1950a to 1950b shown in FIG. 80A is drawn (displayed).

As shown in FIG. 80(a), the variable display of the decorative symbols 1950a to 1950c is stopped when the stop symbols of the decorative symbols 1950a to 1950c are stopped and displayed with the same decorative symbol after a predetermined time has elapsed after the start. It is a big hit. On the other hand, after the variable display of the decorative symbols 1950a to 1950c has started and a predetermined time has elapsed, as shown in FIG. 80(b), the stop symbols of the decorative symbols 1950a to 1950c are not stopped and displayed with the same decorative symbol, It will be “out”.

In the present embodiment, when the state in which the game ball does not enter the first starting port 2101 or the second starting port 2102 continues and the reserved balls are exhausted to become zero pieces for a predetermined time (for example, , (60 seconds in the present embodiment), the first light guide plate 5000d is selected from the plurality of light guide plates included in the game board side effect display unit 1900 to perform surface emission, and the customer shown in FIG. A demonstration screen, which is a standby screen, is drawn (displayed) in the display area of the game board side effect display unit 1900. At this time, the sound effect and the music are set to be muted. When the demonstration screen is advanced and displayed a predetermined number of times (for example, 15 times in the present embodiment) in the display area of the game board side effect display unit 1900, the power saving mode is entered and the game board side effect is displayed. Nothing is displayed in the display area of the display unit 1900 (that is, a black screen). At this time, various lamps provided on the door frame 5 and various lamps provided on the game board 4 shown in FIG. 2 are also turned off.

[19-2. Effects displayed along with the switching of the light guide plate in the display area of the game board side effect display unit]
Next, effects (hereinafter, referred to as “specific effects”) displayed in the display area of the game board side effect display unit 1900 with switching of the light guide plate will be described with reference to FIGS. 81 to 84. .. The effect accompanied by the switching of the light guide plate is performed during the specific effect execution period from the start of the variable display of the decorative symbols 1950a to 1950b shown in FIG. 80A to the stop display thereof.

The first special lottery result drawn by receiving the game balls into the first starting opening 2101 or the second special lottery result drawn by receiving the game balls into the second starting opening 2102 is obtained from the main control board 4100. The peripheral control unit 4150 of the peripheral control board 4140 shown in FIG. 17 controls the liquid crystal and sound control unit 4160 based on the effect commands relating to the game effect which are the various commands shown in FIG. As shown in FIG. 5, the variable display of the decorative design 1950a on the left side, the decorative design 1950b on the center, and the decorative design 1950c on the right side of the display area of the game board side effect display unit 1900 is started, and the specific effect execution period comes. Then, after the effect accompanied by the switching of the light guide plate is performed, the variable display of the decorative symbols 1950a to 1950c is stopped and the player can recognize the first special lottery result or the second special lottery result. ing. At this time, the first special lottery result or the second special lottery result is confirmed even in the first special symbol or the second special symbol displayed on the upper special symbol display 1185 or the lower special symbol display 1186 of the function display unit 1180. You can do it.

When the decorative patterns 1950a to 1950c are variably displayed, the decorative patterns 1950a to 1950c become translucent to such an extent that the background image can be visually recognized. Is displayed from the center upper side to the center lower side of the display area, and the decorative pattern 1950c is variably displayed as if the reels are rotating from the upper right side to the lower right side of the display area. There is. Then, when the variable display of the decorative symbols 1950a to 1950c is started and the specific effect execution period comes, the decorative symbols 1950a to 1950c head toward the lower right corner after the display area of the liquid crystal side effect display unit 1900, although not shown. While moving, the whole shape is reduced and the variable display is continued, and when the movement to the lower right corner is completed, the existence disappears. At this time, the variable display of the first special symbol or the second special symbol displayed on the upper special symbol display 1185 or the lower special symbol display 1186 of the function display unit 1180 is continued.

Then, after the specific effect execution period has elapsed, another effect is advanced, and the decorative symbols 1950a to 1950c are displayed again in the lower right corner after the display area of the liquid crystal side effect display unit 1900, and the lower right While moving from the side corner to the original position at the start of the variation, the overall shape is enlarged to the original size, the variation display of the decorative patterns 1950a to 1950c is stopped, and the first special lottery result or the second The player can recognize the result of the special lottery.

When the specific effect execution period comes, since the first light guide plate 5000d of the liquid crystal side effect display unit 1900 in which the decorative symbols 1950a to 1950c are variably displayed is selected, the first light guide plate 5000d is selected. Becomes a backlight (in this case, the light guide plate information specifies that the first light guide plate 5000d is selected from the plurality of light guide plates included in the game board side effect display unit 1900 and the surface light emission is specified. In addition, the other light guide plates (the second light guide plate 5000f, the third light guide plate 5000g, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k) are not turned on and do not emit light. The content is specified.), and the image character CHA appears in the display area of the liquid crystal panel 5000e of the liquid crystal side effect display unit 1900, as shown in FIG. 81(a). Then, the process proceeds to the effect of the bullet flying toward the image character CHA.

When a predetermined number of bullets fly toward the image character CHA, the second light guide plate 5000f becomes a backlight by switching from the first light guide plate 5000d of the liquid crystal side effect display unit 1900 to the second light guide plate 5000f. (In this case, the light guide plate information specifies that the second light guide plate 5000f is selected from the plurality of light guide plates included in the game board side effect display unit 1900 to perform surface emission, and the other light guide plates are specified. It is specified that the (first light guide plate 5000d, the third light guide plate 5000g, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k) is turned off without surface emission. ), in the display area of the liquid crystal panel 5000e of the liquid crystal side effect display unit 1900 corresponding to the light emitting area 5000f4 formed on the second light guide plate 5000f, as shown in FIG. 81(b), toward the image character CHA. A player sits in front of the pachinko gaming machine 1 through a predetermined number of holes through which bullets have flown, and through a region RGN (that is, a non-light emitting region 5000f3 formed in the second light guide plate 5000f) formed by the holes. Is in a state in which a part (hereinafter, referred to as “first part”) of an object existing behind the liquid crystal side effect display unit 1900 can be visually recognized. At this time, of the objects existing behind the liquid crystal side effect display unit 1900, the rotary lighting device 3100 shown in FIG. 8 lights up in red and rotates (the rotation lighting mode is as described above. , Not realized by rotating the reflector by an electric drive source such as a motor, but realized by adjusting the order in which a plurality of LEDs mounted on the decorative substrate are turned on. Therefore, the red light becomes stronger or weaker through the region RGN (that is, the non-light emitting region 5000f3 formed in the second light guide plate 5000f).

When a predetermined number of bullets fly toward the image character CHA, the second light guide plate 5000f of the liquid crystal side effect display unit 1900 is switched to the third light guide plate 5000g, so that the third light guide plate 5000g becomes a backlight. (In this case, the light guide plate information specifies that the third light guide plate 5000g is selected from the plurality of light guide plates included in the game board side effect display unit 1900 and the surface emission is performed, and other light guide plates are selected. It is specified that the light plates (the first light guide plate 5000d, the second light guide plate 5000f, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k) are turned off without surface emission. ,) in the display area of the liquid crystal panel 5000e of the liquid crystal side effect display unit 1900 corresponding to the light emitting area 5000g4 formed on the third light guide plate 5000g, as shown in FIG. 82(c). , A non-light-emitting area 5000g formed on the third light guide plate 5000g 3) A predetermined number of holes are opened by bullets, and the area formed by the hole opened this time in addition to the holes opened so far Through the RGN, the player sitting on the front surface of the pachinko gaming machine 1 has other parts (hereinafter, referred to as “second part”) in addition to the first part among the objects existing behind the liquid crystal side effect display unit 1900. .) is visible. At this time, of the objects existing behind the liquid crystal side effect display unit 1900, the rotary light emitting device 3100 is in the rotation lighting mode. Therefore, the red light becomes stronger or weaker through the region RGN (that is, the non-light-emitting region 5000g3 formed in the third light guide plate 5000g). The strength can be greatly felt by the player.

When a predetermined number of bullets fly toward the image character CHA, the third light guide plate 5000g of the liquid crystal side effect display unit 1900 is switched to the fourth light guide plate 5000h, so that the fourth light guide plate 5000h becomes a backlight. (In this case, the light guide plate information specifies that the fourth light guide plate 5000h is selected from the plurality of light guide plates included in the game board side effect display unit 1900 and the surface emission is performed, and other light guide plates are selected. It is specified that the light plates (the first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k) are turned off without surface emission. ), the display area of the liquid crystal panel 5000e of the liquid crystal side effect display unit 1900 corresponding to the light emitting area 5000h4 formed on the fourth light guide plate 5000h faces the image character CHA as shown in FIG. 82(d). A predetermined number of holes in which the bullets have been blown are further opened, and in addition to the holes opened so far, a region RGN formed by the holes opened this time (that is, a non-light emitting region 5000h3 formed in the fourth light guide plate 5000h3 ), the player sitting on the front surface of the pachinko gaming machine 1 becomes able to visually recognize other parts of the object existing behind the liquid crystal side effect display unit 1900 in addition to the second part. .. At this time, of the objects existing behind the liquid crystal side effect display unit 1900, the rotary light emitting device 3100 is in the rotation lighting mode. Therefore, the red light becomes stronger or weaker through the region RGN (that is, the non-light-emitting region 5000h3 formed in the fourth light guide plate 5000h). The strength can be felt more and more by the player.

When a predetermined number of bullets fly toward the image character CHA, the fifth light guide plate 5000i is switched to the backlight by switching from the fourth light guide plate 5000h of the liquid crystal side effect display unit 1900 to the fifth light guide plate 5000i. (In this case, the light guide plate information specifies that the fifth light guide plate 5000i is selected from the plurality of light guide plates included in the game board side effect display unit 1900 and the surface emission is performed, and the other light guide plates are selected. It is specified that the light plates (the first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000h, the fourth light guide plate 5000h, and the sixth light guide plate 5000k) are turned off without surface emission. ), the display area of the liquid crystal panel 5000e of the liquid crystal side effect display unit 1900 corresponding to the light emitting area 5000i4 formed on the fifth light guide plate 5000i has been opened so far as shown in FIG. 83(e). Due to the holes, the display area of the liquid crystal panel 5000e is broken and broken into pieces, and a plurality of pieces are peeled off. Through 5000i3), the player sitting on the front surface of the pachinko gaming machine 1 becomes able to visually recognize that there are a plurality of objects existing behind the liquid crystal side effect display unit 1900. At this time, of the objects existing behind the liquid crystal side effect display unit 1900, the rotary light emitting device 3100 is in the rotation lighting mode. Therefore, the red light becomes stronger or weaker through the region RGN (that is, the non-light emitting region 5000i3 formed in the fifth light guide plate 5000i). The strength can be felt even more by the player.

Then, after that, by switching from the fifth light guide plate 5000i of the liquid crystal side effect display unit 1900 to the sixth light guide plate 5000k, the sixth light guide plate 5000k becomes a backlight (in this case, the light guide plate information is , Of the plurality of light guide plates included in the game board side effect display unit 1900, the sixth light guide plate 5000k is selected to specify the surface light emission, and other light guide plates (first light guide plate 5000d, first light guide plate 5000d, It is specified that the second light guide plate 5000f, the third light guide plate 5000h, the fourth light guide plate 5000h, and the fifth light guide plate 5000i) are turned off without surface emission), and the sixth light guide plate 5000k. In the display area of the liquid crystal panel 5000e of the liquid crystal side effect display unit 1900 corresponding to the formed light emitting area 5000k4, as shown in FIG. 83(f), a strip-shaped "press the detonation button!" Message MSG is displayed, and through the area RGN (that is, the non-light emitting area 5000k3 formed in the sixth light guide plate 5000k) formed above the area in which this message MSG is displayed, the pachinko gaming machine 1 The player sitting on the front can visually recognize the rotary light emitting device 3100 existing behind the liquid crystal side effect display unit 1900, and excludes a region corresponding to the light emitting region 5000k4 formed on the sixth light guide plate 5000k. Then, the model 3400 imitating the detonator and the model 3500 imitating dynamite can be visually recognized. At this time, of the objects existing behind the liquid crystal side effect display unit 1900, the rotary light emitting device 3100 is in the rotation lighting mode. Therefore, the red light becomes stronger or weaker through the region RGN (that is, the non-light-emitting region 5000k3 formed in the sixth light guide plate 5000k). The strength can be felt even more by the player.

Then, after that, the first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000g, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k are all surfaces. While not emitting light (in this case, the light guide plate information includes a plurality of light guide plates included in the game board side effect display unit 1900, that is, the first light guide plate 5000d, the second light guide plate 5000f, and the second light guide plate 5000f. 3 light guide plate 5000h, fourth light guide plate 5000h, fifth light guide plate 5000i, and sixth light guide plate 5000k are specified to be turned off without surface emission), and liquid crystal of liquid crystal side effect display unit 1900. Since nothing is displayed in the display area of the panel 5000e, as shown in FIG. 84(g), the rotary light-emitting device 3100 existing behind the liquid crystal side effect display unit 1900, the model 3400 imitating the detonator, and All of the model 3500 imitating dynamite can be visually recognized. At this time, of the objects existing behind the liquid crystal side effect display unit 1900, the rotary light emitting device 3100 is in the rotation lighting mode. Therefore, the red light becomes stronger or weaker through the region RGN (that is, the non-light emitting region 5000k3 formed in the sixth light guide plate 5000k). The strength can be felt extremely large by the player, and the player can operate the detonation button 3400a of the model 3400 imitating the detonator so that the detonator operates, so that the player can turn on the light by rotating the red light. It is also possible to prompt by the production of a mode.

After that, when the player operates the pressing operation unit 405 of the operation unit 400 attached to the center of the upper portion of the dish unit 300 in the door frame 5 shown in FIG. 2 in order to press the detonation button 3400a so that the detonator operates, In conjunction with this (with this as a trigger), when the specific effect execution period has elapsed, or when the specific effect execution period has elapsed without the player operating the pressing operation unit 405, the liquid crystal side effect display unit 1900. Liquid crystal panel of the liquid crystal side effect display unit 1900 corresponding to the light emitting area 5000d4 (that is, the entire surface of the first light guide plate 5000d) formed in the first light guide plate 5000d. An image (screen) by another effect is displayed in the display area of 5000e, and the effect proceeds. Then, again, the decorative symbols 1950a to 1950c are displayed in the lower right corner after the display area of the liquid crystal side effect display unit 1900, and while moving from the lower right corner to the original position at the time of start of variation, the entire pattern is displayed. The shape is enlarged to the original size, the variable display of the decorative symbols 1950a to 1950c is stopped, and the player can recognize the first special lottery result or the second special lottery result. ..

In this way, the first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000g, the fourth light guide plate 5000h, and the fifth light guide plate 5000d of the liquid crystal side effect display unit 1900 according to the progress of the specific effect. Display of the liquid crystal panel 5000e of the liquid crystal side effect display unit 1900 corresponding to the surface emission by one of the plurality of light guide plates by causing the light guide plate 5000i and the sixth light guide plate 5000k to sequentially emit surface light. Since an image (screen) is drawn (displayed) in the area, even though the liquid crystal panel 5000e has a rectangular shape, a liquid crystal panel 5000e having another physical shape is displayed. As a completely different entity, a display section on which an image (screen) is drawn (displayed) appears. It is possible to provide the player with such a novel effect based on the specific effect.

According to the pachinko gaming machine 1 of the present embodiment described above, an effect can be performed based on the progress of the game, and the VDP 4160a with a built-in sound source is directly controlled among the decorative substrates of the door frame 5 of FIG. 2 as a control target. A plurality of LEDs (decorative LEDs) provided on each of the plurality of frame-side VDP control target decoration substrates that are control targets, liquid crystal in the peripheral control substrate 4140 of FIG. 17 and liquid crystal of the sound control unit 4160 as information storage means. A sound control ROM 4160b, a liquid crystal and sound control unit 4160 of the peripheral control board 4140 of FIG. 19 as an image object creating means, a sound source built-in VDP 4160a, a channel CH2 of the sound source built-in VDP 4160a of FIG. A positive phase side ferrite bead as a positive phase side inductance element, a negative phase side ferrite bead as a negative phase side inductance element, a transmitter IC 4160d of peripheral control board 4140 of FIG. 19 as a signal converting means, and a frame decoration drive amplifier of FIG. 19 as a signal restoring means. The receiver IC 194f of the board 194, the frame side signal separation control circuit 194g of the frame decoration drive amplifier board 194 of FIG. 19 as the extraction means, and the frame side VDP control target decoration LED control of the frame decoration drive amplifier board 194 of FIG. 42 as the drive control means. The frame-side VDP control target first decoration LED control circuit 194i1 to the frame-side VDP control target first 143 decoration LED control circuit 194i143 in the circuit 194i is provided.

The liquid crystal and sound control ROM 4160b can store a plurality of types of information regarding effects. Specifically, the liquid crystal and sound control ROM 4160b is game board side character data for drawing in the display area of the game board side effect display unit 1900, and the above-described predetermined screen (red (R) in this embodiment). : 50%, gray (G): 50%, blue (B): gray screen with 50%), and of the decorative boards of the game board 4, VDP4160a with a built-in sound source directly controls Game board side light emission mode setting image data for setting the light emission mode of a plurality of LEDs (decorative LEDs) provided on each of the plurality of game board side VDP control target decorative substrates to be controlled, and a door frame In order to set the light emission mode of the plurality of LEDs (decorative LEDs) provided on each of the plurality of frame-side VDP control target decoration boards that are directly controlled by the sound source built-in VDP4160a The door frame side light emitting mode setting image data and various sound data such as music, sound effects, notification sounds, and notification sounds are stored in advance.

Based on the information read from the liquid crystal and the sound control ROM 4160b, the sound source built-in VDP 4160a includes electric decoration information as an image as control information for a plurality of LEDs (decorative LEDs) mounted on various decorative substrates of the door frame 5. It is possible to create a frame side image object.

Specifically, first, as described above, the peripheral control MPU 4150a uses the screen generation schedule data in time series according to the screen generation schedule data and the light emission mode generation schedule data set in the schedule data storage area 4150cae. Each time the V blank signal is input, the screen data arranged in the above and the light emission data arranged in time series in the light emission mode generation schedule data are input one by one from the first screen data and from the first light emission data. Output to the VDP4160a with a built-in sound source one by one.

The screen generation schedule data is configured by arranging the screen data defining the screen configuration in time series, and the screen generation schedule data for the game board side effect display unit 1900 (liquid crystal panel 5000e) and the plate side. There is screen generation schedule data for the liquid crystal display device 470, and the order of screens to be drawn (displayed) is defined. The light emission mode generation schedule data is configured such that light emission data defining the light emission mode is arranged in time series, and the light emission mode generation schedule data for the plurality of LEDs provided on each decorative board of the game board 4 and the door. There is a light emitting mode generation schedule data for a plurality of LEDs provided on each decorative substrate of the frame 5, and the order of the light emitting modes is defined respectively.

The sound source built-in VDP 4160a is a screen that defines the configuration of a predetermined screen (a gray screen having red (R): 50%, green (G): 50%, and blue (B): 50% in this embodiment). Data and light emission of a plurality of LEDs (decorative LEDs) provided on each of the plurality of frame-side VDP control target decorative substrates that are directly controlled by the sound source built-in VDP 4160a among the decorative substrates of the door frame 5. When the light emission data defining the mode is input from the peripheral control MPU 4150a, a predetermined screen (book) is displayed from the liquid crystal and sound control ROM 4160b based on the input screen data according to a predetermined door frame side generation rule. In the embodiment, sprite data is created by extracting dummy data for drawing a gray screen having red (R): 50%, green (G): 50%, and blue (B): 50%. The door frame side drawing data is generated in the door frame side drawing data area VRGN2a of the door frame side display area VRGN2 provided on the built-in VRAM, and the door is controlled from the liquid crystal and sound control ROM 4160b based on the input light emission data. Of the decorative boards of the frame 5, the light emission mode of a plurality of LEDs (decorative LEDs) provided on each of the plurality of frame-side VDP control target decorative boards that are directly controlled by the sound source built-in VDP 4160a is set. The door frame side light emission mode setting image data is extracted and the electric decoration information is generated as drawing data in the door frame side accompanying information area VRGN2b of the door frame side display area VRGN2 provided on the built-in VRAM.

The channel CH2 of the VDP 4160a with a built-in sound source in FIG. 19 can output a parallel signal including a frame-side image object created by the VDP 4160a with a built-in sound source.

Specifically, the channel CH2 of the VDP 4160a with a built-in sound source uses a parallel interface. The drawing data output from the channel CH2 is composed of three video signals of a red video signal, a green video signal, and a blue video signal, and three sync signals of a horizontal sync signal, a vertical sync signal, and a clock signal. ing. The sound source built-in VDP 4160a includes, as a frame-side image object created by itself, door-frame-side drawing data generated in a door-frame-side drawing data region VRGN2a of a door-frame-side display region VRGN2 provided in the built-in VRAM, and a built-in Drawing data including the door frame side associated information area VRGN2b of the door frame side display area VRGN2 provided on the VRAM and the drawing data including parallel lighting signals are used as parallel signals for a red video signal, a green video signal, and a blue video signal. And a horizontal synchronizing signal, a vertical synchronizing signal, and a clock signal.

The transmitter IC 4160d of the peripheral control board 4140 converts the parallel signal output from the channel CH2 of the VDP 4160a with a built-in sound source into a signal of the clockless transmission system as a serial signal composed of a positive phase signal and a negative phase signal. It can be output.

Specifically, the transmitter IC 4160d has three video signals, that is, a red video signal, a green video signal, and a blue video signal, which are parallel signals output from the channel CH2 of the VDP 4160a with a built-in sound source, a horizontal synchronization signal, and a vertical synchronization signal. , And a clock signal, and three synchronous signals are serialized into a differential serial signal (serial data) called "V-by-One (registered trademark)" of THine Electronics Co., Ltd., which is a kind of clockless transmission system. (In other words, a parallel signal composed of three video signals of a red video signal, a green video signal, and a blue video signal, and three sync signals of a horizontal sync signal, a vertical sync signal, and a clock signal is multiplexed. In addition, serialize the serial signal (serial data) of the differential system) and control these various signals only with a differential 1 pair cable that makes one wiring the positive phase and the other wiring the opposite phase. The signal is output (transmitted) from the board 4140 to the frame peripheral relay terminal plate 868, the peripheral door relay terminal plate 882, and the frame decoration drive amplifier 194.

A twisted pair cable, which is a differential 1-pair cable, is configured by twisting wiring that transmits a positive-phase signal and wiring that transmits a negative-phase signal. Specifically, one wiring of the twisted pair cable is configured as a wiring for transmitting a positive phase signal, and the other wiring of the twisted pair cable is configured as a wiring for transmitting a reverse phase signal.

A positive-phase signal transmitted via a twisted pair cable is input to the positive-phase ferrite beads. The opposite-phase side ferrite beads are inputted with the opposite-phase signal transmitted via the twisted pair cable. Specifically, the frame decoration drive amplifier substrate 194 is provided with the positive phase side ferrite beads and the negative phase side ferrite beads. A serial signal (serial data) by a differential method called "V-by-One (registered trademark)" of THine Electronics Co., Ltd., which is a kind of clockless transmission method, is transmitted from the transmitter IC 4160d in the peripheral control board 4140 as a plus signal and a minus signal. Then, the plus signal is immediately before the RXIN+ terminal of the receiver IC 194f via a common mode choke coil (not shown) provided on the frame decoration drive amplifier substrate 194 or directly without a common mode choke coil (not shown). The circuit is configured so that it is input to the RXIN+ terminal via the provided positive-phase side ferrite beads, and the negative signal is input to the RXIN- terminal via the negative-phase side ferrite beads provided immediately before the RXIN- terminal of the receiver IC 194f. The circuit is configured to be input.

The positive-phase side ferrite beads and the negative-phase side ferrite beads reflect the noise that the inductor (coil) component of the ferrite bead penetrates into the twisted wire and prevent it from passing through, and the resistance component of the ferrite bead penetrates the twisted wire. Has the characteristic that it can be converted into heat and removed. Due to such characteristics of the ferrite beads, it is possible to suppress the disturbance of the waveform due to the superposition of noise on the serial signal transmitted through the twisted wire and arrange the waveform into a beautiful waveform.

The receiver IC 194f of the frame decoration drive amplifier board 194 outputs a serial signal composed of a positive-phase signal input via the positive-phase side ferrite beads and a negative-phase signal input via the negative-phase side ferrite beads. It can be restored to a parallel signal and output.

Specifically, when the serial signal (serial data) from the peripheral control board 4140 is input to the frame decoration drive amplifier board 194 via the twisted pair cable, the plus signal of the serial signal is provided immediately before the RXIN+ terminal of the receiver IC 194f. In addition to being input to the RXIN+ terminal via the positive-phase side ferrite beads, the negative signal of the serial signal is input to the RXIN- terminal via the negative-phase side ferrite beads provided immediately before the RXIN- terminal of the receiver IC 194f. When the receiver IC 194f receives the serial signal (serial data), the serialized various signals are parallel signals (that is, the red video signal, the green video signal, which are the drawing data output from the channel CH2 of the VDP 4160a with a built-in sound source, and the green video signal, and To the frame side signal separation control circuit 194g.

The frame side signal separation control circuit 194g can extract and output the electric decoration information as the control information from the frame side image object created by the sound source built-in VDP 4160a based on the restored parallel signal output by the receiver IC 194f. Is.

Specifically, the frame-side signal separation control circuit 194g uses the parallel signal restored by the receiver IC 194f to determine the above-described predetermined screen (in the present embodiment, red (R): 50%, green (G): 50). %, blue (B): gray screen having 50%) door frame side drawing data, which are three video signals of a red video signal, a green video signal, and a blue video signal, a horizontal synchronization signal, and a vertical synchronization signal. , And clock signals, and a plurality of decorative boards of the door frame 5 provided on each of the frame-side VDP controlled decorative boards that are directly controlled by the sound source built-in VDP 4160a. It is separated into electrical decoration information for the LED (decorative LED).

42. Frame-side VDP control target decoration LED control circuit 194i of the frame-decoration drive amplifier board 194 of FIG. 42: frame-side VDP control target first decoration LED control circuit 194i1 to frame-side VDP control target 143 decoration LED control circuit 194i143 is a plurality of frames to be controlled by the sound source built-in VDP 4160a, which are directly controlled by the sound source built-in VDP 4160a, based on the electric decoration information as the control information output by the frame side signal separation control circuit 194g. It is possible to control the drive of a plurality of LEDs (decorative LEDs) provided on each of the side VDP control target decorative substrates.

Specifically, the frame side signal separation control circuit 194g, based on the electrical decoration information separated from the parallel signal restored by the receiver IC 194f, the frame side VDP control target decoration LED control circuit 194i in the frame side VDP control target decoration LED control circuit 194i. 1 decoration LED control circuit 194i1 to frame side VDP control target is a control target directly controlled by the sound source built-in VDP 4160a of each decoration board of the door frame 5 via the 143th decoration LED control circuit 194i143. By outputting signals to the plurality of frame-side VDP control target decoration substrates, the plurality of LEDs (decorative LEDs) provided on each of the plurality of frame-side VDP control target decoration substrates emit light. As a result, the frame side VDP control target decoration LED control circuit 194i in the frame side VDP control target decoration LED control circuit 194i1 to the frame side VDP control target 143 decoration LED control circuit 194i143 separates the frame side signal. Based on the electric decoration information as the control information separated by the control circuit 194g, among the decoration boards of the door frame 5, a plurality of frame-side VDP control target decoration boards that are directly controlled by the sound source built-in VDP 4160a are controlled. A plurality of LEDs (ornamental LEDs) provided for each can perform a light emission effect.

That is, among the decoration boards of the door frame 5, the light emission effect by the plurality of LEDs (decorative LEDs) provided on each of the plurality of frame-side VDP control target decoration boards that are directly controlled by the sound source built-in VDP 4160a. Is able to run.

In this way, based on the information read from the liquid crystal and the sound control ROM 4160b, the electric decoration information is included as an image as the control information for the plurality of LEDs (decorative LEDs) mounted on the various decorative substrates of the door frame 5. The frame side image object is created by the VDP4160a with a built-in sound source, the parallel signal including the created frame side image object is output from the channel CH2 of the VDP4160a with a built-in sound source, and the parallel signal is converted from the positive phase signal and the negative phase signal. The transmitter IC 4160d converts the serial signal into a serial signal, and the converted serial signal is a differential 1-pair cable configured by twisting a wire for transmitting a positive-phase signal and a wire for transmitting a negative-phase signal. A positive phase signal is input to the positive phase side ferrite beads and a negative phase signal is input to the negative phase side ferrite beads through a certain twisted pair cable. A serial signal composed of a positive phase signal input via the positive phase side ferrite beads and an opposite phase signal input via the negative phase side ferrite beads is input to the receiver IC 194f. .. That is, in the transmission path from the transmitter IC 4160d to the receiver IC 194f, the serial signal is transmitted via the twisted pair cable and the positive phase side ferrite beads and the negative phase side ferrite beads. The receiver IC 194f restores the input serial signal to a parallel signal again, and based on the restored parallel signal, the frame side signal separation control circuit 194g takes out the electric decoration information from the frame side image object as the control information, and takes out this. Based on the electric decoration information as the control information, among the decoration boards of the door frame 5, a plurality of frame-side VDP control target decoration boards that are control targets directly controlled by the sound source built-in VDP 4160a are provided. The drive control of the LED (decorative LED) is controlled by the frame-side VDP control target decoration LED control circuit 194i. The frame-side VDP control target first decoration LED control circuit 194i1 to the frame-side VDP control target first 143 decoration LED control. The circuit 194i143 is adapted to be able to perform.

The twisted pair cable consists of wiring that transmits positive phase signals and wiring that transmits negative phase signals twisted together, so if noise enters the twisted pair cable, wiring that transmits positive phase signals Then, noise will intrude into the wiring that transmits the signal of the opposite phase. Then, the noise invading the positive phase signal and the noise invading the negative phase signal cancel each other, and the disturbance of the waveform is suppressed through the positive phase side ferrite beads and the negative phase side ferrite beads. By inputting to the receiver IC 194f in a state in which the waveform is adjusted to a beautiful waveform, it is possible to restore the parallel signal again with the noise removed in the receiver IC 194f. Therefore, accurate control can be realized for the controlled object.

[20. Another example]
It is needless to say that the present invention is not limited to the above-described embodiments and can be implemented in various modes as long as they are within the technical scope of the present invention.

For example, in the above-described embodiment, the length of the wiring for sending the drawing data from the liquid crystal/sound control unit 4160 built-in sound source VDP 4160a shown in FIG. 19 is longer than that of the channel CH1 of the sound source built-in VDP 4160a shown in FIG. For the channel CH2 of the VDP 4160a with a built-in sound source that becomes extremely long, it is a kind of clockless transmission method between the transmitter and the receiver in the transmitter IC 4160d of the peripheral control board 4140 and the receiver IC 194f of the frame decoration drive amplifier board 194. Although differential communication called "V-by-One (registered trademark)" of THine Electronics Co., Ltd. is adopted, another IC may be used as long as it is a clockless transmission method. In the above-described embodiment, the transmitter IC 4160d, which is a dedicated IC, is adopted as the transmitter, and the receiver IC 194f, which is a dedicated IC, is adopted as the receiver. A transmission transceiver IC can also be used.

Here, the serial transmission transceiver IC will be briefly described with reference to FIGS. 85 and 86. FIG. 85 is a schematic explanatory diagram of various terminals of the serial transmission transceiver IC, and FIG. 86 is a schematic diagram of a usage example of the serial transmission transceiver IC. The serial transmission transceiver IC 7000 is an IC capable of switching between the tone shifter operation and the receiver operation (transmitter/receiver). As shown in FIG. 85, the TX_XRX terminal serves as a switching terminal, the HS terminal, the VS terminal, and the PCLK serve as input/output terminals. Terminal, R0 terminal, R1 terminal, R2 terminal, R3 terminal, R4 terminal, R5 terminal, R6 terminal, R7 terminal, G0 terminal, G1 terminal, G2 terminal, G3 terminal, G4 terminal, G5 terminal, G6 terminal, G7 terminal, B0 terminal, B1 terminal, B2 terminal, B3 terminal, B4 terminal, B5 terminal, B6 terminal, B7 terminal, DFXTX+ terminal as differential output transmitter plus terminal, DFTX− terminal as differential output transmitter minus terminal, differential receiver plus terminal DFRX+ terminal, differential receiver minus terminal as DFRX- terminal, status output terminal as ERR terminal, power supply terminal as VDD terminal, and ground terminal as GND terminal.

The TX_XRX terminal can be set to transceiver operation when a control voltage (eg, +3.3V) is applied, and can be set to receiver operation when grounded to ground (GND).

The HS terminal can input/output a horizontal synchronizing signal, the VS terminal can input/output a vertical synchronizing signal, and the PCLK terminal can input/output a clock signal.

The R0 terminal, the R1 terminal, the R2 terminal, the R3 terminal, the R4 terminal, the R5 terminal, the R6 terminal, and the R7 terminal can input and output the red video signal, and the G0 terminal, the G1 terminal, the G2 terminal, the G3 terminal, and the G4 terminal. The terminal, the G5 terminal, the G6 terminal, and the G7 terminal can input and output the green video signal, and the B0 terminal, the B1 terminal, the B2 terminal, the B3 terminal, the B4 terminal, the B5 terminal, the B6 terminal, and the B7 terminal, A blue video signal can be input/output.

The DFXTX+ terminal and the DFTX- terminal are a horizontal synchronizing signal input to the HS terminal, a vertical synchronizing signal input to the VS terminal, a clock signal input to the PCLK terminal, an R0 terminal, an R1 terminal, an R2 terminal, Red video signal input to R3 terminal, R4 terminal, R5 terminal, R6 terminal, and R7 terminal, and input to G0 terminal, G1 terminal, G2 terminal, G3 terminal, G4 terminal, G5 terminal, G6 terminal, and G7 terminal Serialized to a clockless transmission method based on the green video signal and the blue video signal input to the B0 terminal, B1 terminal, B2 terminal, B3 terminal, B4 terminal, B5 terminal, B6 terminal, and B7 terminal. The generated signal can be output by a differential method. It should be noted that the DFXTX+ terminal and the DFTX- terminal of the differential transmitter of the serial transmission transceiver IC 7000 have a predetermined terminating resistor (for example, 50 ohm) built therein.

The DFRX+ terminal and the DFRX- terminal can receive a signal output by the differential method and serialized by the clockless transmission method. The serial transmission transceiver IC 7000 uses a built-in clock data recovery (CDR: Clock Data Recovery) function to perform data (parallel data restored to 8-bit from each of the red video signal, the green video signal, and the blue video signal that are serial data). , A clock (horizontal synchronizing signal, vertical synchronizing signal, and clock signal). It should be noted that the DFRX+ terminal and the DFRX- terminal of the differential receiver of the serial transmission transceiver IC 7000 have a predetermined terminating resistor (for example, 50 ohm) built therein.

When the serial transmission transceiver IC 7000 is set to operate as a transceiver, the ERR terminal can output a transmission state and output a transmission normal logic that indicates stable time, while transmitting a transmission abnormal logic that indicates unstable transmission. (Logic obtained by inverting the normal transmission logic) can be output. On the other hand, the ERR terminal can output the reception error check result when the serial transmission transceiver IC 7000 is set to the receiver operation, and can output the reception normal logic for transmitting the reception normality, while It is possible to output a reception abnormality logic (a logic obtained by inverting the reception normal logic) that conveys the reception abnormality.

A control voltage (for example, +3.3V) is applied to the VDD terminal, and the GND terminal is grounded to the ground (GND).

Next, a circuit will be described in which the serial transmission transceiver IC 7000 is set for transmitter operation and provided on the peripheral control board 4140 while the serial transmission transceiver IC 7000 is set for receiver operation and provided on the frame decoration drive amplifier board 194. As shown in FIG. 86, when the serial transmission transceiver IC 7000 is provided on the peripheral control board 4140, the TX_XRX terminal is applied to the control voltage for transmitter operation. The image data output from the channel CH2 of the sound source built-in VDP 4160a is, as described above, three images of a red video signal (8 bit width), a green video signal (8 bit width), and a blue video signal (8 bit width). The horizontal sync signal is input to the HS terminal, the vertical sync signal is input to the VS terminal, and the clock signal is input to the horizontal sync signal. The red video signal (8-bit width) is input to the PCLK terminal, and the red video signal (8-bit width) is input to the R0 terminal, R1 terminal, R2 terminal, R3 terminal, R4 terminal, R5 terminal, R6 terminal, and R7 terminal, respectively. Width) is input to the G0 terminal, G1 terminal, G2 terminal, G3 terminal, G4 terminal, G5 terminal, G6 terminal, and G7 terminal, respectively, and the blue video signal (8-bit width) is input to the B0 terminal, B1 terminal, B2 terminal, It is input to the B3 terminal, the B4 terminal, the B5 terminal, the B6 terminal, and the B7 terminal, respectively.

The DFTX+ terminal and the DFXT- terminal are provided with capacitors (for coupling) TCX1 and TCX2, respectively, and are transmitted to the frame peripheral relay terminal plate 868, the peripheral door relay terminal plate 882, and the frame decoration drive amplifier substrate 194 without clock transmission. The signal serialized by the method is output (transmitted) by the differential method.

The DFRX+ terminal, the DFRX- terminal, and the ERR terminal are electrically unconnected. The VDD terminal is applied with the same control voltage as the TX_XRX terminal, and the GND terminal is grounded to the ground (GND).

On the other hand, when the frame decoration drive amplifier board 194 is provided with the serial transmission transceiver IC 7000, the TX_XRX terminal is grounded for the receiver operation. The serial transmission transceiver IC 7000 provided on the frame decoration drive amplifier board 194 is configured so that serial signals from the DFTX+ terminal and the DFTX- terminal of the serial transmission transceiver IC 7000 provided as a transceiver operation provided on the peripheral control board 4140 are respectively coupled by a capacitor (coupling). (For use) is input (received) to the DFRX+ terminal and the DFRX- terminal via RCX1 and RCX2, and the data (serial video red video signal, green video signal, and blue video signal) is input by the built-in clock data recovery (CDR) function. From the parallel data restored to 8 bits respectively) and a clock (horizontal synchronizing signal, vertical synchronizing signal, and clock signal).

Then, the serial transmission transceiver IC 7000 provided on the frame decoration drive amplifier board 194 outputs the horizontal synchronization signal from the HS terminal to the frame side signal separation control circuit 194g, and outputs the vertical synchronization signal from the VS terminal to the frame side signal separation control circuit 194g. Outputs a clock signal from the PCLK terminal to the frame side signal separation control circuit 194g, and outputs a red image as a parallel signal from the R0 terminal, R1 terminal, R2 terminal, R3 terminal, R4 terminal, R5 terminal, R6 terminal, and R7 terminal. The signal is output to the frame side signal separation control circuit 194g, and the green video signal is controlled as a parallel signal from the G0 terminal, G1 terminal, G2 terminal, G3 terminal, G4 terminal, G5 terminal, G6 terminal, and G7 terminal to the frame side signal separation control. The signal is output to the circuit 194g, and the blue video signal is output as a parallel signal from the G0 terminal, the G1 terminal, the G2 terminal, the G3 terminal, the G4 terminal, the G5 terminal, the G6 terminal, and the G7 terminal to the frame-side signal separation control circuit 194g.

The serial transmission transceiver IC 7000 provided on the frame decoration drive amplifier board 194 transmits the reception error check result to the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 from the ERR terminal to the peripheral door relay terminal board 882, The frame peripheral relay terminal board 868 and the peripheral control board 4140 output normal reception logic or abnormal reception logic. The peripheral control MPU 4150a monitors the normal reception logic or the abnormal reception logic output from the ERR terminal of the serial transmission transceiver IC 7000 provided on the frame decoration drive amplifier board 194, and thereby the peripheral control board 4140, the frame peripheral relay terminal board 868, It is possible to monitor whether or not a defect has occurred in the transmission path extending to the peripheral door relay terminal plate 882 and the frame decoration drive amplifier board 194. If there is a problem, the message "There is a problem with the transmission path to the door frame." is displayed in the display area of the game board effect display unit 1900, and the speaker provided on the door frame 5 is displayed. A control is performed to output a voice from 130, "A problem has occurred in the transmission path to the door frame."

In the serial transmission transceiver IC 7000 provided on the frame decoration drive amplifier board 194, the DFTX+ terminal and the DFRT− terminal are not electrically connected. A control voltage is applied to the VDD terminal, and the GND terminal is grounded to the ground (GND).

In this way, a common IC called the serial transmission transceiver IC 7000 capable of setting the transceiver operation and the receiver operation can be provided on the peripheral control board 4140 side and the frame decoration drive amplifier board 194, respectively. This eliminates the need to purchase separate electronic components for the transceiver and the receiver, thereby making it possible to purchase a common IC, which is twice as many as the case where separate electronic components are used, thus reducing the unit price of the common IC. be able to. Therefore, it is possible to contribute to the reduction of the manufacturing cost of the pachinko gaming machine 1 and the control number of electronic components.

Moreover, in the above-described embodiment, the first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000g, the fourth light guide plate 5000h, and the fifth light guide plate included in the game board side effect display unit 1900. Although a light emitting region and a non-light emitting region are formed by light from the upper end surface and the lower end surface of each light guide plate in the plurality of light guide plates configured by the 5000i and the sixth light guide plate 5000k, respectively. For example, the light from the upper end surface of the light guide plate forms the upper light emitting area and the upper non-light emitting area, while the light from the side end surface of the light guide plate forms the side light emitting area and the side non-light emitting area. Good. In this case, for example, in the second light guide plate 5000f, the light guide plate upper decorative substrate 5000f1 is arranged on the upper end face of the second light guide plate 5000f, and the side end face of the second light guide plate 5000f (for example, when viewed from the front is seen). The light guide plate side decorative substrate 5000f2' is disposed on the right side end surface). The light guide plate decoration substrate 5000f1 is controlled by the LED driver IC 4810 in the first light guide plate control circuit 3420k1, and the light guide plate side decoration substrate 5000f2′ is controlled by the LED driver IC 4810′ in the first light guide plate control circuit 3420k1. It

A large number of reflecting portions on the back surface (back surface) of the second light guide plate 5000 are formed so that the upper light emitting region emits surface light when the light source of the light guide plate upper decorative substrate 5000f1 is turned on, and the light source of the light guide plate upper decorative substrate 5000f2' is turned on. Thus, a large number of reflecting portions on the back surface (back surface) of the second light guide plate 5000 are formed so that the side light emitting regions emit surface light. As a result, the liquid crystal panel 5000e receives the light in the upper light emitting region, which is surface-emitted by the second light guide plate 5000f when the light source of the light guide plate upper decorative substrate 5000f1 is turned on. According to the control mode of the liquid crystal panel 5000e, in the liquid crystal panel 5000e, an image can be easily visually recognized in the inner part of the upper light emitting region, while the light source of the light guide plate side decorative substrate 5000f2' is turned on to The light in the side light emitting area, which is surface-emitted by the light guide plate 5000f, enters the side light emitting area of the liquid crystal panel 5000e according to the control mode of the liquid crystal panel 5000e when viewed from the front. The image can be easily viewed. Further, the size and position of the non-light emitting area and the light emitting area can be changed by changing the angle of the light incident on one light guide plate.

Further, in the above-described embodiment, the game board side effect display unit 1900 has the first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000g, and the fourth light guide plate 5000d as the backlight of the liquid crystal panel 5000e. The light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k are provided in the plurality of light guide plates, but the liquid crystal panel 5000e and the plurality of light guide plates may be replaced to emit light by themselves. A possible organic EL display device may be used. When an organic EL display device is used, both an area displaying an image and an object existing behind the area other than the area displaying the image are visually recognized through the organic EL display device. can do.

Furthermore, in the embodiment described above, in the game board side effect display unit 1900, the first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000g, and the fourth light guide plate 5000d are used as the backlight of the liquid crystal panel 5000e. Control for sequentially switching the plurality of light guide plates configured by the light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k from the first light guide plate 5000d to the sixth light guide plate 5000k. However, for example, the first light guide plate 5000d→the third light guide plate 5000g→the fifth light guide plate 5000i may be switched in order, or the first light guide plate 5000d→the second light guide plate 5000d. The order may be reversed or randomly, such as light plate 5000f→third light guide plate 5000g→second light guide plate 5000f→third light guide plate 5000g→.

In the above-described embodiment, the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board is arranged in time series in the screen generation schedule data according to the screen generation schedule data and the light emission mode generation schedule data. Every time the above-mentioned V blank signal is input, the screen data and the light emission data arranged in time series in the light emission mode generation schedule data are input one by one from the top screen data and one from the first light emission data. Each of them was output to the liquid crystal in the peripheral control board 4140 and the VDP 4160a with the built-in sound source of the sound control unit 4160. As described above, the screen generation schedule data is composed of screen data that defines the screen configuration arranged in time series, and the screen generation schedule data for the game board side effect display unit 1900 (liquid crystal panel 5000e). , And the order of screens to be drawn (displayed) is specified. As described above, the schedule data for light emission mode generation is configured such that the light emission data defining the light emission mode is arranged in time series, and for the light emission mode generation for the plurality of LEDs provided on each decorative board of the game board 4. There are schedule data and schedule data for light emission mode generation for a plurality of LEDs provided on each decorative substrate of the door frame 5, and the order of light emission modes is defined respectively. As described above, a plurality of these schedule data are stored in advance in the peripheral control ROM 4150b of the peripheral control unit 4150 in the peripheral control board. Therefore, the peripheral control MPU 450a is configured to store a plurality of screen generation and emission mode generation schedule data in which the screen generation schedule data and the light emission mode generation schedule data are set as one schedule data in advance in the peripheral control ROM 4150b. According to the screen generation and light emission mode generation schedule data, the screen data and the light emission data arranged in time series in the screen generation and light emission mode generation schedule data are input each time the V blank signal is input. The screen data and the light emission data may be sequentially output to the sound source built-in VDP 4160a one by one.

In the above-described embodiment, the game board side effect display unit 1900 has the first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000g, and the fourth light guide plate 5000d as the backlight of the liquid crystal panel 5000e. Although the non-light-emitting regions of the plurality of light guide plates configured by the light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k are formed in a circular shape or a polygonal shape, The relationship with the shape of the non-light emitting area is appropriately determined depending on the world view of the effect that the developer of the pachinko gaming machine 1 desires to realize.

Further, in the above-described embodiment, the drawing data output from the channel CH1 of the liquid crystal in the peripheral control board 4140 and the VDP 4160a with the built-in sound source of the sound control unit 4160 includes the clock signal differential 1 pair cable and the TA signal differential 1 pair. The signal is transmitted to the liquid crystal output substrate 3420 via the cable, the differential 1 pair cable for the TB signal, the differential 1 pair cable for the TC signal, and the differential 1 pair cable for the TD signal, and the RGB conversion circuit 3420f of the liquid crystal output substrate 3420f. In the above, the signal is converted into the parallel signal based on the signal transmitted by the LVDS system (that is, the clock signal, the TA signal, the TB signal, the TC signal, and the TD signal). Therefore, a clock signal differential 1-pair cable, a TA signal differential 1-pair cable, a TB signal differential 1-pair cable, and a TC signal differential are provided between the peripheral control board 4140 and the liquid crystal output board 3420. By electrically connecting with a plurality of pair cables, that is, a 1-pair cable and a differential 1-pair cable for TD signals, it may be difficult to route the cables because the number of cables increases. In some cases, a large dedicated space is provided on the back side of the game board 4 for drawing around. Therefore, between the peripheral control board 4140 and the liquid crystal output board 3420, three video signals of a red video signal, a green video signal, and a blue video signal, and three video signals of a horizontal synchronization signal, a vertical synchronization signal, and a clock signal are provided. Synchronous signal and serial signal (serial data) of the differential system called the clockless transmission system described above is serialized, and only one pair of differential cables in which one wiring has a positive phase and the other wiring has a negative phase May be configured to transmit these various signals.

In this case, the RGB conversion circuit 3420f of the liquid crystal output board 3420 shown in FIG. 20 is provided in the peripheral control board 4140 so that the drawing data transmitted by the LVDS method from the channel CH1 of the VDP 4160a with a built-in sound source can be read by the RGB conversion circuit. , A red video signal, a green video signal, and a blue video signal, and a horizontal signal, a horizontal sync signal, a vertical sync signal, and a clock signal. The peripheral control board 4140 is provided with a transmitter for serializing the converted parallel signal into a serial signal (serial data) of a differential system called a clockless transmission system. Then, various serialized signals are parallel signals (that is, three video signals of a red video signal, a green video signal, and a blue video signal, and three sync signals of a horizontal synchronization signal, a vertical synchronization signal, and a clock signal). ,) is provided on the liquid crystal output substrate 3420. The parallel signal restored by this receiver is input to the game board side signal separation control circuit 3420g. In this manner, between the peripheral control board 4140 and the liquid crystal output board 3420, that is, the transmitter and the receiver are provided with only one differential pair cable, and three video signals of a red video signal, a green video signal, and a blue video signal are provided. , 3 horizontal synchronizing signals, a vertical synchronizing signal, and a clock signal can be transmitted, so that it is possible to reduce the number of cables, so that the cables can be routed very easily and the cables can be routed. Therefore, it is not necessary to provide a large dedicated space on the back side of the game board 4.

The RGB conversion circuit 3420f of the liquid crystal output board 3420 is provided in the peripheral control board 4140, so that the drawing data transmitted by the LVDS system from the channel CH1 of the VDP 4160a with a built-in sound source is converted into a red video signal and a green color by the RGB conversion circuit. A differential signal called a clockless transmission method is converted into a parallel signal composed of three video signals, a video signal and a blue video signal, and three sync signals, a horizontal sync signal, a vertical sync signal, and a clock signal. When the peripheral control board 4140 is provided with a transmitter for serializing a serial signal (serial data), drawing data from the channels CH1 and CH2 of the VDP 4160a with a built-in sound source is transmitted to a board outside the peripheral control board 4140 via the transmitter. Since it is transmitted, the drawing data from the channel CH1 is transmitted to the liquid crystal output substrate 3420, and the drawing data from the channel CH2 is transmitted via the frame peripheral relay terminal plate 868 and the peripheral door relay terminal plate 882. The drawing data from the channel CH1 may be transmitted to the substrate 194, and the drawing data from the channel CH1 may be transmitted to the frame decoration drive amplifier substrate 194 via the frame peripheral relay terminal plate 868 and the peripheral door relay terminal plate 882. The drawing data from the channel CH2 may be transmitted to the liquid crystal output substrate 3420.

Furthermore, in the above-described embodiment, the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 receives game board side motor drive data from the motor drive board serial I/O port via the peripheral control output circuit. By transmitting to the motor drive board 4180, control is performed to output a drive signal to an electric drive source such as a motor or a solenoid that operates various movable bodies provided on the game board 4. In other words, the peripheral control MPU 4150a is a control that outputs a drive signal to an electric drive source such as a motor or a solenoid that operates various movable bodies provided in the game board 4 by directly transmitting the game board side motor drive data. Was going on. Therefore, the control target of the electric drive source on the game board 4 side may be separated from the control by the peripheral control MPU 4150a and controlled by the sound source VDP 4160a.

For example, as described above, the eleventh serial controller 3420gd11 in the game board side signal separation control circuit 3420g shown in FIG. 25 decoration LED control circuit 3420i25, game board side VDP control target 26th decoration LED control circuit 3420i26, game board side VDP control target Output to 27th decoration LED control circuit 3420i27, game board side VDP control target 25th decoration LED control circuit 3420i25, game board side VDP control target 26th decoration LED control circuit 3420i26, game board side VDP control target 27th decoration LED control circuit 3420i27 is one serial connection (one The circuit configuration was electrically connected as a serial system).

Therefore, here, the game board side VDP control target 25th decoration LED control circuit 3420i25, the game board side VDP control target 26th decoration LED control circuit 3420i26, the game board side VDP control target 27th decoration LED control The circuit 3420i27 and the output control circuit 3420it1 capable of setting its own ID are provided on the liquid crystal output substrate 3420 to be electrically connected as one serial connection (one serial system). The ID of the output control circuit 3420it1 is different from the IDs respectively set in the game board side VDP control target 25th decorative LED control circuit 3420i25 to the game board side VDP control target 27th decorative LED control circuit 3420i27. Is set.

Then, the eleventh serial controller 3420gd11 in the game board side signal separation control circuit 3420g uses the electric decoration information as serial data SDAT11 based on the clock signal SCLK11, and the game board side VDP control target 25th decoration LED control circuit 3420i25, the game. It outputs to the board side VDP control target 26th decoration LED control circuit 3420i26, the game board side VDP control target 27th decoration LED control circuit 3420i27, and the output control circuit 3420it1. As described above, the electric decoration information is information for specifying the light emission mode and is composed of the electric decoration LED specifying information and the gradation information. The electric control information corresponds to the output control circuit 3420it1. Source drive is added. The electric drive source drive is information for specifying the drive mode of the electric drive source on the game board 4 side, and is composed of output control specification information and output information. The output control designation information is information that designates the output control circuit 3420it1 and is set with the above-mentioned ID. The output information is information for driving and controlling the electric drive source on the game board 4 side.

The output control circuit 3420it1 will be briefly described. The output control circuit 3420it1 includes an address setting unit, a logic processing unit, a shift register, and an output port. The address setting unit can set the ID according to the magnitude of the voltage applied to the plurality of address setting terminals. The logic processing unit receives the serial data SDAT11 from the eleventh serial controller 3420gd11 in the game board side signal separation control circuit 3420g based on the clock signal SCLK11, and based on the address which is its own ID set by the address setting unit, When the output control designation information in the serial data SDAT11 includes its own ID, it is determined that the serial data SDAT11 is for itself, and the output information in the serial data SDAT11 is fetched by the shift register and restored to parallel data. While controlling the writing to the output port, when the output control designation information in the serial data SDAT11 does not include its own ID, it is determined that the serial data SDAT11 is not for itself, and the output information in the serial data SDAT11 is stored in the shift register. Control is performed to maintain the previously written content (current content) without capturing (or restoring to parallel data and writing to the output port even if captured).

The output port is capable of outputting a parallel signal according to the parallel data written by the logic processing unit. A motor drive board 4180, which is a separate board from the liquid crystal output board 3420, is shown in a drive source drive circuit 4180a capable of outputting a drive signal to a motor (electric drive source) for operating various movable bodies provided on the game board 4. Not provided with a motor drive circuit, and a solenoid drive circuit (not shown) in the drive source drive circuit 4180a that can output a drive signal to a solenoid (electric drive source) that operates various movable bodies provided on the game board 4 The parallel signal from the output port of the output control circuit 3420it1 included in the liquid crystal output substrate 3420 is used as a control signal via a non-illustrated electrical wiring, the motor drive circuit of the drive source drive circuit 4180a included in the motor drive substrate 4180, and the solenoid. It is input to the drive circuit. The motor drive circuit is a motor that operates various movable bodies provided on the game board 4 according to the logic of the parallel signal (control signal) from the output port (for example, the button portion 3400a that imitates the detonation button shown in FIG. 8 or It is possible to output a drive signal to a motor (electric drive source) that operates the model 3500 imitating dynamite), and the solenoid drive circuit is operated according to the logic of the parallel signal (control signal) from the output port. A drive signal to a solenoid (for example, a solenoid (electric drive source) that operates the button portion 3400a that imitates the detonation button shown in FIG. 8 or the model 3500 that imitates dynamite) that operates various movable bodies provided on the board 4. Can be output. Thus, the output control circuit 3420it1, the motor drive circuit of the drive source drive circuit 4180a, and the solenoid drive circuit form a game board side drive control circuit. With this game board side drive control circuit, it is not necessary to provide the motor drive board side transmission data storage area 4150cag shown in FIG. 18 in which the game board side motor drive data is set in the peripheral control RAM 4150c, and the backup management target described above is provided. It is also possible to contribute to reduction of the processing load of the peripheral control MPU 4150a.

A motor drive circuit (not shown) in a drive source drive circuit 4180a capable of outputting a drive signal to a motor (electric drive source) for operating various movable bodies provided on the game board 4, and various movable bodies provided on the game board 4 An enable signal input circuit is provided for a solenoid drive circuit (not shown) in the drive source drive circuit 4180a capable of outputting a drive signal to a solenoid (electric drive source) for activating the control signal from the peripheral control MPU 4150a. The transmission path is formed so that the enable signal is input. Specifically, the enable signal for the motor is transmitted from the parallel I/O port of the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 to the motor drive circuit (not shown) of the motor drive board 4180 via the peripheral control output circuit (not shown). It is input to the enable signal input circuit. Further, a solenoid enable signal is input from a parallel I/O port of the peripheral control MPU 4150a of the peripheral control unit 4150 of the peripheral control board 4140 via a peripheral control output circuit (not shown) to an enable signal of a solenoid drive circuit (not shown) of the motor drive board 4180. Input to the circuit.

A motor drive circuit (not shown) operates various movable bodies provided on the game board 4 according to the logic of the parallel signal (control signal) from the output port based on the logic of the motor enable signal from the peripheral control MPU 4150a. Output of a drive signal to a motor (for example, a motor (electric drive source) that operates the button portion 3400a imitating the detonation button and the model 3500 imitating dynamite shown in FIG. 8) is permitted or not permitted ( Prohibited). The motor enable signal is a first motor enable signal for a motor (electric drive source) that operates the button portion 3400a that imitates a detonation button, and a motor (electric drive source) that operates the model 3500 that imitates dynamite. To the second motor enable signal. Here, the logic of the motor enable signal from the peripheral control MPU 4150a will be briefly described. When the logic of the motor enable signal from the peripheral control MPU 4150a is set to the operation permission logic (valid logic), the electric drive source is set. As a drive permission state for permitting the drive of the control signal, the peripheral control MPU 4150a permits the output of the drive signal to the electric drive source according to the logic of the parallel signal (control signal) from the output port described above by the motor drive circuit (not shown). On the other hand, when the logic of the motor enable signal from the peripheral control MPU 4150a is set to the operation disapproval logic (invalid logic (logic that is the operation enable logic (valid logic) inverted)), the electric drive source As a drive prohibition state in which the drive is prohibited, the peripheral control MPU 4150a prohibits the output of the drive signal to the electric drive source according to the logic of the parallel signal (control signal) from the output port described above by the motor drive circuit (not shown). State.

A solenoid drive circuit (not shown) operates various movable bodies provided on the game board 4 in accordance with the logic of the parallel signal (control signal) from the output port based on the logic of the enable signal for solenoid from the peripheral control MPU 4150a. Allowing or disallowing the output of a drive signal to a solenoid (for example, a solenoid (electric drive source) that operates the button portion 3400a imitating the detonation button or the model 3500 imitating dynamite shown in FIG. 8). Prohibited). The solenoid enable signal is the first solenoid enable signal for the solenoid (electric drive source) that operates the button portion 3400a that imitates the detonation button, and the solenoid (electric drive source) that operates the model 3500 that imitates dynamite. To the second solenoid enable signal. Here, the logic of the solenoid enable signal from the peripheral control MPU 4150a will be briefly described. When the logic of the solenoid enable signal from the peripheral control MPU 4150a is set to the operation permission logic (effective logic), the electric drive source As a drive permission state for permitting the drive of the above, the peripheral control MPU 4150a permits the output of the drive signal to the electric drive source according to the logic of the parallel signal (control signal) from the output port described above by the solenoid drive circuit (not shown). On the other hand, when the logic of the solenoid enable signal from the peripheral control MPU 4150a is set to the operation disapproval logic (invalid logic (logic that is the inversion of the operation permission logic (valid logic))) of the electric drive source As a drive prohibition state in which the drive is prohibited, the peripheral control MPU 4150a prohibits the solenoid drive circuit (not shown) from outputting the drive signal to the electric drive source according to the logic of the parallel signal (control signal) from the output port described above. State.

The peripheral control MPU 4150a sets the logic of the enable signal for the motor and the enable signal for the solenoid, respectively, to permit the output of the drive signal of the electric drive source to operate the motor or the solenoid, or to drive the electric drive source. It is possible to prohibit the output of signals and stop the operation of the motor or solenoid. Thereby, for example, when the behavior of activating the button portion 3400a imitating the detonation button or the model 3500 imitating dynamite is given, the peripheral control MPU 4150a determines whether or not the special symbol is a winning/losing start of the special symbol described above. From within the special symbol 1 fluctuation period from the time to the fluctuation stop is performed at predetermined intervals (for example, 3 seconds) or at random, and when the judgment result is winning, the logic of the enable signal for the motor and the enable signal for the solenoid is activated. On the other hand, the logic of the enable signal for the motor and the enable signal for the solenoid is set to the operation non-permission logic (invalid logic) when the judgment result is unsuccessful while the logic is set to the permission logic (valid logic). As a result, the button portion 3400a imitating the detonation button and the model 3500 imitating the dynamite are activated, stopped, reactivated, and so on, imitating the button portion 3400a imitating the detonation button and the dynamite. An effect of intermittently operating the model 3500 can be created in real time. In this way, the peripheral control MPU 4150a independently sets the logic of the enable signal for the motor and the enable signal for the solenoid, so that the variation of the effect by the button part 3400a imitating the detonation button or the model 3500 imitating the dynamite is realized in real time. Can be increased with. Therefore, it is possible to suppress a decrease in interest.

Note that, for example, the game board side VDP control target 22nd decoration LED control circuit 3420i22 to the game board side VDP control target 26th decoration LED control circuit 3420i26 is a model 3500 that imitates a button portion 3400a or a dynamite that imitates a detonation button. When a plurality of LEDs (hereinafter referred to as "buttons 3400a and decorative LEDs of model 3500") are driven (emits light) as decorative LEDs provided on each decorative substrate provided in the game board side VDP control target 22nd decoration LED control circuit 3420i22 to game board side VDP control target 26th decoration LED control circuit 3420i26 is provided with an enable signal input circuit, respectively, and game board side VDP control target from peripheral control MPU 4150a A transmission path may be formed so that each of the 22 decoration LED control circuit enable signal to the game board side VDP control target 26th decoration LED control circuit enable signal is input. Specifically, from the parallel I/O port of the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140, via the peripheral control output circuit (not shown), the game board side VDP control target 22nd decoration LED control circuit enable Signal ~ game board side VDP control target 26th decoration LED control circuit enable signal corresponds to the liquid crystal output circuit 3420 game board side VDP control target 22nd decoration LED control circuit 3420i22 ~ game board side VDP control target 26 of the decorative LED control circuits 3420i26.

The game board side VDP control target 22nd decoration LED control circuit enable signal to the game board side VDP control target 26th decoration LED control circuit enable signal is a light emission permission logic (valid logic) and a light emission non-permission logic ( One of the invalid logic (the logic obtained by inverting the light emission enable logic (valid logic)) is set, and the light emission enable logic (valid logic) is set to the motor enable signal and the solenoid enable signal described above. Is the same as the operation permission logic (valid logic), and the light emission non-permission logic (invalid logic) is the same as the operation non-permission logic (invalid logic) set in the motor enable signal and solenoid enable signal described above. It is logic. When the logic of the game board side VDP control target 22nd decoration LED control circuit enable signal to the game board side VDP control target 26th decoration LED control circuit enable signal is set to the light emission enable logic (valid logic) , The peripheral control MPU4150a, as a drive permission state (light emission permission state) for permitting driving (light emission) of the decorative LED of the button portion 3400a and the model 3500, the game board side VDP control target 22nd decorative LED control circuit 3420i22- While the game board side VDP control target 26th decorative LED control circuit 3420i26 allows the adjustment of the brightness (gradation) of the decorative LED of the button portion 3400a and the model 3500 based on the above-mentioned electric decoration information, the game is played. Board side VDP control target 22nd decoration LED control circuit enable signal to game board side VDP control target 26th decoration LED control circuit enable signal logic is a non-emission logic (invalid logic (emission enable logic (valid (Logic) which is the reverse of logic)) is set, the peripheral control MPU4150a is set to the game board side as a drive prohibited state (light emission prohibited state) that prohibits driving (light emission) of the decorative LED of the button portion 3400a and the model 3500. VDP control target 22nd decorative LED control circuit 3420i22 to game board side VDP control target 26th decorative LED control circuit 3420i26 is a decorative LED of the decorative LED of the button portion 3400a or model 3500 based on the above-mentioned electrical decoration information. The adjustment of the luminance (gradation) is prohibited. As a result, the button portion 3400a imitating the detonation button and the model 3500 imitating the dynamite are activated, stopped, reactivated, and so on, imitating the button portion 3400a imitating the detonation button and the dynamite. Since the button portion 3400a and the decorative LED of the model 3500 can be driven (emits light) when the model 3500 that has been operated is intermittently operated, the operation of the button portion 3400a that imitates a detonation button and the model 3500 that imitates dynamite can be performed. It is possible to provide a player with a sense of unity by interlocking (synchronizing) with the light emitting modes of the button portion 3400a and the decorative LED of the model 3500.

In the process of performing the winning/loss determination (hereinafter, referred to as “game board side movable effect implementation winning/loss determination process”), the effect control program, for example, the peripheral control of the peripheral control unit power-on process shown in FIG. 68. In the received command analysis processing of step S1022 in the routine regular processing, various commands stored in the received command storage area 4150cac are analyzed, and the analyzed commands operate the button section 3400a imitating the detonation button and the model 3500 imitating dynamite. When the behavior to be performed is given, the winning determination is performed at every predetermined interval (for example, 3 seconds) described above or at random. Then, the enable signal for the motor, the enable signal for the solenoid, the enable signal for the VDP control on the game board side, which is based on the determination result by the game board side movable effect execution hit/miss determination process, the enable signal for the 22nd LED control circuit for decoration to the VDP control object on the game board side. The logic setting and output of the 26th decorative LED control circuit enable signal is performed by newly providing the enable signal logic setting and output processing in the above-described peripheral control unit steady processing (this enable signal logic setting and output processing is , And may be provided as one process of the peripheral controller 1 ms timer interrupt process shown in FIG. 70). When the special symbol 1 changing period ends (when the special figure 1 tuning effect ending command and the special figure 2 tuning effect ending command are received), the logic of the enable signal for the motor and the enable signal for the solenoid is the initial value (that is, The operation enable logic and the light emission enable logic (valid logic) are set, and the motor enable signal, the solenoid enable signal, the game board side VDP control target, the 22nd decoration LED control circuit enable signal to the game board side VDP control target The 26th decorative LED control circuit enable signal is output in the enable signal logic setting and output processing. Note that the determination result by the game board-side movable effect execution win/loss determination process may be configured to be retained and updated as the backup target information, for example, by providing a dedicated area in Bank0 (1fr) in the backup management target work area 4150ca. Good. Further, the logic of the enable signal for the motor, the enable signal for the solenoid, the enable signal for the game board side VDP control target 22nd decoration LED control circuit to the enable for the game board side VDP control target 26th decoration LED control circuit is When the power is turned on, the operation permission logic and the light emission permission logic (valid logic) are set as initial values. At the time of power recovery when a power failure or momentary power failure occurred during the hall's business and power was restored, the motor enable signal, solenoid enable signal, game board side VDP control target 22nd decorative LED control circuit enable signal ~ The logic of the enable signal for the gaming board side VDP control target 26th decorative LED control circuit may be set to an initial value (that is, an operation permission logic, a light emission permission logic (valid logic)). , The operation permission logic, the light emission permission logic (valid logic) or the operation non-permission logic, and the light emission non-permission logic (invalid logic) are set based on the dedicated area provided in the backup management target work area 4150ca. Good. Further, the enable signal for the motor, the enable signal for the solenoid, the enable signal for the LED control circuit for the game board side VDP control target for the 22nd decoration to the 26th decorative LED control circuit for the game board side VDP control target are respectively Although they are configured as individual signals, they may be configured to be used as one common enable signal. By doing so, it is possible to contribute to the reduction of the processing load of the peripheral control MPU 4150a by reducing the number of signals for setting the logic, and to contribute to the cost reduction by reducing the number of wirings.

In the above-described embodiment, the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 receives the door side motor drive data from the frame decoration drive amplifier board motor serial I/O port, the peripheral control output circuit, and the frame. By transmitting to the frame decoration drive amplifier board 194 via the peripheral relay terminal plate 868 and the peripheral door relay terminal plate 882, the dial operation portion 401 of the operation unit 400 in the door frame 5 is rotated or a click feeling is given. The control is performed to output a drive signal to the dial drive motor 414 (electric drive source) that can give various behaviors such as vibration, vibration, and the like. In other words, the peripheral control MPU 4150a performs control to output a drive signal to the dial drive motor 414 (electric drive source) by directly transmitting door side motor drive data. Therefore, the control target of the electric drive source on the door frame 5 side may be separated from the control by the peripheral control MPU 4150a and controlled by the sound source VDP 4160a.

For example, as described above, the eleventh serial controller 194gd11 in the frame-side signal separation control circuit 194g shown in FIG. 40 uses the decoration information as the serial data SDAT11′ based on the clock signal SCLK11′ to determine the frame-side VDP control target first. 131 decoration LED control circuit 194i131 to frame side VDP control target 143 outputs to the decoration LED control circuit 194i143 and frame side VDP control target 131st decoration LED control circuit 194i131 to frame side VDP control target 143th The decorative LED control circuit 194i143 has a circuit configuration electrically connected as one serial connection (one serial system).

Therefore, here, the decoration LED control circuit 194i131 for the frame-side VDP control target 131, the decoration LED control circuit 194i131 for the frame-side VDP control target 131,..., The decoration LED for the frame-side VDP control target 143 The control circuit 194i143 and the output control circuit 194it1 capable of setting its own ID are provided on the frame decoration drive amplifier substrate 194 to be electrically connected as one serial connection (one serial system). .. The ID of the output control circuit 194it1 is set to be different from the IDs set in the decorative LED control circuit 194i131 of the frame-side VDP control target 131st decoration LED control circuit 194i143 of the frame-side VDP control target 143i143. It

Then, the eleventh serial controller 194gd11 in the frame-side signal separation control circuit 194g uses the decoration information as the serial data SDAT11′ based on the clock signal SCLK11′, and the decoration LED control circuit 194i131 for the frame-side VDP control target 131, the frame. , The decoration LED control circuit 194i131 for the side VDP control target 131, the decoration LED control circuit 194i143 for the frame side VDP control target 143, and the output control circuit 194it1. As described above, the electric decoration information is information for specifying the light emission mode, and is composed of the electric decoration LED specification information and the gradation information. The electric control information corresponds to the output control circuit 194it1. Source drive information is added. The electric drive source drive is information for designating the drive mode of the electric drive source on the side of the door frame 5, and is composed of output control designation information and output information. The output control designation information is information that designates the output control circuit 194it1 and is set with the above-mentioned ID. The output information is information for driving and controlling the electric drive source on the door frame 5 side.

The output control circuit 194it1 will be briefly described. The output control circuit 194it1 includes an address setting unit, a logic processing unit, a shift register, and an output port. The address setting unit can set the ID according to the magnitude of the voltage applied to the plurality of address setting terminals. The logic processing unit receives the serial data SDAT11′ from the eleventh serial controller 194gd11 in the frame side signal separation control circuit 194g based on the clock signal SCLK11′, and based on the address which is its own ID set by the address setting unit. , When the output control designation information in the serial data SDAT11' includes its own ID, it is determined that the serial data SDAT11' is for itself, and the output information in the serial data SDAT11' is fetched by the shift register to obtain the parallel data. When the output control designation information in the serial data SDAT11' does not include its own ID, it is determined that the serial data SDAT11' is not for itself and the serial data SDAT11' is controlled. The output information in (1) is not captured by the shift register (or even if it is captured, it is not restored to parallel data and is not written to the output port), and control is performed to maintain the previously written content (current content).

The output port is capable of outputting a parallel signal according to the parallel data written by the logic processing unit. The frame decoration drive amplifier board 194 includes a motor drive circuit (not shown) capable of outputting a drive signal to the dial drive motor 414 (electric drive source), and the parallel signal from the output port drives the motor as a control signal. Input to the circuit. The motor drive circuit can output a drive signal to the dial drive motor 414 (electric drive source) according to the logic of the parallel signal (control signal) from the output port. In this way, the output control circuit 194it1 and a motor drive circuit (not shown) capable of outputting a drive signal to the dial drive motor 414 (electric drive source) constitute a door side drive control circuit. This door side drive control circuit eliminates the need to provide the frame decoration drive amplifier board side motor transmission data storage area 4150caf shown in FIG. 18, in which the door side motor drive data is set, in the peripheral control RAM 4150c, and the backup management described above is performed. It is not a target and can contribute to reduction of the processing load of the peripheral control MPU 4150a.

According to the pachinko gaming machine 1 of this embodiment adopting this aspect, it is possible to perform an effect based on the progress of the game, and the dial drive motor 414 provided in the operation unit 400 of the door frame 5 of FIG. 7 as a control target. 17, the liquid crystal and sound control ROM 4160b of the liquid crystal and sound control unit 4160 in the peripheral control board 4140 of FIG. 17 as information storage means, the sound source built-in VDP 4160a of the liquid crystal and sound control unit 4160 in the peripheral control board 4140 of FIG. 19 as image object creating means, Channel CH2 of VDP4160a with a built-in sound source of FIG. 19 as a parallel signal output unit, twisted pair cable as a twisted wire, positive phase side ferrite beads as a positive phase side inductance element, negative phase side ferrite beads as a negative phase side inductance element, and signal conversion means 19, a transmitter IC 4160d of the peripheral control board 4140, a receiver IC 194f of the frame decoration drive amplifier board 194 of FIG. 19 as signal restoration means, a frame side signal separation control circuit 194g of the frame decoration drive amplifier board 194 of FIG. 19 as extraction means, drive control As means, a frame side VDP control target decoration LED control circuit 194i of the frame decoration drive amplifier board 194 of FIG. 42, a frame side VDP control target first decoration LED control circuit 194i1 to a frame side VDP control target first 143 decoration LED The control circuit 194i143 is provided.

The liquid crystal and sound control ROM 4160b can store a plurality of types of information regarding effects. Specifically, the liquid crystal and sound control ROM 4160b is game board side character data for drawing in the display area of the game board side effect display unit 1900, and the above-described predetermined screen (red (R) in this embodiment). : 50%, gray (G): 50%, blue (B): gray screen with 50%), and of the decorative boards of the game board 4, VDP4160a with a built-in sound source directly controls Game board side light emission mode setting image data for setting the light emission mode of a plurality of LEDs (decorative LEDs) provided on each of the plurality of game board side VDP control target decorative substrates to be controlled, and a door frame In order to set the light emission mode of the plurality of LEDs (decorative LEDs) provided on each of the plurality of frame-side VDP control target decoration boards that are directly controlled by the sound source built-in VDP4160a The door frame side light emitting mode setting image data and various sound data such as music, sound effects, notification sounds, and notification sounds are stored in advance.

The VDP 4160a with a built-in sound source drives a plurality of LEDs (decorative LEDs) mounted on various decorative substrates of the door frame 5 and a dial drive provided in the operation unit 400 of the door frame 5 based on the information read from the liquid crystal and the sound control ROM 4160b. The frame-side image object can be created so that the electric decoration information and the output information are included as an image as the control information for the motor 414.

Specifically, first, as described above, the peripheral control MPU 4150a uses the screen generation schedule data in time series according to the screen generation schedule data and the light emission mode generation schedule data set in the schedule data storage area 4150cae. Each time the V blank signal is input, the screen data arranged in the above and the light emission data arranged in time series in the light emission mode generation schedule data are input one by one from the first screen data and from the first light emission data. Output to the VDP4160a with a built-in sound source one by one.

The screen generation schedule data is configured by arranging the screen data defining the screen configuration in time series, and the screen generation schedule data for the game board side effect display unit 1900 (liquid crystal panel 5000e) and the plate side. There is screen generation schedule data for the liquid crystal display device 470, and the order of screens to be drawn (displayed) is defined. The light emission mode generation schedule data is configured such that light emission data defining the light emission mode is arranged in time series, and the light emission mode generation schedule data for the plurality of LEDs provided on each decorative board of the game board 4 and the door. There is a light emitting mode generation schedule data for a plurality of LEDs provided on each decorative substrate of the frame 5, and the order of the light emitting modes is defined respectively.

The sound source built-in VDP 4160a is a screen that defines the configuration of a predetermined screen (a gray screen having red (R): 50%, green (G): 50%, and blue (B): 50% in this embodiment). Data and light emission of a plurality of LEDs (decorative LEDs) provided on each of the plurality of frame-side VDP control target decorative substrates that are directly controlled by the sound source built-in VDP 4160a among the decorative substrates of the door frame 5. When the light emission data defining the mode is input from the peripheral control MPU 4150a, a predetermined screen (book) is displayed from the liquid crystal and sound control ROM 4160b based on the input screen data according to a predetermined door frame side generation rule. In the embodiment, sprite data is created by extracting dummy data for drawing a gray screen having red (R): 50%, green (G): 50%, and blue (B): 50%. The door frame side drawing data is generated in the door frame side drawing data area VRGN2a of the door frame side display area VRGN2 provided on the built-in VRAM, and the door is controlled from the liquid crystal and sound control ROM 4160b based on the input light emission data. Of the decorative boards of the frame 5, the light emission mode of a plurality of LEDs (decorative LEDs) provided on each of the plurality of frame-side VDP control target decorative boards that are directly controlled by the sound source built-in VDP 4160a is set. The door frame side light emission mode setting image data is extracted and the electric decoration information is generated as drawing data in the door frame side accompanying information area VRGN2b of the door frame side display area VRGN2 provided on the built-in VRAM. The electrical decoration information is information for designating the light emission mode and is composed of electrical decoration LED designation information and gradation information, to which electrical drive source drive information corresponding to the output control circuit 194it1 is added. It is composed. The electric drive source drive is information for designating the drive mode of the electric drive source on the side of the door frame 5, and is composed of output control designation information and output information. The output control designation information is information that designates the output control circuit 194it1 and is set with the above-mentioned ID. The output information is information for driving and controlling the dial drive motor 414 provided in the operation unit 400 of the door frame 5, which is an electric drive source on the door frame 5 side.

The channel CH2 of the VDP 4160a with a built-in sound source in FIG. 19 can output a parallel signal including a frame-side image object created by the VDP 4160a with a built-in sound source.

Specifically, the channel CH2 of the VDP 4160a with a built-in sound source uses a parallel interface. The drawing data output from the channel CH2 is composed of three video signals of a red video signal, a green video signal, and a blue video signal, and three sync signals of a horizontal sync signal, a vertical sync signal, and a clock signal. ing. The sound source built-in VDP 4160a includes, as a frame-side image object created by itself, door-frame-side drawing data generated in a door-frame-side drawing data region VRGN2a of a door-frame-side display region VRGN2 provided in the built-in VRAM, and a built-in Drawing data including the door frame side associated information area VRGN2b of the door frame side display area VRGN2 provided on the VRAM and the drawing data including parallel lighting signals are used as parallel signals for a red video signal, a green video signal, and a blue video signal. And a horizontal synchronizing signal, a vertical synchronizing signal, and a clock signal.

The transmitter IC 4160d of the peripheral control board 4140 converts the parallel signal output from the channel CH2 of the VDP 4160a with a built-in sound source into a signal of the clockless transmission system as a serial signal composed of a positive phase signal and a negative phase signal. It can be output.

Specifically, the transmitter IC 4160d has three video signals, that is, a red video signal, a green video signal, and a blue video signal, which are parallel signals output from the channel CH2 of the VDP 4160a with a built-in sound source, a horizontal synchronization signal, and a vertical synchronization signal. , And a clock signal, and three synchronous signals are serialized into a differential serial signal (serial data) called "V-by-One (registered trademark)" of THine Electronics Co., Ltd., which is a kind of clockless transmission system. (In other words, a parallel signal composed of three video signals of a red video signal, a green video signal, and a blue video signal, and three sync signals of a horizontal sync signal, a vertical sync signal, and a clock signal is multiplexed. In addition, serialize the serial signal (serial data) of the differential system) and control these various signals only with a differential 1 pair cable that makes one wiring the positive phase and the other wiring the opposite phase. The signal is output (transmitted) from the board 4140 to the frame peripheral relay terminal plate 868, the peripheral door relay terminal plate 882, and the frame decoration drive amplifier 194.

A twisted pair cable, which is a differential 1-pair cable, is configured by twisting wiring that transmits a positive-phase signal and wiring that transmits a negative-phase signal. Specifically, one wiring of the twisted pair cable is configured as a wiring for transmitting a positive phase signal, and the other wiring of the twisted pair cable is configured as a wiring for transmitting a reverse phase signal.

A positive-phase signal transmitted via a twisted pair cable is input to the positive-phase ferrite beads. The opposite-phase side ferrite beads are inputted with the opposite-phase signal transmitted via the twisted pair cable. Specifically, the frame decoration drive amplifier substrate 194 is provided with the positive phase side ferrite beads and the negative phase side ferrite beads. A serial signal (serial data) by a differential method called "V-by-One (registered trademark)" of THine Electronics Co., Ltd., which is a kind of clockless transmission method, is transmitted from the transmitter IC 4160d in the peripheral control board 4140 as a plus signal and a minus signal. Then, the plus signal is immediately before the RXIN+ terminal of the receiver IC 194f via a common mode choke coil (not shown) provided on the frame decoration drive amplifier substrate 194 or directly without a common mode choke coil (not shown). The circuit is configured so that it is input to the RXIN+ terminal via the provided positive-phase side ferrite beads, and the negative signal is input to the RXIN- terminal via the negative-phase side ferrite beads provided immediately before the RXIN- terminal of the receiver IC 194f. The circuit is configured to be input.

The positive-phase side ferrite beads and the negative-phase side ferrite beads reflect the noise that the inductor (coil) component of the ferrite bead penetrates into the twisted wire and prevent it from passing through, and the resistance component of the ferrite bead penetrates the twisted wire. Has the characteristic that it can be converted into heat and removed. Due to such characteristics of the ferrite beads, it is possible to suppress the disturbance of the waveform due to the superposition of noise on the serial signal transmitted through the twisted wire and arrange the waveform into a beautiful waveform.

The receiver IC 194f of the frame decoration drive amplifier board 194 outputs a serial signal composed of a positive-phase signal input via the positive-phase side ferrite beads and a negative-phase signal input via the negative-phase side ferrite beads. It can be restored to a parallel signal and output.

Specifically, when the serial signal (serial data) from the peripheral control board 4140 is input to the frame decoration drive amplifier board 194 via the twisted pair cable, the plus signal of the serial signal is provided immediately before the RXIN+ terminal of the receiver IC 194f. In addition to being input to the RXIN+ terminal via the positive-phase side ferrite beads, the negative signal of the serial signal is input to the RXIN- terminal via the negative-phase side ferrite beads provided immediately before the RXIN- terminal of the receiver IC 194f. When the receiver IC 194f receives the serial signal (serial data), the serialized various signals are parallel signals (that is, the red video signal, the green video signal, which are the drawing data output from the channel CH2 of the VDP 4160a with a built-in sound source, and the green video signal, and To the frame side signal separation control circuit 194g.

The frame-side signal separation control circuit 194g extracts and outputs electric decoration information and output information as control information from the frame-side image object created by the sound source built-in VDP 4160a based on the restored parallel signal output by the receiver IC 194f. It can be done.

Specifically, the frame-side signal separation control circuit 194g uses the parallel signal restored by the receiver IC 194f to determine the above-described predetermined screen (in the present embodiment, red (R): 50%, green (G): 50). %, blue (B): gray screen with 50%) door frame side drawing data, three video signals of a red video signal, a green video signal, and a blue video signal, a horizontal synchronization signal, and a vertical synchronization signal. , And clock signals, and a plurality of decorative boards of the door frame 5 provided on each of a plurality of frame-side VDP controlled decorative boards that are directly controlled by the sound source built-in VDP 4160a. It is separated into the electric decoration information for the LED (decorative LED) and the output information for the dial drive motor 414 provided in the operation unit 400 of the door frame 5 which is the electric drive source on the door frame 5 side.

42. Frame-side VDP control target decoration LED control circuit 194i of the frame-decoration drive amplifier board 194 of FIG. 42: frame-side VDP control target first decoration LED control circuit 194i1 to frame-side VDP control target 143 decoration LED control circuit 194i143 is a plurality of frames to be controlled by the sound source built-in VDP 4160a, which are directly controlled by the sound source built-in VDP 4160a, based on the electric decoration information as the control information output by the frame side signal separation control circuit 194g. It is possible to control the drive of a plurality of LEDs (decorative LEDs) provided on each of the side VDP control target decorative substrates. The output control circuit 194it1 provided in the frame side VDP control target decoration LED control circuit 194i of the frame decoration drive amplifier board 194 is based on the output information as the control information output by the frame side signal separation control circuit 194g, and the door frame 5 The drive control of the dial drive motor 414 provided in the operation unit 400 can be performed.

Specifically, the frame side signal separation control circuit 194g, based on the electrical decoration information separated from the parallel signal restored by the receiver IC 194f, the frame side VDP control target decoration LED control circuit 194i in the frame side VDP control target decoration LED control circuit 194i. 1 decoration LED control circuit 194i1 to frame side VDP control target is a control target directly controlled by the sound source built-in VDP 4160a of each decoration board of the door frame 5 via the 143th decoration LED control circuit 194i143. By outputting signals to the plurality of frame-side VDP control target decoration substrates, the plurality of LEDs (decorative LEDs) provided on each of the plurality of frame-side VDP control target decoration substrates emit light. As a result, the frame side VDP control target decoration LED control circuit 194i in the frame side VDP control target decoration LED control circuit 194i1 to the frame side VDP control target 143 decoration LED control circuit 194i143 separates the frame side signal. Based on the electric decoration information as the control information separated by the control circuit 194g, among the decoration boards of the door frame 5, a plurality of frame-side VDP control target decoration boards that are directly controlled by the sound source built-in VDP 4160a are controlled. A plurality of LEDs (ornamental LEDs) provided for each can perform a light emission effect.

The frame-side signal separation control circuit 194g controls a motor drive circuit (not shown) provided in the frame decoration drive amplifier board 194 via the output control circuit 194it1 based on the output information separated from the parallel signal restored by the receiver IC 194f. It is possible to output a signal and execute an effect by the dial drive motor 414 provided in the operation unit 400 of the door frame 5. As a result, the output control circuit 194it1 can execute the effect by the dial drive motor 414 provided in the operation unit 400 of the door frame 5 based on the output information as the control information separated by the frame-side signal separation control circuit 194g. it can.

As described above, based on the information read from the liquid crystal and the sound control ROM 4160b, the frame so that the output information is included as an image as the control information for the plurality of LEDs (decorative LEDs) mounted on the various decorative boards of the door frame 5 The side image object is created by the VDP4160a with a built-in sound source, the parallel signal including the created frame side image object is output from the channel CH2 of the VDP4160a with a built-in sound source, and the parallel signal is composed of a positive phase signal and a negative phase signal. The transmitter IC 4160d converts the serial signal into a serial signal, and the converted serial signal is a differential 1-pair cable configured by twisting a wire for transmitting a positive-phase signal and a wire for transmitting a negative-phase signal. A positive phase signal is input to the positive phase side ferrite beads and a negative phase signal is input to the negative phase side ferrite beads via the twisted pair cable. A serial signal composed of a positive phase signal input via the positive phase side ferrite beads and an opposite phase signal input via the negative phase side ferrite beads is input to the receiver IC 194f. .. That is, in the transmission path from the transmitter IC 4160d to the receiver IC 194f, the serial signal is transmitted via the twisted pair cable and the positive phase side ferrite beads and the negative phase side ferrite beads. The receiver IC 194f restores the input serial signal to a parallel signal again, and based on the restored parallel signal, the frame side signal separation control circuit 194g takes out the output information as the control information from the frame side image object, and takes out the output information. Based on the output information as the control information, the output control circuit 194it1 outputs a control signal to a motor drive circuit (not shown) included in the frame decoration drive amplifier board 194 to drive the dial drive motor 414 provided in the operation unit 400 of the door frame 5. It is possible to control.

The twisted pair cable consists of wiring that transmits positive phase signals and wiring that transmits negative phase signals twisted together, so if noise enters the twisted pair cable, wiring that transmits positive phase signals Then, noise will intrude into the wiring that transmits the signal of the opposite phase. Then, the noise invading the positive phase signal and the noise invading the negative phase signal cancel each other, and the disturbance of the waveform is suppressed through the positive phase side ferrite beads and the negative phase side ferrite beads. By inputting to the receiver IC 194f in a state in which the waveform is adjusted to a beautiful waveform, it is possible to restore the parallel signal again with the noise removed in the receiver IC 194f. Therefore, accurate control can be realized for the controlled object.

In addition to the dial drive motor 414 that can give various behaviors to the dial operation unit 401, a plurality of movable bodies are provided on the door frame 5 and a plurality of motors that can operate the plurality of movable bodies. When the door frame 5 is provided with an electric drive source such as a solenoid or a solenoid, similarly to the dial drive motor 414, a motor drive circuit (not shown) provided on the frame decoration drive amplifier board 194 via the output control circuit 194it1 described above. A drive signal to a motor or a solenoid (electric drive source) can be output from a solenoid drive circuit (not shown). As the movable body provided on the door frame 5, for example, a game device provided with a rotating body, a game device capable of moving a slide member in the left-right direction or in the up-down direction, and the like can be cited. The rotating body and the slide member may or may not be provided with the decorative LED.

Further, a motor drive circuit (not shown) capable of outputting a drive signal to the dial drive motor 414 (electric drive source) is provided with an enable signal input circuit, and the enable signal from the peripheral control MPU 4150a is input. The transmission path is formed so that Specifically, the enable signal is transmitted from the parallel I/O port of the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 to the frame peripheral relay terminal board 868 and the peripheral door relay terminal 882 via a peripheral control output circuit (not shown). It is input to the enable signal input circuit of the motor drive circuit (not shown) of the frame decoration drive amplifier board 194 via the above.

The motor drive circuit (not shown) drives the dial drive motor 414 (electric drive source) according to the logic of the parallel signal (control signal) from the output port based on the logic of the enable signal from the peripheral control MPU 4150a. Allow or disallow (prohibit) signal output. Here, the logic of the enable signal from the peripheral control MPU 4150a will be briefly described. When the logic of the enable signal from the peripheral control MPU 4150a is set to the operation permission logic (valid logic), the dial drive motor 414 (electric drive) The peripheral control MPU 4150a sets the dial drive motor 414 (electric drive source) in accordance with the logic of the parallel signal (control signal) from the output port described above by the motor drive circuit (not shown) as a drive permission state permitting the drive of the source). While permitting the output of the drive signal to the device, the logic of the enable signal from the peripheral control MPU4150a is set to the operation disapproval logic (invalid logic (logic that is the operation enable logic (valid logic) inverted)). The peripheral control MPU 4150a sometimes sets the dial drive motor 414 (electrical drive source) to a drive inhibit state in accordance with the logic of the parallel signal (control signal) from the output port described above by the motor drive circuit (not shown). The output of the drive signal to the drive motor 414 (electric drive source) is prohibited.

The peripheral control MPU 4150a sets the logic of the enable signal to permit the output of the drive signal of the dial drive motor 414 (electrical drive source) to rotate the dial drive motor 414 or to rotate the dial drive motor 414 (electrical drive source). The dial drive motor 414 can be stopped by prohibiting the output of the drive signal of the drive source). Thereby, for example, when the behavior of rotating the dial operation unit 401 in the clockwise direction is given, the peripheral control MPU 4150a determines the winning/losing judgment by the unique random number from the start of the fluctuation of the special symbol to the stop of the fluctuation. Within the period during which the symbol 1 is changing, it is performed at predetermined intervals (for example, 3 seconds) or randomly, and when the determination result is won, the logic of the enable signal is set to the operation permission logic (valid logic), while the determination result is lost. When this is done, the logic of the enable signal is set to the operation disapproval logic (invalid logic). Thus, the dial operation unit 401 is rotated in a clockwise direction, stopped, rotated again in a clockwise direction, and the like, and the dial operation unit 401 is intermittently rotated in real time. You can Further, when the behavior of rotating the dial operation unit 401 in the counterclockwise direction is given, the peripheral control MPU 4150a independently determines whether or not the random number is won or lost at predetermined intervals (for example, 3 seconds) within one fluctuation of the symbol, or Randomly, when the judgment result is successful, the logic of the enable signal is set to the operation enable logic (valid logic), while when the judgment result is unsuccessful, the logic of the enable signal is set to the operation disapproval logic (invalid logic). .. As a result, the dial operation unit 401 is rotated in the counterclockwise direction, stopped, rotated again in the counterclockwise direction, and so on, and the dial operation unit 401 is intermittently rotated in real time. Can be produced. In this way, the peripheral control MPU 4150a can increase the variation of the effect by the dial operation unit 401 in real time by independently setting the logic of the enable signal. Therefore, it is possible to suppress a decrease in interest.

The frame-side peripheral control MPU control target fifth decorative LED control circuit 194k5 to the frame-side peripheral control MPU control target seventh decorative LED control circuit 194k7 is the dish unit 300 shown in FIG. The whole plate unit 300 is light-emitted and decorated by dimming and lighting a plurality of LEDs (decorative LEDs) provided on each frame-side peripheral control MPU control target decorative substrate provided in the operation unit 400. At the same time, the dial operation section 401 and the pressing operation section 405 of the operation unit 400 are decorated with light emission. Here, for example, the frame side VDP control target 131th decorative LED control circuit 194i131, the frame side VDP control target 131st decorative LED control circuit 194i131,..., The frame side VDP control target first 143 decorative LED The control circuit 194i143, the output control circuit 194it1, and the decorative LED control circuit 194i145 of the frame side VDP control target 145 are provided on the frame decoration drive amplifier board 194 and electrically connected as one serial connection (one serial system). Circuit configuration. The ID of the decoration LED control circuit 194i145 of the frame side VDP control target 145 is the decoration LED control circuit 194i131 of the frame side VDP control target 131th decoration LED control circuit 194i143 of the frame side VDP control target 143, and the output. Different IDs are set in the control circuit 194it1. The decorative LED control circuit 194i145 of the frame-side VDP control target 145 is a plurality of LEDs mounted on each decorative substrate provided in the operation unit 400, and is used as a decorative LED (hereinafter referred to as "decorative LED of the operation unit 400"). Drive (light emission), the enable signal input circuit is provided in each of the decoration LED control circuits 194i145 of the frame side VDP control target 145, and the LED enable signal from the peripheral control MPU 4150a is input. The transmission path may be formed so that. Specifically, the enable signal for LED is transmitted from the parallel I/O port of the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 via the peripheral control output circuit (not shown) to the frame peripheral relay terminal board 868 and the peripheral door relay terminal. It is inputted to the enable signal input circuit in the decorative LED control circuit 194i145 of the frame-side VDP control target 145 of the frame decoration drive amplifier substrate 194 via 882.

For the LED enable signal, any one of a light emission permission logic (valid logic) and a light emission non-permission logic (invalid logic (logic obtained by inverting light emission permission logic (valid logic))) is set, and the light emission permission logic is set. (Valid logic) is the same as the operation permission logic (valid logic) set in the enable signal described above, and the light emission non-permission logic (invalid logic) is the operation non-permission logic (invalid) set in the enable signal described above. Logic) is the same logic. When the light emission permission logic (valid logic) is set in the logic of the LED enable signal, the peripheral control MPU4150a sets a drive permission state (light emission permission state) that permits driving (light emission) of the decoration LED of the operation unit 400. While the decoration LED control circuit 194i145 of the frame-side VDP control target 145 allows the adjustment of the brightness (grayscale) of the decoration LED of the operation unit 400 based on the above-mentioned electrical decoration information, the LED enable signal When the light emission non-permission logic (invalid logic (logic in which light emission permission logic (valid logic) is inverted)) is set as the logic, a drive prohibited state (light emission prohibited) that prohibits driving (light emission) of the decorative LED of the operation unit 400 As the state), the peripheral control MPU 4150a prohibits the adjustment of the brightness (gradation) of the decorative LED of the operation unit 400 based on the above-described electrical decoration information by the decorative LED control circuit 194i145 of the frame-side VDP control target 145. And As a result, when the dial operation unit 401 is rotated, stopped, rotated again, and so on, and the dial operation unit 401 is intermittently rotated, the decoration LED of the operation unit 400 is driven (light emission). Therefore, it is possible to provide the player with a sense of unity by interlocking (synchronizing) the operation of the dial operation unit 401 and the light emission mode of the decorative LED of the operation unit 400.

In the process of performing the winning/losing determination described above (hereinafter, referred to as “door frame side movable effect execution winning/decision determining process”), the effect control program, for example, the peripheral control of the peripheral controller power-on process shown in FIG. 68. In the received command analysis processing of step S1022 in the routine regular processing, various commands stored in the received command storage area 4150cac are analyzed, and the analyzed command imparts the behavior of rotating the dial operation unit 401 clockwise. At this time, when the behavior of rotating the dial operation unit 401 in the counterclockwise direction is given, the winning determination is performed at the above-described predetermined intervals (for example, 3 seconds) or randomly. Then, the logic setting and output of the enable signal and the LED enable signal based on the determination result by the door frame side movable effect implementation hit/miss determination process is newly provided with the enable signal logic setting and output process in the above-described peripheral control unit steady process. (This enable signal logic setting and output process may be provided as one process of the peripheral controller 1 ms timer interrupt process shown in FIG. 70). Then, when the special symbol 1 changing period ends (when the special figure 1 tuning effect end command and the special figure 2 tuning effect end command are received), the logic of the enable signal is an initial value (that is, operation permission logic, light emission permission logic). (Valid logic)) and the enable signal is output in the enable signal logic setting and output processing. Note that the determination result by the door frame side movable effect execution hit/miss determination process may be configured to be retained and updated as information to be backed up, for example, by providing a dedicated area in Bank0 (1fr) in the backup management target work area 4150ca. Good. Further, the logics of the enable signal and the LED enable signal are set to the operation permission logic and the light emission permission logic (valid logic) as initial values when the power is turned on. At the time of power recovery when a power failure or a momentary power failure occurs during the operation of the hall and the power is restored, the logic of the enable signal and the LED enable signal is the initial value (that is, the operation permission logic and the light emission permission logic (valid logic). ) May be set, the operation permission logic, the light emission permission logic (valid logic) or the operation non-permission logic, the light emission non-permission logic (invalid) based on the dedicated area provided in the backup management target work area 4150ca. Logic) may be set. Further, the enable signal and the LED enable signal are configured as individual signals, but may be configured to be used as one common enable signal. By doing so, it is possible to contribute to the reduction of the processing load of the peripheral control MPU 4150a by reducing the number of signals for setting the logic, and to contribute to the cost reduction by reducing the number of wirings.

In addition to the dial drive motor 414 that can give various behaviors to the dial operation unit 401, a plurality of movable bodies are provided on the door frame 5 and a plurality of motors that can operate the plurality of movable bodies. When the door frame 5 is provided with an electric drive source such as a solenoid or a solenoid, similarly to the dial drive motor 414, a motor drive circuit (not shown) provided on the frame decoration drive amplifier board 194 via the output control circuit 194it1 described above. A drive signal to a motor or a solenoid (electric drive source) can be output from a solenoid drive circuit (not shown). Even in such a case, the peripheral control MPU 4150a sets and outputs the logic of the enable signal (motor enable signal, solenoid enable signal) described above, and outputs the drive signal to the motor or solenoid (electric drive source). By permitting or disabling (prohibiting) output, it is possible to create an effect by a plurality of movable bodies on the door frame 5 in real time and increase variations of the effect in real time. As the movable body provided on the door frame 5, for example, a game device provided with a rotating body, a game device capable of moving a slide member in the left-right direction or in the up-down direction, and the like can be cited. The rotating body and the slide member may or may not be provided with the decorative LED.

Further, in the above-described embodiment, the VDP 4160a with a built-in sound source of FIG. 19 has two channels CH1 and CH2, the channel CH1 uses a differential interface by a serial system called LVDS, and the channel CH2 uses a parallel system. However, it may have a plurality of channels such as three channels and four channels. In this case, one or both of the channels CH3 and CH4 may use a differential interface by a serial method called LVDS or an interface by a parallel method. When the VDP 4160a with a built-in sound source has a plurality of channels, an area for creating drawing data for each channel may be provided in the built-in VRAM of the VDP 4160a with a built-in sound source, or may be externally attached to the VDP 4160a with a built-in sound source. It may be configured to be provided in each RAM (frame memory).

Further, in the above-described embodiment, the VDP 4160a with a built-in sound source has a predetermined screen (in the present embodiment, red (R): 50%, green (G): 50%, and blue (B): 50% gray). Screen data for defining the configuration of the screen) and a plurality of frame-side VDP control target decorative boards that are control targets directly controlled by the sound source built-in VDP 4160a among the decorative boards of the door frame 5. When light emission data that defines the light emission mode of the LED (decorative LED) is input from the peripheral control MPU 4150a, liquid crystal and sound control is performed based on the input screen data according to a predetermined door frame side generation rule. Dummy data for drawing a predetermined screen (a gray screen having red (R): 50%, green (G): 50%, blue (B): 50% in the present embodiment) is extracted from the ROM 4160b. Then, the sprite data is created to generate door frame side drawing data in the door frame side drawing data area VRGN2a of the door frame side display area VRGN2 provided on the built-in VRAM, and based on the input light emission data. , The liquid crystal and sound control ROM 4160b to the plurality of LEDs (for decoration) provided on each of the frame-side VDP control target decorative substrates which are control targets to be directly controlled by the sound source built-in VDP 4160a among the decorative substrates of the door frame 5. Door frame side accompanying information area of the door frame side display area VRGN2 provided on the built-in VRAM by extracting door frame side light emitting mode setting image data for setting the light emitting mode of (LED). The door frame side of a predetermined screen (in the present embodiment, a gray screen having red (R): 50%, green (G): 50%, and blue (B): 50%) by being generated in VRGN 2b The drawing data is provided with the electric decoration information according to a predetermined door frame side generation rule, and the drawing data generated in the door frame side display region VRGN2 is output from the channel CH2. Only the door frame side light emission mode setting image data for setting the light emission mode of the plurality of LEDs (decorative LEDs) provided on each of the plurality of frame-side VDP control target decorative substrates that are directly controlled by the VDP 4160a May be extracted to generate the electric decoration information as drawing data in the door frame side display area VRGN2 provided on the built-in VRAM, and the drawing data may be output from the channel CH2. In other words, the door frame side display area VRGN2 is provided as the door frame side accompanying information area VRGN2b without providing the door frame side drawing data area VRGN2a in the door frame side display area VRGN2.

In such a configuration, as the predetermined door frame side generation rule described above, the first resolution conversion unit of the signal separation unit 194ga in the frame side signal separation control circuit 194g of the frame decoration drive amplifier board 194 shown in FIG. Since the door frame side drawing data to be cut out by 194gaa does not exist in the first place, the door frame side drawing data is not cut out at all, and the second resolution conversion unit 194gab of the signal separation unit 194ga is configured to operate in the sound source built-in VDP 4160a. The decoration information generated as drawing data is accurately cut out in the door frame side accompanying information area VRGN2b of the door frame side display area VRGN2 provided on the built-in VRAM, and the distribution output control unit is provided. 194gc is configured to be able to accurately distribute the electrical decoration information read from the buffer memory 194gb to the first serial controller 194gd1 to the eleventh serial controller 194gd11, respectively. According to the predetermined door frame side generation rule configured in this way, in the signal separation unit 194ga, the first resolution conversion unit 194ga does not cut out the door frame side drawing data at all, and the second resolution conversion unit 194gab. In the above, from the drawing data restored to the parallel signal, among the decorative boards of the door frame 5, a plurality of frame-side VDP control object decorative boards that are directly controlled by the sound source built-in VDP 4160a By cutting out the electric decoration information for the LED (decorative LED), a plurality of frames, which are control targets to be directly controlled by the sound source built-in VDP 4160a, of the respective decorative boards of the door frame 5 from the drawing data restored to the parallel signal. The electric decoration information for a plurality of LEDs (decorative LEDs) provided on each of the side VDP control target decorative substrates is separated and output to the buffer memory 194gb to perform the writing operation.

Furthermore, in the above-described embodiment, the pachinko gaming machine 1 is described as an example, but the gaming machine to which the present invention is applicable is not limited to the pachinko gaming machine, and gaming machines other than the pachinko gaming machine, for example, slot machines. The present invention can also be applied to a (rotating body type game machine) or a fusion game machine in which a pachinko game machine and a slot machine are fused (one that performs a slot game using a game ball). Here, a slot machine as a spinning-type gaming machine will be described with reference to FIG. FIG. 87 is a schematic perspective view of the slot machine.

As shown in FIG. 87, the slot machine 6000 includes a front door 6002 and a main body portion 6004. The front door 6002 and the main body portion 6004 are connected to each other via a hinge (not shown). The front door 6002 can be opened from the main body portion 6004 by inserting a key into a keyhole 6005 provided at the right end of the front door 6002 and turning clockwise around this hinge.

The upper half of the front door 6002 is provided with a game panel 6006, and the lower half of the front door 6002 is formed with a protruding portion that protrudes forward from the game panel 6006. The medal slot 6008, the bet buttons 6010 and 6012, the starting lever 6014, the left stop button 6016, the middle stop button 6018, the right stop button 6020, and the like are arranged along the lower edge of the game panel 6006 on this protrusion. A storage settlement button 6022 and a decorative plate 6024 are arranged in the lower half of the front door 6002, and a tray 6026 is provided below the decorative plate 6024. These bet buttons 6010, 6012, start lever 6014, left stop button 6016, middle stop button 6018, right stop button 6020, and storage adjustment button 6022 are main control boards (main control MPU) for controlling the progress of the game (not shown). ) Is electrically connected to.

A rectangular display window (not shown) is formed at a substantially central position of the game panel 6006, and the three variable rotating bodies (not shown) installed inside the slot machine 6000 and the rendering device are seen through the display window. You can do it. On these variable rotators, a light-transmissive pattern band, in which a plurality of types of patterns (for example, bell, watermelon, cherry, 7, V, etc.) are printed as pattern information, is attached to each tubular frame. ing. Such a tubular variable rotating body is called a reel or a drum in a gaming machine such as a slot machine, and an output shaft of a stepping motor (not shown) and each variable rotating body are connected to each other. These stepping motors are drive-controlled by a main control board (main control MPU), and by rotating the output shaft of the stepping motor, a plurality of types of symbols are continuously displayed from the above-mentioned display window from top to bottom. It seems to change to.

The rendering device includes a plurality of movable bodies (the above-described rotary light-emitting device 3100, the model 3400 imitating the detonator, and the model 3500 imitating dynamite), a rendering display unit (the rendering display unit 1900 described above), and a plurality. Each of the decorative boards on which the LED of FIG. An effect control board (VDP with built-in sound source) (not shown) controls drawing of the liquid crystal panel in the effect display unit and switching of a plurality of light guide plates of the effect display unit based on various commands from the main control board (main control MPU). By performing various controls such as light emission control of a plurality of LEDs provided on each decorative substrate, the progress of the effect is controlled. The main control board and the effect control board are installed inside the slot machine 6000.

The main control board (main control MPU), a predetermined number of medals are inserted into the medal insertion slot 6008 as a game medium, the variable display of the symbol information is started based on the operation of the start lever 6014, the left stop button 6016, the middle stop The variable display of the symbol information is stopped based on the operation of the button 6018 or the right stop button 6020 or the elapse of a predetermined time. Then, the main control board (main control MPU) generates a profit-giving state (big hit game state) on condition that the symbol information is in a predetermined specific display mode, and a large amount of medals as a game medium are received in the tray 6026. Pay out.

In the fusion game machine, the medal slot 6008 becomes a ball slot 6008', and the main control board (main control MPU) is loaded with a predetermined number of game balls as a game medium into the ball slot 6008', and the starting lever. The variable display of the symbol information is started based on the operation of 6014, and the variable display of the symbol information is stopped based on the operation of the left stop button 6016, the middle stop button 6018, the right stop button 6020 or the lapse of a predetermined time. Then, the main control board (main control MPU) generates a profit giving state (big hit game state) on condition that the symbol information is a predetermined specific display mode, and a large amount of game balls as a game medium in the tray 6026. Pay out to.

1... Pachinko gaming machine, 2... Outer frame, 3... Main body frame, 4... Game board, 5... Door frame, 192... Handle relay terminal plate, 300... Dish unit, 470... Upper plate side liquid crystal display device, 650... Hit ball Launching device, 740... Award ball device, 744... Discharge motor, 751... Counting switch, 784... External terminal board, 851... Power supply board, 855... Power supply control unit, 855d... Power supply creating circuit, 855da... Power consumption monitoring circuit, 855daa ... power measurement circuit, 855dab... power consumption suppression stage determination circuit, 855db... +5V power supply creation circuit, 855dc... +12V power supply creation circuit, 855dd... +24V power supply creation circuit, 860a... operation switch, 860b... error LED indicator, 1100... game Area 1900... Game board side effect display unit, 2100... Attacker unit, 2105... Starter solenoid, 2108... Attacker solenoid, 4100... Main control board, 4100a... Main control MPU, 4110... Payout control board, 4120... Payout control section 4120a...Payout control MPU, 4120ag... Launch ball sending control circuit, 4120ah... Launch ball sending failure monitoring circuit, 4140...Peripheral control board, 4150...Peripheral control unit, 4150a...Peripheral control MPU, 4150f... Power consumption status history RAM, 4150g... Battery, 4150k... Power saving mode transition notification LED, 4160... Liquid crystal and sound control unit, 4160a... VDP with built-in sound source, 4165... RTC control unit, 4165a... RTC, 4165b... Battery, 4180... Motor drive board, BC0... Capacitor, MC2... Electrolytic capacitor.

Claims (1)

A gaming machine that produces effects based on the progress of the game,
An information storage means capable of storing a plurality of types of information regarding performance,
An image object creating unit capable of creating an image object based on the information read from the information storage unit;
A parallel signal output unit that outputs a parallel signal including the image object created by the image object creating unit;
A signal converting unit that converts the parallel signal output by the parallel signal output unit into a serial signal composed of a positive-phase signal and a negative-phase signal, and outputs the serial signal.
A twisted wire configured by twisting the wiring transmitting the positive phase signal and the wiring transmitting the negative phase signal,
The positive-phase side ferrite beads to which the positive-phase signal and the opposite-phase signal transmitted by the stranded wire are input via a common mode choke coil, and the opposite-phase signal is input. Electrically connected to the opposite phase ferrite beads,
A serial signal composed of the positive phase signal input via the positive phase side ferrite beads and the negative phase signal input via the negative phase side ferrite beads is restored to a parallel signal and output. Signal restoration means for
Image display means for displaying an image based on the image object created by the image object creating means based on the restored parallel signal output by the signal restoring means;
A gaming machine comprising: