JP2017148102A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine capable of accurately controlling an object to be controlled.SOLUTION: A frame side image object is created by a sound source built-in VDP. A parallel signal including the created frame side image object is outputted by a channel CH2 of the sound source built-in VDP. The parallel signal is converted by a transmitter into a serial signal composed by a positive phase signal and a reversed phase signal. The converted serial signal is inputted to a receiver IC via twist pair of cables to be differential one pair of cables composed by twisting wiring transmitting the positive phase signal and wiring transmitting the reversed phase signal.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a gaming machine.

  2. Description of the Related Art Conventionally, a gaming machine that displays an image on a display device and controls a plurality of controlled objects based on a control signal output in a serial manner to produce a gorgeous effect has been proposed (for example, Patent Document 1). .

JP 2008-073438 A (FIGS. 7 to 11)

  By the way, in a gaming machine, accurate control is required for a controlled object in order to perform a gorgeous effect using the controlled object as intended during development.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a gaming machine capable of realizing accurate control on a controlled object.

  Effective solutions for achieving the above-described object will be described below. In addition, the effect | action etc. are demonstrated as needed. In addition, for easy understanding, the corresponding configuration in the embodiment of the invention is also shown as appropriate, but is not limited at all.

(Solution 1)
A gaming machine that produces an effect based on the progress of the game, the control target, an information storage unit capable of storing a plurality of types of information related to the effect, and a control for the control target based on information read from the information storage unit Image object creation means capable of creating an image object so that information is included as an image, a parallel signal output section for outputting a parallel signal including the image object created by the image object creation means, and the parallel signal output section The signal conversion means for converting the parallel signal output from the above into a serial signal composed of a positive-phase signal and a negative-phase signal and outputting the serial signal, the wiring for transmitting the positive-phase signal, and the negative-phase signal A stranded wire configured by twisting together wires that transmit the wire, and the positive phase signal and the reverse phase that are input via the stranded wire. A signal restoring means for restoring a serial signal composed of signals to a parallel signal and outputting the parallel signal; and the image object created by the image object creating means based on the restored parallel signal output by the signal restoring means A game machine comprising: take-out means for taking out and outputting the control information from the control unit; and drive control means for performing drive control of the control target based on the control information outputted from the take-out means.

  In this gaming machine, it is possible to produce effects based on the progress of the game, control target, information storage means, image object creation means, parallel signal output unit, stranded wire, signal conversion means, signal restoration means, extraction means, drive Control means are provided. The information storage means can store a plurality of types of information related to the effect. The image object creating means can create an image object based on the information read from the information storage means so that the control information for the controlled object is included as an image. The parallel signal output unit can output a parallel signal including an image object created by the image object creating means. The signal conversion means can convert the parallel signal output from the parallel signal output unit into a serial signal composed of a normal phase signal and a reverse phase signal and output the serial signal. The stranded wire is configured by twisting together a wiring for transmitting a normal phase signal and a wiring for transmitting a reverse phase signal. The signal restoration means can restore a serial signal composed of a normal phase signal and a reverse phase signal input via a stranded wire into a parallel signal and output the parallel signal. The extracting means can extract control information from the image object created by the image object creating means based on the restored parallel signal output by the signal restoring means and output it. The drive control means can perform drive control of the controlled object based on the control information output by the take-out means.

  In this gaming machine, it is possible to execute an effect by a controlled object.

  As described above, the image object creating unit creates the image object so that the control information for the control target is included as an image based on the information read from the information storage unit, and the parallel signal including the created image object is the parallel signal. The output unit outputs the parallel signal, and the signal conversion means converts the parallel signal into a serial signal composed of a positive-phase signal and a reverse-phase signal, and the converted serial signal transmits a positive-phase signal. It is input to the signal restoration means via a stranded wire formed by twisting wires that transmit signals of opposite phases. That is, in the transmission path from the signal converting means to the signal restoring means, a serial signal is transmitted via a stranded wire. The signal restoration means restores the input serial signal again to a parallel signal, the control information is taken out from the image object based on the restored parallel signal, and the control target drive is driven based on the extracted control information. The drive control means can perform the control.

  A stranded wire is composed of a wire that transmits a positive-phase signal and a wire that transmits a reverse-phase signal, so that when noise enters the stranded wire, the wire transmits a positive-phase signal. As a result, noise enters the wirings that transmit signals of opposite phases. Then, the noise that has entered the normal phase signal and the noise that has entered the reverse phase signal cancel each other, so that the signal can be restored to the parallel signal again with the noise removed by the signal restoration means. Therefore, accurate control can be realized for the controlled object.

  In the present embodiment, for example, the pachinko gaming machine 1 of FIG. 1 corresponds to a gaming machine, and a plurality of LEDs (decorative LEDs) mounted on various decorative boards of the door frame 5 of FIG. 2 or the door frame 5 of FIG. The dial drive motor 414 provided in the operation unit 400 corresponds to the control target, the liquid crystal and sound control ROM 4160b of the peripheral control board 4140 in FIG. 17 corresponds to the information storage means, and the peripheral in FIG. The frame side image object which is the drawing data generated in the door frame side display area VRGN2 provided on the built-in VRAM of the liquid crystal and sound source built-in VDP 4160a of the sound control unit 4160 on the control board 4140 corresponds to the image object, and the periphery of FIG. The liquid crystal and sound source built-in VDP 4160a of the sound control unit 4160 on the control board 4140 corresponds to the image object creating means. The channel CH2 of the sound source built-in VDP 4160a in FIG. 19 corresponds to the parallel signal output unit, the twisted pair cable corresponds to the stranded wire, the transmitter IC 4160d of the peripheral control board 4140 in FIG. 19 corresponds to the signal conversion means, and the frame decoration in FIG. The receiver IC 194f of the drive amplifier board 194 corresponds to signal restoring means, the frame side signal separation control circuit 194g of the frame decoration drive amplifier board 194 in FIG. 19 corresponds to extraction means, and the frame of the frame decoration drive amplifier board 194 in FIG. The side VDP control object decoration LED control circuit 194i (the frame side VDP control object first decoration LED control circuit 194i1 to the frame side VDP control object 143 decoration LED control circuit 194i143) and the output control circuit 194it1 are drive control means. It corresponds to.

(Solution 2)
The gaming machine according to claim 1, wherein the gaming machine is a revolving type gaming machine.

  In the gaming machine of the present invention, since the gaming machine is a spinning type gaming machine, the operational effect of the solving means 1 can be obtained in the spinning type gaming machine. As a basic configuration of the spinning machine, after a symbol information string (for example, a plurality of reel columns with a plurality of symbol information) composed of a plurality of symbol information is variably displayed, the display result of the symbol information is stopped and displayed. In addition to the fluctuation display means, the fluctuation display of the symbol information is started based on the operation of the start operation means (for example, the start lever), and based on the operation of the stop operation means (for example, the stop button) or the elapse of a predetermined time. Stop changing the symbol information. And it is provided with a profit granting state generating means for generating a profit granting state (big hit gaming state) on the condition that the symbol information becomes a predetermined specific display mode, and a medal is used as a game medium, and a profit granting state is generated. It is structured so that a large amount of medals are sometimes paid out.

(Solution 3)
The gaming machine according to Solution 1, wherein the gaming machine is a fusion gaming machine obtained by fusing a pachinko gaming machine and a revolving gaming machine.

  In the gaming machine of the present invention, since the gaming machine is a fusion gaming machine in which a pachinko gaming machine and a spinning-type gaming machine are fused, The effect of the solution 1 is obtained. As a basic configuration of a fusion gaming machine in which a pachinko gaming machine and a spinning-type gaming machine are merged, a symbol information string composed of a plurality of symbol information (for example, a plurality of reel strings with a plurality of symbols) is variably displayed. Later, it is provided with a fluctuation display means for stopping and displaying the display result of the symbol information, and starts the fluctuation display of the symbol information based on the operation of the start operation means (for example, the start lever), and the stop operation means (for example, stop) Button) or the change display of the symbol information is stopped based on the passage of a predetermined time. And it is provided with the profit grant state generation means which generates a profit grant state (big hit game state) on condition that the symbol information becomes a predetermined specific display mode, and a game ball is used as a game medium, A large amount of game balls are paid out when they are generated.

  In the gaming machine of the present invention, it is possible to achieve accurate control over the controlled object.

It is a perspective view which shows the state which open | released the main body frame with respect to the outer frame of a pachinko gaming machine, and opened the door frame with respect to the main body frame. It is a front view of a pachinko gaming machine. It is a rear view of a pachinko gaming machine. It is a front perspective view of an outer frame. It is a front perspective view of a main body frame. It is a back surface perspective view of the board | substrate unit in a main body frame. It is a perspective view of a door frame. It is a front view of a game board. It is the disassembled perspective view which decomposed | disassembled the game board of FIG. 8 and was seen from the front. It is a front exploded perspective view showing a configuration example when the effect display unit is viewed from the front. It is a rear surface exploded perspective view showing a configuration example when the effect display unit is viewed from the rear surface. It is sectional drawing which shows an example of the cross-sectional structure of an effect display unit. It is a front view which expands and shows the function display unit in a game board in the state attached to the pachinko gaming machine. It is a block diagram of a main control board, a payout control board, and a peripheral control board. FIG. 15 is a block diagram showing a continuation of FIG. 14. It is the schematic of the various detection signals input / output to lending device connection terminal boards, such as a game ball which relays the electrical connection of the payout control board which comprises a main board, CR unit, and a frequency display board. FIG. 15 is a block diagram showing a continuation of FIG. 14. It is a block diagram which shows the outline of peripheral control MPU. It is a block diagram around VDP with a built-in sound source in the liquid crystal and the sound control unit. FIG. 20 is a block diagram continued from FIG. 19. It is a block diagram which shows the power supply system of a pachinko gaming machine. FIG. 4A is a block diagram showing a power generation circuit, and FIG. 2B is a diagram showing a relationship between power consumption and a power consumption suppression level accompanying the power consumption. FIG. 22 is a block diagram illustrating the continuation of FIG. 21. It is a circuit diagram which shows the circuit of a main control board. It is a circuit diagram which shows a power failure monitoring circuit. It is a circuit diagram which shows the interface circuit for communication between the board | substrates of a main control board and a peripheral control board. It is a circuit diagram which shows the circuit etc. of a payout control part. It is a circuit diagram which shows the payout control input circuit. FIG. 29 is a circuit diagram showing a continuation of FIG. 28. It is a circuit diagram which shows a payout motor drive circuit. It is a circuit diagram which shows CR unit input / output circuit. It is an input / output diagram showing various input / output signals to / from the main control board and various output signals to the external terminal board. It is a figure which shows the arrangement | sequence of the output terminal of an external terminal board. It is a block diagram of a liquid crystal output substrate. It is a figure which shows the correspondence of the various serial controllers and output destination in a game board side signal separation control circuit. It is a block diagram of various light-guide plate control circuits. It is a block diagram of a game board side VDP control target decoration LED control circuit. It is a block diagram of a game board side peripheral control MPU control target decoration LED control circuit. It is a block diagram of a frame decoration drive amplifier board. It is a figure which shows the correspondence of the various serial controllers in a frame side signal separation control circuit, and an output destination. It is a figure which shows the correspondence of the frame side VDP control object decoration LED control circuit and several LED (decoration LED) provided in the frame side VDP control object decoration board | substrate. It is a block diagram of a frame-side VDP control target decoration LED control circuit. It is a block diagram of a frame side peripheral control MPU control target decoration LED control circuit. It is a table which shows an example of the various commands transmitted to the payout control board from the main control board. It is a table which shows an example of the various commands transmitted to a peripheral control board from a main control board. 46 is a table showing a continuation of various commands transmitted from the main control board to the peripheral control board in FIG. It is a table which shows an example of the various commands from the payout control board which a main control board receives. It is a flowchart which shows an example of the main control side power-on process. FIG. 49 is a flowchart showing a continuation of main-control-side power-on processing in FIG. It is a flowchart which shows an example of the main control side timer interruption process. It is a flowchart which shows an example of the process at the time of power-on of a payout control part. FIG. 52 is a flowchart showing a continuation of the power-on process of the payout control unit of FIG. 51. FIG. FIG. 53 is a flowchart showing a continuation of the payout control unit power-on process following FIG. 52. It is a flowchart which shows an example of a payout control part timer interruption process. It is a flowchart which shows an example of a rotation angle switch log | history production process. It is a flowchart which shows an example of a sprocket fixed position determination skip process. It is a flowchart which shows an example of a spherical collision determination process. It is a flowchart which shows an example of the prize ball stock number addition process for prize balls. It is a flowchart which shows an example of the number-of-use prize ball stock number addition process. It is a flowchart which shows an example of a stock monitoring process. It is a flowchart which shows an example of a pay-out ball engagement operation determination setting process. It is a flowchart which shows an example of a payout setting process. It is a flowchart which shows an example of a sphere ball movement setting process. It is a flowchart which shows an example of a retry operation | movement monitoring process. It is a flowchart which shows an example of a mismatch counter reset determination process. It is a flowchart which shows an example of an error cancellation operation determination process. It is a timing chart which shows the signal process (a) at the time of paying-out operation by ball lending, and the input signal confirmation process (a) from CR unit. It is a flowchart which shows an example of a peripheral control part power-on process. It is a flowchart which shows an example of the peripheral control part V blank interruption process. It is a flowchart which shows an example of a peripheral control part 1ms timer interruption process. It is a flowchart which shows an example of a peripheral control part command reception interruption process. It is a flowchart which shows an example of a peripheral control part power failure warning signal interruption process. It is a flowchart which shows an example of a power saving power saving mode transition determination process. It is a flowchart which shows an example of a power consumption monitoring process. The figure which shows the relationship between the value set as a master volume value for power suppression, and a power consumption suppression stage, The figure which shows the relationship between the brightness | luminance set as a brightness | luminance for power suppression, and a power consumption suppression stage (b) ). It is a flowchart which shows an example of a LOCKN signal log | history creation process. It is a flowchart which shows an example of a connection malfunction determination process. It is a flowchart which shows an example of a connection recovery process. It is a timing chart explaining the timing which outputs a connection confirmation signal with respect to the INIT terminal of the transmitter IC for upper plate side liquid crystals. It is a figure which shows an example of the variable display effect displayed on the display area of a game board side effect display unit. It is a figure which shows an example of the effect displayed with the switching of a light-guide plate in the display area of a game board side effect display unit. It is a figure which shows an example of the production of the continuation of FIG. FIG. 83 is a diagram showing an example of the effect subsequent to FIG. 82. FIG. 84 is a diagram showing an example of a continuation effect of FIG. 83. It is a schematic explanatory drawing of the various terminals of serial transmission transceiver IC. It is the schematic of the usage example of serial transmission transceiver IC. It is a schematic perspective view of a slot machine.

[1. Overall configuration of pachinko machine]
Hereinafter, a pachinko gaming machine as a gaming machine of the present invention will be described with reference to the drawings. First, the entire pachinko gaming machine according to the embodiment will be described with reference to FIGS. FIG. 1 is a perspective view showing a state in which a main body frame is opened with respect to an outer frame of a pachinko gaming machine according to an embodiment and a door frame is opened with respect to the main body frame, and FIG. 2 is a front view of the pachinko gaming machine. FIG. 3 is a rear view of the pachinko gaming machine.

  As shown in FIG. 1 to FIG. 3, the pachinko gaming machine 1 includes an outer frame 2 installed in an island facility (not shown) of a game hall, and a box that is pivotally supported by the outer frame 2 so as to be opened and closed and opened on the front side. A game board 4 having a frame-shaped main body frame 3, a game area 1100 in which a game ball as a game medium is inserted and fixed to the main body frame 3 from the front side, and the front face of the main body frame 3 and the game board 4 are on the player side And a door frame 5 pivotally supported so as to be openable and closable with respect to the main body frame 3. The door frame 5 of the pachinko gaming machine 1 stores a gaming window 101 formed so that the gaming area 1100 of the gaming board 4 can be viewed from the player side, and a gaming ball disposed below the gaming window 101. A dish-shaped upper plate 301 and lower plate 302 (see FIG. 7), and a handle device 500 that a player operates to drive game balls stored in the upper plate 301 into the game area 1100 of the game board 4 It is equipped with.

  Also, in the pachinko gaming machine 1, the outer frame 2, the main body frame 3, and the door frame 5 are each formed in a vertically long rectangular shape extending in the vertical direction in the front view, and the horizontal widths in the horizontal directions are substantially the same. The size of the main body frame 3 and the door frame 5 is slightly shorter than that of the outer frame 2. A decorative cover 23 is attached to the front surface of the outer frame 2 at a position below the main body frame 3 and the door frame 5, and the front surface of the outer frame 2 is completely closed by the door frame 5 and the decorative cover 23. It has become so. The outer frame 2, the main body frame 3, and the door frame 5 are arranged so that their upper ends are substantially aligned, and the main body frame 3 and the door frame 5 can be rotated at a position on the left end front side of the outer frame 2. The right end of the main body frame 3 and the door frame 5 moves to the front side with respect to the outer frame 2 so as to be in an open state.

  Further, the pachinko gaming machine 1 has a game area 1100 into which a game ball is driven through a substantially circular game window 101 in front view, and projects forward to the lower side of the game window 101. In this way, two upper plates 301 and lower plates 302 are arranged vertically. In addition, a handle device 500 for the player to operate is arranged at the lower right corner of the front surface of the door frame 5. When the rotation operation is performed, the game ball in the upper plate 301 is driven into the game area 1100 of the game board 4 with a hitting strength corresponding to the rotation angle, and a game can be played.

  The game window 101 of the door frame 5 is closed by a transparent glass unit 590 so that the player can visually recognize the inside of the game area 1100, but the player inserts a hand or the like into the game area 1100 to play the game. The game balls and obstacle nails in the area 1100, various winning holes and bonuses cannot be touched.

[2. Overall structure of outer frame]
Next, the outer frame 2 installed in the island facility of the game hall will be described with reference to FIG. FIG. 4 is a front perspective view of the outer frame. As shown in FIG. 4, the outer frame 2 includes upper and lower upper and lower frame plates 10 and 11 that extend in the horizontal direction, left and right side frame plates 12 and 13 that extend in the vertical (vertical) direction, and respective frame plates. And four connecting members 14 that connect the end portions of 10, 11, 12, and 13 and connecting the frame plates 10, 11, 12, and 13 with the connecting member 14 to form a vertically long rectangular shape ( (Square shape). The upper frame plate 10 and the lower frame plate 11 in the outer frame 2 are formed of a solid material (for example, wood, plywood, etc.) having a predetermined thickness. Note that an upper support fitting 20 described later is attached to the upper surface and the front surface of the left end portion of the upper frame plate 10.

  On the other hand, the side frame plates 12 and 13 are light metal molds (for example, aluminum alloys) having a constant cross-sectional shape. In addition, a plurality of grooves extending in the vertical direction are formed on the outer side surface and the inner side surface of the side frame plates 12 and 13, and work is performed when the pachinko gaming machine 1 is installed in the pachinko island facility of the game hall. The pachinko gaming machine 1 can be easily held by a person's finger and the design of the appearance can be enhanced.

  The outer frame 2 is arranged so as to face the upper support fitting 20 fixed to the upper surface of the left end of the upper frame plate 10 and the lower support plate 20 and is fixed to a predetermined position inside the lower portion of the left side frame plate 12. A support bracket 21, a reinforcement bracket 22 arranged to support the lower surface of the lower support bracket 21 and fixed to connect the left and right side frame plates 12 and 13, and a decorative cover fixed to the front surface of the reinforcement bracket 22 23. The upper support fitting 20 and the lower support fitting 21 are for pivotally supporting the main body frame 3 and the door frame 5 so as to be opened and closed. A shaft support pin 633 (see FIG. 5) of an upper shaft support bracket 630 in the main body frame 3 to be described later is detachably engaged with the support hole 20c in the upper support bracket 20. A main body frame shaft support formed on a main body frame shaft support bracket 644 of the main body frame 3, which will be described later, is inserted into the support protrusion 21d of the lower support bracket 21. After the main body frame 3 is inserted into the support hole of the main body frame shaft support bracket 644, the main body frame 3 can be simply mounted by locking the shaft support pin 633 of the upper shaft support bracket 630 of the main body frame 3 in the support hole 20c. It can be pivotally supported so that it can be opened and closed.

  Further, the outer frame 2 has two closing plates 24 and 25 (see FIG. 1) attached and fixed inside the right side frame plate 13 with a predetermined distance apart in the vertical direction. These closing plates 24 and 25 are formed in a substantially L shape in plan view. The closing plates 24 and 25 are hook portions 1054 and 1065 (see FIG. 1) of a locking device 1000 (locking device) attached along the open side of the main body frame 3 when the main body frame 3 is closed with respect to the outer frame 2. As will be described in detail later, by inserting a key into the cylinder lock 1010 of the lock device 1000 and rotating it to one side, the hook portions 1054 and 1065 and the closing plates 24 and 25 are connected to each other. The engagement is released and the closed state of the main body frame 3 with respect to the outer frame 2 can be released.

[3. Overall structure of main frame]
Next, the main body frame 3 provided on the front side of the outer frame 2 so as to be freely opened and closed will be described with reference to FIGS. 5 and 6. FIG. 5 is a front perspective view of the main body frame, and FIG. 6 is a rear perspective view of the substrate unit in the main body frame. As shown in FIG. 5, the main body frame 3 forms a skeleton of the main body frame 3 and penetrates in the front-rear direction and has a main body frame base 600 having a rectangular game board holding port 601 for holding the game board 4. An upper shaft support bracket 630 and a lower shaft support bracket 640 that are respectively attached to the upper and lower ends of the left end of the main body frame base 600 and are pivotally supported by the outer frame 2 and pivotally support the door frame 5; A hitting device 650 for driving a game ball into a game area 1100 of the game board 4 attached to the lower front surface of the main body frame base 600, and a game to the upper plate 301 of the tray unit 300 attached to the rear side of the main body frame base 600. A prize ball unit 700 for paying out a ball, and when the door frame 5 is attached to the front surface of the main body frame base 600 and the door frame 5 is opened with respect to the main body frame 3, It includes a ball outlet opening and closing unit 790 to shut off the flow of skill sphere, the.

  The main body frame 3 is attached to the lower rear surface of the main body frame base 600, and includes various control boards and power supply boards 851 for controlling electrical components provided in the door frame 5 and the main body frame 3 except the game board 4. Are combined into a unit board unit 800, a back cover 900 that covers the rear opening of the game board holding port 601 in the main body frame base 600, and a side security plate 950 that covers the left end of the main body frame base 600 when viewed from the front. And a locking device 1000 that is attached to the right end portion of the main body frame base when viewed from the front and that locks the main body frame 3 with respect to the outer frame 2 and opens and closes the door frame 5 with respect to the main body frame 3.

[3-1. Body frame base]
Next, the main body frame base 600 will be described. The main body frame base 600 is integrally formed of a synthetic resin, and the outer shape in front view is a vertically long rectangular shape along the outer shape of the door frame 5, and is formed to have a predetermined amount of depth in the front-rear direction. Has been. The main body frame base 600 has a game board holding port 601 through which the inside of about 3/4 of the whole from the upper part to the lower part penetrates in a rectangular shape in the front-rear direction and can fit and hold the outer periphery of the game board 4, and the main body frame A U-shaped front end frame portion 602 that forms the outer periphery of the front end excluding the left side of the base 600 when viewed from the front, and is recessed backward from the front surface of the front end frame portion 602, and from the lower end of the door frame base body 110 in the door frame 5 to the rear. The protruding door frame protruding piece 110c (see FIG. 1), the upper bent protruding piece 167 (see FIG. 1) protruding to the rear of the upper reinforcing sheet metal 151 in the reinforcing unit 150 of the door frame 5, and the open side reinforcing sheet metal 153. And an engaging groove 603 into which an open-side outer bent protruding piece 164 (see FIG. 1) protruding rearward is inserted and engaged.

  Further, the main body frame base 600 extends from the lower side of the game board holding port 601 to the lower end of the main body frame base 600 and is recessed from the front end of the front end frame portion 602 to the rear side by a predetermined amount and spread in a plate shape in the left-right direction. 604 and a peripheral wall portion 605 that protrudes rearward inside the front end frame portion 602 and forms the inner peripheral wall of the game board holding port 601. The free end portions (upper and lower left end portions in front view) of the U-shaped front end frame portion 602 are connected to each other by the peripheral wall portion 605 so that the outer shape of the main body frame base 600 becomes a frame shape. It has become.

  In addition, the main body frame base 600 forms a lower side of the game board holding port 601 at the upper end of the lower rear wall part 604, and a game board placement part 606 on which the game board 4 is placed, and the game board placement part 606. A positioning protrusion 607 that protrudes upward from substantially the center in the left-right direction and engages with the out-ball discharge groove of the game panel 1150 in the game board 4, and is formed at a predetermined position on the right inner wall when viewed from the front in the peripheral wall portion 605. A game board locking portion to which the tool 1120 is fastened, and a plurality of upper end regulating ribs 609 arranged in the left-right direction in a plate shape that hangs downward from the upper inner wall of the peripheral wall portion 605 and whose lower ends can come into contact with the upper end of the game board 4 And. The positioning protrusion 607 of the main body frame base 600 can be engaged with the out-ball discharge groove of the game board 4 to restrict the lower end of the game board 4 from moving in the left-right direction and the rear direction. Yes. Further, the game board locking portion can restrict the right side of the game board 4 from moving in the front-rear direction when the game board stopper 1120 of the game board 4 is locked. . Although the details of the left side of the game board 4 when viewed from the front will be described later, movement in the front-rear direction is restricted by the positioning member 956 of the side security plate 950.

  In addition, the main body frame base 600 is formed at a position where the lower rear wall portion 604 is recessed one step further to the rear side than the front surface of the front end frame portion 602. The ball striking device 650 is attached from the front side so that the firing solenoid 654 of 650 is housed in the solenoid housing recess. In a state in which the ball hitting device 650 is attached to the front surface of the lower rear wall portion 604, a foul space 626 that extends leftward and downward is formed on the left side of the front view of the ball hitting device 650 from the upper end of the shot rail 660. It is like that. In the present embodiment, when the door frame 5 is closed with respect to the main body frame 3, the foul ball inlet 542e (see FIG. 1) in the foul cover unit 540 is positioned below the foul space 626. The game ball descending the foul space 626 is received by the foul ball inlet 542e of the foul cover unit 540 and discharged to the lower plate 302 (see FIG. 7) in the plate unit 300.

  Further, the main body frame base 600 is formed in a plurality of openings in a rectangular shape in the front-rear direction on the left side of the left and right center of the lower rear wall 604 in the front view, and a plurality of openings on the upper side of the opening and the left and right sides in the front view. And a through hole 615 penetrating the through hole. The opening portion of the main body frame base 600 is closed from the front side by a relay terminal plate cover 692, and the board unit attached to the rear surface of the lower rear wall portion 604 through the opening 692 a of the relay terminal plate cover 692. The 800 main door relay terminal plate 880 and the peripheral door relay terminal plate 882 face the front side.

  Further, the main body frame base 600 detects the opening of the door frame 5 with respect to the main body frame 3 on the lower front surface of the substantially circular cylinder lock through hole 611 penetrating in the front-rear direction at the upper right end of the lower rear wall 604 in front view. A door frame opening switch 618 is attached, and when the door frame 5 is opened (opened) with respect to the main body frame 3, the pressing is released and the opening of the door frame 5 can be detected. It is like that. Further, the main body frame base 600 is provided with a main body frame opening switch 619 for detecting the opening of the main body frame 3 with respect to the outer frame 2 on the lower rear surface from the position where the door frame opening switch 618 is attached. When the main body frame 3 is opened (opened) with respect to the outer frame 2, the pressing is released and the opening of the main body frame 3 can be detected.

[3-2. Upper shaft support bracket and lower shaft support bracket]
Next, the upper shaft bracket 630 and the lower shaft bracket 640 will be described. The upper shaft bracket 630 and the lower shaft bracket 640 are respectively attached to the bracket mounting portions on the upper left and lower rear ends of the main body frame base 600 using a predetermined screw to attach the door frame 5 to the main body frame 3. The main frame 3 can be pivotally supported with respect to the outer frame 2 so as to be openable and closable.

  The upper shaft support bracket 630 is attached to the upper bracket attachment portion of the main body frame base 600 and has a plate-like attachment portion 631 extending in the vertical and horizontal directions, and a plate-like front extension extending forward from the upper end of the attachment portion 631. Portion 632, a shaft support pin 633 projecting upward from the vicinity of the front end of the front extension portion 632, and a shaft pin 155 of the door frame 5 disposed on the left side of the shaft support pin 633 in front view (FIG. 7). And the door frame shaft support hole 634 penetrating in the up-down direction, and the front end of the front extension 632 hangs downward from the front end and restricts the rotation end of the door frame 5 toward the open side. And a stopper. In the upper shaft support 630, the attachment portion 631, the front extension portion 632, and the stopper are integrally formed by bending a single metal plate.

  The lower shaft support bracket 640 is disposed below the door frame shaft support bracket 642 for supporting the door frame 5 and supports the main body frame 3 with respect to the outer frame 2. The main body frame shaft support bracket 644 is provided. The door frame shaft support bracket 642 in the lower shaft support bracket 640 is attached to the lower bracket mounting portion of the main body frame base 600 and extends forward from the lower end of the mounting portion. A plate-like front extension 642b, a door frame shaft support hole 642c through which a shaft pin 157 (see FIG. 7) of the door frame 5 is inserted in the vertical direction near the front end of the front extension 642b, and the front And a stopper 642d that is erected upward from the left end portion of the extension portion 642b when viewed from the front and restricts the rotation end of the door frame 5 toward the open side. The door frame shaft support 642 is integrally formed with a mounting portion, a front extension 642b, and a stopper 642d by bending a single metal plate.

  Further, the main body frame shaft support bracket 644 in the lower shaft support bracket 640 is attached to the lower bracket attachment portion of the main body frame base 600 and extends forward and downward from the lower end of the attachment portion. A front extending portion 644b that protrudes and a main body frame pivot support hole that penetrates in the vertical direction in the vicinity of the front end of the front extending portion 644b are provided. The main body frame shaft support 644 is also integrally formed with an attachment portion and a front extension portion 644b by bending a single metal plate.

  The lower shaft bracket 640 is in a state where the mounting portion of the door frame shaft bracket 642 and the mounting portion of the main body frame shaft bracket 644 are overlapped (contacted) in the front-rear direction. The front extension part 642b and the front extension part 644b of the main body frame shaft support metal 644 are attached to the lower metal attachment part of the main body frame base 600 in a state of being separated by a predetermined distance in the vertical direction.

  The upper shaft support 630 and the lower shaft support 640 are attached to the main body frame base 600, and the shaft support pin 633 of the upper shaft support 630 and the main body frame shaft support hole of the lower shaft support 640 are coaxial. The body frame shaft support hole of the body frame shaft support bracket 644 in the lower shaft support bracket 640 is fitted to the support protrusion 21d (see FIG. 4) of the lower support bracket 21 in the outer frame 2. The front extension portion 644b of the main body frame shaft support bracket 644 is placed on the support protruding piece 21c (see FIG. 4) of the lower support bracket 21, so that the shaft of the upper shaft support bracket 630 is inserted. By inserting the support pin 633 into the support hole 20c (see FIG. 4) of the upper support fitting 20 in the outer frame 2, the main body frame 3 can be pivotally supported with respect to the outer frame 2 so as to be opened and closed. It is like that.

  Further, the upper shaft support bracket 630 and the lower shaft support bracket 640 are attached to the main body frame base 600, and the door frame shaft support hole 634 of the upper shaft support bracket 630 and the door frame shaft support hole of the lower shaft support bracket 640. 642c is positioned coaxially with the door frame so that the shaft pin 157 of the door frame 5 is inserted into the door frame shaft support hole 642c of the door frame shaft support bracket 642 in the lower shaft support bracket 640. 5 is mounted on the front extension 642b of the door frame shaft bracket 642, and the shaft pin 155 of the door frame 5 is placed on the door frame of the upper shaft bracket 630. The door frame 5 can be pivotally supported with respect to the main body frame 3 so as to be openable and closable by being inserted into the pivotal support hole 634. In the present embodiment, the shaft pin 155 on the upper side of the door frame 5 is slidable in the vertical direction. When the shaft pin 155 is inserted into the door frame shaft support hole 634 of the upper shaft support 630, the shaft pin 155 is inserted. Is once slid downward so that the upper shaft support portion 156 of the door frame 5 and the front extension portion 632 of the upper shaft support fitting 630 overlap vertically, and then the shaft pin 155 is slid upward. It can be inserted into the door frame shaft support hole 634.

[3-3. Hitting ball launcher]
Next, the hit ball launching device 650 will be described. The hitting ball launching device 650 is mounted so that the metal plate launch base 652 is mounted at a predetermined position on the front surface of the lower rear wall portion 604 in the main body frame base 600, and the rotary drive shaft 654a projects forward from the lower rear surface of the launch base 652. Firing solenoid 654, a hitting ball 656 fixed to the rotation drive shaft 654a of the firing solenoid 654 so as to be integrally rotatable, a tip 658 fixed to the tip of the hitting ball 656, and a predetermined movement path of the tip 658 A firing rail 660 extending diagonally to the upper left when viewed from the front and attached to the front surface of the firing base 652, and a tip 658 at the tip of the hitting ball 656 passes between the firing rail 660 and the top of the firing rail 660. A ball stopper that holds the game ball at the base end of the launch rail 660 by forming a gap through which the game ball cannot pass at the same time. 662 and a stopper for restricting the ball hitting ball 656 (tip 658) from rotating toward the shooting rail 660 from the hitting position where the game ball held at the base end of the shooting rail 660 by the ball stopper piece 662 can be hit. 664.

  The firing solenoid 654 in the hitting ball launching device 650 is not shown in detail, but the rotational drive shaft 654a reciprocates at a strength (speed) corresponding to the rotational operation angle of the handle device 500. . Further, the hitting ball basket 656 of the hitting ball launching device 650 has a fixed portion 656a fixed to the rotation drive shaft 654a of the launch solenoid 654, and a gentle arc extending from the fixed portion 656a, and the tip is centered on the rotation drive shaft 654a. On the other hand, a hook portion 656b with the hook tip 658 fixed to the tip at a normal direction, a stopper portion 656c extending to the opposite side of the hook portion 656b with the fixing portion 656a interposed therebetween, and a stopper portion 656c capable of contacting the stopper 664 It has. When the stopper portion 656c of the hitting ball basket 656 is in contact with the stopper 664, the tip of the tip 658 is rotated to the firing rail 660 side from the hitting position (the rotation end in the counterclockwise direction when viewed from the front). Being regulated.

  When the hitting ball launcher 650 is attached to the lower rear wall portion 604 of the main body frame base 600, the upper end of the firing rail 660 is substantially the center in the left-right direction, that is, the upper end of the lower rear wall portion 604, that is, the game board mounting portion. 606 (the lower side of the game board holding port 601) is located below and has a predetermined width in the left-right direction between the lower end of the outer rail 1111 in the game board 4 held by the game board holding port 601. Thus, a foul space 626 extending downward is formed. The hit ball launching device 650 can hit the game ball into the game area 1100 of the game board 4 by firing the game ball so as to jump over the foul space 626 on the left side of the front view from the launch rail 660. It has become. In a state where the door frame 5 is closed with respect to the main body frame 3, the foul ball inlet 542e of the foul cover unit 540 attached to the door frame 5 is positioned below the foul space 626. A game ball that has become a foul ball without being driven into the area 1100 falls in the foul space 626, is received by the foul ball inlet 542 e, and is discharged to the lower plate 302.

[3-4. Prize ball unit]
Next, the prize ball unit 700 will be described. In the pachinko island facility in the hall where the pachinko gaming machine 1 is installed, the game balls supplied from the pachinko island facility side to the pachinko gaming machine 1 are stored, and the upper plate 301 of the pachinko gaming machine 1 is based on a predetermined payout instruction. To pay out. The prize ball unit 700 has a prize ball base 710 attached to the rear surface of the main body frame base 600 and a prize ball tank attached to the upper rear surface of the prize ball base 710 and receiving and storing game balls supplied from the Pachinko island equipment side. 720, a tank rail unit 730 arranged below the prize ball tank 720 and arranged to send the game balls stored in the prize ball tank 720 to the downstream side, and the game balls arranged by the tank rail unit 730 The prize ball device 740 to be paid out based on the payout instruction, and the game balls paid out by the prize ball device 740 can be guided to the upper plate 301 of the tray unit and are paid out when the upper plate 301 is full of game balls. And a full tank branching unit 770 capable of branching and guiding the game ball to the lower plate 302 side.

  The prize ball unit 700 includes an external terminal board 784 attached to the rear surface of the prize ball base 710 and an external terminal board cover 786 that covers the rear side of the external terminal board 784.

[3-4-1. Prize ball tank]
In the prize ball tank 720, the outer periphery of the bottom wall portion 721 is surrounded by an outer peripheral wall portion 722, and a predetermined amount of game balls can be stored on the bottom wall portion 721. The prize ball tank 720 is inclined so that the upper surface of the bottom wall portion 721 is lowered toward the discharge port 723 so that the game ball on the bottom wall portion 721 rolls toward the discharge port 723. It has become.

  The prize ball tank 720 includes two ball leveling members 727 that are pivotally supported by the shaft portion 725. One end side of the ball leveling member 727 is pivotally supported by the shaft portion 725 and holds a weight inside, and the other end side is suspended by its own weight. The ball leveling member 727 hangs down in a tank rail unit 730, which will be described later, so that game balls circulating in the tank rail unit 730 can be leveled and aligned.

[3-4-2. Tank rail unit]
The tank rail unit 730 includes a tank rail 731 disposed below the prize ball tank 720 and extending long in the left-right direction. The tank rail 731 has a bowl shape with a predetermined depth with the upper part open, and has a width (depth) in which the game balls can be aligned in two lines in the front-rear direction. The bottom is inclined so as to be low.

  The tank rail unit 730 is connected to the alignment gear 732 rotatably supported on the upper portion of the discharge port of the tank rail 731, the gear cover 733 covering the upper portion of the alignment gear 732, and the right end of the gear cover 733 as viewed from the front, A ball retainer plate 734 that closes the upper portion of the rail 731; a ball stop piece 735 that can move forward and backward in the tank rail 731 and stop the game ball in the tank rail 731 from rolling toward the outlet; It is equipped with. Two alignment gears 732 are provided side by side in the front-rear direction so as to correspond to the two flow paths of the game balls partitioned in two rows by the partition wall of the tank rail 731.

[3-4-3. Prize ball device]
The prize ball device 740 is for paying out the game balls discharged and supplied from the discharge port of the tank rail unit 730 to the upper plate 301 of the plate unit 300 based on a predetermined payout instruction. The prize ball device 740 has a predetermined width that communicates with a supply passage that opens to the upper end and extends to a position slightly lower than the center in the vertical direction with a width that is slightly wider than the outer shape of the game ball. A distribution space having a space, a prize ball passage that opens into the left side of the rear view when bent in a substantially square shape and communicates with the lower left side (open side) of the rear side of the distribution space, and the right side of the rear side of the distribution space (Axis support side) A ball passage that communicates with the lower end and extends downward and opens at the lower end. The supply passage, the distribution space, the prize ball passage, and the ball removal passage are formed in a state opened rearward.

  The prize ball device 740 is meshed with the first gear fixed to the rotating shaft of the payout motor 744 and disposed behind the motor support plate, the second gear meshing with the first gear, and the second gear. The third gear that rotates together with the third gear and the dispensing rotator as a sprocket disposed in the distribution space and the dispensing rotator are fixed to the opposite side so as to be integrally rotatable with the third gear interposed therebetween. A rotation detecting board having a plurality of (three in the present embodiment) detection slits formed at equal intervals in the direction, and a ball break switch 750 for detecting the presence or absence of a game ball in the supply passage; A counting switch 751 for detecting a game ball flowing down in the prize ball passage, a rotation angle switch 752 for detecting a detection slit formed in a rotation detection board that rotates integrally with the payout rotating body, and a rotation angle switch 752 Hold A rotational angle switch substrate 753 includes payout motor 744, burn out switch 750, a counting switch 751, and the rotation angle prize balls casing substrate 754 that relays the connection between dispensing the below-described control board and the switch 752, the.

  The payout rotator as a sprocket has three recesses each having a size capable of accommodating one game ball at equal intervals in the circumferential direction. The balls are accommodated in the recesses one by one, and can be paid out to the prize ball passage or the ball removal passage side. Further, the three detection slits formed on the rotation detecting board that rotates integrally with the payout rotating body are equally formed (every 120 degrees) on the outer periphery of the rotation detecting board, and correspond to between the recesses of the payout rotating body. The rotation position of the payout rotating body can be detected by detecting the detection slit with the rotation angle switch 752. In the present embodiment, the rotation between the detection slits (120 degrees) of the rotation detection board (dispensing rotary body) is designed to correspond to the 18-step rotation of the dispensing motor 744.

  The award ball device 740 is configured such that when the payout rotating body is rotated counterclockwise by the payout motor 744, the game ball in the supply passage is paid out to the award ball passage. The game balls paid out to the prize ball passage by the rotation of the body are counted by the counting switch 751 one by one and then delivered to the prize ball passage. On the other hand, when the ball removal operation member is operated by a hall clerk or the like, the game balls in the supply passage are paid out to the ball removal passage. The pachinko gaming machine 1 can be discharged from the lower end of the passage to the rear outside of the pachinko gaming machine 1 through a full tank branching unit 770 described later.

[3-4-4. Full tank branch unit]
The full tank branching unit 770 is formed in a box shape that becomes lower as it goes from the rear end to the front end. A prize ball receiving hole for a game ball flowing down the ball passage, a branching space that is arranged below the prize ball receiving hole and extends in the left-right direction, and a game from directly under the prize ball receiving hole in the branching space to the front side A normal path for guiding the ball, a normal ball outlet 774 that releases the game ball flowing through the normal path to the front and opened at the front right end of the front view, and the right side in the rear view rather than just below the prize ball receiving opening in the branch space A full tank passage that guides the game ball from the raised position to the front side, and a full ball exit 776 that discharges the game ball that has circulated through the full tank passage to the front and opens to the left in front of the normal ball outlet 774. ing.

  In addition, the full tank branching unit 770 includes a ball receiving port that receives a game ball that opens upward at the left end portion of the rear end upper portion when viewed from the front and flows down the ball passage of the prize ball device 740, and a ball receiving portion. A ball passage that guides the game ball received in the mouth to the front side, and a game ball that has circulated through the ball passage is released forward and at the left end of the front view at a position behind the normal ball outlet 774 and the full ball exit 776 And an open ball outlet.

  When the full tank branching unit 770 is in a state in which the door frame 5 is closed with respect to the main body frame 3, the normal ball outlet 774 and the full tank outlet 776 are respectively connected to the first ball inlet 542 a of the foul cover unit 540 in the door frame 5. And the second ball inlet 542c (see FIG. 1) and communicates with each other, and the game ball released from the normal ball outlet 774 passes through the first ball inlet 542a of the foul cover unit 540, The game balls supplied to the upper plate 301 of the unit 300 and released from the full ball outlet 776 are supplied to the lower plate 302 of the plate unit 300 through the second ball inlet 542c of the foul cover unit 540. ing. The ball outlet is formed so as to communicate with the upper right side upper end of the main body frame base ball passage in the main body frame base 600, and the game ball discharged from the ball outlet is the main body frame of the main body frame base 600. It is to be delivered to the base ball passage.

  When a game ball is further paid out from the prize ball unit 700 (prize ball device 740) in a state where the upper plate 301 of the dish unit 300 is full of game balls, the upper ball ball is raised from the first ball exit of the foul cover unit 540. The game balls that can no longer come out to the side of the tray 301 stagnate in the first ball passage of the foul cover unit 540, and eventually fill up the normal passage upstream through the normal ball outlet 774 in the full tank branching unit 770. In this state, the game ball that has entered the branch space from the prize ball receiving port cannot normally enter the passage, and starts moving in the lateral direction in the branch space, and the game ball that has moved in the horizontal direction is full. So as to enter the tongue passage and be supplied from the full bulb exit to the lower plate 302 of the dish unit 300 through the second bulb inlet 542c, the second bulb passage, and the second bulb outlet of the foul cover unit 540. It has become.

[3-5. Substrate unit]
Next, the substrate unit 800 will be described. As shown in FIG. 6, the substrate unit 800 includes a substrate unit base 810 attached to the rear surface of the lower rear wall portion of the main body frame base 600, a speaker box 820 attached to the rear left side of the substrate unit base 810, and a substrate. A power supply board box holder 840 attached to the rear face of the unit base 810, and a power supply board box attached to the rear face of the power supply board box holder 840 and having a rear end substantially flush with the rear end of the speaker box 820 850, a payout control board box 860 attached to the rear surfaces of the power supply board box 850 and the speaker box 820, and a terminal board box 870 attached to the rear face of the speaker box 820 so as to cover the left end of the payout control board box 860 when viewed from the front. And board unit base A main door relay terminal plate 880 and the peripheral door relay terminal plate 882 is attached to the front surface 10, and a.

  The power supply board box holder 840 has a discharge ball receiving portion 841 that receives a game ball that is opened upward and discharged from the out ball discharge portion of the game board 4 downward from the left and right front in front view, A discharge passage 842 that guides and discharges the game ball received by the discharge ball receiving portion 841 downward and the front of the discharge passage 842 and the side of the discharge ball receiving portion 841 (right side in front view) is opened forward and upward. A power supply board box holder 840 having a box housing portion that is formed so that the entire rear surface of the power board box holder 840 is recessed to the front side and can accommodate the front end of the power board board box 850.

  The power supply board box holder 840 is configured such that the open front end side of the discharge passage 842 is closed by the rear surface of the substrate unit base 810 and the opening of the substrate unit base 810 faces the discharge passage 842. The main body frame base 600 is circulated through the main body frame base ball passage formed on the rear surface of the lower rear wall portion of the main body frame base 600 and flows down to the rear side of the substrate unit base 810 through the opening of the substrate unit base 810. The game ball and the game ball discharged from the out ball discharge portion of the game board 4 and received by the discharge ball receiving portion 841 can be discharged to the lower rear side of the pachinko gaming machine 1 through the discharge passage 842. It has become.

  The power supply board box 850 is formed in a horizontally long box shape with the front open, and includes a power supply board 851 attached so as to close the front end opening. The power supply board box 850 accommodates various electronic components attached to the power supply board 851, and externally transfers heat from the electronic parts and the like through a plurality of slits 850a formed on the upper surface and the lower surface. Can be released. A power switch 852 attached to the power board 851 faces the rear surface of the power board box 850.

  The payout control board box 860 includes a thin box-shaped box base 861 that is horizontally long and opened rearward, a thin box-shaped cover 862 that is fitted into the box base 861 from the rear side and opened front, and a box base 861. And a payout control board 4110 attached to the rear surface and covered by the cover 862. Further, the payout control board box 860 includes a plurality of separation cutting portions 863 that protrude outward from the left end in the rear view and are formed on both the box base 861 and the cover 862, and are provided at one location of the plurality of separation cutting portions 863. The box base 861 and the cover 862 are fixed by caulking. Thus, in order to separate the box base 861 and the cover 862, the separation and cutting portion 863 must be cut so that the box base 861 and the cover 862 cannot be separated. When the dispensing control board box 860 is opened, the trace remains. . Therefore, it can be determined whether or not the dispensing control board box 860 has been opened and closed illegally. In the present embodiment, the payout control board box 860 can be opened and closed only once for inspection or the like.

  Further, the payout control board box 860 is configured such that an operation switch 860a (error release unit) attached to the payout control board 4110, an inspection output terminal 860c, and the like face rearward through the cover 862. The payout control board box 860 has various connection terminals for connecting to the main control board 4100 and the like facing rearward through the cover 862. The operation switch 860a is operated when clearing the RAM built in the microprocessor of the payout control board 4110 and the RAM built in the microprocessor of the main control board 4100 when the power is turned on, or after the power is turned on. When an error is reported, it is operated to cancel the error, and the RAM clearing function at power-on and the power-on (time period for functioning as RAM clearing have elapsed) And a function of canceling an error in (after). A detailed description of this point will be described later.

  The terminal board box 870 includes a board base 871 attached to the rear face of the speaker box 820, a frame peripheral relay terminal board 868 attached to the rear face of the board base 871 and fixed with a peripheral panel relay terminal 872 toward the rear, and a board base. A board for lending device connection terminal plate 869 such as a game ball attached to the rear surface of 871 and having CR unit relay terminal 873 fixed to the rear, so that peripheral panel relay terminal 872 and CR unit relay terminal 873 face the rear side. And a substrate cover 874 that covers the rear side of the base 871. The peripheral panel relay terminal 872 is for connecting to a frequency indicator for displaying the operating state of the pachinko gaming machine 1 provided on the pachinko island facility side where the pachinko gaming machine 1 is installed. The terminal 873 is for connection with a CR unit installed adjacent to the pachinko gaming machine 1.

  The main door relay terminal plate 880 and the peripheral door relay terminal plate 882 are provided in the door frame 5, the peripheral control board 4140 provided in the game board 4 attached to the main body frame 3, the payout control board 4110 of the board unit 800, and the like. This is for relaying connections to the handle device 500, various substrates, the operation unit 400, and the like. The main door relay terminal plate 880 and the peripheral door relay terminal plate 882 are attached to the board mounting portion formed on the front surface of the board unit base 810 so as to face the front side of the main body frame base 600, Wiring extending from the door frame 5 can be connected.

  The main door relay terminal plate 880 and the peripheral door relay terminal plate 882 are covered with a relay terminal plate cover 692 attached to the front surface of the main body frame base 600, and the front side of the relay terminal plate cover 692 is also covered. Only the connection terminal faces the front side through the opening 692a, so that the front surface of the main body frame 3 has a clean appearance.

  Further, the main door relay terminal plate 880 includes a ball rental button 361, a return button 362, a remaining rental display portion 363, a potentiometer 512 of the handle device 500, and a touch in the tray unit 300 arranged on the door frame 5 side. This is for relaying the connection between the switch 516, the firing stop switch 518, and the full tank switch 550 of the foul cover unit 540 and the payout control board 4110 disposed on the main body frame 3 side. It should be noted that the ball rental button 361, the return button 362, the remaining rental display unit 363, the potentiometer 512 of the handle device 500, the touch switch 516, the firing stop switch 518, and the full switch 550 of the foul cover unit 540 are provided. The description will be described later.

  Further, the peripheral door relay terminal plate 882 is provided on each decorative board (hereinafter referred to as “the door frame 5”) provided in each of the decorative units 200, 240, 280, the dish unit 300, and the operation unit 400 disposed on the door frame 5 side. May be referred to as “a plurality of frame-side decorative boards”), and the operation of the dial drive motor 414 provided in the operation unit 400 and the operation of the dial operation unit 401 and the pressing operation unit 405 provided in the operation unit 400 are detected. This relay relays the connection between the various switches and the peripheral control board 4140 of the game board 4 arranged on the main body frame 3 side. The decorative units 200, 240, and 280 arranged on the door frame 5 side, the dish unit 300, a plurality of frame-side decorative boards provided in the operation unit 400, the dial drive motor 414 provided in the operation unit 400, A description will be given later of various switches that detect the operation of the dial operation unit 401 and the pressing operation unit 405 provided in the operation unit 400.

[4. Overall structure of door frame]
Next, the door frame 5 that can be freely opened and closed on the front side of the main body frame 3 will be described with reference to FIG. FIG. 7 is a perspective view of the door frame. As shown in FIG. 7, the door frame 5 includes a door frame base unit 100 having a gaming window 101 whose outer shape is formed in a vertically long rectangular shape and whose inner peripheral shape is a slightly vertically long circular shape (elliptical shape), A right side decoration unit 200 attached to the right outer periphery of the gaming window 101 on the front surface of the frame base unit 100, and a left side facing the right side decoration unit 200 and attached to the left outer periphery of the gaming window 101 on the front surface of the door frame base unit 100. The decoration unit 240, the upper decoration unit 280 attached to the upper outer periphery of the gaming window 101 in front of the door frame base unit 100, and the door frame base unit disposed below the lower ends of the right side decoration unit 200 and the left side decoration unit 240. And a pair of speaker covers 290 attached to the front surface of 100.

  The door frame 5 is attached to the front side of the door frame base unit 100 at the lower part of the gaming window 101, the operation unit 400 attached to the upper center of the dish unit 300, and the right side of the dish unit 300. A handle device 500 that is attached to the lower right corner portion of the door frame base unit 100 through the upper plate side liquid crystal display device 470 and the tray unit 300, and a door frame base unit 100. A foul cover unit 540 that is disposed on the rear side of the dish unit 300 and is attached to the rear surface of the door frame base unit 100, and a ball feeding unit 580 that is attached to the rear surface of the door frame base unit 100 on the right side of the foul cover unit 540 (see FIG. 1) and the gaming window 101 closed on the rear side of the door frame base unit 100 The glass unit 590 mounted for, and a.

[4-1. Door frame base unit]
Next, the door frame base unit 100 will be described. The door frame base unit 100 has a door frame base main body 110 having a gaming window 101 having an outer shape formed in a vertically long rectangular shape and penetrating in the front-rear direction and having an inner periphery formed in a substantially elliptical shape. An upper bracket 120 that is attached to the upper center of the gaming window 101 on the front surface of the base body 110 and fixes the upper decoration unit, and a pair of speakers that are attached to the lower left and right outer sides of the gaming window 101 on the front surface of the door frame base body 110. 130 and a handle bracket that is attached to the lower right corner in front view on the front surface of the door frame base main body 110 and supports the handle device 500.

  The door frame base unit 100 includes a metal frame-shaped reinforcing unit 150 (see FIG. 1) fixed to the rear side of the door frame base main body 110, and the gaming window 101 on the rear surface of the door frame base main body 110. A security cover 180 (see FIG. 1) attached so as to cover the lower part, and a glass unit locking member 190 (see FIG. 1) attached to a predetermined position on the outer periphery of the gaming window 101 on the rear surface of the door frame base body 110. 1), and a launch cover 191 (see FIG. 1) that is disposed on the left side (open side) from the center in the left-right direction in a rear view and is attached to the rear surface of the door frame base body 110 along the lower end of the game window 101. A main control board mounted on the rear surface of the door frame base body 110 below the launch cover 191 and provided in a potentiometer 512 of the handle device 500 described later and a game board 4 described later. A handle relay terminal plate 192 (see FIG. 1) that relays the connection to the 100, a handle relay terminal plate cover 193 (see FIG. 1) that covers the rear side of the handle relay terminal plate 192, and a center in the left-right direction. A frame decoration drive amplifier board 194 that is disposed on the opposite side to the launch cover 191 and the handle relay terminal plate 192 (on the right side (axial support side) from the center in the left-right direction in rear view) and attached to the rear surface of the door frame base body. (See FIG. 1) and a frame decoration drive amplifier board cover 195 (see FIG. 1) covering the rear side of the frame decoration drive amplifier board 194.

  The frame decoration drive amplifier board 194 is electrically connected to the speaker 130 and is electrically connected to a plurality of frame side decoration boards provided in each of the decoration units 200, 240, 280, the dish unit 300, and the operation unit 400. It is connected. The frame decoration drive amplifier board 194 is electrically connected to a peripheral control board 4140 provided in the game board 4 to be described later, and amplifies an acoustic signal sent from the peripheral control board 4140 and outputs it to each speaker 130. In addition to the amplifier circuit, various LED controls for driving a plurality of LEDs as decoration LEDs provided on a plurality of frame side decorative boards provided in the decoration units 200, 240, 280, the dish unit 300, and the operation unit 400. It has a circuit. Although not specifically illustrated, in this embodiment, the frame decoration drive amplifier board 194, the dial drive motor and switch provided in the operation unit 400, the handle relay terminal plate 192, and the ball rental unit 360 of the dish unit 300. , And the payout control board 4110, the peripheral control board 4140, and the like are bundled together at the right side (axial support side) position in the rear view of the frame decoration drive amplifier board 194. It extends rearward and is connected to the main door relay terminal plate 880 and the peripheral door relay terminal plate 882 of the main body frame 3.

  Here, each decoration unit 200,240,280 is demonstrated easily. As described above, each of the decoration units 200, 240, and 280 includes a plurality of frame-side decoration substrates. The frame side decorative board is directly connected to a frame side peripheral control MPU control target decorative board that is a control target directly controlled by the peripheral control MPU of the peripheral control board 4140 described later and a sound source built-in VDP of the peripheral control board 4140 described later. There is a frame-side VDP control target decorative board that is a control target to be controlled.

  The right side decoration unit 200 has a right side VDP control target first light-decorated by a plurality of LEDs (decorative LEDs) provided on the frame side VDP control target decoration boards RV1 to RV3 from the lower side to the upper side. The light emission decoration area RTV1 to the right side VDP control target third light emission decoration area RTV3 are formed and arranged between the right side VDP control target first light emission decoration area RTV1 and the right side VDP control target second light emission decoration area RTV2. The plurality of LEDs (decoration) provided on the frame side peripheral control MPU control target decoration board RM1 that are spaced apart from the right side VDP control target first light emission decoration area RTV1 and the right side VDP control target second light emission decoration area RTV2 by a predetermined distance. Right side peripheral control MPU control target first light emitting decoration area RTM1 decorated with light emitting LED), and right side The right side VDP control target second light emission decoration area RTV2 and the right side VDP control target third light emission decoration area RTV3 disposed between the VDP control target second light emission decoration area RTV2 and the right side VDP control target third light emission decoration area RTV3. A right side peripheral control MPU control target second light emitting decoration area RTM2 that is light-decorated by a plurality of LEDs (decorative LEDs) provided on the frame side peripheral control MPU control target decorative board RM2 that is spaced apart from the RTV 3 by a predetermined distance; Right side peripheral control MPU control that is light-decorated by a plurality of LEDs (decorative LEDs) provided on the frame-side peripheral control MPU control target decorative board RM3, which is arranged near the upper side of the third VDP control target third light-emitting decorative region RTV3. A target third light emitting decoration region RTM3 is formed.

  The left side decoration unit 240 has a left side VDP control target first light-decorated by a plurality of LEDs (decorative LEDs) respectively provided on the frame side VDP control target decoration boards LV1 to LV3 from the lower side to the upper side. The light emission decoration area LTV1 to the left side VDP control target third light emission decoration area LTV3 are formed and arranged between the left side VDP control target first light emission decoration area LTV1 and the left side VDP control target second light emission decoration area LTV2. A plurality of LEDs (decoration) provided on the frame side peripheral control MPU control target decoration board LM1 that separate the left side VDP control target first light emission decoration area LTV1 and the left side VDP control target second light emission decoration area LTV2 by a predetermined distance. Left side peripheral control MPU control target first light emission decoration area LTM1 decorated with light emission by LED), and left side The left side VDP control target second light emission decoration area LTV2 and the left side VDP control target third light emission decoration area LTV3 disposed between the VDP control target second light emission decoration area LTV2 and the left side VDP control target third light emission decoration area LTV3. A left side peripheral control MPU control target second light emitting decoration area LTM2 that is light-decorated by a plurality of LEDs (decorative LEDs) provided on the frame side peripheral control MPU control target decorative board LM2 and spaced apart from the LTV 3 by a predetermined distance; Left side peripheral control MPU control that is light-decorated by a plurality of LEDs (decorative LEDs) provided on the frame-side peripheral control MPU control target decorative board LM3, which is disposed near the upper side of the third VDP control target third light-emitting decorative region LTV3. A target third light emitting decoration region LTM3 is formed.

  The upper decoration unit 280 has a right side VDP control target fourth light emission decoration region that is decorated with a plurality of LEDs (decoration LEDs) provided on the frame side VDP control target decoration board RV4 from the lower right side to the upper side. While the RTV 4 is formed, a plurality of LEDs (decorative LEDs) provided on the frame-side peripheral control MPU control target decorative board RM4, which are arranged near the upper side of the right side VDP control target fourth light emission decorative region RTV4 The right side periphery control MPU control target fourth light emission decoration region RTM4 is formed. Further, the upper decoration unit 280 has a left side VDP control target fourth light emission decoration area that is decorated with light emission by a plurality of LEDs (decoration LEDs) provided on the frame side VDP control target decoration board LV4 from the lower left side to the upper side. The LTV 4 is formed, and a plurality of LEDs (decorative LEDs) provided on the frame side peripheral control MPU control target decorative board LM4, which are disposed in the vicinity of the upper part of the left side VDP control target fourth light emission decorative region LTV4 The left side peripheral control MPU control target fourth light emission decoration area LTM4 is formed. Note that the left side VDP control target fourth light emission decoration area LTV4 and the right side VDP control target fourth light emission decoration area RTV4 are arranged in a pair of left and right, and the left side peripheral control MPU control target fourth light emission decoration area LTM4 and the right side. The side periphery control MPU control target fourth light emission decoration region RTM4 is arranged in a pair on the left and right.

  In a state where the decoration units 200, 240, and 280 are attached to the door frame base unit 100, the right side VDP control target third light emission decoration region RTV 3 and the upper decoration unit 280 are formed in the right side decoration unit 200. A right side peripheral control MPU control target third light emission decoration region RTM3 formed in the right side decoration unit 200 is disposed between the right side VDP control target fourth light emission decoration region RTV4 and the right side VDP control target fourth light emission decoration region RTV4. The three-light-emitting decoration area RTV3 and the right-side VDP control target fourth light-emitting decoration area RTV4 are spaced apart by a predetermined distance, and the left-side VDP control target third light-emitting decoration area LTV3 and the upper decoration unit formed in the left-side decoration unit 240 Left side VDP control target fourth light emission decoration area LTV formed in 280 The left side peripheral control MPU control target third light emission decoration region LTM3 formed in the left side decoration unit 240 is disposed between the left side VDP control target third light emission decoration region LTV3 and the left side VDP control target The four light emitting decoration area LTV4 is spaced apart by a predetermined distance.

  In the state where the decoration units 200 and 240 are attached to the door frame base unit 100, the left side VDP control target first light emission decoration region LTV1 to the left side VDP control target third formed on the left side decoration unit 240. The light emission decoration area LTV3 and the right side VDP control target first light emission decoration area RTV1 to the right side VDP control target third light emission decoration area RTV3 formed in the right side decoration unit 200 are arranged in a pair of left and right, and left Left side periphery control MPU control target first light emission decoration area LTM1 to left side periphery control MPU control target third light emission decoration area LTM3 formed in the side decoration unit 240 and right side periphery control formed in the right side decoration unit 200 MPU control target first light emission decoration region RTM1-right side periphery control MPU system Target third light emitting decorative region RTM3, it is arranged in a left-right pair.

  Frame side VDP control target decoration boards RV1 to RV3 of the right side decoration unit 200, frame side VDP control target decoration boards LV1 to LV3 of the left side decoration unit 240, frame side VDP control target decoration boards RV4 of the upper decoration unit 280, and the frame side The resist color on the surface (mounting surface) on which a plurality of LEDs (decorative LEDs) are provided on each of the decorative substrates LV4 for VDP control and the resist color on the back surface are black. In addition, the mounting surfaces of the frame side VDP control target decorative boards RV1 to RV4 and the frame side VDP control target decorative boards LV1 to LV4 are rectangular openings at positions corresponding to the plurality of LEDs (decorative LEDs) provided respectively. A grid-like black partition plate in which (square-shaped openings) are formed is placed as a spacer, and is covered by a resin cover body to which a design is applied. In other words, the frame-side VDP control target decorative boards RV1 to RV4 and the frame-side VDP control target decorative boards LV1 to LV4 between the mounting surface and the cover body, the frame-side VDP control target decorative boards RV1 to RV4, and the frame Lattice-like black partition plates having rectangular openings formed at positions corresponding to the plurality of LEDs (decorative LEDs) provided on the mounting surfaces of the side VDP control target decorative boards LV1 to LV4, respectively, are sandwiched as spacers. It has a structured.

  In the state in which the partition plate is sandwiched between the mounting surface of the frame side VDP control target decorative substrates RV1 to RV4 and the frame side VDP control target decorative substrates LV1 to LV4 and the cover body, a rectangular shape formed on the partition plate A plurality of LEDs (decorative LEDs) respectively provided on the mounting surfaces of the frame side VDP control target decorative boards RV1 to RV4 and the frame side VDP control target decorative boards LV1 to LV4, corresponding to the openings of In addition, the rear side of the partition plate (that is, the mounting side of the frame side VDP control target decorative boards RV1 to RV4 and the frame side VDP control target decorative boards LV1 to LV4) and the frame side VDP control target decorative boards RV1 to RV4. , And the mounting surfaces of the frame side VDP control target decorative boards LV1 to LV4 can be in close contact with each other. Thereby, light emission of a plurality of LEDs (decorative LEDs) provided on the mounting surfaces of the frame side VDP control target decoration substrates RV1 to RV4 and the frame side VDP control target decoration substrates LV1 to LV4 is formed on the partition plate. It is possible to irradiate toward the back side of the cover body through a rectangular opening arranged in a grid shape, so that each LED emits light in the rectangular opening formed in a grid shape on the partition plate. Can be configured as LED displays that are arranged adjacent to each other vertically and horizontally.

  That is, the right side VDP control target first light emission decoration region RTV1 to the right side VDP control target third light emission decoration region RTV3 formed in the right side decoration unit 200, and the right side VDP control target first shape formed in the upper decoration unit 280. The four-light-emitting decoration area RTV4 can display various information as an LED display in dots, and the left-side VDP control target first light-emitting decoration area LTV1 to the left-side VDP control target formed in the left-side decoration unit 240. The third light emitting decoration area LTV3 and the left side VDP control target fourth light emitting decoration area LTV4 formed in the upper decoration unit 280 can each display various information as an LED display in dots.

  On the back side (mounting surface side) of the cover body that covers the mounting surfaces of the frame side VDP control target decorative substrates RV1 to RV4 and the frame side VDP control target decorative substrates LV1 to LV4, a metal vapor deposition film is formed thinly (for example, A plurality of LEDs (decorative LEDs) provided on each of the frame side VDP control target decorative boards RV1 to RV4 and the frame side VDP control target decorative boards LV1 to LV4. ) Can be easily visually recognized.

  As a result, the resist color on the mounting surface of the frame side VDP control target decorative boards RV1 to RV4 and the frame side VDP control target decorative boards LV1 to LV4 is black, and the base is black due to the grid-like black partition plate. The metal-deposited film is thinly formed so that the back surface side (mounting surface side) of the cover body is almost transparent (for example, aluminum is thinly deposited). And the frame side VDP control target decoration board RV1 to RV4 and the frame side VDP control target decoration board LV1 in a state where a plurality of LEDs (decoration LEDs) are turned off on each of the frame side VDP control target decoration boards LV1 to LV4. A metallic feeling can be expressed on the surface of the cover body that covers the mounting surfaces of LV4.

  In addition, although the partition plate is clamped between the mounting surface of the frame side VDP control target decorative boards RV1 to RV4 and the frame side VDP control target decorative boards LV1 to LV4 and the cover body, the partition plate and the cover body You may comprise so that the substantially transparent lens board in which a metal vapor deposition film | membrane is formed thinly (for example, aluminum is vapor-deposited thinly) between each may be pinched | interposed. This lens plate is a position corresponding to a rectangular opening (square opening) arranged in a lattice shape formed in the partition plate in a state of being sandwiched between the partition plate and the cover body, A rectangular opening formed in the partition plate by a predetermined distance (for example, 2 mm) from the partition plate side surface (that is, the rear surface of the lens plate) toward the cover body surface (that is, the front surface of the lens plate). Recesses having the same outer shape as the square opening) are formed, and the recesses are arranged in a lattice pattern. These rectangular recesses function as lens portions. The light emission of the plurality of LEDs (decorative LEDs) provided on the mounting surfaces of the frame side VDP control target decoration boards RV1 to RV4 and the frame side VDP control target decoration boards LV1 to LV4 is a lattice shape formed on the partition plate. Can be diffused through a rectangular opening arranged in the lens plate and a rectangular concave portion arranged in a lattice shape formed in the lens plate.

  Here, a plurality of LEDs (decorative LEDs) provided on the mounting surfaces of the frame-side VDP control target decorative boards RV1 to RV4 and a plurality of LEDs provided on the mounting surfaces of the frame-side VDP control target decorative boards LV1 to LV4, respectively. The arrangement of LEDs (decorative LEDs) will be briefly described.

  In a state where the decoration units 200, 240, and 280 are attached to the door frame base unit 100, the right side VDP control target first light emission decoration region RTV1 to the right side VDP control target third formed on the right side decoration unit 200. The right side VDP control target fourth light emission decoration area RTV4 formed in the light emission decoration area RTV3 and the upper decoration unit 280, and the left side VDP control object first light emission decoration area LTV1 to the left side formed in the left side decoration unit 240. The VDP control target third light emitting decoration area LTV3 and the left side VDP control target fourth light emission decoration area LTV4 formed in the upper decoration unit 280 are arranged in a pair of left and right, and the frame side VDP control target decoration board RV1. A plurality of LEDs (decorative LEDs) provided on each mounting surface of the RV4 When a plurality of LED provided on each mounting surface of the frame side VDP controlled object decorative board LV1～LV4 (decorative LED), they are arranged symmetrically. Here, a plurality of LEDs (decorative LEDs) provided on the mounting surfaces of the frame side VDP control target decorative substrates RV1 to RV4 will be described, and provided on the mounting surfaces of the frame side VDP control target decorative substrates LV1 to LV4, respectively. Description of the plurality of LEDs (decorative LEDs) to be performed is omitted.

  As described above, the right-side VDP control target first light-emitting decoration area RTV1 is decorated with light emission by a plurality of LEDs (decorative LEDs) provided on the frame-side VDP control target decoration board RV1. The frame-side VDP control target decorative board RV1 has first to fourteenth blocks in which a plurality of full-color LEDs (decorative LEDs) are provided horizontally in a row from the lower side to the upper side. The first block is provided with nine full-color LEDs (decorative LEDs) horizontally in a row, the second block is provided with ten full-color LEDs (decorative LEDs) horizontally in a row, and the third to sixth blocks. The block is provided with nine full-color LEDs (decorative LEDs) horizontally in a row, and the seventh block and the eighth block are provided with eight full-color LEDs (decorative LEDs) horizontally in a row. The 9th to 11th blocks are each provided with eight full color LEDs (decorative LEDs) horizontally in a row, and the twelfth block is provided with six full color LEDs (decorative LEDs) horizontally in a row. The block is provided with four full-color LEDs (decorative LEDs) horizontally in a row, and the 14th block is provided with a row of full-color LEDs (decorative LEDs). It is provided two horizontally. The first block to the fourteenth block are dots (that is, the size of rectangular openings arranged in a grid formed on the partition plate described above) along the shape of the right side VDP control target first light emitting decoration region RTV1. ) The right side of the unit is shifted to the frame side VDP control target decorative board RV1, and a total of 104 full-color LEDs (decorative LEDs) are provided on the frame side VDP control target decorative board RV1. In the left side VDP control target first light emission decoration area LTV1, dots are arranged along the shape of the left side VDP control target first light emission decoration area LTV1 (that is, in a grid pattern formed on the partition plate described above). The first block to the fourteenth block are arranged shifted to the left in units of the size of the rectangular opening), and a total of 104 full-color LEDs (decorative LEDs) are provided.

  As described above, the right-side VDP control target second light emission decoration area RTV2 is decorated with light emission by a plurality of LEDs (decoration LEDs) provided on the frame side VDP control target decoration board RV2. The frame-side VDP control target decorative board RV2 has a first block to a twenty-second block in which a plurality of full-color LEDs (decorative LEDs) are provided horizontally in a row from the lower side to the upper side. The first block is provided with three full color LEDs (decorative LEDs) horizontally in a row, and the second block is provided with four full color LEDs (decorative LEDs) horizontally in a row. The block is provided with five full-color LEDs (decorative LEDs) horizontally in a row, and the sixth to twentieth blocks are provided with four full-color LEDs (decorative LEDs) horizontally in a row. The block is provided with three full-color LEDs (decorative LEDs) horizontally in a row, and the twenty-second block is provided with two full-color LEDs (decorative LEDs) horizontally in a row. The first block to the twenty-second block are dots (that is, the size of rectangular openings arranged in a grid formed on the partition plate described above) along the shape of the right side VDP control target second light emitting decoration region RTV2. ) The right side of the unit is shifted to the frame side VDP control target decorative board RV2, and a total of 87 full-color LEDs (decorative LEDs) are provided on the frame side VDP control target decorative board RV2. In the left side VDP control target second light emitting decoration area LTV2, dots are arranged along the shape of the left side VDP control target second light emitting decoration area LTV2 (that is, in a grid pattern formed on the partition plate described above). The first block to the twenty-second block are arranged on the left side in units of the size of the rectangular opening), and a total of 87 full-color LEDs (decorative LEDs) are provided.

  As described above, the right-side VDP control target third light emission decoration area RTV3 is light-decorated by a plurality of LEDs (decoration LEDs) provided on the frame-side VDP control target decoration board RV3. The frame-side VDP control target decorative board RV3 has first to 26th blocks in which a plurality of full-color LEDs (decorative LEDs) are provided horizontally in a row from the lower side to the upper side. The first block is provided with two full-color LEDs (decorative LEDs) horizontally in a row, the second block is provided with three full-color LEDs (decorative LEDs) horizontally in a row, and the third to seventh blocks. The block is provided with four full-color LEDs (decorative LEDs) horizontally in a row, and the eighth to tenth blocks are provided with five full-color LEDs (decorative LEDs) horizontally in a row. From block to thirteenth block, four full color LEDs (decorative LEDs) are provided horizontally in a row, and from the fourteenth block to sixteenth block, five full color LEDs (decorative LEDs) are provided horizontally in one row. In the 17th to 21st blocks, six full-color LEDs (decorative LEDs) are provided horizontally in a row, and the 22nd block In the twenty-third and twenty-third blocks, five full-color LEDs (decorative LEDs) are provided horizontally in one row, and in the twenty-fourth block, four full-color LEDs (decorative LEDs) are provided horizontally in one row. The block is provided with three full-color LEDs (decorative LEDs) horizontally in a row, and the 26th block is provided with two full-color LEDs (decorative LEDs) horizontally in a row. The first block to the twenty-sixth block are dots (that is, the size of rectangular openings arranged in a grid formed in the partition plate described above) along the shape of the right side VDP control target third light emitting decoration region RTV3. ) The right side or the left side of the unit is arranged on the frame side VDP control target decoration board RV3, and a total of 116 full-color LEDs (decoration LEDs) are provided on the frame side VDP control target decoration board RV3. In the left side VDP control target third light emission decoration area LTV3, dots (that is, a grid formed on the partition plate described above) are arranged along the shape of the left side VDP control target third light emission decoration area LTV3. The first block to the 26th block are arranged to be shifted to the left or right side in units of the size of the rectangular opening), and a total of 116 full-color LEDs (decorative LEDs) are provided.

  As described above, the right-side VDP control target fourth light emission decoration area RTV4 is decorated with light emission by a plurality of LEDs (decoration LEDs) provided on the frame side VDP control target decoration board RV4. The frame-side VDP control target decorative board RV4 has first to 25th blocks in which a plurality of full-color LEDs (decorative LEDs) are provided horizontally in a row from the lower side to the upper side. The first block is provided with two full-color LEDs (decorative LEDs) horizontally in a row, the second block is provided with three full-color LEDs (decorative LEDs) horizontally in a row, and the third block is full-color. Four LEDs (decorative LEDs) are provided horizontally in a row, the fourth block is provided with six full-color LEDs (decorative LEDs) horizontally, and the fifth block is a full-color LED (decorative LEDs). 7 are provided horizontally in one row, nine full-color LEDs (decorative LEDs) are provided horizontally in the sixth block, and full-color LEDs (decorative LEDs) 11 are provided in the seventh block horizontally in one row. There are 12 full-color LEDs (decorative LEDs) arranged horizontally in the eighth block, and the full-color LEDs (decorative LEDs) arranged in the ninth block. Fourteen horizontal LEDs are provided, 15 full-color LEDs (decorative LEDs) are provided horizontally in the 10th and 11th blocks, and full-color LEDs (decorative blocks) are provided in the 12th and 13th blocks. 16 LEDs are provided horizontally in a row, the 14th block is provided with 17 full color LEDs (decorative LEDs) horizontally, and the 15th block is provided with full color LEDs (decorative LEDs) in a row. Sixteen horizontal blocks are provided, 15 full-color LEDs (decorative LEDs) are arranged horizontally in the 16th and 17th blocks, and 15 full-color LEDs (decorative LEDs) are arranged in the 18th block. Fourteen horizontal LEDs are provided, and the nineteenth block is provided with 13 full-color LEDs (decorative LEDs) horizontally in a row. The 20th block is provided with 11 full color LEDs (decorative LEDs) horizontally in a row, the 21st block is provided with 10 full color LEDs (decorative LEDs) horizontally in a row, and the 22nd block is full color. Nine LEDs (decorative LEDs) are provided horizontally in a row, seven full-color LEDs (decorative LEDs) are provided horizontally in the twenty-third block, and full-color LEDs (decorative LEDs) are provided in the twenty-fourth block. Are provided horizontally in one row, and the 25th block is provided with three full-color LEDs (decorative LEDs) horizontally in one row. The first block to the twenty-fifth block are dots (that is, the size of rectangular openings arranged in a grid formed on the partition plate described above) along the shape of the right side VDP control target fourth light emitting decoration region RTV4. ) It is arranged on the frame side VDP control target decoration board RV4 while being shifted to the right or left in units, and a total of 265 full color LEDs (decoration LEDs) are provided on the frame side VDP control target decoration board RV4. In the left side VDP control target fourth light emission decoration region LTV4, dots (that is, a grid formed on the partition plate described above) are arranged along the shape of the left side VDP control target fourth light emission decoration region LTV4. The first block to the 25th block are arranged to be shifted to the left side or the right side in units of the size of the rectangular opening), and a total of 265 full-color LEDs (decorative LEDs) are provided.

  As described above, the right side VDP control target first light emission decoration area RTV1 to the right side VDP control target fourth light emission decoration area RTV4 are 104 full-color LEDs provided on the frame side VDP control target decoration board RV1, as described above. , 87 full-color LEDs provided on the frame-side VDP control target decorative board RV2, 116 full-color LEDs provided on the frame-side VDP control target decorative board RV3, and 265 provided on the frame-side VDP control target decorative board RV4 As shown above, the left side VDP control target first light emission decoration area LTV1 to the left side VDP control target fourth light emission decoration area LTV4 are decorated with the frame side VDP. 104 full-color LEDs provided on the decorative board LV1 to be controlled 87 full-color LEDs provided on the frame side VDP control target decorative board LV2, 116 full color LEDs provided on the frame side VDP control target decorative board LV3, and 265 full colors provided on the frame side VDP control target decorative board LV4 The LED is decorated with a total of 572 full-color LEDs.

  That is, the right side decoration unit 200 (right side VDP control target first light emission decoration area RTV1 to right side VDP control target third light emission decoration area RTV3), the left side decoration unit 240 (left side VDP control object first light emission decoration area LTV1). The left side VDP control target third light emission decoration area LTV3) and the upper decoration unit 280 (the right side VDP control target fourth light emission decoration area RTV4, the left side VDP control target fourth light emission decoration area LTV4) are the right side VDP control. 572 full-color LEDs (decorative LEDs) that illuminate and decorate the target first light emission decoration area RTV1 to the right side VDP control target fourth light emission decoration area RTV4, and the left side VDP control object first light emission decoration area LTV1 to the left side VDP. 572 full-color lights that decorate the fourth light-emitting decoration area LTV4 to be controlled. And over LED (decorative LED), it emitted decorated by by total 1144 pieces of full color LED (decorative LED).

[4-1-1. Door frame base body]
The door frame base body 110 is formed in a vertically long frame shape with a synthetic resin, and is formed in such a manner that the gaming window 101 having a vertically long and substantially elliptical shape penetrating in the front-rear direction is offset upward as a whole. Has been. The gaming window 101 is formed in a smooth curved shape in which the left and right side and upper inner peripheral edges are continuous, whereas the lower inner peripheral edge is formed in a straight line extending left and right. In addition, a rectangular notch that allows insertion of the first ball outlet of the foul cover unit 540 is formed on the shaft support side (left side in front view) on the inner peripheral edge of the lower side of the game window 101 in the door frame base body 110. A speaker mounting portion for mounting and fixing the speaker 130 disposed on the left and right outer sides of the lower side of the gaming window 101, and a right side (open side) end of the front surface that is disposed in the lower right corner portion and is bulging forward in front view A handle attachment portion for attaching the handle bracket inclined obliquely so as to move backward, a wiring passage opening through which a wire from the handle device 500 can pass through in a front-rear direction at a predetermined position of the handle attachment portion, and above the handle attachment portion A lock hole 116 is formed which is formed in a cylindrical shape that extends short forward and into which a cylinder lock 1010 described later can be inserted. The door frame base body 110 has an upper side formed by the game window 101 and widths on the left and right sides of an upper reinforcing sheet metal 151, a pivot supporting side reinforcing sheet metal 152, and an open side reinforcing sheet metal 153 of a reinforcing unit 150 described later. The gaming window 101 is formed as large as possible with respect to the size of the door frame base body in a front view.

[4-1-2. Reinforcement unit]
The reinforcing unit 150 includes an upper reinforcing sheet metal 151 (see FIG. 1) attached along the back side of the upper side of the door frame base main body 110 and a shaft support attached along the back side of the side of the side of the door frame base main body 110 Side reinforcing sheet metal 152 (see FIG. 1), an open side reinforcing sheet metal 153 (see FIG. 1) attached along the back side of the open side of the door frame base body 110, and the gaming window 101 of the door frame base body 110 And a lower reinforcing metal plate 154 (see FIG. 1) attached along the back surface of the lower side, and they are fastened to each other with screws, rivets or the like to form a square shape.

  An upper shaft support portion 156 having a shaft pin 155 slidably provided in an upper and lower direction on an upper surface and a lower shaft support portion 158 having a shaft pin 157 on its lower surface at upper and lower ends of the shaft support side reinforcing sheet metal 152. Integrated. The upper and lower shaft pins 155 and 157 are pivotally supported by the upper shaft bracket 630 and the lower shaft bracket 640 formed on the upper and lower sides of the body frame 3, so that the door frame 5 is attached to the body frame 3. So that it can be freely opened and closed.

  In addition, a hook cover 165 that contacts the door frame hook portion 1041 of the locking device 1000 is provided at the lower rear side of the opening-side reinforcing sheet metal 153. The hook cover 165 engages with the door frame hook portion 1041 of the lock device 1000 (locking device) attached along the open side of the main body frame 3 when the door frame 5 is closed with respect to the main body frame 3. By inserting a key into the cylinder lock 1010 of the lock device 1000 and rotating it in one direction (rotating in the direction opposite to the direction in which the main body frame 3 is opened with respect to the outer frame 2), the door frame hook portion 1041 and the hook cover 165 are disengaged, and the closed state of the door frame 5 with respect to the main body frame 3 can be released.

[4-2. Dish unit]
Next, the dish unit 300 will be described. The tray unit 300 includes an upper plate 301 and a lower plate 302 for storing the game balls paid out from the prize ball device 740, and the game balls stored in the upper plate 301 are shot through the ball feeding unit. Can be supplied to the device 650.

  The shape of the upper dish upper panel 314 of the dish unit 300 is formed in a curved shape so as to protrude forward from the left to the center in a front view, and forward straightly from the center to the right. Protrusively formed. An operation unit attachment portion to which the operation unit 400 is attached is formed at the upper center of the plate unit 300, and a liquid crystal attachment portion 314d for attaching the upper plate side liquid crystal display device 470 is formed on the right side of the operation unit attachment portion. . The shape of the upper plate upper panel 314 on which the liquid crystal mounting portion 314d is formed is formed in a plate shape, and for example, when a player presses the portion downward with a hand, the upper plate 314d bends downward. When the pressing force exceeds a predetermined force, the upper plate upper panel 314 is broken. This is because the upper plate side liquid crystal display device 470 is expensive, and when the player presses the hand on the screen of the upper plate side liquid crystal display device 470, the force is received by the upper plate upper panel 314. The upper plate side liquid crystal display device 470 is prevented from being damaged by bending the upper plate upper panel 314. That is, a structure is adopted in which the upper plate upper panel 314 is damaged before the upper plate side liquid crystal display device 470 is damaged. In addition, when the upper plate upper panel 314 is damaged, the plate unit 300 is replaced. In this case, the upper plate side liquid crystal display device 470 is removed from the broken upper plate upper panel 314 and attached to the upper plate upper panel 314 of the plate unit 300 to be replaced for reuse.

  Further, the dish unit 300 includes an upper dish ball removal mechanism 340 for removing game balls stored in the upper dish 301 to the lower dish 302 in response to an operation of the upper dish ball removal button 341, and a lower dish ball removal button 354. The lower tray ball removing mechanism 350 for pulling down the game balls stored in the lower tray 302 in accordance with the operation of the lower tray ball through the lower tray ball removing hole 324b and the pachinko gaming machine 1 are not shown. A ball rental unit 360 for operating the CR unit.

[4-2-1. Operation unit]
The operation unit 400 is disposed on the front surface of the upper plate 301 at a substantially center in the left-right direction when viewed from the front. Operation part), and can accept the player's operation according to the gaming state, or the dial operation part 401 can be moved, not only the game ball driving operation to the player It is intended to be able to participate in production during the game. The rotation (rotation direction) of the dial operation unit 401 is detected by a rotation detection switch provided in the operation unit 400, and the operation of the pressing operation unit 405 is detected by a press detection switch provided in the operation unit 400.

  Further, the operation unit 400 can rotate the dial operation unit 401 in the clockwise direction or the counterclockwise direction by the driving force of the dial drive motor 414. Further, the operation unit 400 rotates the dial operation unit 401 step by step by the driving force of the dial drive motor 414 using a stepping motor, or when the player rotates the dial operation unit 401, Rotation can be assisted, it can be prevented from turning on purpose, or a click can be added to the rotation. Further, the operation unit 400 can vibrate the dial operation unit 401 by alternately repeating a rotation for rotating the dial drive motor 414 in small increments and a rotation for rotating in reverse.

[4-2-2. Rental unit]
The lending unit 360 includes a lending button 361 and a return button 362 that can be pressed backward, and a lending remaining display portion 363 between the lending button 361 and the return button 362. When the ball rental button 361 is operated, it is detected by the ball rental switch 365a, and when the return button 362 is operated, it is detected by the return switch 365b. The display content of the remaining frequency indicator 365c can be visually recognized through the rental remaining display portion 363. A CR unit lamp 365d is disposed adjacent to the remaining frequency indicator 365c so that the light emission mode of the CR unit lamp 365d can be visually recognized through the rental remaining display portion 363. The ball lending switch 365a, the return switch 365b, the remaining frequency indicator 365c, and the CR unit lamp 365d are mounted on the frequency display plate 365, and the frequency display plate 365 is attached to the inside of the ball rental unit 360. . When the ball rental unit 360 is pushed into the ball lending machine provided adjacent to the pachinko gaming machine 1 with a cash or prepaid card and the ball lending button 361 is pressed, a predetermined number of game balls are transferred to the dish unit. 300 can be lent out (paid out) into the top plate 301, and when the return button 362 is pressed, the balance of the loaned portion is drawn and the remaining cash or prepaid card is returned. ing. In addition, the remaining lending display section 363 displays the number of cash and prepaid cards remaining in the ball lending machine.

[4-3. Ball transport unit]
Next, the ball feeding unit 580 will be described. The ball feeding unit 580 can supply the game balls supplied from the upper plate 301 in the plate unit 300 one by one to the hitting ball launching device 650, and the game balls stored in the upper plate 301 are supplied to the upper plate ball. It can be pulled out to the lower pan 302 by operating the upper pan ball release button 341 of the pulling mechanism 340.

  The ball feeding unit 580 is an intrusion port in which game balls stored in the upper plate 301 of the plate unit 300 are supplied through the upper plate ball discharge port of the upper plate 301 and the ball opening of the door frame base body 110 and penetrate in the front-rear direction. And a box-shaped front cover that has a ball opening that opens below the intrusion opening and is open at the rear, and a box-like shape that closes the rear end of the front cover and opens the front, and penetrates in the front-rear direction The rear cover having a hitting ball supply port 582a for supplying the game ball that has entered from the intrusion port of the front cover to the hitting ball launcher 650, and the axis extending in the front-rear direction between the rear cover and the front cover. A ball removing member that is pivotally supported and has a partitioning portion for partitioning between the entrance and the ball outlet on the rear side of the front cover, and the game balls on the partitioning portion of the ball removing member are hit one by one on the rear cover. Up and down between the front cover and the rear cover before feeding to the supply port 582a And Tamaoku member rotatably supported around an axis extending to, and a Tamaoku solenoid 585 to rotate the Tamaoku member.

  When the ball feeding solenoid 585 is driven (ON state), the ball feeding member accepts one game ball, while when the ball feeding solenoid 585 is released (OFF state), the ball feeding member accepts it. The game ball is sent (supplied) to the hitting ball launching device 650 side.

[4-4. Handle device]
Next, the handle device 500 will be described. The handle device 500 is fixed to a handle bracket attached to the front surface of the door frame base main body 110, is cylindrical, and has a handle base whose front end bulges out in a direction perpendicular to the axis, and a handle base that is rotatable relative to the handle base. Arranged at the front of the front of the rotary handle main body 506, the front of the rotary handle main body 506, the front of the rotary handle main body 506 fixed to the front of the rear of the rotary handle main body and being rotatable integrally with the rear of the rotary handle main body. And a front end cover 508 that is fixed to the handle base and rotatably supports the front of the rotary handle main body 506 and the rear of the rotary handle main body in cooperation with the handle base.

  In addition, the handle device 500 is attached and fixed to the center of rotation in front of the rotary handle body so as to protrude from the front side to the rear side, and has a non-circular bearing portion at the rear end, and the shaft member bearing portion is fitted. A potentiometer 512 that has a detection shaft portion that can be rotated together and is non-rotatably fitted to the front surface of the handle base, and is fixed to the front surface of the handle base so that the potentiometer 512 is sandwiched between the handle base and A switch support member having a through-hole through which the shaft portion can pass, a touch switch 516 attached to the rear surface of the switch support member, and a firing stop switch 518 attached to the touch switch 516 at a different position on the rear surface of the switch support member; A single-shot button that is pivotally supported with respect to the switch support member and operates the firing stop switch 518. And a handle that is arranged so as to cover the outer periphery of the shaft member and urges the front of the rotary handle body 506 and the rear of the rotary handle body to return to the original rotation position (rotation end in the counterclockwise direction when viewed from the front). And a return spring. The potentiometer 512 is for electrically adjusting the strength of launching the game ball toward the game area 1100 according to the rotational position of the front 506 of the rotary handle. In addition, after the rotary handle main body 506 and after the rotary handle main body, it is rotated from the original rotational position to the limit rotational position (rotation end in the clockwise direction when viewed from the front) that is the maximum rotational position in the clockwise direction when viewed from the front. To do.

  Further, in the handle device 500, the potentiometer 512 is a variable resistor. When the front part 506 of the rotary handle and the rear part of the rotary handle body are rotated, the detection shaft portion of the potentiometer 512 is rotated via the shaft member. . Then, the internal resistance of the potentiometer 512 changes in accordance with the rotation position (rotation angle) of the detection shaft portion, and the driving force of the launch solenoid 654 in the ball hitting device 650 changes in accordance with the internal resistance of the potentiometer 512, thereby rotating the rotary handle. A game ball is driven into the game area 1100 with a launch intensity corresponding to (a match with) the rotation angle of the front of the main body 506 and the rear of the rotary handle, that is, the rotation position of the front of the rotary handle main body 506 and the rear of the rotary handle. Yes.

[4-5. Foul cover unit]
Next, the foul cover unit 540 will be described. The foul cover unit 540 is attached to the rear surface below the game window 101 in the door frame base unit 100 and is played by a game ball paid out from the prize ball unit 700 or a hitting ball launcher 650. A game ball (foul ball) that has not reached the area 1100 is guided to the upper plate 301 or the lower plate 302 of the plate unit 300. The foul cover unit 540 includes a cover base that is open on the front side and has a plurality of game ball passages therein, and a front cover that closes the front end of the cover base.

  The cover base of the foul cover unit 540 has a first sphere inlet 542a that is disposed in the upper right corner when viewed from the rear and penetrates in the front-rear direction, and a first base that communicates with the first sphere inlet and expands to the right in the front view toward the front end of the cover base 542. One ball passage, a second ball inlet 542c arranged outside the first ball inlet 542a (on the right side in the rear view) and having a larger opening than the first ball inlet 542a, and communicated with the second ball passage and inside the cover base And a second sphere inlet 542c that extends downward and is inclined toward the lower right corner when viewed from the front. The first ball inlet 542a and the second ball inlet 542c are the normal ball outlet 774 and the full ball outlet 776 of the full tank branching unit 770 in the prize ball unit 700 in a state where the door frame 5 is closed with respect to the main body frame 3. Are formed at positions facing each other. In the second ball passage in the cover base, the height of the portion extending in the left-right direction along the lower end is about three times as high as the outer diameter of the game ball. An accommodating space that can be accommodated is formed.

  Further, the cover base 542 is arranged at a substantially upper center in the left-right direction and has a foul ball inlet 542e that opens upward, and a foul that communicates with the foul ball inlet 542e and can guide the game ball to the upper portion near the downstream of the second ball passage. And a ball passage. In addition, the cover base includes an opening / closing operation piece for operating the opening / closing shutter 792 of the bulb outlet opening / closing unit 790 on the lower rear surface of the second bulb entrance. When the door frame 5 is closed with respect to the main body frame 3, the opening / closing operation piece contacts the spherical contact portion of the opening / closing crank in the ball outlet opening / closing unit 790, thereby rotating the opening / closing crank and opening / closing the shutter 792. It can be in an open state.

  The front cover of the foul cover unit 540 is formed in a substantially plate shape that closes the front surface of the cover base. An outlet, and a second ball outlet that is disposed in the lower right corner of the front view and communicates with the downstream end of the second ball passage of the cover base 542 and penetrates in the front-rear direction. A first ball outlet of the front cover is connected to an upper plate ball supply port of the plate unit 300 through a notch portion of the door frame base unit 100. Further, the rear end of the lower tray ball supply bowl in the tray unit 300 is connected to the second ball outlet through the ball passage opening of the door frame base main body 110.

  The foul cover unit 540 transfers the game balls supplied from the normal ball outlet 774 of the full tank branching unit 770 in the prize ball unit 700 to the first ball inlet 542a from the first ball outlet to the dish unit 300 through the first ball passage. It can supply to the upper plate 301 through the upper plate ball supply port. Further, the foul cover unit 540 passes the game ball supplied from the full tank outlet 776 of the full tank branch unit 770 in the prize ball unit 700 to the second ball inlet 542c from the second ball outlet through the second ball passage. The plate unit 300 can be supplied to the lower plate 302 via the lower plate ball supply basket and the lower plate ball supply port.

  Further, in the foul cover unit 540, when the door frame 5 is closed with respect to the main body frame 3, the foul ball inlet 542e is positioned below the foul space 626 of the main body frame 3, and the ball hitting device When the game ball launched by 650 does not reach the game area 1100 and becomes a foul ball and falls in the foul space 626, the game ball is received by the foul ball inlet 542e. The foul cover unit 540 can discharge (supply) the game balls received at the foul ball inlet 542e from the second ball outlet to the lower plate 302 of the dish unit 300 through the foul ball passage and the second ball passage. It can be done.

  Further, the foul cover unit 540 forms an upstream (left side in front view) side surface of the accommodation space in the second ball passage and is pivotally supported by the cover base so as to be swingable by a game ball stored in the accommodation space. A member, a full tank switch 550 that detects the swing of the swing member, and a spring that biases the swing member in a non-detection state by the full switch 550. The swinging member is pivotally supported at the lower end with respect to the cover base, and the upper end is rotated to the left when viewed from the front. It comes to form. Further, the swing member is biased to a position where the swing member is in a substantially vertical state by a spring. Further, the swinging member is formed with a detection piece projecting outward on the side surface opposite to the accommodation space side, and this detection piece is detected by the full switch 550. That is, based on the detection signal from the full tank switch 550, it can be determined whether or not the game ball in which the accommodation space is stored is full.

[5. Overall configuration of game board]
Next, the overall configuration of the game board 4 will be described with reference to FIGS. FIG. 8 is a front view of the game board, and FIG. 9 is an exploded perspective view of the game board of FIG. As shown in FIGS. 8 and 9, the game board 4 has an outer rail 1111 and an inner rail 1112, and a game area 1100 in which a game ball as a game medium is driven when the player operates the handle device 500. A frame-shaped front component member 1110 that defines an outer periphery, and a position that is visible from the game window 101 of the door frame 5 to the player side when the front component member 1110 is attached to the pachinko gaming machine 1 at the lower left corner when viewed from the front. And a plurality of openings 1158 penetrating in the front-rear direction in a predetermined shape at positions corresponding to the game area 1100 and attached to the rear side of the front component member 1110 so as to close the game area 1100. A plate-like gaming panel 1150, a front unit 2000 attached from the front side to the opening 1158 of the gaming panel 1150, and a gaming panel A back unit 3000 is attached to the rear surface 150, and a.

  Further, the game board 4 is detachably attached to the front side of the back unit 3000, and an effect display unit 1900 (hereinafter referred to as "game board") that can display a predetermined effect image that can be viewed from the player side according to the game state. Side effect display unit 1900 "), and a substrate holder 1160 attached to the lower rear portion of the game panel 1150 so as to cover the lower portion of the back unit 3000 from the rear side. On the rear surface of the substrate holder 1160, a peripheral substrate box 1905 that accommodates the peripheral control substrate 4140 and the liquid crystal output substrate 3420, and a main control substrate box that accommodates the main control substrate 4100 so as to overlap the rear of the peripheral substrate box 1905. 1170 are attached.

  The game board 4 includes a plurality of decorative boards (hereinafter, may be referred to as “a plurality of game board side decorative boards”). The game board side decorative board includes a game board side peripheral control MPU control target decoration board that is a control object directly controlled by a peripheral control MPU of the peripheral control board 4140 described later, and a sound source built-in VDP of the peripheral control board 4140 described later. There is a game board side VDP control target decorative board which is a control target to be directly controlled.

[5-1. Previous component]
Next, the front component member 1110 will be described. The front component member 1110 has a substantially rectangular shape whose outer shape can be inserted into the game board holding port 601 of the main body frame 3, and has an inner shape that penetrates in a front-rear direction in a substantially circular shape. The outer periphery of the region 1100 is partitioned. The front component member 1110 has an outer rail 1111 that extends in an arc shape from the lower left end toward the left side from the center in the left-right direction in a front view and extends to the upper right side through the center upper end in the left-right direction in the front view. An inner rail 1112 that is arranged substantially along the outer rail 1111 inside the outer rail 1111 and extends in an arc shape from the lower center in the left-right direction when viewed from the front to the upper left side when viewed from the front. An inner peripheral rail 1113 extending in an arc shape to a position below the end (upper end) of the outer rail 1111 along the counterclockwise circumferential direction when viewed from the front, and the end (upper end) of the inner peripheral rail 1113 and the outer rail 1111 , The inner rail 1112 and the inner peripheral rail 1113, which can be contacted with the game ball rolling along the outer rail 1111. Is located at the lowermost end of the game area 1100 at the boundary of the outer area, and is supported by the upper end of the inner rail 1112 so as to be rotatable, and closes between the outer rail 1111. In this way, it is possible to rotate only between a closed position that extends upward from the upper end of the inner rail 1112 and an open position that rotates clockwise from the front and opens the outer rail 1111. And a backflow preventing member 1116 biased by a spring so as to return to the closed position side.

  When the front component member 1110 is in a state where the game board 4 is attached to the main body frame 3, the lower end opening between the outer rail 1111 and the inner rail 1112 is a launch rail 660 in the hitting ball launcher 650 of the main body frame 3 (FIG. 1). )). Between the lower end of the outer rail 1111 and the upper end of the launch rail 660, a space extending in the left-right direction and downward is formed, and the game ball launched along the launch rail 660 of the hit ball launcher 650 is Then, it jumps over the space and is driven between the outer rail 1111 and the inner rail 1112 from the lower end opening between the outer rail 1111 and the inner rail 1112. The game ball driven between the outer rail 1111 and the inner rail 1112 rolls upward along the outer rail 1111 according to the momentum, and the backflow prevention member 1116 pivotally supported on the upper end of the inner rail 1112 is used. The player can enter the game area 1100 by rotating it toward the open position against the biasing force.

  In addition, when the game ball is strongly hit by the hit ball launching device 650, the game ball that rolls along the outer rail 1111 in the game area 1100 comes into contact with the stop portion 1114 provided at the end of the outer rail 1111. The rolling direction of the game ball can be forcibly changed by the game ball coming into contact with the stop 1114, and the game ball rolls continuously from the outer rail 1111 to the inner rail 1113. It can be prevented from moving. Note that even if a game ball that has entered (injected into) the game area 1100 returns to between the outer rail 1111 and the inner rail 1112, the backflow prevention member 1116 returns to the closed position by the biasing force before that. Thus, the backflow prevention member 1116 prevents the backflow of the game ball.

  In addition, when the game balls that have been driven into the game area 1100 are not received in the various winning holes provided in the front unit 2000, they flow down to the lower end of the game area 1100, and the inner rail 1112 and the inner peripheral rail 1113 Is guided to the out port 1151 of the game panel 1150 and discharged from the out port 1151 to the lower rear side of the game board 4.

  On the other hand, if the game ball launched from the hitting ball launcher 650 cannot enter the game area 1100 beyond the backflow prevention member 1116 at the tip of the inner rail 1112, the outer rail 1111 and the inner rail 1112 A foul space 626 formed between the upper end of the firing rail 660 and the lower end of the outer rail 1111 from the lower end opening between the outer rail 1111 and the inner rail 1112. 1 (see FIG. 1), and is received by a foul ball inlet 542e (see FIG. 1) of the foul cover unit 540 attached to the door frame 5 located at the lower part of the foul space 626. It is discharged to the lower plate 302 (see FIG. 7).

  Note that the outer rail 1111 in the front component member 1110 has a metal plate attached to the surface thereof, so that the wear resistance due to rolling of the game ball is enhanced and the game ball rolls smoothly. ing. In addition, the stopper 1114 has an elastic body such as rubber or synthetic resin on the surface, and even if the game ball rolls vigorously along the outer rail 1111 and collides, the impact is reduced. The game ball can be repelled inward.

  In addition, the front component member 1110 is spaced apart in the vertical direction at the left end when viewed from the front, is recessed from the front to the rear and is opened at the left end, and is spaced apart from the right end when viewed from the front in the vertical direction. A pair of game board stoppers 1120 arranged, a fixed recess 1121 which is arranged on the left side of the front view from the lower end of the outer rail 1111 and opened downward and is formed in an arc shape on the upper side and recessed from the front side, and a lower end of the front view And a ball passage cutout 1122 that is cut out in a rectangular shape extending in the left-right direction upward from the lower end. The positioning concave portion 1119 of the front component member 1110 is fitted with a positioning member 956 (see FIG. 5) attached to the inside of the side crime prevention plate 950 in the main body frame 3, thereby allowing the game board holding port 601 (see FIG. 5). It is possible to restrict the left end of the game board 4 inserted in the front view from moving in the front-rear direction. The game board stopper 1120 can be detachably locked to the game board locking portion of the main body frame base 600 in the main body frame 3, and the game board stopper 1120 is connected to the game board. By locking to the stop portion, the right end of the game board 4 inserted into the game board holding port 601 of the main body frame 3 can be restricted from moving in the front-rear direction.

  Further, the fixing recess 1121 of the front component member 1110 has a game board fixture 690 (see FIG. 5) pivotally supported on the front surface of the main body frame 3 in a state where the game board 4 is inserted into the game board holding port 601 of the main body frame 3. (See FIG. 5) is inserted into the game board fixing tool 690, and the game board fixing tool 690 allows the game board 4 to be inserted. The lower end of the head is restricted from moving forward. Further, the ball passage cutout portion 1122 of the front component member 1110 is formed with the same ball passage cutout portion 1152 at the same position of the game panel 1150, and the game board 4 is connected to the game board holding port 601 of the main body frame 3. In the inserted state, the front end of the full tank branching unit 770 (see FIG. 5) is inserted into the notches 1122 and 1152 for the ball passage.

  A function display unit 1180, which will be described later, is arranged at the lower right of the front component member 1110 when viewed from the front.

[5-2. Table unit]
Next, the front unit 2000 of the game board 4 will be described. The front unit 200 is a lower part in the game area 1100 and above the out port 1151, and is supported by the front surface of the game panel 1150. And a side prize opening member 2200 supported along the front surface of the gaming panel 1150 and a frame-shaped center accessory 2300 disposed approximately at the center of the gaming area 1100 and supported by the gaming panel 1150. Yes.

  The front unit 2000 is inserted from the front side into the opening 1158 formed at a position corresponding to the gaming area 1100 in the gaming panel 1150, and is attached to the front surface of the gaming panel 1150. A portion protruding forward from the game panel 1150 is positioned in the game area 1100. As a result, the front unit 2000 comes into contact with the game ball that has been driven into the game area 1100 at an appropriate position, and together with the obstacle nail implanted on the front surface of the game panel 1150, Can be changed. The table unit 2000 can decorate the game area 1100.

[5-2-1. Attacker unit]
Next, the attacker unit 2100 of the table unit 2000 will be described. The attacker unit 2100 has a plurality of entrances (winning ports) through which game balls that have been driven into the game area 1100 can be received. Specifically, a first start port 2101 disposed substantially at the center in the left-right direction, a rectangular large winning port 2103 disposed on the right side of the first start port 2101 and extending greatly in the left-right direction, and a large winning port 2103 A general winning port 2104 disposed on the left side of the first starting port 2101 and a second starting port device 2150 provided with a second starting port 2102 disposed on the upper side of the large winning port 2103. . The game balls received in the first start port 2101, the second start port 2102, the big winning port 2103, and the general winning port 2104 are guided from the front side to the rear side of the game panel 1150.

  In addition to the second start port 2102, the second start port device 2150 includes a gate portion 2150 a through which game balls can pass, a movable piece 2106 that opens and closes the second start port 2102, and a movable piece after passing through the gate portion 2150 a. A game ball discharge route 2150d for discharging game balls that cannot enter the second starting port 2102 to the big prize opening 2103 by closing the 2106, and the movable piece 2106 is opened after passing through the gate portion 2150a. Accordingly, a game ball guide route 2150e capable of guiding the game ball to the second start port 2102 is provided. The gate unit 2150a is provided with a gate switch 2352 that detects a game ball passing through the gate unit 2150a.

  The game ball that hits the game ball strongly in the hitting ball launcher 650 and rolls along the outer rail 1111 in the game area 1100 comes into contact with the stop portion 1114 provided at the end of the outer rail 1111, and the inner circumference When the “right-handed” in which the game ball rolls to the rail 1113 is performed, the second starting port device 2150 is reached. Then, the game ball passes through the gate portion 2150a of the second starter device 2150 as it is, reaches the movable piece 2106, and is moved from the position where the movable piece 2106 is advanced to the retracted position to open the second starter port 2102. In this case, the game ball can enter and enter the second starting port 2102, while the movable piece 2106 is moved from the retracted position to the advanced position to close the second starting port 2102. In some cases, the game ball falls toward the grand prize winning opening 2103. The movable piece 2106 is driven by the start opening solenoid 2105 according to a normal lottery result that is drawn based on the detection of the passage of the game ball by the gate switch 2352 of the gate unit 2150 (when the result of the normal lottery is “winning”). It is designed to be opened and closed.

  The first start port 2101 and the general winning port 2104 of the attacker unit 2100 are opened upward so that game balls can be received (winned) at all times. The special winning opening 2103 of the attacker unit 2100 can be opened and closed by a horizontally-long rectangular opening / closing member 2107 that can close the opening. The opening / closing member 2107 is pivotally supported at the lower side, and in a substantially vertical state, the prize winning opening 2103 can be closed to make it difficult to receive a game ball, and the upper side moves forward. When it is turned, the special winning opening 2103 is opened so that a game ball can be easily received. The opening / closing member 2107 is in a state in which the big prize opening 2103 is closed in a normal gaming state, and lottery is performed when a game ball is received (start winning prize) into the first starting opening 2101 and the second starting opening 2102. Depending on the result of the special lottery (when the result of the special lottery is “big hit” or “small hit”), the attacker solenoid 2108 is driven to open and close.

  Although not shown in detail, the attacker unit 2100 detects a second start port switch 2109 that detects a game ball received in the second start port 2102 and a game ball received in the big winning port 2103. The game ball detected by the second start port switch 2109 and the count switch 2110 is discharged onto the bottom wall portion of the substrate holder 1160. The back unit 3000 includes a first start port switch 3022 for detecting a game ball received in the first start port 2101 and a general winning port switch 3020 for detecting a game ball received in the general winning port 2104. ing.

  Further, the attacker unit 2100 includes a game board side peripheral control MPU control target decoration board PM1 which is a control target directly controlled by a peripheral control MPU of the peripheral control board 4140, which will be described later, and this game board side peripheral control MPU control target. Light emission decoration is performed by a plurality of LEDs (decorative LEDs) provided on the decorative substrate PM1.

[5-2-2. Side prize opening member]
Next, the side prize opening member 2200 of the front unit 2000 will be described. The side winning opening member 2200 is inserted from the front side with respect to the opening 1158 formed on the left side of the opening 1158 in which the attacker unit 2100 is inserted and fixed at the lower left side from the center in the left-right direction of the game panel 1150. Above, it is fixed to the front surface of the game panel 1150, and is provided with a general winning opening 2201 along the outer periphery of the game area 1100. The general winning opening 2201 is opened upward so that game balls can be received (winned) at all times. The game ball received in the general winning opening 2201 is detected by a general winning opening switch 3020 provided in the back unit 3000 after being guided from the front side to the rear side of the gaming panel 1150.

  Further, the side prize opening member 2200 is arranged at a position where the left end is substantially in contact with the outer periphery of the game area 1100 at the upper left end of the side prize opening member 2200 and is inclined so as to become lower toward the right end. 2202, and the game ball flowing down along the outer periphery of the game area 1100 by the shelf 2202 can be brought closer to the center of the game area 1100.

  The side prize opening member 2200 is formed so as to have a light-transmitting property as a whole, and the game board side peripheral control MPU control which is a control target directly controlled by the peripheral control MPU of the peripheral control board 4140 described later. A target decoration board PM2 is provided, and light emission decoration is performed by a plurality of LEDs (decoration LEDs) provided on the game board side peripheral control MPU control target decoration board PM2.

[5-2-3. Center character]
Next, the center accessory 2300 of the table unit 2000 will be described. The center accessory 2300 is inserted from the front side into an opening 1158 that is formed so as to penetrate substantially the center of the game panel 1150, and is fixed to the front surface of the game panel 1150. It is formed in a frame shape with a size that occupies most of the area 1100, and the outer peripheral surface on the right side when viewed from the front is in an arc shape so that a gap slightly larger than the outer diameter of the game ball is formed between the outer periphery of the game area 1100 Is formed.

  The center accessory 2300 is an upper shelf portion 2301 that is inclined so as to become lower toward the left side from the position slightly on the right side in the center in the left-right direction on the outer peripheral surface on the upper side of the front wall portion located on the front surface of the game panel 1150. When a game ball driven into the upper part of the game area 1100 flows down to the upper shelf 2301, it flows down through the left side of the center accessory 2300 (so-called “left-handed”) ), The game balls that have flowed down (invaded) to the right side of the upper shelf 2301 flow down to the lower part of the game area 1100 through the right side of the center accessory 2300 (so-called “right-handed”).

  Further, the center accessory 2300 has entered a warp inlet 2302 in which a game ball flowing down the game area 1100 can enter the outer peripheral surface on the left side of the front wall portion located on the front side of the game panel 1150 and the warp inlet 2302. A warp exit (not shown) that releases the game ball into the frame, and a game ball released from the warp exit rolls in the left-right direction, and then releases it into the game area 1100 above the attacker unit 2100. And a stage 2310 formed on the upper surface of the lower side in the frame in 2300.

  Although the detailed illustration of the stage 2310 in the center accessory 2300 is omitted, the game ball released from the warp outlet is supplied to the first stage, and the game ball is placed from the first stage on the front side of the first stage. A second stage that is supplied and capable of releasing a game ball into the game area 1100. This stage 2310 is formed in a curved surface shape such that the approximate center in the left-right direction is lowered. In addition, a chance entrance 2313 into which a game ball can enter is formed at the rear side of the center of the first stage in the left-right direction. The game is discharged from the exit 2314 into the game area 1100. The chance exit 2314 is arranged immediately above the first start opening 2101 in the attacker unit 2100, and the game balls released from the chance exit 2314 are likely to be received (win) in the first start opening 2101. It has become.

  The stage 2310 in the center accessory 2300 is formed of a transparent member, and through this stage 2310, the decorative body arranged below the stage 2310 in the back unit 3000 is visible from the player side. It has become.

  Further, the center accessory 2300 includes a game board side peripheral control MPU control target decoration board PM3 which is a control target directly controlled by a peripheral control MPU of the peripheral control board 4140 described later, and this game board side peripheral control MPU control. Light emission is decorated by a plurality of LEDs (decorative LEDs) provided on the target decorative board PM3.

[5-3. Back unit]
Next, the back unit 3000 of the game board 4 will be described. The back unit 3000 includes a back box 3001 that is open at the front and attached to the rear surface of the game panel 1150 and is fixed, a rotary light emitting device 3100 that is disposed on the upper side of the back box 3001, and a lower box in the back box 3001. A model 3400 simulating an initiation device arranged on the left side and a model 3500 simulating dynamite arranged on the lower right side in the back box 3001 are provided. The back box 3001 is provided with a plurality of decorative members around a rotary light emitting device 3100, a model 3400 simulating an initiation device, and a model 3500 simulating dynamite arranged on the lower right side in the back box 3001. . The rotary light emitting device 3100 and the plurality of decorative members respectively include a game board side VDP control target decoration board which is a control target directly controlled by a VDP with built-in sound source of the peripheral control board 4140 described later. Light emission decoration is performed by a plurality of LEDs (decoration LEDs) provided on each of the VDP control target decoration substrates.

  Further, the back unit 3000 is disposed above the center of the rear left part of the back box 3001 and is disposed below the lamp drive board box 3423 and the lamp drive board box 3423 that houses the lamp drive board 4170. A motor drive board box 3430 that accommodates a motor drive board 4180 arranged at the center of the rear left side, and a panel that is arranged below the motor drive board box 3430 and arranged below the rear left center of the back box 3001. A relay terminal plate 4161.

  In the present embodiment, the back unit 3000 is visible from the player side through the frame of the center accessory 2300 in the front unit 2000, and each unit 3100, 3400, The concept of the pachinko gaming machine 1 can be characterized by 3500 or the like.

[5-3-1. Back box]
Next, the back box 3001 of the back unit 3000 will be described. The back box 3001 is formed in a box shape with the front side open, and is provided with a plurality of flange-like fixing parts 3001a projecting outward at the front end, and on the rear side of the game panel 1150 through the fixing parts 3001a. It is supposed to be fixed. In addition to the rotary light emitting device 3100, the model 3400 imitating the detonator, and the model 3500 imitating the dynamite, the back box 3001 is attached with a game board side effect display unit 1900 and the like on the open side of the back box 3001. A mounting portion for fixing the head is formed at an appropriate position. Thereby, when the game board side liquid crystal display unit 1900 is fixed to the open side of the back box 3001, the rotary light emitting device 3100 provided in the back box 3001, the model 3400 imitating a detonator, and the model imitating dynamite The presence of 3500 can be hidden. In addition, as described above, the back box 3001 is provided with a plurality of decorative members around the rotary light emitting device 3100, the model 3400 imitating the detonator, and the model 3500 imitating the dynamite. Each of the plurality of decoration members includes a game board side VDP control target decoration board that is a control target directly controlled by the sound source built-in VDP of the peripheral control board 4140, and each of these game board side VDP control target decoration boards. A plurality of LEDs (decorative LEDs) are provided. Among these plural decorative members, the decorative member surrounding the game board side liquid crystal display unit 1900 is arranged in front of the game board side liquid crystal display unit 1900, and serves as the center function of the table unit 2000 described above. The structure fits within the frame of the object 2300 and does not interfere.

  The game balls that have entered (winned (winned)) the various winning openings provided on the game board 4 pass through a guide discharge passage (not shown) formed on the lower side of the back box 3001 and onto the bottom wall portion of the substrate holder 1160. It is discharged and discharged from the out ball discharge portion 1161 of the substrate holder 1160 to the lower side of the game board 4. In addition, a magnetic detection switch 3024 capable of detecting magnetism is provided in the vicinity of the position corresponding to the first start port 2101 of the attacker unit 2100 in the induction discharge passage.

[5-3-2. Rotating light emitting device]
Next, the rotary light emitting device 3100 will be described. The rotary light emitting device 3100 is attached and fixed to the upper side in the back box 3001. The rotary light emitting device 3100 is formed in a cylindrical shape along the vertical direction, and the lower end side is formed in a hemisphere. The hemispherical portion is formed in a transparent shape, and a plurality of LEDs provided on the game board side VDP control target decorative board, which is a control target directly controlled by a sound source built-in VDP of the peripheral control board 4140 described later, (LED for decoration) and the reflecting plate which can reflect toward the front the light which several LED (LED for decoration) emitted. In the rotary light emitting device 3100, a plurality of LEDs (decorative LEDs) provided on the game board side VDP control target decoration board are mainly lit in red, and the turn-on order is adjusted to rotate the reflector. In addition, a rotating lighting mode can be performed. In other words, the rotational light emission mode by the rotary light emitting device 3100 is not realized by rotating the reflection plate by an electric drive source such as a motor, but a plurality of LEDs provided on the game board side VDP control target decorative board. The order in which the (decorative LEDs) are turned on is adjusted.

[5-3-3. Various models]
Next, various models such as a model 3400 imitating a detonator and a model 3500 imitating dynamite will be described. A model 3400 imitating a detonator is for detonating a model 3500 imitating a dynamite, and a button portion 3400a imitating a detonation button can move in the vertical direction. For example, when the player operates the pressing operation unit 405 of the operation unit 400 attached to the upper center of the dish unit 300 in the door frame 5 illustrated in FIG. 2, the button unit 3400 a is interlocked with this (triggered by this). The peripheral control board 4140 moves from the upper end position shown in FIG. 8 to the lower end position by controlling an electric drive source such as a solenoid or a motor (not shown). Further, the model 3500 simulating dynamite has a peripheral control board 4140 that controls an electrical drive source such as a solenoid or a motor (not shown) to move back and forth, left and right, and up and down from the position shown in FIG. It is a mechanism to give vibration.

[5-4. Production display unit]
Next, the effect display unit 1900 of the game board 4 will be described with reference to FIGS. 10 is a front exploded perspective view showing a configuration example when the effect display unit is viewed from the front, and FIG. 11 is a rear exploded perspective view showing a configuration example when the effect display unit is viewed from the rear. These are sectional views showing an example of a sectional configuration of the effect display unit.

[5-4-1. Structure of production display unit]
As shown in FIGS. 10 and 11, the effect display unit 1900 includes a frame 5000c formed in a box shape that is opened at the rear, a main body 5000p accommodated in the frame 5000c, and a transparent back that blocks the rear of the frame 5000c. And a lid 5000m. On the bottom plate of the frame 5000c, an opening 5000ca to be a display area of the effect display unit 1900 is formed.

  Protrusions 5000cb are formed at the center of the left side and the center of the right side of the frame 5000c, respectively. The projecting portion 550cb is formed with an opening at the back thereof, and has a function as a wiring port for passing electric wiring through various electric members accommodated in the liquid crystal display unit 1900. The left and right sides of the frame 5000c have mounting holes for attaching the effect display unit 1900 to other members (back box 3001 of the back unit 3000 of the game board 4) above and below the protrusion 5000cb. Each of the mounting protrusions is formed. Further, a plurality of ribs 5000cc having a rectangular parallelepiped shape are formed on the inner side surface of the frame 5000c excluding the projecting portion 5000cb from the front back surface side of the frame 5000c toward the rear, and spaced apart by a predetermined interval. In addition to functioning as a reinforcing member, it also has a function as a fixing auxiliary member that restricts movement of the main body 5000p accommodated in the frame 5000c in the vertical and horizontal directions.

  The effect display unit 1900 includes a liquid crystal panel 5000e, a first light guide plate 5000d, a second light guide plate 5000f, and a third guide between the frame 5000c and the back cover 5000m from the frame 5000c toward the back cover 5000m. By being sandwiched between the comb-like upper fixing member 5000a and the comb-like lower fixing member 5000b in the order of the optical plate 5000g, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k, respectively. The main body 5000p arranged so as to be parallel is housed. Although detailed description will be given later, each of the light guide plates 5000d, 5000f, 5000g, 5000h, 5000i, and 5000k reflects, for example, the light incident from the end surfaces such as the upper and lower surfaces to diffuse the light. This is a type of panel that emits uniform light from its surface.

  The liquid crystal panel 5000e is a transparent rectangular flat plate member of 12 inches (image size 800 × 600 dots).

  Although the liquid crystal panel 5000e will be described in detail later, the liquid crystal panel 5000e includes two polarizing layers whose polarization directions are set to a predetermined angle (for example, a right angle), and a large number of layers are provided between the two polarizing layers. A liquid crystal layer in which liquid crystal molecules are arranged. Note that description of other components such as an alignment film is omitted. In the liquid crystal panel 5000e, for example, the amount of light transmitted is controlled by controlling the alignment state of the many liquid crystal molecules described above in accordance with the control of the energization state by the peripheral control board 4140. In the liquid crystal panel 5000e, for example, the arrangement of each liquid crystal molecule in each portion changes according to the energization state to a pair of transparent electrodes provided for each of a plurality of transparent dots corresponding to the three primary colors. In addition, the amount of light that passes through one polarizing layer can be adjusted.

  The first light guide plate 5000d is a flat transparent panel, and a light guide plate decoration substrate 5000d1 (one light source) is provided on the upper end surface of the transparent panel, and is guided to the lower end surface of the transparent panel. An under-lighting decorative substrate 5000d2 (the other light source) is provided.

  The first light guide plate 5000d is a surface of the first light guide plate 5000d when viewed from the front when light enters the interior of the light guide plate upper decorative substrate 5000d1 and the light guide plate lower decorative substrate 5000d2. The whole (hereinafter referred to as “planar shape”) has a light emitting region 5000d4 as a surface light source. In the first light guide plate 5000d, a large number of reflecting portions are processed and formed in the light emitting region 5000d4 on the back surface (back surface) of the transparent panel, so that the light emitting region 5000d4 becomes a surface light source when the light source is turned on.

  In the first light guide plate 5000d, the light (first light) output from the light guide plate upper decorative substrate 5000d1 enters from the upper end surface and travels through the transparent panel, as described above. The light is reflected by a large number of reflecting portions formed on the (back surface), and is output in a planar shape mainly from the front. On the other hand, the light (second light) output from the lower decorative board 5000d2 of the light guide plate is incident from the lower end surface thereof and is reflected by a large number of reflecting portions while traveling through the transparent panel, and has a planar shape mainly from the front. Is output.

  That is, the first light guide plate 5000d emits light in the front direction (in the direction of the opening 5000ca of the frame 5000c) from the light emitting region 5000d4. As a result, planar light that is surface-emitted by the first light guide plate 5000d is incident on the liquid crystal panel 5000e. When viewed from the front, the liquid crystal panel 5000e is controlled according to the control mode of the liquid crystal panel 5000e. Therefore, the image can be easily visually recognized on the inner portion of the planar shape.

  The second light guide plate 5000f is a flat transparent panel, and a light guide plate decoration substrate 5000f1 (one light source) is provided on the upper end surface of the transparent panel, and is guided to the lower end surface of the transparent panel. A light-plate lower decorative substrate 5000f2 (the other light source) is provided.

  The second light guide plate 5000f is formed in a predetermined number of circular shapes when viewed from the front when light is incident on the interior of the light guide plate upper decorative substrate 5000f1 and the light guide plate lower decorative substrate 5000f2. Non-light-emitting area 5000f3 and light emission as a surface light-emitting source formed in a planar shape excluding the non-light-emitting area 5000f3 and having a hole (hereinafter referred to as a "planar shape with a hole"). And a region 5000f4. In the second light guide plate 5000f, a large number of reflecting portions are processed and formed in the light emitting area 5000f4 on the back surface (back surface) of the transparent panel, so that the light emitting area 5000f4 becomes a surface light source by turning on the light source. On the other hand, no emission parts are formed in the predetermined number of non-light emitting areas 5000f3, and the plurality of non-light emitting areas 5000f3 are not used as surface light emitting sources due to the lighting of the light source.

  In the second light guide plate 5000f, the light (first light) output from the light guide plate upper decorative substrate 5000f1 enters from the upper end surface and travels through the transparent panel, as described above. The light is reflected by a large number of reflecting portions formed on the (rear surface), and is output in a planar shape mainly having holes from the front. On the other hand, the light (second light) output from the decorative substrate under the light guide plate 5000f2 is incident from the lower end surface thereof, reflected by a number of reflecting portions while traveling through the transparent panel, and a plane mainly having holes from the front. Output as a shape.

  That is, the second light guide plate 5000f emits light from the light emitting region 5000f4 in the front direction (in the direction of the opening 5000ca of the frame 5000c). As a result, plane-shaped light that is surface-emitted by the second light guide plate 5000f is made incident on the liquid crystal panel 5000e. When viewed from the front, the liquid crystal panel 5000e has a control mode. Accordingly, in the liquid crystal panel 5000e, the image can be easily visually recognized in the inner portion excluding the hole in the planar shape having the hole.

  The third light guide plate 5000g is a flat transparent panel, and a light guide plate decoration substrate 5000g1 (one light source) is provided on the upper end surface of the transparent panel, and is guided to the lower end surface of the transparent panel. A light-plate lower decorative substrate 5000g2 (the other light source) is provided.

  When the third light guide plate 5000g is viewed from the front when light enters the interior of the light guide plate upper decorative substrate 5000g1 and the light guide plate lower decorative substrate 5000g2, the third light guide plate 5000g is not in contact with the second light guide plate 5000f. In addition to the position corresponding to the light emitting region 5000f3, a non-light emitting region 5000g3 formed in a predetermined number of circular shapes, and a planar shape excluding the non-light emitting region 5000g3 and having a hole (hereinafter referred to as “hole opened” And a light emitting region 5000g4 as a surface light emitting source formed in a plane shape. In the third light guide plate 5000g, the light emitting area 5000g4 becomes a surface light source by turning on the light source by processing and forming a large number of reflecting portions in the light emitting area 5000g4 on the back surface (back surface) of the transparent panel. Thus, no emission part is formed in the plurality of non-light emitting areas 5000g3, and the non-light emitting areas 5000g3 do not become surface emitting sources at all due to the lighting of the light source.

  In the third light guide plate 5000g, the light (first light) output from the decorative substrate 5000g1 on the light guide plate enters from the upper end surface of the third light guide plate 5000g1 and travels through the transparent panel as described above. The light is reflected by a large number of reflecting portions formed on the (rear surface), and is output as a planar shape mainly having holes from the front. On the other hand, the light (second light) output from the decorative substrate under the light guide plate 5000g2 is incident from the lower end surface thereof, reflected by a number of reflecting portions while traveling through the transparent panel, and a plane mainly having holes from the front. Output as a shape.

  That is, the third light guide plate 5000g emits light in the front direction (in the direction of the opening 5000ca of the frame 5000c) from the light emitting region 5000g4. As a result, plane-shaped light that is surface-emitted by the third light guide plate 5000g and has a hole is incident on the liquid crystal panel 5000e. When viewed from the front, the liquid crystal panel 5000e has a control mode. Accordingly, in the liquid crystal panel 5000e, the image can be easily visually recognized in the inner portion excluding the hole in the planar shape having the hole.

  The fourth light guide plate 5000h is a flat plate-like transparent panel. A light guide plate decoration substrate 5000h1 (one light source) is provided on the upper end surface of the transparent panel, and the fourth light guide plate 5000h is guided to the lower end surface of the transparent panel. A light-plate lower decorative substrate 5000h2 (the other light source) is provided.

  When the fourth light guide plate 5000h is viewed from the front when light enters the interior of the light guide plate upper decorative substrate 5000h1 and the light guide plate lower decorative substrate 5000h2, the fourth light guide plate 5000h In addition to the positions corresponding to the light emitting area 5000f3 and the non-light emitting area 5000g3 of the third light guide plate 5000g, a non-light emitting area 5000h3 formed in a predetermined number of circular shapes and a planar shape excluding the non-light emitting area 5000h3, respectively. And a light emitting region 5000h4 as a surface light emitting source formed in a shape with a hole (hereinafter referred to as a "planar shape with a hole"). In the fourth light guide plate 5000h, the light emitting area 5000h4 becomes a surface light emitting source by turning on the light source by processing and forming a large number of reflection parts in the light emitting area 5000h4 on the back surface (back surface) of the transparent panel. Thus, no emitting part is formed in the plurality of non-light-emitting areas 5000h3, and the non-light-emitting areas 5000h3 do not become surface emitting sources at all due to the lighting of the light source.

  In the fourth light guide plate 5000h, the light (first light) output from the light guide plate upper decorative substrate 5000h1 enters from the upper end surface thereof and travels through the transparent panel, as described above. The light is reflected by a large number of reflecting portions formed on the (rear surface), and is output as a planar shape mainly having holes from the front. On the other hand, the light (second light) output from the decorative substrate under the light guide plate 5000g2 is incident from the lower end surface thereof, reflected by a number of reflecting portions while traveling through the transparent panel, and a plane mainly having holes from the front. Output as a shape.

  That is, the fourth light guide plate 5000h emits light in the front direction (in the direction of the opening 5000ca of the frame 5000c) from the light emitting region 5000h4. As a result, plane-shaped light that is surface-emitted by the fourth light guide plate 5000h and has a hole is incident on the liquid crystal panel 5000e. When viewed from the front, the liquid crystal panel 5000e has a control mode. Accordingly, in the liquid crystal panel 5000e, the image can be easily visually recognized in the inner portion excluding the hole in the planar shape having the hole.

  The fifth light guide plate 5000i is a flat transparent panel, and a light guide plate decoration substrate 5000i1 (one light source) is provided on the upper end surface of the transparent panel, and is guided to the lower end surface of the transparent panel. A light-plate underside decorative substrate 5000i2 (the other light source) is provided.

  The fifth light guide plate 5000i is formed in a plurality of polygonal shapes when viewed from the front when light enters the interior of the light guide plate upper decorative substrate 5000i1 and the light guide plate lower decorative substrate 5000i2. A non-light emitting area 5000i3 and a planar shape excluding the non-light emitting area 5000i3 with a polygonal hole (hereinafter referred to as a "planar shape with a polygonal hole"). In the fifth light guide plate 5000i, a large number of reflective portions are processed and formed in the plurality of light emitting regions 5000i4 on the back surface (rear surface) of the transparent panel. While the plurality of light emitting areas 5000i4 become surface light sources when turned on, no emitting part is formed in the plurality of non-light emitting areas 5000i3, and when the light source is turned on, the non-light emitting areas 5000 3 is not exactly the surface-emitting sources, respectively.

  In the fifth light guide plate 5000i, the light output from the decorative substrate 5000i1 on the light guide plate (first light) enters from the upper end surface and travels through the transparent panel, as described above. The light is reflected by a large number of reflecting portions formed on the (rear surface), and is output as a planar shape mainly having polygonal holes opened from the front. On the other hand, the light (second light) output from the lower decorative board 5000i2 of the light guide plate is incident from the lower end surface and is reflected by a number of reflecting portions while traveling through the transparent panel, and polygonal holes are mainly formed from the front. Output as an open planar shape.

  That is, the fifth light guide plate 5000i emits light in the front direction (in the direction of the opening 5000ca of the frame 5000c) from the plurality of light emitting regions 5000i4. As a result, the liquid crystal panel 5000e receives plane-shaped light that is surface-emitted by the fifth light guide plate 5000i and has a polygonal hole. When viewed from the front, the liquid crystal panel 5000e According to the control mode, in the liquid crystal panel 5000e, images can be easily visually recognized in the inner portion excluding the polygonal holes in the planar shape having the polygonal holes.

  The sixth light guide plate 5000k is a flat transparent panel, and a light guide plate decoration substrate 5000k1 (one light source) is provided on the upper end surface of the transparent panel, and is guided to the lower end surface of the transparent panel. An under-lighting decorative board 5000k2 (the other light source) is provided.

  The sixth light guide plate 5000k is an upper side of the sixth light guide plate 5000k when viewed from the front when light is incident on the interior of the light guide plate upper decorative substrate 5000k1 and the light guide plate lower decorative substrate 5000k2. A non-light-emitting region 5000k3 formed in a thick strip from the bottom to the bottom, and a flat strip shape excluding the non-light-emitting region 5000k3 (hereinafter referred to as a “planar narrow strip shape”). And a light emitting region 5000k4 as a surface emitting source. In the sixth light guide plate 5000k, the light emitting area 5000k4 becomes a surface light source by turning on the light source by processing and forming a large number of reflecting portions in the light emitting area 5000k4 on the back surface (back surface) of the transparent panel. Thus, no emitting part is formed in the non-light emitting area 5000k3, and the non-light emitting area 5000k3 does not become a surface light emitting source at all due to the lighting of the light source.

  In the sixth light guide plate 5000k, the light output from the decorative substrate 5000k1 on the light guide plate (first light) is incident from the upper end surface and travels through the transparent panel, as described above. The light is reflected by a large number of reflecting portions formed on the (rear surface), and is mainly output from the front as a flat strip shape. On the other hand, the light (second light) output from the decorative substrate under the light guide plate 5000k2 is incident from its lower end surface and reflected by a number of reflecting portions while traveling through the transparent panel, Is output.

  That is, the sixth light guide plate 5000k emits light in the front direction (in the direction of the opening 5000ca of the frame 5000c) from the light emitting region 5000k4. As a result, light in the form of a flat strip that is surface-emitted by the sixth light guide plate 5000k is incident on the liquid crystal panel 5000e, and when viewed from the front, according to the control mode of the liquid crystal panel 5000e. In the liquid crystal panel 5000e, an image can be easily visually recognized in the inner portion of the flat strip shape.

  As described above, the first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000g, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the first light guide plate 5000d, which are arranged in order from the front side. Although the liquid crystal panel 5000e has a rectangular shape depending on which of the six light guide plates 5000k emits light, it is completely different from the liquid crystal panel 5000e having another physical shape, A display area where the image is displayed appears.

[5-4-2. Sectional structure of production display unit]
The structure of the effect display unit 1900 will be described in more detail. As shown in FIG. 12, the effect display unit 1900 has the above-described effect display unit 1900 formed by attaching a back cover 5000m to the frame 5000c. As described above, the liquid crystal panel 5000e, the first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000g, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k. They are arranged and accommodated so as to be parallel to each other. Note that the opening 5000ca serving as a display area of the effect display unit 1900 formed on the front surface of the frame 5000c is formed in a rectangular shape smaller than the outer periphery of the rectangular liquid crystal panel 5000e of the liquid crystal panel 5000e.

  The comb-shaped upper fixing member 5000a and the comb-shaped lower fixing member 5000b are formed in the same shape, and a plurality of comb teeth are formed apart from each other by a predetermined distance, thereby forming a groove between the comb teeth. Each is formed, and a protrusion is formed toward the opposing wall of each groove. The liquid crystal panel 5000e, the first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000g, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k are comb-like upper side. When sandwiched between the fixing member 5000a and the comb-like lower fixing member 5000b, the liquid crystal panel 5000e, the first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000g, the fourth light guide plate 5000h, The upper end surface and the lower end surface of the fifth light guide plate 5000i and the sixth light guide plate 5000k are respectively engaged with the protrusions formed on the opposing walls of each groove.

  Respective groove depths into which the first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000g, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k are inserted. The first light guide plate 5000d, the second light guide plate 5000f, and the third guide are provided on the side, that is, on the side of the comb teeth of the comb-shaped upper fixing member 5000a and on the side of the comb teeth of the lower comb-shaped fixing member 5000b. A substrate housing space is formed for housing the substrate for emitting light to the upper end surface and the lower end surface of the light plate 5000g, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k. , The first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000g, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the respective grooves into which the sixth light guide plate 5000k are inserted. So Each communicate with each other.

  More specifically, in the substrate housing space 5000d5 of the comb-shaped upper fixing member 5000a into which the first light guide plate 5000d is inserted, a large number of LEDs 5000d6 (in this embodiment, white LEDs are employed as the LEDs 5000d6). Is mounted on the light guide plate decoration substrate 5000d1 and is not shown in FIG. 12, but is a substrate storage space of the comb-like lower fixing member 5000b into which the first light guide plate 5000d is inserted. 5000d5 houses a light guide plate lower decorative board 5000d2 on which a large number of LEDs 5000d6 are mounted. The light guide plate upper decorative substrate 5000d1 and the light guide plate lower decorative substrate 5000d2 are formed from the respective side end surfaces of the comb-like upper fixing member 5000a and the comb-like lower fixing member 5000b. Each LED 5000d6 outputs light according to the energized state under the control of the peripheral control board 4140.

  These lights are reflected through the inside of the first light guide plate 5000d and output from the planar light emitting region 5000d4 toward the liquid crystal panel 5000e as described above. Due to the light thus reflected, the user's eyes can see an image on the inner portion of the planar shape through the liquid crystal panel 5000e in accordance with the control mode of the liquid crystal panel 5000e.

  The first light guide plate 5000d is configured such that the first light guide plate 5000d is a transparent panel when the LEDs 5000d6 provided on the light guide plate upper decorative substrate 5000d1 and the light guide plate lower decorative substrate 5000d2 are not emitting light (normal state). Since it is configured, the user's eyes can visually recognize the rear of the first light guide plate 5000d through the first light guide plate 5000d.

  In the substrate housing space 5000f5 of the comb-shaped upper fixing member 5000a into which the second light guide plate 5000f is inserted, a light guide plate on which a large number of LEDs 5000f6 (in this embodiment, white LEDs are employed as the LEDs 5000f6) is mounted. While the upper decorative substrate 5000f1 (one light source) is accommodated and not shown in FIG. 12, the substrate accommodating space 5000f5 of the comb-like lower fixing member 5000b into which the second light guide plate 5000f is inserted. Contains a light guide plate lower decorative substrate 5000f2 (the other light source) on which a large number of LEDs are mounted. The light guide plate upper decorative substrate 5000f1 and the light guide plate lower decorative substrate 5000f2 are formed from the respective side end surfaces of the comb upper fixing member 5000a and the comb lower fixing member 5000b. Each LED 5000f6 outputs light in accordance with the energized state under the control of the peripheral control board 4140, which is inserted into the board housing space 5000f5 of the lower fixing member 5000b.

  These lights are reflected through the inside of the second light guide plate 5000f, and are output toward the liquid crystal panel 5000e from the planar light emitting region 5000f4 having a hole as described above. According to the control mode of the liquid crystal panel 5000e, an image is visually recognized by the user's eyes through the liquid crystal panel 5000e on the inner portion excluding the holes in the planar shape with the holes. It becomes like this.

  In the second light guide plate 5000f, when the LEDs 5000f6 provided on the light guide plate upper decorative substrate 5000f1 and the light guide plate lower decorative substrate 5000f2 are not emitting light (normal state), the second light guide plate 5000f is a transparent panel. Since it is configured, the user's eyes can visually recognize the back of the second light guide plate 5000f through the second light guide plate 5000f.

  In the substrate housing space 5000g5 of the comb-shaped upper fixing member 5000a into which the third light guide plate 5000g is inserted, a light guide plate on which a large number of LEDs 5000g6 (in this embodiment, white LEDs are employed as the LEDs 5000g6) is mounted. While the upper decorative substrate 5000g1 (one light source) is accommodated and not shown in FIG. 12, the substrate accommodating space 5000g5 of the comb-like lower fixing member 5000b into which the third light guide plate 5000g is inserted. Accommodates a light guide plate lower decorative substrate 5000g2 (the other light source) on which a large number of LEDs are mounted. The light guide plate upper decorative substrate 5000g1 and the light guide plate lower decorative substrate 5000g2 are formed from the respective side end surfaces of the comb-like upper fixing member 5000a and the comb-like lower fixing member 5000b. Each LED 5000g6 outputs light in accordance with the energized state under the control of the peripheral control board 4140, which is inserted into the board housing space 5000g5 of the lower fixing member 5000b.

  These lights are reflected through the inside of the third light guide plate 5000g, and are output toward the liquid crystal panel 5000e from the planar light emitting region 5000g4 having a hole as described above. According to the control mode of the liquid crystal panel 5000e, an image is visually recognized by the user's eyes through the liquid crystal panel 5000e on the inner part of the planar shape with the holes except for the holes. Become so.

  The third light guide plate 5000g is a transparent panel when the LEDs 5000g6 provided on the light guide plate upper decorative substrate 5000g1 and the light guide plate lower decorative substrate 5000g2 are not emitting light (normal state). Since it is configured, the user's eyes can visually recognize the back of the third light guide plate 5000g through the third light guide plate 5000g.

  In the substrate housing space 5000h5 of the comb-shaped upper fixing member 5000a into which the fourth light guide plate 5000h is inserted, a light guide plate on which a large number of LEDs 5000h6 (in this embodiment, white LEDs are adopted as the LEDs 5000h6) is mounted. While the upper decorative substrate 5000h1 (one light source) is accommodated and not shown in FIG. 12, the substrate accommodating space 5000h5 of the comb-like lower fixing member 5000b into which the fourth light guide plate 5000h is inserted. Accommodates a light guide plate lower decorative substrate 5000h2 (the other light source) on which a large number of LEDs are mounted. The light guide plate upper decorative substrate 5000h1 and the light guide plate lower decorative substrate 5000h2 are formed from the respective side end surfaces of the comb upper fixing member 5000a and the comb lower fixing member 5000b. Each LED 5000h6 outputs light according to the energized state under the control of the peripheral control board 4140.

  These lights are reflected through the inside of the fourth light guide plate 5000h, and are output toward the liquid crystal panel 5000e from the planar light emitting region 5000h4 having a hole as described above. According to the control mode of the liquid crystal panel 5000e, an image is visually recognized by the user's eyes through the liquid crystal panel 5000e on the inner part of the planar shape with the holes except for the holes. Become so.

  The fourth light guide plate 5000h is a transparent panel in a state where the LEDs 5000h6 provided on the light guide plate upper decorative substrate 5000h1 and the light guide plate lower decorative substrate 5000h2 are not emitting light (normal state). Since it is comprised, a user's eyes can visually recognize the back of the 4th light guide plate 5000h via the 4th light guide plate 5000h.

  In the substrate housing space 5000i5 of the comb-shaped upper fixing member 5000a into which the fifth light guide plate 5000i is inserted, a light guide plate on which a number of LEDs 5000i6 (in this embodiment, white LEDs are adopted as the LEDs 5000i6) is mounted. While the upper decorative substrate 5000i1 (one light source) is accommodated and not shown in FIG. 12, the substrate accommodating space 5000i5 of the comb-like lower fixing member 5000b into which the fifth light guide plate 5000i is inserted. Contains a light guide plate lower decorative substrate 5000i2 (the other light source) on which a large number of LEDs are mounted. The light guide plate upper decorative substrate 5000i1 and the light guide plate lower decorative substrate 5000i2 are formed from the respective side end surfaces of the comb-like upper fixing member 5000a and the comb-like lower fixing member 5000b. Each LED 5000i6 outputs light in accordance with the energized state under the control of the peripheral control board 4140, which is inserted into the board accommodation space 5000i5 of the lower fixing member 5000b.

  These lights are reflected through the inside of the fifth light guide plate 5000i, and are output toward the liquid crystal panel 5000e from the planar light emitting region 5000i4 having the polygonal holes as described above. According to the control mode of the liquid crystal panel 5000e, the reflected light causes the user's eyes to pass through the liquid crystal panel 5000e and display an image on the inner portion of the planar shape having a polygonal hole. Are now visible.

  The fifth light guide plate 5000i is a transparent panel when the LEDs 5000i6 provided on the light guide plate upper decorative substrate 5000i1 and the light guide plate lower decorative substrate 5000i2 are not emitting light (normal state). Since it is configured, the user's eyes can visually recognize the back of the fifth light guide plate 5000i through the fifth light guide plate 5000i.

  In the substrate housing space 5000k5 of the comb-shaped upper fixing member 5000a into which the sixth light guide plate 5000k is inserted, a light guide plate on which a number of LEDs 5000k6 (in this embodiment, white LEDs are employed as the LEDs 5000k6) is mounted. The upper decorative substrate 5000k1 (one light source) is accommodated, and although not shown in FIG. 12, the substrate accommodating space 5000k5 of the comb-like lower fixing member 5000b into which the sixth light guide plate 5000k is inserted. Contains a light guide plate lower decorative board 5000k2 (the other light source) on which a large number of LEDs are mounted. The light guide plate upper decorative substrate 5000k1 and the light guide plate lower decorative substrate 5000k2 are formed from the respective side end surfaces of the comb-like upper fixing member 5000a and the comb-like lower fixing member 5000b. Each LED 5000k6 outputs light in accordance with the energized state under the control of the peripheral control board 4140, which is inserted into the board accommodation space 5000k5 of the lower fixing member 5000b.

  These lights are reflected through the inside of the sixth light guide plate 5000k, and are output from the light emitting region 5000k4 having a flat strip shape toward the liquid crystal panel 5000e as described above. Due to the reflected light, the user's eyes can see an image on the inner side of the flat strip through the liquid crystal panel 5000e in accordance with the control mode of the liquid crystal panel 5000e.

  The sixth light guide plate 5000k is a transparent panel when the LEDs 5000k6 provided on the light guide plate upper decorative substrate 5000k1 and the light guide plate lower decorative substrate 5000k2 are not emitting light (normal state). Since it is configured, the user's eyes can see the back of the sixth light guide plate 5000k through the sixth light guide plate 5000k.

  In the present embodiment, among the display areas of the transmissive liquid crystal panel 5000e, the liquid crystal panel 5000e is transmissive in areas where no image or the like is displayed on the liquid crystal panel 5000e. What is present behind the transmission type liquid crystal panel 5000e corresponding to this region, that is, behind the effect display unit 1900 can be seen.

  Here, the principle of the liquid crystal panel 5000e will be briefly described. The liquid crystal shutter is configured by sealing liquid crystal between two glass substrates formed of an alignment film, a transparent electrode, a polarizing plate, etc., so that a voltage can be applied between the glass substrates of the liquid crystal shutter. It has become. More specifically, the liquid crystal shutter includes a pixel drive side substrate module, a counter electrode side basic module, and a liquid crystal molecular layer (liquid crystal layer). The pixel drive side substrate module has a polarizing plate, a glass substrate, a transparent conductive film (pixel electrode, drive transistor) and an alignment film in order from the outside (the light incident side, that is, the side where the light guide plate as a backlight is disposed). Are stacked. In the counter electrode side basic module, a polarizing plate, a glass substrate, a color filter, a transparent electrode film (counter electrode), and an alignment film are laminated in order from the outside (the side opposite to the outside in the pixel drive side substrate module). The liquid crystal molecular layer is disposed between the pixel driving side substrate module and the counter electrode side basic module. That is, the polarizing plate, the glass substrate, the transparent electrode film, and the alignment film are paired.

  The transparent conductive film is for applying a voltage between the pixel electrode and the counter electrode (that is, between two glass substrates), and is made of a transparent electrode material such as ITO so as not to hinder display. Yes.

  The alignment film is a film for aligning liquid crystal molecules in a certain direction, and is formed of a polyimide resin or the like on the transparent conductive film.

  The polarizing plate is an optical film that allows only light oscillating in the same direction as the transmission axis from natural light emitted from a light guide plate as a backlight.

  The driving transistor is one transistor for each pixel of the pixel driving module, and controls the brightness of the liquid crystal shutter.

  The color filter is a filter in which red, green, and blue, which are the three primary colors of light, are arranged for each pixel for image colorization.

  The liquid crystal molecules in the liquid crystal molecular layer have the property of changing the alignment when a voltage is applied between the two glass substrates. The amount of transmitted light is adjusted according to the voltage applied at this time.

  In addition, it is comprised so that a voltage can be applied corresponding to each of the three primary colors of light, red, green, and blue, and when a voltage is applied to red, the arrangement of liquid crystal molecules corresponding to this voltage is applied. When the voltage is applied to green, the alignment of liquid crystal molecules changes accordingly, and when the voltage is applied to blue, the alignment of liquid crystal molecules changes accordingly. The degree of change in the arrangement of liquid crystal molecules varies depending on the magnitude of the voltage. By adjusting the voltage, the transmission amount of the liquid crystal shutter can be changed for light of any one color of red, green, and blue. it can. In this way, the liquid crystal shutter can add any color to the transmitted light using the three primary colors.

  As for the arrangement of liquid crystal molecules, there are a normally white mode and a normally black mode. In this embodiment, a normally black mode is adopted. The normally white mode is a structure in which liquid crystal is sandwiched between polarizing plates, and light passes through when white is not applied and white is displayed on the screen, while light is applied when voltage is applied. Is a mode in which black is displayed on the screen. In the normally black mode, in the structure in which the liquid crystal molecular layer is sandwiched between the polarizing plates, when the voltage is not applied, the light is blocked and black is displayed on the screen, whereas the voltage is applied. Sometimes it is a mode in which light passes and white is displayed on the screen.

  The liquid crystal panel 5000e has a large number of pixels arranged by a liquid crystal shutter. A pixel is a minimum unit point having color information. When one pixel transmits light of all colors of red, green, and blue through the liquid crystal shutter with the same transmission amount, white (transparent) is obtained. Only red light per pixel passes through the liquid crystal shutter and turns red. Similarly, when only green light in one pixel passes through the liquid crystal shutter, it becomes green, and when only blue light in one pixel passes through the liquid crystal shutter, it becomes blue. Further, when light of a color mixed by changing the transmission amounts of red, green, and blue in one pixel is transmitted through the liquid crystal shutter, the mixed color is obtained. A desired image can be displayed on the liquid crystal panel 5000e by coloring each pixel constituting the liquid crystal panel 5000e.

  The peripheral control board 4140 controls the transmission type liquid crystal panel 5000e in the effect display unit 1900 to display an effect image as a moving image according to the progress of the game, and the first light guide plate 5000d and the second light guide plate 5000d. The light guide plate 5000f, the third light guide plate 5000g, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k are controlled to emit surface light. Thus, according to the principle of the liquid crystal panel 5000e described above, the transmissive liquid crystal panel 5000e in the effect display unit 1900 has an effect image as a moving image corresponding to the progress of the game in the area emitted from the light guide plate as the backlight. Can be visually recognized, and rearward visual recognition is blocked. On the other hand, for a non-light emitting area that does not emit light from the light guide plate as the backlight, the player cannot visually recognize the effect image regardless of whether or not the effect image is controlled to be displayed in this area ( However, there is a possibility that light from other sources can be visually recognized through the liquid crystal shutter), and if a voltage is applied, the player can visually recognize the rear through the non-light emitting area.

  Note that the above-described effect display unit 1900 may be configured such that a liquid crystal shutter is disposed and accommodated on the rear surface of each light guide plate. Specifically, between the frame 5000c and the back cover 5000m, the liquid crystal panel 5000e, the first light guide plate 5000d, the liquid crystal shutter A, the second light guide plate 5000f, from the frame 5000c toward the back cover 5000m, The order of liquid crystal shutter B, third light guide plate 5000g, liquid crystal shutter C, fourth light guide plate 5000h, liquid crystal shutter D, fifth light guide plate 5000i, liquid crystal shutter E, sixth light guide plate 5000k, and liquid crystal shutter F. Thus, the main body 5000p arranged so as to be parallel is accommodated by being sandwiched between the comb-like upper fixing member 5000a and the comb-like lower fixing member 5000b.

  The liquid crystal shutters A to F are in the form of a sheet, for example, a transparent polymer film in which small droplets of nematic liquid crystals (called capsules) are dispersed and sandwiched between two polyester films with a transparent conductive film. When no liquid crystal is applied, liquid crystals represented as rod-like molecules are aligned along the inner wall of the capsule, and the incident light is reflected on the surface of the capsule by the difference in refractive index between the polymer and liquid crystal and the birefringence of the liquid crystal. As a result, the light cannot be traveled straight and is scattered, and the liquid crystal shutters A to F appear opaque (diffused state). In addition, when a voltage is applied, the liquid crystal molecules try to line up parallel to the direction in which the voltage is applied, and are aligned perpendicular to the electrodes, so that if the liquid crystal has a refractive index that matches that of the polymer, Even when there is no interface, the state becomes equal, and as a result, the light travels straight without being scattered, and the liquid crystal shutters A to F appear to be transparent (non-diffused state). Switching control of the liquid crystal shutters A to F to transparent / opaque is performed by, for example, a peripheral control board 4140 (peripheral control MPU in a peripheral control unit described later).

  The liquid crystal shutter A is disposed behind the first light guide plate 5000d along the rear surface of the first light guide plate 5000d, and corresponds to the planar shape described above behind the light emitting region 5000d4 of the first light guide plate 5000d. Consists of segments. In the case of the liquid crystal shutter A, when the light emitting region 5000d4 is caused to emit light, a voltage is not applied to the segment portion, and a diffusion state (milky white) is obtained. In this case, a part of the light is reflected on the milky white segment and is directed forward. This also illuminates the above-mentioned planar inner portion of the liquid crystal panel 5000e from behind. For this reason, the image on the liquid crystal panel 5000e can be visually recognized more clearly. On the other hand, when the light emitting region 5000d4 is not caused to emit light, a voltage is applied to the segment portion to make a non-diffusing state (transparent) that does not diffuse the transmitted light. Further, when any one of the second light guide plate 5000f to the sixth light guide plate 5000k is used as a surface light source, a voltage is always applied to the segment portion on the liquid crystal shutter A side. The entire liquid crystal shutter A is controlled to be in a non-diffusing state (transparent).

  The liquid crystal shutter B is disposed behind the second light guide plate 5000f along the rear surface of the second light guide plate 5000f, and the above-described hole is opened behind the light emitting region 5000d4 of the second light guide plate 5000f. A segment corresponding to the shape and other segments corresponding to other regions are formed. In the case of the liquid crystal shutter B, when the light emitting region 5000f4 is caused to emit light, a voltage is not applied to a segment portion corresponding to a planar shape with a hole, and a diffusion state (milky white) is obtained. In this case, a part of the light is reflected on the milky white segment and is directed forward. This also illuminates the planar inner portion of the liquid crystal panel 5000e with the above-described holes from behind, and the boundary between the light emitting region 5000f4 and other portions becomes clear. For this reason, the image on the liquid crystal panel 5000e can be visually recognized more clearly. On the other hand, when the light emitting region 5000f4 is not caused to emit light, a voltage is applied to the segment portion corresponding to the planar shape with a hole so that the transmitted light is not diffused (transparent). The other segments are controlled so that a voltage is always applied, and are in a non-diffusion state (transparent). Further, when any one of the first light guide plate 5000d and the third light guide plate 5000g to the sixth light guide plate 5000k is used as a surface light source, a plane with a hole on the liquid crystal shutter B side. Control is performed so that voltages are always applied to the segment portion corresponding to the shape and the other segments, and the entire liquid crystal shutter B is set to a non-diffusing state (transparent).

  The liquid crystal shutter C is disposed behind the third light guide plate 5000g along the rear surface of the third light guide plate 5000g, and the above-described hole is opened behind the light emitting region 5000g4 of the third light guide plate 5000g. A segment corresponding to the shape and other segments corresponding to other regions are formed. In the case of the liquid crystal shutter C, when the light emitting area 5000g4 is caused to emit light, a voltage is not applied to the segment portion corresponding to the planar shape with a hole, and a diffusion state (milky white) is obtained. In this case, a part of the light is reflected on the milky white segment and is directed forward. This also illuminates the planar inner portion of the liquid crystal panel 5000e with the above-described holes from behind, and the boundary between the light emitting region 5000g4 and other portions becomes clear. For this reason, the image on the liquid crystal panel 5000e can be visually recognized more clearly. On the other hand, when the light emitting region 5000g4 is not caused to emit light, a voltage is applied to the segment portion corresponding to the planar shape with a hole so that the transmitted light is not diffused (transparent). The other segments are controlled so that a voltage is always applied, and are in a non-diffusion state (transparent). When any one of the first light guide plate 5000d, the second light guide plate 5000f, and the fourth light guide plate 5000h to the sixth light guide plate 5000k is used as the surface light source, the liquid crystal shutter C side Are controlled so that voltages are always applied to the segment portion corresponding to the planar shape with holes and other segments, and the entire liquid crystal shutter C is set to the non-diffusing state (transparent).

  The liquid crystal shutter D is disposed behind the fourth light guide plate 5000h so as to be along the rear surface of the fourth light guide plate 5000h, and the above-described hole is opened behind the light emitting region 5000h4 of the fourth light guide plate 5000h. A segment corresponding to the shape and other segments corresponding to other regions are formed. In the case of the liquid crystal shutter D, when the light emitting region 5000h4 is caused to emit light, a diffusion state (milky white) is applied without applying a voltage to a segment portion corresponding to a planar shape with a hole. In this case, a part of the light is reflected on the milky white segment and is directed forward. This also illuminates the planar inner portion of the liquid crystal panel 5000e with the above-described holes from behind, and the boundary between the light emitting region 5000h4 and other portions becomes clear. For this reason, the image on the liquid crystal panel 5000e can be visually recognized more clearly. On the other hand, when the light emitting region 5000h4 is not caused to emit light, a voltage is applied to the segment portion corresponding to the planar shape with a hole so that the transmitted light is not diffused (transparent). The other segments are controlled so that a voltage is always applied, and are in a non-diffusion state (transparent). When any one of the first light guide plate 5000d to the third light guide plate 5000g, the fifth light guide plate 5000i, and the sixth light guide plate 5000k is used as the surface light source, the liquid crystal shutter D side is used. Are controlled so that voltages are always applied to the segment portion corresponding to the planar shape with holes and the other segments, and the entire liquid crystal shutter D is set to the non-diffusing state (transparent).

  The liquid crystal shutter E is disposed behind the fifth light guide plate 5000i along the rear surface of the fifth light guide plate 5000i, and the polygonal holes described above are provided behind the light emitting region 5000i4 of the fifth light guide plate 5000i. A segment corresponding to the open planar shape and other segments corresponding to other regions are formed. In the case of the liquid crystal shutter E, when the light emitting region 5000i4 is caused to emit light, a voltage is not applied to a segment portion corresponding to a planar shape with a polygonal hole, and a diffusion state (milky white) is obtained. In this case, a part of the light is reflected on the milky white segment and is directed forward. This also illuminates the planar inner portion of the liquid crystal panel 5000e with the above-described polygonal holes from behind, and the boundary between the light emitting region 5000i4 and other portions becomes clear. For this reason, the image on the liquid crystal panel 5000e can be visually recognized more clearly. On the other hand, when the light emitting region 5000i4 is not caused to emit light, a voltage is applied to the segment portion corresponding to the planar shape having a polygonal hole so that the transmitted light is not diffused (transparent). The other segments are controlled so that a voltage is always applied, and are in a non-diffusion state (transparent). Further, when any one of the first light guide plate 5000d to the fourth light guide plate 5000h and the sixth light guide plate 5000k is used as a surface light source, a polygonal hole on the liquid crystal shutter E side is formed. Control is performed so that voltages are always applied to the segment portion corresponding to the open planar shape and the other segments, and the entire liquid crystal shutter E is set to a non-diffusing state (transparent).

  The liquid crystal shutter F is disposed behind the sixth light guide plate 5000k along the rear surface of the sixth light guide plate 5000k, and has the above-described flat strip shape behind the light emitting region 5000k4 of the sixth light guide plate 5000k. The segment includes a corresponding segment and another segment corresponding to another region. In the case of the liquid crystal shutter F, when the light emitting region 5000k4 is caused to emit light, the voltage is not applied to the segment portion corresponding to the shape of the thin flat strip and the diffusion state (milky white) is set. In this case, a part of the light is reflected on the milky white segment and is directed forward. This also illuminates the inside portion of the above-described flat strip shape of the liquid crystal panel 5000e from behind, and the boundary between the light emitting region 5000k4 and other portions becomes clear. For this reason, the image on the liquid crystal panel 5000e can be visually recognized more clearly. On the other hand, when the light emitting region 5000k4 is not caused to emit light, a voltage is applied to the segment portion corresponding to the flat strip shape so that the transmitted light is not diffused (transparent). The other segments are controlled so that a voltage is always applied, and are in a non-diffusion state (transparent). In addition, when any one of the first light guide plate 5000d to the fifth light guide plate 5000i is used as a surface light source, a segment portion corresponding to the flat strip shape on the liquid crystal shutter F side, and others The segments are controlled so that voltages are always applied to the segments, and the entire liquid crystal shutter F is set to a non-diffusing state (transparent).

[6. Function display unit]
Next, the function display unit 1180 in the game board 4 will be described with reference to FIG. This function display unit 1180 is mounted and disposed at a predetermined position of the front component member 1110. FIG. 13 is an enlarged front view showing the function display unit in the game board in a state of being attached to the pachinko gaming machine.

  As shown in an enlarged view in FIG. 13, the function display unit 1180 is a game state display composed of one LED for displaying a game state that is changed by a game ball driven into the game area 1100 at the left end when viewed from the front. An upper special symbol memory display 1184 for displaying the number of suspensions related to the reception of the game ball to the first start port 2101, which is composed of two LEDs arranged in the vertical direction on the right side of the game status indicator 1183, The upper special symbol memory display 1184 is arranged on the right side, and is composed of one 7-segment LED for displaying the first special lottery result drawn as a first special symbol by lottery by receiving the game ball into the first starting port 2101. A special symbol display 1185 and an upper special symbol display 1185 are arranged diagonally on the right and are selected by receiving a game ball at the second starting port 2102. The lower special symbol display 1186 consisting of one 7-segment LED for displaying the second special lottery result as the second special symbol, and two LEDs arranged vertically on the right side of the lower special symbol display 1186 And a lower special symbol memory display 1187 for displaying the number of holdings relating to the reception of the game ball in the 2 start opening 2102.

  The display unit 1181 of the function display unit 1180 displays the number of suspensions related to the passage of the gate unit 2150 by the game balls arranged in an arc shape substantially along the inner rail 1113 from directly above the lower special symbol display 1186. The normal symbol memory display 1188 composed of the four LEDs and a normal lottery result that is placed on the lower side of the normal symbol memory display and drawn by passing the game ball through the gate portion 2150 is displayed as a normal symbol. The normal symbol display 1189 made of one LED and the normal symbol memory display 1188 are arranged side by side diagonally to the upper right, and the first prize lottery result or the second special lottery result is “big hit”, and the opening / closing of the big prize opening 2103 A round indicator 1190 composed of two LEDs for displaying the number of repetitions of the pattern (number of rounds).

  The gaming status indicator 1183 is a full-color LED that can change the emission color of red, green, and orange, and various gaming statuses ( For example, a normal state, a probability variation state, a time shortening state, a probability variation short state, a big hit gaming state, a small hit gaming state, etc.) can be displayed.

  The upper special symbol memory display 1184 suspends the start of variable display when a game ball is received at the first start port 2101 when the first special symbol cannot be displayed in a variable manner on the upper special symbol display 1185. The number of stored (stored) first special symbols that have been stored is displayed. In addition, the special symbol memory display 1184 has a first special symbol memory lamp 1184a and a first special symbol memory lamp 1184b made of predetermined LEDs. The first special symbol memory lamps 1184a and 1184b are turned on / off. The number of holds can be displayed by the blinking pattern. Specifically, for example, the first special symbol memory lamp 1184a is turned on and the first special symbol memory lamp 1184b is turned off when the number of holdings is one, and the first special symbol memory lamps 1184a and 1184b when the number of holdings is two. When the number of holds is 3, the first special symbol memory lamp 1184a blinks and the first special symbol memory lamp 1184b is lit. When the number of held is 4, the first special symbol memory lamps 1184a and 1184b are both It is blinking. In the present embodiment, up to four are reserved.

  The lower special symbol memory display 1187 suspends the start of variable display when a game ball is received at the second starting port 2102 when the second special symbol cannot be displayed in a variable manner on the lower special symbol display 1186. The number of stored (stored) second special symbols is displayed. The lower special symbol memory indicator 1187 has a second special symbol memory lamp 1187a and a second special symbol memory lamp 1187b made of predetermined LEDs. The number of holds can be displayed by the blinking pattern. Specifically, for example, the second special symbol memory lamp 1187a is turned on and the second special symbol memory lamp 1187b is turned off when the number of reserved is 1, and the second special symbol memory display lamp 1187a, When the number of holdings is three, the second special symbol memory lamp 1187a flashes and the second special symbol memory lamp 1187b is lit. When the number of holdings is four, the second special symbol memory lamps 1187a and 1187b are turned on. Both are blinking. In the present embodiment, up to four are reserved.

  The upper special symbol display 1185 and the lower special symbol display 1186 display the first special lottery result and the second special lottery result that are drawn by receiving the game balls to the first starting port 2101 and the second starting port 2102. The 7-segment LED stops after fluctuating for a predetermined time according to the special lottery result, and the first special lottery result and the second special lottery result depending on the emission pattern (special symbol) of the stopped 7-segment LED Can be recognized by the player.

  The normal symbol display 1189 is a full-color LED that can change the emission color of red, green, and orange, and the gate portion 2150 is played by a combination of the emission color and lighting / flashing. A normal lottery result drawn by passing a ball can be displayed. In addition, the display of the normal symbol by the normal symbol display 1189 is also stopped and displayed with the light emission pattern corresponding to the normal lottery result after being displayed for a predetermined period of time, like the special symbol.

  The normal symbol memory display 1188 is a normal symbol whose start of variable display is suspended (stored) when a game ball passes through the gate portion 2150 when the normal symbol display 1189 cannot display the normal symbol in a variable manner. The number of hold (number of storage) is displayed. The normal symbol memory display 1188 includes four normal symbol memory lamps 1188a to 1188d arranged side by side from below, each of which is a predetermined LED, and the normal symbol memory lamp 1188a from the bottom according to the number of holds. By sequentially lighting up to 1188d, it is possible to display the number of reserved normal symbols. In the present embodiment, up to four normal symbol fluctuation displays are held (stored).

  The round indicator 1190 includes a two-round display lamp 1190a made of predetermined LEDs and a 15-round display lamp 1190b, and can display the number of rounds in a “hit” game by lighting each lamp. It is like that.

  Further, as shown in FIG. 13, the function display unit 1180 can be viewed from the player side through the game window 101 of the door frame 5 with the game board 4 attached to the pachinko gaming machine 1. Yes. Game status indicator 1183, upper special symbol memory display 1184, upper special symbol indicator 1185, lower special symbol indicator 1186, lower special symbol memory indicator 1187, normal symbol memory indicator 1188, normal symbol indicator 1189, and The round indicator 1190 is attached to the front surface of the function display board 1191. Note that a connection terminal for connecting the function display board 1191 and the main control board 4100 is attached to the rear end of the rearward projecting portion of the function display unit 1180.

  In this embodiment, since the function display unit 1180 is provided in the front component member 1110 of the game board 4, as compared with the case where it is provided in the front unit 2000 and the back unit 3000 attached to the game panel 1150 The function display unit 1180 can be used as the basic configuration of the game board 4, and the configuration related to the pachinko gaming machine 1 can be simplified to prevent an increase in cost, and the model of the pachinko gaming machine 1 (table The position of the function display unit 1180 does not change even if the detailed configuration of the game board 4 which is embodied by the unit 2000 or the back unit 3000 and can characterize the model of the pachinko gaming machine 1 is different. Let the hall clerk recognize the position of the function display unit 1180 without confusion. So that the can.

[7. Main control board, payout control board and peripheral control board]
Next, a control board for performing various controls of the pachinko gaming machine 1 will be described with reference to FIGS. FIG. 14 is a block diagram of the main control board, the payout control board, and the peripheral control board, FIG. 15 is a block diagram showing the continuation of FIG. 14, and FIG. 16 is a payout control board, CR unit and frequency constituting the main board. FIG. 17 is a schematic diagram of various detection signals input / output to / from a lending device connection terminal board such as a game ball that relays electrical connection with the display board, FIG. 17 is a block diagram showing a continuation of FIG. 14, and FIG. FIG. 19 is a block diagram showing an outline of the peripheral control MPU, FIG. 19 is a block diagram around the sound source built-in VDP in the liquid crystal and sound control unit, and FIG. 20 is a continuation block diagram of FIG.

  As shown in FIG. 14, the control configuration of the pachinko gaming machine 1 is mainly configured by a main control board 4100, a payout control board 4110, and a peripheral control board 4140, and various controls are shared. First, the main control board will be described, and then the payout control board, the power supply board, and the peripheral control board will be described.

[7-1. Main control board]
As shown in FIG. 14, the main control board 4100 for controlling the progress of the game controls the power-on process that is executed when the power is turned on, and is executed after a predetermined time has elapsed since the power is turned on and performs the game operation. Various control programs such as a main control program to be controlled, a ROM for storing various commands, a RAM for temporarily storing data, and the like are input to the main control MPU 4100a, which is a microprocessor, and detection signals from various detection switches. Main control input circuit 4100b, main control output circuit 4100c for outputting various signals to an external substrate, etc., main control solenoid drive circuit 4100d for driving various solenoids, And a power failure monitoring circuit 4100e for monitoring signs of a stop.

  The main control MPU 4100a includes a built-in RAM (hereinafter referred to as “main control built-in RAM”) and a built-in ROM (hereinafter referred to as “main control built-in ROM”). Further, a watchdog timer 4100af (hereinafter referred to as “main control built-in WDT 4100af”) for monitoring the operation (system), a function for preventing fraud, and the like are also incorporated.

  The main control MPU 4100a has a built-in nonvolatile RAM. In this non-volatile RAM, a unique ID code with a unique code (a code that exists only in the world) for identifying an individual by the manufacturer that manufactured the main control MPU 4100a is stored in advance. Since the ID code once attached is stored in the nonvolatile RAM, it cannot be rewritten using an external device. The main control MPU 4100a can take out and refer to the ID code from the nonvolatile RAM.

  The main control MPU 4100a also uses a hardware random number circuit 4100an (hereinafter referred to as "built-in main control") to update a big hit determination random number for use in determining whether or not to generate a big hit gaming state among various random numbers related to the game. A hard random number circuit 4100an ”). The main random number circuit 4100an with built-in main control generates a random number within a predetermined numerical range (in this embodiment, a numerical range of a value 0 to a maximum value 32767 is preset as a minimum value), A predetermined value as the initial value is not fixed (that is, the initial value is not fixed), and the circuit configuration is such that a different value is set each time the main control MPU 4100a is reset. Specifically, when the main control MPU 4100a is reset, the hard random number circuit 4100an with built-in main control first sets a clock signal (input to the main control MPU 4100a as an initial value within a predetermined numerical range). Based on the clock signal output from the main control crystal oscillator (to be described later), other values within the predetermined numerical range are extracted one after another without duplication, and all values within the predetermined numerical range are extracted. Then, again, one value in the predetermined numerical range is extracted, and other values in the predetermined numerical range are not duplicated at high speed based on the clock signal input to the main control MPU 4100a. Extract one after another. The main control built-in hard random number circuit 4100an repeats such a high-speed lottery, and the main control MPU 4100a wins the value extracted by the main control built-in hard random number circuit 4100an at the time of acquiring a value from the main control built-in hard random number circuit 4100an. It is set as a random number for judgment.

  The main control input circuit 4100b is not provided with a reset terminal for forcibly resetting information whose detection signals from various detection switches are input to the various input terminals, and does not have a reset function. Therefore, the main control input circuit 4100b is configured as a circuit to which a system reset signal from a main control system reset described later is not input. That is, the main control input circuit 4100b does not reset the information based on the detection signals from the various detection switches input to the various input terminals by a main control system reset to be described later. The circuit is configured to be output from the output terminal.

  The main control output circuit 4100c is configured as an open collector output type in which an emitter terminal is grounded with a ground (GND), and various signals for outputting various signals to an external substrate or the like are input to the various input terminals. Main control output circuit 4100ca with a reset function having a reset function in which a reset terminal for forcibly resetting the received information is provided, and a main control output circuit 4100cb without reset function without a reset function in which no reset terminal is provided. And is composed of. The main control output circuit 4100ca with a reset function is configured as a circuit to which a system reset signal from a main control system reset described later is input. That is, the main control output circuit 4100ca with a reset function is reset when information for outputting various signals input to the various input terminals to an external board or the like is reset by a main control system reset described later. Is configured as a circuit that does not output any signal from the various output terminals. On the other hand, the main control output circuit 4100cb without a reset function is configured as a circuit to which a system reset signal from a main control system reset described later is not input. That is, the main control output circuit 4100cb having no reset function does not reset the information for outputting various signals input to the various input terminals to an external board or the like by a main control system reset described later. The signal based on this is comprised as a circuit from which the various output terminals are output.

  As shown in FIG. 8, a first start port switch 3022 that detects a game ball that has entered the first start port 2101, a second start port switch 2109 that detects a game ball that has entered the second start port 2102, and general A detection signal from the general winning opening switch 3020 for detecting a game ball that has entered the winning opening 2104 and a signal from the power failure monitoring circuit 4100e are input to a predetermined input port of the main control MPU 4100a via the main control input circuit 4100b. Has been entered. Also, a gate switch 2352 for detecting a game ball that has passed through the gate 2150, a general winning port switch 3020 for detecting a gaming ball that has entered the general winning port 2201, and a big winning port 2103 shown in FIG. A detection signal from a count switch 2110 that detects a game ball and a magnetic detection switch 3024 that is attached to the back unit 3000 shown in FIG. The signal is inputted to the input terminal of a predetermined input port of the main control MPU 4100a through the terminal board 4161 and the main control input circuit 4100b.

  The main control MPU 4100a outputs a drive signal from the output terminal of the predetermined output port to the main control output circuit 4100ca with reset function based on the detection signals from these switches, so that the main control output circuit with reset function is output. 4100ca outputs a control signal to the main control solenoid drive circuit 4100d, and outputs a drive signal from the main control solenoid drive circuit 4100d to the start port solenoid 2105 and the attacker solenoid 2108 via the panel relay terminal plate 4161, or a predetermined output thereof. By outputting a drive signal from the output terminal of the port to the main control output circuit 4100ca with reset function, the upper special symbol display from the main control output circuit 4100ca with reset function via the panel relay terminal board 4161 and the function display board 1191 1185, Drive signals to the special symbol display 1186, the upper special symbol storage display 1184, the lower special symbol storage display 1187, the normal symbol display 1189, the normal symbol storage display 1188, the game state display 1183, and the round display 1190 Or output.

  Further, the main control MPU 4100a outputs various information (game information) relating to the game from the output terminal of the predetermined output port to the main control output circuit 4100ca with reset function, so that payout control is performed from the main control output circuit 4100ca with reset function. Various information about the game (game information) is output to the substrate 4110, or a signal (power failure clear signal) is output from the output terminal of the predetermined output port to the main control output circuit 4100ca with reset function. A signal (power failure clear signal) is output from the control output circuit 4100ca to the power failure monitoring circuit 4100e.

  In the present embodiment, a non-contact type electromagnetic proximity switch is used for the first start port switch 3022, the second start port switch 2109, the gate switch 2352, and the count switch 2110. The general winning opening switches 3020 and 3020 are contact type ON / OFF operation type mechanical switches. This is because game balls frequently enter the first start port 2101 and the second start port 2102 and frequently pass through the gate portion 2150, so the first start port switch 3022, the second start port switch 2109, and Detection of game balls by the gate switch 2352 also frequently occurs. Therefore, long-life proximity switches are used for the first start port switch 3022, the second start port switch 2109, and the gate switch 2352. In addition, when a big hit gaming state that is advantageous to the player occurs, the game winning balls 2103 are opened and game balls are frequently entered, so that the game balls are frequently detected by the count switch 2110. For this reason, a proximity switch having a long life is also used as the count switch 2110. On the other hand, detection by the general winning opening switches 3020 and 3020 does not occur frequently in the general winning opening 2104 and 2201 where game balls do not enter frequently. For this reason, mechanical switches having a shorter lifetime than the proximity switches are used as the general winning award opening switches 3020 and 3020.

  Also, the main control MPU 4100a transmits various commands relating to payout as serial data from the output terminal of the predetermined serial output port to the main control output circuit 4100cb without reset function, thereby controlling payout from the main control output circuit 4100cb without reset function. Various commands are transmitted to the substrate 4110 as serial data. When the payout control board 4110 completes normal reception of various commands from the main control board 4100 as serial data, the payout control board 4110 outputs a signal to that effect (payer ACK signal) to the main control board 4100. This signal (payer ACK signal) is input to an input terminal of a predetermined input port of the main control MPU 4100a through the main control input circuit 4100b.

  Also, the main control MPU 4100a receives various commands related to the state of the pachinko gaming machine 1 from the payout control board 4110 as serial data by the main control input circuit 4100b, so that the main control input circuit 4100b receives the predetermined serial input port. Receives various commands as serial data at the input terminal. When the main control MPU 4100a completes normal reception of various commands from the payout control board 4110 as serial data, a main control output with a reset function is sent from the output terminal of the predetermined output port to that effect (main payout ACK signal). The signal is output to the circuit 4100ca, and a signal (main payment ACK signal) is output from the main control output circuit 4100ca with reset function to the payout control board 4110.

  Further, the main control MPU 4100a transmits, as serial data, various commands relating to control of game effects and various commands relating to the state of the pachinko gaming machine 1 to the main control output circuit 4100cb having no reset function from the output terminal of the predetermined serial output port. Thus, various commands are transmitted as serial data from the main control output circuit 4100cb having no reset function to the peripheral control board 4140.

  Here, a main peripheral serial transmission port for transmitting various commands as serial data to the peripheral control board 4140 will be briefly described. The main control MPU 4100a is configured with a main control CPU core 4100aa as the center. In addition to the main control built-in RAM, a main peripheral serial transmission port 4100ae, which is one of the main control various serial I / O ports, has a bus 4100ah. Circuit connection (see FIG. 26). The main peripheral serial transmission port 4100ae transmits various commands as main peripheral serial data to the peripheral control board 4140, and mainly includes a transmission shift register 4100aea, a transmission buffer register 4100aeb, a serial management unit 4100aec, and the like (FIG. 26). When the main control CPU core 4100aa sets a command in the transmission buffer register 4100aeb and outputs a transmission start signal to the serial management unit 4100aec, the serial management unit 4100aec sends the command set in the transmission buffer register 4100aeb from the transmission buffer register 4100aeb. The data is transferred to the transmission shift register 4100aea, and transmission to the peripheral control board 4140 is started as main peripheral serial data. In the present embodiment, the transmission buffer register 4100aeb has a storage capacity of 32 bytes. The main control CPU core 4100aa continuously sends a plurality of commands to the peripheral control board 4140 by setting a plurality of commands in the transmission buffer register 4100aeb and then outputting a transmission start signal to the serial management unit 4100aec.

  Note that the power supply board 851 for supplying various voltages to the main control board 4100 is an electric power source as a backup power supply for supplying power to the main control board 4100 for a predetermined time (3 hours in the present embodiment) even when the power is shut off. A multilayer capacitor (hereinafter simply referred to as “capacitor”) BC0 (see FIG. 21) is provided. The capacitor BC0 allows the main control MPU 4100a to store various types of information in the main control built-in RAM even when the power is turned off. Various kinds of information stored in the main control built-in RAM are stored in the operation signal (RAM clear signal) from the operation switch 860a when an operation switch 860a of a payout control board 4110 (to be described later) is operated within a predetermined period from when the power is turned on. Is output from the payout control board 4110 and input to the input terminal of a predetermined input port of the main control MPU 4100a via the main control input circuit 4100b, and triggered by this, the main control MPU 4100a completely erases it from the main control built-in RAM. (Clear).

[7-2. Dispensing control board]
As shown in FIG. 15, a payout control board 4110 for performing game ball launch control, ball feed control, etc., in addition to game ball payout control, performs various controls related to payout and controls game ball launch control and ball feed control. A payout control unit 4120 for performing the above-described operations, an operation switch 860a also having various functions, and an error LED display 860b for displaying the state of the pachinko gaming machine 1. Further, the operation switch 860a having a function as a RAM clear switch is described as a RAM (hereinafter referred to as “main control built-in RAM”) built in the main control MPU 4100a based on a detection signal output by being operated. A RAM clear signal for completely erasing the information stored in.

[7-2-1. Dispensing control unit]
As shown in FIG. 15, a payout control unit 4120 that performs various controls relating to payout and controls game ball launch control and ball transport control controls power-on processing that is executed when the power is turned on, and is predetermined from the time the power is turned on. Dispensing is a microprocessor with a built-in various control programs including a payout control program for controlling a payout operation of game media executed after a lapse of time, a ROM for storing various commands, a RAM for temporarily storing data, and the like Control MPU 4120a, payout control input circuit 4120b to which detection signals from various detection switches relating to payout and detection signals from various detection switches relating to the launch of game balls are input, and payout for outputting various signals to an external substrate or the like The control output circuit 4120c and the payout motor 744 of the prize ball device 740 shown in FIG. It includes a payout motor drive circuit 4120d for outputting a signal, and a CR unit output circuit 4120e for exchanging various signals between the CR unit 6. The payout control MPU 4120a includes a launch ball feed control circuit 4120ag that performs launch control by the launch solenoid 654 of the hit ball launcher 650 shown in FIG. 5 and ball feed control by the ball feed solenoid 585 of the ball feed unit 580 shown in FIG. A launching ball feed failure monitoring circuit 4120ah for monitoring whether or not a failure has occurred in the launching ball feed control circuit 4120ag is incorporated. The payout control MPU 4120a has a built-in RAM (hereinafter referred to as “payout control built-in RAM”), a built-in ROM (hereinafter referred to as “payout control built-in ROM”), A watchdog timer for monitoring the operation (system) and a function for preventing fraud are also incorporated.

  The discharge ball feeding control circuit 4120ag built in the dispensing control MPU 4120a that performs the firing control by the firing solenoid 654 and the ball feeding control by the ball feeding solenoid 585 corresponds to the rotational position of the front 506 of the rotating handle body shown in FIG. And a touch switch for detecting whether or not a palm or a finger is touching the front 506 of the rotary handle body, and an operation signal from the potentiometer 512 that electrically adjusts the strength (launch strength) of launching the game ball toward the game area 1100. A detection signal from 516 and a detection signal from a firing stop switch 518 that detects whether or not the launching (launching) of the game ball is forcibly stopped according to the player's will are a handle relay terminal plate 192, a power supply board 851 and the payout control input circuit 4120b of the payout control board 4110. In addition, when the CR unit 6 and the game ball lending device connection terminal plate 869 are electrically connected, the launch ball feed control circuit 4120ag transmits a CR connection signal to that effect to the CR unit input / output of the payout control board 4110. It is input via the circuit 4120e.

  The shot ball feed control circuit 4120ag adjusts a drive current for launching (shooting) the game ball toward the game area 1100 based on an operation signal from the potentiometer 512, and a payout control output circuit 4120c (with a reset function to be described later) A discharge control output circuit 4120c (a payout control with a reset function, which will be described later) is performed on the power supply board 851 (a launch solenoid drive circuit 858 which will be described later) via the payout control output circuit 4120ca) and a firing control by the firing solenoid 654 is performed. The ball of the ball feeding unit 580 is output to the power supply board 851 (ball feeding solenoid drive circuit 859 described later) via the output circuit 4120ca) and a constant current is outputted to the ball feeding solenoid 585 via the handle relay terminal plate 192. The feeding member is the upper plate 30 of the plate unit 300 shown in FIG. Receiving 1 ball the accumulated game balls, control is performed to send the game ball Tamaoku member accepts the hitting launcher 650 side.

  The firing ball feed control circuit 4120ag operates in accordance with the payout control program. When the firing operation permission is set, the game ball 1905 is played in the game area 1100 according to the rotational position of the front 506 of the rotary handle shown in FIG. An operation signal from a potentiometer 512 that electrically adjusts the strength (firing strength) to be launched toward the head, a detection signal from a touch switch 516 that detects whether a palm or finger is touching the front 506 of the rotating handle, The detection signal from the firing stop switch 518 for detecting whether or not the launching (launching) of the game ball is forcibly stopped at the will of the player, and the CR unit 6 and the game ball lending device connection terminal plate 869 are electrically connected. Control of the game ball is performed based on the CR connection signal indicating that the connection is established. On the other hand, when the launch operation prohibition is set, the above-described launch control of the game ball is forcibly stopped.

  The game ball launch control by the shot ball feed control circuit 4120ag is 99.93 to 99.95 as the number of game balls that can be launched (launched) toward the game area 1100 per minute. It is preset so that it does not exceed 100 balls. This is realized by a PWM circuit (not shown) for generating a PWM (abbreviation of Pulse Width Modulation) signal (not shown) built in the payout control MPU 4120a. The pulse width of the PWM signal output from this circuit is such that the number of game balls that can be launched (launched) toward the game area 1100 per minute is 99.93 to 99.95. The PWM signal is set in advance, and the circuit is connected so that the PWM signal is input to the shot ball feed control circuit 4120ag. The shot ball feed control circuit 4120ag measures the launch timing of the game ball based on the input PWM signal.

  As described above, the firing ball feed failure monitoring circuit 4120ah monitors whether or not a failure has occurred in the firing ball feed control circuit 4120ag, and stores the monitoring result (whether or not a failure has occurred) as status information. It can be held. When the payout control program obtains status information from the launching ball feed failure monitoring circuit 4120ah and determines that a failure has occurred in the launching ball feed control circuit 4120ag, it controls the launching of the game ball by the launching ball feed control circuit 4120ag. In order to forcibly stop, the launching operation prohibition is set to the launching ball feed control circuit 4120ag.

  The payout control program sets the launching operation prohibition to the launching ball feed control circuit 4120ag as an initial state (default) when an instantaneous power failure or power failure occurs and the power is restored after the power is turned on. After that, when the status information is acquired from the shooting ball feeding failure monitoring circuit 4120ah and it is determined that the shooting ball feeding control circuit 4120ag is not defective, the shooting ball sending control circuit 4120ag starts the launch control of the game ball. The launching operation permission is set for the launching ball feed control circuit 4120ag, while the status information is acquired from the launching ball feed failure monitoring circuit 4120ah and it is determined that the launching ball feed control circuit 4120ag is malfunctioning. Launch to maintain the state where the launch control of the game ball by the ball feed control circuit 4120ag is stopped Setting the firing operation prohibition against sending control circuit 4120ag.

  Here, as a problem in the shot ball feed control circuit 4120ag, it is difficult to adjust the drive current for launching (shooting) the game ball toward the game area 1100 based on the operation signal from the potentiometer 512. If the operation signal from the potentiometer 512 is affected by noise, it becomes a highly distorted signal, and the drive current for launching (launching) the game ball toward the game area 1100 cannot be specified. Is difficult to adjust, the detection signal from the touch switch 516 turns into a very distorted signal due to the influence of noise, and whether the player's palm or finger is touching the front 506 of the rotary handle If it is difficult to identify the detection signal, the detection signal from the firing stop switch 518 is affected by noise. In addition to the case where it becomes difficult to specify whether or not the launching (launching) of the game ball has been forcibly stopped by the player's will due to the distorted signal, When 4120ag itself is destroyed for some reason and cannot be used, or when the number of game balls launched (launched) toward the game area 1100 per predetermined time exceeds a predetermined number (this embodiment) In this case, the number of game balls shot (launched) toward the game area 1100 per minute may exceed 100).

  Under the control of the payout control MPU 4120a, the payout control program converts various information related to games (game information) and various commands related to payout from the main control board 4100 as payer serial data transmission signals via the payout control I / O port 4120b. Receive serial data by serial method. In addition, the payout control program generates a frame state 1 command triggered by an occurrence of an error in the game ball payout operation, or 16 bits based on an operation signal (detection signal) of the operation switch 860a as an error release unit. A (2 byte) error canceling navigation command is created and output to the receiving port of the main control board 4100 through the payout control I / O port 4120b as serial data of a serial system as a payer serial data transmission signal. In addition, the payout control program is provided after a predetermined time has elapsed since the power was turned on, that is, after the payout control unit main process is executed or the payout control unit timer interrupt process is executed to start payout control. When an error occurs in the operation, the error is canceled based on a detection signal generated in response to the operation of the operation switch 860a, and output of warning information corresponding to the error is stopped.

  In addition, when the payout control program obtains status information from the launching ball feed failure monitoring circuit 4120ah and determines that there is no malfunction in the launching ball feed control circuit 4120ag, the payout control program 4120ag plays a game ball In order to start the launch control, the launching operation permission is set for the launching ball feed control circuit 4120ag. On the other hand, when it is determined that the launching ball feed control circuit 4120ag is defective, a game by the launching ball feed control circuit 4120ag is performed. In order to forcibly stop the launch control of the sphere, the launch operation prohibition is set to the launch ball feed control circuit 4120ag.

  The payout control input circuit 4120b is not provided with a reset terminal for forcibly resetting information whose detection signals from the various detection switches are input to the various input terminals, and does not have a reset function. Therefore, the payout control input circuit 4120b is configured as a circuit to which a system reset signal from a payout control system reset described later is not input. In other words, the payout control input circuit 4120b does not reset the information based on the detection signals from the various detection switches inputted to the various input terminals by a payout control system reset to be described later. The circuit is configured to be output from the output terminal.

  The payout control output circuit 4120c is configured as an open collector output type in which the emitter terminal is grounded with the ground (GND), and various signals for outputting various signals to an external substrate or the like are input to the various input terminals. Payout control output circuit 4120ca with a reset function having a reset function in which a reset terminal for forcibly resetting the received information is provided, and a payout control output circuit 4120cb without reset function having no reset function in which no reset terminal is provided And is composed of. The payout control output circuit 4120ca with a reset function is configured as a circuit to which a system reset signal from a payout control system reset described later is input. That is, the payout control output circuit 4120ca with a reset function resets the information for outputting various signals input to the various input terminals to an external substrate or the like by a payout control system reset described later, and the information Is configured as a circuit that does not output any signal from the various output terminals. In contrast, the payout control output circuit 4120cb without a reset function is configured as a circuit to which a system reset signal from a payout control system reset described later is not input. In other words, the payout control output circuit 4120cb without the reset function does not reset the information for outputting the various signals input to the various input terminals to an external substrate or the like by the payout control system reset described later. The signal based on this is comprised as a circuit from which the various output terminals are output.

  A detection signal from a ball break switch 750 that detects the presence or absence of a game ball in the supply passage of the prize ball device 740 and a count switch 751 that detects a game ball flowing down in the prize ball device 740 is first a prize. It is input to the input terminal of a predetermined input port of the payout control MPU 4120a through the prize ball case substrate 754 of the ball device 740 and the payout control input circuit 4120b. The detection signals from the rotation angle switch 752 for detecting the detection slit formed on the rotation detection board of the prize ball device 740 are first a rotation angle switch board 753 of the prize ball device 740, a prize ball case inner board 754, and It is input to the input terminal of a predetermined input port of the payout control MPU 4120a via the payout control input circuit 4120b.

  The detection signals from the door frame opening switch 618 for detecting the opening of the door frame 5 with respect to the main body frame 3 and the main body frame opening switch 619 for detecting the opening of the main body frame 3 with respect to the outer frame 2 are sent to the payout control input circuit 4120b. To the input terminal of a predetermined input port of the payout control MPU 4120a.

  Further, the detection signal from the full switch 550 for detecting whether or not the storage space of the foul cover unit 540 shown in FIG. 1 is full is stored in the handle relay terminal plate 192, the power supply board. 851 and the input terminal of a predetermined input port of the payout control MPU 4120a via the payout control input circuit 4120b.

  The payout control MPU 4120a receives various commands related to payout from the main control board 4100 via the payout control input circuit 4120b in the serial data mode at the input terminal of the serial input port, or the operation signal (detection) of the operation switch 860a. Signal) is output to the main control board 4100 via the payout control input circuit 4120b. When the payout control MPU 4120a completes normal reception of various commands from the main control board 4100 as serial data, a payout control output with a reset function is sent from the output terminal of the predetermined output port. By outputting to the circuit 4120ca, a signal (payer ACK signal) is output from the payout control output circuit with reset function 4120ca to the main control board 4100.

  Also, the payout control MPU 4120a sends out various commands for indicating the state of the pachinko gaming machine 1 from the output terminal of the serial output port as serial data to the payout control output circuit 4120cb without the reset function, thereby giving out the payout without the reset function. Various commands are transmitted as serial data from the control output circuit 4120cb to the main control board 4100. When the main control board 4100 completes normal reception of various commands from the payout control board 4110 as serial data, the main control board 4100 outputs a signal (main payment ACK signal) to that effect to the payout control board 4110. This signal (main payment ACK signal) is input to an input terminal of a predetermined input port of the payout control MPU 4120a via the payout control input circuit 4120b.

  Also, the payout control MPU 4120a outputs a drive signal for driving the payout motor 744 from the output terminal of the predetermined output port to the payout control output circuit 4120ca with reset function, so that the payout control output circuit 4120ca with reset function is output. Is output to the payout motor drive circuit 4120d, and the drive signal is output from the payout motor drive circuit 4120d to the payout motor 744 via the prize ball case substrate 754, or from the output terminal of the predetermined output port. By outputting a drive signal for displaying the state of the gaming machine 1 on the error LED indicator 860b to the payout control output circuit 4120ca with reset function, the drive signal is output from the error LED indicator 860b with the reset function payout control output circuit 4120ca. Or output to

  The error LED display 860b is a segment display and displays the state of the pachinko gaming machine 1 by displaying alphanumeric characters and figures. The contents displayed and notified by the error LED indicator 860b include the following. For example, when the figure “-” is displayed, it is notified that it is “normal”, and when the numeral “0” is displayed, it indicates that it is “connection abnormality” (specifically, with the main control board 4100). The fact that there is an abnormality in electrical connection between the board and the payout control board 4110) is notified, and when the number “1” is displayed, it is “out of ball” (specifically, out of ball) Based on the detection signal from the switch 750, it is notified that there is no game ball in the supply passage of the prize ball device 740, and when the number “2” is displayed, it means that “the ball is clear” (specifically, Is based on the detection signal from the rotation angle switch 752, and the payout rotator and the game ball are meshed in the vicinity of the entrance at the entrance of the distribution space communicating with the supply passage of the prize ball device 740, and the payout rotator is difficult to rotate. Number) When “3” is displayed, the fact that it is a “counter switch error” (specifically, that a malfunction has occurred in the count switch 751 based on a detection signal from the count switch 751) is notified, and the number “ When “5” is displayed, it is informed that it is a “retry error” (specifically, that the number of retries of the payout operation has reached a preset upper limit value), and the number “6” is displayed. When it is, it is informed that it is “full” (specifically, based on the detection signal from the full tank switch 550, the game ball in which the accommodation space of the foul cover unit 540 is stored is full) When the number “7” is displayed, it is reported that “CR is not connected” (electrical connection is cut off from either the payout control board 4110 to the CR unit 6). However, when the number “9” is displayed, it is “in stock (awarded ball stock (unpaid) is present)” (specifically, the number of game balls that have not yet been paid out is a predetermined number of balls) To that effect).

  Also, the payout control MPU 4120a outputs the number of game balls actually paid out as prize balls from the output terminal of the predetermined output port to the payout control output circuit 4120ca with reset function, thereby providing payout control with reset function. The number of game balls actually paid out as prize balls is output from the output circuit 4120ca to the external terminal board 784 through a resistor (not shown).

  Also, the payout control board 4110 outputs various information (game information) related to the game from the main control board 4100 to the external terminal board 784 via a resistor (not shown). In addition to the payout control board 4110, various information from the peripheral control board 4140 (number of game balls to be paid out as prize balls, etc.) is also input to the external terminal board 784. The external terminal board 784 is provided with a plurality of photocouplers (not shown) (infrared LEDs and photo ICs are built in), and a game hall (hole) is provided via the plurality of photocouplers. ), The number of game balls, and various information (game information, content of error relating to game ball payout operation, or the fact that there was an error) are transmitted to the hall computer installed in (1). The external terminal board 784 and the hall computer are electrically insulated by a plurality of photocouplers, and an abnormal voltage is applied to the hall computer via the external terminal board 784 of the pachinko gaming machine 1. The hall computer does not malfunction or break down, and the main control board 4100 that advances the game from the hall computer via the external terminal board 784 of the pachinko gaming machine 1, the payout control board that controls the payout etc. An abnormal voltage is applied to 4110 and the peripheral control board 4140 that controls the progress of the production, so that malfunction or failure does not occur. The hall computer includes the number of game balls actually paid out by the pachinko gaming machine 1 as prize balls, game information of the pachinko gaming machine 1, and the number of game balls scheduled to be paid out by the pachinko gaming machine 1 as prize balls. By grasping this, the player's game and game ball payout information (so-called play information) by the payout operation of the pachinko gaming machine 1 are monitored.

  The ball lending request signal for the game ball from the ball lending switch 365a of the ball lending unit 360 and the return request signal for the prepaid card from the return switch 365b shown in FIG. And, it is input to the CR unit 6 through a lending device connection terminal board 869 such as a game ball. The CR unit 6 transmits a signal designating the number of game balls to be lent according to the ball lending request signal to the payout control board 4110 via the gaming ball lending device connection terminal board 869 in a serial manner, and this signal is transmitted to the CR unit. It is input to an input terminal of a predetermined input port of the payout control MPU 4120a via the input / output circuit 4120e. In addition, the CR unit 6 updates the remaining degree of the prepaid card inserted according to the number of rented game balls, and displays a signal for displaying the remaining degree on the remaining number display 365c, such as a game sphere. The signal is output to the lending device connection terminal plate 869, the main door relay terminal plate 880, and the frequency display plate 365, and this signal is input to the remaining frequency display 365c. In addition, the CR unit lamp 365d adjacent to the remaining frequency indicator 365c is supplied with the supply voltage from the CR unit 6 via the game ball lending device connection terminal plate 869 and the main door relay terminal plate 880. Yes.

  In addition, the CR unit 6 includes a prepaid card remaining degree, various hall information, gaming machine data (for example, a game description (gaming specifications) described in a gaming machine booklet, contents explaining an outline of production, etc.), a wagon, etc. Various information such as guidance on services (for example, drinks) is output as video signals to the upper plate side liquid crystal display device 470 via the game ball rental device connection terminal plate 869 and the main door relay terminal plate 880. . The upper plate side liquid crystal display device 470 includes a type having a touch panel so as to cover the display area, and the position information on the touch panel touched by the player is transferred from the upper plate side liquid crystal display device 470 to the main door relay terminal plate 880. The ball is output to the CR unit 6 via the game ball lending device connection terminal board 869. In the case where, for example, a guide for a wagon service is displayed as various information in the display area of the upper dish side liquid crystal display device 470 according to the video signal from the CR unit 6, a player out of a plurality of drink images is displayed. Is touched with a finger, the position information of the finger is input to the CR unit 6, and the CR unit 6 obtains the drink information corresponding to the image touched by the player. When the confirmation button image is touched with a finger, the position information of the finger is input to the CR unit 6, and the acquired drink information and the machine number of the pachinko gaming machine where the ordered player is sitting and playing the game ( For example, the CR unit 6 is transmitted to a terminal installed in the drink service center in the hall via the radio. When the power is turned on, the CR unit 6 monitors whether or not a malfunction has occurred in the CR unit 6 and, in a normal state in which the malfunction has not occurred, informs an unillustrated notification lamp in green. On the other hand, in the abnormal state in which a problem has occurred, a notification lamp (not shown) is lit in red to notify. In addition, the CR unit 6 transmits information (for example, information on drinks ordered by the player) to the drink service center in the hall according to the player's operation from the touch panel of the upper plate side liquid crystal display device 470. A notification lamp (not shown) is lit in blue to notify, and when the provision of the drink service is completed, a signal to that effect is transmitted to the CR unit 6. As a result, the CR unit 6 notifies the result of monitoring whether or not a defect has occurred in itself by turning on a notification lamp (not shown). Regarding the end of the provision of the drink service, it may be transmitted to the CR unit 6 via radio when the drink is provided using the terminal owned by the clerk who provided the drink, or the clerk who provided the drink is in the hall. You may transmit to CR unit 6 via a radio | wireless using the terminal installed in a drink service center after returning to a drink service center.

  The power supply board 851 for supplying various voltages to the payout control board 4110 is a capacitor BC1 as a backup power supply for supplying power to the payout control board 4110 for a predetermined time (1 hour in the present embodiment) even when the power is shut off. (See FIG. 21). With this capacitor BC1, the payout control MPU 4120a can store various types of information in the payout control built-in RAM (payout storage unit) even when the power is shut off. Various types of information stored in the payout control built-in RAM are stored in the payout control MPU 4120a via the payout control input circuit 4120b when the operation switch 860a is operated within a predetermined period from when the power is turned on. The payout control MPU 4120a input to the input terminal of the input port determines as a RAM clear signal for completely erasing the information stored in the payout control built-in RAM, and triggered by this from the payout control built-in RAM by the payout control MPU 4120a. It is completely erased (cleared). This operation signal (RAM clear signal) is output to the payout control output circuit 4120cb without reset function, and is output to the main control board 4100 from the payout control output circuit 4120cb without reset function.

[7-2-2. Exchange of various signals with game ball rental device connection terminal board]
Here, the exchange of various signals between the payout control unit 4120 and the CR unit 6, the exchange of various signals between the CR unit 6 and the frequency display board 365, and the various signals between the CR unit 6 and the upper plate side liquid crystal display device 470. The exchange will be described with reference to FIG. As shown in FIG. 16, the game ball lending device connection terminal board 869 relays the electrical connection between the CR unit 6 and the payout control board 4110, as well as the CR unit 6 and the frequency display board 365. (To be precise, the game ball rental device connection terminal plate 869 is electrically connected to the frequency display plate 365 via the main door relay terminal plate 880. The CR unit 6 and the game ball lending device connection terminal plate 869 are electrically connected, the game ball lending device connection terminal plate 869 and the main door relay terminal plate 880 are electrically connected, and the main door relay Terminal board 880 and frequency display board 365 are electrically connected). Between the board of CR unit 6 and gaming ball lending device connection terminal plate 869, between the gaming ball lending device connection terminal plate 869 and payout control board 4110, gaming ball lending device connection terminal plate 869 and main door relay. Each wiring (harness) is between the board with the terminal board 880, between the main door relay terminal board 880 and the frequency display board 365, and between the main door relay terminal board 880 and the upper side liquid crystal display device 470. Are electrically connected to each other. In addition, AC24V, which will be described later, from the power supply board 851 is supplied to the CR unit 6 via a game ball rental device connecting terminal plate 869. The CR unit 6 generates a predetermined voltage VL (DC +12 V (DC +12 V, hereinafter referred to as “+12 V”) in this embodiment) from the supplied AC 24 V by a built-in voltage generation circuit (not shown), and the ground LG At the same time, it is supplied to the payout control board 4110 via the game ball lending device connection terminal plate 869, and is supplied to the frequency display plate 365 via the game ball lending device connection terminal plate 869 and the main door relay terminal plate 880. Yes. Further, the CR unit 6 incorporates a predetermined voltage LVL (DC +3.3 V (DC +3.3 V, hereinafter referred to as “+3.3 V”)) from the supplied AC 24 V, which is not shown. It is created by the creation circuit and supplied to the upper plate side liquid crystal display device 470 through the lending device connection terminal plate 869 such as a game ball and the main door relay terminal plate 880 together with the ground LLG.

  The frequency display board 365 has a ball lending switch 365a, which is a push button switch, mounted on the component surface at a position corresponding to the lending button 361 of the lending unit 360 shown in FIG. A return switch 365b, which is a push button switch, is mounted at a position corresponding to the button 362, and a remaining frequency display 365c, which is a segment display, is mounted at a position corresponding to the remaining lending display section 363 of the rental unit 360.

  The ball rental switch 365a and the return switch 365b are electrically connected to the ground LG from the CR unit 6 via a game ball rental device connection terminal plate 869 and a main door relay terminal plate 880. When the ball lending button 361 is pressed, the ball lending switch 365a is turned on (the ball lending switch 365a is turned on), and the ball lending operation signal TDS from the ball lending switch 365a is transmitted to the main door relay terminal plate 880 and the game. It is input to the CR unit 6 through a ball lending device connection terminal board 869. When the return button 365b is pressed, the return switch 365b is turned on (turned on), and the return operation signal RES from the return switch 365b is connected to the main door relay terminal plate 880 and a rental device such as a game ball. The signal is input to the CR unit 6 through the terminal board 869.

  The remaining frequency indicator 365c is composed of three segment indicators arranged in a line. Of these three digit segment indicators, one digit segment indicator is sequentially driven, so-called dynamic lighting system is used for three digits. The segment display is controlled to be lit. By such lighting control, the remaining frequency indicator 365c displays the remaining amount of the prepaid card inserted into the CR unit 6 or displays an error of the CR unit 6. The remaining frequency indicator 365c includes digit signals DG0 to DG2 (three signals in total) for designating one-digit segment indicator among the three-digit segment indicator, and the designated one-digit segment indicator. Segment drive signals SEG-A to SEG-G (a total of 7 signals) for designating the contents to be lit and displayed are connected from the CR unit 6 to the lending device connection terminal board 869 such as a game ball and the main door relay terminal board When input via the 880, a one-digit segment indicator is sequentially emitted according to the input digit signals DG0 to DG2 and segment drive signals SEG-A to SEG-G, and these three-digit segment indicators The contents due to the light emission can be visually recognized through the lending remaining display portion 363.

  A CR unit lamp 365d is mounted on the frequency display board 365 adjacent to the remaining frequency display 365c. The CR unit lamp 365d is supplied with a predetermined voltage VL from the CR unit 6 via a game ball lending device connection terminal plate 869 and a main door relay terminal plate 880. The predetermined voltage VL is input to the CR unit 6 as a ball lending available signal TDL through a current limiting resistor mounted on the gaming ball lending device connection terminal plate 869 via the CR unit lamp 365d. The CR unit 6 creates a predetermined voltage VL from the AC 24 V supplied from the power supply board 851 by the built-in voltage creation circuit, and the ball rental switch 365a and the return switch 365b are in a valid ball rental state. Controls the logic of the ball lending available signal TDL to cause the CR unit lamp 365d to emit light, and this light emission can be visually recognized through the lending remaining display portion 363. Further, the segment drive signals SEG-A to SEG-G are input to the remaining frequency indicator 365c through a current limiting resistor mounted on the gaming ball lending device connection terminal board 869.

  In the CR unit 6, the ball lending button 361 is pressed, and the ball lending operation signal TDS from the ball lending switch 365a is transmitted from the frequency display plate 365 via the main door relay terminal plate 880 and the game ball lending device connection terminal plate 869. When inputted, the ball rental request signal BRDY is output to the payout control board 4110 (payout control MPU 4120a) via the game ball lending device connecting terminal board 869. The CR unit 6 performs a single payout operation start request signal for paying out a predetermined number of rented balls (in this embodiment, 25 balls, corresponding to 100 yen as an amount) in one payout operation. Is output to the payout control board 4110 (the payout control MPU 4120a) via the gaming ball rental device connecting terminal board 869. The payout control board 4110 (payout control MPU 4120a) to which BRDY and BRQ are input, sends EXS, which is a signal for notifying that the one payout operation has been started or ended, to the lending device connection terminal board 869 such as a game ball. A ball terminal for connecting a device such as a game ball to output a PRDY signal indicating that the payout operation for outputting the ball or paying out the ball is possible or impossible. Or output to the CR unit 6 via 869. In addition, for example, when a hall clerk or the like is preset in the CR unit 6 so that a game ball of 200 yen is paid out when the ball rental button 361 is pressed, one payout operation is performed. Is performed twice in succession, and when 25 balls for 100 yen are paid out, 25 balls for 100 yen are paid out, and 50 balls for a total of 200 yen are paid out. Become.

  In the CR unit 6, the return button 362 is pressed, and a return operation signal RES from the return switch 365 b is input from the frequency display board 365 via the main door relay terminal board 880 and the game ball lending device connection terminal board 869. The prepaid card is discharged from an insertion slot (not shown) and returned. The returned prepaid card stores a remaining amount obtained by subtracting an amount corresponding to the number of game balls paid out as a result of the ball rental button 361 being pressed.

  The CR unit 6 includes a prepaid card remaining level, various hall information, gaming machine data (for example, a game description (gaming specifications) described in a gaming machine booklet and contents explaining an outline of production), a wagon service ( For example, various information such as guidance on drinks etc. is output as video signals LVS to the upper plate side liquid crystal display device 470 through the lending device connection terminal plate 869 such as a game ball and the main door relay terminal plate 880. When the video signal LVS is input, the upper plate side liquid crystal display device 470 displays the above-described various information in the display area.

[7-3. Power supply board]
Next, the power supply board 851 will be briefly described. The power supply board 851 is supplied from the Pachinko Island facility, and can be electrically connected to or disconnected from AC 24 volts (AC24V), and a power supply control unit 855 that generates various power supplies. 5, a launch solenoid drive circuit 858 for driving the launch solenoid 654 of the hit ball launcher 650 shown in FIG. 5, and a ball feed solenoid drive circuit for driving the ball feed solenoid 585 of the ball feed unit 580 shown in FIG. 859. The launch solenoid drive circuit 858 is controlled by a launch ball feed control circuit 4120ag built in the payout control MPU 4120a of the payout control board 4110 and launches a game ball toward the game area 1100 based on an operation signal from the potentiometer 512 (launch). The drive current to the firing solenoid 654 is adjusted so that it can be The ball feeding solenoid drive circuit 859 is controlled by the launch ball feeding control circuit 4120ag built in the dispensing control MPU 4120a of the dispensing control board 4110, and the ball feeding member of the ball feeding unit 580 is the upper plate of the dish unit 300 shown in FIG. One game ball stored in 301 is received, and the driving current to the ball feeding solenoid 585 is adjusted to be a constant current so that the game ball received by the ball feeding member can be sent to the ball hitting device 650 side. It has become so.

[7-3-1. Power control unit]
The power control unit 855 operates the power switch 852 to improve the power factor of the power rectified by the synchronous rectifier circuit 855a that rectifies the AC 24 volts (AC 24V) supplied from the pachinko island facility and the synchronous rectifier circuit 855a. Power factor correction circuit 855b, smoothing circuit 855c for smoothing the power whose power factor has been improved by power factor improvement circuit 855b, and various direct currents for supplying power smoothed by smoothing circuit 855c to various substrates A power generation circuit 855d for generating a power supply.

[7-4. Peripheral control board]
As shown in FIG. 17, the peripheral control board 4140 performs drawing control of the peripheral control unit 4150 that performs effect control based on various commands from the main control board 4100 and the game board side effect display unit 1900 (liquid crystal panel 5000e). And controlling the light emission of various LEDs, and controlling sound such as music and sound effects flowing from the speaker housed in the speaker box 820 shown in FIG. 5 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 A liquid crystal and sound control unit 4160 for performing the operation, a real-time clock (hereinafter referred to as “RTC”) control unit 4165 holding calendar information for specifying the date and time, and time information for specifying the hour, minute, second, and main body Volumes of music, sound effects and the like flowing from the speakers housed in the speaker box 820 provided in the frame 3 and the speakers 130 provided in the door frame 5 And volume adjustment volume 4140a be adjusted by turning operation of the knob portion, and a.

[7-4-1. Peripheral control unit]
As shown in FIG. 17, the peripheral control unit 4150 for effect control controls the peripheral control MPU 4150a as a microprocessor and the power-on process executed when the power is turned on, and after a predetermined time has elapsed since the power was turned on. Various control programs such as a sub-control program that is executed and controls the production operation, a peripheral control ROM 4150b that stores various data, various control data, and various schedule data, and a VDP 4160a with a built-in sound source of the liquid crystal and sound control unit 4160 described later. Various information continued across the peripheral control unit steady process executed each time a V blank signal is input (for example, schedule data or various data defining a screen to be drawn (displayed) on the game board side effect display unit 1900 or the like Schedule data that defines the light emission mode of LEDs, etc. Peripheral control RAM 4150c for storing information etc. for managing etc., and various information continued across days (for example, information for managing the history of occurrence of big hit gaming state and managing special effect flags) The peripheral control SRAM 4150d for storing the information and the like, and the peripheral control external watchdog timer 4150e for monitoring whether the peripheral control MPU 4150a is operating normally (hereinafter referred to as “peripheral control external WDT 4150e”). ) And a value (power consumption suppression stage described later) transmitted by the power consumption suppression signal from the power supply board 851 is sampled at a predetermined cycle via the frame peripheral relay terminal plate 868 (peripheral control unit 1 ms described later). As power consumption status history information (in power consumption status history information creation processing in timer interrupt processing) Next-held power consumption status history RAM 4150f and battery 4150g for supplying backup power to the power consumption status history storage unit 4150f so that the power consumption status history information of the power consumption status history storage unit 4150f is stored when the power is cut off. Based on the power consumption status history information stored and held in the power consumption status history RAM 4150f, the power status consumed by the pachinko gaming machine 1 at the time of power-off (immediately before the power-off) is grasped at the time of power recovery. A power saving mode transition notification LED 4150k for notifying the transition state to the power saving mode at the time of power recovery that suppresses the power consumed by the gaming machine 1;

  Peripheral control RAM 4150c can retain the stored content only for the time when power is restored immediately after an instantaneous power failure, and power is cut off for a long time (when a long-time power interruption occurs) ), The peripheral control SRAM 4150d is supplied with backup power by a large-capacity electrolytic capacitor (not shown) provided on the power supply board 851 (hereinafter referred to as “electrolytic capacitor for SRAM”). Thus, the stored contents can be held for about 50 hours. By providing the electrolytic capacitor for SRAM on the power supply board 851, when the game board 4 is detached from the pachinko gaming machine 1, backup power is not supplied to the peripheral control SRAM 4150d. Therefore, the peripheral control SRAM 4150d Loses its contents because it can no longer hold.

  The peripheral control external WDT 4150e is a timer for monitoring whether or not the system of the peripheral control MPU 4150a is running out of control. When this timer expires, a hardware reset is performed. That is, the peripheral control MPU 4150a is reset when a clear signal for clearing the timer of the peripheral control external WDT 4150e is not output to the peripheral control external WDT 4150e within a certain period (until the timer expires). When the peripheral control MPU 4150a outputs a clear signal to the peripheral control external WDT 4150e within a certain period, the peripheral control external WDT 4150e can restart the timer count of the peripheral control external WDT 4150e, and therefore no reset is applied.

  The peripheral control MPU 4150a incorporates a plurality of parallel I / O ports, serial I / O ports, and the like. When various commands are received from the main control board 4100, the peripheral control MPU 4150a is provided on the game board 4 based on the various commands. Games that are scheduled to be paid out as prize balls based on the game balls entered in the various winning holes such as the first starting port 2101, the second starting port 2102, the general winning port 2104, 2201, and the big winning port 2103 shown in FIG. Each time the number of balls reaches a predetermined number (in this embodiment, 10 is set), a main prize ball number information output signal is transmitted from the parallel I / O port. Output to the external terminal board 784 through the peripheral control output circuit, or power based on the power consumption status history information stored in the power consumption status history RAM 4150f. To understand the power status consumed by the pachinko gaming machine 1 at the time of power recovery (just before the power is turned off) and to inform the state of transition to the power saving mode during power recovery that suppresses the power consumed by the pachinko gaming machine 1 A power saving mode information output signal is output from the parallel I / O port to the external terminal board 784 via a peripheral control output circuit (not shown).

  In addition, the peripheral control MPU 4150a includes a plurality of LEDs provided on each of the plurality of game board side peripheral control MPU control target decorative boards that are controlled by the peripheral control MPU 4150a directly among the decorative boards of the game board 4. The game board side light emission data SL-DAT for outputting a lighting signal, blinking signal or gradation lighting signal to the decoration LED) is synchronized with the game board side light emission clock signal SL-CLK, and the serial for the game board side decoration board A drive signal is transmitted from the I / O port to the lamp drive board 4170 via a peripheral control output circuit (not shown) or a drive signal to an electric drive source such as a motor or a solenoid for operating various movable bodies provided on the game board 4. Game board side motor drive data to be transmitted from the motor drive board serial I / O port via the peripheral control output circuit to the motor drive board 4180 ( A motor drive circuit (or such a serial / parallel conversion circuit is built in) via a serial / parallel conversion circuit (not shown) which is provided in the data drive board 4180 and can convert serial data into parallel data and output a parallel signal. Motor drive circuit) or solenoid drive circuit (or a solenoid drive circuit incorporating such a serial-parallel conversion circuit). The peripheral control MPU 4150a also outputs door side motor drive data for outputting a drive signal to an electrical drive source such as a dial drive motor 414 provided on the door frame 5 from the frame decoration drive amplifier board motor serial I / O port. Via the peripheral control output circuit, the frame peripheral relay terminal plate 868, and the peripheral door relay terminal plate 882, the frame decoration drive amplifier board 194 (which is provided in the frame decoration drive amplifier board 194, converts serial data into parallel data and converts the parallel signal into It can be output to a motor drive circuit (or a motor drive circuit incorporating such a serial / parallel conversion circuit) via a serial / parallel conversion circuit (not shown) that can output, A plurality of frame-side peripheral control MPU control target decoration groups that are controlled by the peripheral control MPU 4150a directly The frame side light emission data STL-DAT for outputting a lighting signal, a blinking signal, or a gradation lighting signal to a plurality of LEDs (decorative LEDs) provided in each of the LEDs is synchronized with the frame side light emission clock signal STL-CLK. Transmission from the frame side decorative board serial I / O port to the frame decoration drive amplifier board 194 via the peripheral control output circuit, the frame peripheral relay terminal board 868, and the peripheral door relay terminal board 882, and the frame decoration of the door frame 5 LOCKN signal output request data for confirming whether or not a failure has occurred between the connection with the drive substrate 194 is output from the LOCKN signal output request serial I / O port.

  Various commands from the main control board 4100 are input to the serial I / O port for main control board of the peripheral control MPU 4150a via a peripheral control input circuit (not shown). In addition, a detection signal from a rotation detection switch for detecting the rotation (rotation direction) of the dial operation unit 401 and a pressure detection switch for detecting the operation of the pressing operation unit 405 provided in the operation unit 400. The detection signal is serialized by a door-side serial transmission circuit (not shown) provided on the frame decoration drive amplifier board 194, and the serialized operation unit detection data is transmitted from the door-side serial transmission circuit to the peripheral door relay terminal plate 882, the frame. The signal is input to the operation unit detection serial I / O port of the peripheral control MPU 4150a via the peripheral relay terminal plate 868 and the peripheral control input circuit.

  Detection signals from various detection switches (for example, photosensors) for detecting the original positions and movable positions of various movable bodies provided on the game board 4 are on the game board side (not shown) provided on the motor drive board 4180. Serialized by the serial transmission circuit, and this serialized movable body detection data is input to the serial I / O port for the motor drive board of the peripheral control MPU 4150a from the serial transmission circuit on the game board via the peripheral control input circuit. Yes. The peripheral control MPU 4150a exchanges various data between the peripheral control board 4140 and the motor drive board 4180 by switching the input / output of the serial I / O port for the motor drive board.

  The peripheral control MPU 4150a has a built-in watchdog timer (hereinafter referred to as “peripheral control built-in WDT”), and its own system runs away using both the peripheral control built-in WDT and the peripheral control external WDT 4150e. It is diagnosed whether or not.

[7-4-1a. Peripheral control MPU]
Next, the peripheral control MPU 4150a which is a microcomputer will be described. As shown in FIG. 18, the peripheral control MPU 4150a is centered on the peripheral control CPU core 4150aa, and includes a peripheral control built-in RAM 4150ab, a peripheral control DMA (abbreviation of Direct Memory Access) controller 4150ac, a peripheral control bus controller 4150ad, and various peripheral control serial Is. / O port 4150ae, peripheral control built-in WDT 4150af, peripheral control various parallel I / O ports 4150ag, peripheral control analog / digital converter (hereinafter referred to as peripheral control A / D converter) 4150ak, and the like.

  Peripheral control CPU core 4150aa reads / writes various data to / from peripheral control built-in RAM 4150ab and peripheral control DMA controller 4150ac via internal bus 4150ah, while peripheral control various serial I / O ports 4150ae, peripheral control built-in WDT 4150af, Various data are read from and written to the various peripheral control parallel I / O ports 4150ag and the peripheral control A / D converter 4150ak via the internal bus 4150ah, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai.

  The peripheral control CPU core 4150aa reads various data from the peripheral control ROM 4150b via the internal bus 4150ah, the peripheral control bus controller 4150ad, and the external bus 4150h, while the peripheral control RAM 4150c, the peripheral control SRAM 4150d, and the power Various data are read from and written to the consumption status history RAM 4150f via the internal bus 4150ah, the peripheral control bus controller 4150ad, and the external bus 4150h.

  The peripheral control DMA controller 4150ac includes storage devices such as a peripheral control built-in RAM 4150ab, a peripheral control ROM 4150b, a peripheral control RAM 4150c, and a peripheral control SRAM 4150d, peripheral control various serial I / O ports 4150ae, peripheral control built-in WDT 4150af, peripheral control various parallel I / O port 4150ag and a dedicated controller that performs data transfer independently between devices such as the peripheral control A / D converter 4150ak and the peripheral control CPU core 4150aa without using the DMA0 ~ It has four channels called DMA3.

  Specifically, the peripheral control DMA controller 4150ac includes a storage device of a peripheral control built-in RAM 4150ab incorporated in the peripheral control MPU 4150a, various peripheral control serial I / O ports 4150ae and peripheral control built-in WDT 4150af incorporated in the peripheral control MPU 4150a. In order to transfer data independently between the peripheral control various parallel I / O ports 4150ag and the input / output devices such as the peripheral control A / D converter 4150ak without the peripheral control CPU core 4150aa. The peripheral control built-in RAM 4150ab reads / writes data from / to the storage device via the internal bus 4150ah, while the peripheral control serial I / O port 4150ae, the peripheral control built-in WDT 4150af, and the peripheral control various parallel I / O port 4150. g, and the peripheral control A / D converter input and output devices such as 4150Ak, via the peripheral control bus controller 4150ad and peripheral bus 4150Ai, reading and writing.

  The peripheral control DMA controller 4150ac is a storage device such as a peripheral control ROM 4150b, a peripheral control RAM 4150c, and a peripheral control SRAM 4150d externally attached to the peripheral control MPU 4150a, and various peripheral control serial I / Os built in the peripheral control MPU 4150a. Without the peripheral control CPU core 4150aa between the input / output devices such as the O port 4150ae, the peripheral control built-in WDT 4150af, the peripheral control various parallel I / O ports 4150ag, and the peripheral control A / D converter 4150ak. In order to perform data transfer independently, peripheral control bus controller 4150ad and external bus 4150h are connected to storage devices such as peripheral control ROM 4150b, peripheral control RAM 4150c, and peripheral control SRAM 4150d. The peripheral control I / O port 4150ae, peripheral control built-in WDT 4150af, peripheral control various parallel I / O port 4150ag, peripheral control A / D converter 4150ak, etc. Reading and writing are performed via the control bus controller 4150ad and the peripheral bus 4150ai.

  The peripheral control bus controller 4150ad controls the internal bus 4150ah, peripheral bus 4150ai, and external bus 4150h to control the central processing unit of the peripheral control MPU core 4150aa, peripheral control built-in RAM 4150ab, peripheral control ROM 4150b, peripheral control RAM 4150c, and peripheral control Various devices such as storage devices such as SRAM 4150d, peripheral control various serial I / O ports 4150ae, peripheral control built-in WDT 4150af, peripheral control various parallel I / O ports 4150ag, and peripheral control A / D converter 4150ak It is a dedicated controller that exchanges various data between them.

  Peripheral control various serial I / O ports 4150ae are game board side decorative board serial I / O port, motor drive board serial I / O port, frame side decoration board serial I / O port, frame decoration drive amplifier board motor Serial I / O port, main control board serial I / O port, operation unit information acquisition serial I / O port, and LOCKN signal output request serial I / O port.

  Peripheral control built-in watchdog timer (peripheral control built-in WDT) 4150af is a timer for monitoring whether the system of the peripheral control MPU 4150a is running out of control, and when this timer is up, the hardware reset is performed. It has become. That is, if the peripheral control CPU core 4150aa does not output a clear signal for clearing the timer to the peripheral control built-in WDT 4150af within a certain period (until the timer expires) when the watchdog timer is started, the peripheral control CPU core 4150aa That would be the case. When the peripheral control CPU core 4150aa starts the watchdog timer and outputs the clear signal to the peripheral control built-in WDT 4150af within a certain period, the peripheral control CPU core 4150aa can restart the timer count, so that the reset is not performed.

  The peripheral control various parallel I / O port 4150ag outputs various latch signals such as a game board side motor drive latch signal and a door side motor drive light emission latch signal, and also outputs a clear signal to the peripheral control external WDT 4150e, Award balls based on game balls entered in various winning ports such as the first starting port 2101, the second starting port 2102, the general winning ports 2104, 2201 and the big winning port 2103 shown in FIG. When the number of game balls scheduled to be paid out reaches a predetermined number of balls (in this embodiment, it is set to 10), the main prize ball is used as the main prize ball number information to notify that fact. Output the number information output signal to the external terminal board 784 or when the power is cut off based on the power consumption status history information stored in the power consumption status history RAM 4150f (power supply As power-saving mode information for reporting the state of power consumed by the pachinko gaming machine 1 at the time of power recovery in the previous time) and reporting the state of transition to the power-saving power saving mode for suppressing power consumed by the pachinko gaming machine 1 The motor drive board 4180 is provided with detection signals from various detection switches for outputting power-saving mode information output signals to the external terminal board 784 and detecting the original positions and movable positions of various movable bodies provided on the game board 4. This is serialized by a game board side serial transmission circuit (not shown), and the serialized movable body detection data is received from the game board side serial transmission circuit by the peripheral I / O port for the motor drive board of the peripheral control MPU 4150a. Output body information acquisition latch signal. Note that the output control of the main prize ball number information output signal and the output control of the power saving mode information output signal are executed in a peripheral control unit 1 ms timer interrupt process described later.

  The peripheral control A / D converter 4150ak is electrically connected to the volume adjustment volume 4140a, and the resistance value is changed by rotating the knob portion of the volume adjustment volume 4140a, and the resistance at the rotation position of the knob portion is changed. The voltage divided by the value is converted from an analog value to a digital value, and converted to a value in 1024 steps from a value 0 to a value 1023. In the present embodiment, the values of 1024 levels are divided into seven and managed as substrate volumes 0-6. The substrate volume 0 is set to mute, the substrate volume 6 is set to the maximum volume, and the volume is set to increase from the substrate volume 0 toward the substrate volume 6. The peripheral control MPU 4150a (peripheral control CPU core 4150aa) controls the liquid crystal and sound control unit 4160 (a sound source built-in VDP 4160a, which will be described later) so as to achieve the volume set to the substrate volume 0 to 6, and the speaker provided in the main body frame 3 Music and sound effects flow from the speakers housed in the box 820 and the speakers 130 provided on the door frame 5. In this way, music and sound effects flow from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 by volume adjustment based on the turning operation of the knob portion. .

  In the present embodiment, in addition to music and sound effects, notification sounds for notifying a hall clerk or the like of the occurrence of a malfunction of the pachinko gaming machine 1 or fraudulent acts on the pachinko gaming machine 1, contents relating to game effects, etc. (For example, the screen unfolded on the game board side effect display unit 1900 is rendered more powerful, or is notified that there is a high possibility of shifting to a game state advantageous to the player). ) Also flows from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, but the notification sound and the notification sound are adjusted in volume based on the turning operation of the knob portion. The flow from the mute to the maximum volume is controlled by a liquid crystal and sound control unit 4160 (a sound source built-in VDP4 which will be described later). 60a) The peripheral control MPU4150a (peripheral control CPU core 4150Aa) is adapted to be able to adjust and control. The volume adjusted by this program can be smoothly changed from the mute to the maximum volume, unlike the substrate volume divided into the above seven stages. Thus, for example, even when a hall clerk or the like rotates the knob portion of the volume adjustment volume 4140a to set the volume to a low level, the speakers and doors housed in the speaker box 820 provided in the main body frame 3 Although the production sound such as music and sound effects flowing from the speaker 130 provided in the frame 5 is reduced, the sound volume is increased when a malfunction occurs in the pachinko gaming machine 1 or when the player is cheating. In the embodiment, the notification sound set to the maximum volume) can be played. Therefore, even if the volume of the production sound is reduced, it is possible to prevent the hall clerk or the like from becoming difficult to notice the occurrence of a malfunction or the player's cheating due to the notification sound. Also, based on the current board volume set by volume adjustment based on the turning operation of the knob part, the volume of the advertisement sound is reduced so as not to interfere with the music and sound effects. In addition to music and sound effects, there is a possibility that the screen unfolded on the game board side effect display unit 1900 will be rendered more powerful, or that it will shift to a gaming state advantageous to the player. You can also announce that it is expensive.

[7-4-1b. Peripheral control ROM]
The peripheral control ROM 4150b stores in advance various control programs, various data, various control data, and various schedule data for controlling the peripheral control unit 4150, the liquid crystal and sound control unit 4160, the RTC control unit 4165, and the like. The various schedule data includes screen generation schedule data for generating a screen to be drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e), light emission mode generation schedule data for generating various LED light emission modes, music And sound generation schedule data for generating sound effects, etc., electric drive source schedule data for generating drive modes of electric drive sources such as motors and solenoids, and the number of game balls to be paid out as prize balls Main prize ball information output signal schedule data for generating a main prize ball information output signal for transmitting to the hall computer as main prize ball information that the number of balls set (10 balls in this embodiment) has been reached. is there.

  The screen generation schedule data is configured by arranging screen data defining the configuration of the screen in time series, and includes screen generation schedule data for the game board side effect display unit 1900 (liquid crystal panel 5000e). The order of screens to be displayed is specified. The light emission mode generation schedule data is composed of light emission data defining the light emission mode arranged in time series, and the light emission mode generation schedule data for the plurality of LEDs provided on each decorative board of the game board 4 and the door There are schedule data for light emission mode generation for a plurality of LEDs provided on each decorative board of the frame 5, and the order of the light emission modes is defined respectively. In addition, the light emission mode generation schedule data for the plurality of LEDs provided on each decorative board of the game board 4 includes contents of the light guide plates provided in the game board side effect display unit 1900 in addition to the contents for defining the light emission mode. Among them, the contents for defining (designating) one light guide plate used as a backlight are also included in the light emission data and arranged in time series.

  The sound generation schedule data is configured by arranging sound command data in time series, and defines the order in which music and sound effects flow. The sound command data includes an output channel number for instructing which output channel to use among a plurality of output channels in a built-in sound source of the sound source built-in VDP 4160a of the liquid crystal and sound control unit 4160 described later, and a sound source built-in VDP 4160a. A track number for instructing which track to incorporate sound data such as music and sound effects out of a plurality of tracks in the built-in sound source is defined. The electrical drive source schedule data is configured by arranging drive data of electrical drive sources such as motors and solenoids in time series, and defines the operation of electrical drive sources such as motors and solenoids. The main award ball information output signal schedule data is a hall with main award ball information indicating that the number of game balls to be paid out as a prize ball has reached a predetermined number (10 balls in this embodiment). Output waveform data for generating a main prize ball information output signal to be transmitted to the computer is arranged in time series, and an output waveform of the main prize ball information output signal is defined.

  Various control programs stored in the peripheral control ROM 4150b may be read out and executed directly from the peripheral control ROM 4150b, or copied to various control program copy areas of the peripheral control RAM 4150c described later when the power is turned on. Some are read and executed. In addition, various data, various control data, and various schedule data stored in the peripheral control ROM 4150b may be directly read from the peripheral control ROM 4150b, or when various power control data copy areas of the peripheral control RAM 4150c described later are turned on. Some of which are copied in the above are read out.

[7-4-1c. Peripheral control RAM]
As shown in FIG. 18, the peripheral control RAM 4150c externally attached to the peripheral control MPU 4150a is a backup that exclusively stores information to be backed up among various information updated by executing various control programs. A management target work area 4150ca, a backup first area 4150cb and a backup second area 4150cc for storing a copy of various information stored in the backup management target work area 4150ca, and a peripheral control ROM 4150b. Various control program copy area 4150cd for storing a copy of the various control programs exclusively, and various data, various control data, various schedule data, etc. stored in peripheral control ROM 4150b, etc. Various control data copy area 4150ce that stores the copied data exclusively, and backup non-management target that stores information that is not backed up among various information updated by executing various control programs And a work area 4150cf.

  When the pachinko gaming machine 1 is turned on (including when power is restored due to a momentary power failure or a power failure), the value 0 is forcibly written to the backup unmanaged work area 4150cf and cleared to zero. For the backup management target work area 4150ca, the backup first area 4150cb, and the backup second area 4150cc, the power-on state command (see FIG. 45) from the main control board 4100 is cleared to RAM when the pachinko gaming machine 1 is powered on. Instructing the start of the effect and the gaming state (for example, instructing the start of the effect when the operation switch 860a shown in FIG. 14 is operated within a predetermined period from when the power is turned on) Is cleared to zero.

  The backup management target work area 4150ca is effect information (various information updated in the peripheral control unit steady process executed each time a V blank signal from the VDP 4160a with built-in sound source of the liquid crystal and sound control unit 4160 described later is input) Bank 0 (1fr) for storing 1fr) exclusively as a backup target, and production information (1ms) which is various information updated in the peripheral control unit 1ms timer interrupt process executed every time a 1ms timer interrupt described later occurs. Bank 0 (1 ms) that is stored exclusively as a backup target. Here, the names of Bank0 (1fr) and Bank0 (1 ms) will be briefly described. “Bank” is a minimum management unit representing the size of a storage area for storing various information. The subsequent “0” means that the storage area is normally used for storing various information updated by executing various control programs. That is, “Bank 0” means that the size of the storage area that is normally used is the minimum management unit. In addition, “Bank1,” “Bank2,” “Bank3,” and “Bank4” provided in an area extending from a backup first area 4150cb to a backup second area 4150cc, which will be described later, are in the same storage area as “Bank0”. It means having a size. As will be described later, “(1fr)” is a screen from the peripheral control MPU 4150a when the sound generator built-in VDP 4160a outputs drawing data for one screen (one frame) to the game board side effect display unit 1900 (liquid crystal panel 5000e). Since a V blank signal indicating that data can be accepted is output to the peripheral control MPU 4150a, every time a V blank signal is input, in other words, every one frame (1 frame) From the place where the control unit steady process is executed, “Bank0”, “Bank1”, “Bank2”, “Bank3”, and “Bank4” are appended respectively (effect information (1fr) and effect backup information (described later)). 1fr) is also used in the same meaning). As described later, “(1 ms)” indicates that “Bank0”, “Bank1”, “Bank2”, “Bank3”, “Bank0”, “Bank1”, “Bank3”, and the like are executed every time a 1 ms timer interrupt occurs. And “Bank 4”, respectively (the effect information (1 ms) and the effect backup information (1 ms) described later are also used in the same meaning).

  Bank 0 (1fr) includes a game board side peripheral control MPU control target LED transmission data storage area 4150caa, a frame side peripheral control MPU control target LED transmission data storage area 4150cab, a reception command storage area 4150cac, and an RTC information acquisition storage area 4150cad. And a schedule data storage area 4150cae. The game board side peripheral control MPU control target LED transmission data storage area 4150caa is a plurality of game board side peripheral control MPU control targets that are controlled by the peripheral control MPU 4150a directly among the decorative boards of the game board 4. This is a storage area in which game board side light emission data SL-DAT for outputting lighting signals, blinking signals, or gradation lighting signals to a plurality of LEDs (decorative LEDs) provided on each of the decorative boards is set. In the frame side peripheral control MPU control target LED transmission data storage area 4150cab, among the decorative boards of the door frame 5, a plurality of frame side peripheral control MPU control target decorations that are controlled by the peripheral control MPU 4150a are directly controlled. This is a storage area in which frame side light emission data STL-DAT for outputting lighting signals, blinking signals, or gradation lighting signals to a plurality of LEDs (decorative LEDs) provided on each of the substrates is set. The received command storage area 4150cac is a storage area in which various commands transmitted from the main control board 4100 are received and the received various commands are set. The RTC information acquisition storage area 4150cad is a storage area in which various types of information acquired from the RTC control unit 4165 (RTC built-in RAM 4165aa of the RTC 41654a described later) are set. The schedule data storage area 4150cae is a storage area in which various schedule data corresponding to the received command are set based on the command received from the main control board 4100 (main control MPU 4100a). In the schedule data storage area 4150cae, some schedule data copied from the peripheral control ROM 4150b to the various control data copy areas 4150ce are read and set. Some are set.

  Bank 0 (1 ms) includes a frame decoration drive amplifier board side motor transmission data storage area 4150 caf, a motor drive board side transmission data storage area 4150 cag, a movable body information acquisition storage area 4150 cah, an operation unit information acquisition storage area 4150 cai, and a drawing. A state information acquisition storage area 4150cak and the like are provided. In the frame decoration drive amplifier board side motor transmission data storage area 4150caf, door side motor drive data STM-DAT for outputting a drive signal to an electric drive source such as a dial drive motor 414 provided in the door frame 5 is stored. This is a storage area to be set, and a motor drive board side transmission data storage area 4150cag is used to output a drive signal to an electric drive source such as a motor or solenoid for operating various movable bodies provided in the game board 4. This is a storage area where the game board side motor drive data SM-DAT is set. The movable body information acquisition storage area 4150cah is provided in the game board 4 based on detection signals from various detection switches provided in the game board 4. This is a storage area in which various information obtained by acquiring the original position and the movable position of various movable bodies is set, and an operation unit information acquisition storage area 4150ca. Includes various information (for example, in the operation unit 400) obtained from the rotation (rotation direction) of the dial operation unit 401 and the operation of the pressing operation unit 405 based on detection signals from various detection switches provided in the operation unit 400. The rotation (rotation direction) history information of the dial operation unit 401, the operation history information of the pressing operation unit 405, and the like created based on detection signals from the various detection switches provided. In the state information acquisition storage area 4150cak, when the frame decoration drive amplifier board 194 receives the drawing data from the sound source built-in VDP 4160a in the peripheral control board 4140 and determines that the received drawing data is abnormal data, the fact is displayed. Peripheral control board 4140 and frame decoration drive amplifier based on LOCKN signal output for transmission A storage area in which various information obtained the occurrence of defects in the frequency or malfunction in the connection between the plate 194 is set.

  Bank 0 (1fr) game board side peripheral control MPU control target LED transmission data storage area 4150caa and frame side peripheral control MPU control target LED transmission data storage area 4150cab, and Bank 0 (1 ms) frame decoration drive amplifier board side The motor transmission data storage area 4150caf and the motor drive board side transmission data storage area 4150cag are each divided into two areas, a first area and a second area.

  The game board side peripheral control MPU control target LED transmission data storage area 4150caa is stored in the first area of the game board side peripheral control MPU control target LED transmission data storage area 4150caa when a peripheral control unit steady process described later is executed. When the game board side light emission data SL-DAT is set and the next peripheral control unit steady process is executed, the game board side light emission is generated in the second area of the game board side peripheral control MPU control target LED transmission data storage area 4150caa. Data SL-DAT is set, and each time the peripheral control unit steady process is executed, the first and second areas of the game board side peripheral control MPU control target LED transmission data storage area 4150caa The game board side light emission data SL-DAT are alternately set. The peripheral control unit steady process is executed. For example, in the current peripheral control unit steady process, the game board side light emission data SL-DAT is set in the second area of the game board side peripheral control MPU control target LED transmission data storage area 4150caa. When the previous peripheral control unit steady process is executed, based on the game board side light emission data SL-DAT set in the first area of the game board side peripheral control MPU control target LED transmission data storage area 4150caa Processing is going on.

  When the peripheral control unit steady process is executed, the frame-side peripheral control MPU control target LED transmission data storage area 4150cab has a frame-side light emission in the first area of the frame-side peripheral control MPU control target LED transmission data storage area 4150cab. When the data STL-DAT is set and the next peripheral control unit steady process is executed, the frame side light emission data STL-DAT is set in the second area of the frame side peripheral control MPU control target LED transmission data storage area 4150cab. Each time the peripheral control unit steady process is executed, the frame-side emission data STL-DAT is stored in the first and second areas of the frame-side peripheral control MPU control target LED transmission data storage area 4150cab. Set alternately. For example, when the frame-side emission data STL-DAT is set in the second area of the frame-side peripheral control MPU control target LED transmission data storage area 4150cab in the current peripheral control section regular process. When the previous peripheral control unit steady process is executed, the process proceeds based on the frame side emission data STL-DAT set in the first area of the frame side peripheral control MPU control target LED transmission data storage area 4150cab. It is like that.

  The frame decoration drive amplifier board side motor transmission data storage area 4150caf has a door in the first area of the frame decoration drive amplifier board side motor transmission data storage area 4150caf when a later-described peripheral control unit 1 ms timer interrupt process is executed. When the side motor drive data STM-DAT is set and the next peripheral control unit 1 ms timer interrupt process is executed, the door side motor drive data STM is stored in the second area of the frame decoration drive amplifier board side motor transmission data storage area 4150caf. -DAT is set, and each time the peripheral control unit 1 ms timer interrupt process is executed, the door side is connected to the first area and the second area of the frame decoration drive amplifier board side motor transmission data storage area 4150caf. Motor drive data STM-DAT is set alternately. The peripheral control unit 1 ms timer interrupt process is executed. For example, in this peripheral control unit 1 ms timer interrupt process, the door side motor drive data STM-DAT is stored in the second area of the frame decoration drive amplifier board side motor transmission data storage area 4150caf. When set, the door side motor drive data STM-DAT set in the first area of the frame decoration drive amplifier board side motor transmission data storage area 4150caf when the previous peripheral control unit 1 ms timer interrupt process was executed. The process is based on this.

  When the peripheral control unit 1 ms timer interrupt process is executed, the motor drive board side transmission data storage area 4150cag is set with the game board side motor drive data SM-DAT in the first area of the motor drive board side transmission data storage area 4150cag. When the next peripheral control unit 1 ms timer interrupt process is executed, the game board side motor drive data SM-DAT is set in the second area of the motor drive board side transmission data storage area 4150cag, Each time the peripheral control unit 1 ms timer interrupt process is executed, the game board side motor drive data SM-DAT are alternately set in the first area and the second area of the motor drive board side transmission data storage area 4150cag. The peripheral control unit 1 ms timer interrupt process is executed. For example, in the current peripheral control unit 1 ms timer interrupt process, the game board side motor drive data SM-DAT is set in the second area of the motor drive board side transmission data storage area 4150cag. Sometimes, when the previous peripheral control unit 1 ms timer interrupt process is executed, the process proceeds based on the game board side motor drive data SM-DAT set in the first area of the motor drive board side transmission data storage area 4150cag. It is like that.

  Next, the backup first area 4150cb and backup second area 4150cc that store specially copied production information, which is various information stored in the backup management target work area 4150ca, will be described. In the backup first area 4150cb and the backup second area 4150cc, two pairs of two banks are managed as one page. Production information (1fr), which is the content stored in Bank0 (1fr), which is a storage area that is normally used, is produced as production backup information (1fr) every time the peripheral control unit steady process is executed for each frame (1frame). In addition, the production information (1 ms) which is the content stored in Bank0 (1 ms), which is a storage area normally used, is copied to the backup first area 4150 cb and the backup second area 4150 cc at high speed by the peripheral control DMA controller 4150ac. As the production backup information (1 ms), the peripheral control DMA controller 41 is assigned to the backup first area 4150 cb and the backup second area 4150 cc each time the peripheral control unit 1 ms timer interrupt process is executed every time a 1 ms timer interrupt occurs. It is copied to the high speed by 0ac. The consistency of one page is determined by whether or not the contents of two banks constituting the page match.

  Specifically, the backup first area 4150cb is managed as a pair of Bank1 (1fr) and Bank2 (1fr) as one pair, and Bank1 (1ms) and Bank2 (1ms) as one pair. ing. The contents stored in Bank0 (1fr), which is a storage area that is normally used, are the peripheral control DMA in Bank1 (1fr) and Bank2 (1fr) each time the peripheral control unit steady process is executed for each frame (1frame). The memory that is copied at a high speed by the controller 4150ac and stored in Bank0 (1 ms), which is a storage area that is normally used, is stored every time a peripheral control unit 1 ms timer interrupt process is executed every time a 1 ms timer interrupt occurs. The peripheral control DMA controller 4150ac copies the data to Bank1 (1ms) and Bank2 (1ms) at high speed. The consistency of this page is determined by whether or not the contents of Bank1 (1fr) and Bank2 (1fr) match. Bank1 (1ms) and Bank2 ( It carried out by whether or not the contents of the ms) are the same.

  The backup second area 4150cc is managed as one page with a total of two pairs, with Bank3 (1fr) and Bank4 (1fr) as one pair and Bank3 (1ms) and Bank4 (1ms) as one pair. The contents stored in Bank0 (1fr), which is a storage area that is normally used, are the peripheral control DMA in Bank3 (1fr) and Bank4 (1fr) each time the peripheral control unit steady process is executed for each frame (1frame). The memory that is copied at a high speed by the controller 4150ac and stored in Bank0 (1 ms), which is a storage area that is normally used, is stored every time a peripheral control unit 1 ms timer interrupt process is executed every time a 1 ms timer interrupt occurs. It is copied to Bank 3 (1 ms) and Bank 4 (1 ms) at high speed by the peripheral control DMA controller 4150ac, and the consistency of this page is determined by whether or not the contents of Bank 3 (1 fr) and Bank 4 (1 fr) match. Bank3 (1 ms) and Bank4 ( It carried out by whether or not the contents of the ms) are the same.

  As described above, in this embodiment, the backup first area 4150cb has one pair of Bank1 (1fr) and Bank2 (1fr), and one pair of Bank1 (1ms) and Bank2 (1ms). It is an area to manage as a page, and the backup second area 4150 cc has a total of 2 pairs, with Bank 3 (1 fr) and Bank 4 (1 fr) as one pair, Bank 3 (1 ms) and Bank 4 (1 ms) as one pair This is an area for management as one page. Different ID codes are stored at the beginning and end of each page, that is, at the beginning and end of the backup first area 4150cb and backup second area 4150cc.

  In the present embodiment, the production information (1fr) that is the content stored in Bank0 (1fr) that is a storage area that is normally used is the production control information (1fr), and the peripheral control unit for each frame (1frame). Every time the steady process is executed, the contents are copied to the backup first area 4150cb and the backup second area 4150cc at high speed by the peripheral control DMA controller 4150ac and stored in Bank0 (1 ms) which is a storage area used normally. The production information (1 ms) is, as production backup information (1 ms), every time the 1 ms timer interrupt is generated, the backup first area 4150 cb and the backup second area 4150 cc are executed each time the peripheral control unit 1 ms timer interruption process is executed. Peripheral control Although designed to be copied at a high speed by the MA controller 4150Ac, a program for executing a fast copy from these peripheral control DMA controller 4150Ac are common. That is, in this embodiment, the production information (1fr) and the production information (1 ms) are managed by a common management method (execution of a common program).

[7-4-1d. Peripheral control SRAM]
A peripheral control SRAM 4150d externally attached to the peripheral control MPU 4150a includes a backup management target work area 4150da that exclusively stores information to be backed up among various information updated by executing various control programs. A backup first area 4150db and a backup second area 4150dc are provided for storing a copy of various information stored in the backup management target work area 4150da. The contents stored in the peripheral control SRAM 4150d are the power-on state commands (see FIG. 45) from the main control board 4100 when the pachinko gaming machine 1 is powered on (including when power is restored due to an instantaneous power failure or power failure). ) Instructs the start of the RAM clear effect and the gaming state (for example, instructs the start of the effect when the operation switch 860a shown in FIG. 14 is operated within a predetermined period from when the power is turned on. Is not cleared to zero. This is completely different from the point that the backup management target work area 4150ca, the backup first area 4150cb, and the backup second area 4150cc of the peripheral control RAM 4150c described above are cleared to zero. Further, when the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400 is operated within a predetermined time after the pachinko gaming machine 1 is turned on, a screen for performing the setting mode is displayed on the game board side effect display unit 1900 (liquid crystal display). Displayed on the panel 5000e). By operating the dial operation unit 401 and the pressing operation unit 405 of the operation unit 400 according to the setting mode screen, each content (item) stored in the peripheral control SRAM 4150d (for example, a history of occurrence of a big hit gaming state, etc.) On the other hand, the contents (items) stored in the peripheral control RAM 4150c are not displayed at all and cannot be cleared in the setting mode. This point is also completely different between the peripheral control RAM 4150c and the peripheral control SRAM 4150d.

  The backup management target work area 4150da is production information (SRAM) which is various information continued across days (for example, information for managing the history of occurrence of the big hit gaming state and special production flag management) Information) and the like are stored in a dedicated manner as a backup target. Here, the name of Bank 0 (SRAM) will be briefly described. As described above, “Bank” is a minimum management unit indicating the size of a storage area for storing various types of information. The subsequent “0” means that the storage area is normally used for storing various information updated by executing various control programs. That is, “Bank 0” means that the size of the storage area that is normally used is the minimum management unit. “Bank1,” “Bank2,” “Bank3,” and “Bank4” provided in an area extending from a backup first area 4150db to a backup second area 4150dc, which will be described later, are in the same storage area as “Bank0”. It means having a size. Since “(SRAM)” is a backup target of various information stored in the peripheral control SRAM 4150d externally attached to the peripheral control MPU 4150a, “Bank0”, “Bank1”, “Bank2”, “Bank3” , And “Bank 4”, respectively (effect information (SRAM) and effect backup information (SRAM) to be described later are also used in the same meaning).

  Next, the backup first area 4150db and backup second area 4150dc that store specially copied production information (SRAM), which is various information stored in the backup management target work area 4150da, will be described. The backup first area 4150db and the backup second area 4150dc are managed with two banks as one pair, and this one pair as one page. Production information (SRAM), which is the content stored in Bank0 (SRAM), which is a storage area used normally, is production backup information (SRAM) each time the peripheral control unit steady process is executed for each frame (1 frame). The peripheral control DMA controller 4150ac copies the backup first area 4150db and the backup second area 4150dc at high speed. The consistency of one page is determined by whether or not the contents of two banks constituting the page match.

  Specifically, in the backup first area 4150db, Bank1 (SRAM) and Bank2 (SRAM) are managed as one pair, and this one pair is managed as one page. The contents stored in Bank0 (SRAM), which is a storage area that is normally used, are stored in the peripheral control DMA in Bank1 (SRAM) and Bank2 (SRAM) each time the peripheral control unit steady process is executed for each frame (1 frame). This page is copied at high speed by the controller 4150ac, and the consistency of this page is determined by whether or not the contents of Bank1 (SRAM) and Bank2 (SRAM) match.

  In the backup second area 4150dc, Bank3 (SRAM) and Bank4 (SRAM) are managed as one pair, and this one pair is managed as one page. The contents stored in Bank 0 (SRAM), which is a storage area that is normally used, are stored in the peripheral control DMA in Bank 3 (SRAM) and Bank 4 (SRAM) each time the peripheral control unit steady process is executed for each frame (1 frame). This page is copied at high speed by the controller 4150ac, and the consistency of this page is determined by whether or not the contents of Bank3 (SRAM) and Bank4 (SRAM) match.

  As described above, in this embodiment, the backup first area 4150db is an area for managing Bank 1 (SRAM) and Bank 2 (SRAM) as one pair, and managing this one pair as one page. Reference numeral 4150 dc is an area for managing Bank 1 (SRAM) and Bank 4 (SRAM) as one pair, and managing this one pair as one page. Different ID codes are stored at the beginning and end of each page, that is, at the beginning and end of the backup first area 4150db and backup second area 4150dc.

[7-4-1e. Power consumption status history RAM]
The power consumption status history RAM 4150f externally attached to the peripheral control MPU 4150a samples the value (power consumption suppression step) transmitted by the power consumption suppression signal from the power supply board 851 at a predetermined cycle (peripheral to be described later) This is stored and held as power consumption status history information (in the power consumption status history information creation processing in the control unit 1 ms timer interrupt processing). Specifically, the peripheral control MPU 4150a executes a peripheral control unit 1ms timer interrupt process every time a 1ms timer interrupt described later occurs, and in this peripheral control unit 1ms timer interrupt process, a power consumption suppression signal from the power supply board 851 is executed. Is sampled and stored in the power consumption status history RAM 4150f as power consumption status history information. In this embodiment, the power consumption status history information can store and hold the value (power consumption suppression stage) transmitted by the power consumption suppression signal for 3000 times as the number of samplings. When the transmitted value (power consumption suppression stage) is stored and held, the values (power consumption suppression stage) transmitted by the power consumption suppression signal already sampled up to the previous time are shifted one by one so that they are arranged in time series. The value (power consumption suppression stage) that is sampled and transmitted by the power consumption suppression signal is stored and held, and when the number of sampling reaches 3000 times, the value that is sampled and transmitted by the power consumption suppression signal (power consumption) Each time the suppression stage is stored, the value that the oldest sampled power consumption suppression signal conveys ( Power consumption inhibiting step) is adapted to be discarded one by one in sequence. In other words, the power consumption status history information includes the value (power consumption suppression stage) conveyed by the power consumption suppression signal sampled this time for the most recent 3000 times (in other words, the peripheral control MPU 4150a executes the peripheral control unit 1 ms timer interrupt process). Each time the value (power consumption suppression stage) transmitted by the power consumption suppression signal from the power supply board 851 is sampled and sequentially stored in the power consumption status history RAM 4150f as power consumption status history information, the peripheral control unit 1 ms timer interrupt processing Is executed 3000 times so that values (power consumption suppression steps) transmitted by the power consumption suppression signal for 3 seconds (= 1 ms × 3000 times) are arranged in time series.

[7-4-1f. Power saving mode transition notification LED]
The power saving mode transition notification LED 4150k indicates the power status consumed by the pachinko gaming machine 1 when the power is turned off (immediately before the power is turned off) based on the power consumption status history information stored in the power consumption status history RAM 4150f. This is to notify the state of transition to the power saving mode at the time of power recovery that suppresses the power consumed by the pachinko gaming machine 1 by grasping in FIG. The power saving mode transition notification LED 4150k is not electrically connected to the peripheral control board 4140 via a signal wiring, but is directly mounted on the peripheral control board 4140 so that the light emission mode is controlled by the peripheral control MPU 4150a. Has been. In this embodiment, the power-saving mode transition notification LED 4150k is a surface-mount type, which employs a high-luminance single color light emitting in green, and a staff such as a hall clerk shows the lock device shown in FIGS. When the main body frame 3 is opened with respect to the outer frame 2 by releasing the closed state of the main body frame 3 with respect to the outer frame 2 by inserting a key into the 1000 cylinder lock 1010 and rotating, The power saving mode transition notification LED 4150k is directly soldered to the peripheral control board 4140 at the position where the main frame 3 is attached to the back side of the pachinko gaming machine 1 (that is, the back side of the game board 4) and the outer frame 2. A staff member such as a clerk in the hall can see the light emission mode of the power saving mode transition notification LED 4150k from the open side of the main body frame 3 when opened.

  Specifically, the peripheral control MPU 4150a stores the power consumption status history information stored and held in the power consumption status history RAM 4150f in the power saving power saving mode transition determination process in the power-on process of the peripheral control unit described later that is executed at the time of power recovery. Based on the above, it is determined whether or not to shift to the power saving mode at the time of power recovery by identifying the power status (power consumption suppression stage described later) consumed by the pachinko gaming machine 1 at the time of power-off (immediately before power-off). The peripheral control MPU 4150a sets the light emission mode of the power saving mode transition notification LED 4150k to the non-power saving notification mode (lighting state) when the determination result does not shift to the power saving power saving mode, while the determination result is the power saving power saving mode. When switching to the power saving mode, the light emission mode of the power saving mode transition notification LED 4150k is set to the power saving notification mode (light-off state). A staff member such as a store clerk of the hall rotates whether the pachinko machine 1 is in a state where it has shifted to the power saving mode after power recovery by inserting a key into the cylinder lock 1010 of the lock device 1000, By releasing the closed state of the main body frame 3 with respect to the outer frame 2 and opening the main body frame 3 with respect to the outer frame 2, the light emission mode of the power saving mode transition notification LED 4150k can be confirmed by visual observation.

  Here, the reason for adopting the surface mounting type that is directly soldered to the peripheral control board 4140 as the power saving mode transition notification LED 4150k will be briefly described. When the power saving mode transition notification LED 4150k is arranged away from the peripheral control board 4140 and is electrically connected to the peripheral control board 4140 through the signal wiring, for example, a staff member such as a hall clerk is working. When the signal wiring connector is disconnected from the peripheral control board 4140 or the main body frame 3 is opened with respect to the outer frame 2, the signal wiring is placed in the gap on the closing side of the main body frame 3. If the gap between the outer frame 2 and the outer frame 2 is closed to narrow the gap and the signal wiring is disconnected, it becomes difficult for the peripheral control MPU 4150a to control the light emission mode of the power saving mode transition notification LED 4150k. Because. In this embodiment, as the power saving mode transition notification LED 4150k, a surface mount type that is soldered directly to the peripheral control board 4140 is adopted, but a lead type that can be soldered directly to the peripheral control board 4140 is used. Also good.

[7-4-2. Liquid crystal and sound control unit]
The drawing control of the game board side effect display unit 1900 (liquid crystal panel 5000e), the light emission control of various LEDs, the music accommodated in the speaker box 820 provided in the main body frame 3, and the music flowing from the speaker 130 provided in the door frame 5. The liquid crystal and sound control unit 4160 that controls sound such as sound and sound has a built-in sound source for sound control such as music and sound effects (hereinafter referred to as “built-in sound source”). As shown in FIG. 17, the liquid crystal and sound control unit 4160 controls the drawing control of the game board side effect display unit 1900 (liquid crystal panel 5000 e) and the control target directly controlled among the decorative boards of the game board 4. Light emission control of a plurality of LEDs (decorative LEDs) provided on each of the plurality of game board side VDP control target decoration boards and a control object directly controlled by each of the decoration boards of the door frame 5 A sound source built-in VDP (abbreviation of Video Display Processor) 4160a for performing light emission control of a plurality of LEDs (decorative LEDs) provided on each of the plurality of frame side VDP control target decorative boards, and a game board side effect display unit 1900 In addition to the various character data of the screen drawn (displayed) on the (liquid crystal panel 5000e), a predetermined screen (in this embodiment, In addition to dummy data for drawing red (R): 50%, green (G): 50%, blue (B): 50%), each of the decorative boards of the game board 4 A plurality of game board sides for setting light emission modes of a plurality of LEDs (decorative LEDs) provided on a plurality of game board side VDP control target decoration boards that are controlled objects directly controlled by the sound source built-in VDP 4160a Among the light emission mode setting image data and each decorative board of the door frame 5, a plurality of LEDs (decorative elements) provided on each of the plurality of frame side VDP control target decorative boards that are controlled by the built-in sound source VDP 4160a. LED) and a liquid crystal and sound control ROM 4160b for storing a plurality of door frame side light emission mode setting image data and a plurality of various sound data such as music and sound effects, and serial Audio data transmission IC 4160c for transmitting the converted music, sound effect, etc. as audio data to the frame decoration drive amplifier board 194 via the frame peripheral relay terminal plate 868 and the peripheral relay terminal plate 882, and serialized drawing Transmitter IC 4160d for transmitting data toward frame decoration drive amplifier board 194 via frame peripheral relay terminal plate 868 and peripheral relay terminal plate 882, and LOCKN signal output request serial incorporated in peripheral control MPU 4150a of peripheral control unit 4150 A differential circuit 4160e that differentiates the LOCKN signal output request data, which is serial data output from the I / O port, into a plus signal and a minus signal, and a signal output from the transmitter IC 4160d, as well as the differentiation The signal from circuit 4160e is input. When the signal from the differential circuit 4160e is input, the circuit is connected so as to transmit the signal. On the other hand, when the signal from the differential circuit 4160e is not input, the signal is output from the transmitter IC 4160d. And a forcible switching circuit 4160f for circuit connection so as to transmit the signal.

  The peripheral control MPU 4150a of the peripheral control unit 4150 performs various controls of the peripheral control ROM 4150b or the peripheral control RAM 4150c of the peripheral control unit 4150 based on the screen generation schedule data and the light emission mode generation schedule data corresponding to the command from the main control board 4100. Extracted from the data copy area 4150ce and set in the schedule data storage area 4150cae of the peripheral control RAM 4150c. The top screen data of the screen generation schedule data and the start of the emission mode generation schedule data set in the schedule data storage area 4150cae Are extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c, and the sound source built-in VDP 416 is extracted. After output to a, triggered by the input of a V blank signal, which will be described later, following the first screen data according to the screen generation schedule data and the light emission mode generation schedule data set in the schedule data storage area 4150cae The next screen data and the next light emission data following the head light emission data are extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or the various control data copy areas 4150ce of the peripheral control RAM 4150c and output to the sound source built-in VDP 4160a. As described above, the peripheral control MPU 4150a, in accordance with the screen generation schedule data and the light emission mode generation schedule data set in the schedule data storage area 4150cae, screen data arranged in time series in the screen generation schedule data, Each time the V blank signal is input, the light emission data arranged in time series in the light emission mode generation schedule data is output to the built-in sound source VDP 4160a one by one from the top screen data and one from the top light emission data. To do.

  Also, the peripheral control MPU 4150a receives the sound command data at the head of the sound generation schedule data corresponding to the command from the main control board 4100 from the peripheral control ROM 4150b of the peripheral control unit 4150 or the various control data copy areas 4150ce of the peripheral control RAM 4150c. Extracted and set in the schedule data storage area 4150cae of the peripheral control RAM 4150c, the head sound command data of the sound generation schedule data set in the schedule data storage area 4150cae is the peripheral control ROM 4150b of the peripheral control unit 4150 or the peripheral control The schedule data storage is triggered by the input of the V blank signal after extracting from the various control data copy area 4150ce of the RAM 4150c and outputting it to the VDP 4160a with built-in sound source. In accordance with the sound generation schedule data set in the area 4150cae, the next sound command data following the head sound command data is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or the various control data copy areas 4150ce of the peripheral control RAM 4150c, and the sound source Output to built-in VDP 4160a. As described above, the peripheral control MPU 4150a receives the sound command data arranged in time series in the sound generation schedule data according to the sound generation schedule data set in the schedule data storage area 4150cae, and the V blank signal is input. Each time, the head sound command data is output to the built-in sound source VDP 4160a one by one.

  Thus, as described above, the peripheral control unit 4150 that performs the effect control controls the power-on process that is executed when the power is turned on, and is also executed after a predetermined time has elapsed since the power is turned on. A V blank signal is input from a peripheral control ROM 4150b for storing various control programs such as a sub-control program for controlling the sound, various data, various control data and various schedule data, and a sound source built-in VDP 4160a of the liquid crystal and sound control unit 4160 described later. Peripheral control RAM 4150c for storing various information continued across the peripheral control unit steady process executed every time, and peripheral control SRAM 4150d for storing various information continued across the day, The peripheral control unit 4150 stores a plurality of types of information related to effects. Can be provided with peripheral control ROM4150b, peripheral control RAM4150c, and peripheral control SRAM4150d. In addition, as described above, the liquid crystal and sound control unit 4160 has a predetermined screen in addition to a plurality of various character data on the screen drawn (displayed) on the game board side effect display unit 1900 (the liquid crystal panel 5000e). (In this embodiment, in addition to dummy data for drawing red (R): 50%, green (G): 50%, blue (B): 50%), the game board 4 For setting the light emission mode of a plurality of LEDs (decorative LEDs) provided on each of the plurality of game board side VDP control target decorative boards that are controlled by the built-in sound source VDP 4160a among the decorative boards. Among a plurality of game board side light emission mode setting image data and each decoration board of the door frame 5, a plurality of frame side VDP control target decoration bases that are controlled by the sound source built-in VDP 4160a directly A liquid crystal that stores a plurality of door frame side light emission mode setting image data for setting a light emission mode of a plurality of LEDs (decorative LEDs) provided in each of the plurality of LEDs, and a plurality of various sound data such as music and sound effects, and Since the sound control ROM 4160b is provided, the liquid crystal and sound control unit 4160 is provided with a liquid crystal and sound control unit 4160 that can store a plurality of types of information related to effects.

[7-4-2a. Sound source built-in VDP]
The built-in sound source VDP 4160a controlled by the peripheral control MPU 4150a incorporates a VRAM (hereinafter referred to as “built-in VRAM”) in addition to the above-described built-in sound source. The VRAM may be provided in a frame memory separate from the sound source built-in VDP 4160a (that is, a RAM (frame memory) externally attached to the sound source built-in VDP 4160a). When the screen data and the light emission data are input from the peripheral control MPU 4150a, the sound source built-in VDP 4160a receives the game from the liquid crystal and sound control ROM 4160b based on the input screen data and the light emission data, as shown in FIG. The game board-side character data for drawing in the display area of the liquid crystal panel 5000e included in the board-side effect display unit 1900 (hereinafter, sometimes referred to as “display area of the game board-side effect display unit 1900”) and the above-described character data. Dummy data for drawing a predetermined screen (in this embodiment, a gray screen having red (R): 50%, green (G): 50%, blue (B): 50%) is extracted. Sprite data is created for one screen (one frame) to be drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). Drawing data and a predetermined screen (in this embodiment, a gray screen having red (R): 50%, green (G): 50%, blue (B): 50%). The drawing data for one screen (one frame) to be displayed is generated in the built-in VRAM.

  The sound source built-in VDP 4160a can output the drawing data generated on the built-in VRAM from the channels CH1 and CH2. More specifically, the sound source built-in VDP 4160a is composed of the screen data defining the screen configuration drawn on the game board side effect display unit 1900 (liquid crystal panel 5000e) and the sound board built-in VDP 4160a among the decorative boards of the game board 4. The peripheral control MPU 4150a receives light emission data defining light emission modes of a plurality of LEDs (decorative LEDs) provided on each of the plurality of game board side VDP control target decorative boards that are controlled by the computer. Then, according to a predetermined game board side generation rule, game board side character data to be drawn in the display area of the game board side effect display unit 1900 from the liquid crystal and sound control ROM 4160b based on the input screen data. Game board display area provided on the built-in VRAM by extracting and creating sprite data The game board side drawing data is generated in the game board side drawing data area VRGN1a of RGN1 and, based on the inputted light emission data, among the decorative boards of the game board 4 from the liquid crystal and sound control ROM 4160b, the sound source built-in VDP 4160a Game board side light emission mode setting image data for setting a light emission mode of a plurality of LEDs (decorative LEDs) provided on each of the plurality of game board side VDP control target decorative boards that are controlled directly by Light guide plate information and electrical decoration information, which will be described later, are extracted and generated as drawing data in the game board side accompanying information area VRGN1b of the game board side display area VRGN1 provided on the built-in VRAM. Thereby, the light guide plate information and the decoration information are attached to the game board side drawing data of the screen drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e) in accordance with the predetermined game board side generation rule. The drawing data generated in the game board side display area VRGN1 is output from the channel CH1. The drawing data generated in the game board side display area VRGN1 is referred to as “game board side image object”. Note that the “predetermined game board side generation rule” will be described later.

  The sound source built-in VDP 4160a defines the configuration of a predetermined screen (in this embodiment, a gray screen having red (R): 50%, green (G): 50%, blue (B): 50%). Among the decoration data of the screen frame and the door frame 5, a plurality of LEDs (decoration LEDs) provided on each of the plurality of frame side VDP control target decoration substrates that are controlled by the sound source built-in VDP 4160 a. When the light emission data defining the light emission mode is input from the peripheral control MPU 4150a, a predetermined screen (from the liquid crystal and sound control ROM 4160b (based on the input screen data) according to a predetermined door frame side generation rule ( In this embodiment, dummy data for drawing red (R): 50%, green (G): 50%, blue (B): 50%) is extracted. Predicate data is generated and door frame side drawing data is generated in the door frame side drawing data region VRGN2a of the door frame side display region VRGN2 provided on the built-in VRAM, and the liquid crystal is generated based on the input light emission data. Among the decorative boards of the door frame 5 from the sound control ROM 4160b, a plurality of LEDs (decorative LEDs) provided on each of the plurality of frame side VDP control target decorative boards that are controlled by the built-in sound source VDP 4160a The door frame side light emitting mode setting image data for setting the light emitting mode is extracted, and the door frame side associated information region of the door frame side display region VRGN2 provided on the built-in VRAM with the below-described illumination information as drawing data Generated in VRGN2b. As a result, electric power is supplied to the drawing data on the door frame side of a predetermined screen (in this embodiment, a gray screen having red (R): 50%, green (G): 50%, blue (B): 50%). The drawing data generated in the door frame side display area VRGN2 is output from the channel CH2, assuming that the decoration information is attached according to a predetermined door frame side generation rule. The drawing data generated in the door frame side display area VRGN2 is referred to as “frame side image object”. Note that the “predetermined door frame side generation rule” will be described later.

  When the drawing data output from the channel CH1 is output from the peripheral control board 4140 to the liquid crystal output board 3420, on the liquid crystal output board 3420, game board side drawing data for the game board side effect display unit 1900, and a light guide plate described later. Information and electrical information. Thereby, the liquid crystal output board 3420 outputs the game board side rendering data to the game board side effect display unit 1900, thereby displaying the screen on the game board side effect display unit 1900, and the game board side based on the light guide plate information. By selecting one of the various light guide plates of the effect display unit 1900, the selected light guide plate emits light, and among the decorative boards of the game board 4, the sound source built-in VDP 4160a directly controls based on the electrical information. The plurality of LEDs (decorative LEDs) emit light by outputting signals to the plurality of LEDs (decorative LEDs) provided on the plurality of game board side VDP control target decorative boards that are to be controlled.

  When the drawing data output from the channel CH2 is output from the peripheral control board 4140 to the frame peripheral relay terminal board 868, the peripheral door relay terminal board 882, and the frame decoration drive amplifier board 194, in the frame decoration drive amplifier board 194, Door frame side drawing data of a predetermined screen (in this embodiment, a gray screen having red (R): 50%, green (G): 50%, blue (B): 50%), and power to be described later. It is separated into decoration information. As a result, the frame decoration drive amplifier board 194 includes a plurality of frame side VDP control target decoration boards that are controlled by the sound source built-in VDP 4160a among the decoration boards of the door frame 5 based on the electrical decoration information. While a plurality of LEDs (decorative LEDs) emit light by outputting signals to the plurality of LEDs (decorative LEDs) provided in each, a predetermined screen (in this embodiment, red (R): 50%, The door frame side drawing data (green (G): 50%, blue (B): 50% gray screen) are not output to other electronic components or other substrates. In other words, the drawing data output from the channel CH2 has a predetermined screen (in this embodiment, red (R): 50%) in order to cut out (take out) the illumination information in the frame decoration drive amplifier board 194. Illumination information is attached to the door frame side drawing data of green (G): 50%, blue (B): 50% gray screen).

  As described above, since the drawing data output from the channel CH1 is output from the peripheral control board 4140 to the game board side effect display unit 1900 via the liquid crystal output board 3420 as described above, the peripheral control board 4140, the liquid crystal Since the output board 3420 and the game board side effect display unit 1900 are respectively attached to the game board 4, the length of wiring required for the route from the channel CH1 to the game board side effect display unit 1900 is short. In contrast, the drawing data output from the channel CH2 is output from the peripheral control board 4140 to the frame decoration drive amplifier board 194 via the frame peripheral relay terminal board 868 and the peripheral door relay terminal board 882 as described above. Therefore, the length of the wiring required for the route to the peripheral control board 4140, the frame peripheral relay terminal board 868, the peripheral door relay terminal board 882, and the frame decoration drive amplifier board 194 is extremely longer than that of the channel CH1. As a result, the transmission path in the channel CH2 is extremely longer than the transmission path in the channel CH1, so that it is extremely susceptible to noise. For this reason, for the channel CH2 in which the length of the wiring for sending drawing data is extremely longer than that of the channel CH1, the transmitter IC 4160d uses “V-” of Zain Electronics Co., Ltd., which is a kind of clockless transmission method. By adopting a differential communication called “by-One (registered trademark)”, the system is less susceptible to noise. The “clockless transmission method” is a clock data recovery (CDR: Clock Data Recovery) provided in a receiver when a signal in which a clock is superimposed on data is transmitted from the transmitter to the receiver between the transmitter and the receiver. This is a method of separating data and clocks by function.

  The channel CH1 uses a serial differential interface called LVDS (Low Voltage Differential Signaling). Briefly explaining the differential interface by the serial system called LVDS, the channel CH1 can output a clock signal differentiated into a plus signal and a minus signal from a TCLK plus terminal and a TCLK minus terminal. The plus terminal and the TCLK minus terminal are electrically connected to a differential signal pair cable for clock signal in which one wiring is in a positive phase and the other wiring is in a reverse phase, and a clock signal is supplied to the liquid crystal output board 3420. To transmit. The channel CH1 can output five signals, that is, a red video signal, a green video signal, a blue video signal, a horizontal synchronization signal, and a vertical synchronization signal, as four data streams (TA, TB, TC, and TD). .

  Specifically, the channel CH1 can output the first data stream TA signal constituting the four data streams differentiated into the plus signal and the minus signal from the TA plus terminal and the TA minus terminal. The TA plus terminal and the TA minus terminal are electrically connected to the TA signal differential one-pair cable with one wiring having a positive phase and the other wiring having a reverse phase, respectively, and connected to the liquid crystal output board 3420. The first data stream TA signal constituting the four data streams is transmitted. Further, the channel CH1 can output the second data stream TB signal constituting the four data streams differentiated into the plus signal and the minus signal from the TB plus terminal and the TB minus terminal. A plus terminal and a TB minus terminal are electrically connected to a differential signal pair cable for TB signal in which one wiring has a positive phase and the other wiring has a reverse phase, and four data are supplied to the liquid crystal output board 3420. A second data stream TB signal constituting the stream is transmitted.

  Further, the channel CH1 can output the third data stream TC signal constituting the four data streams differentiated into the plus signal and the minus signal from the TC plus terminal and the TC minus terminal. A plus terminal and a TC minus terminal are electrically connected to a differential pair cable for TC signal in which one wiring has a normal phase and the other wiring has a reverse phase, respectively, and four data are supplied to the liquid crystal output board 3420. A third data stream TC signal constituting the stream is transmitted. Further, the channel CH1 can output the fourth data stream TD signal constituting the four data streams differentiated into the plus signal and the minus signal from the TD plus terminal and the TD minus terminal. The plus terminal and the TD minus terminal are electrically connected to a differential pair cable for TD signal in which one wiring is in a normal phase and the other wiring is in a reverse phase, and four data are supplied to the liquid crystal output board 3420. A fourth data stream TD signal constituting the stream is transmitted.

  In this way, the drawing data output from the channel CH1 includes a clock signal differential 1 pair cable, a TA signal differential 1 pair cable, a TB signal differential 1 pair cable, a TC signal differential 1 pair cable, And transmitted to the liquid crystal output substrate 3420 via the differential pair cable for TD signal. 1 pair cable for clock signal, 1 pair cable for TA signal, 1 pair cable for TB signal, 1 pair cable for TC signal, and 1 pair cable for TD signal are 2 The wiring of the book is not a parallel line simply provided in parallel, but a twisted pair cable. This twisted pair cable is a cable in which two wires are twisted together, and is also called a twisted pair wire (twisted wire).

  Then, as shown in FIG. 20, the drawing data output from the channel CH1 is transmitted through the LVDS method in the RGB conversion circuit 3420f of the liquid crystal output substrate 3420 (that is, the clock signal, TA signal, TB signal, TC). Signal and TD signal). This parallel signal is composed of three video signals, a red video signal, a green video signal, and a blue video signal, and three synchronization signals, a horizontal synchronization signal, a vertical synchronization signal, and a clock signal.

  The RGB conversion circuit 3420f converts the drawing data output from the channel CH1 into a parallel signal (that is, a red video signal that is drawing data output from the channel CH1 of the sound source built-in VDP 4160a) based on a signal transmitted by the LVDS method. 3 video signals of green video signal and blue video signal and 3 sync signals of horizontal sync signal, vertical sync signal, and clock signal) and output to the game board side signal separation control circuit 3420g. The game board side signal separation control circuit 3420g is a red video signal and a green video signal, which are game board side drawing data for the game board side effect display unit 1900 (liquid crystal panel 5000e) from the parallel signal converted by the RGB conversion circuit 3420f. , And three video signals such as a blue video signal, three synchronization signals such as a horizontal synchronization signal, a vertical synchronization signal, and a clock signal, and one light guide plate among a plurality of light guide plates provided in the game board side effect display unit 1900. The light guide plate information to be selected and a plurality of LEDs (decorative elements) provided on each of the plurality of game board side VDP control target decoration boards to be controlled by the sound source built-in VDP 4160a among the decoration boards of the game board 4 LED) and the illumination information.

  The game board side signal separation control circuit 3420g is a game board side rendering display data for the game board side effect display unit 1900 (liquid crystal panel 5000e) separated from the parallel signal converted by the RGB conversion circuit 3420f. A game board-side effect display unit for three video signals, a video signal and a blue video signal, and three synchronization signals, a horizontal synchronization signal, a vertical synchronization signal, and a clock signal, via a game board-side liquid crystal drive circuit 3420h. By outputting to 1900 (liquid crystal panel 5000e), the game board side effect display unit 1900 (liquid crystal panel 5000e) displays a screen. The game board-side signal separation control circuit 3420g separates from the parallel signals converted by the RGB conversion circuit 3420f, and various light guide plates of the game board side effect display unit 1900 via the various light guide plate control circuits 3420k based on the light guide plate information. The selected light guide plate emits surface light by selecting one of the various light guide plates by outputting to the game board side, and via the game board side VDP control target decoration LED control circuit 3420i. Of each decoration board of the game board 4, a signal is output to a plurality of LEDs (decoration LEDs) provided on each of the plurality of game board side VDP control target decoration boards that are controlled by the built-in sound source VDP 4160a. By doing so, a plurality of LEDs (decorative LEDs) emit light.

  Returning to FIG. 19, the channel CH2 uses a parallel interface for the channel CH1. The drawing data output from the channel CH2 is composed of three video signals, a red video signal, a green video signal, and a blue video signal, and three synchronization signals, a horizontal synchronization signal, a vertical synchronization signal, and a clock signal. Serialized by the transmitter IC 4160d and output (transmitted) to a peripheral control output circuit (not shown), a frame peripheral relay terminal plate 868, a peripheral door relay terminal plate 882, and a frame decoration drive amplifier board 194. The various serialized signals are restored to parallel signals in the frame decoration drive amplifier board 194.

  As described above, the peripheral control MPU 4150a displays screen data for one screen (one frame) to be drawn (displayed) on the game board side effect display unit 1900, and a predetermined screen (in this embodiment, red (R): 50%, green (G): 50%, blue (B): gray screen having 50%) (screen) for one screen (one frame) is output to the built-in sound source VDP 4160a. . “Screen data for one screen (for one frame)” refers to drawing data for one screen (for one frame) to be drawn (displayed) on the game board side effect display unit 1900 and a predetermined screen (this embodiment). Then, drawing data for one screen (one frame) for drawing (displaying) red (R): 50%, green (G): 50%, blue (B): 50%, Is data for generating on the built-in VRAM.

  In this embodiment, the game board side effect display unit 1900 (liquid crystal panel 5000e) adopts 12 inches having an image size of 800 × 600 dots, and has a predetermined screen (in this embodiment, red (R): 50%). , Green (G): 50%, blue (B): gray screen having 50%) employs an image size of 480 × 272 dots. In this way, the image size of the game board side effect display unit 1900 (liquid crystal panel 5000e) is determined according to a predetermined screen (in this embodiment, red (R): 50%, green (G): 50%, blue (B ): A gray screen having 50%). For this reason, the image size is the same as that of a predetermined screen (in this embodiment, a gray screen having red (R): 50%, green (G): 50%, blue (B): 50%). Actually predetermined screen in a 4.3 inch liquid crystal display device having an image size (in this embodiment, red (R): 50%, green (G): 50%, blue (B): 50%) When displaying a gray screen), the operating frequency of the game board side effect display unit 1900 (liquid crystal panel 5000e) is higher than the operating frequency of the 4.3 inch liquid crystal display device.

  The sound source built-in VDP 4160a outputs (transmits) drawing data for one screen (one frame) from the channel CH1 to the liquid crystal output board 3420, and outputs image data for one screen (one frame) from the channel CH2. When output (transmitted) to the peripheral control output circuit (not shown), the frame peripheral relay terminal plate 868, the peripheral door relay terminal plate 882, and the frame decoration drive amplifier board 194, the screen data from the peripheral control MPU 4150a can be received. Is output to the peripheral control MPU 4150a. In this embodiment, a game board side effect display unit 1900 and a predetermined screen (in this embodiment, red (R): 50%, green (G): 50%, blue (B): 50% gray Since the frame frequency (number of screen updates per second), which is the frequency at which drawing data for one screen (one frame) is updated, is set to approximately 30 fps per second, a V blank signal is output. The interval is about 33.3 ms (= 1000 ms ÷ 30 fps). The peripheral control MPU 4150a executes a peripheral control unit V blank signal interrupt process to be described later when this V blank signal is input. Here, the interval at which the V blank signal is output depends on the liquid crystal size of the game board side effect display unit 1900 and a predetermined screen (in this embodiment, red (R): 50%, green (G): 50%, Blue (B): a gray screen having 50%) slightly changes depending on the image size. In addition, even in the manufacturing lot of the peripheral control board 4140 on which the peripheral control MPU 4150a and the built-in sound source VDP 4160a are mounted, the interval at which the V blank signal is output may change somewhat.

  The sound source built-in VDP 4160a employs a frame buffer method. This “frame buffer system” is a game board side effect display unit 1900 and a predetermined screen (in this embodiment, red (R): 50%, green (G): 50%, blue (B): 50%. The drawing data for one screen (one frame) with the gray screen having the image is held in the frame buffer (built-in VRAM), and the drawing for one screen (one frame) held in this frame buffer (built-in VRAM) This is a method for outputting data.

  When the sound command data described above is input from the peripheral control MPU 4150a based on a command from the main control board 4100, the sound source built-in VDP 4160a receives music stored in the liquid crystal and sound control ROM 4160b as shown in FIG. By extracting sound data such as sound and sound effects and controlling the built-in sound source, sound data such as music and sound effects are incorporated into the track according to the track number specified in the sound command data and used according to the output channel number The output channel is set and the music accommodated in the speaker box 820 provided in the main body frame 3 and the speaker, the sound effect, etc. flowing from the speaker 130 provided in the door frame 5 are serialized and output as audio data to the audio data transmission IC 4160c. .

  Note that the sound command data also includes a sub-volume value for adjusting the volume of the track in which the sound data is incorporated, and a plurality of tracks in the built-in sound source of the sound source built-in VDP 4160a include effect sounds such as music and sound effects. In addition to the sound data and the sub-volume value for adjusting the sound volume, the sound data of the notification sound and the sound volume for notifying the clerk of the hall of the occurrence of the malfunction of the pachinko gaming machine 1 and the illegal act on the pachinko gaming machine 1 Incorporates a sub-volume value that adjusts. Specifically, for the production sound, the substrate volume adjusted by rotating the knob portion of the volume adjustment volume 4140a described above is set as the sub volume value, and for the notification sound, the volume adjustment is performed. The maximum volume is set as the sub-volume value without depending on the volume adjustment based on the turning operation of the knob portion of the volume 4140a. The sub-volume value of the effect sound can be adjusted by shifting to a setting mode to be described later by operating the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400.

  The sound command data also includes a master volume value for adjusting the volume of the output channel, and a plurality of output channels in the built-in sound source of the built-in sound source VDP 4160a include a plurality of sound channels in the built-in sound source of the sound source built-in VDP 4160a. Of the tracks, the sound data of the production sound built into the track to be used is combined with the sub-volume value that adjusts the volume of the production sound built into the track to be used. Actually, it amplifies the master volume value that is the volume that flows from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, and serializes the amplified effect sound as audio data. The data is output to the audio data transmission IC 4160c.

  In the present embodiment, the master volume value is set to a constant value excluding the master volume value for power suppression, and when the volume of the combined effect sound is the maximum volume, the master volume value is amplified to the master volume value. The sound volume flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 is set to an allowable maximum sound volume. Specifically, for the production sound, among the multiple tracks, the sound data of the production sound incorporated in the track to be used and the sub-volume value that adjusts the volume of the production sound incorporated in the track to be used The volume of the set sound adjustment volume 4140a is synthesized with the substrate volume adjusted by rotating the knob, and the volume of the synthesized performance sound is actually applied to the speaker box 820 provided in the main body frame 3. It amplifies up to the master volume value that is the volume that flows from the speaker to be accommodated and the speaker 130 provided on the door frame 5, serializes the amplified effect sound, and outputs it as audio data to the audio data transmission IC 4160c. Indicates the sound data of the notification sound incorporated in the track used and the sound of the notification sound incorporated in the track used. Is combined with the maximum volume without depending on the volume adjustment based on the turning operation of the knob portion of the volume adjustment volume 4140a set as the sub volume value for adjusting the volume, and the volume of the synthesized notification sound is actually Amplification is performed up to a master volume value which is a volume flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, and the amplified notification sound is serialized to be audio data as audio data. The data is output to the transmission IC 4160c.

  Here, when the production sound is flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, the occurrence of the malfunction of the pachinko gaming machine 1 or the pachinko gaming machine 1 To briefly explain the control of playing a notification sound in order to notify the store clerk etc. of fraudulent behavior, the sub-volume value of the track in which the production sound is incorporated is forcibly set to mute, and this production sound is incorporated. The track sound data, the sub-volume value set for the mute, the sound data of the track in which the notification sound is incorporated, and the sub-volume value where the notification sound volume is set to the maximum volume are synthesized. The volume of the produced effect sound and the volume of the notification sound are actually set to the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker provided in the door frame 5. Amplified to a master volume value as the volume flowing from 130, and outputs the amplified effect sound and alarm sound as an audio data to the audio data transmission IC4160c Serialize.

  In other words, the sound that flows from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 is only the notification sound of the maximum volume. At this time, since the production sound is muted, the production sound does not flow from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, but the production sound is used for the sound generation described above. Progressing according to schedule data. In the present embodiment, the notification sound flows from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 for a predetermined period (for example, 90 seconds). When the period of time elapses, the volume of the effect sound that has progressed in accordance with the sound generation schedule data that has been forcibly set to mute so far has been adjusted by rotating the knob portion of the volume adjustment volume 4140a. It is set again as the volume value (at this time, when the adjustment is made by moving to the setting mode by operating the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400, the adjusted effect sound is sub- Set to the volume value), the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker provided in the door frame 5. So that the flow from mosquitoes 130.

  Thus, when the production sound is flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, the occurrence of a malfunction of the pachinko gaming machine 1 or the pachinko gaming machine 1 When a notification sound flows in order to notify a store clerk or the like of a fraudulent act to the hall, the volume of the effect sound is muted and the notification sound is provided in the speaker and door frame 5 housed in the speaker box 820 provided in the main body frame 3. Although the silenced effect sound flows from the speaker 130 and proceeds in accordance with the sound generation schedule data, the speaker is accommodated in the speaker box 820 provided in the main body frame 3 after a predetermined period of time. When the speaker 130 provided on the door frame 5 stops flowing, the production sound does not start to flow again from where the notification sound starts to flow. So that the start flowing again from where the notification sound is beginning to flow to proceed according to the schedule data for generating sound until after the lapse of a predetermined period of time.

[7-4-2b. Liquid crystal and sound control ROM]
As shown in FIG. 19, the liquid crystal and sound control ROM 4160b includes the game board side character data to be drawn in the display area of the game board side effect display unit 1900, and the above-described predetermined screen (in this embodiment, red ( R): 50%, green (G): 50%, blue (B): gray screen having 50%)) and among the decorative boards of the game board 4, the sound source built-in VDP 4160a is Game board side light emission mode setting image data for setting a light emission mode of a plurality of LEDs (decorative LEDs) provided on each of the plurality of game board side VDP control target decoration boards that are controlled directly; Among each decorative board of the door frame 5, a plurality of LEDs (on each of the plurality of frame side VDP control target decorative boards that are controlled by the built-in sound source VDP 4160a) A door frame-side light emission mode setting image data for setting a light emitting mode for LED) decorative, music, sound effects, the notification sound, and a variety of sound data, such announcement sound, but are stored in advance.

[7-4-2c. Audio data transmission IC]
When the audio data transmission IC 4160c receives serialized audio data from the sound source built-in VDP 4160a, the audio data transmission IC 4160c converts the right audio data as a positive signal and a negative signal as differential serial data, and outputs a peripheral control output circuit and frame peripheral relay not shown A peripheral control output circuit (not shown) is transmitted to the frame decoration drive amplifier board 194 via the terminal board 868 and the peripheral door relay terminal board 882 and as differential serial data with the left audio data as a positive signal and a negative signal. Then, the frame is transmitted to the frame decoration drive amplifier board 194 via the frame peripheral relay terminal plate 868 and the peripheral door relay terminal plate 882. Thereby, music, sound effects, etc. adapted to various effects are reproduced in stereo from the speakers housed in the speaker box 820 provided in the main body frame 3 and the speakers 130 provided in the door frame 5.

  Note that the audio data transmission IC 4160c outputs audio data between the boards extending from the peripheral control board 4140 to the frame decoration drive amplifier board 194 as left and right difference type serial data, for example, a positive signal of left audio data, Even when the negative signal is affected by noise, the frame decoration drive amplifier board 194 combines the noise component riding on the plus signal and the noise component riding on the minus signal into one left audio data. Since noise components are canceled by canceling each other, noise countermeasures can be taken.

[7-4-2d. Transmitter IC]
As shown in FIG. 19, the transmitter IC 4160d receives drawing data output from the channel CH2 of the sound source built-in VDP 4160a. As described above, the channel CH2 uses a parallel interface. The drawing data is composed of three video signals, a red video signal, a green video signal, and a blue video signal, and three synchronization signals, a horizontal synchronization signal, a vertical synchronization signal, and a clock signal. Each of the green video signal and the blue video signal is composed of 8 bits and a total of 24 bits. In this embodiment, since the red video signal, the green video signal, and the blue video signal that can be input to the transmitter IC 4160d are 10 bits each, that is, 30 bits in total, all 8 bits of each video signal are input to the transmitter IC 4160d. ing. Since each of the red video signal, the green video signal, and the blue video signal is 8 bits, the extra 2 bits that can be input to the transmitter IC 4160d are invalidated (specifically, each video signal of the transmitter IC 4160d is invalidated). The lower 2 bits of the input terminals are grounded to the ground (GND), respectively).

  Three video signals such as a red video signal, a green video signal, and a blue video signal, and three synchronization signals such as a horizontal synchronization signal, a vertical synchronization signal, and a clock signal, which are drawing data output from the channel CH2 of the sound source built-in VDP 4160a. Are input to the transmitter IC 4160d, the transmitter IC 4160d has three video signals, a red video signal, a green video signal, and a blue video signal, and three synchronization signals, a horizontal synchronization signal, a vertical synchronization signal, and a clock signal. Are serialized into a differential serial signal (serial data) called “V-by-One (registered trademark)” of THine Electronics Co., Ltd., which is a type of clockless transmission system (in other words, red video signal, green Video signal and blue video signal A parallel signal composed of a video signal and three synchronization signals, a horizontal synchronization signal, a vertical synchronization signal, and a clock signal, is multiplexed and serialized into a differential serial signal (serial data). These differential signals are transmitted from the peripheral control board 4140 to the frame peripheral relay terminal board 868, the peripheral door relay terminal board 882, and the frame using only the differential one-pair cable with the other wiring in the normal phase and the other wiring in the reverse phase. Output (send) to the decoration drive amplifier 194.

  As described above, the drawing data output from the channel CH1 of the sound source built-in VDP 4160a is output (transmitted) from the peripheral control board 4140 to the liquid crystal output board 3420, and therefore transmitted from the channel CH1 to the game board side effect display unit 1900. Although the length of the wiring required for the route (first transmission route) is short, the drawing data output from the channel CH2 of the built-in sound source VDP 4160a is transmitted from the peripheral control board 4140 to the frame peripheral relay terminal board 868 and the peripheral door relay terminal board 882. Is output (transmitted) to the frame decoration drive amplifier board 194 via the transmission line, the length of the wiring required for the transmission path (second transmission path) from the channel CH2 to the frame decoration drive amplifier board 194 is required for the first transmission path. By being extremely longer than the length of the wiring, it becomes extremely susceptible to noise.

  Specifically, since the door frame 5 is pivotally supported so as to be openable and closable with respect to the main body frame 3 shown in FIG. 1, it is opposite to the lock device 1000 shown in FIG. 5 along the open side of the main body frame 3. The main frame 3 side such as the frame decoration drive amplifier board 194 accommodated in the dish unit 300 provided in the door frame 5 from the peripheral control board 4140 provided in the game board 4 mounted on the main frame 3, for example, It is necessary to pass various wirings that electrically connect the various substrates provided in the circuit board and the various substrates provided on the door frame 5 side. However, on the closed side of the main body frame 3, as shown in FIG. 3, in addition to the prize ball device 740, the game balls paid out by the prize ball device 740 are displayed on the plate unit 300 shown in FIG. A full tank branching unit 770 is provided which can be guided to the upper plate 301 and can branch the guided game ball to the lower plate 302 side when the upper plate 301 is filled with game balls. A substrate unit 800 shown in FIG. 5 is arranged below the main body frame 3 in which the power supply substrate 851 and the like shown in FIG. 6 to which power is supplied from the pachinko island facility are grouped. As described above, various wirings for electrically connecting the various substrates provided on the main body frame 3 side and the various substrates provided on the door frame 5 side are in the vicinity of the prize ball device 740, the full tank branching unit 770, the power supply substrate 851, and the like. In addition to noise due to driving of the payout motor 744 provided in the prize ball device 740, noise due to electrostatic discharge by the game ball and the pachinko island equipment where the pachinko gaming machine 1 is installed are supplied. The environment is subject to noise that has entered the power line.

  For this reason, for the channel CH2 in which the length of the wiring for sending drawing data is extremely longer than that of the channel CH1, the transmitter IC 4160d provided in the peripheral control board 4140 is a type of clockless transmission method, THine Electronics. By adopting a differential system communication called “V-by-One (registered trademark)” of a corporation, it is a mechanism that is hardly affected by noise. In the present embodiment, wiring for electrically connecting between the transmitter IC 4160d provided on the peripheral control board 4140 and the receiver IC 194f provided on the frame decoration driving board 194 of the door frame 5, that is, between the transmitter and the receiver. As described above, a differential one-pair cable is used, but this differential one-pair cable is not a parallel line in which two wires are simply provided in parallel, but a twisted pair cable. This twisted pair cable is a cable in which two wires are twisted together, and is also called a twisted pair wire (twisted wire). A stranded wire is composed of a wire that transmits a positive-phase signal and a wire that transmits a reverse-phase signal, so that when noise enters the stranded wire, the wire transmits a positive-phase signal. As a result, noise enters the wirings that transmit signals of opposite phases. Then, the noise that has entered the positive phase signal and the noise that has entered the negative phase signal cancel each other out, so that the noise is removed by the receiver IC 194f, and the red video signal, the green video signal, and A parallel signal composed of three video signals called a blue video signal and three synchronization signals called a horizontal synchronizing signal, a vertical synchronizing signal, and a clock signal can be restored. It should be noted that the connection between the transmitter IC 4160d provided on the peripheral control board 4140 and the receiver IC 194f provided on the frame decoration drive board 194 of the door frame 5, that is, the wiring for electrically connecting the transmitter and the receiver In order to further suppress the influence of noise, for example, in addition to the above-described normal-phase wiring and reverse-phase wiring, a total of three wirings of ground (GND) wiring may be used as a twisted wire. It is possible to have a structure in which a twisted pair wire (also referred to as a twisted pair shielded cable) is formed by twisting a normal phase wire and a reverse phase wire and covering the twisted wire with a shield coating. it can. This shield coating is grounded to the ground (GND) of the peripheral control board 4140 and the ground (GND) of the frame decoration drive board 194, respectively, and becomes the same ground (GND).

  Here, the case where a parallel line is adopted as a differential one-pair cable for electrically connecting a transmitter and a receiver will be briefly described. One type of clockless transmission method is used in the transmitter IC 4160d provided in the peripheral control board 4140 for the channel CH2 of the sound source built-in VDP 4160a in which the length of the wiring for sending drawing data is extremely longer than the channel CH1 of the sound source built-in VDP 4160a. As a mechanism that is difficult to be affected by noise by adopting differential communication called “V-by-One (registered trademark)” of Zain Electronics Co., Ltd. If the serial data on the parallel lines is affected by noise due to electrostatic discharge, noise entering the power supply line supplied from the pachinko island facility where the pachinko machine 1 is installed, etc., the frame decoration drive amplifier board of the door frame 5 Receiver IC1 for 194 Since the noise is not canceled (removed) when received by 4f, the serial data is received by the receiver IC 194f in an affected state, and the drawing data output from the channel CH2 of the sound source built-in VDP 4160a is normal. There is a problem that the receiver IC 194f receives the signal as a distorted one different from the one.

  Therefore, in this embodiment, in the transmitter IC 4160d provided in the peripheral control board 4140 for the channel CH2 of the sound source built-in VDP 4160a in which the length of the wiring for sending drawing data is extremely longer than the channel CH1 of the sound source built-in VDP 4160a. In addition to adopting a differential communication system called “V-by-One (registered trademark)” of Zain Electronics Co., Ltd., which is a kind of clockless transmission system, a mechanism that is less susceptible to noise and such hardware In addition to the configuration described above, a twisted pair cable that can cancel (remove) the noise on the receiving side even if the serial data in the differential method is affected by noise that has entered the wiring. Between it adopted as differential pair cable for electrically connecting. As a result, even if serial data is affected by the twisted pair cable due to noise caused by electrostatic discharge of the game ball, noise entering the power supply line supplied from the pachinko island facility where the pachinko gaming machine 1 is installed, etc., the door Since the noise is canceled (removed) when receiving by the receiver IC 194f included in the frame decoration drive board 194 of the frame 5, the drawing data output from the channel CH2 of the sound source built-in VDP 4160a is the door frame 5 Can be reliably received by the receiver IC 194f included in the frame decoration drive amplifier board 194.

  In this embodiment, the frame peripheral relay terminal is connected between the transmitter IC 4160d provided on the peripheral control board 4140 and the receiver IC 194f provided on the frame decoration drive board 194 of the door frame 5, that is, between the transmitter and the receiver. A plate 868 and a peripheral door relay terminal plate 882 are interposed. This is because the main body frame 3 and the door frame 5 are not integrally configured, but a structure in which the door frame 5 is attached to the main body frame 3 after being assembled separately is adopted. After connecting the door frame 5 to the door frame 5, electrically connect various wirings such as harnesses and twisted pair cables from various boards provided on the door frame 5 side to the peripheral door relay terminal plate 882 provided on the main body frame 3 side. Thus, various substrates provided on the main body frame 3 side and various substrates provided on the door frame 5 side can be electrically connected. With such a configuration, after the door frame 5 is opened from the main body frame 3 and various wirings are removed, the main body frame 3 and the door frame 5 can be maintained by removing the door frame 5 from the main body frame 3. If the problem that occurred in the door frame 5 cannot be resolved, another door frame 5 ′ is attached to the main body frame 3 instead of the defective door frame 5, and the door frame 5 By electrically connecting various wirings from various substrates provided on the 'side to the peripheral door relay terminal plate 882 provided on the main body frame 3 side, various substrates provided on the main body frame 3 side and various types provided on the door frame 5' side The substrate can be electrically connected.

  In the present embodiment, as described above, in the transmitter IC 4160d provided in the peripheral control board 4140, a differential method called “V-by-One (registered trademark)” of Zain Electronics Co., Ltd., which is a kind of clockless transmission method, is used. In addition to this hardware configuration, even if the serial data by the differential method is affected by noise that has intruded into the wiring, the noise on the receiving side is adopted. A twisted pair cable capable of canceling (removing) is adopted as a differential one-pair cable for electrically connecting the transmitter and the receiver. Specifically, between the peripheral control board 4140 and the frame peripheral relay terminal board 868, between the frame peripheral relay terminal board 868 and the peripheral door relay terminal board 882, and between the peripheral door relay terminal board 882 and the frame decoration drive. The amplifier board 194 and the amplifier board 194 are electrically connected by a twisted pair cable, while the power supply wiring and other wiring for transmitting various signals are electrically connected by a harness. As a result, the frame peripheral relay terminal plate 868 and the peripheral door relay terminal plate 882 have the power transmission wiring pattern and the like in addition to the video transmission wiring pattern for transmitting the differential serial data transmitted by the transmitter IC 4160d. Various signal wiring patterns for transmitting other various signals are mixed. For this reason, the above-described video transmission wiring patterns are formed on the frame peripheral relay terminal plate 868 and the peripheral door relay terminal plate 882 by being separated from the power supply wiring pattern and various signal wiring patterns by a predetermined dimension. Since the route from the transmitter to the receiver spans a plurality of relay terminal plates such as the frame peripheral relay terminal plate 868 and the peripheral door relay terminal plate 882, the video transmission formed on the plurality of relay terminal plates is used. Between the input and output of the wiring pattern, there arises a problem that a part of the signal for transmitting the differential serial data transmitted by the transmitter IC 4160d is reflected and becomes noise, or the output level of the signal is lowered. Therefore, in this embodiment, impedance matching is performed on the video transmission wiring patterns formed on the plurality of relay terminal boards.

  In the present embodiment, as described above, between the peripheral control board 4140 and the frame peripheral relay terminal board 868, between the frame peripheral relay terminal board 868 and the peripheral door relay terminal board 882, and the peripheral door relay. The board of the terminal board 882 and the frame decoration drive amplifier board 194 are electrically connected by a twisted pair cable, whereas the wiring for transmitting power supply wiring and other various signals is electrically connected by a harness. Although one of the twisted pair cables is red and the other is gray, the wiring that supplies power is red and the other wires are gray. Yes. Note that the power supply wiring may be yellow instead of red.

  In this embodiment, a serial signal (serial data) based on a differential method called “V-by-One (registered trademark)” of Zain Electronics Co., Ltd., which is a kind of clockless transmission method, is transmitted from the transmitter IC 4160d in the peripheral control board 4140. When transmitted as a plus signal and a minus signal, they are input to a common mode choke coil (not shown) provided on the frame decoration drive amplifier board 194 via the frame peripheral relay terminal plate 868 and the peripheral door relay terminal plate 882, respectively. Noise can be separated from the plus signal and the minus signal by the common mode choke coil. The plus signal and minus signal from which the noise is separated are input to the RXIN + terminal and the RXIN- terminal of the receiver IC 194f, respectively. A resistor (not shown) is electrically connected between the RXIN + terminal and the RXIN− terminal. This resistor (not shown) is a termination resistor (terminator), which prevents the plus signal and the minus signal from reflecting at the RXIN + terminal and the RXIN− terminal, respectively, and prevents the serial signal from being disturbed.

  Further, as described above, between the peripheral control board 4140 and the frame peripheral relay terminal board 868, between the frame peripheral relay terminal board 868 and the peripheral door relay terminal board 882, and between the peripheral door relay terminal board 882 and the frame. Between the board | substrate with the decoration drive amplifier board | substrate 194, each is electrically connected by the twisted pair cable. Of these twisted pair cables, all twisted pair cables, one or more twisted pair cables (not all twisted pair cables, but one or more (predetermined number of twisted pair cables)), or one of the twisted pair cables of the ring core Noise countermeasures can be taken by inserting through holes. The ring core can exhibit an effect for removing high-frequency noise in the several hundred kHz to several hundred MHz band, and can be applied with a thin coating for preventing scattering and reducing damage.

  Further, by providing the frame decoration drive amplifier board 194 with the normal phase side ferrite beads and the reverse phase side ferrite beads, it is possible to further take measures against noise. In this case, the serial signal (serial data) by the differential method “V-by-One (registered trademark)” of THINE ELECTRONICS CO., LTD., Which is a kind of clockless transmission method, from the transmitter IC 4160d in the peripheral control board 4140 is a plus signal and a minus signal. When transmitted as a signal, via a common mode choke coil (not shown) provided on the frame decoration drive amplifier board 194, the plus signal is received via the positive phase side ferrite beads provided immediately before the RXIN + terminal of the receiver IC 194f. (That is, the terminal of a common mode choke coil (not shown) that outputs a positive signal is electrically connected to one end of a positive phase side ferrite bead, and the other end of the positive phase side ferrite bead is configured. And receiver IC The negative signal is input to the RXIN− terminal via the negative phase side ferrite bead provided immediately before the RXIN− terminal of the receiver IC 194f. (That is, the terminal of the common mode choke coil (not shown) that outputs the negative signal and one end of the negative-phase side ferrite bead are electrically connected, and the other end of the negative-phase side ferrite bead and the receiver IC 194f The circuit is configured so that the RXIN− terminal is electrically connected). The positive-phase side ferrite bead and the negative-phase side ferrite bead reflect the noise that the inductor (coil) component of the ferrite bead intrudes into the stranded wire and prevent the ferrite bead component from entering the stranded wire. Has the property that it can be converted into heat and removed. Due to the characteristics of the ferrite beads, it is possible to prepare a beautiful waveform by suppressing the disturbance of the waveform due to noise superposition on the serial signal transmitted through the stranded wire.

  The above-described differential signal plus signal and minus signal of the serial signal (serial data) are not directly connected to the common mode choke coil (not shown) but directly above the RXIN + terminal of the receiver IC 194f. The circuit is configured to be input to the RXIN + terminal via the ferrite bead, and the negative signal is input to the RXIN− terminal via the above-described negative phase side ferrite bead provided immediately before the RXIN− terminal of the receiver IC 194f. A circuit configuration can also be configured as described above.

[7-4-2e. Forced switching circuit, differential circuit]
The signal output from the transmitter IC 4160d is output (transmitted) to the forced switching circuit 4160f, a peripheral control output circuit (not shown), the frame peripheral relay terminal plate 868, the peripheral door relay terminal plate 882, and the frame decoration drive amplifier board 194. It has become. In addition to the signal output from the transmitter IC 4160d, the forced switching circuit 4160f includes a serial signal output from the LOCKN signal output request serial I / O port built in the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140. The LOCKN signal output request data, which is data, is differentiated into a plus signal and a minus signal and inputted in the differentiation circuit 4160e. The differential circuit 4160e serializes the LOCKN signal output request data into a differential serial signal (serial data). This LOCKN signal output request data is a demonstration by the game board side effect display unit 1900 during the period when the start-up screen at the time of power-on of the pachinko gaming machine 1 is displayed on the game board side effect display unit 1900 or in the waiting state of the customer. During the period when the transmitter IC 4160d provided on the peripheral control board 4140 and the receiver IC 194f provided on the frame decoration driving board 194 of the door frame 5 are connected, that is, a connection between the transmitter and the receiver is defective. It is sent to confirm whether or not. Forcibly switching circuit 4160f, when two signals that have been differentiated into a plus signal and a minus signal in differential circuit 4160e are input, the two circuits are connected so as to transmit the two signals. When two signals that are differentiated into a plus signal and a minus signal are not input in the conversion circuit 4160e, the circuit is configured so as to transmit a signal output from the transmitter IC 4160d. As a result, when two signals differentiated into a plus signal and a minus signal are input in the differential circuit 4160e, the two signals are connected to each other so as to transmit the two signals. The peripheral control board 4140 outputs (transmits) to the frame peripheral relay terminal board 868, the peripheral door relay terminal board 882, and the frame decoration drive board 194 of the door frame 5, while the differential circuit 4160e outputs a plus signal and a minus signal. When the two differential signals are not input to the circuit, the signal output from the transmitter IC 4160d is transmitted from the peripheral control board 4140 to the periphery of the frame because the circuit is connected to transmit the signal output from the transmitter IC 4160d. The relay terminal board 868, the peripheral door relay terminal board 882, and the frame decoration drive board 194 of the door frame 5 are provided on the frame decoration drive board 194. It is output (transmitted) to the over server IC194f. The peripheral control MPU 4150a performs a demonstration by the game board side effect display unit 1900 during the period when the start screen at the time of power-on of the pachinko gaming machine 1 is displayed on the game board side effect display unit 1900 or in the waiting state of the customer. LOCKN signal output request data is output from the LOCKN signal output request serial I / O port to the frame decoration drive board 194 of the door frame 5 (actually, the differential circuit 4160e provided in the peripheral control board 4140). Output (send).

  When the frame decoration drive board 194 of the door frame 5 receives the serial signal (serial data) from the peripheral control board 4140 by the receiver IC 194f, it outputs various serialized signals from the parallel signal (that is, the channel CH2 of the sound source built-in VDP 4160a). The drawing data is restored to three video signals, namely, a red video signal, a green video signal, and a blue video signal, and three synchronization signals such as a horizontal synchronization signal, a vertical synchronization signal, and a clock signal. The signal is output to the side signal separation control circuit 194g. The frame-side signal separation control circuit 194g uses the above-described predetermined screen (in this embodiment, red (R): 50%, green (G): 50%, blue (B ): Gray screen having 50%), which are drawing data on the door frame side, namely, three video signals of a red video signal, a green video signal, and a blue video signal, a horizontal synchronization signal, a vertical synchronization signal, and a clock signal. Among the three synchronizing signals and each decorative board of the door frame 5, a plurality of LEDs (decorative LEDs) provided on each of the plurality of frame side VDP controlled target decorative boards that are controlled by the built-in sound source VDP 4160a ) And the illumination information.

  The frame-side signal separation control circuit 194g is a predetermined screen (in this embodiment, red (R): 50%, green (G): 50%, blue (B) separated from the parallel signal restored by the receiver IC 194f. ): Gray screen having 50%), which are drawing data on the door frame side, namely, three video signals of a red video signal, a green video signal, and a blue video signal, a horizontal synchronization signal, a vertical synchronization signal, and a clock signal. The three synchronization signals are not output to other electronic components or other boards. On the other hand, the frame-side signal separation control circuit 194g receives each of the door frames 5 via the frame-side VDP control target decoration LED control circuit 194i based on the electrical decoration information separated from the parallel signal restored by the receiver IC 194f. Among the decorative boards, a plurality of LEDs are output by outputting signals to a plurality of LEDs (decorative LEDs) provided on each of the plurality of frame-side VDP control target decorative boards that are controlled by the built-in sound source VDP 4160a. (Decoration LED) emits light.

  When the receiver IC 194f receives the drawing data from the sound source built-in VDP 4160a and determines that the received drawing data is abnormal data, the receiver IC 194f sends a LOCKN signal to that effect to the peripheral door relay terminal board 882 and the frame peripheral relay terminal board. The data is output to the peripheral control board 4140 via 868. The LOCKN signal is input to the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 via a peripheral control input circuit (not shown) in the peripheral control board 4140. Peripheral control MPU 4150a, based on the input LOCKN signal, when a predetermined condition is satisfied, generates an image for notifying that effect by controlling sound source built-in VDP 4160a in the display area of game board side effect display unit 1900. Display and inform.

  When the receiver IC 194f determines that the two received signals are LOCKN signal output request data from the LOCKN signal output request serial I / O port, the receiver IC 194f sends the LOCKN signal from the LOCKN terminal to the peripheral door relay terminal plate 882, and The data is output to the peripheral control board 4140 through the frame peripheral relay terminal board 868. The LOCKN signal is input to the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 via a peripheral control input circuit (not shown) in the peripheral control board 4140. Accordingly, the peripheral control MPU 4150a determines that there is no malfunction in the connection between the transmitter and the receiver when the LOCKN signal is input as a response signal to the transmission of the LOCKN signal output request data. While it can be determined that there is no malfunction in the drive amplifier board 194, when the LOCKN signal is not input, it is determined that a malfunction has occurred in the connection between the transmitter and the receiver. It is determined that a problem has occurred in the amplifier board 194, and a notification image (for example, "A problem has occurred between the transmitter and the receiver. Please call the store clerk") is transmitted to the VDP 4160a with a built-in sound source. Control to draw (display) on the game board side effect display unit 1900 The door frame 5 is transmitted to the audio data transmission IC 4160c by controlling the built-in sound source VDP 4160a and outputting a notification sound (for example, “a defect has occurred between the transmitter and the receiver”) to the effect. Control is performed to send a notification sound from the speaker 130 provided in Thereby, notification can be performed by the notification image drawn (displayed) in the display area of the game board side effect display unit 1900 and the notification sound that repeatedly flows from the speaker 130 provided on the door frame 5. Yes. At this time, all of the plurality of LEDs provided on each decorative board of the door frame 5 and the plurality of LEDs provided on each decorative board of the game board 4 may be lit.

[7-4-3. RTC control unit]
As shown in FIG. 17, the RTC control unit 4165 that holds calendar information for specifying the date and time and time information for specifying the hour, minute, and second is configured with the RTC 4165a as the center. The RTC 4165a has a built-in RAM 4165aa that holds calendar information and time information (hereinafter referred to as “RTC built-in RAM 4165aa”). The RTC 4165a is supplied with power from a battery 4165b (in this embodiment, a button battery is used) as a driving power source and a backup power source for the RTC built-in RAM 4165aa. That is, the RTC 4165a is not supplied with any power from the peripheral control board 4140 (pachinko gaming machine 1), but is supplied with power from the battery 4165b independently of the peripheral control board 4140 (pachinko gaming machine 1). Thereby, even if the power of the pachinko gaming machine 1 is cut off, the RTC 4165a can update and hold calendar information and time information by supplying power from the battery 4165b.

  The peripheral control MPU 4150a of the peripheral control unit 4150 acquires calendar information and time information from the RTC built-in RAM 4165aa of the RTC 4165a, sets the information in the RTC information acquisition storage area 4150cad of the peripheral control RAM 4150c, and stores the acquired calendar information and time information. An effect based on the game board side effect display unit 1900 can be developed. As such an effect, for example, if it is December 25, the screen of a Christmas tree or a reindeer is unfolded on the game board side effect display unit 1900, or if it is New Year's Eve, the screen for executing the New Year countdown is the game board side effect. For example, it can be unfolded on the display unit 1900. Calendar information and time information are set at the time of factory shipment.

  In addition to the calendar information and time information, the RTC built-in RAM 4165aa also stores the input date and time information as the date, time, hour, minute and second information when the calendar information and the time information are first stored in the RTC built-in RAM 4165aa. Yes.

  Various information stored in the RTC built-in RAM 4165aa, such as calendar information, time information, and input date / time information, is set in the production line of the gaming machine manufacturer. In the production line, for example, in order to perform various tests such as a display test of the game board side effect display unit 1900, the year when the input date and time information was input on the production line as the date and time when the game board side effect display unit 1900 was first turned on. Set to the date and time of manufacture, which is the date and time.

  In this manner, the RTC built-in RAM 4165aa has calendar information that is information that needs to be maintained independently of the model information of the pachinko gaming machine 1 (for example, the probability of occurrence of a big hit gaming state with low probability or high probability), Time information, input date and time information, and the like can be stored and held.

  The current date and time may be specified by acquiring calendar information for specifying the date and time and time information for specifying the hour, minute, and second directly from the RTC built-in RAM 4165aa of the RTC control unit 4165, or a peripheral described later. Current calendar information that is set in the calendar information storage unit and updated by the system of the peripheral control board 4140 in the RTC information acquisition storage area 4150cad of the peripheral control RAM 4150c in the current time information acquisition process of step S1002 in the control unit power-on process And the current time information set in the time information storage unit and updated by the system of the peripheral control board 4140 may be acquired to identify the current date and time.

[7-4-4. Volume adjustment volume]
As described above, the volume adjustment volume 4140a is used to rotate the knob portion to adjust the volume of music, sound effects and the like flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5. It can be adjusted by doing. As described above, the volume adjustment volume 4140a is configured such that the resistance value can be changed by rotating the knob portion, and the electrically connected peripheral control A / D converter 4150ak is connected to the knob portion. The voltage divided by the resistance value at the rotational position is converted from an analog value to a digital value, and converted into a value in 1024 steps from 0 to 1023. In the present embodiment, as described above, the values of the 1024 steps are divided into seven and managed as the substrate volumes 0 to 6. The substrate volume 0 is set to mute, the substrate volume 6 is set to the maximum volume, and the volume is set to increase from the substrate volume 0 toward the substrate volume 6. The liquid crystal and sound control unit 4160 (VDP 4160a with built-in sound source) is controlled so that the volume is set to the substrate volume 0 to 6, and the speaker and door frame 5 provided in the speaker box 820 provided in the main body frame 3 are provided. Music and sound effects flow from the speaker 130.

  In this way, music and sound effects flow from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 by volume adjustment based on the turning operation of the knob portion. . Further, in the present embodiment, as described above, in addition to music and sound effects, a notification sound for notifying the clerk of the hall of the occurrence of a malfunction of the pachinko gaming machine 1 or an illegal act against the pachinko gaming machine 1, Announce contents related to game effects (for example, an announcement that there is a high possibility that the screen unfolded on the game board side effect display unit 1900 will be rendered more powerful, or that it is likely to shift to a game state advantageous to the player) The notification sound for the flow of sound from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 is also operated. It is a mechanism that flows without depending on the volume adjustment based on the sound volume, and the volume from the mute to the maximum volume is programmed by the liquid crystal and sound control unit 4160 (sound source built-in VD So that the it can be adjusted by controlling the 4160a).

  The volume adjusted by this program can be smoothly changed from the mute to the maximum volume, unlike the substrate volume divided into the above seven stages. Thus, for example, even when a hall clerk or the like rotates the knob portion of the volume adjustment volume 4140a to set the volume to a low level, the speakers and doors housed in the speaker box 820 provided in the main body frame 3 Although the production sound such as music and sound effects flowing from the speaker 130 provided in the frame 5 is reduced, the sound volume is increased when a malfunction occurs in the pachinko gaming machine 1 or when the player is cheating. In the embodiment, the notification sound set to the maximum volume) can be played. Therefore, even if the volume of the production sound is reduced, it is possible to prevent the hall clerk or the like from becoming difficult to notice the occurrence of a malfunction or the player's cheating due to the notification sound.

  Also, based on the current board volume set by volume adjustment based on the turning operation of the knob part, the volume of the advertisement sound is reduced so as not to interfere with the music and sound effects. In addition to music and sound effects, there is a possibility that the screen unfolded on the game board side effect display unit 1900 will be rendered more powerful, or that it will shift to a gaming state advantageous to the player. You can also announce that it is expensive.

  In the present embodiment, in addition to adjusting the volume of music and sound effects by turning the knob of the volume adjustment volume 4140a, the dial operation unit 401 and the press of the operation unit 400 are adjusted. By operating the operation unit 405, it is possible to shift to the setting mode and adjust the volume of music and sound effects. When the dial operation unit 401 or the press operation unit 405 of the operation unit 400 is operated within a predetermined time after the power of the pachinko gaming machine 1 is turned on, a screen for performing the setting mode is displayed on the game board side effect display unit 1900. In addition, when the dial operation unit 401 or the press operation unit 405 of the operation unit 400 is operated during the period when the game board side effect display unit 1900 is in the waiting state and the demonstration is performed, the setting mode is performed. The screen is displayed on the game board side effect display unit 1900. By operating the dial operation unit 401 and the press operation unit 405 of the operation unit 400 in accordance with the setting mode screen, the volume of music and sound effects can be adjusted to a desired volume.

  Specifically, the peripheral control A / D converter 4150ak converts the voltage divided by the resistance value at the rotational position of the knob portion of the volume adjustment volume 4140a from an analog value to a digital value. Thus, the value of the substrate volume can be increased or decreased by adding or subtracting a predetermined value according to the operation of the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400. . This adjusted volume is set and updated as a sub-volume value for a track in which sound data of effect sound such as music or sound effect is incorporated among a plurality of tracks in the sound source of the sound source with built-in sound source VDP 4160a. However, it is not reflected in the adjustment of the volume of the notification sound or notification sound described above.

  As described above, in the present embodiment, the volume of the music or the sound effect is adjusted by directly rotating the knob of the volume adjustment volume 4140a, and the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400 is adjusted. There are two methods: adding or subtracting a predetermined value according to the operation to adjust the volume of music or sound effects by increasing or decreasing the value of the substrate volume. Since the volume adjustment volume 4140a is mounted on the peripheral control board 4140, the main body frame 3 must be opened from the outer frame 2 without fail. Then, the hall clerk can turn the knob of the volume adjustment volume 4140a. However, at the volume adjusted by the hall clerk, it may be difficult for the player to hear the music or sound effect, or may be loud for the player to feel the music or sound effect. Therefore, after the power of the pachinko gaming machine 1 is turned on, the dial operation unit 401 and the pressing operation unit 405 of the operation unit 400 are operated within a predetermined time, or a demonstration is performed by the game board side effect display unit 1900 in a waiting state. If the dial operation unit 401 or the press operation unit 405 of the operation unit 400 is operated during the period being performed, a screen for performing the setting mode is displayed on the game board side effect display unit 1900. By operating the dial operation unit 401 and the pressing operation unit 405 of the operation unit 400 according to the setting mode screen, the volume of music and sound effects can be adjusted to a desired volume. Thus, the player can adjust the volume of the music and sound effects to a desired volume. Therefore, when the volume of the hall clerk feels low and it is difficult to hear the music and sound effects, the operation unit 400 The dial operation unit 401 and the pressing operation unit 405 can be operated to increase the volume to a desired level. If the volume of the hall clerk feels loud and the music and sound effects are noisy, the operation unit 400 The dial operation unit 401 and the pressing operation unit 405 can be operated to reduce the volume to a desired level.

  Further, in the present embodiment, a state in which no game is played in the pachinko gaming machine 1 is continued for a predetermined time, and when the customer board waiting state is entered and the demonstration by the game board side effect display unit 1900 is repeatedly performed (for example, 10 times). ) The volume adjusted by the player who was sitting on the front of the pachinko gaming machine 1 and playing the game last time is canceled and the volume is initialized. In the initialization of the volume, the volume adjusted by the hall clerk, that is, the volume adjusted by the hall clerk by directly rotating the knob portion of the volume adjustment volume 4140a is adjusted. As a result, if it is difficult to hear the music or sound effect by feeling the volume adjusted by the player who was sitting on the front of the pachinko gaming machine 1 last time and adjusting the volume, A player who sits down and plays a game can increase the sound volume to a desired level by operating the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400, or sits in front of the pachinko gaming machine 1 and plays a game. When the player who has played the game feels loud and adjusts the volume, the player who sits on the front surface of the pachinko gaming machine 1 and plays the game this time It is possible to reduce the sound volume to a desired level by operating 401 or the pressing operation unit 405.

[8. Power system]
Next, the power supply system of the pachinko gaming machine 1 will be described with reference to FIGS. FIG. 21 is a block diagram showing a power supply system of a pachinko gaming machine, FIG. 22 is a block diagram (a) showing a power generation circuit, and a diagram showing a relationship between power consumption and a power consumption suppression level associated with power consumption ( FIG. 23 is a block diagram showing a continuation of FIG. First, the power supply board will be described, and then the power supplied to each control board will be described. Note that the grounds (GND) of various substrates and the grounds (GND) of various terminal boards are electrically connected to the ground (GND) of the power supply substrate 851 and are the same ground (GND).

[8-1. Power supply board]
The power supply board 851 is electrically connected to the power cord, and the plug of the power cord is inserted into the power outlet of the pachinko island facility. When the power switch 852 shown in FIG. 3 is operated, the power supplied from the pachinko island facility is supplied to the power supply board 851, and the pachinko gaming machine 1 can be turned on.

  As shown in FIG. 21, the power supply board 851 includes a power supply control unit 855, a firing solenoid drive circuit 858, and a ball feed solenoid drive circuit 859. The power supply control unit 855 is a circuit that creates various DC voltages from AC 24 volts (AC24V) supplied from the Pachinko Island facility, and supplies backup power to the main control board 4100 and the payout control board 4110. The drive circuit 858 is a circuit that drives the firing solenoid 654 of the ball striking device 650 shown in FIG. 5, and the ball feed solenoid drive circuit 859 drives the ball feed solenoid 585 of the ball feed unit 580 shown in FIG. Circuit.

  The power supply control unit 855 includes a synchronous rectification circuit 855a, a power factor correction circuit 855b, a smoothing circuit 855c, a power supply generation circuit 855d, and capacitors BC0 and BC1. The AC 24V supplied from the pachinko island facility is supplied to the gaming ball lending device connection terminal plate 869 via the power supply board 851 and to the synchronous rectifier circuit 855a. The synchronous rectification circuit 855a rectifies 24 volt (AC 24V) supplied from the Pachinko Island facility and supplies the rectified current to the power factor correction circuit 855b. This power factor improvement circuit 855b improves the power factor of the rectified power to create a direct current + 37V (DC + 37V, hereinafter referred to as “+ 37V”) and supplies it to the smoothing circuit 855c. The smoothing circuit 855c removes the supplied + 37V ripple, smoothes + 37V, and supplies it to the firing solenoid drive circuit 858, the ball feed solenoid drive circuit 859, and the power generation circuit 855d.

  The capacitor BC0 supplies backup power to a RAM (main control built-in RAM) built in the main control MPU 4100a of the main control board 4100, and the capacitor BC1 is built in the payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110. A backup power source is supplied to the RAM (payout control built-in RAM).

  The launch solenoid drive circuit 858 is controlled by the launch ball feed control circuit 4120ag built in the payout control MPU 4120a of the payout control board 4110 shown in FIG. The driving current to the firing solenoid 654 is adjusted so that the game ball can be launched (launched) toward the game area 1100 based on the operation signal from. Thereby, the game ball can be launched (launched) toward the game area 1100 shown in FIG. 1 with a launch strength (launch strength) corresponding to the rotational position of the front 506 of the rotary handle body shown in FIG. On the other hand, the ball feed solenoid drive circuit 859 is controlled by a launch ball feed control circuit 4120ag built in the payout control MPU 4120a of the payout control board 4110 shown in FIG. Thus, the drive current to the ball feeding solenoid 585 is adjusted to be a constant current. As a result, the ball feeding member of the ball feeding unit 580 receives one game ball stored in the upper plate 301 of the dish unit 300 shown in FIG. 7, and the game ball received by the ball feeding member is directed to the ball hitting device 650. Can send.

  The power generation circuit 855d includes a power consumption monitoring circuit 855da, a + 5V power generation circuit 855db, a + 12V power generation circuit 855dc, and a + 24V power generation circuit 855dd. + 37V supplied from the smoothing circuit 855c is supplied to the + 5V power generation circuit 855db, the + 12V power generation circuit 855dc, and the + 24V power generation circuit 855dd via the power consumption monitoring circuit 855da.

  The power consumption monitoring circuit 855da monitors the power consumption of + 37V supplied from the smoothing circuit 855c. The power consumption monitoring circuit 855da monitors the power consumption of +37 V supplied from the smoothing circuit 855c, and determines a power consumption suppression stage indicating how much power consumption should be suppressed based on the power consumption. The determination result is output to the frame peripheral relay terminal plate 868 as a power consumption suppression signal. The power consumption suppression signal output from the power consumption monitoring circuit 855da of the power generation circuit 855d is configured as three signal wires (that is, configured as three parallel signals), and has a value 0 to a value 7 Can be transmitted to the peripheral control board 4140 through the frame peripheral relay terminal plate 868, while being input through the frame peripheral relay terminal plate 868 and the peripheral door relay terminal plate 882. The frame decoration drive amplifier board 194 is inputted (see FIG. 23B). Then, the power consumption suppression signal from the power consumption monitoring circuit 855da of the power generation circuit 855d is input to the board to which the door frame is mounted via the frame decoration drive amplifier board 194 (FIG. 23 (b)).

  Specifically, the power consumption monitoring circuit 855da includes a power measurement circuit 855daa and a power consumption suppression stage determination circuit 855dab as shown in FIG. + 37V supplied from the smoothing circuit 855c is supplied to the + 5V power generation circuit 855db, the + 12V power generation circuit 855dc, and the + 24V power supply generation circuit 855dd via the power measurement circuit 855daa. The power measurement circuit 855daa measures the power consumption of + 37V supplied from the smoothing circuit 855c in real time and outputs it to the power consumption suppression stage determination circuit 855dab. The power consumption suppression stage determination circuit 855dab determines a power consumption suppression stage indicating how much power consumption should be suppressed based on the power consumption measured by the power measurement circuit 855daa. The value of the power consumption suppression signal configured as a signal wiring is set and output to the frame peripheral relay terminal board 868.

  The relationship between the power consumption suppression stage indicating how much power consumption should be suppressed, the power consumption measured by the power measurement circuit 855daa, and the power consumption suppression stage indicating how much power consumption should be suppressed (ie, power The relationship between the consumption and the power consumption suppression level accompanying the power consumption) will be briefly described. In the present embodiment, it is assumed that the power (AC 24 V) is supplied to one pachinko gaming machine 1 for one transformer (maximum allowable capacity: 250 VA) provided in the pachinko island facility, and FIG. As shown, when the horizontal axis represents the power consumption with respect to the maximum allowable capacity of the transformer and the vertical axis represents steps 0 to 7 as the power consumption suppression step, the power consumption suppression stage determination circuit 855dab is a power measurement circuit. When the power consumption of + 37V measured at 855daa is 0% or more and less than 10%, it is determined that the power consumption suppression stage is stage 0, the value 0 is set as the value of the power consumption suppression signal, and measurement is performed by the power measurement circuit 855daa. When the power consumption of + 37V is 10% or more and less than 20%, it is determined that the power consumption suppression stage is stage 1, and the value 1 is set as the value of the power consumption suppression signal. When the power consumption of + 37V measured by the power measurement circuit 855daa is 20% or more and less than 30%, it is determined as stage 2 as the power consumption suppression stage, and the value 2 is set as the value of the power consumption suppression signal, When the power consumption of + 37V measured by the power measurement circuit 855daa is 30% or more and less than 40%, it is determined as stage 3 as the power consumption suppression stage, and the value 3 is set as the value of the power consumption suppression signal. When the power consumption of + 37V measured at 855 daa is 40% or more and less than 50%, it is determined as stage 4 as the power consumption suppression stage, and the value 4 is set as the value of the power consumption suppression signal, and measurement is performed by the power measurement circuit 855daa. When the power consumption of + 37V is 50% or more and less than 60%, the power consumption is judged to be stage 5 as the power consumption suppression stage. When the power consumption of + 37V measured by the power measurement circuit 855daa is 60% or more and less than 70%, the value 5 is set as the control signal value, and it is determined as step 6 as the power consumption suppression stage, and the power consumption suppression signal The value 6 is set as the value, and when the power consumption of + 37V measured by the power measuring circuit 855daa is 70% or more, it is determined as the stage 7 as the power consumption suppression stage and the value 7 is set as the value of the power consumption suppression signal To do.

  It should be noted that in the pachinko island facility, a system is usually used in which, for example, four pachinko gaming machines 1 are supplied as a group to one transformer, for example, to supply power (AC24V), respectively (for example, in one row). In a pachinko island facility in which 20 pachinko machines 1 are installed, four pachinko machines 1 are managed as five groups, and one transformer is provided for each group (a total of five transformers). ), Because a system in which power (AC24V) is supplied is adopted), a plurality of transformers having a maximum allowable capacity of 1000 VA are provided in the pachinko island facility.

  The + 5V power supply creation circuit 855db creates DC + 5V (DC + 5V, hereinafter referred to as “+ 5V”) from + 37V supplied from the smoothing circuit 855c via the power consumption monitoring circuit 855da. The +12 V power supply generation circuit 855 dc generates DC +12 V (DC +12 V, hereinafter referred to as “+12 V”) from +37 V supplied from the smoothing circuit 855 c via the power consumption monitoring circuit 855 da. The + 24V power supply generation circuit 855dd generates a direct current + 24V (DC + 24V, hereinafter referred to as “+ 24V”) from + 37V supplied from the smoothing circuit 855c via the power consumption monitoring circuit 855da. + 5V, + 12V, and + 24V are supplied to the payout control board 4110 and the frame peripheral relay terminal board 868, respectively. The power supply system supplied with + 5V is the + 5V power supply line, the power supply system supplied with + 12V is supplied with the + 12V power supply line, and the power supply system supplied with + 24V is supplied with the + 24V power supply line.

  + 5V generated by the + 5V power supply generation circuit 855db of the power supply generation circuit 855d is supplied to the payout control board 4110, as will be described later. + 5V supplied to the payout control board 4110 is applied to the power supply terminal of the payout control MPU 4120a via the payout control filter circuit 4110a, and to the power supply terminal of the payout control built-in RAM via the diode PD0. ing. The + 12V generated by the + 12V power supply generation circuit 855dc of the power supply generation circuit 855d is supplied to the + 5V generation circuit 4100g of the main control board 4100 via the payout control board 4110. The + 5V creation circuit 4100g creates + 5V that is the control reference voltage of the main control MPU 4100a from + 12V from the payout control board 4110. The + 5V generated by the + 5V generating circuit 4100g is supplied to the power supply terminal of the main control MPU 4100a via the main control filter circuit 4100h and is also supplied to the power supply terminal of the main control built-in RAM via the diode MD0. ing.

  The negative terminal of the capacitor BC1 of the power supply board 851 is grounded to the ground (GND), while the positive terminal of the capacitor BC1 is electrically connected to the power supply terminal of the payout control built-in RAM of the payout control board 4110 and is discharged. The cathode terminal of the diode PD0 of the control board 4110 is also electrically connected. In other words, + 5V created by the + 5V power supply creation circuit 855db of the power supply creation circuit 855d on the power supply board 851 flows current toward the power supply terminal of the payout control MPU 4120a, and the power supply of the payout control built-in RAM is forward by the diode PD0. A current flows toward the terminal and the positive terminal of the capacitor BC1. As described above, the capacitor BC1 is electrically connected to the supply control board 4110 and again from the supply control board 4110 to the power supply board 851 by + 5V generated by the + 5V power supply generation circuit 855db of the power supply generation circuit 855d in the power supply board 851. With a simple connection method, + 5V is supplied and charging is possible. As a result, when + 5V generated by the + 5V power generation circuit 855db of the power generation circuit 855d is not supplied to the payout control board 4110, the charge charged in the capacitor BC1 is supplied to the payout control board 4110 as the payout VBB. Since the current is blocked by the diode PD0 and does not flow to the power supply terminal of the payout control MPU 4120a and the payout control MPU4120a does not operate, the payout VBB is supplied to the power supply terminal of the payout control built-in RAM. Thus, the stored contents are held.

  The negative terminal of the capacitor BC0 of the power supply board 851 is grounded to the ground (GND), while the positive terminal of the capacitor BC0 is electrically connected to the power supply terminal of the main control built-in RAM of the main control board 4100 via the payout control board 4110. And is also electrically connected to the cathode terminal of the diode MD0 of the main control board 4100. In other words, + 5V created by the + 5V creating circuit 4100g is such that current flows toward the power supply terminal of the main control MPU 4100a, and the power supply terminal of the main control built-in RAM, which is forward by the diode MD0, and the positive terminal of the capacitor BC0, An electric current flows toward. In this way, the capacitor BC0 is charged with + 5V supplied by the electrical connection method in which + 5V generated by the + 5V generating circuit 4100g is supplied from the main control board 4100 and the payout control board 4110 to the power supply board 851. Can be done. As a result, + 12V generated by the + 12V power generation circuit 855dc of the power generation circuit 855d in the power supply board 851 is not supplied to the + 5V generation circuit 4100g of the main control board 4100 via the payout control board 4110, and the + 5V generation circuit 4100g becomes + 5V. Since the charge charged in the capacitor BC0 is supplied as the main VBB to the main control board 4100 via the payout control board 4110, the main control MPU 4100a Although the main control MPU 4100a does not operate because the current is blocked by the diode MD0 and the main control MPU 4100a does not operate, the main VBB is supplied to the power supply terminal of the main control built-in RAM so that the stored contents are held. Yes.

[8-2. Voltage supplied to each control board]
Next, an outline of the voltage supplied to each control board and the like will be described, and subsequently, the voltage supplied mainly to the payout control board and the voltage supplied to the main control board will be described.

  The three types of voltages of + 5V, + 12V, and + 24V created by the + 5V power generation circuit 855db, the + 12V power generation circuit 855dc, and the + 24V power generation circuit 855dd of the power generation circuit 855d on the power supply board 851 are as shown in FIG. In addition, two types of voltages of + 12V and + 24V among these three types of voltages are supplied to the main control board 4100 via the payout control board 4110. The three types of voltages, + 5V, + 12V, and + 24V, created by the + 5V power generation circuit 855db, the + 12V power generation circuit 855dc, and the + 24V power generation circuit 855dd of the power generation circuit 855d on the power supply board 851 are the frame peripheral relay terminals. In addition to being supplied to the board 868, it is supplied to the peripheral control board 4140 and the peripheral door relay terminal board 882 via the frame peripheral relay terminal board 868.

  One type of voltage of +5 V supplied to the peripheral control board 4140 is supplied to the lamp driving board 4170 as shown in FIG. The + 5V supplied from the peripheral control board 4140 is supplied to the game board side peripheral control MPU control target decoration LED control circuit 4170k of the lamp drive board 4170 as an electric decoration power supply (also serving as a control voltage). These are supplied to various electronic components (electronic components whose control voltage is +5 V) mounted on the lamp driving substrate 4170.

  Three types of voltages of +5 V, +12 V, and +24 V supplied to the peripheral control board 4140 are supplied to the drive source drive circuit 4180a of the motor drive board 4180, respectively, as shown in FIG. The drive source drive circuit 4180a of the motor drive board 4180 is a circuit that outputs a drive signal to an electric drive source such as a motor or solenoid of the game board 4, and converts serial data provided in the motor drive board 4180 into parallel data. A parallel signal is input from the serial-parallel conversion circuit. This serial-parallel conversion circuit is a motor, solenoid or the like that operates various movable bodies provided on the game board 4 from the peripheral I / O port for the motor drive board of the peripheral control MPU 4150a of the peripheral control board 4140 via the peripheral control output circuit. The game board side motor drive data (serial data) for outputting a drive signal to the electrical drive source is input, and the serial data is converted into parallel data to output a parallel signal. The drive source drive circuit 4180a includes a motor drive circuit that can output a drive signal to the motor in response to a parallel signal from the serial-parallel conversion circuit, and a solenoid drive circuit that can output a drive signal to the solenoid. I have. If the motor drive circuit and the solenoid drive circuit have a built-in serial / parallel conversion circuit, it is not necessary to arrange the serial / parallel conversion circuit in the previous stage, so that the peripheral I / O MPU 4150a has a serial I / O for the motor drive board. It is possible to configure the circuit so that game board side motor drive data from the O port is input.

  Three types of voltages, +5 V, +12 V, and +24 V, supplied to the peripheral control board 4140 are supplied to the liquid crystal output board 3420 as shown in FIG. + 24V supplied from the peripheral control board 4140 is supplied to the power supply circuit 3420e for various light guide plates on the game board side of the liquid crystal output board 3420. The game board side various light guide plate power supply circuit 3420e is composed of a total of six light guide plate power supply circuits, that is, a first light guide plate power circuit to a sixth light guide plate circuit, from + 24V to the light guide plate. + 12V is created as a power source for the system. + 12V created by the various light guide plate power circuit 3420e on the game board side is supplied to the various light guide plate control circuits 3420k. The various light guide plate control circuits 3420k include six independent light guide plate control circuits, i.e., a first light guide plate control circuit to a sixth light guide plate control circuit, which will be described later, and constitute six independent power source circuits 3420e for the game board side light guide plates. The power supply circuit for the light guide plate is configured independently and supplied with + 12V. + 12V supplied from the peripheral control board 4140 is supplied to the game board side liquid crystal module power supply circuit 3420a of the liquid crystal output board 3420. The game board-side liquid crystal module power supply circuit 3420a creates a direct current of 3.3V (+ 3.3V, hereinafter referred to as “+ 3.3V”) from + 12V. The + 3.3V created by the game board side liquid crystal module power supply circuit 3420a is supplied to various electronic components mounted on the liquid crystal output board 3420 (electronic components having + 3.3V as a control voltage). These are supplied to various electronic components mounted on the board provided in the game board side effect display unit 1900. The + 5V supplied from the peripheral control board 4140 is supplied to the game board side VDP control target decoration LED control circuit 3420i of the liquid crystal output board 3420 as an electric power source for decoration (also serves as a control voltage). These are supplied to various electronic components (electronic components having a control voltage of +5 V) mounted on the output board 3420.

  On the other hand, three types of voltages, + 5V, + 12V, and + 24V, supplied to the peripheral door relay terminal plate 882 are supplied to the frame decoration drive amplifier board 194 as shown in FIG. + 5V supplied from the peripheral door relay terminal plate 882 serves as a decorative LED control circuit 194i for the frame side VDP control object of the frame decoration drive amplifier board 194 and a frame side peripheral control MPU control as a power source for decoration (also serves as a control voltage). In addition to being supplied to the target decoration LED control circuit 194k, it is also supplied to various electronic components (electronic components whose + 5V is the control voltage) mounted on the frame decoration drive amplifier board 194. Further, three types of voltages of +5 V, +12 V, and +24 V are supplied to a motor drive circuit (not shown) that outputs a drive signal to an electric drive source such as a dial drive motor 414 provided on the door frame 5. The motor drive circuit receives a parallel signal from a serial / parallel conversion circuit (not shown) that converts serial data included in the frame decoration drive amplifier board 194 into parallel data. This serial / parallel conversion circuit is connected to an electric circuit such as a dial drive motor 414 provided on the door frame 5 via a peripheral control output circuit from the frame decoration drive amplifier board motor serial I / O port of the peripheral control MPU 4150a of the peripheral control board 4140. This is a circuit that receives door side motor drive data (serial data) for outputting a drive signal to a general drive source, converts this serial data into parallel data, and outputs a parallel signal. The motor drive circuit can output a drive signal to the dial drive motor 414 or the like according to the parallel signal from the serial / parallel conversion circuit. If the motor drive circuit has a built-in serial / parallel conversion circuit, it is not necessary to arrange the serial / parallel conversion circuit in the previous stage, so that the peripheral control MPU 4150a has a frame decoration drive amplifier board motor serial I / O port. It is possible to configure the circuit so that door side motor drive data from is input.

  In addition, a total of three types of voltages, + 5V, + 12V, and + 24V, supplied from the peripheral door relay terminal plate 882 are supplied to the board on which the door frame is mounted.

[8-2-1. Voltage supplied to dispensing control board]
As shown in FIG. 21, the payout control board 4110 includes a payout control filter circuit 4110a in addition to the payout control MPU 4120a. The payout control filter circuit 4110a is supplied with + 5V from the power supply board 851, and removes noise from the + 5V. In addition to being supplied to the capacitor BC1 of the power supply board 851 via the diode PD0, this + 5V is supplied to, for example, the payout control MPU 4120a of the payout control unit 4120. For example, + 12V from the power supply board 851 is supplied to the payout control input circuit 4120b of the payout control unit 4120 and the like, and is also supplied to the external communication circuit 784a of the external terminal board 784 via the payout control board 4110. The external communication circuit 784a of the external terminal board 784 outputs a signal that conveys the number of game balls paid out by the pachinko gaming machine 1 and game information of the pachinko gaming machine 1 to a hall computer installed in the game hall (hall). Circuit. The hall computer monitors the player's game by grasping the number of game balls paid out by the pachinko gaming machine 1 and the game information of the pachinko gaming machine 1 from the signal output from the external communication circuit 784a. . Note that +24 from the power supply board 851 is supplied to the main control board 4100 via the payout control board 4110 without being used in the payout control board 4110 at all.

[8-2-2. Voltage supplied to main control board]
As shown in FIG. 21, the main control board 4100 includes, in addition to the main control MPU 4100a and the like, a + 5V creation circuit 4100g, a main control filter circuit 4100h, a power failure monitoring circuit 4100e, and the like. The + 5V creation circuit 4100g is supplied with + 12V from the power supply board 851 via the payout control board 4110, and creates + 5V which is the control reference voltage of the main control MPU 4100a from this + 12V. In the main control board 4100, a power supply system supplied with + 5V generated by the + 5V generating circuit 4100g is a + 5V power supply line. In the present embodiment, the + 5V power supply line created by the + 5V power creation circuit 855db of the power supply creation circuit 855d in the power supply board 85 and the + 5V power supply line created by the + 5V creation circuit 4100g of the main control board 4100 are electrically connected. Since the circuit is configured so as not to be connected, the + 5V power supply line created by the + 5V power supply creation circuit 855db of the power supply creation circuit 855d in the power supply board 851 is electrically connected to various electronic components of the main control board 4100. In other words, the + 5V power supply line created by the + 5V creation circuit 4100g of the main control board 4100 is not electrically connected to various electronic components such as other boards other than the main control board 4100.

  The main control filter circuit 4100h is supplied with + 5V created by the + 5V creation circuit 4100g, and removes noise from this + 5V. In addition to being supplied to the capacitor BC0 of the power supply substrate 851 through the diode MD0, this + 5V is supplied to, for example, the main control MPU 4100a. For example, + 12V from the payout control board 4110 is supplied to the main control input circuit 4100b and the like, and + 24V from the payout control board 4110 is supplied to the main control solenoid drive circuit 4100d and the like, for example.

  The power failure monitoring circuit 4100e is supplied with + 12V and + 24V from the power supply board 851 via the payout control board 4110, and monitors these + 12V and + 24V signs of power failure or instantaneous power failure. When the power failure monitoring circuit 4100e detects signs of + 12V and + 24V power failure or instantaneous power failure, the power failure monitoring circuit 4100e outputs a power failure warning signal to the main control MPU 4100a as a power failure warning. The power failure notice signal is input to the payout control MPU 4120a via the main control board 4100 and the payout control input circuit 4120b of the payout control board 4110. The power failure notice signal is input to the peripheral control board 4140 via the main control board 4100. Further, the power failure notice signal is input to the frame decoration drive amplifier board 194 through the peripheral control board 4140, the frame peripheral relay terminal board 868, and the peripheral door relay terminal board 882 as shown in FIG. At the same time, the frame decoration drive amplifier board 194 is inputted to the board to which the door frame is mounted.

  In the present embodiment, the power failure monitoring circuit 4100e is applied to one of the + 12V power line and the + 24V power line by monitoring the voltages applied to the two power lines, the + 12V power line and the + 24V power line, respectively. Compared with the case where the voltage to be monitored is monitored, it is possible to more accurately grasp the sign of power interruption such as a power failure or a momentary power failure.

[9. Main control board circuit]
Next, the circuit and the like of the main control board 4100 shown in FIG. 14 will be described with reference to FIGS. 24 is a circuit diagram showing a circuit of the main control board, FIG. 25 is a circuit diagram showing a power failure monitoring circuit, and FIG. 26 is a circuit showing an interface circuit for communication between the main control board and the peripheral control board. FIG. First, the main control filter circuit 4100h shown in FIG. 21 will be described, followed by the power source, main control system reset, main control crystal oscillator, main control input circuit, power failure monitoring circuit, main control MPU created by the main control board 4100. Various input / output signals to and from the main control board 4100 and the peripheral control board 4140 will be described.

  Main control board 4100 includes main control MPU 4100a, main control input circuit 4100b, main control output circuit 4100c, main control solenoid drive circuit 4100d, power failure monitoring circuit 4100e, + 5V creation circuit 4100g, In addition to the control filter circuit 4100h, as a peripheral circuit, as shown in FIG. 24, a main control system reset MIC1 that outputs a reset signal, a main control crystal oscillator MX0 that outputs a clock signal (in this embodiment, 24 megahertz (MHz) )) Mainly.

[9-1. Main control filter circuit]
As shown in FIG. 24, the main control filter circuit 4100h mainly includes a main control three-terminal filter MIC0. This main control three-terminal filter MIC0 is a T-type filter circuit, and has excellent attenuation characteristics magnetically shielded with ferrite. In the main control three-terminal filter MIC0, + 5V generated by the + 5V generating circuit 4100g is applied to the first terminal, the second terminal is grounded to the ground (GND), and noise components are removed from the third terminal. + 5V is output. + 5V applied to the first terminal is electrically connected to the other end of the capacitor MC0 whose one end is connected to the ground (GND), so that the ripple (AC component superimposed on the voltage) is first removed. Smoothed.

  + 5V output from the third terminal is electrically connected to the other end of the capacitor MC1 and the electrolytic capacitor MC2 (capacitance: 470 microfarad (μF) in this embodiment), one end of which is grounded with the ground (GND). By connecting to, ripples are further removed and smoothed. The smoothed +5 V is applied to the power supply terminal of the main control system reset MIC1, the VDD terminal that is the power supply terminal of the main control crystal oscillator MX0, the VDD terminal that is the power supply terminal of the main control MPU 4100a, and the like. Note that the power supply terminal of the main control MPU 4100a has a power failure or a momentary power failure, and when the power supply from the pachinko island facility is cut off, the electric charge charged in the electrolytic capacitor MC2 is a power failure or a momentary power failure. It is applied as +5 V over a period of about 7 milliseconds (ms) after the occurrence.

  One end of the VDD terminal of the main control MPU 4100a is electrically connected to the other end of the capacitor MC3 which is grounded to the ground (GND), and + 5V applied to the VDD terminal is further smoothed by removing ripples. The VSS terminal, which is the ground terminal of the main control MPU 4100a, is grounded to the ground (GND).

  In addition, the VDD terminal of the main control MPU 4100a is electrically connected to the anode terminal of the diode MD0 in addition to being electrically connected to the capacitor MC3. The cathode terminal of the diode MD0 is electrically connected to the VBB terminal, which is a power supply terminal of a RAM (main control built-in RAM) built in the main control MPU 4100a, and one end of the capacitor MC4 is grounded to the ground (GND). Is electrically connected to the other end. In addition to being electrically connected to the cathode terminal of the diode MD0 and the other end of the capacitor MC4, the VBB terminal of the main control built-in RAM is connected to the positive terminal of the capacitor BC0 of the power supply board 851 shown in FIG. It is electrically connected to the terminal. That is, +5 V smoothed by removing the noise component by the main control filter circuit 4100h is applied to the VDD terminal of the main control MPU 4100a, and via the diode MD0, the VBB terminal of the main control built-in RAM and the capacitor BC0. Are applied to the positive terminal. Thereby, as described above, + 12V generated by the + 12V power generation circuit 855dc of the power generation circuit 855d in the power supply board 851 shown in FIG. 21 is transferred to the + 5V generation circuit 4100g of the main control board 4100 via the payout control board 4110. When the + 5V generation circuit 4100g cannot generate + 5V because it is not supplied, the electric charge charged in the capacitor BC0 is supplied to the main control board 4100 as the main VBB. Although the main control MPU 4100a does not operate because the current is blocked by the diode MD0 and does not flow to the VDD terminal of the MPU 4100a, the stored contents are held by applying the main VBB to the VBB terminal of the main control built-in RAM. ing.

[9-2. Main control system reset]
As shown in FIG. 24, +5 V smoothed by removing the noise component by the main control filter circuit 4100h is applied to the power supply terminal of the main control system reset MIC1. The main control system reset MIC1 resets the main control MPU 4100a and the main control output circuit 4100ca with a reset function, and has a built-in delay circuit. One end of the delay capacitor terminal of the main control system reset MIC1 is electrically connected to the other end of the capacitor MC5 grounded to the ground (GND), and the delay time by the delay circuit is set by the capacitance of the capacitor MC5. Be able to. Specifically, when + 5V input to the power supply terminal reaches a threshold value (for example, 4.25V), main control system reset MIC1 outputs a system reset signal from the output terminal after the delay time has elapsed.

  The output terminal of the main control system reset MIC1 is electrically connected to the SRST terminal which is a reset terminal of the main control MPU 4100a and the reset terminal of the main control output circuit 4100ca with reset function. The output terminal is an open collector output type, one end of which is electrically connected to the other end of the pull-up resistor MR1 that is electrically connected to the + 5V power line, and the other end is a capacitor that is grounded to the ground (GND). It is electrically connected to the other end of MC6. Ripple is removed and smoothed by this capacitor MC6. When the voltage input to the power supply terminal is larger than the threshold value, the output terminal is pulled up to + 5V side by the pull-up resistor MR1 and the logic becomes HI. When the voltage input to the reset terminal of the circuit 4100ca is lower than the threshold value, the logic is LOW. This logic is the SRST terminal of the main control MPU 4100a and the main control output circuit 4100ca with reset function. Each is input to the reset terminal. Since the SRST terminal of the main control MPU 4100a and the reset terminal of the main control output circuit 4100ca with reset function are negative logic inputs, respectively, when the voltage input to the power supply terminal is smaller than the threshold value, the main control MPU 4100a and the reset function The attached main control output circuit 4100ca is reset. The power supply terminal is electrically connected to the other end of the capacitor MC7 whose one end is grounded (GND), and + 5V input to the power supply terminal is smoothed by removing ripples. The ground terminal is grounded with a grant (GND), and the NC terminal is not electrically connected to the outside.

[9-3. Main control crystal oscillator]
As shown in FIG. 24, + 5V smoothed by removing the noise component by the main control filter circuit 4100h is applied to the VDD terminal which is the power supply terminal of the main control crystal oscillator MX0. This VDD terminal is electrically connected to the other end of the capacitor MC8, one end of which is grounded (GND), and + 5V inputted to the VDD terminal is further smoothed by removing ripples. In addition to the VDD terminal, the smoothed + 5V is also applied to the A terminal, B terminal, C terminal, and ST terminal, which are output frequency selection terminals. The main control crystal oscillator MX0 outputs a clock signal of 24 MHz from the F terminal which is an output terminal by applying + 5V to these A terminal, B terminal, C terminal and ST terminal.

  The F terminal of the main control crystal oscillator MX0 is electrically connected to the CLK terminal which is the clock terminal of the main control MPU 4100a, and a clock signal of 24 MHz is input. Note that the GND terminal, which is the ground terminal of the main control crystal oscillator MX0, is grounded to the ground (GND), and the D terminal that outputs the divided frequency of the F terminal of the main control crystal oscillator MX0 is not electrically connected to the outside. It is in a state.

[9-4. Main control input circuit]
The main control input circuit 4100b detects from the general prize opening switches 3020 and 3020, the first start port switch 3022, the second start port switch 2109, the magnetic detection switch 304, the count switch 2110, and the gate switch 2352 shown in FIG. In addition to the signal, an operation signal (RAM clear signal) or the like from the operation switch 860a provided in the payout control board 4110 shown in FIG. 15 is input. Since the circuit configuration to which the detection signal from each switch is input is the same, here, a circuit to which the operation signal (RAM clear signal) from the operation switch 860a is input will be described.

[9-4-1. A circuit to which an operation signal (RAM clear signal) is input from the operation switch]
First, as described above, the operation switch 860a includes the RAM (payout control built-in RAM) built in the payout control MPU 4120a of the payout control board 4110 and the main control of the main control board 4100 within a predetermined period from when the power is turned on. It is operated when clearing the RAM (main control built-in RAM) built in the MPU 4100a, or when an error is notified after the power is turned on, it is operated to cancel the error. Function to clear RAM within a predetermined period from power-on, and error cancellation after power-on (after a period during which the function is performed as RAM clear, that is, after a predetermined period elapses from power-on) And a function of performing Since the main control board 4100 does not have the error canceling function of the payout control board 4110, if an operation signal is input from the operation switch 860a within a predetermined period from when the power is turned on, the main control board 4100 receives the main control board 4100. A process of clearing the main control built-in RAM is performed as a RAM clear signal for clearing the built-in RAM.

  The main control board 4100 receives an operation signal whose logic is LOW from the payout control board 4110 when the operation switch 860a is not operated, while the logic from the payout control board 4110 when the operation switch 860a is operated. The operation signal in which HI becomes HI is input from the payout control board 4110 (detailed explanation of this point will be described later).

  As shown in FIG. 24, the transmission line for transmitting the operation signal from the operation switch 860a provided in the payout control board 4110 within a predetermined period from the time of power-on is a pull-up in which one end is electrically connected to the + 12V power line. It is electrically connected to the other end of the resistor MR2 and electrically connected to the base terminal of the transistor MTR0 via the resistor MR3. In addition to being electrically connected to the resistor MR3, the base terminal of the transistor MTR0 is also electrically connected to the other end of the resistor MR4 that is grounded to the ground (GND). The emitter terminal of the transistor MTR0 is grounded to the ground (GND), and the collector terminal of the transistor MTR0 is electrically connected to the other end of the resistor MR5, one end of which is electrically connected to the + 5V power supply line, and a non-inverting buffer. Main control via ICMIC 10 (non-inverted buffer ICMIC 10 includes eight non-inverted buffer circuits, and the signal waveform input to one of them (MIC 10A) is shaped and output without being inverted). The MPU 4100a is electrically connected to the input terminal PA0 of the input port PA.

  The circuit that outputs the operation signal from the operation switch 860a in the payout control board 4110 is configured as an open collector output type in which the emitter terminal is grounded to the ground (GND), and transmits the operation signal from the operation switch 860a. The line is pulled up to the + 12V side by the pull-up resistor MR2. In the main control board 4100, when the operation switch 860a is not operated, the operation signal from the payout control board 4110 is pulled down to the ground (GND) side and the logic is input as LOW, while the operation switch 860a is operated. The operation signal from the payout control board 4110 is pulled up to the + 12V side by the pull-up resistor MR2 and the logic becomes HI.

  A circuit including the resistors MR3 and MR4 and the transistor MTR0 is a switch circuit that is turned on / off by an operation signal from the operation switch 860a.

  When the operation switch 860a is not operated, an operation signal whose logic is LOW is input to the base terminal of the transistor MTR0, so that the transistor MTR0 is turned OFF and the switch circuit is also turned OFF. As a result, the voltage applied to the collector terminal of the transistor MTR0 is pulled up to the + 5V side by the resistor MR5 and the operation signal from the operation switch 860a whose logic becomes HI is input to the input terminal PA0 of the input port PA of the main control MPU 4100a. Is done. The main control MPU 4100a does not instruct to perform RAM clear to erase information stored in the main control built-in RAM when the logical value of the operation signal from the operation switch 860a input to the input terminal PA0 is HI. to decide.

  On the other hand, when the operation switch 860a is operated, an operation signal that is pulled up to + 12V by the pull-up resistor MR2 and has a logic level HI is input to the base terminal of the transistor MTR0, so that the transistor MTR0 is turned on. The circuit is also turned on. As a result, the operation signal from the operation switch 860a in which the voltage applied to the collector terminal of the transistor MTR0 is pulled down to the ground (GND) side and the logic becomes LOW is input to the input terminal PA0 of the input port PA of the main control MPU 4100a. Is done. The main control MPU 4100a instructs to clear the RAM for erasing the information stored in the main control built-in RAM when the logical value of the operation signal from the operation switch 860a input to the input terminal PA0 is LOW. Judge.

  The operation signal from the operation switch 860a is pulled up to the + 12V side by the pull-up resistor MR2. This is because an operation signal from the operation switch 860 a is input via the payout control board 4110. That is, between the boards of the main control board 4100 and the payout control board 4110, it is higher than the control reference voltage +5 V in order to suppress the influence of noise entering the wiring (harness) that electrically connects the boards. The reliability of the signal is enhanced by using + 12V which is a voltage. Therefore, in the present embodiment, the detection signals from the general prize opening switch 3020, the first start port switch 3022, and the second start port switch 2109 that are directly input to the main control board 4100 are set to + 5V side by the pull-up resistor. While being pulled up, detection signals from the magnetic detection switch 3024, the count switch 2110, the general winning opening switch 3020, and the gate switch 2352, which are input via the panel relay terminal plate 4161 shown in FIG. Since it is not directly input to the input signal, it is pulled up to the + 12V side by a pull-up resistor in the same manner as the operation signal from the operation switch 860a.

[9-5. Power failure monitoring circuit]
As shown in FIG. 21, the main control board 4100 is supplied with two types of voltages of + 12V and + 24V from the power supply board 851 via the payout control board 4110, and + 12V and + 24V are input to the power failure monitoring circuit 4100e. ing. The power failure monitoring circuit 4100e monitors the signs of + 12V and + 24V power failures or momentary power outages, and detects a power outage notice signal as a power outage notice in addition to the main control MPU 4100a when a sign of power outages or momentary power outages is detected. 4110 is output to the payout control MPU 4120a and the peripheral control board 4140. Here, the configuration of the power failure monitoring circuit will be described first, followed by the monitoring of the + 24V power failure or instantaneous power failure, the + 12V power failure or instantaneous power failure, and the output of the power failure warning signal.

[9-5-1. Configuration of power failure monitoring circuit]
As shown in FIG. 25, the power failure monitoring circuit 4100e mainly includes a shunt-type stabilized power supply circuit MIC20, an open collector output type comparator MIC21, a D-type flip-flop MIC22, and transistors MTR20 to MTR23.

  The reference voltage input terminal REF terminal and the cathode terminal K terminal of the shunt-type stabilized power supply circuit MIC20 are electrically connected to the other end of the resistor MR20, one end of which is electrically connected to the + 5V power supply line. + 5V is applied, and the current input to the REF terminal is limited by the resistor MR20. The K terminal outputs a reference voltage Vref that is a comparison reference voltage of the comparator MIC21 (in this embodiment, 2.495 V is set). The K terminal is electrically connected to the other end of the capacitor MC20 whose one end is grounded to the ground (GND), and the reference voltage Vref output from the K terminal is rippled (convolved with the voltage) by the capacitor MC20. AC component) is removed and smoothed. The A terminal, which is the anode terminal of the shunt-type stabilized power supply circuit MIC20, is grounded to the ground (GND).

  The comparator MIC21 includes two voltage comparison circuits, one of which (MIC21A) is used for comparing the monitor voltage V1 of + 24V and the reference voltage Vref, and the other one (MIC21B). , + 12V monitor voltage V2 and reference voltage Vref are used for comparison. The monitoring voltage V1 of + 24V is applied to the third terminal, which is the positive terminal of the MIC 21A, and the reference voltage Vref is applied to the second terminal, which is the negative terminal of the MIC 21A. The monitoring voltage V2 of + 12V is applied to the 5th terminal which is the plus terminal of the MIC 21B, and the reference voltage Vref is applied to the 6th terminal which is the minus terminal of the MIC 21B. These comparison results are input to the D-type flip-flop MIC22. The D-type flip-flop MIC22 includes two D-type flip-flop circuits, one of which (MIC22A) is used in the present embodiment. The Vcc terminal which is a power supply terminal of the comparator MIC21 is electrically connected to the other end of the capacitor MC21 whose one end is grounded (GND), and + 5V applied to the Vcc terminal which is the power supply terminal of the comparator MIC21 is The ripple is removed and smoothed by the capacitor MC21, and the GND terminal which is the ground terminal of the comparator MIC21 is grounded to the ground (GND).

[9-5-2. Monitoring of + 24V power outage or instantaneous power failure]
As described above, the monitoring of the + 24V power failure or instantaneous power failure is performed by the MIC 21A of the comparator MIC21 comparing the + 24V monitoring voltage V1 with the reference voltage Vref. As shown in FIG. 25, the third terminal, which is the positive terminal of the MIC 21A of the comparator MIC 21 to which the + 24V monitoring voltage V1 is applied, Is connected to the ground (GND), the other end of the resistor MR22 is electrically connected and the other ends of the resistors MR21 and MR22, and the other end of the capacitor MC23 is grounded to the ground (GND). Are electrically connected. The + 24V monitoring voltage V1 applied to the third terminal, which is the positive terminal of the MIC21A of the comparator MIC21, is divided by + 24V by the resistance ratio of the resistors MR21 and MR22, and the ripple is removed by the capacitor MC23 and is smoothed. . The values of the resistors MR21 and MR22 are preset to the power failure detection voltage V1pf (in the present embodiment, set to 21.40V) when + 24V has a power failure or a momentary power failure, and the voltage starts dropping from + 24V. The monitoring voltage V1 of + 24V is set to be the same value as the reference voltage Vref.

  The first terminal that is the output terminal of the MIC 21A of the comparator MIC 21 is an open collector output, and one end is electrically connected to the other end of the pull-up resistor MR23 that is electrically connected to the + 5V power supply line. One end is electrically connected to the other end of the capacitor MC24, which is grounded with the ground (GND), and is electrically connected to a PR terminal which is a preset terminal of the D-type flip-flop MIC22. The capacitor MC24 plays a role as a low-pass filter.

  When the + 24V voltage is higher than the power failure detection voltage V1pf, the + 24V monitoring voltage V1 becomes higher than the reference voltage Vref, and the voltage applied to the first terminal which is the output terminal of the MIC 21A of the comparator MIC21 is + 5V by the pull-up resistor MR23. A signal whose logic is HI is input to the PR terminal which is a preset terminal of the D-type flip-flop MIC22.

  On the other hand, when the + 24V voltage is smaller than the power failure detection voltage V1pf, the + 24V monitoring voltage V1 becomes smaller than the reference voltage Vref, and the voltage applied to the first terminal, which is the output terminal of the MIC 21A of the comparator MIC21, is ground (GND). The signal with the logic level LOW is input to the PR terminal which is the preset terminal of the D-type flip-flop MIC22.

[9-5-3. Monitoring of + 12V power failure or instantaneous power failure]
As described above, the + 12V power failure or instantaneous power failure is monitored by the MIC 21B of the comparator MIC21 comparing the + 12V monitor voltage V2 with the reference voltage Vref. As shown in FIG. 25, the fifth terminal, which is the plus terminal of the MIC 21B of the comparator MIC 21 to which the monitoring voltage V2 of +12 V is applied, has one end connected to the +12 V power supply line and the other end of the resistor MR24. Are connected to the other end of the resistor MR25, and the other ends of the resistors MR24 and MR25, and the other end of the capacitor MC25 is connected to the ground (GND). Are electrically connected. The + 12V monitoring voltage V2 applied to the fifth terminal, which is the positive terminal of the MIC21B of the comparator MIC21, is divided by + 12V by the resistance ratio of the resistors MR24 and MR25, and the ripple is removed by the capacitor MC25 and is smoothed. . The values of the resistors MR24 and MR25 are preset to the power failure detection voltage V2pf (in this embodiment, set to 10.47V) when + 12V has a power failure or a momentary power failure and the voltage starts to drop from + 12V. The monitoring voltage V2 of + 12V is set to be the same value as the reference voltage Vref.

  The 7th terminal, which is the output terminal of the MIC21B of the comparator MIC21, is an open collector output and is electrically connected to the 1st terminal, which is the output terminal of the MIC21A, so that one end is electrically connected to the + 5V power line. The D-type flip-flop MIC22 is preset by being electrically connected to the other end of the pull-up resistor MR23 that is electrically connected, and one end being electrically connected to the other end of the capacitor MC24 that is grounded to the ground (GND). The terminal is electrically connected to the PR terminal. As described above, the capacitor MC24 plays a role as a low-pass filter.

  When the voltage of + 12V is higher than the power failure detection voltage V2pf, the monitoring voltage V2 of + 12V becomes higher than the reference voltage Vref, and the voltage applied to the seventh terminal which is the output terminal of the MIC21B of the comparator MIC21 is + 5V by the pull-up resistor MR23. A signal whose logic is HI is input to the PR terminal which is a preset terminal of the D-type flip-flop MIC22.

  On the other hand, when the voltage of + 12V is smaller than the power failure detection voltage V2pf, the monitoring voltage V2 of + 12V becomes smaller than the reference voltage Vref, and the voltage applied to the seventh terminal which is the output terminal of the MIC21B of the comparator MIC21 is ground (GND). The signal with the logic level LOW is input to the PR terminal which is the preset terminal of the D-type flip-flop MIC22.

[9-5-4. Output of power failure warning signal]
The D type flip-flop MIC22 stores the value (logic) of the signal input to the 1D terminal, which is the D input terminal, according to the change in the edge of the clock signal input to the 1CK terminal, which is the clock input terminal. (Logic) is output from the 1Q terminal that is the output terminal, and a value obtained by inverting the stored value (logic) is output from the negative logic 1Q terminal that is the output terminal. In addition, when a signal whose logic is LOW is input to the CLR terminal which is the clear terminal, the D-type flip-flop MIC22 releases the latch state and changes the logic of the signal input to the PR terminal which is the preset terminal. The inverted signal is output from the 1Q terminal that is the output terminal (at this time, the same logic as that of the signal that is inverted from the logic of the signal output from 1Q, that is, the signal that is input to the PR terminal that is the preset terminal) On the other hand, when a signal whose logic is HI is input to the CLR terminal which is the clear terminal, the latch state is set. The D-type flip-flop MIC22 has a logic LOW at the preset terminal PR when a signal whose logic is HI is input to the CLR terminal which is a clear terminal and the latch state is set. When the signal is input, the state that the signal whose logic is HI is output from the 1Q terminal which is the output terminal is maintained (the signal obtained by inverting the logic of the signal output from 1Q is negative logic) The state of outputting from the 1Q terminal is maintained).

  In the D-type flip-flop MIC22, in this embodiment, the 1D terminal that is the D input terminal and the 1CK terminal that is the clock input terminal are grounded to the ground (GND). The circuit configuration is such that there is no change in the edge of the input clock signal, and the value (logic) of the signal input to the 1D terminal which is the D input terminal is stored and is not output from the 1Q terminal which is the output terminal. ing. As described above, the D-type flip-flop MIC22 has a signal from the first terminal that is the output terminal of the MIC21A of the comparator MIC21 that monitors the power failure or instantaneous power failure of + 24V, and the power failure of + 12V. Alternatively, a signal from the 7th terminal that is the output terminal of the MIC 21B of the comparator MIC 21 that monitors the instantaneous power failure is input, and a signal is output from the 1Q terminal that is the output terminal based on these signals. The Vcc terminal, which is a power supply terminal, is electrically connected to the other end of the capacitor MC22 whose one end is grounded (GND), and is applied to the Vcc terminal, which is the power supply terminal of the D-type flip-flop MIC22. + 5V is smoothed by removing the ripple by the capacitor MC22, the GND terminal as the ground terminal is grounded to the ground (GND), and the negative logic 1Q terminal that inverts the logic of the 1Q terminal as the output terminal is electrically connected to the outside. In an unconnected state.

  In the present embodiment, in the D-type flip-flop MIC22, the power failure clear signal from the main control MPU 4100a is input to the CLR terminal which is a clear terminal via the main control output circuit 4100ca with a reset function. This power failure clear signal is output after a predetermined time has elapsed after the start of output in the main control-side power-on process described later performed by the main control MPU 4100a. Since the CLR terminal is a negative logic input, the power failure clear signal from the main control MPU 4100a is input to the CLR terminal with the logic being LOW via the main control output circuit 4100ca with a reset function. When the power failure clear signal is input to the CLR terminal, the D-type flip-flop MIC22 cancels the latch state. At this time, the logic input to the PR terminal which is a preset terminal is inverted and the output terminal Is output from the 1Q terminal.

  On the other hand, when the output of the power failure clear signal from the main control MPU 4100a is stopped, the logic becomes HI via the main control output circuit 4100ca with reset function and is input to the CLR terminal. When the power failure clear signal is not input to the CLR terminal, the D-type flip-flop MIC22 sets the latch state, and latches the state where the logic is LOW at the PR terminal.

  The 1Q terminal that is the output terminal of the D-type flip-flop MIC22 is electrically connected to the input terminal PA1 of the input port PA of the main control MPU 4100a via the main control input circuit 4100b, and is the output terminal of the D-type flip-flop MIC22. A signal output from the 1Q terminal is input to the input terminal PA1 of the input port PA of the main control MPU 4100a as a power failure warning signal. The 1Q terminal that is the output terminal of the D-type flip-flop MIC22 is electrically connected to the main control output circuit 4100cb having no reset function, and resets the signal output from the 1Q terminal that is the output terminal of the D-type flip-flop MIC22. The functionless main control output circuit 4100cb outputs a payout blackout notice signal to the payout control board 4110 and also outputs to the peripheral control board 4140 as a peripheral blackout notice signal.

  The main control input circuit 4100b that electrically connects the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, and the input terminal PA1 of the input port PA of the main control MPU 4100a has a D-type flip-flop as shown in FIG. The 1Q terminal, which is the output terminal of the MIC 22, is electrically connected to the other end of the resistor MR26, one end of which is electrically connected to the + 5V power supply line, and electrically connected to the base terminal of the transistor MTR20 via the resistor MR27. It is connected. In addition to being electrically connected to the resistor MR27, one end of the transistor MTR20 is electrically connected to the other end of the resistor MR28 that is grounded to the ground (GND). The emitter terminal of the transistor MTR20 is grounded to the ground (GND), and the collector terminal of the transistor MTR20 is electrically connected to the other end of the resistor MR29, one end of which is electrically connected to the + 5V power supply line, and a non-inverting buffer. Main control via ICMIC 23 (non-inverted buffer ICMIC 23 includes eight non-inverted buffer circuits, and the signal waveform input to one (MIC 23A) is shaped and output without being inverted). The MPU 4100a is electrically connected to the input terminal PA1 of the input port PA.

  The circuit composed of the resistors MR27 and MR28 and the transistor MTR20 is a switch circuit that is turned ON / OFF by a signal output from the 1Q terminal that is the output terminal of the D-type flip-flop MIC22.

  When the logic of the signal output from the 1Q terminal which is the output terminal of the D-type flip-flop MIC22 is LOW, the voltage applied to the base terminal of the transistor MTR20 is pulled down to the ground (GND) side, and the transistor MTR20 is turned OFF. The switch circuit is also turned off. On the other hand, when the logic of the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, is HI, the voltage applied to the base terminal of the transistor MTR20 is raised to the + 5V side, and the transistor MTR20 is turned on. The switch circuit is also turned on.

  When both the condition that the voltage of + 24V is larger than the power failure detection voltage V1pf and the condition that the voltage of + 12V is larger than the power failure detection voltage V2pf are satisfied, the signal whose logic is HI is preset in the D-type flip-flop MIC22. Since the signal is output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, the logic becomes LOW and is input to the base terminal of the transistor MTR20. Turn off. As a result, the voltage applied to the collector terminal of the transistor MTR20 is pulled up to + 5V by the resistor MR29, and the power failure warning signal whose logic becomes HI via the non-inverting buffer ICMIC23 is input to the input port PA of the input port PA of the main control MPU4100a Input to PA1.

  On the other hand, when either one of the condition that the voltage of + 24V is smaller than the power failure detection voltage V1pf and the condition that the voltage of + 12V is smaller than the power failure detection voltage V2pf is satisfied, the signal whose logic is LOW is D Since the signal is input to the PR terminal which is the preset terminal of the type flip-flop MIC22, the signal output from the 1Q terminal which is the output terminal of the D-type flip-flop MIC22 becomes the logic HI and is input to the base terminal of the transistor MTR20. As a result, the transistor MTR20 is turned ON. Thereby, the voltage applied to the collector terminal of the transistor MTR20 is pulled down to the ground (GND) side, and the power failure warning signal whose logic becomes LOW via the non-inverting buffer ICMIC23 becomes the input terminal of the input port PA of the main control MPU 4100a. Input to PA1.

  Further, as shown in FIG. 25, the main control output circuit 4100cb without a reset function that outputs a signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, to the payout control board 4110 as a payout blackout signal is opened. The circuit is configured as a collector output type, and the 1Q terminal which is the output terminal of the D-type flip-flop MIC22 is electrically connected to the resistor MR26 of the main control input circuit 4100b described above, and the transistor MTR21 of the previous stage is connected via the resistor MR30. It is electrically connected to the base terminal. In addition to being electrically connected to the resistor MR30, one end of the base terminal of the transistor MTR21 at the previous stage is electrically connected to the other end of the resistor MR31 that is grounded to the ground (GND). The emitter terminal of the front-stage transistor MTR21 is grounded to the ground (GND), and the collector terminal of the front-stage transistor MTR21 is electrically connected to the other end of the resistor MR32 whose one end is electrically connected to the + 5V power supply line. At the same time, it is electrically connected to the base terminal of the subsequent transistor MTR22 via a resistor MR33. In addition to being electrically connected to the resistor MR33, one end of the base terminal of the transistor MTR22 at the subsequent stage is electrically connected to the other end of the resistor MR34 that is grounded to the ground (GND). The emitter terminal of the rear-stage transistor MTR22 is grounded to the ground (GND), and the collector terminal of the rear-stage transistor MTR22 is electrically connected to the other end of the capacitor MC26 whose one end is grounded to the ground (GND). It is electrically connected to the payout control board 4110 via (harness). When the collector terminal of the subsequent transistor MTR22 is electrically connected to the payout control board 4110 via a wiring (harness), the payout control input of the payout control unit 4120 shown in FIG. In the circuit 4120b, one end of the circuit 4120b is electrically connected to the other end of a pull-up resistor (not shown) that is electrically connected to the + 12V power line, and is electrically connected to an input terminal of a predetermined input port of the payout control MPU 4120a shown in FIG. Connected.

  A circuit composed of the resistors MR30 and MR31 and the preceding transistor MTR21 is a preceding switch circuit, and a circuit composed of the resistors MR33 and MR34 and the succeeding transistor MTR22 is a succeeding switch circuit, and is a D-type flip-flop. It is turned ON / OFF by a signal output from the 1Q terminal which is an output terminal of the MIC 22.

  When the logic of the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, is LOW, the voltage applied to the base terminal of the previous transistor MTR21 is pulled down to the ground (GND) side, and the previous transistor The MTR 21 is turned OFF and the preceding switch circuit is also turned OFF, and the voltage applied to the collector terminal of the preceding transistor MTR 21, which is the voltage applied to the base terminal of the succeeding transistor MTR 22, is raised to the + 5V side by the resistor MR 32. As a result, the rear-stage transistor MTR22 is turned on, and the rear-stage switch circuit is also turned on. On the other hand, when the logic of the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, is HI, the voltage applied to the base terminal of the transistor MTR21 is raised to the + 5V side and the transistor MTR21 is turned ON. The front-stage switch circuit is also turned on, and the voltage applied to the collector terminal of the front-stage transistor MTR21, which is the voltage applied to the base terminal of the rear-stage transistor MTR22, is lowered to the ground (GND) side, thereby The transistor MTR22 is turned off, and the subsequent switch circuit is also turned off.

  When both the condition that the voltage of + 24V is larger than the power failure detection voltage V1pf and the condition that the voltage of + 12V is larger than the power failure detection voltage V2pf are satisfied, the signal whose logic is HI is preset in the D-type flip-flop MIC22. Because the signal is input to the PR terminal, which is the terminal, the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, becomes logic LOW and is input to the base terminal of the transistor MTR21 in the previous stage. The transistor MTR21 is turned off. As a result, the voltage applied to the collector terminal of the former-stage transistor MTR21 is pulled up to the + 5V side by the resistor MR32 and applied to the base terminal of the latter-stage transistor MTR22, thereby turning on the latter-stage transistor MTR22. As a result, the voltage applied to the collector terminal of the subsequent transistor MTR22 is pulled down to the ground (GND) side in the payout control board 4110 via the wiring (harness), so that the payout power failure warning signal whose logic is LOW is issued. Input to the control board 4110.

  On the other hand, when either one of the condition that the voltage of + 24V is smaller than the power failure detection voltage V1pf and the condition that the voltage of + 12V is smaller than the power failure detection voltage V2pf is satisfied, the signal whose logic is LOW is D Since the signal is input to the PR terminal, which is the preset terminal of the type flip-flop MIC22, the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, becomes logic HI and becomes the base terminal of the transistor MTR21 in the previous stage. As a result of the input, the previous-stage transistor MTR21 is turned ON. As a result, the voltage applied to the collector terminal of the preceding transistor MTR21 is pulled down to the ground (GND) and applied to the base terminal of the succeeding transistor MTR22, thereby turning off the succeeding transistor MTR22. As a result, the voltage applied to the collector terminal of the transistor MTR22 in the subsequent stage is pulled up to + 12V side by the pull-up resistor in the payout control input circuit 4120b of the payout control unit 4120 in the payout control board 4110 via the wiring (harness). A payout power failure notice signal whose logic is HI is input to the payout control board 4110.

  Further, as shown in FIG. 25, the main control output circuit 4100cb having no reset function that outputs a signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, to the peripheral control board 4140 as a peripheral power failure warning signal is opened. The circuit is configured as a collector output type, and the 1Q terminal which is the output terminal of the D-type flip-flop MIC22 is electrically connected to the resistor MR26 of the main control input circuit 4100b described above, and the base terminal of the transistor MTR23 via the resistor MR35. And are electrically connected. In addition to being electrically connected to the resistor MR35, one end of the transistor MTR23 is electrically connected to the other end of the resistor MR36 that is grounded to the ground (GND). The emitter terminal of the transistor MTR23 is grounded to the ground (GND), and the collector terminal of the transistor MTR23 is electrically connected to the peripheral control board 4140 via a wiring (harness). When the collector terminal of the transistor MTR23 is electrically connected to the peripheral control board 4140 via a wiring (harness), a peripheral control input circuit (not shown) of the peripheral control unit 4150 in the peripheral control board 4140 shown in FIG. In FIG. 17, one end is electrically connected to the other end of a pull-up resistor (not shown) that is electrically connected to the + 12V power line, and is electrically connected to an input terminal of a predetermined input port of the peripheral control MPU 4150a shown in FIG. Connected.

  The circuit composed of the resistors MR35 and MR36 and the transistor MTR23 is a switch circuit that is turned ON / OFF by a signal output from the 1Q terminal that is the output terminal of the D-type flip-flop MIC22.

  When the logic of the signal output from the 1Q terminal which is the output terminal of the D-type flip-flop MIC22 is LOW, the voltage applied to the base terminal of the transistor MTR23 is pulled down to the ground (GND) side, and the transistor MTR23 is turned OFF. The switch circuit is also turned off. On the other hand, when the logic of the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, is HI, the voltage applied to the base terminal of the transistor MTR23 is raised to the + 5V side, and the transistor MTR23 is turned on. The switch circuit is also turned on.

  When both the condition that the voltage of + 24V is larger than the power failure detection voltage V1pf and the condition that the voltage of + 12V is larger than the power failure detection voltage V2pf are satisfied, the signal whose logic is HI is preset in the D-type flip-flop MIC22. Since the signal is output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, the logic becomes LOW and is input to the base terminal of the transistor MTR23. Turn off. As a result, the voltage applied to the collector terminal of the transistor MTR23 is pulled up to + 12V by the pull-up resistor in the payout control input circuit of the peripheral control unit 4150 in the peripheral control board 4140 via the wiring (harness), so that the logic becomes HI. The peripheral power failure warning signal is input to the peripheral control board 4140.

  On the other hand, when either one of the condition that the voltage of + 24V is smaller than the power failure detection voltage V1pf and the condition that the voltage of + 12V is smaller than the power failure detection voltage V2pf is satisfied, the signal whose logic is LOW is D Since the signal is input to the PR terminal that is the preset terminal of the type flip-flop MIC22, the signal output from the 1Q terminal that is the output terminal of the D-type flip-flop MIC22 becomes the logic HI and is input to the base terminal of the transistor MTR23. As a result, the transistor MTR23 is turned ON. As a result, the peripheral power failure notice signal whose logic is LOW is generated when the voltage applied to the collector terminal of the transistor MTR23 is pulled down to the ground (GND) side in the peripheral control board 4140 via the wiring (harness). 4140 is input.

  As described above, the main control input circuit 4100b that transmits the signal output from the 1Q terminal that is the output terminal of the D-type flip-flop MIC22 to the main control MPU 4100a as a power failure warning signal, and the 1Q terminal that is the output terminal of the D-type flip-flop MIC22. The main control output circuit 4100cb without reset function for outputting the signal output from the peripheral control board 4140 to the peripheral control board 4140 has one transistor, and the power failure warning signal input to the main control MPU 4100a and the peripheral While the logic of the peripheral power failure warning signal input to the control board 4140 is the same logic, the signal output from the 1Q terminal which is the output terminal of the D-type flip-flop MIC22 is sent out to the payout control board 4110 No reset function to output as a power failure warning signal The control circuit 4100cb has two transistors, a front stage and a rear stage, and the logic of the payout power failure warning signal is the logic of the power failure warning signal input to the main control MPU 4100a and the peripheral power failure warning signal input to the peripheral control board 4140. The logic of the signal is inverted and is different from the logic of the power failure warning signal and the logic of the peripheral power failure warning signal.

  The collector terminal of the transistor MTR20 of the main control input circuit 4100b is electrically connected to the other end of the resistor MR29, one end of which is electrically connected to the + 5V power supply line, and the main control MPU 4100a via the non-inverting buffer ICMIC23. The collector terminal of the transistor MTR22 at the subsequent stage of the main control output circuit 4100cb without reset function is electrically connected to the input terminal PA1 of the input port PA of the payout control board via the wiring (harness). In the payout control input circuit 4120b of the payout control unit 4120 in 4110, one end is electrically connected to the other end of the pull-up resistor electrically connected to the + 12V power supply line, and the main control output circuit 4100cb without reset function is connected. The collector terminal of the transistor MTR23 is Wiring through a (harness), the payout control input circuit of the peripheral control unit 4150 in the peripheral control board 4140, which is a pull-up resistor electrically connected to one end of which is connected + 12V power supply line and electrically. This is because the transistor MTR20 and the main control MPU 4100a of the main control input circuit 4100b are connected to the main control board between the collector terminal of the transistor MTR20 of the main control input circuit 4100b and the input terminal PA1 of the input port PA of the main control MPU 4100a. 4100, the main control board 4100 and the payout control board are used to perform the power outage notice by the logic (ON / OFF signal) of the power outage notice signal using + 5V which is the control reference voltage of the main control MPU 4100a. In order to suppress the influence of noise entering the wiring (harness) electrically connecting between the boards, the main control MPU 4100a, between the boards with 4110 and between the boards with the main control board 4100 and the peripheral control board 4140, Dispensing control MPU 4120a and peripheral control MPU 4150a Is performed blackout notice by the logic of a control reference voltage + 5V is at a higher voltage than the + with 12V power failure warning signal (ON / OFF signal).

[9-6. Various input / output signals to main control MPU]
Next, various input / output signals to the main control MPU 4100a will be described with reference to FIG. The RXA terminal which is a serial data input terminal of the serial input port of the main control MPU 4100a receives serial data from the payout control board 4110 shown in FIG. 14 as a payer serial data reception signal via the main control input circuit 4100b. . On the other hand, the TXA terminal and the TXB terminal, which are serial data output terminals of the serial output port of the main control MPU 4100a, receive the serial data transmitted from the TXA terminal to the payout control board 4110 as a main payout serial data transmission signal and do not have a reset function. A main payment serial data transmission signal is transmitted from the main control output circuit 4100cb having no reset function to the payout control board 4110 and transmitted from the TXB terminal to the peripheral control board 4140 shown in FIG. The peripheral serial data transmission signal is transmitted to the main control output circuit 4100cb without reset function, and the main peripheral serial data transmission signal is transmitted from the main control output circuit 4100cb without reset function to the peripheral control board 4140.

  In addition to the above-described operation signal (RAM clear signal) being input to each input terminal of a predetermined input port of the main control MPU 4100a, for example, a payout for notifying the completion of normal reception of the above-described main payment serial data reception signal A payer ACK signal from the control board 4110 is input via the main control input circuit 4100b, or detection signals from various switches such as the first start port switch 3022 shown in FIG. 14 are input via the main control input circuit 4100b. Each is entered.

  On the other hand, from each output terminal of a predetermined output port of the main control MPU 4100a, for example, a main payment ACK signal that indicates the completion of normal reception of the above-described payment serial data reception signal is output to the main control output circuit 4100ca with reset function. Then, a main payout ACK signal is output from the main control output circuit 4100ca with reset function to the payout control board 4110, or a drive signal is sent to the main control output circuit 4100ca with reset function for the start port solenoid 2105 shown in FIG. To output a drive signal from the main control output circuit 4100ca with reset function to the start port solenoid 2105 via the main control solenoid drive circuit 4100d, or various displays such as the upper special symbol display 1185 shown in FIG. Drive signal to the main control output circuit 4100ca with reset function. Is output to the various display devices from the main control output circuit 4100ca with reset function, or various information about the game (game information) is output to the main control output circuit 4100ca with reset function to output the main signal with the reset function. Various information (game information) related to the game is output to the payout control board 4110 from the control output circuit 4100ca.

[9-7. Interface circuit for communication between main control board and peripheral control board]
Next, a communication interface circuit between the main control board 4100 and the peripheral control board 4140 will be described with reference to FIG. The main control board 4100 is supplied with + 12V from the power supply board 851 shown in FIG. 21 via the payout control board 4110, and the + 5V creation circuit 4100g creates + 5V that is the control reference voltage of the main control MPU 4100a from this + 12V. ing. The main peripheral serial data transmission signal transmitted from the main control board 4100 to the peripheral control board 4140 is affected by noise entering the wiring (harness) that electrically connects the main control board 4100 and the peripheral control board 4140. Therefore, the reliability is enhanced by using + 12V, which is a voltage higher than + 5V, which is the control reference voltage of the main control MPU 4100a.

  Specifically, the main control board 4100 causes the main control output circuit 4100cb without a reset function to function as a communication interface circuit, and the communication interface circuit mainly includes a resistor MR50, resistors MR51 and MR52, and a transistor MTR50. Has been. On the other hand, the peripheral control board 4140 includes a diode AD10, an electrolytic capacitor AC10 (capacitance: 47 μF in this embodiment), and a photocoupler AIC10 (infrared LED and photo IC) as a communication interface circuit. It is mainly configured).

  + 12V supplied from the power supply board 851 is applied to the anode terminal of the diode MD50 of the main control board 4100 through the payout control board 4110, and the minus terminal is grounded to the ground (GND) to the cathode terminal of the diode MD50. The electrolytic capacitor MC50 (capacitance: 220 microfarad (μF) in this embodiment) is electrically connected to the plus terminal. The cathode terminal of the diode MD50 is electrically connected to the plus terminal of the electrolytic capacitor MC50, and is electrically connected to the anode terminal (first terminal) of the photocoupler AIC10 in the peripheral control board 4140 via wiring (harness). It is connected to the. Thereby, for example, when power from the power supply board 851 is not supplied to the main control board 4100 via the payout control board 4110 due to a power failure or a momentary power failure, the charge charged in the electrolytic capacitor MC50 is reduced. + 12V can be continuously applied from the main control board 4100 to the anode terminal of the photocoupler AIC 10 in the peripheral control board 4140.

  In this way, the VDD terminal, which is the power supply terminal of the main control MPU 4100a, is charged to the electrolytic capacitor MC2 (capacitance: 470 μF in the present embodiment) shown in FIG. 24 when a power failure or a momentary power failure occurs. Therefore, the main peripheral serial transmission port 4100ae built in the main control MPU 4100a serially manages at least the command set by the main control CPU core 4100aa in the transmission buffer register 4100aeb. The unit 4100aec can transfer the data to the transmission shift register 41aea and complete the transmission from the transmission shift register 4100aea as main peripheral serial data.

  The main peripheral serial data transmission signal transmitted from the main control board 4100 to the peripheral control board 4140 is connected to the wiring (harness) that electrically connects the main control board 4100 and the peripheral control board 4140 as described above. In order to suppress the influence of intruding noise, the reliability is enhanced by transmitting + 12V, which is a voltage higher than + 5V, which is the control reference voltage of the main control MPU 4100a.

  Therefore, in the present embodiment, when a power failure or a momentary power failure occurs, the charge charged in the electrolytic capacitor MC50 is applied to the anode terminal of the photocoupler AIC10 in the peripheral control board 4140 from the main control board 4100 as + 12V. Therefore, the main peripheral serial transmission port 4100ae built in the main control MPU 4100a transfers the command set by the main control CPU core 4100aa in the transmission buffer register 4100aeb to the transmission shift register 41aea by the serial management unit 4100aec and transmits it. When transmission is performed from the shift register 4100aea as main peripheral serial data, a main peripheral serial data transmission signal having a logic level of HI can be transmitted from the collector terminal of the transistor MTR50 by + 12V. .

  In this embodiment, the storage capacity of the transmission buffer register 4100aeb of the main peripheral serial transmission port 4100ae built in the main control MPU 4100a has 32 bytes, and one packet is composed of 3 bytes of data. Therefore, data for 10 packets at the maximum is stored in the transmission buffer register 4100aeb. In this embodiment, the transfer bit rate of the main peripheral serial data transmitted from the main control MPU 4100a is set to 19200 bps.

  The cathode terminal (third terminal) of the photocoupler AIC10 is electrically connected to the collector terminal of the transistor MTR50 of the main control board 4100 through the resistor AR10 and its wiring (harness). The resistor AR10 on the peripheral control board 4140 is a limiting resistor for limiting the current flowing through the built-in infrared LED of the photocoupler AIC10.

  The TXB terminal that outputs the main serial data transmission signal from the main control MPU 4100a shown in FIG. 24 is electrically connected to the other end of the resistor MR50 that is electrically connected to the + 5V power supply line, and has the resistor MR51. And is electrically connected to the base terminal of the transistor MTR50. In addition to being electrically connected to the resistor MR51, one end of the transistor MTR50 is electrically connected to the other end of the resistor MR52 that is grounded to the ground (GND). The emitter terminal of the transistor MTR50 is grounded with the ground (GND).

  The circuit composed of the resistors MR51 and MR52 and the transistor MTR50 is a switch circuit. When the logic of the main serial data transmission signal is HI, the voltage applied to the base terminal of the transistor MTR50 is on the ground (GND) side. As a result, the transistor MTR50 is turned off, and the switch circuit is also turned off. As a result, the forward current does not flow to the built-in infrared LED of the photocoupler AIC10 on the peripheral control board 4140, so the photocoupler AIC10 is turned off. On the other hand, when the logic of the main serial data transmission signal is LOW, the voltage applied to the base terminal of the transistor MTR50 is pulled up to + 5V by the resistor MR50, turning on the transistor MTR50 and turning on the switch circuit. . As a result, a forward current flows through the built-in infrared LED of the photocoupler AIC10 on the peripheral control board 4140, so that the photocoupler AIC10 is turned on.

  + 5V supplied from the power supply board 851 is applied to the anode terminal of the diode AD10 in the peripheral control board 4140 via the frame peripheral relay terminal board 868, and the cathode terminal of the diode AD10 is connected to the ground (GND). It is electrically connected to the plus terminal of the electrolytic capacitor AC10 to be grounded. In addition to being electrically connected to the positive terminal of the electrolytic capacitor AC10, the cathode terminal of the diode AD10 is also electrically connected to the Vcc terminal (No. 6 terminal) that is the power supply terminal of the photocoupler AIC10. The emitter terminal (No. 4 terminal) of the photocoupler AIC10 is grounded to the ground (GND), and the collector terminal (No.5 terminal) of the photocoupler AIC10 is a pull-up resistor electrically connected to the plus terminal of the electrolytic capacitor AC10. It is pulled up to + 5V by AR11 and is electrically connected to the input terminal of the serial I / O port for the main control board of the peripheral control MPU 4150a. When the photocoupler AIC10 is turned ON / OFF, the logic of the signal output from the collector terminal of the photocoupler AIC10 changes, and the signal is used as the main peripheral serial data transmission signal as the serial I / O port for the main control board of the peripheral control MPU4150a. Is input to the input terminal.

  Thereby, as described above, for example, when a power failure or a momentary power failure occurs, +5 V supplied from the power supply board 851 is not supplied to the peripheral control board 4140 via the frame peripheral relay terminal board 868. The electric charge charged in the electrolytic capacitor AC10 can be continuously applied to the Vcc terminal of the photocoupler AIC10 as + 5V. When electric power or a momentary power failure occurs, + 5V from the electrolytic capacitor AC10 is applied, so that the main peripheral serial data transmission signal transmitted from the TXB terminal of the main control MPU 4100a to the peripheral control board 4140 is sent to the main control MPU 4100a. The data set in the transmission buffer register 4100aeb of the built-in main circumference serial transmission port 4100ae can be completed, and the main circumference serial data transmission signal in the middle of transmission, that is, the main circumference serial data is cut off. The peripheral control board 4140 reliably receives the signal without being lost or missing.

  When the logic of the main peripheral serial data transmission signal transmitted from the TXB terminal of the main control MPU 4100a to the peripheral control board 4140 is HI, the voltage applied to the base terminal of the transistor MTR50 is pulled down to the ground (GND) side and the transistor Since the photocoupler AIC10 is turned off when the MTR50 is turned off, the voltage applied to the collector terminal of the photocoupler AIC10 is pulled up to the + 5V side by the pull-up resistor AR11, and the logic becomes HI. While the serial data transmission signal is input to the input terminal of the serial I / O port for the main control board of the peripheral control MPU 4150a, the logic of the main peripheral serial data transmission signal transmitted from the TXB terminal of the main control MPU 4100a to the peripheral control board 4140 When is LOW Is applied to the collector terminal of the photocoupler AIC10 because the voltage applied to the base terminal of the transistor MTR50 is pulled up to + 5V by the resistor MR50 and the transistor MTR50 is turned on so that the photocoupler AIC10 is turned on. The main peripheral serial data transmission signal whose logic is LOW by the pulled voltage being pulled down to the ground (GND) side is input to the input terminal of the main control board serial I / O port of the peripheral control MPU 4150a. Thus, the logic of the main circumference serial data transmission signal output from the collector terminal of the photocoupler AIC10 is the same as the logic of the main circumference serial data transmission signal transmitted from the TXB terminal of the main control MPU 4100a to the peripheral control board 4140. It is the logic of

  As described above, in this embodiment, the + 5V power supply line to which + 5V that is the control reference voltage of the main control MPU 4100a is applied, and the + 12V power supply line to which + 12V that is the communication voltage applied via the diode MD50 is applied. Measures are taken when a power failure or a momentary power failure occurs and the control reference voltage and the communication voltage drop. That is, for the main peripheral serial transmission port 4100ae built in the main control MPU 4100a, a + 5V power supply line, a positive terminal of the electrolytic capacitor MC2 using the electrolytic capacitor MC2 of the main control filter circuit 4100h as a first auxiliary power supply, Are electrically connected in parallel, so that even if a power failure or a momentary power failure occurs and the control reference voltage applied from the + 5V power supply line decreases, the electrolytic capacitor of the main control filter circuit 4100h as the first auxiliary power supply By applying the control reference voltage from the plus terminal of MC2, the state in which the control reference voltage is applied can be maintained, and the resistor MR50, the resistors MR51 and MR52, and the transistor MTR50 are configured. Main function without reset function to function as a communication interface circuit For the output circuit 4100cb, + 12V applied to the + 12V power supply line is applied as a communication voltage to the anode terminal of the diode MD50, and the positive terminal of the cathode terminal of the diode MD50 and the electrolytic capacitor MC50 as the second auxiliary power supply. Even if a power failure or a momentary power failure occurs and the communication voltage applied from the + 12V power supply line via the diode MD50 is reduced by the terminals being electrically connected in parallel, the second auxiliary power supply is provided. By applying the communication voltage from the positive terminal of the electrolytic capacitor MC50, the state where the communication voltage is applied can be maintained. As a result, it is possible to prevent the command being transmitted from the main control board 4100 to the peripheral control board 4140 from being broken, and to prevent omission of the command, so that the peripheral control board 4140 reliably receives the command being transmitted. can do. Therefore, it is possible to eliminate the missed command immediately after the occurrence of a power failure or during a momentary power failure.

  A plurality of commands set in the transmission buffer register 4100aeb of the main peripheral serial transmission port 4100ae built in the main control MPU 4100a are all composed of a resistor MR50, resistors MR51 and MR52, and a transistor MTR50 as main peripheral serial data. 470 μF is set as the capacitance of the electrolytic capacitor MC2 of the main control filter circuit 4100h so that the transmission to the peripheral control board 4140 can be completed via the main control output circuit 4100cb having no reset function that functions as a communication interface circuit. 220 μF is set as the capacitance of the electrolytic capacitor MC50. As a result, even if a power failure or a momentary power failure occurs during transmission from the main control board 4100 to the peripheral control board 4140, a reset that causes all of the commands set in the transmission buffer register 4100aeb to function as an interface circuit as main peripheral serial data Since the transmission to the peripheral control board 4140 can be completed via the non-functional main control output circuit 4100cb, the peripheral control board 4140 can omit a plurality of commands set in the transmission buffer register 4100aeb without missing them. And can be received reliably.

[10. Dispensing control board circuit]
Next, the circuit and the like of the payout control board 4110 shown in FIG. 15 will be described with reference to FIGS. 27 is a circuit diagram showing a circuit and the like of the payout control unit, FIG. 28 is a circuit diagram showing a payout control input circuit, FIG. 29 is a circuit diagram showing a continuation of FIG. 28, and FIG. FIG. 31 is a circuit diagram showing a CR unit input / output circuit. FIG. 32 is an input / output diagram showing various input / output signals to / from the main control board and various output signals to an external terminal board. It is. First, the payout control filter circuit will be described, and then the payout control circuit, various input / output signals with the main control board, and various output signals to the external terminal board will be described.

[10-1. Dispensing control filter circuit]
As shown in FIG. 27, the payout control filter circuit 4110a mainly includes a payout control three-terminal filter PIC0. This payout control three-terminal filter PIC0 is a T-type filter circuit, and has excellent attenuation characteristics magnetically shielded with ferrite. The first terminal of the payout control three-terminal filter PIC0 is applied with + 5V from the power supply board 851 shown in FIG. 21, and is electrically connected to the other end of the capacitor PC0 whose one end is grounded (GND). Then, + 5V from the power supply board 851 is first smoothed by removing the ripple (the AC component superimposed on the voltage) by the capacitor PC0. The second terminal of the payout control 3-terminal filter PIC0 is grounded to the ground (GND), and the third terminal of the payout control 3-terminal filter PIC0 outputs +5 V from which noise components have been removed.

  The third terminal of the payout control three-terminal filter PIC0 has one end connected to the ground (GND) and the other end of the capacitor PC1 and the electrolytic capacitor PC2 (capacitance: 180 microfarad (μF) in this embodiment). By being electrically connected to each other, the ripple is further removed from the +5 V output from the third terminal of the payout control three-terminal filter PIC0 and smoothed. The smoothed + 5V is applied to a power supply terminal of the payout control system reset PIC1, a VCC terminal that is a power supply terminal of the payout control crystal oscillator PX0, a VDD terminal that is a power supply terminal of the payout control MPU 4120a, and the like. . In addition, when a power failure or a momentary power failure occurs and the power supply from the pachinko island facility is cut off, the charge charged in the electrolytic capacitor PC2 is a power failure or a momentary power failure. It is applied as +5 V over a period of about 7 milliseconds (ms) after the occurrence.

  The VDD terminal of the payout control MPU 4120a is electrically connected to the other end of the capacitor PC3 whose one end is grounded (GND), and + 5V applied to the VDD terminal is smoothed by further removing ripples by the capacitor PC3. ing. The VSS terminal, which is the ground terminal of the payout control MPU 4120a, is grounded to the ground (GND).

  Further, the VDD terminal of the payout control MPU 4120a is electrically connected to the anode terminal of the diode PD0 in addition to being electrically connected to the capacitor PC3. The cathode terminal of the diode PD0 is electrically connected to a VBB terminal that is a power supply terminal of a RAM (payout control built-in RAM) built in the payout control MPU 4120a, and one end of the capacitor PC4 is grounded to the ground (GND). Is electrically connected to the other end. In addition to being electrically connected to the cathode terminal of the diode PD0 and the other end of the capacitor PC4, the VBB terminal of this payout control built-in RAM is connected to the plus of the capacitor BC1 of the power supply board 851 shown in FIG. It is electrically connected to the terminal. That is, +5 V smoothed by removing noise components by the payout control filter circuit 4110a is applied to the VDD terminal of the payout control MPU 4120a, and via the diode PD0, the VBB terminal of the payout control built-in RAM and the capacitor BC1. Are applied to the positive terminal. As a result, as described above, when + 5V created by the + 5V power generation circuit 855db of the power generation circuit 855d in the power supply board 851 shown in FIG. Since the discharged charge is supplied as the payout VBB to the payout control board 4110, the current is prevented from flowing to the VDD terminal of the payout control MPU 4120a by the diode PD0 and the payout control MPU4120a does not operate. The stored contents are held by applying the pay VBB to the VBB terminal of the built-in RAM.

[10-2. Circuit of payout control unit]
As shown in FIG. 27, the payout control unit 4120 is reset as a peripheral circuit in addition to the payout control MPU 4120a, the payout control input circuit 4120b, the payout control output circuit 4120c, the payout motor drive circuit 4120d, and the CR unit input / output circuit 4120e. The payout control system reset PIC1 that outputs a signal and the payout control crystal oscillator PX0 that outputs a clock signal (in this embodiment, 8 megahertz (MHz)) are mainly configured. Here, the payout control system reset will be described first, followed by the payout control crystal oscillator, the payout control input circuit, the payout motor drive circuit, the CR unit input / output circuit, and various input / output signals to the payout control MPU.

[10-2-1. Payment control system reset]
As shown in FIG. 27, +5 V smoothed by removing the noise component by the payout control filter circuit 4110a is applied to the power supply terminal of the payout control system reset PIC1. The payout control system reset PIC1 resets the payout control MPU 4120a and the payout control output circuit 4120ca with reset function, and has a built-in delay circuit. One end of the delay control terminal of the payout control system reset PIC1 is electrically connected to the other end of the capacitor PC5 grounded to the ground (GND), and the delay time by the delay circuit is set by the capacitance of the capacitor PC5. Be able to. Specifically, the payout control system reset PIC1 outputs a system reset signal from the output terminal after the delay time elapses when + 5V input to the power supply terminal reaches a threshold value (for example, 4.25V).

  The output terminal of the payout control system reset PIC1 is electrically connected to the SRT0 terminal, which is a reset terminal of the payout control MPU 4120a, and the reset terminal of the payout control output circuit 4120ca with reset function. The output terminal is an open collector output type, one end of which is electrically connected to the other end of the pull-up resistor PR1, which is electrically connected to the + 5V power supply line, and one end of which is grounded to the ground (GND). The other end of the PC 6 is electrically connected. The capacitor PC6 plays a role as a low-pass filter. When the voltage input to the power supply terminal is larger than the threshold value, the output terminal is pulled up to + 5V side by the pull-up resistor PR1, and the logic becomes HI. This logic is the SRT0 terminal of the payout control MPU 4120a and the payout control output with reset function. When the voltage inputted to the reset terminal of the circuit 4120ca is smaller than the threshold value, the logic becomes LOW when the voltage inputted to the power supply terminal is smaller than the threshold value. This logic is the SRT0 terminal of the payout control MPU 4120a and Each is input to the reset terminal. Since the SRT0 terminal of the payout control MPU 4120a and the reset terminal of the payout control output circuit 4120ca with reset function are negative logic inputs, respectively, the payout control MPU 4120a and the reset function when the voltage input to the power supply terminal is smaller than the threshold value. The attached payout control output circuit 4120ca is reset. The power supply terminal is electrically connected to the other end of the capacitor PC7 whose one end is grounded (GND), and + 5V input to the power supply terminal is smoothed by removing ripples. The ground terminal is grounded with a grant (GND), and the NC terminal is not electrically connected to the outside.

[10-2-2. Dispensing control crystal oscillator]
As shown in FIG. 27, +5 V smoothed by removing the noise component by the payout control filter circuit 4110a is input to the VCC terminal which is the power supply terminal of the payout control crystal oscillator PX0. The VCC terminal is electrically connected to the other end of the capacitor PC8, one end of which is grounded (GND), and + 5V input to the VCC terminal is further smoothed by removing ripples. In addition to the VCC terminal, the smoothed + 5V is also applied to an OE terminal that is an output enable terminal of the payout control crystal oscillator PX0. The payout control crystal oscillator PX0 outputs an 8 MHz clock signal from the OUT terminal, which is an output terminal, by applying +5 V to its OE terminal.

  The OUT terminal of the payout control crystal oscillator PX0 is electrically connected to the MCLK terminal, which is the clock terminal of the payout control MPU 4120a, and an 8 MHz clock signal is input to the payout control MPU 4120a. Note that the GND terminal, which is the ground terminal of the payout control crystal oscillator PX0, is grounded to the grant (GND).

[10-2-3. Dispensing control input circuit]
The payout control input circuit 4120b receives the payout blackout notice signal from the door frame open switch 618, the main body frame open switch 619 shown in FIG. 15, and the blackout monitor circuit 4100e included in the main control board 4100 shown in FIG. A circuit, a handle relay terminal plate 192 shown in FIG. 15, a circuit to which a detection signal from the full switch 550 is input via the power supply board 851, a circuit to which an operation signal from the operation switch 860a is input, and the like. First, the circuit to which the detection signal from the door frame opening switch is input will be described, then the circuit to which the detection signal from the main body frame opening switch will be input, the circuit to which the payout power failure warning signal from the power failure monitoring circuit will be input, A circuit to which a detection signal from the full switch is input and a circuit to which an operation signal from the operation switch is input will be described. Note that the full switch 550 and various detection switches such as the ball break switch 750, the counting switch 751, and the rotation angle switch 752 shown in FIG. 15 have an output terminal of an open collector output type. Since the circuit configuration to which the detection signal is input is substantially the same, here, a circuit to which the detection signal from the full switch is input will be described.

[10-2-3 (a). Circuit where detection signal from door frame opening switch is input]
The door frame opening switch 618 uses a normally closed type (normally closed (NC)), and the switch is turned on (conducted) with the door frame 5 opened from the main body frame 3 shown in FIG. The switch is turned off (cut) while 5 is closed to the main body frame 3. The second terminal of the door frame opening switch 618 is grounded to the ground (GND), while the first terminal of the door frame opening switch 618 is a pull-up resistor PR20 whose one end is electrically connected to the + 5V power supply line. It is electrically connected to the end and electrically connected to the base terminal of the transistor PTR20 via the resistor PR21. In addition to being electrically connected to the resistor PR21, one end of the transistor PTR20 is electrically connected to the other end of the resistor PR22 that is grounded to the ground (GND). Further, the first terminal of the door frame opening switch 618 is electrically connected to the pull-up resistor PR20, and is also electrically connected to the other end of the capacitor PC20 that is grounded to the ground (GND). . The emitter terminal of the transistor PTR20 is grounded to the ground (GND), and the collector terminal of the transistor PTR20 is electrically connected to the other end of the resistor PR23, one end of which is electrically connected to the + 5V power supply line, and a non-inverting buffer. Dispensing control via ICPIC 20 (non-inverted buffer ICPIC 20 includes eight non-inverted buffer circuits, and the signal waveform input to one (PIC20A) is shaped and output without being inverted). The MPU 4120a is electrically connected to the input terminal PA0 of the input port PA. When the transistor PTR20 is turned ON / OFF, the logic of the signal output from the collector terminal of the transistor PTR20 changes, and the signal is input to the input terminal PA0 of the input port PA of the payout control MPU 4120a as a door opening signal.

  The first terminal of the door frame opening switch 618 is pulled up to the + 5V side by the pull-up resistor PR20 and is electrically connected to the base terminal of the transistor PTR20 through the resistor PR21, and the + 5V side by the pull-up resistor PR20. And is electrically connected to the base terminal of the transistor PTR21 via the resistor PR24. In addition to being electrically connected to the resistor PR24, one end of the transistor PTR21 is electrically connected to the other end of the resistor PR25 that is grounded to the ground (GND). The emitter terminal of the transistor PTR21 is grounded to the ground (GND), and the collector terminal of the transistor PTR21 is electrically connected to the external terminal plate 784 via a wiring (harness). Note that when the collector terminal of the transistor PTR21 is electrically connected to the external terminal plate 784 via a wiring (harness), one end of the external terminal plate 784 is electrically connected to the + 12V power line. It is electrically connected to the other end of the up resistor. When the transistor PTR21 is turned ON / OFF, the logic of the signal output from the collector terminal of the transistor PTR21 changes, and the signal is input to the external terminal plate 784 as the outer end frame door opening information output signal.

  Further, the first terminal of the door frame opening switch 618 is pulled up to the + 5V side by the pull-up resistor PR20 and is electrically connected to the base terminal of the transistor PTR20 through the resistor PR21, and at the + 5V side by the pull-up resistor PR20. To the base terminal of the transistor PTR21 via the resistor PR24, and to the + 5V side by the pull-up resistor PR20 and electrically connected to the base terminal of the transistor PTR22 via the resistor PR26. ing. The base terminal of the transistor PTR22 is electrically connected to the resistor PR26, and one end is electrically connected to the other end of the resistor PR27 that is grounded to the ground (GND). The emitter terminal of the transistor PTR22 is grounded to the ground (GND), and the collector terminal of the transistor PTR22 is electrically connected to the main control board 4100 shown in FIG. 14 via a wiring (harness). When the collector terminal of the transistor PTR22 is electrically connected to the main control board 4100 via wiring (harness), one end of the collector terminal of the main control input circuit 4100b of the main control board 4100 shown in FIG. The other end of a pull-up resistor (not shown) that is electrically connected to the line is electrically connected. When the transistor PTR22 is turned on / off, the logic of the signal output from the collector terminal of the transistor PTR22 changes, and the signal is input to the main control board 4100 as the main frame door opening signal.

  The circuit composed of the pull-up resistor PR20 and the capacitor PC20 is a switch signal generation circuit. When the door frame 5 is opened from the main body frame 3, or when the door frame 5 is closed by the main body frame 3, It is configured as a circuit that also has a function of absorbing voltage fluctuations from the door frame opening switch 618 due to a fluttering phenomenon in which the contacts constituting the door frame opening switch 618 are repeatedly turned on and off for a short time.

  A circuit constituted by resistors PR21 and PR22 and a transistor PTR20, a circuit constituted by resistors PR24 and PR25 and a transistor PTR21, and a circuit constituted by resistors PR26 and PR27 and a transistor PTR22 are a door frame opening switch. This is a switch circuit that is turned ON / OFF by a detection signal from 618.

  In the state where the door frame 5 is opened from the main body frame 3, the door frame opening switch 618 is ON, so that the voltage applied to the base terminal of the transistor PTR20 is pulled down to the ground (GND) side, whereby the transistor PTR20 is The switch circuit is turned off and the switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor PTR20 is pulled up to the + 5V side by the pull-up resistor PR23, and the door opening signal whose logic becomes HI is input to the input terminal PA0 of the input port PA of the payout control MPU4120a. . Further, when the door frame 5 is opened from the main body frame 3, the door frame opening switch 618 is ON, so that the voltage applied to the base terminal of the transistor PTR21 is pulled down to the ground (GND) side, so that the transistor The PTR 21 is turned off and the switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor PTR21 is pulled up to + 12V side by the pull-up resistor of the external terminal board 784 via the wiring (harness), and the outer end frame door opening information output signal whose logic becomes HI. Is input to the external terminal board 784. Further, when the door frame 5 is opened from the main body frame 3, the door frame opening switch 618 is ON, so that the voltage applied to the base terminal of the transistor PTR22 is lowered to the ground (GND) side, thereby causing the transistor The PTR 22 is turned off and the switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor PTR22 is pulled up to the + 12V side by the pull-up resistor of the main control input circuit 4100b of the main control board 4100 via the wiring (harness), and the logic becomes HI. A door opening signal is input to the main control board 4100.

  On the other hand, when the door frame 5 is closed from the main body frame 3, the door frame opening switch 618 is OFF, so that the voltage applied to the base terminal of the transistor PTR20 is pulled up to the + 5V side by the pull-up resistor PR20. Thus, the transistor PTR20 is turned on and the switch circuit is also turned on. As a result, the voltage applied to the collector terminal of the transistor PTR20 is pulled down to the ground (GND) side, and the door opening signal whose logic is LOW is input to the input terminal PA0 of the input port PA of the payout control MPU 4120a. In addition, when the door frame 5 is closed from the main body frame 3, the door frame opening switch 618 is OFF, so that the voltage applied to the base terminal of the transistor PTR21 is pulled up to the + 5V side, thereby turning on the transistor PTR21. The switch circuit is also turned on. As a result, the voltage applied to the collector terminal of the transistor PTR21 is pulled down to the ground (GND) side, and the outer end frame door opening information output signal whose logic is LOW is input to the external terminal plate 784. In addition, when the door frame 5 is closed from the main body frame 3, the door frame opening switch 618 is OFF, so that the voltage applied to the base terminal of the transistor PTR22 is raised to the + 5V side so that the transistor PTR22 is turned ON. The switch circuit is also turned on. As a result, the main frame door opening signal in which the voltage applied to the collector terminal of the transistor PTR22 is pulled down to the ground (GND) side and the logic becomes LOW is input to the main control board 4100.

  In this way, when the door frame 5 is opened from the main body frame 3, the door frame opening switch 618 is turned on so that the door opening signal whose logic is HI is input to the input terminal PA0 of the input port PA of the payout control MPU 4120a. The outer frame door opening information output signal whose logic is HI is input to the external terminal board 784, and the main frame door opening signal whose logic is HI is input to the main control board 4100, while the door When the frame 5 is closed to the main body frame 3, the door frame opening switch 618 is turned OFF, so that the door opening signal whose logic is LOW is input to the input terminal PA0 of the input port PA of the payout control MPU 4120a. Is output to the external terminal board 784, and the main frame door opening signal whose logic is LOW is input to the main control board 4100.

[10-2-3 (b). A circuit to which the detection signal from the body frame opening switch is input]
The body frame opening switch 619 uses a normally closed type (normally closed (NC)), and the switch is turned on (conducted) with the body frame 3 opened from the outer frame 2 shown in FIG. The switch is turned off (cut) while 3 is closed by the outer frame 2. The second terminal of the body frame opening switch 619 is grounded to the ground (GND), while the first terminal of the body frame opening switch 619 is connected to the other end of the pull-up resistor PR28 whose one end is electrically connected to the + 5V power supply line. It is electrically connected to the end and electrically connected to the base terminal of the transistor PTR23 via the resistor PR29. In addition to being electrically connected to the resistor PR29, one end of the transistor PTR23 is electrically connected to the other end of the resistor PR30 that is grounded to the ground (GND). In addition to being electrically connected to the pull-up resistor PR28, the first terminal of the body frame opening switch 619 is also electrically connected to the other end of the capacitor PC21 that is grounded to the ground (GND). . The emitter terminal of the transistor PTR23 is grounded to the ground (GND), the collector terminal of the transistor PTR23 is electrically connected to the collector terminal of the transistor PTR21 described above, and is connected to the external terminal plate 784 via a wiring (harness). Electrically connected. Note that when the collector terminal of the transistor PTR23 is electrically connected to the external terminal plate 784 via a wiring (harness), one end of the external terminal plate 784 is electrically connected to the + 12V power line. It is electrically connected to the other end of the up resistor. When the transistor PTR23 is turned on / off, the logic of the signal output from the collector terminal of the transistor PTR23 changes, and the signal is input to the external terminal plate 784 as the outer end frame door opening information output signal.

  Further, the first terminal of the body frame opening switch 619 is pulled up to + 5V side by the pull-up resistor PR28 and is electrically connected to the base terminal of the transistor PTR23 through the resistor PR29, and also at the + 5V side by the pull-up resistor PR28. And is electrically connected to the base terminal of the transistor PTR24 via the resistor PR31. In addition to being electrically connected to the resistor PR31, one end of the transistor PTR24 is electrically connected to the other end of the resistor PR32 that is grounded to the ground (GND). The emitter terminal of the transistor PTR24 is grounded to the ground (GND), and the collector terminal of the transistor PTR24 is electrically connected to the collector terminal of the transistor PTR22 described above and shown in FIG. 14 via a wiring (harness). The main control board 4100 is electrically connected. Note that when the collector terminal of the transistor PTR 24 is electrically connected to the main control board 4100 via a wiring (harness), one end of the main control input circuit 4100b of the main control board 4100 shown in FIG. The other end of a pull-up resistor (not shown) that is electrically connected to the line is electrically connected. When the transistor PTR24 is turned on / off, the logic of the signal output from the collector terminal of the transistor PTR24 changes, and the signal is input to the main control board 4100 as the main frame door opening signal.

  The circuit composed of the pull-up resistor PR28 and the capacitor PC21 is a switch signal generation circuit, and when the main body frame 3 is opened from the outer frame 2 or when the main body frame 3 is closed by the outer frame 2, The contacts constituting the body frame opening switch 619 are configured as a circuit that also has a function of absorbing fluctuations in voltage from the body frame opening switch 619 due to a fluttering phenomenon in which the contacts that repeatedly turn ON / OFF repeatedly.

  A circuit composed of the resistors PR29 and PR30 and the transistor PTR23 and a circuit composed of the resistors PR31 and PR32 and the transistor PTR24 are switch circuits that are turned on / off by a detection signal from the body frame opening switch 619.

  In the state where the main body frame 3 is opened from the outer frame 2, the main body frame opening switch 619 is ON, so that the voltage applied to the base terminal of the transistor PTR23 is pulled down to the ground (GND) side, whereby the transistor PTR23 is turned on. The switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor PTR23 is pulled up to the + 12V side by the pull-up resistor of the external terminal board 784 via the wiring (harness), and the outer end frame door opening information output signal whose logic becomes HI. Is input to the external terminal board 784. In the state where the main body frame 3 is opened from the outer frame 2, the main body frame opening switch 619 is ON, so that the voltage applied to the base terminal of the transistor PTR 24 is lowered to the ground (GND) side, so that the transistor The PTR 24 is turned off and the switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor PTR24 is pulled up to the + 12V side by the pull-up resistor of the main control input circuit 4100b of the main control board 4100 via the wiring (harness), and the logic becomes HI. A door opening signal is input to the main control board 4100.

  On the other hand, when the main body frame 3 is closed by the outer frame 2, the main body frame opening switch 619 is OFF, so that the voltage applied to the base terminal of the transistor PTR23 is pulled up to the + 5V side by the pull-up resistor PR28. Thus, the transistor PTR23 is turned on, and the switch circuit is also turned on. As a result, the voltage applied to the collector terminal of the transistor PTR23 is pulled down to the ground (GND) side in the external terminal board 784 via the wiring (harness), and the outer frame door opening information output signal whose logic becomes LOW is output. Input to the external terminal board 784. In the state where the main body frame 3 is closed by the outer frame 2, the main body frame opening switch 619 is OFF, so that the voltage applied to the base terminal of the transistor PTR24 is pulled up to the + 5V side by the pull-up resistor PR28. As a result, the transistor PTR24 is turned on, and the switch circuit is also turned on. As a result, the voltage applied to the collector terminal of the transistor PTR 24 is pulled down to the ground (GND) side in the main control board 4100 via the wiring (harness), and the main frame door open signal whose logic is LOW is generated in the main control board. 4100 is input.

  As described above, when the main body frame 3 is released from the outer frame 2, the main body frame opening switch 619 is turned on so that the outer end frame door opening information output signal whose logic is HI is input to the external terminal plate 784. When the main frame door opening signal whose logic is HI is input to the main control board 4100, while the main body frame 3 is closed to the outer frame 2, the main body frame opening switch 619 is turned OFF, Is output to the external terminal board 784, and the main frame door opening signal whose logic is LOW is input to the main control board 4100.

  In the present embodiment, as described above, one or both of the state in which the door frame 5 is closed by the main body frame 3 and the state in which the main body frame 3 is opened from the outer frame 2 are used. Even in this case, since the main frame door opening signal is input to the main control board 4100, the main control MPU 4100a of the main control board 4100 shown in FIG. Although it is not possible to determine whether the door frame 5 is opened from the main body frame 3 or the main body frame 3 is opened from the outer frame 2, the door frame 5 and / or It can be determined that a state in which the player has opened the main body frame 3 does not occur during a normal game, and an outer end frame door opening information output signal is output to the external terminal board 784. This outer edge because it is designed to be entered The door opening information output signal is transmitted to the hall computer via the external terminal board 784, and the hall computer is in a state where the door frame 5 is opened from the main body frame 3 based on the outer frame door opening information output signal. Although it cannot be determined whether or not the main body frame 3 is opened from the outer frame 2, there is a state in which the player does not occur during normal games that the door frame 5 and / or the main body frame 3 are opened. It can be determined that it has occurred.

  In the present embodiment, as described above, the door frame opening switch 618 and the main body frame opening switch 619 are normally closed, so that the door frame opening switch 618 is short-circuited for some reason and the switch is turned on ( Even if the door frame 5 is opened from the main body frame 3 even if it is in a conductive state, the main body frame opening switch 619 is short-circuited for some reason and the switch is turned on (conductive). 3 is released from the outer frame 2. Thus, by adopting a normally closed switch for the door frame opening switch 618 and the main body frame opening switch 619, a main frame door opening signal can be output to the main control board 4100 even when a short circuit occurs, and the outer end The frame door opening information output signal can be transmitted to the hall computer via the external terminal board 784.

  When the door frame opening switch 618 and the body frame opening switch 619 are changed from a normally closed switch to a normally open type (normally open (NO)) switch (door frame opening switch 618 ′ and body frame opening switch 619 ′). The door frame opening switch 618 ′ is turned on (conductive) when the door frame 5 is closed from the main body frame 3, and is turned off (cut) when the door frame 5 is opened to the main body frame 3. . The body frame opening switch 619 ′ is turned on (conductive) when the body frame 3 is closed from the outer frame 2, and turned off (disconnected) when the body frame 3 is opened to the outer frame 2. Then, even if the door frame opening switch 618 ′ is disconnected due to some cause and the switch is turned off (cut), the door frame 5 is opened from the main body frame 3, and the main body is not used for some reason. Even when the frame opening switch 619 ′ is disconnected and the switch is turned off (cut), the main body frame 3 is released from the outer frame 2. As described above, the door frame opening switch 618 ′ and the body frame opening switch 619 ′ can output a main frame door opening signal to the main control board 4100 even when a normally open switch is used or a disconnection occurs. An outer end frame door opening information output signal can be transmitted to the hall computer via the external terminal board 784.

[10-2-3 (c). A circuit that receives a power outage warning signal from the power outage monitoring circuit]
A transmission line for transmitting a payout power failure notice signal from the power failure monitoring circuit 4100e provided on the main control board 4100 is electrically connected to the other end of the pull-up resistor PR40, one end of which is electrically connected to the + 12V power supply line, and a resistor. It is electrically connected to the base terminal of the transistor PTR40 via PR41. In addition to being electrically connected to the resistor PR41, one end of the transistor PTR40 is electrically connected to the other end of the resistor PR42 that is grounded to the ground (GND). The emitter terminal of the transistor PTR40 is grounded to the ground (GND), and the collector terminal of the transistor PTR40 is electrically connected to the other end of the resistor PR43, one end of which is electrically connected to the + 5V power supply line, and a non-inverting buffer. Dispensing control via ICPIC 40 (non-inverted buffer ICPIC 40 includes eight non-inverted buffer circuits, and the signal waveform input to one (PIC 40A) is shaped and output without being inverted). The MPU 4120a is electrically connected to the input terminal PA1 of the input port PA. When the transistor PTR40 is turned on / off, the logic of the signal output from the collector terminal of the transistor PTR40 changes, and the signal is input to the input terminal PA1 of the input port PA of the payout control MPU 4120a as a payout power failure notice signal.

  A circuit composed of the resistors PR41 and PR42 and the transistor PTR40 is a switch circuit that is turned ON / OFF by a payout power failure notice signal from a power failure monitoring circuit 4100e provided in the main control board 4100.

  As described above, the power failure monitoring circuit 4100e monitors the signs of power failure or instantaneous power failure of two types of voltages, + 12V and + 24V, from the power supply board 851, and if a power failure or power failure sign is detected, there is no reset function. A payout blackout notice signal is output to the payout control board 4110 as a blackout notice via the main control output circuit 4100cb. The power failure monitoring circuit 4100e monitors the signs of a power failure or instantaneous power failure at + 12V and + 24V. As described above, the condition that the voltage of + 24V is larger than the power failure detection voltage V1pf, and the voltage of + 12V is higher than the power failure detection voltage V2pf. When both conditions are satisfied, the voltage applied to the collector terminal of the subsequent transistor MTR22 is pulled down to the ground (GND) side in the payout control board 4110 via the wiring (harness), and the logic becomes LOW. One of a condition that the + 24V voltage is smaller than the power failure detection voltage V1pf and a condition that the voltage of + 12V is smaller than the power failure detection voltage V2pf is input to the dispensing control board 4110. When the condition is satisfied, the subsequent transistor MTR22 Payout power failure warning signal of the voltage applied to the collector terminal wiring logic by via (harness) is pulled up to + 12V side by the pull-up resistor PR40 described above it becomes HI is input to the payout control board 4110.

  When both the condition that the voltage of + 24V is larger than the power failure detection voltage V1pf and the condition that the voltage of + 12V is larger than the power failure detection voltage V2pf are satisfied, that is, there is no sign of power failure or instantaneous interruption of the voltages of + 12V and + 24V. In some cases, a payout power failure warning signal whose logic is LOW is input to the payout control board 4110, so that the voltage applied to the base terminal of the transistor PTR40 is pulled down to the ground (GND) side to turn off the transistor PTR40. The voltage applied to the collector terminal of the transistor PTR40 is pulled up to the + 5V side by the resistor PR43. As a result, a payout power failure warning signal whose logic is HI is input from the collector terminal of the transistor PTR40 to the input terminal PA1 of the input port PA of the payout control MPU 4120a.

  On the other hand, when either one of the condition that the voltage of + 24V is smaller than the power failure detection voltage V1pf and the condition that the voltage of + 12V is smaller than the power failure detection voltage V2pf is satisfied, that is, the voltage of + 12V and / or + 24V When there is an indication of a power outage or a momentary power failure, a payout power outage warning signal whose logic is HI is input to the payout control board 4110 and is applied to the base terminal of the transistor PTR 40 by a payout power outage notice signal from the power outage monitoring circuit 4100e. Is pulled up to + 12V by the pull-up resistor PR40, the transistor PTR40 is turned on, and the voltage applied to the collector terminal of the transistor PTR40 is pulled down to the ground (GND) side. As a result, a payout power failure warning signal whose logic at the collector terminal of the transistor PTR40 is LOW is input to the input terminal PA1 of the input port PA of the payout control MPU 4120a.

  Thus, when there is an indication of a power failure or instantaneous power failure at a voltage of +12 V and / or +24 V, a payout power failure notice signal whose logic is HI is input to the input terminal PA1 of the input port PA of the payout control MPU 4120a, When there is no sign of a power failure or a momentary power failure at voltages of +12 V and +24 V, a payout power failure notice signal whose logic is LOW is input to the input terminal PA1 of the input port PA of the payout control MPU 4120a. This is because, as described above, when there is an indication of a power failure or a momentary power failure at a voltage of + 12V and / or + 24V, a power failure warning signal whose logic is HI is input to the input terminal PA1 of the input port PA of the main control MPU 4100a. On the other hand, when there is no sign of + 12V and + 24V power failure or instantaneous power failure, a power failure warning signal is input to the input terminal PA1 of the input port PA of the main control MPU 4100a. The logic of the payout blackout signal input to the payout control MPU 4120a and the logic of the blackout notice signal input to the main control MPU4100a are the same logic.

[10-2-3 (d). Circuit that receives detection signal from full switch]
The detection signal from the full switch 550 provided in the foul cover unit 540 shown in FIG. 1 is sent to the payout control board 4110 via the handle relay terminal plate 192 shown in FIG. Have been entered. The output terminal of the full switch 550 is configured as an open collector output type in which the emitter terminal is grounded to the ground (GND), and one end of the payout control board 4110 is electrically connected to the + 12V power supply line. The pull-up resistor PR44a is electrically connected to the other end of the pull-up resistor PR44a and electrically connected to the first terminal of the full-switch three-terminal filter PIC50. This full-tank switch three-terminal filter PIC50 is a T-type filter circuit, and has excellent attenuation characteristics magnetically shielded with ferrite.

  The second terminal of the full tank switch three-terminal filter PIC50 is grounded to the ground (GND), and the third terminal of the full tank switch three-terminal filter PIC50 is connected to the full tank switch three-terminal filter PIC50 via the resistor PR44b. Is electrically connected to the base terminal of the transistor PTR41 via the resistor PR45. Thereby, the detection signal of the full tank switch 550 is input to the base terminal of the transistor PTR 41 after the noise component is removed in the full terminal switch three-terminal filter PIC50. In addition to the resistor PR45 being electrically connected, the base terminal of the transistor PTR41 is electrically connected to the other end of the resistor PR46 that is grounded to the ground (GND), and has one end connected to the ground (GND). The other end of the electrically connected capacitor PC40 is electrically connected. The capacitor PC40 plays a role as a low-pass filter. The emitter terminal of the transistor PTR41 is grounded to the ground (GND), and the collector terminal of the transistor PTR41 is electrically connected to the other end of the resistor PR47, one end of which is electrically connected to the + 5V power supply line, and a non-inverting buffer. Payout control via ICPIC 40 (non-inverted buffer ICPIC 40 includes eight non-inverted buffer circuits, and the signal waveform input to one (PIC 40B) is shaped and output without being inverted). The MPU 4120a is electrically connected to the input terminal PA2 of the input port PA. When the transistor PTR41 is turned on / off, the logic of the signal output from the collector terminal of the transistor PTR41 changes, and the signal is input as a full signal to the input terminal PA2 of the input port PA of the payout control MPU 4120a.

  A circuit composed of the resistors PR45 and PR46 and the transistor PTR41 is a switch circuit that is turned on / off in response to a detection signal from the full switch 550.

  As described above, the full tank switch 550 detects whether or not the storage space in the second ball passage of the foul cover unit 540 is full with the stored game balls. In this embodiment, when the storage space is not full with the stored game balls, the voltage applied to the output terminal of the full switch 550 is paid out via the handle relay terminal plate 192 and the power supply board 851. When the control board 4110 is pulled up to the + 12V side by the pull-up resistor 44a and the logic becomes HI, the signal is input to the payout control board 4110, while the game ball in which the accommodation space is stored is full. The voltage applied to the output terminal of the full switch 550 is pulled down to the ground (GND) side in the payout control board 4110 via the handle relay terminal board 192 and the power supply board 851, and a signal whose logic is LOW is sent out. Input to the control board 4110.

  When the storage space is not full with the stored game balls, the voltage applied to the output terminal of the full tank switch 550 is pulled on the payout control board 4110 via the handle relay terminal board 192 and the power supply board 851. When the signal that has been pulled up to + 12V by the up resistor 44a and whose logic has become HI is input to the base terminal of the transistor PTR41 described above, the transistor PTR41 is turned ON and the switch circuit is also turned ON. As a result, a full signal in which the voltage applied to the collector terminal of the transistor PTR41 is pulled down to the ground (GND) side and the logic becomes LOW is input to the input terminal PA2 of the input port PA of the payout control MPU 4120a.

  On the other hand, when the game ball in which the accommodation space is stored is full, the voltage applied to the output terminal of the full tank switch 550 is supplied to the payout control board 4110 via the handle relay terminal board 192 and the power supply board 851. When the signal that is pulled down to the ground (GND) side and becomes logic LOW is input to the base terminal of the transistor PTR41 described above, the transistor PTR41 is turned OFF and the switch circuit is also turned OFF. As a result, a full-tank signal whose voltage applied to the collector terminal of the transistor PTR41 is pulled up to the + 5V side by the resistor PR47 and becomes logic HI is input to the input terminal PA2 of the input port PA of the payout control MPU 4120a.

  In the present embodiment, the detection signal from the full switch 550 is input to a switch circuit constituted by the resistor PR45, the resistor PR46, and the transistor PTR41 via the full switch three-terminal filter PIC50. However, the detection signals from the various detection switches such as the ball break switch 750, the counting switch 751, and the rotation angle switch 752 shown in FIG. 15 are T-type filter circuits such as a full-switch three-terminal filter PIC50. It is a circuit configuration that is directly input to each switch circuit without going through. Since the full tank switch 550 is provided in the foul cover unit 540 attached to the door frame 5, the ball break switch 750, the counting switch 751, and the rotation angle switch 752 provided in the prize ball device 740 attached to the main body frame 3. Compared to the above, the path for transmitting the detection signal is extremely long, and it is very susceptible to noise.

  The full tank switch 550 detects whether or not the storage space in the second ball passage of the foul cover unit 540 is full with the stored game balls. The payout control MPU 4120a If it is determined that the game space in which the accommodation space is stored is full, the drive control of the payout motor 744 is forcibly stopped and the payout of the game ball by the payout rotating body is stopped. To do. In other words, when noise enters a transmission path (transmission line) that transmits a detection signal from the full tank switch 550, the payout control MPU 4120a drives the payout motor 744 even though the game ball in which the accommodation space is stored is not full. In some cases, the control is forcibly stopped and the payout of the game ball by the payout rotating body is stopped, or the payout motor 744 is driven and controlled even though the storage space is full with the stored game balls. If the game ball is filled up to the upstream side of the above-mentioned prize ball passage by rotating the payout rotator and continuing to pay out the game ball, the payout rotator itself can no longer rotate and the payout motor 744 The load is abnormal, the payout motor 744 is overloaded, abnormally generates heat and breaks down, or the rotary shaft of the payout motor 744 is transmitted to the rotary motion of the payout rotating body. Sometimes referred to 構等 is or failure. Therefore, in this embodiment, in order to prevent such a problem from occurring, the circuit configuration is adopted so that the noise component is first removed from the detection signal from the full tank switch 550 in the full terminal switch three-terminal filter PIC50. .

[10-2-3 (e). Circuit that receives operation signals from operation switches]
The output terminals 1 and 2 of the operation switch 860a are connected to the ground (GND), and the output terminals 3 and 4 of the operation switch 860a are connected to the + 5V side by the pull-up resistor PR48. It is pulled up and electrically connected to the base terminal of the previous-stage transistor PTR42 via the resistor PR49. In addition to being electrically connected to the resistor PR49, one end of the base terminal of the transistor PTR42 in the previous stage is electrically connected to the other end of the resistor PR50 that is grounded to the ground (GND). The fourth terminal, which is the output terminal of the operation switch 860a, is electrically connected to the pull-up resistor PR48, and is also electrically connected to the other end of the capacitor PC41 whose one end is grounded to the ground (GND). ing. The emitter terminal of the front-stage transistor PTR42 is grounded to the ground (GND), and the collector terminal of the front-stage transistor PTR42 is electrically connected to the other end of the resistor PR51 whose one end is electrically connected to the + 5V power supply line. At the same time, it is electrically connected to the base terminal of the subsequent transistor PTR43 via the resistor PR52. In addition to being electrically connected to the resistor PR52, one end of the base terminal of the transistor PTR43 at the subsequent stage is electrically connected to the other end of the resistor PR53 that is grounded to the ground (GND). The emitter terminal of the rear-stage transistor PTR43 is grounded to the ground (GND), and the collector terminal of the rear-stage transistor PTR43 is electrically connected to the other end of the resistor PR54 whose one end is electrically connected to the + 5V power supply line. A non-inverted buffer ICPIC 40 (the non-inverted buffer ICPIC 40 includes eight non-inverted buffer circuits, and shapes and outputs the signal waveform input to one of them (PIC 40C) without inversion). Via the input terminal PA3 of the input port PA of the payout control MPU 4120a. The logic of the signal output from the collector terminal of the downstream transistor PTR43 is changed by turning ON / OFF the upstream and downstream transistors PTR42 and PTR43. Is input.

  The third and fourth terminals, which are the output terminals of the operation switch 860a, are pulled up to the + 5V side by the pull-up resistor PR48 and are electrically connected to the base terminal of the previous transistor PTR42 via the resistor PR49. The voltage is pulled up to + 5V by the pull-up resistor PR48 and is electrically connected to the base terminal of the transistor PTR44 via the resistor PR55. In addition to being electrically connected to the resistor PR55, one end of the transistor PTR44 is electrically connected to the other end of the resistor PR56 that is grounded to the ground (GND). The emitter terminal of the transistor PTR44 is grounded to the ground (GND), and the collector terminal of the transistor PTR44 is electrically connected to the main control board 4100 via a wiring (harness). When the collector terminal of the transistor PTR 44 is electrically connected to the main control board 4100 via a wiring (harness), one end of the collector terminal of the main control input circuit 4100b of the main control board 4100 shown in FIG. It is electrically connected to the other end of pull-up resistor MR2 that is electrically connected to the power supply line. When the transistor PTR44 is turned on / off, the logic of the signal output from the collector terminal of the transistor PTR44 changes, and the signal is input as the RAM clear signal to the input terminal PA0 of the input port PA of the main control MPU 4100a.

  The circuit composed of the pull-up resistor PR48 and the capacitor PC41 is a switch signal generation circuit, and when the operation switch 860a is pressed, the contact that constitutes the operation switch 860a repeatedly turns on and off for a short time. Is configured as a circuit that also has a function of absorbing fluctuations in voltage from the operation switch 860a.

  A circuit composed of the resistors PR49 and PR50 and the transistor PTR42 is a previous-stage switch circuit, and a circuit composed of the resistors PR52 and PR53 and the transistor PTR43 is a subsequent-stage switch circuit, and the resistors PR55 and PR56 and the transistor PTR44. Is a switch circuit that is turned ON / OFF by an operation signal from the operation switch 860a.

  As described above, the operation switch 860a is connected to the RAM (payout control built-in RAM) built in the payout control MPU 4120a of the payout control board 4110 and the main control MPU 4100a of the main control board 4100 within a predetermined period from when the power is turned on. It is operated when clearing the built-in RAM (main control built-in RAM), or when an error is reported after the power is turned on, it is operated to cancel the error. A function for clearing RAM within a predetermined period from the time and canceling an error after the power is turned on (after a period during which the function is performed as a RAM clear has elapsed, that is, after a predetermined period has elapsed since the power was turned on) And has a function. The operation signal from the operation switch 860a becomes a RAM clear signal in the function of performing a RAM clear within a predetermined period from the time of turning on the power, and after the power is turned on (after a predetermined period has elapsed since the time of turning on the power). In the function for performing error cancellation in (), an error cancellation signal is generated.

  When the operation switch 860a is not operated, the operation signal whose logic becomes HI by pulling up the third terminal and the fourth terminal, which are the output terminals of the operation switch 860a, to the + 5V side by the pull-up resistor PR48 is transmitted to the previous stage transistor. When input to the base terminal of the PTR 42, the previous stage transistor PTR 42 is turned ON, and the previous stage switch circuit is also turned ON, and is applied to the collector terminal of the previous stage transistor PTR 43, which is a voltage applied to the base of the subsequent stage transistor PTR 43. As a result, the rear-stage transistor PTR43 is turned OFF, and the rear-stage switch circuit is also turned OFF. Thereby, the voltage applied to the collector terminal of the transistor PTR43 at the subsequent stage is pulled up to the + 5V side by the resistor PR54, and the RWMCLR signal whose logic becomes HI is input to the input terminal PA3 of the input port PA of the payout control MPU 4120a. The payout control MPU 4120a performs a RAM clear for erasing information stored in the payout control built-in RAM when the logic of the RWMCLR signal input to the input terminal PA3 is HI within a predetermined period from the time when the power is turned on. If the logic of the RWMCLR signal input to the input terminal PA3 is HI after the power is turned on (after a predetermined period has elapsed since the power was turned on), the error is canceled. Judge that it is not an instruction.

  When the operation switch 860a is not operated, the operation signal in which the output terminal of the operation switch 860a is the third terminal and the fourth terminal are pulled up to the + 5V side by the pull-up resistor PR48 and the logic becomes HI is output from the transistor PTR44. The transistor PTR44 is turned on and the switch circuit is also turned on. As a result, the RAM clear signal in which the voltage applied to the collector terminal of the transistor PTR44 is pulled down to the ground (GND) side in the main control board 4100 via the wiring (harness) and the logic becomes LOW is sent to the main control board 4100. Entered. When the RAM clear signal whose logic is LOW is input within a predetermined period from when the power is turned on, the main control MPU 4100a of the main control board 4100 has the logic shown in FIG. Is input to the base terminal of the transistor MTR0, the transistor MTR0 is turned OFF and the switch circuit is also turned OFF. Thereby, the voltage applied to the collector terminal of the transistor MTR0 is pulled up to the + 5V side by the resistor MR5 and the logic clear signal HI is input to the input terminal PA0 of the input port PA of the main control MPU 4100a. The main control MPU 4100a determines that the RAM clear signal for erasing the information stored in the main control built-in RAM is not instructed when the logic of the RAM clear signal input to the input terminal PA0 is HI.

  On the other hand, when the operation switch 860a is operated, the operation signal whose logic is LOW by pulling down the third terminal and the fourth terminal, which are output terminals of the operation switch 860a, to the ground (GND) side is the transistor in the previous stage. When input to the base terminal of the PTR 42, the previous stage transistor PTR 42 is turned OFF and the previous stage switch circuit is also turned OFF, and the voltage applied to the base of the rear stage transistor PTR 43 is applied to the collector terminal of the previous stage transistor PTR 42. As a result, the subsequent transistor PTR43 is turned on and the subsequent switch circuit is also turned on. As a result, the voltage applied to the collector terminal of the subsequent transistor PTR43 is pulled down to the ground (GND) side, and the RWMCLR signal whose logic is LOW is input to the input terminal PA3 of the input port PA of the payout control MPU 4120a. The payout control MPU 4120a performs a RAM clear for erasing information stored in the payout control built-in RAM when the logic of the RWMCLR signal input to the input terminal PA3 is LOW within a predetermined period from when the power is turned on. If the logic of the RWMCLR signal input to the input terminal PA3 is LOW after the power is turned on (after a predetermined period has elapsed since the power was turned on), the error is canceled. Judge that it is an instruction.

  In addition, when the operation switch 860a is being operated, an operation in which the logic becomes LOW because the third and fourth terminals, which are output terminals of the operation switch 860a, are pulled down to the ground (GND) side by the pull-up resistor PR48. A signal is input to the base terminal of the transistor PTR44, the transistor PTR44 is turned OFF, and the switch circuit is also turned OFF. As a result, the voltage applied to the collector terminal of the transistor PTR44 is pulled up to the + 12V side by the pull-up resistor MR2 of the main control input circuit 4100b of the main control board 4100 via the wiring (harness), and the logic becomes HI. A clear signal is input to the main control board 4100. When the RAM clear signal whose logic is HI is input within a predetermined period from the time of turning on the power, the main control MPU 4100a of the main control board 4100 has the logic shown in FIG. When the RAM clear signal is input to the base terminal of the transistor MTR0, the transistor MTR0 is turned on and the switch circuit is also turned on. As a result, the RAM clear signal in which the voltage applied to the collector terminal of the transistor MTR0 is pulled down to the ground (GND) side and the logic becomes LOW is input to the input terminal PA0 of the input port PA of the main control MPU 4100a. When the logic of the RAM clear signal input to the input terminal PA0 is LOW, the main control MPU 4100a determines that the instruction is to instruct RAM clear to erase information stored in the main control built-in RAM.

[10-2-4. Dispensing motor drive circuit]
Next, a payout motor drive circuit 4120d for outputting a drive signal to the payout motor 744 of the prize ball device 740 shown in FIG. 5 will be described. As shown in FIG. 30, the payout motor drive circuit 4120d is mainly composed of a voltage switching circuit 4120da and a drive ICPIC 60. The power input terminals 1 and 2 of the voltage switching circuit 4120da are electrically connected to the + 12V power supply line and the + 5V power supply line, respectively, and +12 and + 5V are applied, respectively. The ground terminal of the voltage switching circuit 4120da is the ground (GND) Grounded. A voltage switching signal is input to the power source switching input terminal of the voltage switching circuit 4120da. This voltage switching signal is output from the output terminal of the predetermined output port of the payout control MPU 4120a to the payout control output circuit 4120ca with reset function, and is output from the payout control output circuit 4120ca with reset function to the power supply switching input terminal of the voltage switch circuit 4120da. It has come to be. The power output terminal of the voltage switching circuit 4120da is electrically connected to the third terminal and the tenth terminal, which are the cathode terminals of the drive ICPIC 60, via the Zener diode PZD60, and electrically connected to the power supply terminal of the payout motor 744. Based on the voltage switching signal input to the voltage switching input terminal of the voltage switching circuit 4120da, + 12V or + 5V is used as the motor driving voltage, and the third terminal which is the cathode terminal of the drive ICPIC60 through the Zener diode PZD60 The power is supplied to the terminal and the 10th terminal, and supplied to the dispensing motor 744.

  The drive ICPIC 60 includes four Darlington power transistors. In the present embodiment, the sixth terminal and the seventh terminal, which are the emitter terminals of the drive ICPIC 60, are grounded to the ground (GND), respectively, and are the base terminals of the drive ICPIC 60. The payout motor drive signal is input to the first terminal, the fifth terminal, the eighth terminal, and the twelfth terminal through the resistors PR60 to PR63, respectively. The second terminal, the fourth terminal, the ninth terminal, and the eleventh terminal that are the collector terminals of the drive ICPIC 60 are the first terminal, the fifth terminal, the eighth terminal, and the twelfth terminal that are the base terminals of the drive ICPIC 60, respectively. If the payout motor drive signal is input to the first terminal, the fifth terminal, the eighth terminal, and the twelfth terminal of the drive ICPIC 60 through the resistors PR60 to PR63, respectively, A certain drive pulse is output to each phase (/ B phase, B phase, A phase, / A phase) corresponding to the dispensing motor 744. This payout motor drive signal is output from the output terminal of a predetermined output port of the payout control MPU 4120a to the payout control output circuit 4120ca with reset function, and from the payout control output circuit 4120ca with reset function via the resistors PR60 to PR63, the drive ICPIC60. The signal is output to the first terminal, the fifth terminal, the eighth terminal, and the twelfth terminal, which are base terminals. These drive pulses are generated by switching excitation currents that flow through the phases (/ B phase, B phase, A phase, / A phase) of the dispensing motor 744, and rotate the dispensing motor 744. Note that a back electromotive force is generated when the drive pulse (excitation signal) of each phase (/ B phase, B phase, A phase, / A phase) is cut off by this switching. When this back electromotive force exceeds the withstand voltage of the drive ICPIC 60, the drive ICPIC 60 is damaged. As a protection, the above-described Zener diode PZD0 is electrically connected to the third terminal and the tenth terminal before the drive ICPIC 60. The circuit configuration is adopted.

[10-2-5. CR unit input / output circuit]
Next, a CR unit input / output circuit 4120e for inputting / outputting various signals to / from the CR unit 6 shown in FIG. 16 will be described. As described above, the payout control board 4110 receives the ball rental request signal BRDY and one payout operation start request signal BRQ from the CR unit 6 via the game ball rental device connection terminal plate 869. , And a predetermined voltage VL (+12 V) and a ground LG created from the AC24V supplied from the power supply board 851 shown in FIG. Via the terminal board 869, an EXS signal that indicates that one payout operation has been started or ended, and a PRDY signal that indicates that a payout operation for paying out a rental ball is possible or impossible. And are output. As shown in FIG. 31, an input / output circuit for inputting / outputting these various signals mainly includes photocouplers PIC70 to PIC74 (infrared LEDs and phototransistors are incorporated).

  The predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC70 via the resistor PR70. The cathode terminal of the photocoupler PIC 70 is electrically connected to the ground LG from the CR unit 6. The resistor PR60 is a limiting resistor for limiting the current flowing through the built-in infrared LED of the photocoupler PIC70. When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC70, the photocoupler PIC70 is turned on, while the predetermined voltage VL from the CR unit 6 is not applied to the anode terminal of the photocoupler PIC70. In some cases, the photocoupler PIC 70 is turned off. The emitter terminal of the photocoupler PIC70 is grounded to the ground (GND), and the collector terminal of the photocoupler PIC70 is electrically connected to the base terminal of the transistor PTR70 via the resistor PR71, and the transistor via the resistor PR72. It is electrically connected to the base terminal of the PTR 71. In addition to being electrically connected to the resistor PR71, the collector terminal of the photocoupler PIC70 is electrically connected to the other end of the pull-up resistor PR73 that is electrically connected to the + 5V power supply line.

  In addition to being electrically connected to the resistor PR71, the base terminal of the transistor PTR70 is electrically connected to the other end of the resistor PR74 that is grounded to the ground (GND). The emitter terminal of the transistor PTR70 is grounded to the ground (GND), and the collector terminal of the transistor PTR70 is electrically connected to the other end of the resistor PR75, one end of which is electrically connected to the + 5V power supply line, and a non-inverting buffer. 27, the ICPIC 80 (the non-inverted buffer ICPIC 80 includes eight non-inverted buffer circuits, and shapes and outputs the signal waveform input to one of them (PIC 80A) without inversion). Are electrically connected to an input terminal of a predetermined input port of the payout control MPU 4120a shown in FIG. When the transistor PTR70 is turned ON / OFF, the logic of the signal output from the collector terminal of the transistor PTR70 changes, and the signal is input as the CR connection signal 1 to the input terminal of the predetermined input port of the payout control MPU 4120a.

  On the other hand, the base terminal of the transistor PTR71 is electrically connected to the resistor PR72 and one end is electrically connected to the other end of the resistor PR76 that is grounded to the ground (GND). The emitter terminal of the transistor PTR71 is grounded to the ground (GND), and the collector terminal of the transistor PTR71 is electrically connected to the power supply substrate 851 via a wiring (harness). Note that when the collector terminal of the transistor PTR71 is electrically connected to the power supply substrate 851 via a wiring (harness), one end of the collector terminal of the power supply substrate 851 is electrically connected to the + 12V power supply line (not shown). Is electrically connected to the other end. When the transistor PTR71 is turned on / off, the logic of the signal output from the collector terminal of the transistor PTR71 changes, and the signal is input to the power supply board 851 as a CR connection signal.

  A circuit composed of the resistors PR71 and PR74 and the transistor PTR70 is a switch circuit that is turned on / off by turning on / off the photocoupler PIC70.

  When the predetermined voltage VL from the CR unit 6 is not applied to the anode terminal of the photocoupler PIC70, the photocoupler PIC70 is turned off, and the transistor PTR70 is turned on by being pulled up to the + 5V side by the pull-up resistor PR73. It will be turned on. As a result, the voltage applied to the collector terminal of the transistor PTR 70 is pulled down to the ground (GND) side, and the CR connection signal 1 whose logic becomes LOW is input to the input terminal of the predetermined input port of the payout control MPU 4120a.

  On the other hand, when the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC70, the photocoupler PIC70 is turned on, and the voltage applied to the base terminal of the transistor PTR70 is pulled down to the ground (GND) side. As a result, the transistor PTR 70 is turned OFF, and the switch circuit is also turned OFF. As a result, the voltage applied to the collector terminal of the transistor PTR70 is pulled up to the + 5V side by the pull-up resistor PTR75, and the CR connection signal 1 whose logic becomes HI is input to the input terminal of the predetermined input port of the payout control MPU4120a. The

  The circuit composed of the resistors PR72 and PR76 and the transistor PTR71 is also a switch circuit that is turned on / off by turning on / off the photocoupler PIC70.

  When the predetermined voltage VL from the CR unit 6 is not applied to the anode terminal of the photocoupler PIC70, the photocoupler PIC70 is turned off and pulled up to the + 5V side by the pull-up resistor PR73, thereby turning on the transistor PTR71 and the switch circuit also It will be turned on. As a result, the CR connection signal in which the voltage applied to the collector terminal of the transistor PTR71 is pulled down to the ground (GND) side in the power supply board 851 via the wiring (harness) and the logic becomes LOW is input to the power supply board 851. The

  On the other hand, when the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC70, the photocoupler PIC70 is turned on, and the voltage applied to the base terminal of the transistor PTR71 is pulled down to the ground (GND) side. As a result, the transistor PTR 71 is turned off, and the switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor PTR71 is pulled up to + 12V side by the pull-up resistor of the power supply board 851 via the wiring (harness), and the CR connection signal whose logic becomes HI is input to the power supply board 851. Is done.

  The predetermined voltage VL from the CR unit 6 is applied not only to the anode terminal of the photocoupler PIC70 but also to the anode terminal of the photocoupler PIC71 via the resistor PR77. The BRDY from the CR unit 6 is input to the cathode terminal of the photocoupler PIC71. The resistor PR77 is a limiting resistor for limiting the current flowing through the built-in infrared LED of the photocoupler PIC71. When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC71 and the BRDY logic from the CR unit 6 is LOW, the photocoupler PIC71 is turned on, while the photocoupler PIC71 is turned on. When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the coupler PIC71 and the BRDY logic from the CR unit 6 is HI, the photocoupler PIC71 is turned off. Yes. The emitter terminal of the photocoupler PIC71 is grounded to the ground (GND), and the collector terminal of the photocoupler PIC71 is electrically connected to the other end of the pull-up resistor PR78 whose one end is electrically connected to the + 5V power supply line. A non-inverted buffer ICPIC 80 (the non-inverted buffer ICPIC 80 includes eight non-inverted buffer circuits, and shapes and outputs the signal waveform input to one of them (PIC 80B) without inverting it). To the input terminal of a predetermined input port of the payout control MPU 4120a. When the photocoupler PIC71 is turned ON / OFF, the logic of the signal output from the collector terminal of the photocoupler PIC71 changes, and the signal is input as a BRDY signal to the input terminal of a predetermined input port of the payout control MPU 4120a.

  When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC71 and the BRDY logic from the CR unit 6 is LOW, the photocoupler PIC71 is turned on. The BRDY signal whose logic is set to LOW when the voltage applied to the collector terminal of the coupler PIC71 is pulled down to the ground (GND) side is input to the input terminal of a predetermined input port of the payout control MPU 4120a. On the other hand, when the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC71 and the BRDY logic from the CR unit 6 is HI, the photocoupler PIC71 is turned off. Then, the BRDY signal whose logic applied to HI is pulled up to the + 5V side by the pull-up resistor PR78 and the voltage applied to the collector terminal of the photocoupler PIC71 is input to the input terminal of the predetermined input port of the payout control MPU 4120a. Thus, the logic of the BRDY signal output from the collector terminal of the photocoupler PIC 71 is the same as the logic of BRDY from the CR unit 6.

  The predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC72 via the resistor PR79 in addition to the anode terminal of the photocoupler PIC70 and the anode terminal of the photocoupler PIC71. The BRQ from the CR unit 6 is input to the cathode terminal of the photocoupler PIC72. The resistor PR79 is a limiting resistor for limiting the current flowing through the built-in infrared LED of the photocoupler PIC72. When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC72 and the BRQ logic from the CR unit 6 is LOW, the photocoupler PIC72 is turned on, while the photocoupler PIC72 is turned on. When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the coupler PIC 72 and the BRQ logic from the CR unit 6 is HI, the photo coupler PIC 72 is turned off. Yes. The emitter terminal of the photocoupler PIC72 is grounded to the ground (GND), and the collector terminal of the photocoupler PIC72 is electrically connected to the other end of the pull-up resistor PR80 whose one end is electrically connected to the + 5V power supply line. A non-inverted buffer ICPIC 80 (the non-inverted buffer ICPIC 80 includes eight non-inverted buffer circuits, and shapes and outputs the signal waveform input to one of them (PIC 80C) without inverting it). To the input terminal of a predetermined input port of the payout control MPU 4120a. When the photocoupler PIC72 is turned on / off, the logic of the signal output from the collector terminal of the photocoupler PIC72 changes, and the signal is input as a BRQ signal to the input terminal of a predetermined input port of the payout control MPU 4120a.

  When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC72 and when the BRQ logic from the CR unit 6 is LOW, the photocoupler PIC72 is turned on. A BRQ signal whose logic is LOW when the voltage applied to the collector terminal of the coupler PIC 72 is pulled down to the ground (GND) side is input to the input terminal of a predetermined input port of the payout control MPU 4120a. On the other hand, when the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC72 and the BRQ logic from the CR unit 6 is HI, the photocoupler PIC72 is turned off. The voltage applied to the collector terminal of the photocoupler PIC72 is pulled up to the + 5V side by the pull-up resistor PR80, and the BRQ signal whose logic becomes HI is input to the input terminal of the predetermined input port of the payout control MPU4120a. Thus, the logic of the BRQ signal output from the collector terminal of the photocoupler PIC 72 is the same as the logic of the BRQ from the CR unit 6.

  An EXS signal notifying that the one-time payout operation is started or ended from the output terminal of the predetermined output port of the payout control MPU 4120a is output to the payout control output circuit 4120cb without reset function, and the payout control output circuit without reset function 4120cb is input to the cathode terminal of the photocoupler PIC73 via the resistor PR81. One end of the anode terminal of the photocoupler PIC73 is electrically connected to the other end of the resistor PR82 that is electrically connected to the + 12V power supply line. The resistor PR82 is a limiting resistor for limiting the current flowing through the built-in infrared LED of the photocoupler PIC73. EXS output when + 12V is applied to the anode terminal of the photocoupler PIC73 via the resistor PR82 and output from the output terminal of a predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cb without reset function. When the logic of the signal is LOW, the photocoupler PIC73 is turned on, while + 12V is applied to the anode terminal of the photocoupler PIC73 via the resistor PR82, and a predetermined output port of the payout control MPU 4120a. The photocoupler PIC 73 is turned OFF when the logic of the EXS signal output from the output terminal via the non-reset payout control output circuit 4120cb is HI. The emitter terminal of the photocoupler PIC73 is grounded to the ground LG from the CR unit 6, and the collector terminal of the photocoupler PIC73 is connected to the inside of the CR unit 6 via the pull-up resistor PR83 via the game ball lending device connection terminal plate 869. The voltage is raised to a predetermined voltage VL and electrically connected to the built-in control device. When the photocoupler PIC73 is turned ON / OFF, the logic of the signal output from the collector terminal of the photocoupler PIC73 changes, and the signal is input as EXS to the built-in control device of the CR unit 6.

  EXS output when + 12V is applied to the anode terminal of the photocoupler PIC73 via the resistor PR82 and output from the output terminal of a predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cb without reset function. When the logic of the signal is LOW, the photocoupler PIC73 is turned ON, so that the voltage applied to the collector terminal of the photocoupler PIC73 is pulled down to the ground (GND) side, and EXS in which the logic becomes LOW is the CR unit. 6 built-in control device. On the other hand, when + 12V is applied to the anode terminal of the photocoupler PIC73 via the resistor PR82, the output is output from the output terminal of a predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cb without reset function. When the logic of the EXS signal is HI, the photocoupler PIC73 is turned OFF, so that the voltage applied to the collector terminal of the photocoupler PIC73 is pulled up to the predetermined voltage VL by the pull-up resistor PR83, and the logic becomes HI. EXS is input to the built-in control device of the CR unit 6. Thus, the logic of the EXS output from the collector terminal of the photocoupler PIC73 is the logic of the EXS signal output from the output terminal of the predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cb without a reset function. It has the same logic.

  The PRDY signal that indicates that the payout operation for paying out the rented ball from the output terminal of the predetermined output port of the payout control MPU 4120a is possible or impossible is a cathode terminal of the photocoupler PIC74 via the resistor PR84. Has been entered. One end of the anode terminal of the photocoupler PIC74 is electrically connected to the other end of the resistor PR85 that is electrically connected to the + 12V power supply line. The resistor PR85 is a limiting resistor for limiting the current flowing through the built-in infrared LED of the photocoupler PIC74. PRDY output from the output terminal of a predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cb without reset function when + 12V is applied to the anode terminal of the photocoupler PIC74 via the resistor PR85. When the logic of the signal is LOW, the photocoupler PIC74 is turned on, and when + 12V is applied to the anode terminal of the photocoupler PIC74 via the resistor PR85, the predetermined output port of the payout control MPU4120a When the logic of the PRDY signal output from the output terminal via the payout control output circuit 4120cb without reset function is HI, the photocoupler PIC74 is turned OFF. The emitter terminal of the photocoupler PIC74 is grounded to the ground LG from the CR unit 6, and the collector terminal of the photocoupler PIC74 is connected to the inside of the CR unit 6 by a pull-up resistor PR86 via a game ball lending device connection terminal plate 869. The voltage is raised to a predetermined voltage VL and electrically connected to the built-in control device. When the photocoupler PIC74 is turned on / off, the logic of the signal output from the collector terminal of the photocoupler PIC74 changes, and the signal is input as PRDY to the built-in control device of the CR unit 6.

  PRDY output from the output terminal of a predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cb without reset function when + 12V is applied to the anode terminal of the photocoupler PIC74 via the resistor PR85. When the signal logic is LOW, the photocoupler PIC74 is turned on. Therefore, the voltage applied to the collector terminal of the photocoupler PIC74 is pulled down to the ground (GND) side, and the PRDY whose logic is LOW is the CR unit. 6 built-in control device. On the other hand, when + 12V is applied to the anode terminal of the photocoupler PIC74 via the resistor PR85, it is output from the output terminal of a predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cb without reset function. When the logic of the PRDY signal is HI, the photocoupler PIC74 is turned OFF, so that the voltage applied to the collector terminal of the photocoupler PIC74 is pulled up to the predetermined voltage VL by the pull-up resistor PR86, and the logic becomes HI. The PRDY is input to the built-in control device of the CR unit 6. Thus, the logic of PRDY output from the collector terminal of the photocoupler PIC74 is the logic of the PRDY signal output from the output terminal of the predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cb without reset function. It has the same logic.

[10-2-6. Various input / output signals to payout control MPU]
Next, various input / output signals input / output from the input / output terminals of the various input / output ports of the payout control MPU 4120a will be described.

  The RXD terminal, which is the serial data input terminal of the serial input port of the payout control MPU 4120a, receives serial data from the main control board 4100 as a main pay serial data reception signal via the payout control input circuit 4120b as shown in FIG. Is done. On the other hand, from the TXD terminal which is a serial data output terminal of the serial output port of the payout control MPU 4120a, serial data to be sent to the main control board 4100 is sent as a payer serial data transmission signal to the payout control output circuit 4120cb without reset function. A payer serial data transmission signal is transmitted from the payout control output circuit 4120cb having no reset function to the main control board 4100.

  Each input terminal of the predetermined input port of the payout control MPU 4120a has the above-described RWMCLR signal, payout blackout signal, door open signal, full signal, various signals from the CR unit 6 (BRQ signal, BRDY signal, CR connection) For example, a main pay ACK signal from the main control board 4100 that informs the completion of normal reception of the payer serial data reception signal is sent via the payout control input circuit 4120b. 15, detection signals from the ball break switch 750, the count switch 751, the rotation angle switch 752, and the like shown in FIG. 15 are input via the payout control input circuit 4120 b, and the potentiometer shown in FIG. An operation signal from the meter 512, the touch switch 516, the firing stop switch 518, and the like shown in FIG. Detection signal is power supply board 851 from Tan switch 550 etc., and the like or are input via the payout control input circuit 4120b payout control board 4100.

  On the other hand, the EXS signal and the PRDY signal described above are output from the output terminals of the predetermined output port of the payout control MPU 4120a to the payout control output circuit 4120cb without reset function, respectively, and the EXS signal from the payout control output circuit 4120cb without reset function and The PRDY signal is output to the CR unit input / output circuit 4120e, or the voltage switching signal described above is output to the payout control output circuit 4120ca with reset function, and the voltage switching signal is output from the payout control output circuit 4120ca with reset function to the voltage switching circuit 4120da. Or outputs a payout motor drive signal to the payout control output circuit 4120ca with reset function, and outputs a payout motor drive signal from the payout control output circuit 4120ca with reset function to the payout motor 744 via the payout motor drive circuit 4120d. In addition, for example, a payer ACK signal for notifying completion of normal reception of the main payment serial data reception signal described above is output to the payout control output circuit 4120ca with reset function, and the payout control output circuit 4120ca with reset function pays off. The main ACK signal is output to the main control board 4100, or the drive signal of the error LED indicator 860b shown in FIG. 15 is output to the payout control output circuit 4120ca with reset function to drive the drive signal from the payout control output circuit 4120ca with reset function. Is output to the error LED indicator 860b, or a control signal for adjusting the drive current to the firing solenoid drive circuit 858 shown in FIG. 15 is output to the payout control output circuit 4120ca with a reset function to output a payout control output circuit with a reset function. Outputs drive current from 4120ca to firing solenoid 654 15 outputs a control signal for adjusting the drive current to the ball feed solenoid drive circuit 859 shown in FIG. 15 to the payout control output circuit 4120ca with reset function, and sends the drive current from the ball feed solenoid output circuit 4120ca with reset function to the ball feed solenoid. Output to 585 or the like.

[10-3. Various input / output signals with the main control board and various output signals to the external terminal board]
Next, various input / output signals between the payout control board 4110 and the main control board 4100 and various output signals from the payout control board 4110 to the external terminal board 784 will be described with reference to FIG.

[10-3-1. Various input / output signals with the main control board]
The payout control board 4110 exchanges various input / output signals with the main control board 4100. Specifically, as shown in FIG. 32 (a), the payout control board 4110 has the above-described payer serial data transmission signal, payer ACK signal, operation signal (RAM clear signal), main frame door open signal, and the like. Is output to the main control board 4100. These output signals are pulled up to + 12V by the pull-up resistor of the main control input circuit 4100b of the main control board 4100.

  On the other hand, in addition to the main payment serial data reception signal, the main payment ACK signal, and the operation signal (RAM clear signal), the payout control board 4110 has a 15 round big hit information output signal, a two round big hit information output signal, etc. Jackpot information output signal, probabilistic fluctuation information output signal, special symbol display information output signal, normal symbol display information output signal, short and middle information output signal, start opening prize information output signal, etc. A signal or the like is input from the main control board 4100. These input signals are pulled up to the + 12V side by the pull-up resistor of the payout control input circuit 4120b of the payout control unit 4120 of the payout control board 4110.

[10-3-2. Various output signals to external terminal board]
The payout control board 4110 outputs various signals to the external terminal board 784. Specifically, as shown in FIG. 32B, in addition to the above-described outer frame door opening information output signal, the number of game balls actually paid out by the payout motor 744 as prize balls reaches 10 balls. Winning ball number information output signal output every time, 15 round jackpot information output signal and 2 round jackpot information output signal via main control board 4100 through payout control board 4110, information output during probability variation A game information signal such as a signal, a special symbol display information output signal, a normal symbol display information output signal, a short time information output signal, and a start opening prize information output signal is output to the external terminal board 784. These output signals are pulled up to the + 12V side by the pull-up resistor of the external terminal board 784.

  In addition to the various signals described above being input to the external terminal board 784, as shown in FIG. 32 (b), a main prize ball number information output signal and a power saving mode information output signal from the peripheral control board 4140 are provided. Is entered. Briefly explaining the main prize ball number information output signal, the main control board 4100 is provided with a first start port 2101, a second start port 2102, a general winning port 2104, 2201 shown in FIG. , And the number of game balls scheduled to be paid out as prize balls based on the game balls entered in various winning openings such as the grand prize opening 2103 (in this embodiment, 10 balls are set). In order to convey the fact each time the value reaches (1)), a main prize ball number information output command to be described later is transmitted to the peripheral control board 4140, and the peripheral control board 4140 is based on the received main prize ball number information output command. Based on the game balls entered in various winning ports such as the first starting port 2101, the second starting port 2102, the general winning ports 2104 and 2201, and the big winning port 2103, it is paid out as a winning ball Each time the number of game balls to be played reaches a predetermined number of balls (in this embodiment, 10 is set), the main prize ball number information output signal is used as the main prize ball number information. The data is output to the external terminal board 784 and transmitted to the hall computer. The main prize ball number information output signal is pulled up to the + 12V side by the pull-up resistor of the external terminal board 784.

  Next, the power saving mode information output signal will be briefly described. The peripheral control board 4140 is based on the power consumption status history information stored and held in the power consumption status history RAM 4150f shown in FIG. The status of the transition to power saving mode at the time of power recovery that suppresses the power consumed by the pachinko gaming machine 1 by grasping the power status consumed by the pachinko gaming machine 1 at the time of power recovery when the power is turned off (immediately before the power is turned off) This is transmitted to the hall computer via the terminal board 784. Specifically, the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 shown in FIG. 17 performs the power saving power transition mode transition determination process in the power-on process of the peripheral control unit, which will be described later. Based on the power consumption status history information stored and held in the consumption status history RAM 4150f, the power status consumed by the pachinko gaming machine 1 when the power is turned off (immediately before the power is turned off) (the power consumption suppression stage described later) is specified. It is determined whether or not to enter the power saving mode during power recovery. The peripheral control MPU 4150a outputs a power saving mode information output signal to the external terminal board 784 as power saving mode information to notify the hall computer when the determination result does not shift to the power saving mode at the time of power recovery. When shifting to the power saving mode at the time of power recovery, a power saving mode information output signal is output to the external terminal board 784 as power saving mode information to inform the hall computer. This power saving mode information output signal is pulled up to + 12V by the pull-up resistor of the external terminal board 784.

  That is, the external terminal board 784 outputs two signals, that is, an outer end frame door opening information output signal from the payout control board 4110 side and a prize ball number information output signal, and a 15 round big hit from the main control board 4100 side. There are seven signals: an information output signal, a 2-round jackpot information output signal, a probability changing information output signal, a special symbol display information output signal, a normal symbol display information output signal, a short time medium information output signal, and a start opening prize information output signal. Two signals, that is, a main prize ball number information output signal and a power saving mode information output signal from the peripheral control board 4140 side are output through (passing through) the payout control board 4110.

  A signal output from the external terminal board 784 is transmitted to a hall computer installed in a game hall (hall) (not shown), and the hall computer monitors a player's game and the like. When the 15 round jackpot information output signal or the 2 round jackpot information output signal is output to the hall computer as one jackpot information output signal, the hall computer counts the number of jackpots (two round jackpots). And the number of jackpots with 15 rounds (number of jackpots for 15 rounds) is the sum of the number of jackpots of the pachinko gaming machine 1. For this reason, since the hall computer cannot grasp the number of occurrences of 2 rounds of big hits and the number of occurrences of 15 land big hits from the total number of big hits, the number of big hits actually generated in the pachinko gaming machine 1 is large. However, it is not possible to grasp whether it is a big hit of 2 rounds or a big hit of 15 rounds. In addition, a data counter (not shown) is arranged above the pachinko gaming machine 1, and a player determines whether or not to play a game with reference to the number of occurrences of the big hit gaming state displayed on the data counter. Some people choose.

  However, the number of occurrences of the jackpot gaming state displayed in the data counter may actually be biased to the number of occurrences of two rounds of big hits. 15 round hits may not occur easily. As described above, the number of occurrences of the jackpot gaming state displayed on the data counter can give the player a sense of expectation, but may cause the player to be more eager than necessary.

  Therefore, in the present embodiment, as the jackpot information output signal, the 15 round jackpot information output signal and the two round jackpot information output signal are separately output to the hall computer, so that the hall computer can generate the number of occurrences of the two round jackpot, The number of occurrences of 15 round big hits can be accurately grasped. Therefore, the hall computer can grasp whether the number of big hits actually generated in the pachinko gaming machine 1 is a big hit of two rounds or a big hit of 15 rounds. Since the number of occurrences of big hits for rounds and the number of occurrences of big hits for two rounds can be displayed separately or only the number of occurrences of big hits for 15 rounds can be displayed as the number of occurrences of big hit gaming status, Nor.

  In the present embodiment, the 2-round jackpot information output signal is output to the hall computer in the period from when the 2-round jackpot is generated until it is finished, and the 15-round jackpot information output signal is also a 15-round jackpot. It is in a state of being output to the hall computer during the period from occurrence to termination. In addition to the method of outputting the 2-round jackpot information output signal and the 15-round jackpot information output signal to the hall computer as in the present embodiment, for example, when a 2-round jackpot occurs, the 2-round jackpot information output signal is output only for a predetermined period. When the 15 round jackpot is generated and the 15 round jackpot information output signal is output to the hall computer for a predetermined period when the 15 round jackpot occurs, such a 2 round jackpot information output signal and 15 round jackpot information are output. A method of outputting the output signal to the hall computer for the same predetermined period can also be mentioned.

[11. Output terminal arrangement of external terminal board]
Next, the arrangement of the output terminals of the external terminal board 784 that outputs various signals to the hall computer installed in the game hall (hall) will be described with reference to FIG. The external terminal plate 784 is attached to the rear surface of the prize ball base 710 attached to the rear surface of the main body frame base 600 shown in FIG. 3, and the rear side is covered with the external terminal plate cover 786. FIG. 33 is a diagram showing an arrangement of output terminals of the external terminal board.

  As described above, the external terminal board 784 includes the outer frame door opening information output signal, the prize ball number information output signal, the 15 round jackpot information output signal and the 2 round jackpot information output signal, and the probability changing An information output signal, a special symbol display information output signal, a normal symbol display information output signal, a short time medium information output signal, and a start opening prize information output signal are input from the payout control board 4110, and a main prize ball number information output signal, The power saving mode information output signal is input from the peripheral control board 4140, and these various signals are output to the outside of the pachinko gaming machine 1. The hall computer is electrically connected to the external terminal board 784 so that a signal larger than the minimum detection signal width (for example, a signal width of 60 ms) can be detected as various signals from the external terminal board 784. It has become.

  Briefly explaining these various signals, the outer end frame door opening information output signal is not generated during a normal game by a player that the door frame 5 and / or the main body frame 3 shown in FIG. 1 is opened. The signal indicating that a state has occurred. The prize ball number information output signal is displayed every time the number of game balls actually paid out by the payout motor 744 shown in FIG. 5 reaches 10 balls. The main prize-ball number information output signal is a signal indicating the effect, and various prize-winning openings such as the first starting opening 2101, the second starting opening 2102, the general winning opening 2104, 2201, and the big winning opening 2103 shown in FIG. This is a signal to notify that every time the number of game balls scheduled to be paid out as prize balls reaches 10 on the basis of the game balls that entered the ball, ) In pachinko machine 1 It is a signal that tells the state of power spent at the time of power recovery and informs the state of transition to the power saving mode during power recovery that suppresses power consumed by the pachinko machine 1, and 15 rounds jackpot information output signal is 15 rounds The signal that tells that a big hit is occurring, the 2-round jackpot information output signal is a signal that tells that a two-round jackpot has occurred, and the information output signal during probability variation is The signal indicating that the probability variation is occurring. The special symbol display information output signal is specially displayed on the upper special symbol display 1185 and the lower special symbol display 1186 shown in FIG. The signal indicating that the symbol variation display is finished (stopped), and the normal symbol display information output signal is a normal symbol display on the function display board 1191 shown in FIG. 189 is a signal indicating that the normal symbol variation display has been completed (stopped), and the time-short-time information output signal is a signal indicating that a time-short state has occurred, and the start opening winning information output signal Is a signal to notify that every time a game ball enters the first start port 2101 or the second start port 2102 shown in FIG.

  On the external terminal plate 784, as shown in FIG. 33, output terminals PT1 to PT11 are arranged horizontally in a row. The output terminal PT1 is provided in white and outputs an award ball number information output signal. As described above, the award ball number information output signal is a signal to notify that every time the number of game balls actually paid out as award ball by the payout motor 744 shown in FIG. In the embodiment, the output terminal PT1 is set to 0.106 seconds (in this embodiment, 2 ms is set as an interrupt cycle when a payout control unit timer interrupt process described later is performed, so an output period of 0.106 seconds (that is, The signal width of the award ball number information output signal output from the output terminal PT1) is output during a period in which the payout control unit timer interrupt process is repeated 53 times) based on an interrupt period of 2 ms). ing. When the prize ball number information output signal from the external terminal board 784 is input to the hall computer, the hall computer outputs the prize motor 744 of the pachinko gaming machine 1 as a prize ball every time the prize ball number information output signal is input. It is possible to grasp that 10 game balls have been paid out as prize balls, and to count the number of game balls that have been paid out and to grasp the total number of game balls paid out by the pachinko gaming machine 1 it can.

  The output terminal PT2 is provided in green and outputs an outer end frame door opening information output signal. As described above, the outer end frame door opening information output signal has a state in which the player does not generate a normal game when the door frame 5 and / or the main body frame 3 shown in FIG. 1 is opened. In this embodiment, the signal is output while the door frame 5 and / or the main body frame 3 are opened from the output terminal PT2. When the outer end frame door opening information output signal from the external terminal board 784 is input to the hall computer, the hall computer outputs the door frame 5 of the pachinko gaming machine 1 while the outer end frame door opening information output signal is input. And / or it can grasp | ascertain that the main body frame 3 is open | released.

  The output terminal PT3 is provided in gray and outputs a special symbol display information output signal. As described above, the special symbol display information output signal is displayed in a state where the special symbol variation display is ended (stopped) by the upper special symbol display 1185 and the lower special symbol display 1186 shown in FIG. In this embodiment, the signal is 0.128 at the time of termination (stop) of the special symbol variation display on the function display board 1191 from the output terminal PT3 on the upper special symbol display 1185 or the lower special symbol display 1186. It is output for 2 seconds. When the special symbol display information output signal from the external terminal board 784 is input to the hall computer, the hall computer receives the special symbol display information output signal, and then the upper special symbol on the function display board 1191 of the pachinko gaming machine 1. The display 1185 and the lower special symbol display 1186 can grasp that the variation display of the special symbol has ended (stopped), and the upper special symbol of the function display board 1191 of the pachinko gaming machine 1 is counted by counting the number of times. The total number of times the special symbol is variably displayed on the display 1185 or the lower special symbol display 1186 can be grasped.

  The output terminal PT4 is yellow and outputs a start opening winning information output signal. As described above, the start opening winning information output signal is a signal to notify that every time a game ball enters the first start opening 2101 or the second start opening 2102 shown in FIG. Each time a game ball enters the first start port 2101 or the second start port 2102 from the output terminal PT4, it is output for 0.128 seconds. When the start port winning information output signal from the external terminal board 784 is input to the hall computer, the hall computer receives the first start port 2101 or the first start port 2101 of the pachinko gaming machine 1 every time the start port winning information output signal is input. 2 It is possible to grasp that a game ball has entered the start port 2102 and count the number of times the start port winning information output signal is input to count the first start port 2101 or the second start port of the pachinko gaming machine 1 The total number of game balls entered in 2102 can be grasped.

  The output terminal PT5 is black and outputs a 15 round big hit information output signal. As described above, the 15 round jackpot information output signal is a signal that indicates that the 15 round jackpot has occurred. In this embodiment, while the 15 round jackpot is being generated from the output terminal PT5, It is output. When the 15 round jackpot information output signal from the external terminal board 784 is input to the hall computer, the hall computer generates 15 round jackpots in the pachinko machine 1 while the 15 round jackpot information output signal is input. The number of times that the 15 round jackpot information output signal has been input can be counted, and the total number of times that 15 round jackpots have occurred in the pachinko gaming machine 1 can be determined.

  The output terminal PT6 is colored pink and outputs a 2-round jackpot information output signal. As described above, the 2-round jackpot information output signal is a signal that indicates that the 2-round jackpot has occurred. In the present embodiment, while the 2-round jackpot is being generated from the output terminal PT6, It is output. When a 2-round jackpot information output signal from the external terminal board 784 is input to the hall computer, the hall computer generates a 2-round jackpot on the pachinko machine 1 while the 2-round jackpot information output signal is being input. It is possible to grasp the total number of occurrences of two round big hits in the pachinko gaming machine 1 by counting the number of times the two round big hit information output signal is input.

  The output terminal PT7 is provided in blue and outputs a normal symbol display information output signal. As described above, the normal symbol display information output signal is a signal that informs that the normal symbol change display is finished (stopped) on the normal symbol display 1189 of the function display board 1191 shown in FIG. In this embodiment, the output is performed for 0.128 seconds from the output terminal PT7 when the normal symbol variation display 1189 of the function display board 1191 is ended (stopped). When the normal symbol display information output signal from the external terminal board 784 is input to the hall computer, the hall computer displays the normal symbol display on the function display board 1191 of the pachinko gaming machine 1 when the normal symbol display information output signal is input. It is possible to grasp that the fluctuation display of the normal symbol is finished (stopped) in the device 1189, and the number of times is counted to display the fluctuation of the normal symbol on the normal symbol display 1189 of the function display board 1191 of the pachinko gaming machine 1. Can grasp the total number of times.

  The output terminal PT8 is provided in red and outputs an information output signal for a short time. As described above, the time reduction / medium information output signal is a signal indicating that a time reduction state has occurred, and in the present embodiment, the signal is output from the output terminal PT8 while the time reduction state is occurring. ing. When the time and medium information output signal from the external terminal board 784 is input to the hall computer, the hall computer grasps that the time and time state has occurred in the pachinko gaming machine 1 when the time and medium information output signal is input. In addition, the total number of times that the time-saving state has occurred in the pachinko gaming machine 1 can be grasped by counting the number of times the time-short-time information output signal is input.

  The output terminal PT9 is provided with an orange color and outputs a probability changing information output signal. As described above, the probability variation in-progress information output signal is a signal that informs that the probability variation is occurring. In this embodiment, the signal is output while the probability variation is occurring from the output terminal PT9. It has become so. When the information output signal during probability variation from the external terminal board 784 is input to the hall computer, the hall computer is in a state where probability variation occurs in the pachinko gaming machine 1 when the information output signal during probability variation is input. And the total number of times the probability variation has occurred in the pachinko gaming machine 1 can be grasped by counting the number of times the information output signal during probability variation is input.

  The output terminal PT10 is light blue and outputs a main prize ball number information output signal. As described above, the main prize ball number information output signal is based on a command (main prize ball number information output command described later) from the main control board 4100, and the first start port 2101 and the second start shown in FIG. Each time the number of game balls scheduled to be paid out as prize balls reaches 10 on the basis of game balls that have entered the winning holes such as the mouth 2102, the general winning holes 2104, 2201, and the grand prize opening 2103 In this embodiment, this signal is output from the output terminal PT10 for 0.128 seconds (payout control unit timer interrupt processing described later in this embodiment as an interrupt cycle when peripheral control unit 1 ms timer interrupt processing described later is performed. Is set to 1 ms, unlike the interrupt cycle (2 ms) when the output is performed. The signal width of the main winning ball number information output signal) is output during a period in which the peripheral control unit 1 ms timer interrupt process is repeated 128 times based on an interrupt period of 1 ms). . When the main prize ball number information output signal from the external terminal board 784 is input to the hall computer, the hall computer receives 10 pachinko gaming machines 1 as prize balls each time the main prize ball number information output signal is input. The number of game balls to be paid out by the pachinko gaming machine 1 can be determined by counting the number of game balls to be paid out. Can be grasped. Based on a command from the main control board 4100 (main prize ball number information output command described later), for example, the first start port 2101, the second start port 2102, the general winning ports 2104, 2201, the big winning port 2103, etc. When the number of game balls scheduled to be paid out as prize balls reaches 20 or more based on the game balls entered in the various prize winning openings and the main prize ball number information output signal is output a plurality of times, the main prize The external terminal board 784 is spaced from the peripheral control board 4140 with an interval of 0.128 seconds so that the ball number information output signal is 0.256 (= 0.128 seconds × 2 times) for one continuous signal. Is output.

  The output terminal PT11 is provided in yellow green to output a power saving mode information output signal. As described above, the power saving mode information output signal is generated when the power is turned off (immediately before the power is turned off) based on the power consumption status history information stored in the power consumption status history RAM 4150f shown in FIG. The peripheral control MPU 4150a shown in FIG. 17 grasps the power state consumed by the pachinko gaming machine 1 at the time of power recovery, and notifies the state of transition to the power saving mode during power recovery that suppresses the power consumed by the pachinko gaming machine 1. In this embodiment, in the state of shifting to the power saving power saving mode, in this embodiment, the power saving power saving mode state maintaining period, which is the upper limit time described later, from the output terminal PT11 is 5 minutes (peripheral control unit 1 ms timer interrupt described later) In this embodiment, an interrupt cycle when a payout control unit timer interrupt process (to be described later) is performed (as an interrupt cycle when processing is performed) The output period of 5 minutes (300 seconds) (that is, the signal width of the power saving mode information output signal output from the output terminal PT11) is set based on the interrupt cycle of 1 ms. The control unit 1 ms timer interruption process is repeated for 300,000 times).

  Among the output terminals PT1 to PT11 of the external terminal plate 784, the output terminals PT1 and PT2 output various signals output on the payout control board 4110 side, and the output terminals PT3 to PT9 output on the main control board 4100 side. The various signals are output (passed) through the payout control board 4110, and the output terminals PT10 and PT11 are arranged so that signals output on the peripheral control board 4140 side are output. Each of the output terminals PT1 to PT11 is colored, and by electrically connecting wirings having connectors colored in the same colors as these colors to the output terminals PT1 to PT11, the other wirings are mistakenly electrically connected. Connection can be prevented. The payout control board 4110 does not mix various signals output on the payout control board 4110 side, various signals output on the main control board 4100 side, and signals output on the peripheral control board 4140 side. Output terminals PT1 and PT2 for transmitting various signals output on the side to the hall computer are arranged in a line on the left side of the external terminal board 784, and for transmitting various signals output on the main control board 4100 side to the hall computer. The output terminals PT3 to PT9 are arranged in a row from the center left side to the right side of the external terminal board 784, and the output terminals PT10 and PT11 for transmitting signals output on the peripheral control board 4140 side to the hall computer are external terminal boards. The output terminals PT1 to PT11 are arranged on the right side of 784. By arranging them in a line, the wiring for transmitting various signals output on the payout control board 4110 side to the hall computer and the various signals output on the main control board 4100 side are also transferred to the hall computer. It is possible to prevent an erroneous electrical connection between the wiring for transmitting to the wiring and the wiring for transmitting a signal output on the peripheral control board 4140 side to the hall computer.

  In the present embodiment, the prize ball number information output signal output on the payout control board 4110 side and the main prize ball number information output signal output on the peripheral control board 4140 side are respectively transmitted from the external terminal board 784 to the hall. It is configured to communicate to a computer. This is because, for example, the game balls stored in the prize ball tank 720 are not supplied to the prize ball tank 720 shown in FIG. 1 due to some trouble in the pachinko island equipment. If the 15-round big hit happens to happen in the pachinko gaming machine 1 at the time when there is a short remaining, the number of game balls stored in the prize ball tank 720 for paying out game balls as prize balls will be insufficient. (For example, if a clogged ball or a ball is generated in the prize ball device 740, the game ball cannot be paid out unless it can be eliminated). Then, the prize ball number information output signal output on the payout control board 4110 side is, as described above, the number of game balls actually paid out as prize balls by the payout motor 744 shown in FIG. 5 reaches 10 balls. Since it is a signal to notify that every time, it becomes impossible to pay out the game ball, so that the payout control board 4110 outputs a prize ball number information output signal to the hall computer via the external terminal board 784. become unable. When the game ball is not paid out, the player calls a hall clerk or the like. The hall clerk, for example, checks the position of the ball clogging by checking a hose-like supply nozzle for supplying game balls from the Pachinko Island facilities to the prize ball tank 720 (for example, in the prize ball device 740) When the generated ball clogging position and the position of the ball clogging are identified and resolved, the game ball is returned to a state where it is paid out.

  However, even if the hall clerk etc. is working, the game by the main control board 4100 is in progress, and after the big round of 15 rounds is finished, the game ball is paid out by the work of the hall clerk etc. Returning to the state, the payout control board 4110 pays out unpaid game balls one after another, and the payout control board 4110 is in a period when the 15th round big hit ends and the 15th round big hit has not occurred. Outputs an award ball number information output signal indicating that every time the number of game balls actually paid out by the payout motor 744 reaches 10 balls, and transmits it to the hall computer via the external terminal board 784. It will be. Then, in spite of the fact that 15 rounds of big hits have not occurred, an extremely large number of game balls will be paid out. Therefore, the gaming state of the pachinko gaming machine 1 and the game balls paid out by the pachinko gaming machine 1 There arises a problem that the hall computer cannot accurately grasp the relationship between the number of balls.

  Therefore, in this embodiment, regardless of whether or not the payout motor 744 is driven and controlled by the payout control board 4110 and is actually paid out as a prize ball, that is, different from the prize ball number information output signal output by the payout control board 4110. As shown in FIG. 8, the main control board 4100 receives game balls that have entered the various winning holes such as the first starting port 2101, the second starting port 2102, the general winning ports 2104 and 2201, and the big winning port 2103 shown in FIG. Each time the number of game balls scheduled to be paid out as prize balls reaches 10 on the basis of this, a command (main prize ball number information output command to be described later) is transmitted to the peripheral control board 4140, and the peripheral control board is transmitted. Reference numeral 4140 denotes a first start port 2101, a second start port 2102, a general winning port 21 based on the received command (a main prize ball number information output command to be described later). Main winning ball number information every time the number of game balls to be paid out as prize balls reaches 10 on the basis of game balls entered in various winning holes such as 4,2201, and the big winning hole 2103 As the main prize ball number information output signal, a mechanism for outputting the signal to the external terminal board 784 and transmitting it to the hall computer is adopted. As a result, even if the above-described troubles (troubles such as clogging of the refilling nozzle or the like, clogging of the ball in the prize ball device 740, or ball clogging) occur, the gaming state of the pachinko gaming machine 1 and this gaming state It is possible to accurately convey the relationship between the number of game balls to be paid out and the hall computer. Therefore, the hall computer can accurately grasp the relationship between the gaming state of the pachinko gaming machine 1 and the number of game balls to be paid out in the gaming state.

[12. Circuit of LCD output board]
Next, the circuit of the liquid crystal output substrate 3420 shown in FIG. 19 will be described with reference to FIGS. First, the configuration of the liquid crystal output substrate will be described, followed by the configuration of various light guide plate control circuits and the game board side VDP control target decoration LED control circuit. 34 is a block diagram of the liquid crystal output board, FIG. 35 is a diagram showing the correspondence between various serial controllers and output destinations in the game board side signal separation control circuit, and FIG. 36 is a block diagram of various light guide plate control circuits. FIG. 37 is a block diagram of the game board side VDP control target decoration LED control circuit.

[12-1. Configuration of LCD output board]
The built-in sound source VDP 4160a of the liquid crystal and sound control unit 4160 on the peripheral control board 4140 includes light guide plate information and electrical decorations on the game board side drawing data of the screen drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). Drawing data is generated in the game board side display area VRGN1 provided on the built-in VRAM as information attached according to a predetermined game board side generation rule, and is output from the channel CH1. As described above, when the drawing data output from the channel CH1 is transmitted to the liquid crystal output board 3420 by the LVDS system, the RGB conversion circuit 3420f of the liquid crystal output board 3420 is based on the signal transmitted by the LVDS system. Are converted into parallel signals. As described above, the parallel signal is composed of three video signals such as a red video signal, a green video signal, and a blue video signal, and three synchronization signals such as a horizontal synchronization signal, a vertical synchronization signal, and a clock signal. ing.

  The RGB conversion circuit 3420f converts the drawing data output from the channel CH1 into a parallel signal (that is, a red video signal that is drawing data output from the channel CH1 of the sound source built-in VDP 4160a) based on a signal transmitted by the LVDS method. 3 video signals of green video signal and blue video signal and 3 sync signals of horizontal sync signal, vertical sync signal, and clock signal) and output to the game board side signal separation control circuit 3420g.

  As shown in FIG. 34, the game board-side signal separation control circuit 3420g includes a signal separation unit 3420ga, a buffer memory 3420gb, a distribution output control unit 3420gc, a first serial controller 3420gd1 to an eleventh serial controller 3420gd11. . When the parallel signal converted by the RGB conversion circuit 3420f is input, it is input to the signal separation unit 3420ga.

  The signal separation unit 3420ga includes a first resolution conversion unit 3420gaa and a second resolution conversion unit 3420gab. The first resolution conversion unit 3420gaa is the game board side drawing data for the game board side effect display unit 1900 (liquid crystal panel 5000e) from the drawing data converted into the parallel signal. The red video signal, the green video signal, and the blue video The game board side drawing data is separated from the drawing data converted into the parallel signal by cutting out three video signals called signals and three synchronizing signals called horizontal synchronizing signals, vertical synchronizing signals, and clock signals. The second resolution conversion unit 3420gab outputs to the game board side liquid crystal drive circuit 3420h of the output board 3420, while the second resolution conversion unit 3420gab uses a plurality of light guide plates provided in the game board side effect display unit 1900 from drawing data converted into parallel signals. Light guide plate information for selecting one light guide plate and VD with built-in sound source among the decorative boards of the game board 4 4160a is converted into a parallel signal by cutting out electrical decoration information for a plurality of LEDs (decorative LEDs) provided on each of the plurality of game board side VDP control target decorative boards that are controlled by 4160a. The light guide plate information and the illumination information are separated from the drawn data and output to the buffer memory 3420gb to perform the writing operation.

  In other words, the first resolution conversion unit 3420gaa is generated from the drawing data converted into the parallel signal into the game board side drawing data area VRGN1a of the game board side display area VRGN1 provided in the built-in VRAM of the sound source built-in VDP 4160a. By cutting out the game board side drawing data, the game board side drawing data can be separated from the drawing data converted into parallel signals and output to the game board side liquid crystal drive circuit 3420h of the liquid crystal output board 3420. The second resolution conversion unit 3420gab generates, as drawing data, from the drawing data converted into the parallel signal into the game board side accompanying information area VRGN1b of the game board side display area VRGN1 provided on the built-in VRAM of the sound source built-in VDP 4160a. Cut out light guide plate information and illumination information More, in which can be output to the buffer memory 3420gb separates the light guide plate information and decorative illumination information from the drawing data converted into parallel signals performs a write operation.

  In the present embodiment, the game board side drawing data generated in the game board side drawing data area VRGN1a of the game board side display area VRGN1 provided in the built-in VRAM of the sound source built-in VDP 4160a is provided in the game board side effect display unit 1900. Since the resolution matches the resolution of the liquid crystal panel 5000e (12 inches having an image size of 800 × 600 dots), the first resolution conversion unit 3420gaa does not perform the enlargement or reduction process, and the extracted drawing data on the game board side. The data is output to the game board side liquid crystal drive circuit 3420h of the liquid crystal output board 3420 as it is. The game board side drawing data generated in the game board side drawing data area VRGN1a of the game board side display area VRGN1 provided in the built-in VRAM of the sound source built-in VDP 4160a is the liquid crystal panel 5000e provided in the game board side effect display unit 1900. If the resolution does not match (12 inches having an image size of 800 × 600 dots), the first resolution conversion unit 3420gaa enlarges or reduces the cut-out game board drawing data so as to match. The processing is performed and output to the game board side liquid crystal drive circuit 3420h of the liquid crystal output board 3420.

  In the present embodiment, the light guide plate information and the decoration information generated as drawing data in the game board side accompanying information area VRGN1b of the game board side display area VRGN1 provided on the built-in VRAM of the sound source built-in VDP 4160a are stored in the buffer memory 3420gb. Therefore, the second resolution conversion unit 3420gab outputs the cut light guide plate information and the illumination information as they are to the buffer memory 3420gb without performing the enlargement or reduction process, and performs the writing operation.

  The buffer memory 3420gb is configured as a double buffer memory including a first buffer memory 3420gb1 and a second buffer memory 3420gb2, and one of the first buffer memory 3420gb1 and the second buffer memory 3420gb2 is written. When the operation is in progress, the contents already written in the other buffer memory are read from the distribution output control unit 3420gc. The distribution output control unit 3420gc distributes the light guide plate information and the illumination information read from the buffer memory to the first serial controller 3420gd1 and the second serial controller 3420gd2 according to a predetermined game board side generation rule. The illumination information is distributed to the third serial controller 3420gd3 to the eleventh serial controller 3420gd11.

  The first serial controller 3420gd1 and the second serial controller 3420gd2 output light guide plate information to the first light guide plate control circuit 3420k1 to the sixth light guide plate control circuit 3420k6 constituting the various light guide plate control circuits 3420k, and the third serial controller. The controller 3420gd3 to the eleventh serial controller 3420gd11 are a game board side VDP control target decoration LED control circuit 3420i constituting a game board side VDP control target decoration LED control circuit 3420i, and a game board side VDP control target 27th The illumination information is output to the decoration LED control circuit 3420i27.

  Specifically, as shown in FIG. 35, the first serial controller 3420gd1 uses a light guide plate information as serial data SDAT1 and a first light guide plate control circuit 3420k1, a second light guide plate control circuit 3420k1, which will be described later, based on a clock signal SCLK1. The light is output to the light guide plate control circuit 3420k2 and the third light guide plate control circuit 3420k3. The first light guide plate control circuit 3420k1, the second light guide plate control circuit 3420k2, and the third light guide plate control circuit 3420k3 are electrically connected as one serial connection (one serial system). Yes.

  As shown in FIG. 35, the second serial controller 3420gd2 uses a light guide plate information as serial data SDAT2 and a fourth light guide plate control circuit 3420k4, a fifth light guide plate control circuit 3420k5, which will be described later, based on the clock signal SCLK2. It outputs to the 6th light-guide plate control circuit 3420k6. The fourth light guide plate control circuit 3420k4, the fifth light guide plate control circuit 3420k5, and the sixth light guide plate control circuit 3420k6 are electrically connected as one serial connection (one serial system). Yes.

  As shown in FIG. 35, the third serial controller 3420gd3 is a game board side VDP control target first decoration LED control circuit 3420i1, game board based on the clock signal SCLK3 with the decoration information as serial data SDAT3. To the side VDP control target second decoration LED control circuit 3420i2 and the game board side VDP control target third decoration LED control circuit 3420i3. The game board side VDP control target first decoration LED control circuit 3420i1, the game board side VDP control target second decoration LED control circuit 3420i2, and the game board side VDP control target third decoration LED control circuit 3420i3 are 1 The circuit configuration is electrically connected as one serial connection (one serial system).

  As shown in FIG. 35, the fourth serial controller 3420gd4 uses the decoration information as serial data SDAT4 and based on the clock signal SCLK4, which will be described later, a game board side VDP control target fourth decoration LED control circuit 3420i4, game board To the side VDP control target fifth decoration LED control circuit 3420i5 and the game board side VDP control target sixth decoration LED control circuit 3420i6. The game board side VDP control target fourth decoration LED control circuit 3420i4, the game board side VDP control target fifth decoration LED control circuit 3420i5, and the game board side VDP control target sixth decoration LED control circuit 3420i6 are 1 The circuit configuration is electrically connected as one serial connection (one serial system).

  As shown in FIG. 35, the fifth serial controller 3420gd5 uses the decoration information as serial data SDAT5, based on the clock signal SCLK5, and will be described later, a game board side VDP control target seventh decoration LED control circuit 3420i7, game board Output to the side VDP control target eighth decoration LED control circuit 3420i8 and the game board side VDP control target ninth decoration LED control circuit 3420i9. The game board side VDP control target seventh decoration LED control circuit 3420i7, the game board side VDP control target eighth decoration LED control circuit 3420i8, and the game board side VDP control target ninth decoration LED control circuit 3420i9 are 1 The circuit configuration is electrically connected as one serial connection (one serial system).

  As shown in FIG. 35, the sixth serial controller 3420gd6 uses the decoration information as serial data SDAT6, based on the clock signal SCLK6, and will be described later on the game board side VDP control target tenth decoration LED control circuit 3420i10, game board To the side VDP control target eleventh decoration LED control circuit 3420i11 and the game board side VDP control target twelfth decoration LED control circuit 3420i12. The game board side VDP control target 10th decoration LED control circuit 3420i10, the game board side VDP control target 11th decoration LED control circuit 3420i11, and the game board side VDP control target 12th decoration LED control circuit 3420i12 are 1 The circuit configuration is electrically connected as one serial connection (one serial system).

  As shown in FIG. 35, the seventh serial controller 3420gd7 uses the decoration information as serial data SDAT7, based on the clock signal SCLK7, and will be described later on the game board side VDP control target thirteenth decoration LED control circuit 3420i13, game board To the side VDP control target fourteenth decoration LED control circuit 3420i14 and the game board side VDP control target fifteenth decoration LED control circuit 3420i15. The game board side VDP control target thirteenth decoration LED control circuit 3420i13, the game board side VDP control target fourteenth decoration LED control circuit 3420i14, and the game board side VDP control target fifteenth decoration LED control circuit 3420i15 are 1 The circuit configuration is electrically connected as one serial connection (one serial system).

  As shown in FIG. 35, the eighth serial controller 3420gd8 uses the decoration information as serial data SDAT8 and based on the clock signal SCLK8, the game board side VDP control target 16th decoration LED control circuit 3420i16, game board To the side VDP control target seventeenth decoration LED control circuit 3420i17 and the game board side VDP control target eighteenth decoration LED control circuit 3420i18. The game board side VDP control object 16th decoration LED control circuit 3420i16, the game board side VDP control object 17th decoration LED control circuit 3420i17, and the game board side VDP control object 18th decoration LED control circuit 3420i18 are 1 The circuit configuration is electrically connected as one serial connection (one serial system).

  As shown in FIG. 35, the ninth serial controller 3420gd9 uses, as will be described later, a game board side VDP control target nineteenth decoration LED control circuit 3420i19 based on the clock signal SCLK9 with the decoration information as serial data SDAT9, and the game board. To the side VDP control target 20th decoration LED control circuit 3420i20 and the game board side VDP control target 21st decoration LED control circuit 3420i21. The game board side VDP control target 19th decoration LED control circuit 3420i19, the game board side VDP control target 20th decoration LED control circuit 3420i20, and the game board side VDP control target 21st decoration LED control circuit 3420i21 are 1 The circuit configuration is electrically connected as one serial connection (one serial system).

  As shown in FIG. 35, the tenth serial controller 3420gd10 uses the decoration data as serial data SDAT10, based on the clock signal SCLK10, and will be described later on the game board side VDP control target 22th decoration LED control circuit 3420i22, game board To the side VDP control target 23rd decoration LED control circuit 3420i23 and the game board side VDP control target 24th decoration LED control circuit 3420i24. The game board side VDP control target 22nd decoration LED control circuit 3420i22, the game board side VDP control target 23rd decoration LED control circuit 3420i23, and the game board side VDP control target 24th decoration LED control circuit 3420i24 are 1 The circuit configuration is electrically connected as one serial connection (one serial system).

  As shown in FIG. 35, the eleventh serial controller 3420gd11 uses a decorating data as serial data SDAT11 and based on a clock signal SCLK11, the game board side VDP control target 25th decoration LED control circuit 3420i25, Output to the side VDP control target 26th decoration LED control circuit 3420i26 and game board side VDP control target 27th decoration LED control circuit 3420i27. The 25th decoration LED control circuit 3420i25 for the game board side VDP control object, the 26th decoration LED control circuit 3420i26 for the game board side VDP control object, and the 27th decoration LED control circuit 3420i27 for the game board side VDP control object are 1 The circuit configuration is electrically connected as one serial connection (one serial system).

  The game board side VDP control target first decoration LED control circuit 3420i1 to the game board side VDP control target 27th decoration LED control circuit 3420i27 is directly controlled by the built-in sound source VDP 4160a among the decoration boards of the game board 4. This is a circuit that can adjust the luminance (gradation) of a plurality of LEDs (decorative LEDs) provided on each of a plurality of game board side VDP control target decorative boards that are controlled.

  In this way, the drawing data output from the channel CH1 of the liquid crystal and sound source built-in VDP 4160a of the sound control unit 4160 in the peripheral control board 4140 is a screen drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). The game board side drawing data is generated in the game board side display area VRGN1 provided on the VRAM as light guide plate information and electrical decoration information attached in accordance with a predetermined game board side generation rule. The “predetermined game board side generation rule” means that in the game board side signal separation control circuit 3420g of the liquid crystal output board 3420, the first resolution converter 3420gaa of the signal separator 3420ga is provided in the built-in VRAM of the sound source built-in VDP 4160a. Game board side drawing data area V of the game board side display area VRGN1 The game board side is configured so that the drawing data on the game board side generated in the GN 1a can be accurately cut out, and the second resolution conversion unit 3420gab of the signal separation unit 3420ga is provided on the built-in VRAM of the sound source built-in VDP 4160a The light guide plate information and the illumination information generated as the drawing data can be accurately cut out in the game board side accompanying information area VRGN1b of the display area VRGN1, and the distribution output control unit 3420gc includes a buffer memory. The light guide plate information read from 3420gb can be accurately distributed to the first serial controller 3420gd1 and the second serial controller 3420gd2, respectively, and the illumination information read from the buffer memory 3420gb corresponds to the first information. 3 siri And it is configured to be able to accurately dispensed respectively in Le controller 3420gd3~ 11 serial controller 3420Gd11.

  Specifically, in the game board side signal separation control circuit 3420g of the liquid crystal output board 3420, the distribution output control unit 3420gc reads the first light guide plate control circuit 3420k1 and the second light guide plate control circuit read from the buffer memory 3420gb. The light guide plate information for the first light guide plate control circuit 3420k1 and the second light guide plate so that the light guide plate information for the 3420k2 and the third light guide plate control circuit 3420k3 can be accurately distributed to the first serial controller 3420gd1. The light guide plate information for the control circuit 3420k2 and the light guide plate information for the third light guide plate control circuit 3420k3 are attached to the game board side drawing data of the screen on which the game board side effect display unit 1900 (liquid crystal panel 5000e) is drawn (displayed). Game board provided on the VRAM It is generated on the game board side incidental information area VRGN1b of 示用 region VRGN1.

  The distribution output control unit 3420gc outputs the light guide plate information read from the buffer memory 3420gb to the fourth light guide plate control circuit 3420k4, the fifth light guide plate control circuit 3420k5, and the sixth light guide plate control circuit 3420k6 by the second serial controller. The light guide plate information for the fourth light guide plate control circuit 3420k4, the light guide plate information for the fifth light guide plate control circuit 3420k5, and the light guide plate for the sixth light guide plate control circuit 3420k6 so that it can be accurately distributed to 3420gd2. The information on the game board side of the game board side display area VRGN1 provided on the VRAM as information attached to the game board side drawing data of the screen on which the information is drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). It is generated in the information area VRGN1b.

  In addition, the distribution output control unit 3420gc provides the illumination information for the game board side VDP control target first decoration LED control circuit 3420i1 to the game board side VDP control target third decoration LED control circuit 3420i3 read from the buffer memory 3420gb. Electric decoration information for the game board side VDP control target first decoration LED control circuit 3420i1, the game board side VDP control target second decoration LED so that it can be accurately distributed to the corresponding third serial controller 3420gd3 On the screen on which the illumination information for the control circuit 3420i2 and the illumination information for the third decoration LED control circuit 3420i3 for the game board side VDP control are drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). Installed on VRAM as attached to game board side drawing data It is generated on the game board side incidental information area VRGN1b of the game board side display area VRGN1 to be.

  In addition, the distribution output control unit 3420gc displays the illumination information for the game board side VDP control target fourth decoration LED control circuit 3420i4 to the game board side VDP control target sixth decoration LED control circuit 3420i6 read from the buffer memory 3420gb. Electric decoration information for the game board side VDP control target fourth decoration LED control circuit 3420i4, game board side VDP control target fifth decoration LED so that it can be accurately distributed to the corresponding fourth serial controller 3420gd4 On the screen on which the illumination information for the control circuit 3420i5 and the illumination information for the sixth decoration LED control circuit 3420i6 for the game board side VDP control are drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). Installed on VRAM as attached to game board side drawing data It is generated on the game board side incidental information area VRGN1b of the game board side display area VRGN1 to be.

  In addition, the distribution output control unit 3420gc outputs the electrical decoration information for the game board side VDP control target seventh decoration LED control circuit 3420i7 to the game board side VDP control target ninth decoration LED control circuit 3420i9 read from the buffer memory 3420gb. The electric decoration information for the seventh decoration LED control circuit 3420i7 for the game board side VDP control object, the eighth decoration LED for the game board side VDP control object so that it can be accurately distributed to the corresponding fifth serial controller 3420gd5 On the screen on which the illumination information for the control circuit 3420i8 and the illumination information for the game board side VDP control target ninth decoration LED control circuit 3420i9 are drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). Installed on VRAM as attached to game board side drawing data It is generated on the game board side incidental information area VRGN1b of the game board side display area VRGN1 to be.

  Also, the distribution output control unit 3420gc provides the illumination information for the game board side VDP control target 10th decoration LED control circuit 3420i10 to the game board side VDP control target 12th decoration LED control circuit 3420i12 read from the buffer memory 3420gb. In order to be able to accurately distribute to the corresponding sixth serial controller 3420gd6, the electrical decoration information for the game board side VDP control target 10th decoration LED control circuit 3420i10, the game board side VDP control target 11th decoration LED On the screen on which the illumination information for the control circuit 3420i11 and the illumination information for the 12th decoration LED control circuit 3420i12 for the game board side VDP control are drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). Attached to game board side drawing data It is generated on the game board side incidental information area VRGN1b of the game board side display area VRGN1 provided in the VRAM to.

  In addition, the distribution output control unit 3420gc provides the illumination information for the game board side VDP control target thirteenth decoration LED control circuit 3420i13 to the game board side VDP control target fifteenth decoration LED control circuit 3420i15 read from the buffer memory 3420gb. In order to be able to accurately distribute to the corresponding seventh serial controller 3420gd7, the illumination information for the game board side VDP control target thirteenth decoration LED control circuit 3420i13, the game board side VDP control target fourteenth decoration LED On the screen on which the illumination information for the control circuit 3420i14 and the illumination information for the game board side VDP control target 15th decoration LED control circuit 3420i15 are drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). Attached to game board side drawing data It is generated on the game board side incidental information area VRGN1b of the game board side display area VRGN1 provided in the VRAM to.

  In addition, the distribution output control unit 3420gc displays the illumination information for the game board side VDP control target 16th decoration LED control circuit 3420i16 to the game board side VDP control target 18th decoration LED control circuit 3420i18 read from the buffer memory 3420gb. In order to be able to accurately distribute to the corresponding eighth serial controller 3420gd8, the electrical decoration information for the game board side VDP control target 16th decoration LED control circuit 3420i16, the game board side VDP control target 17th decoration LED On the screen on which the illumination information for the control circuit 3420i17 and the illumination information for the 18th decoration LED control circuit 3420i18 for the game board side VDP control are drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). Attached to game board side drawing data It is generated on the game board side incidental information area VRGN1b of the game board side display area VRGN1 provided in the VRAM to.

  In addition, the distribution output control unit 3420gc displays the illumination information for the game board side VDP control target 19th decoration LED control circuit 3420i19 to the game board side VDP control target 21st decoration LED control circuit 3420i21 read from the buffer memory 3420gb. In order to be able to accurately distribute to the corresponding ninth serial controller 3420gd9, the electrical decoration information for the game board side VDP control target 19th decoration LED control circuit 3420i19, the game board side VDP control target 20th decoration LED On the screen on which the illumination information for the control circuit 3420i20 and the illumination information for the game board side VDP control target 21st decoration LED control circuit 3420i21 are drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). Attached to game board side drawing data It is generated on the game board side incidental information area VRGN1b of the game board side display area VRGN1 provided in the VRAM to.

  In addition, the distribution output control unit 3420gc provides the illumination information for the game board side VDP control target 22nd decoration LED control circuit 3420i22 to the game board side VDP control target 24th decoration LED control circuit 3420i24 read from the buffer memory 3420gb. In order to be able to accurately distribute to the corresponding tenth serial controller 3420gd10, electrical decoration information for the game board side VDP control target 22nd decoration LED control circuit 3420i22, game board side VDP control target 23rd decoration LED On the screen on which the illumination information for the control circuit 3420i23 and the illumination information for the 24th decoration LED control circuit 3420i24 for the game board side VDP control are drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). Attached to game board side drawing data It is generated on the game board side incidental information area VRGN1b of the game board side display area VRGN1 provided in the VRAM as the.

  In addition, the distribution output control unit 3420gc provides the illumination information for the game board side VDP control target 25th decoration LED control circuit 3420i25 to the game board side VDP control target 27th decoration LED control circuit 3420i27 read from the buffer memory 3420gb. In order to be able to accurately distribute to the corresponding 11th serial controller 3420gd11, the lighting information for the game board side VDP control target 25th decoration LED control circuit 3420i25, the game board side VDP control target 26th decoration LED On the screen on which the lighting information for the control circuit 3420i26 and the lighting information for the 27th decoration LED control circuit 3420i27 for the game board side VDP control are drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). Attached to game board side drawing data It is generated on the game board side incidental information area VRGN1b of the game board side display area VRGN1 provided in the VRAM as the.

  In this way, the drawing data output from the channel CH1 of the liquid crystal and sound source built-in VDP 4160a of the sound control unit 4160 in the peripheral control board 4140 is a screen drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). The game board side drawing data is generated in the game board side display area VRGN1 provided on the built-in VRAM as a result of adding light guide plate information and electrical decoration information according to a predetermined game board side generation rule to thereby generate the first The serial controller 3420gd1 outputs light guide plate information as serial data SDAT1 to the first light guide plate control circuit 3420k1, the second light guide plate control circuit 3420k2, and the third light guide plate control circuit 3420k3 based on the clock signal SCLK1. , Second serial controller 3420g 2 outputs light guide plate information as serial data SDAT2 to the fourth light guide plate control circuit 3420k4, the fifth light guide plate control circuit 3420k5, and the sixth light guide plate control circuit 3420k6 based on the clock signal SCLK2. The plurality of LEDs mounted on the LED substrates respectively disposed on the upper side and the lower side of the plurality of light guide plates provided in the game board side effect display unit 1900 are driven. The brightness of the LEDs mounted in a plurality of rows on the LED substrate is adjusted by the control by this driving.

  Further, the third serial controller 3420gd3 to the eleventh serial controller 3420gd11 use the decoration information as serial data SDAT3 to serial data SDAT11, based on the clock signal SCLK3 to clock signal SCLK11, for the first decoration for the game board side VDP control object. LED control circuit 3420i1 to game board side VDP control target 27th decoration LED control circuit 3420i27, by outputting to the decoration board of game board 4, a plurality of control targets directly controlled by the sound source built-in VDP 4160a A plurality of LEDs (decorative LEDs) provided on each of the game board side VDP control target decorative boards are driven. The brightness (gradation) of the decorative LED is adjusted by this drive control.

  The first serial controller 3420gd1 to the eleventh serial controller 3420gd11 select a common mode in which the respective output timings can be set to the same timing, and an individual mode in which the respective output timings can be set at different timings. Can be done. In the case of setting to the common mode in which the output timings of the first serial controller 3420gd1 to the eleventh serial controller 3420gd11 are set to the same timing, the output from the first serial controller 3420gd1 to the eleventh serial controller 3420gd11 is a very short period of time. Even when a large current flows as an inrush current, the current shortage does not occur and no instantaneous power failure occurs. On the other hand, when the individual modes in which the output timings of the first serial controller 3420gd1 to the eleventh serial controller 3420gd11 are set to different timings are controlled by the outputs from the first serial controller 3420gd1 to the eleventh serial controller 3420gd11. When a large current flows as an inrush current to the object in a very short period of time, there is a possibility that an instantaneous power failure may occur due to power shortage.

  In the present embodiment, the individual modes in which the output timings of the first serial controller 3420gd1 to the eleventh serial controller 3420gd11 are different from each other are set. When the game board 4 is attached to a dedicated frame (outer frame 2, main body frame 3, and door frame 5) representing the world view expressed by the production, the game board 4 is provided on the game board 4 or the dedicated frame side. The power supply board 851 of the board unit 800 attached to the main body frame 3 so as to correspond to the power supplied to an electric drive source such as a plurality of LEDs (decorative LEDs) and a motor or solenoid for operating a plurality of movable bodies. Because the power generation circuit is designed, sufficient power is supplied so that no momentary power failure will occur even if the movable body starts operating with the start of lighting of multiple LEDs (decorative LEDs) and an electric drive source such as a motor or solenoid. Has capacity.

  However, a game board mounted on the main body frame 3 of the outer frame 2 already installed in the hall (a game board of another model different from the game board 4 (for example, the world view expressed by the production is different, LED (decorative The number of LEDs), the presence or absence of a movable body operated by an electric drive source such as a motor or a solenoid, and the number thereof may also be exchanged. Therefore, when the game board 4 is simply replaced, a plurality of LEDs ( When the lighting of the decoration LED) starts, or when the movable body starts to operate by an electric drive source such as a motor or a solenoid, there is a possibility that a momentary power failure may occur.

  Therefore, in the present embodiment, control is performed by the outputs from the first serial controller 3420gd1 to the eleventh serial controller 3420gd11 by setting individual modes in which the output timings of the first serial controller 3420gd1 to the eleventh serial controller 3420gd11 are different timings. When a large current flows as an inrush current in a very short period with respect to the object, the power shortage can be prevented due to power shortage, and a power generation circuit that can withstand the inrush current described above is provided as a power supply substrate 851. There is no need to install it. Thereby, the load to the power supply board 851 of the board | substrate unit 800 attached to the main body frame 3 of the outer frame 2 already installed in the hole different from the exclusive frame mentioned above can be suppressed.

  Note that the liquid crystal and sound source built-in VDP 4160a in the peripheral control board 4140 is generated on the built-in VRAM because the frame frequency is set to 30 fps as described above (about every 33.3 ms). Since the drawing data is output from the channels CH1 and CH2, the drawing data output from the channel CH1 of the sound source built-in VDP 4160a is also input to the game board side signal separation control circuit 3420g of the liquid crystal output board 3420 about every 33.3 ms. The Rukoto. Therefore, a screen (effect image) drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e) separated in the first resolution conversion unit 3420gaa of the signal separation unit 3420ga in the game board side signal separation control circuit 3420g. ) Is output to the game board side effect display unit 1900 (liquid crystal panel 5000e) via the game board side liquid crystal drive circuit 3420h about every 33.3 ms, and the game board side signal separation control circuit. The light guide plate information and the illumination information separated in the second resolution conversion unit 3420gab of the signal separation unit 3420ga in 3420g are clocked as serial data SDAT1 to serial data SDAT11 from the first serial controller 3420gd1 to eleventh serial controller 3420gd11. It is possible to realize the synchronization of effects by the plurality of control objects respectively output from the first serial controller 3420gd1 to the eleventh serial controller 3420gd11 by being output every about 33.3 ms based on the numbers SCLK1 to SCLK11. As well as being able to prevent a shift in the progress of the production by the plurality of control objects, a decrease in interest can be suppressed.

[12-2. Various light guide plate control circuit and game board side VDP control object decoration LED control circuit configuration]
Next, the configurations of various light guide plate control circuits and game board side VDP control target decoration LED control circuits will be described. The liquid crystal output board 3420 includes, as various light guide plate control circuits, a first light guide plate control circuit 3420k1 capable of dimming light emitted from the first light guide plate 5000d included in the game board side effect display unit 1900, and a game board. Light emission by the second light guide plate control circuit 3420k2 capable of dimming the light emitted by the second light guide plate 5000f provided in the side effect display unit 1900, and light emission by the third light guide plate 5000g provided in the game board side effect display unit 1900. The third light guide plate control circuit 3420k3 capable of dimming and lighting, and the fourth light guide plate control circuit capable of dimming and emitting light emitted by the fourth light guide plate 5000h included in the game board side effect display unit 1900 3420k4 and the light emitted by the fifth light guide plate 5000i included in the game board side effect display unit 1900 A fifth light guide plate control circuit 3420k5 that can be controlled, and a sixth light guide plate control circuit 3420k6 that is capable of dimming the light emitted by the sixth light guide plate 5000k included in the game board side effect display unit 1900. I have.

  Further, the liquid crystal output board 3420 is a game board side VDP control target decoration LED control circuit 3420i, among the decoration boards of the game board 4, a plurality of game board sides that are controlled by the sound source built-in VDP 4160a directly. Game board side VDP control object capable of dimming light emitted from a plurality of LEDs (decorative LEDs) provided on each of the VDP control object decoration boards First decoration LED control circuit 3420i1 to game board side VDP control object A 27th decorative LED control circuit 3420i27 (a total of 27 circuits) is provided.

  In this embodiment, in the game board side effect display unit 1900, the high-brightness LED 5000d6 and the second light guide plate respectively mounted on the light guide plate upper decorative substrate 5000d1 and the light guide plate lower decorative substrate 5000d2 of the first light guide plate 5000d. The high-brightness LED 5000f6 mounted on the 5000f1 light guide plate upper decorative substrate 5000f2 and the light guide plate lower decorative substrate 5000f2 respectively, and the third light guide plate 5000g mounted on the light guide plate upper decorative substrate 5000d1 and the light guide plate lower decorative substrate 5000d2, respectively. The high-brightness LED 5000g6, the high-brightness LED 5000h6 and the fifth light-guide plate 5000i on the light-guide plate 5000i mounted on the light-guide plate upper-decoration substrate 5000h1 and the light-guide plate-decoration substrate 5000h2, respectively. 5000i1 and light guide plate lower decorative substrate 5000i A plurality of light guide plate LEDs such as a high brightness LED 5000k6 and a high brightness LED 5000k6 mounted on a light guide plate upper decorative substrate 5000k1 and a light guide plate lower decorative substrate 5000k2 of the sixth light guide plate 5000k, respectively. Managed in groups.

  The first light guide plate control circuit 3420k1 can dimm the light emitted by the first light guide plate 5000d, and the second light guide plate control circuit 3420k2 can light the light emitted by the second light guide plate 5000f. LED 5000f6 that can be dimmed and lit by the third light guide plate 5000g by the third light guide plate control circuit 3420k3 is managed as a first group for light guide plates. The fourth light guide plate control circuit 3420k4 can dimm the light emitted by the fourth light guide plate 5000h, and the fifth light guide plate control circuit 3420k5 can light the light emitted by the fifth light guide plate 5000i. The LED 5000i6 that can be dimmed by the sixth light guide plate 5000k by the sixth light guide plate control circuit 3420k6 is managed as a second group for light guide plates.

  Further, in the present embodiment, the game board side decorations are dimmed by the game board side VDP control target first decoration LED control circuit 3420i1 to the game board side VDP control target third decoration LED control circuit 3420i3. It is managed as the first group. In addition, the ones that are dimmed by the fourth decorative LED control circuit 3420i4 to the gaming board side VDP control target to the sixth decorative LED control circuit 3420i6 as the gaming board side VDP control target are the second decorative board side decorations. It is managed. Also, the third decoration LED control circuit 3420i7 to the game board side VDP control object to the dimming and lighting by the game board side VDP control object ninth decoration LED control circuit 3420i9 is the third board for decoration on the game board side. It is managed. In addition, the fourth decoration LED control circuit 3420i10 to the game board side VDP control target 10th decoration LED control circuit 3420i12 that is dimmed and lighted by the game board side VDP control target 12th decoration LED control circuit 3420i12 is a game board side decoration fourth group. It is managed.

  In addition, the fifth board for decoration on the game board side is the one that is dimmed by the 15th decoration LED control circuit 3420i15 for the game board side VDP control object to the 15th decoration LED control circuit 3420i15 for the game board side VDP control object. It is managed. Also, the sixth board LED for the game board side decoration is the one that is dimmed by the 16th decoration LED control circuit 3420i16 for the game board side VDP control object to the 18th decoration LED control circuit 3420i18 for the game board side VDP control object. It is managed. The seventh board for decoration on the game board side is the one that is dimmed by the 19th decoration LED control circuit 3420i19 for the game board side VDP control object to the 21st decoration LED control circuit 3420i21 for the game board side VDP control object. It is managed. In addition, what is dimmed by the game board side VDP control target 22nd decoration LED control circuit 3420i22 to game board side VDP control target 24th decoration LED control circuit 3420i24 is the game board side decoration 8th loop. It is managed. In addition, what is dimmed by the 25th decoration LED control circuit 3420i27 for the game board side VDP control object to 25th decoration LED control circuit 3420i27 for the game board side VDP control object is the 9th group for game board side decoration. It is managed.

  In the liquid crystal output board 3420, the first light guide plate power supply (+ 12V) is dedicated to the first light guide plate power supply circuit 3420e from the first light guide plate power supply circuit 3420e as a power supply for the first light guide plate control circuit 3420k1. As a power source for the second light guide plate control circuit 3420k2, a second light guide plate power source (+ 12V) is supplied exclusively from the second light guide plate power circuit of the game board side various light guide plate power circuit 3420e, As a power source for the third light guide plate control circuit 3420k3, a third light guide plate power source (+ 12V) is supplied exclusively from the third light guide plate power circuit of the game board side various light guide plate power circuit 3420e, As a power source for the light guide plate control circuit 3420k4, the fourth light guide plate power source (+ 12V) is exclusively used from the fourth light guide plate power source circuit of the various light guide plate side power source circuits 3420e. As a power source for the fifth light guide plate control circuit 3420k5, a fifth light guide plate power source (+ 12V) is supplied exclusively from the fifth light guide plate power circuit of the game board side various light guide plate power circuit 3420e. As a power source for the sixth light guide plate control circuit 3420k6, a sixth light guide plate power source (+ 12V) is supplied exclusively from the sixth light guide plate power circuit of the various light guide plate power circuit 3420e.

  Further, in addition to its own control power supply, the liquid crystal output board 3420 serves as a power supply for the game board side VDP control target first decoration LED control circuit 3420i1 to the game board side VDP control target 27th decoration LED control circuit 3420i27. The power for illumination (+ 5V) is supplied from the power supply board 851 through the frame peripheral relay terminal board 868, the peripheral door frame relay terminal board 882, and the peripheral control board 4140.

  The first light guide plate control circuit 3420k1 mainly includes an LED driver IC 4810, a first light guide plate PWM (Pulse Width Modulation) control circuit 4950, peripheral circuits, and the like. The second light guide plate control circuit 3420k2 mainly includes an LED driver IC 4830, a second light guide plate PWM control circuit 4960, peripheral circuits, and the like. The third light guide plate control circuit 3420k3 mainly includes an LED driver IC 4850, a third light guide plate PWM control circuit 4970, peripheral circuits, and the like. The fourth light guide plate control circuit 3420k5 mainly includes an LED driver IC 4815, a fourth light guide plate PWM control circuit 4955, peripheral circuits, and the like. The fifth light guide plate control circuit 3420k5 mainly includes an LED driver IC 4835, a fifth light guide plate PWM control circuit 4965, peripheral circuits, and the like. The sixth light guide plate control circuit 3420k6 mainly includes an LED driver IC 4855, a sixth light guide plate PWM control circuit 4975, peripheral circuits, and the like.

  The LED driver IC 4810 of the first light guide plate control circuit 3420k1 is based on the first light guide plate PWM signal from the first light guide plate PWM control circuit 4950 of the first light guide plate control circuit 3420k1. The light emission at 5000d can be turned off, and the luminance range from low luminance (minimum luminance) to high luminance (maximum luminance) can be adjusted by 1%, and the luminance can be adjusted to one of the luminance ranges. It can be lighted. The first light guide plate PWM signal includes a light guide plate upper decorative substrate 5000d1 provided on the upper end surface of the first light guide plate 5000d, a light guide plate lower decorative substrate 5000d2 provided on the lower end surface of the first light guide plate 5000d, The LED 5000d6 can be instructed to emit light. Thus, since the LED driver IC 4810 can finely adjust the luminance of the LED 5000d6, it can perform fine control such as dimming lighting of the first light guide plate 5000d.

  The LED driver IC 4830 of the second light guide plate control circuit 3420k2 is based on the second light guide plate PWM signal from the second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2. The light emission by 5000f can be turned off, and the luminance range from low luminance (minimum luminance) to high luminance (maximum luminance) can be adjusted by 1%, and adjusted to one luminance in the luminance range. It can be lighted. The second light guide plate PWM signal includes a light guide plate upper decorative substrate 5000f1 provided on the upper end surface of the second light guide plate 5000f, a light guide plate lower decorative substrate 5000f2 provided on the lower end surface of the second light guide plate 5000f, and The LED 5000f6 can be instructed to emit light. Thus, since the LED driver IC 4830 can finely adjust the luminance of the LED 5000f6, it can perform fine control such as dimming lighting of the second light guide plate 5000f.

  The LED driver IC 4850 of the third light guide plate control circuit 3420k3 is based on the third light guide plate PWM signal from the third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3. The light emission at 5000 g is turned off, and the luminance range from low luminance (minimum luminance) to high luminance (maximum luminance) can be adjusted by 1%, and adjusted to one luminance within the luminance range. It can be lighted. The third light guide plate PWM signal includes a light guide plate upper decorative substrate 5000g1 provided on the upper end surface of the third light guide plate 5000g, a light guide plate lower decorative substrate 5000g2 provided on the lower end surface of the third light guide plate 5000g, It is possible to instruct the light emission of a plurality of LEDs 5000g6 mounted on each. Thus, since the LED driver IC 4850 can finely adjust the luminance of the LED 5000g6, it can perform fine control such as dimming lighting of the third light guide plate 5000g.

  The LED driver IC 4815 of the fourth light guide plate control circuit 3420k4 is based on the fourth light guide plate PWM signal from the fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4. The light emission at 5000h is turned off, and the luminance range from low luminance (minimum luminance) to high luminance (maximum luminance) can be adjusted by 1%, and adjusted to one luminance in the luminance range. It can be lighted. The fourth light guide plate PWM signal includes a light guide plate upper decorative substrate 5000h1 provided on the upper end surface of the fourth light guide plate 5000h, a light guide plate lower decorative substrate 5000h2 provided on the lower end surface of the fourth light guide plate 5000h, The LED 5000h6 mounted in plurality can be instructed to emit light. Thus, since the LED driver IC 4815 can finely adjust the luminance of the LED 5000h6, it can perform fine control such as dimming lighting of the fourth light guide plate 5000h.

  The LED driver IC 4835 of the fifth light guide plate control circuit 3420k5 is based on the fifth light guide plate PWM signal from the fifth light guide plate PWM control circuit 4965 of the fifth light guide plate control circuit 3420k5. The light emitted by 5000i can be turned off, and the brightness range from low brightness (minimum brightness) to high brightness (maximum brightness) can be adjusted by 1%, and adjusted to one brightness within the brightness range. It can be lighted. The fifth light guide plate PWM signal includes a light guide plate upper decorative substrate 5000i1 provided on the upper end surface of the fifth light guide plate 5000i, a light guide plate lower decorative substrate 5000i2 provided on the lower end surface of the fifth light guide plate 5000i, The LED 5000i6 mounted in plurality can be instructed to emit light. Thus, since the LED driver IC 4835 can finely adjust the brightness of the LED 5000i6, it can perform fine control such as dimming lighting of the fifth light guide plate 5000i.

  The LED driver IC 4855 of the sixth light guide plate control circuit 3420k6 is based on the sixth light guide plate PWM signal from the sixth light guide plate PWM control circuit 4975 of the sixth light guide plate control circuit 3420k6. Light emission at 5000k can be turned off, and the luminance range from low luminance (minimum luminance) to high luminance (maximum luminance) can be adjusted by 1%, and adjusted to one of the luminance ranges. It can be lighted. The PWM signal for the sixth light guide plate includes a light guide plate upper decorative substrate 5000k1 provided on the upper end surface of the sixth light guide plate 5000k, a light guide plate lower decorative substrate 5000k2 provided on the lower end surface of the sixth light guide plate 5000k, It is possible to instruct the light emission of a plurality of LEDs 5000k6 mounted on each. Thus, since the LED driver IC 4855 can finely adjust the brightness of the LED 5000k6, it can perform fine control such as dimming lighting of the sixth light guide plate 5000k.

  The game board side VDP control target first decoration LED control circuit 3420i1 to the game board side VDP control target 27th decoration LED control circuit 3420i27 are respectively composed of the same decoration LED driver IC. The decoration LED driver IC includes a plurality of LEDs (decoration) provided on each of the plurality of game board side VDP control target decoration boards that are controlled by the built-in sound source VDP 4160a among the decoration boards of the game board 4. LED) can be dimmed individually and can be dimmed in a total of 128 steps from 0 (zero) to 127 (gradient) from off to high luminance (maximum luminance). The brightness is adjusted to the maximum brightness at a gradation of 127. In this way, the game board side VDP control target first decoration LED control circuit 3420i1 to the game board side VDP control target 27th decoration LED control circuit 3420i27 can finely adjust the brightness of the decoration LEDs individually. Therefore, it is possible to perform fine control such as dimming lighting of the decorative LED.

  The peripheral control MPU 4150a of the peripheral control unit 4150 on the peripheral control board 4140 controls the VDP 4160a with built-in sound source of the liquid crystal and sound control unit 4160. The sound source built-in VDP 4160a is a control object that is directly controlled by the sound source built-in VDP 4160a among the screen data that defines the structure of the screen drawn on the game board side effect display unit 1900 (liquid crystal panel 5000e) and the decorative boards of the game board 4. When the light emission data defining the light emission mode of the plurality of LEDs (decorative LEDs) provided on each of the plurality of game board side VDP control target decorative boards is input from the peripheral control MPU 4150a, In accordance with the defined game board side generation rules, based on the input screen data, the game board side character data for drawing in the display area of the game board side effect display unit 1900 is extracted from the liquid crystal and sound control ROM 4160b and sprites are extracted. The game board side display area VRGN1 created on the built-in VRAM by creating data The game board side drawing data is generated in the technique board side drawing data area VRGN1a, and the sound source built-in VDP 4160a is directly connected to the decorative board of the game board 4 from the liquid crystal and sound control ROM 4160b based on the inputted light emission data. The game board side light emission mode setting image data for setting the light emission mode of a plurality of LEDs (decorative LEDs) provided on each of the plurality of game board side VDP control target decorative boards to be controlled is extracted. Then, light guide plate information and electrical decoration information, which will be described later, are generated as drawing data in the game board side accompanying information area VRGN1b of the game board side display area VRGN1 provided on the built-in VRAM. The sound source built-in VDP 4160a outputs the drawing data generated from the channel CH1 to the game board side display area VRGN1 to the liquid crystal output board 3420 by the LVDS method.

  As described above, the drawing data output from the channel CH1 of the sound source built-in VDP 4160a is a parallel signal (that is, the channel CH1 of the sound source built-in VDP 4160a based on the signal transmitted by the LVDS method in the RGB conversion circuit 3420f of the liquid crystal output substrate 3420). 3 video signals of red video signal, green video signal, and blue video signal, and three synchronization signals of horizontal synchronization signal, vertical synchronization signal, and clock signal). Then, the signal is input to the signal separation unit 3420ga in the game board side signal separation control circuit 3420g of the liquid crystal output board 3420. The signal separation unit 3420ga converts the drawing data converted into the parallel signal into the game board side drawing data for the game board side effect display unit 1900 (liquid crystal panel 5000e) in the first resolution conversion unit 3420gaa and the second resolution conversion unit 3420gab. Separated into light guide plate information and electrical information. The first resolution conversion unit 3420gaa draws game board side rendering data for the separated game board side effect display unit 1900 (liquid crystal panel 5000e) via the game board side liquid crystal drive circuit 3420h of the liquid crystal output board 3420. The output to the effect display unit 1900 (liquid crystal panel 5000e), the second resolution conversion unit 3420gab outputs the separated light guide plate information and electrical decoration information to the buffer memory 3420gb in the game board side signal separation control circuit 3420g to perform the writing operation. Do.

  The distribution output control unit 3420gc in the game board side signal separation control circuit 3420g converts the light guide plate information and the electrical decoration information read from the buffer memory 3420gb into the first serial light guide plate information according to the above-described predetermined game board side generation rule. The controller 3420gd1 and the second serial controller 3420gd2 are distributed, and the illumination information is distributed to the third serial controller 3420gd3 to the eleventh serial controller 3420gd11. As described above, the first serial controller 3420gd1 and the second serial controller 3420gd2 use the first light guide plate control circuit 3420k1 to the sixth guide based on the clock signals SCLK1 and SCLK2 with the light guide plate information as serial data SDAT1 and SDAT2. It outputs to the optical plate control circuit 3420k6. As described above, the third serial controller 3420gd3 to the eleventh serial controller 3420gd11 use the illumination information as the serial data SDAT3 to serial data SDAT11, and based on the clock signal SCLK3 to the clock signal SCLK11, To the gaming board side VDP control target first decoration LED control circuit 3420i1 to the gaming board side VDP control target 27th decoration LED control circuit 3420i27.

  As described above, the serial data SDAT1 and the clock signal SCLK1 from the first serial controller 3420gd1 are output from the first light guide plate PWM control circuit 4950 of the first light guide plate control circuit 3420k1 and the second light guide plate control circuit 3420k2. A circuit in which the second light guide plate PWM control circuit 4960 and the third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3 are electrically connected as one serial connection (one serial system). It has a configuration. The serial data SDAT2 and the clock signal SCLK2 from the second serial controller 3420gd2 are, as described above, the fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4, and the fifth light guide plate control circuit. The fifth light guide plate PWM control circuit 4965 of 3420k5 and the sixth light guide plate PWM control circuit 4975 of the sixth light guide plate control circuit 3420k6 are electrically connected as one serial connection (one serial system). Circuit configuration. In addition, the third serial controller 3420gd3 to the eleventh serial controller 3420gd11 are also electrically connected as one serial connection (one serial system) as described above.

  By adopting such a single serial connection method, for example, from the peripheral control board 4140, the first light guide plate PWM signal, the second light guide plate PWM signal, and the third light guide plate PWM signal. The LED driver IC 4810 of the first light guide plate control circuit 3420k1, the LED driver IC 4830 of the second light guide plate control circuit 3420k2, the LED driver IC 4850 of the third light guide plate control circuit 3420k3, and the fourth conductor on the liquid crystal output substrate 3420. The LED driver IC 4815 of the light plate control circuit 3420k4, the LED driver IC 4835 of the fifth light guide plate control circuit 3420k5, and the LED driver IC 4855 of the sixth light guide plate control circuit 3420k6 are connected in parallel, and the above-mentioned decoration Dimming LED individually Compared to the method of parallel connection in which control signals are output individually from the peripheral control board 4140, for example, to the decorative LED individually, the number of wires can be greatly reduced. The degree of freedom can be increased. And in the method of using one serial connection, it is easy to cope with the external noise not entering the wiring by reducing the number of wires. Can be suppressed.

  The first light guide plate PWM control circuit 4950 of the first light guide plate control circuit 3420k1, the second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2, and the third light guide plate control circuit 3420k3. 3 light guide plate PWM control circuit 4970, fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4, fifth light guide plate PWM control circuit 4965 of the fifth light guide plate control circuit 3420k5, The sixth light guide plate PWM control circuit 4975 of the sixth light guide plate control circuit 3420k6 has an ID setting circuit (not shown) such as one of a plurality of ID setting terminals. The ID setting terminal is electrically connected to the control power supply side (DC power supply, + 5V) (or electrically connected by a pull-up resistor) and other ID settings are made. By grounding the child to the ground (GND) side can be set without overlapping the ID.) Is set by the. In addition, in the game board side VDP control target first decoration LED control circuit 3420i1 to the game board side VDP control target 27th decoration LED control circuit 3420i27, an ID that can identify the individual is set as described later. It is set without duplication.

  Accordingly, the first light guide plate PWM control circuit 4950 of the first light guide plate control circuit 3420k1, the second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2, and the third light guide plate control circuit. 3420k3 third light guide plate PWM control circuit 4970, fourth light guide plate control circuit 3420k4 fourth light guide plate PWM control circuit 4955, and fifth light guide plate control circuit 3420k5 fifth light guide plate PWM control circuit. 4965, the sixth light guide plate PWM control circuit 4975 of the sixth light guide plate control circuit 3420k6, the game board side VDP control target first decoration LED control circuit 3420i1 to the game board side VDP control target 27th decoration use The ID can be set in advance for the LED control circuit 3420i27 without overlapping each other.

  The serial data SDAT1 to serial data SDAT11 from the first serial controller 3420gd1 to the eleventh serial controller 3420gd11 in the game board side signal separation control circuit 3420g transmit light guide plate information and electrical decoration information as described above. Here, light guide plate information and electrical decoration information will be described.

  The “light guide plate information” designates a light guide plate that uses one light guide plate as a backlight among the plurality of light guide plates provided in the game board side effect display unit 1900 (in other words, the game board side effect display unit 1900 includes This is information for selecting (switching) one light guide plate among a plurality of light guide plates, and is composed of light guide plate designation information and luminance information. The light guide plate designation information includes the first light guide plate PWM control circuit 4950 of the first light guide plate control circuit 3420k1, the second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2, and the third light guide plate control. Third light guide plate PWM control circuit 4970 of circuit 3420k3, fourth light guide plate PWM control circuit 4955 of fourth light guide plate control circuit 3420k4, and fifth light guide plate PWM control circuit 4965 of fifth light guide plate control circuit 3420k5. And it is the information which shows which PWM control circuit is designated among the 6th light guide plate PWM control circuits 4975 of the 6th light guide plate control circuit 3420k6, and ID mentioned above is set. is there. The luminance information is information indicating which luminance is designated in a luminance range from low luminance (minimum luminance) to high luminance (maximum luminance), and the luminance can be set by 1%. it can.

  “Electric decoration information” is information for designating a light emission mode, and is composed of electrical LED designation information and gradation information. The illumination LED designation information is the game board side VDP control target first decoration LED control circuit 3420i1 to the game board side VDP control target 27th decoration LED control circuit 3420i27, and any game board side VDP control target decoration. This is information indicating whether the LED control circuit is designated, and the above-described ID is set. The gradation information is information indicating which gradation degree is designated from the gradation degree 0 (zero) to the gradation degree 127.

  The liquid crystal output board 3420 includes the luminance of light emitted by the first light guide plate 5000d, the luminance of light emitted by the second light guide plate 5000f, the luminance of light emitted by the third light guide plate 5000g, and the fourth luminance. A luminance overall setting switch 4880 is provided to collectively set the luminance of light emitted by the light guide plate 5000h, the luminance of light emitted by the fifth light guide plate 5000i, and the luminance of light emitted by the sixth light guide plate 5000k. The luminance general setting signal from the luminance general setting switch 4880 is sent to the first light guide plate PWM control circuit 4950 of the first light guide plate control circuit 3420k1 and the second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2. The third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3, the fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4, and the fifth of the fifth light guide plate control circuit 3420k5. The light guide plate PWM control circuit 4965 and the sixth light guide plate PWM control circuit 4975 of the sixth light guide plate control circuit 3420k6.

  Since the liquid crystal output substrate 3420 is arranged on the back side of the game board 4 as described above, a staff member such as a hall clerk closes the main body frame 3 with respect to the outer frame 2 installed in the hall. In this state, the luminance overall setting switch 4880 can be operated.

  When the brightness general setting switch 4880 is operated to the setting A by the turning operation (when 100% is set), the brightness in the serial data SDAT1 from the first serial controller 3420gd1 in the game board side signal separation control circuit 3420g. The luminance set in the information can be set to be used as it is, and this is the fact that the first light guide plate PWM control circuit 4950 and the second light guide plate of the first light guide plate control circuit 3420k1 are used as a luminance overall setting signal. The signals are input to the second light guide plate PWM control circuit 4960 of the control circuit 3420k2 and the third light guide plate PWM control circuit 497 of the third light guide plate control circuit 3420k3, respectively, and in the game board side signal separation control circuit 3420g. 2 Serial data SDAT2 from serial controller 3420gd2 The luminance set in the luminance information can be set to be used as it is, and the fact that this is the case, the fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4, The light is input to the fifth light guide plate PWM control circuit 4965 of the light guide plate control circuit 3420k5 and the sixth light guide plate PWM control circuit 4975 of the sixth light guide plate control circuit 3420k6.

  When the brightness general setting switch 4880 is operated to the setting B by a turning operation (when 85% is set), the brightness in the serial data SDAT1 from the first serial controller 3420gd1 in the game board side signal separation control circuit 3420g. The first light guide plate of the first light guide plate control circuit 3420k1 can be set to be used by forcibly setting the brightness to 85% of the brightness set in the information. While being input to the PWM control circuit 4950, the second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2, and the third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3, respectively. Serial signal from the second serial controller 3420gd2 in the game board side signal separation control circuit 3420g Can be set to be used by forcibly setting 85% of the brightness set in the brightness information in the data SDAT2, and this fact is used as the brightness control setting signal of the fourth light guide plate control circuit 3420k4. 4 light guide plate PWM control circuit 4955, fifth light guide plate PWM control circuit 4965 of fifth light guide plate control circuit 3420k5, and sixth light guide plate PWM control circuit 4975 of sixth light guide plate control circuit 3420k6. Is done.

  When the brightness general setting switch 4880 is operated to the setting C by the turning operation (70% setting), the brightness in the serial data SDAT1 from the first serial controller 3420gd1 in the game board side signal separation control circuit 3420g. The first light guide plate of the first light guide plate control circuit 3420k1 can be set to be used by forcibly setting the brightness set to 70% of the brightness set in the information. While being input to the PWM control circuit 4950, the second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2, and the third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3, respectively. Serial signal from the second serial controller 3420gd2 in the game board side signal separation control circuit 3420g Can be set to be used by forcibly setting 70% of the brightness set in the brightness information in the data SDAT2, and this fact is used as a signal for overall brightness setting in the fourth light guide plate control circuit 3420k4. 4 light guide plate PWM control circuit 4955, fifth light guide plate PWM control circuit 4965 of fifth light guide plate control circuit 3420k5, and sixth light guide plate PWM control circuit 4975 of sixth light guide plate control circuit 3420k6. Is done.

  When the first light guide plate PWM control circuit 4950 of the first light guide plate control circuit 3420k1 receives the serial data SDAT1 from the first serial controller 3420gd1 in the game board side signal separation control circuit 3420g based on the clock signal SCLK1, When the ID is included in the light guide plate designation information in the data SDAT1, the luminance information in the serial data SDAT1 is captured, and based on the luminance information from the luminance general setting switch 4880, the luminance information is The light emitted from the first light guide plate 5000d included in the game board side effect display unit 1900 is turned off, or adjusted to one luminance in a luminance range from low luminance (minimum luminance) to high luminance (maximum luminance). P for first light guide plate that can be lighted And outputs to the LED driver IC4810 of the first light guide plate control circuit 3420k1 create a M signal. In this embodiment, when the first light guide plate PWM control circuit 4950 receives the serial data SDAT1 from the first serial controller 3420gd1 in the game board side signal separation control circuit 3420g based on the clock signal SCLK1, the serial data SDAT1. When the own light ID is not included in the light guide plate designation information in, the luminance information in the serial data SDAT1 is not taken in, and the output of the first light guide plate PWM signal created based on the luminance information taken in last time is maintained.

  When the second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2 receives the serial data SDAT1 from the first serial controller 3420gd1 in the game board side signal separation control circuit 3420g based on the clock signal SCLK1, When the ID is included in the light guide plate designation information in the data SDAT1, the luminance information in the serial data SDAT1 is captured, and based on the luminance information from the luminance general setting switch 4880, the luminance information is The light emitted from the second light guide plate 5000f included in the game board side effect display unit 1900 is turned off, or adjusted to one luminance in a luminance range from low luminance (minimum luminance) to high luminance (maximum luminance). P for second light guide plate that can be lighted Create a M signal output to the LED driver IC4830 of the second light guide plate control circuit 3420K2. In this embodiment, when the second light guide plate PWM control circuit 4960 receives the serial data SDAT1 from the first serial controller 3420gd1 in the game board side signal separation control circuit 3420g based on the clock signal SCLK1, the serial data SDAT1. When the ID of the light guide plate does not include its own ID, the luminance information in the serial data SDAT1 is not captured, and the output of the second light guide plate PWM signal created based on the previously captured luminance information is maintained.

  When the third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3 receives the serial data SDAT1 from the first serial controller 3420gd1 in the game board side signal separation control circuit 3420g based on the clock signal SCLK1, the third light guide plate PWM control circuit 4970 When the ID is included in the light guide plate designation information in the data SDAT1, the luminance information in the serial data SDAT1 is captured, and based on the luminance information from the luminance general setting switch 4880, the luminance information is The light emitted from the third light guide plate 5000g provided in the game board side effect display unit 1900 is turned off, or adjusted to one luminance in a luminance range from low luminance (minimum luminance) to high luminance (maximum luminance). P for third light guide plate that can be lighted Create a M signal output to the LED driver IC4850 of the third light guide plate control circuit 3420K3. In this embodiment, when the third light guide plate PWM control circuit 4970 receives the serial data SDAT1 from the first serial controller 3420gd1 in the game board side signal separation control circuit 3420g based on the clock signal SCLK1, the serial data SDAT1. When the own light ID is not included in the light guide plate designation information at, the luminance information in the serial data SDAT1 is not taken in, and the output of the third light guide plate PWM signal created based on the luminance information taken in last time is maintained.

  When the fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4 receives the serial data SDAT2 from the second serial controller 3420gd2 in the game board side signal separation control circuit 3420g based on the clock signal SCLK2, When the ID is included in the light guide plate designation information in the data SDAT2, the luminance information in the serial data SDAT2 is captured, and based on the integrated luminance signal from the luminance overall setting switch 4880, from the acquired luminance information, The light emitted from the fourth light guide plate 5000h provided in the game board side effect display unit 1900 is turned off, or adjusted to one luminance in a luminance range from low luminance (minimum luminance) to high luminance (maximum luminance). P for fourth light guide plate that can be lighted Create a M signal output to the LED driver IC4815 fourth light guide plate control circuit 3420K4. In this embodiment, when the fourth light guide plate PWM control circuit 4955 receives the serial data SDAT2 from the second serial controller 3420gd2 in the game board side signal separation control circuit 3420g based on the clock signal SCLK2, the serial data SDAT2 When the light guide plate designating information does not include its own ID, the luminance information in the serial data SDAT2 is not captured, and the output of the fourth light guide plate PWM signal created based on the previously captured luminance information is maintained.

  When the fifth light guide plate PWM control circuit 4965 of the fifth light guide plate control circuit 3420k5 receives the serial data SDAT2 from the second serial controller 3420gd2 in the game board side signal separation control circuit 3420g based on the clock signal SCLK2, the fifth light guide plate PWM control circuit 4965 When the ID is included in the light guide plate designation information in the data SDAT2, the luminance information in the serial data SDAT2 is captured, and based on the integrated luminance signal from the luminance overall setting switch 4880, from the acquired luminance information, The light emitted from the fifth light guide plate 5000i provided in the game board side effect display unit 1900 is turned off, or adjusted to one luminance in a luminance range from low luminance (minimum luminance) to high luminance (maximum luminance). P for fifth light guide plate that can be lighted Create a M signal output to the LED driver IC4835 of the fifth light guide plate control circuit 3420K5. In the present embodiment, the fifth light guide plate PWM control circuit 4965 receives the serial data SDAT2 from the second serial controller 3420gd2 in the game board side signal separation control circuit 3420g based on the clock signal SCLK2, and the serial data SDAT2 When the light guide plate designating information does not include its own ID, the luminance information in the serial data SDAT2 is not captured, and the output of the fifth light guide plate PWM signal created based on the previously captured luminance information is maintained.

  When the sixth light guide plate PWM control circuit 4975 of the sixth light guide plate control circuit 3420k6 receives the serial data SDAT2 from the second serial controller 3420gd2 in the game board side signal separation control circuit 3420g based on the clock signal SCLK2, When the ID is included in the light guide plate designation information in the data SDAT2, the luminance information in the serial data SDAT2 is captured, and based on the integrated luminance signal from the luminance overall setting switch 4880, from the acquired luminance information, The light emitted from the sixth light guide plate 5000k provided in the game board side effect display unit 1900 is turned off, or adjusted to one luminance in a luminance range from low luminance (minimum luminance) to high luminance (maximum luminance). P for sixth light guide plate that can be lighted Create a M signal output to the LED driver IC4855 sixth light guide plate control circuit 3420K6. In the present embodiment, when the sixth light guide plate PWM control circuit 4975 receives the serial data SDAT2 from the second serial controller 3420gd2 in the game board side signal separation control circuit 3420g based on the clock signal SCLK2, the serial data SDAT2 When the own light ID is not included in the light guide plate designation information at, the luminance information in the serial data SDAT2 is not taken in, and the output of the sixth light guide plate PWM signal created based on the luminance information taken in last time is maintained.

  The game board side VDP control target first decoration LED control circuit 3420i1 to the game board side VDP control target 27th decoration LED control circuit 3420i27 are the third serial controllers 3420gd3 to 11th in the game board side signal separation control circuit 3420g. When serial data SDAT3 to serial data SDAT11 from serial controller 3420gd11 are received based on clock signal SCLK3 to clock signal SCLK11, respectively, when their own ID is included in the illumination LED designation information in serial data SDAT3 to serial data SDAT11 Then, the gradation information in the serial data SDAT3 to the serial data SDAT11 is fetched, and each of the decorative LEDs is connected to the corresponding decoration LED so that the gradation level is the fetched gradation information. To control the dimming lighting Te. In the present embodiment, the game board side VDP control target first decoration LED control circuit 3420i1 to the game board side VDP control target 27th decoration LED control circuit 3420i27 are the same as those in the game board side signal separation control circuit 3420g. When serial data SDAT3 to serial data SDAT11 from 3 serial controller 3420gd3 to 11th serial controller 3420gd11 are received based on clock signal SCLK3 to clock signal SCLK11, their IDs are included in the LED specification information in serial data SDAT3 to serial data SDAT11. Is not included, the gradation information in the serial data SDAT3 to the serial data SDAT11 is not captured, and the corresponding gradation LED is used for the corresponding decoration LED. To maintain a gradient that.

  As described above, the LED driver IC 4810 of the first light guide plate control circuit 3420k1 is based on the first light guide plate PWM signal from the first light guide plate PWM control circuit 4950 of the first light guide plate control circuit 3420k1. The light emitted from the first light guide plate 5000d is turned off, and the luminance range from low luminance (minimum luminance) to high luminance (maximum luminance) can be adjusted by 1%, and one luminance in the luminance range can be adjusted. It is possible to adjust the lighting to light. Specifically, the LED driver IC 4810 includes a light guide plate upper decorative substrate 5000d1 provided on the upper end surface of the first light guide plate 5000d, a light guide plate lower decorative substrate 5000d2 provided on the lower end surface of the first light guide plate 5000d, The brightness can be adjusted by varying the current flowing through the LEDs 5000d6 mounted in a plurality.

  As described above, the LED driver IC 4830 of the second light guide plate control circuit 3420k2 is based on the second light guide plate PWM signal from the second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2. The light emitted from the second light guide plate 5000f is turned off, and the luminance range from low luminance (minimum luminance) to high luminance (maximum luminance) can be adjusted by 1%, and one luminance in the luminance range can be adjusted. It is possible to adjust the lighting to light. Specifically, the LED driver IC 4830 includes a light guide plate upper decorative substrate 5000f1 provided on the upper end surface of the second light guide plate 5000f, a light guide plate lower decorative substrate 5000f2 provided on the lower end surface of the second light guide plate 5000f, The brightness can be adjusted by varying the current flowing through the LEDs 5000f6 mounted in a plurality of each.

  As described above, the LED driver IC 4850 of the third light guide plate control circuit 3420k3 is based on the third light guide plate PWM signal from the third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3. The light emitted from the third light guide plate 5000g is turned off, and the luminance range from low luminance (minimum luminance) to high luminance (maximum luminance) can be adjusted by 1%, and one luminance in the luminance range can be adjusted. It is possible to adjust the lighting to light. Specifically, the LED driver IC 4850 includes a light guide plate upper decorative substrate 5000g1 provided on the upper end surface of the third light guide plate 5000g, a light guide plate lower decorative substrate 5000g2 provided on the lower end surface of the third light guide plate 5000g, The brightness can be adjusted by varying the current flowing through the LED 5000g6 mounted in a plurality of each.

  As described above, the LED driver IC 4815 of the fourth light guide plate control circuit 3420k4 is based on the fourth light guide plate PWM signal from the fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4. The light emitted by the fourth light guide plate 5000h is turned off, and the luminance range from low luminance (minimum luminance) to high luminance (maximum luminance) can be adjusted by 1%, and one luminance in the luminance range can be adjusted. It is possible to adjust the lighting to light. Specifically, the LED driver IC 4815 includes a light guide plate upper decorative substrate 5000h1 provided on the upper end surface of the fourth light guide plate 5000h, a light guide plate lower decorative substrate 5000h2 provided on the lower end surface of the fourth light guide plate 5000h, The brightness can be adjusted by varying the current flowing through the LEDs 5000h6 mounted in a plurality.

  As described above, the LED driver IC 4835 of the fifth light guide plate control circuit 3420k5 is based on the fifth light guide plate PWM signal from the fifth light guide plate PWM control circuit 4965 of the fifth light guide plate control circuit 3420k5. The light emitted from the fifth light guide plate 5000i is turned off, and the luminance range from low luminance (minimum luminance) to high luminance (maximum luminance) can be adjusted by 1%, and one luminance in the luminance range can be adjusted. It is possible to adjust the lighting to light. Specifically, the LED driver IC 4835 includes a light guide plate upper decorative substrate 5000i1 provided on the upper end surface of the fifth light guide plate 5000i, a light guide plate lower decorative substrate 5000i2 provided on the lower end surface of the fifth light guide plate 5000i, The brightness can be adjusted by varying the current flowing through the LEDs 5000i6 mounted in a plurality of each.

  As described above, the LED driver IC 4855 of the sixth light guide plate control circuit 3420k6 is based on the sixth light guide plate PWM signal from the sixth light guide plate PWM control circuit 4975 of the sixth light guide plate control circuit 3420k6. The light emitted from the sixth light guide plate 5000k is turned off, and the luminance range from low luminance (minimum luminance) to high luminance (maximum luminance) can be adjusted by 1%, and one luminance in the luminance range can be adjusted. It is possible to adjust the lighting to light. Specifically, the LED driver IC 4855 includes a light guide plate upper decorative substrate 5000k1 provided on the upper end surface of the sixth light guide plate 5000k, a light guide plate lower decorative substrate 5000k2 provided on the lower end surface of the sixth light guide plate 5000k, The brightness can be adjusted by varying the current flowing through the LEDs 5000k6 mounted in a plurality.

  In the first light guide plate 5000d, the decorative substrate 5000d1 on the light guide plate has three LED rows in which six LEDs 5000d6 are electrically connected in series, and a total of 18 LEDs 5000d6 are mounted in one row, The light guide plate lower decorative board 5000d2 has three LED rows in which six LEDs 5000d6 are electrically connected in series, and a total of 18 LEDs 5000d6 are mounted in one row. That is, in the first light guide plate 5000d, 18 LEDs 5000d6 are mounted in a row on the upper end surface of the first light guide plate 5000d, and 18 LEDs 5000d6 are arranged in a row on the lower end surface of the first light guide plate 5000d. By being mounted, the light emitting region 500d4 is configured to be able to emit light by a total of 36 LEDs 5000d6.

  In the second light guide plate 5000f, the decorative board 5000f1 on the light guide plate has three LED rows in which six LEDs 5000f6 are electrically connected in series, and a total of 18 LEDs 5000f6 are mounted in one row. The light guide plate lower decorative substrate 5000f2 has three LED rows in which six LEDs 5000f6 are electrically connected in series, and a total of 18 LEDs 5000f6 are mounted in a row. That is, in the second light guide plate 5000f, 18 LEDs 5000f6 are mounted in a row on the upper end surface of the second light guide plate 5000f, and 18 LEDs 5000f6 are arranged in a row on the lower end surface of the second light guide plate 5000f. By being mounted, the light emitting region 5000f4 is configured to be able to emit light by a total of 36 LEDs 5000f6.

  In the third light guide plate 5000g, the decorative board 5000g1 on the light guide plate has three LED rows in which six LEDs 5000g6 are electrically connected in series, and a total of 18 LEDs 5000g6 are mounted in one row, The light guide plate lower decorative board 5000g2 has three LED rows in which six LEDs 5000g6 are electrically connected in series, and a total of 18 LEDs 5000g6 are mounted in a row. That is, in the third light guide plate 5000g, 18 LEDs 5000g6 are mounted in a row on the upper end surface of the third light guide plate 5000g, and 18 LEDs 5000g6 are arranged in a row on the lower end surface of the third light guide plate 5000g. By being mounted, the light emitting region 5000g4 is configured to be capable of surface emitting by a total of 36 LEDs 5000g6.

  In the fourth light guide plate 5000h, the decorative board 5000h1 on the light guide plate has three LED rows in which six LEDs 5000h6 are electrically connected in series, and a total of 18 LEDs 5000h6 are mounted in one row. The light guide plate lower decorative board 5000h2 has three LED rows in which six LEDs 5000h6 are electrically connected in series, and a total of 18 LEDs 5000h6 are mounted in a row. That is, in the fourth light guide plate 5000h, 18 LEDs 5000h6 are mounted in a row on the upper end surface of the fourth light guide plate 5000h, and 18 LEDs 5000h6 are arranged in a row on the lower end surface of the fourth light guide plate 5000h. By being mounted, the light emitting region 500h4 is configured to be able to emit light by a total of 36 LEDs 5000h6.

  In the fifth light guide plate 5000i, the decorative board 5000i1 on the light guide plate has three LED rows in which six LEDs 5000i6 are electrically connected in series, and a total of 18 LEDs 5000i6 are mounted in one row, The light guide plate lower decorative board 5000i2 has three LED rows in which six LEDs 5000i6 are electrically connected in series, and a total of 18 LEDs 5000i6 are mounted in a row. That is, in the fifth light guide plate 5000i, 18 LEDs 5000i6 are mounted in a row on the upper end surface of the fifth light guide plate 5000i, and 18 LEDs 5000i6 are arranged in a row on the lower end surface of the fifth light guide plate 5000i. By being mounted, the light emitting area 5000i4 can be surface-emitted by the 36 LEDs 5000i6 as a whole.

  In the sixth light guide plate 5000k, the decorative board 5000k1 on the light guide plate has three LED rows in which six LEDs 5000k6 are electrically connected in series, and a total of 18 LEDs 5000k6 are mounted in one row, The light guide plate lower decorative substrate 5000k2 has three LED rows in which six LEDs 5000k6 are electrically connected in series, and a total of 18 LEDs 5000k6 are mounted in a row. That is, in the sixth light guide plate 5000k, 18 LEDs 5000k6 are mounted in a row on the upper end surface of the sixth light guide plate 5000k, and 18 LEDs 5000k6 are arranged in a row on the lower end surface of the sixth light guide plate 5000k. By being mounted, the light emitting region 5000k4 can be surface-emitted by 36 LEDs 5000k6 as a whole.

  LED driver IC 4810 of the first light guide plate control circuit 3420k1, LED driver IC 4830 of the second light guide plate control circuit 3420k2, LED driver IC 4850 of the third light guide plate control circuit 3420k3, LED driver of the fourth light guide plate control circuit 3420k4 The IC 4815, the LED driver IC 4835 of the fifth light guide plate control circuit 3420k5, and the LED driver IC 4855 of the sixth light guide plate control circuit 3420k6 electrically connect up to 12 LEDs (white LEDs) to one LED row. Can be connected in series and can drive LEDs of six LED rows (72 LEDs (= 12 LEDs × 6 LED rows)).

  The LED driver IC 4810 of the first light guide plate control circuit 3420k1, the LED driver IC 4830 of the second light guide plate control circuit 3420k2, the LED driver IC 4850 of the third light guide plate control circuit 3420k3, and the fourth light guide plate control circuit 3420k4. The LED driver IC 4815, the LED driver IC 4835 of the fifth light guide plate control circuit 3420k5, and the LED driver IC 4855 of the sixth light guide plate control circuit 3420k6 are PWM type DC / DC converters capable of boosting to a predetermined upper limit voltage. And a current driver unit capable of flowing a constant current up to a predetermined upper limit current, for each first light guide plate that is input to a POWCTL terminal that is a power control terminal described later PWM signal, second Based on the PWM signal for the light guide plate, the PWM signal for the third light guide plate, the PWM signal for the fourth light guide plate, the fifth light guide plate PWM signal, and the sixth light guide plate PWM signal, the brightness of the LED is increased. It can be done with precision.

  As described above, in this embodiment, the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 includes the LED driver IC 4810 of the first light guide plate control circuit 3420k1 capable of dimming and lighting the first light guide plate 5000d. Rather than directly outputting the first PWM signal for the light guide plate, the first light guide plate PWM control circuit 4950 of the first light guide plate control circuit 3420k1, which is a separate circuit from the peripheral control MPU 4150a, is first connected to the LED driver IC 4810. By directly outputting the PWM signal for the light guide plate, the fine control processing of dimming and lighting the first light guide plate 5000d is separated from the control by the peripheral control MPU 4150a and left to the first light guide plate control circuit 3420k1. The control method is adopted. In the present embodiment, the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 includes the second LED driver IC 4830 of the second light guide plate control circuit 3420k2 that can dimm the second light guide plate 5000f. The second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2, which is a circuit different from the peripheral control MPU 4150a, is not directly output to the LED driver IC 4830. By directly outputting the PWM signal for the optical plate, the control that requires a fine processing load such as dimming lighting of the second light guide plate 5000f is separated from the control by the peripheral control MPU 4150a and is left to the second light guide plate control circuit 3420k2. The method was adopted. Further, in the present embodiment, the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 has a third LED driver IC 4850 of the third light guide plate control circuit 3420k3 that can dimm the third light guide plate 5000g. The third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3, which is a circuit different from the peripheral control MPU 4150a, is not directly output to the LED driver IC 4850. By directly outputting the PWM signal for the optical plate, the control that is delicate and processing load such as dimming lighting of the third light guide plate 5000g is separated from the control by the peripheral control MPU 4150a and left to the third light guide plate control circuit 3420k3. The method was adopted.

  In the present embodiment, the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 includes the fourth LED driver IC 4815 of the fourth light guide plate control circuit 3420k4 that can dimm the fourth light guide plate 5000h. The fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4, which is a circuit different from the peripheral control MPU 4150a, is not directly output to the LED driver IC 4815. By directly outputting the PWM signal for the light plate, the control of fine and processing load such as dimming lighting of the fourth light guide plate 5000h is separated from the control by the peripheral control MPU 4150a and left to the fourth light guide plate control circuit 3420k4. The method was adopted. In the present embodiment, the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 includes the fifth LED driver IC 4835 of the fifth light guide plate control circuit 3420k5 that can dimm the fifth light guide plate 5000i. The fifth light guide plate PWM control circuit 4965 of the fifth light guide plate control circuit 3420k5, which is a circuit different from the peripheral control MPU 4150a, is not directly output to the LED driver IC 4835. By directly outputting the PWM signal for the light plate, the control that requires a fine processing load such as dimming lighting of the fifth light guide plate 5000i is separated from the control by the peripheral control MPU 4150a and is left to the fifth light guide plate control circuit 3420k5. The method was adopted. In the present embodiment, the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 includes the sixth LED driver IC 4855 of the sixth light guide plate control circuit 3420k6 capable of dimming and lighting the sixth light guide plate 5000k. The sixth light guide plate PWM control circuit 4975 of the sixth light guide plate control circuit 3420k6 which is a circuit different from the peripheral control MPU 4150a is not directly output to the LED driver IC 4855. By directly outputting the PWM signal for the optical plate, the control that requires a fine processing load such as dimming lighting of the sixth light guide plate 5000k is separated from the control by the peripheral control MPU 4150a and is left to the sixth light guide plate control circuit 3420k6. The method was adopted.

  As described above, the light guide plate information and the electrical decoration information are stored in each of the plurality of game board side VDP control target decoration boards that are controlled by the sound source built-in VDP 4160a among the decoration boards of the game board 4. A plurality of game board side light emission mode setting image data for setting the light emission mode of the plurality of LEDs (decorative LEDs) provided are stored in advance in the liquid crystal and sound control ROM 4160b. Then, the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 performs the first light guide plate control, which is a fine and processing-intensive control such as dimming lighting of a plurality of light guide plates provided in the game board side effect display unit 1900. The circuit 3420k1, the second light guide plate control circuit 3420k2, the third light guide plate control circuit 3420k3, the fourth light guide plate control circuit 3420k4, the fifth light guide plate control circuit 3420k5, and the sixth light guide plate control circuit 3420k6, respectively. Therefore, it is possible to reduce the processing load of light emission control such as dimming lighting for the peripheral control MPU 4150a. Thereby, dimming lighting of the first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000g, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k, Even if the variation of the effect by the image (screen) of the liquid crystal panel 5000e provided in the game board side effect display unit 1900 is increased, the processing load of the light emission control such as dimming lighting is not increased for the peripheral control MPU 4150a. , There are no restrictions on the variation of the production. In other words, in the present embodiment, the variation of the production can be increased while reducing the processing load of the light emission control for the peripheral control MPU 4150a, so that the player's interest in the production can be made difficult to fade. . Therefore, it can contribute to suppressing a decrease in interest.

  In the present embodiment, as described above, the first light guide plate PWM control circuit 4950 of the first light guide plate control circuit 3420k1, the second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2, The third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3, the fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4, and the fifth of the fifth light guide plate control circuit 3420k5. The light guide plate PWM control circuit 4965 and the sixth light guide plate PWM control circuit 4975 of the sixth light guide plate control circuit 3420k6 are supplied from the first serial controller 3420gd1 and the second serial controller 3420gd2 in the game board side signal separation control circuit 3420g. Serial data SDAT1 and serial data SDAT2 are converted to clock signal SCLK1, When received based on the lock signal SCLK2, when the light guide plate designation information in the serial data SDAT1 and the serial data SDAT2 does not include its own ID, the luminance information in the serial data SDAT1 and the serial data SDAT2 is not taken in, and the corresponding first LED driver IC 4810 of the first light guide plate control circuit 3420k1, LED driver IC 4830 of the second light guide plate control circuit 3420k2, LED driver IC 4850 of the third light guide plate control circuit 3420k3, LED driver IC 4815 of the fourth light guide plate control circuit 3420k4 The LED driver IC 4835 of the fifth light guide plate control circuit 3420k5 and the LED driver IC 4855 of the sixth light guide plate control circuit 3420k6 are based on the previously acquired luminance information. It is configured to maintain the output of the first light guide plate for the PWM signal to the sixth light guide plate for the PWM signal of a form. In the present embodiment, as described above, since the frame frequency is set to 30 fps (approximately every 33.3 ms), drawing data is output to the liquid crystal output board 3420 from the channel CH1 of the sound source built-in VDP 4160a. Yes.

  Accordingly, the first light guide plate PWM control circuit 4950, the second light guide plate PWM control circuit 4960, the third light guide plate PWM control circuit 4970, the fourth light guide plate PWM control circuit 4955, and the fifth light guide plate PWM control. Since the circuit 4965 and the sixth light guide plate PWM control circuit 4975 can repeatedly update the luminance information about every 33.3 ms, it is temporarily output from the channel CH1 of the sound source built-in VDP 4160a. Even if the luminance information in the drawing data is captured this time as if it has been changed to something different from the normal content for some electrical reason, the opportunity to acquire the normal content can be obtained next time, that is, after about 33.3 ms. In the extremely short period of about 33.3 ms, the first LED driver IC 4810 Light emission mode of the optical plate 5000d, light emission mode of the second light guide plate 5000f by the LED driver IC 4830, light emission mode of the third light guide plate 5000g by the LED driver IC 4850, light emission mode of the fourth light guide plate 5000h by the LED driver IC 4815, LED driver Even if the light emission mode of the fifth light guide plate 5000i by the IC 4835 and the light emission mode of the sixth light guide plate 5000k by the LED driver IC 4855 change from the normal light emission mode to the unintended light emission mode, the player is not aware of the change. It is possible to correct to a normal light emission mode (that is, a normal light emission mode).

[12-2-1. LED driver ICs for various light guide plate control circuits]
In the present embodiment, the first light guide plate control circuit 3420k1, the second light guide plate control circuit 3420k2, the third light guide plate control circuit 3420k3, the fourth light guide plate control circuit 3420k4, the fifth light guide plate control circuit 3420k5, And the 6th light-guide plate control circuit 3420k6 was employ | adopted as the same circuit structure. Here, the first light guide plate control circuit 3420k1 will be described in detail below, and the second light guide plate control circuit 3420k2, the third light guide plate control circuit 3420k3, the fourth light guide plate control circuit 3420k4, and the fifth guide. Detailed description of the optical plate control circuit 3420k5 and the sixth light guide plate control circuit 3420k6 will be omitted.

  As shown in FIG. 36, the first light guide plate control circuit 3424k1 mainly includes an LED driver IC 4810. The LED driver IC 4810 includes a regulator unit 4810a, an error amplifier unit 4810b, a PWM comparator unit 4810c, a current detection unit 4810d, an oscillation unit (OSC) 4810e, a control unit 4810f, an SR flip-flop unit 4810g, an output buffer unit 4810h, and a current driver unit 4810i. The input buffer unit 4810k is mainly configured as a circuit.

  The PWM DC / DC converter unit capable of boosting the LED driver IC 4810 to the predetermined upper limit voltage described above includes an error amplifier unit 4810b, a PWM comparator unit 4810c, a current detection unit 4810d, an oscillation unit (OSC) 4810e, and a control. Unit 4810f, SR flip-flop unit 4810g, and output buffer unit 4810h, and the current driver unit capable of flowing a constant current up to the above-described predetermined upper limit current in the LED driver IC 4810 is a current driver unit. This is a circuit composed of 4810i.

  The regulator unit 4810a is supplied with power through the Vin terminal which is a power source terminal, and is connected to the POWCTL terminal which is a power control terminal and the first light guide plate PWM control circuit 4950 through the input buffer unit 4810k. 1 light guide plate PWM signal is input. Based on the first light guide plate PWM signal, the regulator unit 4810a can create or stop (stop) the internal power supply Vreg to be supplied to various circuit units in the LED driver IC 4810. It is configured.

  The error amplifier unit 4810b includes first to sixth inverting input terminals, which are six inverting input terminals (denoted as “−” in the figure), and one non-inverting input terminal (in the figure, “ +) ”). As described above, the decorative board 5000d1 on the light guide plate included in the game board side effect display unit 1900 has three LED rows in which six LEDs 5000d6 are electrically connected in series, and a total of 18 LEDs 5000d6 are arranged in one row. As described above, the decorative board under the light guide plate 5000d2 has three LED rows in which six LEDs 5000d6 are electrically connected in series, and a total of 18 LEDs 5000d6 are mounted in one row. Yes.

  In the present embodiment, among the three LED rows of the decorative board 5000d1 on the light guide plate, the cathode terminal of the last LED 5000d6 of the first LED row (that is, the sixth LED 5000d6) is the first via the LED1 terminal. And the cathode terminal of the last LED 5000d6 (that is, the sixth LED 5000d6) of the second LED row among the three LED rows of the decorative board 5000d1 on the light guide plate. It is electrically connected to the second non-inverting input terminal via the LED2 terminal, and among the three LED rows of the decorative board 5000d1 on the light guide plate, the last LED 5000d6 (that is, the sixth LED row) of the third LED row The cathode terminal of the LED 5000d6) is electrically connected to the third non-inverting input terminal via the LED3 terminal. That is, the voltage applied to the cathode terminal of the LED 5000d6 in the final stage of each LED row is applied to the LED terminals 1 to 3.

  In the present embodiment, the cathode terminal of the last LED 5000d6 (that is, the sixth LED 5000d6) of the first LED row out of the three LED rows of the light guide plate lower decorative board 5000d2 is connected via the LED4 terminal. 4, and the cathode terminal of the last LED 5000d6 (that is, the sixth LED 5000d6) of the second LED row among the three LED rows of the light guide plate lower decorative board 5000d2. Are electrically connected to the fifth non-inverting input terminal via the LED5 terminal, and among the three LED rows of the light guide plate lower decorative board 5000d2, the last LED 5000d6 (that is, six LEDs) of the third LED row is provided. The cathode terminal of the LED 5000d6) is electrically connected to the sixth non-inverting input terminal via the LED6 terminal. That is, the voltage applied to the cathode terminal of the LED 5000d6 in the final stage of each LED row is applied to the LED terminals 4 to 6.

  On the other hand, a reference voltage Vref created from the internal power supply Vreg is applied to the non-inverting input terminal.

  The error amplifier unit 4810b compares and compares the lowest voltage among the voltages applied to the first inverting input terminal to the sixth inverting input terminal with the reference voltage Vref applied to the non-inverting input terminal. The result is output to the PWM comparator unit 4810c as the error voltage Ver. The error amplifier section 4810b includes a voltage applied to the anode terminal of the first LED 5000d6 (that is, the first LED 5000d6) of the first LED row among the three LED rows of the light guide plate decoration board 5000d1, the light guide plate Of the three LED rows of the upper decorative substrate 5000d1, the voltage applied to the anode terminal of the first LED 5000d6 (that is, the first LED 5000d6) of the second LED row, the three rows of the light guide plate upper decorative substrate 5000d1 Among the LED strings, the voltage applied to the anode terminal of the first LED 5000d6 (that is, the first LED 5000d6) of the third LED string, the first LED among the three LED strings of the light guide plate lower decorative board 5000d2 Applied to the anode terminal of the first LED 5000d6 (that is, the first LED 5000d6) of the LED row Voltage, voltage applied to the anode terminal of the first LED 5000d6 (that is, the first LED 5000d6) of the second LED row out of the three LED rows of the light guide plate lower decoration board 5000d2, and the light guide plate lower decoration Of the three LED rows on the substrate 5000d2, the voltage applied to the anode terminal of the first LED 5000d6 (that is, the first LED 5000d6) of the third LED row is compared with the output voltage Vout described later. The larger the difference is, the higher the error voltage Ver is.

  As described above, the error amplifier unit 4810b is configured to apply the voltage applied to the LED1 terminal to the LED6 terminal (the voltage applied to the cathode terminal of the LED 5000d6 in the final stage of each LED 5000d6 of the decorative board 5000d1 on the light guide plate and the decorative board 5000d2 below the light guide plate. ) Is monitored.

  The PWM comparator unit 4810c has one inverting input terminal (described as “−” in the drawing) and one non-inverting input terminal (described as “+” in the drawing). An error voltage Ver, which is a comparison result of the error amplifier unit 4810b, is applied to the inverting input terminal, while the voltage of the detection signal from the current detection unit 4810d and the oscillation unit (OSC) 4810e are applied to the inverting input terminal. A voltage obtained by adding the voltage of the triangular wave signal (hereinafter referred to as “addition voltage”) Vad is applied.

  The PWM comparator unit 4810c compares the error voltage Ver applied to the inverting input terminal with the addition voltage Vad applied to the non-inverting input terminal, and generates a duty ratio comparison signal according to the comparison result, thereby controlling the control unit 4810f. It is configured to output to.

  The current detection unit 4810d has two terminals (RP terminal, RP terminal) for detecting a voltage between terminals of a resistor LR1, which will be described later, which is electrically connected to the LED driver IC 4810 separately (that is, externally attached to the LED driver IC 4810). The current flowing through the resistor LR1 is detected based on the voltage applied via the (RN terminal), and the detection result can be output as a detection signal to the PWM comparator unit 4810c.

  The oscillating unit (OSC) 4810e is configured to generate a triangular wave voltage and output it as a triangular wave signal to the PWM comparator unit 4810c and output it to the control unit 4810f.

  The control unit 4810f is configured to generate a set signal and a reset signal based on the comparison signal from the PWM comparator unit 4810c and output the set signal and the reset signal to the SR flip-flop unit 4810g. The control unit 4810f controls ON / OFF of an N-channel field effect transistor LTr1 described later that is electrically connected to the SW terminal that is a switching terminal. The logic of the comparison signal from the PWM comparator unit 4810c is LOW ( In order to control the N-channel field effect transistor LTr1 to ON when it is (logic L), a set signal and a reset signal can be generated and output to the SR flip-flop unit 4810g, while the output from the PWM comparator unit 4810c When the logic of the comparison signal is HI (logic H), the set signal and the reset signal can be generated and output to the SR flip-flop unit 4810g in order to control the N-channel field effect transistor LTr1 to be OFF. It is configured. That is, the control unit 4810f is configured to be able to perform switching control capable of turning on / off the N-channel field effect transistor LTr1 via the SR flip-flop unit 4810g.

  The SR flip-flop unit 4810g has an S terminal that is a set terminal, an R terminal that is a reset terminal, a Q terminal that is an output terminal, and the like. A set signal from the control unit 4810f is input to the S terminal, and a reset signal from the control unit 4810f is input to the R terminal. The SR flip-flop unit 4810g receives a switching signal from the Q terminal which is an output terminal based on the set signal from the control unit 4810f input to the S terminal and the reset signal from the control unit 4810f input to the R terminal. The data is output to the output buffer unit 4810h. The switching signal is output to the N-channel field effect transistor LTr1 via the output buffer unit 4810h and the SW terminal which is a switching terminal.

  In the current driver unit 4810i, voltages applied to the first inverting input terminal to the sixth inverting input terminal of the error amplifier unit 4810b are applied. That is, the current driver unit 4810i is a voltage applied to the anode terminal of the first LED 5000d6 (that is, the first LED 5000d6) of the first LED row among the three LED rows of the light guide plate decorative substrate 500d1; Of the three LED rows of the decorative board 5000d1 on the light guide plate, the voltage applied to the anode terminal of the first LED 5000d6 (that is, the first LED 5000d6) of the second LED row, 3 of the decorative board 5000d1 on the light guide plate Among the LED rows of the third row, the voltage applied to the anode terminal of the first LED 5000d6 (that is, the first LED 5000d6) of the third LED row, and the LED row of the three rows of the light guide plate lower decorative substrate 5000d2 The anode end of the first LED 5000d6 (that is, the first LED 5000d6) of one LED row The voltage applied to the anode terminal of the first LED 5000d6 (that is, the first LED 5000d6) of the second LED row among the three LED rows of the light guide plate lower decorative board 5000d2, and Of the three LED rows on the under-lighting decorative board 5000d2, voltages applied to the anode terminals of the first LED 5000d6 (that is, the first LED 5000d6) of the third LED row are respectively applied.

  The current driver unit 4810i is electrically connected to one end of a resistor LR2 provided externally separately from the LED driver IC 4810 via an Is terminal which is a current setting terminal. The other end of the resistor LR2 is grounded to the ground (GND). The current driver unit 4810i can set the current flowing through the LEDs 5000d6 of the light guide plate upper decorative substrate 5000d1 and the light guide plate lower decorative substrate 5000d2 according to the resistance value of the resistor LR2. In the present embodiment, the current driver unit 4810i A resistance value set to 20 milliamperes (mA) is set in advance.

  Note that in the LED driver IC 4810, a GND terminal that is a ground terminal of the ground (GND) is grounded to the ground (GND) of the liquid crystal output substrate 3420.

  Next, a peripheral circuit of the DC / DC converter unit provided separately from the LED driver IC 4810 operating together with the PWM DC / DC converter unit in the LED driver IC 4810 will be described. The first light guide plate control circuit 3420k1 is a peripheral circuit of the DC / DC converter unit, and is externally attached to the LED driver IC 4810. The coil LL1, a Schottky barrier diode LD1 (hereinafter referred to as “diode LD1”), N. A chopper type booster circuit including electric components such as a channel type field effect transistor LTr1 (hereinafter referred to as “transistor LTr1”), a resistor LR1, and capacitors LC1 and LC2 is provided.

  This chopper type booster circuit drives the coil LL1 by turning ON / OFF the transistor LTr1, and among the various light guide plate power circuit 3420e on the game board side, from the first light guide plate power circuit to be controlled by the game board side VDP. The output voltage Vout is created by boosting the voltage Vp1 of the first light guide plate power supply.

  More specifically, the first power supply for the light guide plate (voltage Vp1) from the first light guide plate power supply circuit for the game board side VDP control among the various light guide plate power supply circuits 3420e for the game board is provided. The light guide plate power supply line and one end of the coil LL1 are electrically connected, and the other end of the coil LL1 is electrically connected to the drain of the transistor LTr1. The other end of the coil LL1 is electrically connected to the drain of the transistor LTr1, and is also electrically connected to the anode terminal of the diode LD1, and has one end grounded to the ground (GND). Is electrically connected to a Vin terminal which is a power supply terminal of the LED driver IC 4810.

  The cathode terminal of the diode LD1 is electrically connected to the other end of the capacitor LC2 whose one end is grounded to the ground (GND), so that the anode terminals (that is, the respective LED terminals) of the three LED rows on the light guide plate decorative substrate 5000d1 are provided. In the LED rows, the anode terminals of the leading LED 5000d6 in which six LEDs 5000d6 are electrically connected in series) and the anode terminals of the three rows of LED rows on the light guide plate lower decorative board 5000d2 (that is, six in each LED row) The LED 5000d6 of the first LED 5000d6 is electrically connected in series to the anode terminal of the first LED 5000d6.

  The gate terminal of the transistor LTr1 is electrically connected to the SW terminal that is the switching terminal of the LED driver IC 4810, and the source terminal of the transistor LTr1 is grounded to the ground (GND) via the resistor LR1.

  One end of the resistor LR1 that is electrically connected to the source terminal of the transistor LTr1 is electrically connected to the RP terminal of the LED driver IC 4810 and is grounded to the other end of the resistor LR1 (that is, the ground (GND)). Side) is electrically connected to the RN terminal.

  The transistor LTr1 is turned ON / OFF by an ON / OFF signal from the SW terminal which is a switching terminal of the LED driver IC 4810. When the transistor LTr1 is in an ON state, the switch current is turned into the coil LL1 by the first light guide plate power source from the game board side VDP control target first light guide plate power source circuit among the various light guide plate side power source circuit 3420e. Then, it flows toward the ground (GND) via the transistor LTr1 and the resistor LR1, and electric energy is stored in the coil LL1. As a result, the voltage applied to the anode terminal of the diode LD1 is pulled down to the ground (GND) side by the transistor LTr1. At this time, if the capacitor LC2 is charged while the transistor LTr1 is ON, the voltage applied to the cathode terminal of the diode LD1 is the voltage applied to the anode terminal of the diode LD1 (here, approximately the ground (GND) level). In contrast, the reverse bias is applied to the diode LD1 and the current discharged from the capacitor LC2 is prevented from flowing toward the transistor LTr1. Thus, the three LED rows on the light guide plate upper decorative substrate 5000d1 and the three LED rows on the light guide plate lower decorative substrate 5000d2 flow.

  On the other hand, when the transistor LTr1 is turned off, the electric energy stored in the coil LL1 is released to generate a counter electromotive voltage in the coil LL1. As a result, the forward bias is applied to the diode LD1 because the voltage applied to the anode terminal of the diode LD1 becomes higher than the cathode terminal of the diode LD1 to which the voltage is applied by discharging the capacitor LC2. In the game board side various light guide plate power circuit 3420e, the current from the first light guide plate power supply from the game board side VDP control target first light guide plate power supply circuit is 3 on the light guide plate decoration board 5000d1. It flows toward the LED rows of the rows and the three rows of LED rows on the light guide plate lower decorative substrate 5000d2. As a result, the voltage applied to the capacitor LC2 can be boosted by charging the capacitor LC2.

  In this way, the LED driver IC 4810 outputs an ON / OFF signal from the SW terminal, which is a switching terminal, to the transistor LTr1, thereby turning on / off the transistor LTr1, thereby storing and releasing electrical energy in the coil LL1. As a result, a counter electromotive voltage is generated in the coil LL1 and rectified by the diode LD1 and the capacitor LC2. From among the various light guide plate power circuit 3420e on the game board side, the first light guide plate power circuit on the game board side VDP control target A predetermined voltage (DC voltage) higher than the voltage Vp1 of the first power supply for the light guide plate is set as an output voltage Vout, and three LED rows in the light guide plate upper decorative substrate 5000d1 and three in the light guide plate lower decorative substrate 5000d2 are used. Each of the LED rows can be supplied.

  Since the resistor LR1 can detect the switch current flowing through the transistor LTr1, the current detection unit 4810d in the LED driver IC 4810 monitors the switch current flowing through the transistor LTr1.

  As described above, in the first light guide plate control circuit 3420k1, the LED driver IC 4810 applies the voltages applied to the LED1 terminal to the LED6 terminal (each of the light guide plate upper decorative substrate 5000d1 and the light guide plate lower decorative substrate 5000d2). The voltage applied to the cathode terminal of the LED 5000d6 in the final stage of the LED 5000d6) is monitored by the error amplifier unit 4810b, and the switch current flowing through the transistor LTr1 is monitored by the current detection unit 4810d. As a result, switch control for turning on / off the transistor LTr1 can be performed by the control unit 4810f. This makes it difficult for the control unit 4810f to follow the error voltage Ver described above because voltage fluctuations of the LED1 to LED6 terminals applied to the inverting input terminal of the error amplifier unit 4810b become steep. In this case, the transistor LTr1 can be turned on / off according to the result of monitoring the switch current flowing in the transistor LTr1 by the current detection unit 4810d, so that the fluctuation of the output voltage Vout can be suppressed. By suppressing such fluctuations in the output voltage Vout, it is not necessary to use a large capacitor having a large capacity as the capacitor LC2, which can contribute to cost reduction and the liquid crystal output substrate 3420 of the capacitor LC2. By suppressing the mounting area at, a layout in which other electronic components are arranged on the liquid crystal output substrate 3420 can be contributed.

[12-2-2. Game board side decoration LED control circuit]
In this embodiment, the game board side VDP control target first decoration LED control circuit 3420i1 to the game board side VDP control target 27th decoration LED control circuit 3420i27 are the same decoration LED driver IC as described above. And a plurality of LEDs (decoration) provided on each of the plurality of game board side VDP control target decoration boards that are controlled by the built-in sound source VDP 4160a among the decoration boards of the game board 4. LED) can be dimmed and lit. Here, the game board side VDP control target first decoration LED control circuit 3420i1 will be briefly described below, and the game board side VDP control target second decoration LED control circuit 3420i2 to the game board side VDP control target No. 27. The description of the decorative LED control circuit 3420i27 will be omitted.

  As shown in FIG. 37, the decoration LED driver IC that constitutes the first decoration LED control circuit 3420i1 for the game board side VDP control has 24 output channels (ch), and each channel has a maximum of 80 mA (mA). ) Is a 24ch constant current LED driver IC. The decoration LED driver IC mainly includes an address setting unit 3420i1a, a logic processing unit 3420i1b, a clock generation unit 3420i1c, a data buffer unit 3420i1d, a PWM unit 3420i1e, and a constant current drive unit 3420i1f.

  The address setting unit 3420i1a can set 64 addresses as its own ID (an ID for identifying an individual) depending on the magnitude of the voltage applied to three address setting terminals (not shown). Yes. The voltage applied to the three address setting terminals is any one of a control voltage (+ 5V) DVp, 2 / 3DVp, 1 / 3DVp, and ground (GND), and 2 / 3DVp and 1 / 3DVp are control power supply DVp. And ground (GND) are divided by a plurality of resistors (not shown) electrically connected in series and taken out.

  For example, the control power supply DVp is supplied to one end of the first resistor, the other end of the first resistor is electrically connected to one end of the second resistor, and the other end of the second resistor is the third resistor. It is electrically connected to one end, and the other end of the third resistor is grounded to the ground (GND), and the resistance values of the three resistors are the same. As a result, the voltage at which the other end of the second resistor and the one end of the third resistor are electrically connected becomes 1/3 DVp, which is a third of the control voltage DVp, and the first resistor The voltage at which the other end of the second resistor and one end of the second resistor are electrically connected is 2/3 DVp, which is two-thirds of the control voltage DVp.

  In this way, the ID that can identify the individual decoration LED driver ICs constituting the first decoration LED control circuit 3420i1 for the game board side VDP control is a hardware that is a voltage applied to the three address setting terminals. It is set in advance by the address setting unit 3420i1a depending on the configuration of the hardware, and is not set as appropriate by receiving data from software.

  The logic processing unit 3420i1b receives the serial data SDAT3 from the third serial controller 3420gd3 in the game board side signal separation control circuit 3420g based on the clock signal SCLK3 and transmits it to the data buffer unit 3420i1d. When the data buffer unit 3420i1d includes its own ID in the illumination LED designation information in the serial data SDAT3 from the logic processing unit 3420i1b based on the address that is its own ID set by the address setting unit 3420i1a, It is determined that the serial data SDAT3 from the processing unit 3420i1b is for itself, the gradation level which is the gradation information in the serial data SDAT3 is captured, and the gradation level which is the captured gradation information is obtained in each channel. While the control is performed to set the gradation level in the PWM unit 3420i1e, when the ID is not included in the illumination LED designation information in the serial data SDAT3 from the logic processing unit 3420i1b, the shim from the logic processing unit 3420i1b is used. Without taking the gradient is the tone information in the serial data SDAT3 determines that certain data SDAT3 is not for itself, control is performed to maintain the contents of the current state that is set in the PWM unit 3420I1e.

  The PWM unit 3420i1e can perform gradation control of the brightness (gradation degree) of the LED in each channel in 128 steps from gradation 0 (zero) to gradation degree 127 from turning off to lighting (maximum luminance). The gradation control is performed for one channel by one PWM gradation control unit. That is, the PWM unit 3420i1e performs gradation control by the PWM gradation control unit 1 for the decoration LED in 1ch, and gradation control by the PWM gradation control unit 2 for the decoration LED in 2ch,... In addition, a total of 24 PWM gradation control units 1 to PWM gradation control unit 24, in which gradation control is performed by the PWM gradation control unit 24 on the decoration LEDs in 24ch, are configured. When the gradation levels are set, the PWM gradation control unit 1 to the PWM gradation control unit 24, based on the clock signal from the clock generation unit 3420i1c, cause a constant current to flow. The drive unit 3420i1f is controlled.

  The constant current drive unit 3420i1f is a full color LED that is a decoration LED by one constant current driver for one channel so as to have the gradation set in the PWM gradation control unit 1 to the PWM gradation control unit 24. A constant current is made to flow through the LED elements constituting the circuit element, and is composed of a total of 24 constant current drivers 1 to 24.

  The constant current driver 1 to the constant current driver 8 are electrically connected to one end of a resistor Rr1 for setting the maximum current to flow through the decoration LED in eight channels from 1ch to 8ch, and the other end of the resistor Rr1 is grounded. (GND) is grounded, and one end of a resistor Rg1 for setting the maximum current to flow through the decoration LED in the eight channels from 9ch to 16ch is electrically connected to the constant current driver 9 to the constant current driver 16 The other end of the resistor Rg1 is grounded to the ground (GND), and the constant current driver 17 to the constant current driver 24 have one end of the resistor Rb1 for setting the maximum current to flow through the decoration LED in the eight channels from 17ch to 24ch. It is electrically connected and the other end of the resistor Rb1 is grounded to the ground (GND).

  The anode terminal of the red LED element, the anode terminal of the green LED element, and the anode terminal of the blue LED element constituting the full-color LED respectively corresponding to the constant current driver 1 to the constant current driver 24 are an electric power source for decoration ( Control power supply). The cathode terminals of the red LED elements constituting the full-color LEDs respectively corresponding to the constant current driver 1 to the constant current driver 8 are electrically connected to the LR1 terminal to the LR8 terminal, and are connected to the constant current driver 9 to the constant current driver 16, respectively. The cathode terminal of the green LED element constituting the corresponding full color LED is electrically connected to the LG1 terminal to LG8 terminal, and the blue LED element constituting the full color LED corresponding to the constant current driver 17 to constant current driver 24, respectively. The cathode terminal is electrically connected to the LB1 terminal to LB8 terminal.

  The constant current driver 1 to the constant current driver 8 apply constant currents LR1 individually set to the red LED elements constituting the full color LED, which is a decoration LED corresponding to each of the eight channels 1ch to 8ch. The constant current driver 9 to the constant current driver 16 are individually supplied to the green LED elements constituting the full-color LED corresponding to the eight channels from 9ch to 16ch, respectively. The constant current set to 1 is passed through the LG1 to LG8 terminals, respectively, and the constant current driver 17 to constant current driver 24 constitutes a full-color LED that is a decoration LED corresponding to each of the eight channels from 17ch to 24ch. Constant current set individually for each blue LED element Flow, respectively, via the B1 terminal ~LB8 terminal.

  It should be noted that the control voltage DVp is applied to the power supply terminal of the decorative LED driver IC that constitutes the first decorative LED control circuit 3420i1 for the game board side VDP control, whereby various internal components of the decorative LED driver IC are used as the internal power supply Vreg. The GND terminal as a ground terminal is grounded to the ground (GND), so that the ground in various internal circuits of the decoration LED driver IC is grounded to the ground (GND) of the liquid crystal output substrate 3420.

  In this way, the decoration LED driver ICs constituting the game board side VDP control target first decoration LED control circuit 3420i1 to the game board side VDP control target 27th decoration LED control circuit 3420i27, respectively, have 24 LED elements. In other words, since eight full-color LEDs, which are decorative LEDs, can be dimmed and lit individually, such dimming can be turned off, lit with one gradation, flashed with one gradation, etc. it can. In addition, there are 216 decoration LED driver ICs as decoration LEDs that respectively constitute the game board side VDP control target first decoration LED control circuit 3420i1 to the game board side VDP control target 27th decoration LED control circuit 3420i27. = 8 full-color LEDs x 27 decorative LED control circuits (decorative LED driver IC)) full-color LEDs, that is, 648 (= 3 LED elements of red, green, and blue x 216 full-color LEDs) It is possible to perform dimming and lighting of an extremely large number of decorative LEDs, i.e., LED elements.

  Further, the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 does not directly output a signal for dimming and lighting individually to a plurality of LEDs provided on each decoration board of the game board 4. The game board side VDP control target first decoration LED control circuit 3420i1 to the game board side VDP control target 27th decoration LED control circuit 3420i27, which is a circuit different from the peripheral control MPU 4150a, is provided on each decoration board of the game board 4 By directly outputting signals for dimming and lighting individually to the plurality of LEDs provided, the delicate and processing load control of the dimming of these LEDs is separated from the control by the peripheral control MPU 4150a. Game board side VDP control target first decorative LED control circuit 3420i1-game board side VDP control pair It can be left respectively to the first 27 of the decorative LED control circuit 3420I27.

  As described above, the light guide plate information and the electrical decoration information are stored in each of the plurality of game board side VDP control target decoration boards that are controlled by the sound source built-in VDP 4160a among the decoration boards of the game board 4. A plurality of game board side light emission mode setting image data for setting the light emission mode of the plurality of LEDs (decorative LEDs) provided are stored in advance in the liquid crystal and sound control ROM 4160b. The peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 is a plurality of game board side VDP control target decorative boards that are controlled by the sound source built-in VDP 4160a directly among the decorative boards of the game board 4. The control which requires detailed processing load such as dimming and lighting of a plurality of LEDs (decorative LEDs) provided in each of the first LED control circuit 3420i1 for the game board side VDP control object and the VDP control object for the game board side 27 can be entrusted to each of the 27 decorative LED control circuits 3420i27, so that it is possible to reduce the processing load of light emission control of dimming lighting on the peripheral control MPU 4150a. As a result, even if the variation of the effects by the game board side VDP control target first decoration LED control circuit 3420i1 to the game board side VDP control target 27th decoration LED control circuit 3420i27 is increased, the peripheral control MPU 4150a is controlled. Since the processing load of the light emission control of dimming lighting does not increase, there is no limitation on the variation of effects. In other words, in the present embodiment, the variation of the production can be increased while reducing the processing load of the light emission control for the peripheral control MPU 4150a, so that the player's interest in the production can be made difficult to fade. . Therefore, it can contribute to suppressing a decrease in interest.

  In the present embodiment, as described above, the game board side VDP control target first decoration LED control circuit 3420i1 to the game board side VDP control target 27th decoration LED control circuit 3420i27 is a game board side signal separation. When the serial data SDAT3 to SDAT11 from the third serial controller 3420gd3 to the eleventh serial controller 3420gd11 in the control circuit 3420g are received based on the clock signal SCLK3 to the clock signal SCLK11, the illumination LED designation in the serial data SDAT3 to SDAT11 is specified. When the information does not include its own ID, the gradation information in the serial data SDAT3 to SDAT11 is not taken in, and the sound of the decorative boards of the corresponding game board 4 is not recorded. For the plurality of LEDs (decorative LEDs) provided on each of the plurality of gaming board side VDP control target decorative boards that are controlled by the built-in VDP 4160a, the gradation level, which is the gradation information captured last time, is set. Configured to maintain.

  In the present embodiment, as described above, since the frame frequency is set to 30 fps (approximately every 33.3 ms), drawing data is output to the liquid crystal output board 3420 from the channel CH1 of the sound source built-in VDP 4160a. Yes. As a result, the first decoration LED control circuit 3420i1 to the game board side VDP control target 27th decoration LED control circuit 3420i27 of the game board side VDP control object has a gradation level that is gradation information about every 33.3 ms. Since the gradation information in the drawing data output from the channel CH1 of the sound source built-in VDP 4160a has been changed to something different from the normal content for some electrical reason. Even if it is taken in this time, it is possible to obtain the opportunity to take in the regular contents next time, that is, after about 33.3 ms, so that the sound source among the decorative boards of the game board 4 can be obtained in a very short period of about 33.3 ms. A plurality of game board side VDP control target decorations that are controlled by the built-in VDP 4160a directly Even if the light emission mode of the plurality of LEDs (decorative LEDs) provided on each of the boards changes from the normal light emission mode to the unintended light emission mode, the player is not aware of the change and the normal light emission mode (that is, normal) Light emission mode).

  The game board side VDP control target first decoration LED control circuit 3420i1 to the game board side VDP control target 27th decoration LED control circuit 3420i27 is a back box of the back unit 3000 of the game board 4 shown in FIG. 3001 is provided around the game board side VDP control target decorative board provided in the rotary light emitting device 3100, and around the rotary light emitting device 3100, a model 3400 imitating a detonator, and a model 3500 imitating dynamite in the back box 3001. The rotary light emitting device 3100 emits light (rotation light emission mode) by performing dimming lighting of a plurality of LEDs (decorative LEDs) provided on the game board side VDP control target decoration board provided in each of the plurality of decoration members. In addition, a plurality of decorative members are decorated with light emission.

  In the embodiment, all the decoration LEDs whose light emission modes are controlled by the game board side VDP control target first decoration LED control circuit 3420i1 to the game board side VDP control target 27th decoration LED control circuit 3420i27 are all full color. A red LED element, a green LED element, and a blue LED element that constitute the LED are used, but a single LED different from a full-color LED (the same color LED may be used, or a plurality of different color LEDs) One group may be a full color LED and the other group may be a single LED (the same color LED or a plurality of different color LEDs). A single group and a plurality of other groups may be combined.

[12-2-3. Light guide plate information]
Here, a method for selecting one of the plurality of light guide plates provided in the game board side effect display unit 1900 will be briefly described. As described above, the gaming board side effect display unit 1900 includes the first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000g, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and The sixth light guide plate 5000k includes a plurality of light guide plates.

  As described above, the built-in sound source VDP 4160a of the liquid crystal and sound control unit 4160 on the peripheral control board 4140 includes screen data defining the configuration of the screen drawn on the game board side effect display unit 1900 (liquid crystal panel 5000e), and the game board. Among the four decorative boards, the light emission mode of a plurality of LEDs (decorative LEDs) provided on each of the plurality of game board side VDP control target decorative boards that are controlled by the built-in sound source VDP 4160a is defined. When the light emission data is input from the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140, the peripheral control board 4140 is based on the input screen data according to the above-described predetermined game board generation rules. From the liquid crystal and sound control ROM 4160b of the liquid crystal and sound control unit 4160. The game board side drawing data area of the game board side display area VRGN1 provided on the built-in VRAM by extracting the game board side character data for drawing in the display area of the board side effect display unit 1900 and creating sprite data. The game board-side drawing data is generated in the VRGN 1a, and based on the input light emission data, among the decorative boards of the game board 4 from the liquid crystal and sound control ROM 4160b, the sound source built-in VDP 4160a is directly controlled. Game board side light emission mode setting image data for setting a light emission mode of a plurality of LEDs (decorative LEDs) provided on each of the plurality of game board side VDP control target decorative boards is extracted, and light guide plate information and electrical decoration are extracted. For information related to the game board side of the game board side display area VRGN1 provided on the built-in VRAM as drawing data. To generate in-band VRGN1b.

  As described above, the light guide plate information designates information using one light guide plate as a backlight among the plurality of light guide plates provided in the game board side effect display unit 1900 (in other words, the game board side effect display unit 1900). Information for selecting (switching) one of the light guide plates among the plurality of light guide plates included in the light guide plate, and includes light guide plate designation information and luminance information.

[12-2-3a. Light guide plate information when selecting the first light guide plate]
For example, when the first light guide plate 5000d is selected (switched to the first light guide plate 5000d), the LEDs 5000d6 on the light guide plate upper decorative substrate 5000d1 and the light guide plate lower decorative substrate 5000d2 in the first light guide plate 5000d are turned on. Therefore, as the light guide plate information, the ID of the first light guide plate PWM control circuit 4950 of the first light guide plate control circuit 3420k1 provided in the liquid crystal output substrate 3420 is set in the light guide plate designation information, and the luminance information As described above, data for setting the luminance of the LED to the maximum luminance (100%) is set. At this time, the second light guide plate 5000f, the third light guide plate 5000g, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k are provided on the upper end surface and the lower end surface, respectively. In order to extinguish the LEDs 5000f6, 5000g6, 5000h6, 5000i6, 5000k6 on the light plate decoration board 5000f1, 5000g1, 5000h1, 5000i1, 5000k1, and the light guide plate lower decoration board 5000f2, 5000g2, 5000h2, 5000i2, 5000k2, as light guide plate information The second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2 and the third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3 included in the liquid crystal output substrate 3420 are included in the light guide plate designation information. , 4th light guide plate system Fourth light guide plate PWM control circuit 4955 of circuit 3420k4, fifth light guide plate PWM control circuit 4965 of fifth light guide plate control circuit 3420k5, and sixth light guide plate PWM control circuit of sixth light guide plate control circuit 3420k6 Each ID of 4975 is set, and data for turning off the LED is set as luminance information.

  The sound source built-in VDP 4160a is a predetermined game board side generation rule in which the light guide plate information and the electrical decoration information are added to the game board side drawing data of the screen drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). The drawing data generated in the game board display area VRGN1 is output from the channel CH1.

  The drawing data output from the channel CH1 is, as described above, the game board side effect display unit 1900 (liquid crystal display) in the first resolution conversion unit 3420gaa of the signal separation unit 3420ga in the game board side signal separation control circuit 3420g of the liquid crystal output board 3420. A plurality of game board side effect display units 1900 provided in the second resolution conversion unit 3420gab of the signal separation unit 3420ga in the game board side signal separation control circuit 3420g of the liquid crystal output board 3420. Light guide plate information for selecting one of the light guide plates, and among the decorative boards of the game board 4, a plurality of game board side VDP control target decorative boards that are controlled by the sound source built-in VDP 4160 a are directly controlled. Multiple LEDs (decorative LEDs) provided for each Against is separated into, and illuminations information. Based on the clock signal SCLK1 as serial data SDAT1 from the first serial controller 3420gd1, the separated light guide plate information is converted into the first light guide plate PWM control circuit 4950 and the second light guide plate control of the first light guide plate control circuit 3420k1. The second light guide plate PWM control circuit 4960 of the circuit 3420k2 and the third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3 are output to the clock signal SCLK2 as serial data SDAT2 from the second serial controller 3420gd2. Based on the fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4, the fifth light guide plate PWM control circuit 4965 of the fifth light guide plate control circuit 3420k5, and the sixth light guide plate control circuit 3420k6. Sixth light guide plate PWM control circuit And outputs it to 975.

  As a result, the first light guide plate PWM control circuit 4950 of the first light guide plate control circuit 3420k1 sets the duty ratio of the first light guide plate PWM signal so that the luminance of the LED becomes the maximum luminance (100%). Control to output to the LED driver IC 4810 of the first light guide plate control circuit 3420k1, and the second light guide plate PWM control circuit 4960 and the third light guide plate control circuit 3420k3 of the second light guide plate control circuit 3420k2. The third light guide plate PWM control circuit 4970, the fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4, the fifth light guide plate PWM control circuit 4965 of the fifth light guide plate control circuit 3420k5, and the sixth. The sixth light guide plate PWM control circuit 4975 of the light guide plate control circuit 3420k6 includes the second light guide plate PWM signal to the sixth light guide plate PW. The LED driver IC 4830 of the second light guide plate control circuit 3420k2, the LED driver IC 4850 of the third light guide plate control circuit 3420k3, and the LED driver IC 4815 of the fourth light guide plate control circuit 3420k4 by setting the duty ratio of the signal to 0%. The LED driver IC 4835 of the fifth light guide plate control circuit 3420k5 and the LED driver IC 4855 of the sixth light guide plate control circuit 3420k6 are controlled to output.

[12-2-3b. Light guide plate information when selecting the second light guide plate]
For example, when the second light guide plate 5000f is selected (switched to the second light guide plate 5000f), the LEDs 5000f6 of the light guide plate upper decorative substrate 5000f1 and the light guide plate lower decorative substrate 5000f2 in the second light guide plate 5000f are turned on. Therefore, as the light guide plate information, the ID of the second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2 provided in the liquid crystal output substrate 3420 is set in the light guide plate designation information, and the luminance information As described above, data for setting the luminance of the LED to the maximum luminance (100%) is set. At this time, the first light guide plate 5000d, the third light guide plate 5000g, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k are provided on the upper end surface and the lower end surface. Light guide plate information for turning off the LEDs 5000d6, 5000g6, 5000h6, 5000i6, 5000k6 on the light plate decorative substrate 5000d1, 5000g1, 5000h1, 5000i1, 5000k1 and the light guide plate lower decorative substrate 5000d2, 5000g2, 5000h2, 5000i2, 5000k2 In the light guide plate designation information, the first light guide plate PWM control circuit 4950 of the first light guide plate control circuit 3420k1 provided on the liquid crystal output substrate 3420, and the third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3. , 4th light guide plate system Fourth light guide plate PWM control circuit 4955 of circuit 3420k4, fifth light guide plate PWM control circuit 4965 of fifth light guide plate control circuit 3420k5, and sixth light guide plate PWM control circuit of sixth light guide plate control circuit 3420k6 Each ID of 4975 is set, and data for turning off the LED is set as luminance information.

  The sound source built-in VDP 4160a is a predetermined game board side generation rule in which the light guide plate information and the electrical decoration information are added to the game board side drawing data of the screen drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). The drawing data generated in the game board display area VRGN1 is output from the channel CH1.

  The drawing data output from the channel CH1 is, as described above, the game board side effect display unit 1900 (liquid crystal display) in the first resolution conversion unit 3420gaa of the signal separation unit 3420ga in the game board side signal separation control circuit 3420g of the liquid crystal output board 3420. A plurality of game board side effect display units 1900 provided in the second resolution conversion unit 3420gab of the signal separation unit 3420ga in the game board side signal separation control circuit 3420g of the liquid crystal output board 3420. Light guide plate information for selecting one of the light guide plates, and among the decorative boards of the game board 4, a plurality of game board side VDP control target decorative boards that are controlled by the sound source built-in VDP 4160 a are directly controlled. Multiple LEDs (decorative LEDs) provided for each Against is separated into, and illuminations information. Based on the clock signal SCLK1 as serial data SDAT1 from the first serial controller 3420gd1, the separated light guide plate information is converted into the first light guide plate PWM control circuit 4950 and the second light guide plate control of the first light guide plate control circuit 3420k1. The second light guide plate PWM control circuit 4960 of the circuit 3420k2 and the third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3 are output to the clock signal SCLK2 as serial data SDAT2 from the second serial controller 3420gd2. Based on the fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4, the fifth light guide plate PWM control circuit 4965 of the fifth light guide plate control circuit 3420k5, and the sixth light guide plate control circuit 3420k6. Sixth light guide plate PWM control circuit And outputs it to 975.

  Accordingly, the second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2 sets the duty ratio of the second light guide plate PWM signal so that the luminance of the LED is set to the maximum luminance (100%). To the LED driver IC 4830 of the second light guide plate control circuit 3420k2, and the first light guide plate PWM control circuit 4950 and the third light guide plate control circuit 3420k3 of the first light guide plate control circuit 3420k1. The third light guide plate PWM control circuit 4970, the fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4, the fifth light guide plate PWM control circuit 4965 of the fifth light guide plate control circuit 3420k5, and the sixth. The sixth light guide plate PWM control circuit 4975 of the light guide plate control circuit 3420k6 includes the first light guide plate PWM signal and the third light guide plate PW. The LED driver IC 4810 of the first light guide plate control circuit 3420k2, the LED driver IC 4850 of the third light guide plate control circuit 3420k3, the fourth duty ratio of the signal to the sixth light guide plate PWM signal are set to zero%, respectively. Output control is performed to the LED driver IC 4815 of the light guide plate control circuit 3420k4, the LED driver IC 4835 of the fifth light guide plate control circuit 3420k5, and the LED driver IC 4855 of the sixth light guide plate control circuit 3420k6.

[12-2-3c. Light guide plate information when selecting the third light guide plate]
For example, when the third light guide plate 5000g is selected (switched to the third light guide plate 5000g), the LEDs 5000g6 of the light guide plate upper decorative substrate 5000g1 and the light guide plate lower decorative substrate 5000g2 in the third light guide plate 5000g are turned on. Therefore, as the light guide plate information, the ID of the third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3 provided in the liquid crystal output substrate 3420 is set in the light guide plate designation information, and the luminance information As described above, data for setting the luminance of the LED to the maximum luminance (100%) is set. At this time, the first light guide plate 5000d, the second light guide plate 5000f, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k are provided on the upper end surface and the lower end surface. In order to extinguish each LED 5000d6, 5000f6, 5000h6, 5000i6, 5000k6 of the light board decoration board 5000d1, 5000f1, 5000h1, 5000i1, 5000k1 and the light guide board decoration board 5000d2, 5000f2, 5000h2, 5000i2, 5000k2, as light guide plate information In the light guide plate designation information, the first light guide plate PWM control circuit 4950 of the first light guide plate control circuit 3420k1 and the second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2 included in the liquid crystal output substrate 3420. , 4th light guide plate system Fourth light guide plate PWM control circuit 4955 of circuit 3420k4, fifth light guide plate PWM control circuit 4965 of fifth light guide plate control circuit 3420k5, and sixth light guide plate PWM control circuit of sixth light guide plate control circuit 3420k6 Each ID of 4975 is set, and data for turning off the LED is set as luminance information.

  The sound source built-in VDP 4160a is a predetermined game board side generation rule in which the light guide plate information and the electrical decoration information are added to the game board side drawing data of the screen drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). The drawing data generated in the game board display area VRGN1 is output from the channel CH1.

  The drawing data output from the channel CH1 is, as described above, the game board side effect display unit 1900 (liquid crystal display) in the first resolution conversion unit 3420gaa of the signal separation unit 3420ga in the game board side signal separation control circuit 3420g of the liquid crystal output board 3420. A plurality of game board side effect display units 1900 provided in the second resolution conversion unit 3420gab of the signal separation unit 3420ga in the game board side signal separation control circuit 3420g of the liquid crystal output board 3420. Light guide plate information for selecting one of the light guide plates, and among the decorative boards of the game board 4, a plurality of game board side VDP control target decorative boards that are controlled by the sound source built-in VDP 4160 a are directly controlled. Multiple LEDs (decorative LEDs) provided for each Against is separated into, and illuminations information. Based on the clock signal SCLK1 as serial data SDAT1 from the first serial controller 3420gd1, the separated light guide plate information is converted into the first light guide plate PWM control circuit 4950 and the second light guide plate control of the first light guide plate control circuit 3420k1. The second light guide plate PWM control circuit 4960 of the circuit 3420k2 and the third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3 are output to the clock signal SCLK2 as serial data SDAT2 from the second serial controller 3420gd2. Based on the fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4, the fifth light guide plate PWM control circuit 4965 of the fifth light guide plate control circuit 3420k5, and the sixth light guide plate control circuit 3420k6. Sixth light guide plate PWM control circuit And outputs it to 975.

  Accordingly, the third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3 sets the duty ratio of the third light guide plate PWM signal so that the luminance of the LED is the maximum luminance (100%). To the LED driver IC 4850 of the third light guide plate control circuit 3420k3, and the first light guide plate PWM control circuit 4950 and the second light guide plate control circuit 3420k2 of the first light guide plate control circuit 3420k1. Second light guide plate PWM control circuit 4960, fourth light guide plate PWM control circuit 4955 of fourth light guide plate control circuit 3420k4, fifth light guide plate PWM control circuit 4965 of fifth light guide plate control circuit 3420k5, and sixth. The sixth light guide plate PWM control circuit 4975 of the light guide plate control circuit 3420k6 includes a first light guide plate PWM signal and a second light guide plate PW. The LED driver IC 4810 and the second light guide plate control circuit of the first light guide plate control circuit 3420k2 by setting the duty ratio of the signals, the fourth light guide plate PWM signal to the sixth light guide plate PWM signal to zero%, respectively. 3420k2 LED driver IC 4830, fourth light guide plate control circuit 3420k4 LED driver IC 4815, fifth light guide plate control circuit 3420k5 LED driver IC 4835, and sixth light guide plate control circuit 3420k6 LED driver IC 4855. Do.

[12-2-3d. Light guide plate information when selecting the fourth light guide plate]
For example, when the fourth light guide plate 5000h is selected (switched to the fourth light guide plate 5000h), the LEDs 5000h6 on the light guide plate upper decorative substrate 5000h1 and the light guide plate lower decorative substrate 5000h2 in the fourth light guide plate 5000h are turned on. Therefore, as the light guide plate information, the ID of the fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4 included in the liquid crystal output substrate 3420 is set in the light guide plate designation information, and the luminance information As described above, data for setting the luminance of the LED to the maximum luminance (100%) is set. At this time, the first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000g, the fifth light guide plate 5000i, and the sixth light guide plate 5000k are provided on the upper end surface and the lower end surface. In order to turn off the LEDs 5000d6, 5000f6, 5000g6, 5000i6, and 5000k6 on the light-plate decorative board 5000d1, 5000f1, 5000g1, 5000i1, 5000k1 and the light-guided board decorative board 5000d2, 5000f2, 5000g2, 5000i2, 5000k2, In the light guide plate designation information, the first light guide plate PWM control circuit 4950 of the first light guide plate control circuit 3420k1 and the second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2 included in the liquid crystal output substrate 3420. The third light guide plate system Third light guide plate PWM control circuit 4970 of circuit 3420k3, fifth light guide plate PWM control circuit 4965 of fifth light guide plate control circuit 3420k5, and sixth light guide plate PWM control circuit of sixth light guide plate control circuit 3420k6 Each ID of 4975 is set, and data for turning off the LED is set as luminance information.

  The sound source built-in VDP 4160a is a predetermined game board side generation rule in which the light guide plate information and the electrical decoration information are added to the game board side drawing data of the screen drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). The drawing data generated in the game board display area VRGN1 is output from the channel CH1.

  The drawing data output from the channel CH1 is, as described above, the game board side effect display unit 1900 (liquid crystal display) in the first resolution conversion unit 3420gaa of the signal separation unit 3420ga in the game board side signal separation control circuit 3420g of the liquid crystal output board 3420. A plurality of game board side effect display units 1900 provided in the second resolution conversion unit 3420gab of the signal separation unit 3420ga in the game board side signal separation control circuit 3420g of the liquid crystal output board 3420. Light guide plate information for selecting one of the light guide plates, and among the decorative boards of the game board 4, a plurality of game board side VDP control target decorative boards that are controlled by the sound source built-in VDP 4160 a are directly controlled. Multiple LEDs (decorative LEDs) provided for each Against is separated into, and illuminations information. Based on the clock signal SCLK1 as serial data SDAT1 from the first serial controller 3420gd1, the separated light guide plate information is converted into the first light guide plate PWM control circuit 4950 and the second light guide plate control of the first light guide plate control circuit 3420k1. The second light guide plate PWM control circuit 4960 of the circuit 3420k2 and the third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3 are output to the clock signal SCLK2 as serial data SDAT2 from the second serial controller 3420gd2. Based on the fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4, the fifth light guide plate PWM control circuit 4965 of the fifth light guide plate control circuit 3420k5, and the sixth light guide plate control circuit 3420k6. Sixth light guide plate PWM control circuit And outputs it to 975.

  Accordingly, the fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4 sets the duty ratio of the fourth light guide plate PWM signal so that the luminance of the LED becomes the maximum luminance (100%). To the LED driver IC 4815 of the fourth light guide plate control circuit 3420k4 and the first light guide plate PWM control circuit 4950 and the second light guide plate control circuit 3420k2 of the first light guide plate control circuit 3420k1. Second light guide plate PWM control circuit 4960, third light guide plate PWM control circuit 4970 of third light guide plate control circuit 3420k3, fifth light guide plate PWM control circuit 4965 of fifth light guide plate control circuit 3420k5, and sixth. The sixth light guide plate PWM control circuit 4975 of the light guide plate control circuit 3420k6 includes a first light guide plate PWM signal to a third light guide plate PW. The LED driver IC 4810 and the second light guide plate control circuit of the first light guide plate control circuit 3420k2 by setting the duty ratio of the signal, the fifth light guide plate PWM signal, and the sixth light guide plate PWM signal to 0%, respectively. 3420k2 LED driver IC 4830, third light guide plate control circuit 3420k3 LED driver IC 4850, fifth light guide plate control circuit 3420k5 LED driver IC 4835, and sixth light guide plate control circuit 3420k6 LED driver IC 4855. Do.

[12-2-3e. Light guide plate information when the fifth light guide plate is selected]
For example, when the fifth light guide plate 5000i is selected (switched to the fifth light guide plate 5000i), the LEDs 5000i6 on the light guide plate upper decorative substrate 5000i1 and the light guide plate lower decorative substrate 5000i2 in the fifth light guide plate 5000i are turned on. Therefore, as the light guide plate information, the ID of the fifth light guide plate PWM control circuit 4965 of the fifth light guide plate control circuit 3420k5 provided in the liquid crystal output substrate 3420 is set in the light guide plate designation information, and the luminance information As described above, data for setting the luminance of the LED to the maximum luminance (100%) is set. At this time, the first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000g, the fourth light guide plate 5000h, and the sixth light guide plate 5000k are provided on the upper end surface and the lower end surface. In order to extinguish the LEDs 5000d6, 5000f6, 5000g6, 5000h6, 5000k6 on the light plate decorative board 5000d1, 5000f1, 5000g1, 5000h1, 5000k1 and the light guide board lower decorative board 5000d2, 5000f2, 5000g2, 5000h2, 5000k2, as light guide plate information In the light guide plate designation information, the first light guide plate PWM control circuit 4950 of the first light guide plate control circuit 3420k1 and the second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2 included in the liquid crystal output substrate 3420. The third light guide plate system Third light guide plate PWM control circuit 4970 of circuit 3420k3, fourth light guide plate PWM control circuit 4955 of fourth light guide plate control circuit 3420k4, and sixth light guide plate PWM control circuit of sixth light guide plate control circuit 3420k6 Each ID of 4975 is set, and data for turning off the LED is set as luminance information.

  The sound source built-in VDP 4160a is a predetermined game board side generation rule in which the light guide plate information and the electrical decoration information are added to the game board side drawing data of the screen drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). The drawing data generated in the game board display area VRGN1 is output from the channel CH1.

  The drawing data output from the channel CH1 is, as described above, the game board side effect display unit 1900 (liquid crystal display) in the first resolution conversion unit 3420gaa of the signal separation unit 3420ga in the game board side signal separation control circuit 3420g of the liquid crystal output board 3420. A plurality of game board side effect display units 1900 provided in the second resolution conversion unit 3420gab of the signal separation unit 3420ga in the game board side signal separation control circuit 3420g of the liquid crystal output board 3420. Light guide plate information for selecting one of the light guide plates, and among the decorative boards of the game board 4, a plurality of game board side VDP control target decorative boards that are controlled by the sound source built-in VDP 4160 a are directly controlled. Multiple LEDs (decorative LEDs) provided for each Against is separated into, and illuminations information. Based on the clock signal SCLK1 as serial data SDAT1 from the first serial controller 3420gd1, the separated light guide plate information is converted into the first light guide plate PWM control circuit 4950 and the second light guide plate control of the first light guide plate control circuit 3420k1. The second light guide plate PWM control circuit 4960 of the circuit 3420k2 and the third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3 are output to the clock signal SCLK2 as serial data SDAT2 from the second serial controller 3420gd2. Based on the fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4, the fifth light guide plate PWM control circuit 4965 of the fifth light guide plate control circuit 3420k5, and the sixth light guide plate control circuit 3420k6. Sixth light guide plate PWM control circuit And outputs it to 975.

  As a result, the fifth light guide plate PWM control circuit 4965 of the fifth light guide plate control circuit 3420k5 sets the duty ratio of the fifth light guide plate PWM signal so that the luminance of the LED becomes the maximum luminance (100%). To the LED driver IC 4835 of the fifth light guide plate control circuit 3420k5, and the first light guide plate PWM control circuit 4950 and the second light guide plate control circuit 3420k2 of the first light guide plate control circuit 3420k1. Second light guide plate PWM control circuit 4960, third light guide plate PWM control circuit 4970 of third light guide plate control circuit 3420k3, fourth light guide plate PWM control circuit 4955 of fourth light guide plate control circuit 3420k4, and sixth. The sixth light guide plate PWM control circuit 4975 of the light guide plate control circuit 3420k6 of the first light guide plate PWM signal to the fourth light guide plate PW. The LED driver IC 4810 of the first light guide plate control circuit 3420k2, the LED driver IC 4830 of the second light guide plate control circuit 3420k2, the third duty ratio of the signal and the PWM signal for the sixth light guide plate are set to zero%, respectively. Output control is performed to the LED driver IC 4850 of the light guide plate control circuit 3420k3, the LED driver IC 4815 of the fourth light guide plate control circuit 3420k4, and the LED driver IC 4855 of the sixth light guide plate control circuit 3420k6.

[12-2-3f. Light guide plate information when selecting the sixth light guide plate]
For example, when the sixth light guide plate 5000k is selected (switched to the sixth light guide plate 5000k), the LEDs 5000k6 on the light guide plate upper decorative substrate 5000k1 and the light guide plate lower decorative substrate 5000k2 in the sixth light guide plate 5000k are turned on. Therefore, as the light guide plate information, the ID of the sixth light guide plate PWM control circuit 4975 of the sixth light guide plate control circuit 3420k6 provided in the liquid crystal output board 3420 is set in the light guide plate designation information, and the luminance information As described above, data for setting the luminance of the LED to the maximum luminance (100%) is set. At this time, the first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000g, the fourth light guide plate 5000h, and the fifth light guide plate 5000i are provided on the upper end surface and the lower end surface. In order to extinguish each LED 5000d6, 5000f6, 5000g6, 5000h6, 5000i6 on the light board decoration board 5000d1, 5000f1, 5000g1, 5000h1, 5000i1 and the light guide board decoration board 5000d2, 5000f2, 5000g2, 5000h2, 5000i2, as light guide plate information In the light guide plate designation information, the first light guide plate PWM control circuit 4950 of the first light guide plate control circuit 3420k1 and the second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2 included in the liquid crystal output substrate 3420. The third light guide plate system Third light guide plate PWM control circuit 4970 of circuit 3420k3, fourth light guide plate PWM control circuit 4955 of fourth light guide plate control circuit 3420k4, and fifth light guide plate PWM control circuit of fifth light guide plate control circuit 3420k5 Each ID of 4965 is set, and data for turning off the LED is set as luminance information.

  The sound source built-in VDP 4160a is a predetermined game board side generation rule in which the light guide plate information and the electrical decoration information are added to the game board side drawing data of the screen drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). The drawing data generated in the game board display area VRGN1 is output from the channel CH1.

  The drawing data output from the channel CH1 is, as described above, the game board side effect display unit 1900 (liquid crystal display) in the first resolution conversion unit 3420gaa of the signal separation unit 3420ga in the game board side signal separation control circuit 3420g of the liquid crystal output board 3420. A plurality of game board side effect display units 1900 provided in the second resolution conversion unit 3420gab of the signal separation unit 3420ga in the game board side signal separation control circuit 3420g of the liquid crystal output board 3420. Light guide plate information for selecting one of the light guide plates, and among the decorative boards of the game board 4, a plurality of game board side VDP control target decorative boards that are controlled by the sound source built-in VDP 4160 a are directly controlled. Multiple LEDs (decorative LEDs) provided for each Against is separated into, and illuminations information. Based on the clock signal SCLK1 as serial data SDAT1 from the first serial controller 3420gd1, the separated light guide plate information is converted into the first light guide plate PWM control circuit 4950 and the second light guide plate control of the first light guide plate control circuit 3420k1. The second light guide plate PWM control circuit 4960 of the circuit 3420k2 and the third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3 are output to the clock signal SCLK2 as serial data SDAT2 from the second serial controller 3420gd2. Based on the fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4, the fifth light guide plate PWM control circuit 4965 of the fifth light guide plate control circuit 3420k5, and the sixth light guide plate control circuit 3420k6. Sixth light guide plate PWM control circuit And outputs it to 975.

  Accordingly, the sixth light guide plate PWM control circuit 4975 of the sixth light guide plate control circuit 3420k6 sets the duty ratio of the sixth light guide plate PWM signal so that the luminance of the LED becomes the maximum luminance (100%). To the LED driver IC 4855 of the sixth light guide plate control circuit 3420k6 and the first light guide plate PWM control circuit 4950 and the second light guide plate control circuit 3420k2 of the first light guide plate control circuit 3420k1. Second light guide plate PWM control circuit 4960, third light guide plate PWM control circuit 4970 of third light guide plate control circuit 3420k3, fourth light guide plate PWM control circuit 4955 of fourth light guide plate control circuit 3420k4, and fifth. The fifth light guide plate PWM control circuit 4965 of the light guide plate control circuit 3420k5 of the first light guide plate PWM signal to the fifth light guide plate PW. The duty ratio of the signal is set to zero%, the LED driver IC 4810 of the first light guide plate control circuit 3420k2, the LED driver IC 4830 of the second light guide plate control circuit 3420k2, and the LED driver IC 4850 of the third light guide plate control circuit 3420k3. The LED driver IC 4815 of the fourth light guide plate control circuit 3420k4 and the LED driver IC 4835 of the fifth light guide plate control circuit 3420k5 are controlled to output.

[12-2-4. Light guide plate for power recovery]
Here, when the power is turned on, when a power failure occurs and then the power recovers, and when the power recovers such as when an instantaneous power failure occurs and the power recovers (instantaneous power failure) The point that a specific light guide plate is selected as the light guide plate for power recovery among the plurality of light guide plates provided in the display unit 1900 will be briefly described.

  The peripheral control board 4140 emits surface light from the first light guide plate 5000d so that the first light guide plate 5000d is selected as the power recovery light guide plate, while the other light guide plates (second light guide plates 5000f, The control for turning off all of the third light guide plate 5000g, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k) is performed on the sound source built-in VDP 4160a. That is, as described above, when the first light guide plate 5000d is selected (switched to the first light guide plate 5000d), the light guide plate upper decorative substrate 5000d1 and the light guide plate lower decorative substrate 5000d2 in the first light guide plate 5000d. In order to light each of the LEDs 5000d6, as the light guide plate information, the ID of the first light guide plate PWM control circuit 4950 of the first light guide plate control circuit 3420k1 provided in the liquid crystal output substrate 3420 is set as the light guide plate designation information. In addition, data for setting the luminance of the LED to the maximum luminance (100%) is set as the luminance information. At this time, the second light guide plate 5000f, the third light guide plate 5000g, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k are provided on the upper end surface and the lower end surface, respectively. In order to extinguish the LEDs 5000f6, 5000g6, 5000h6, 5000i6, 5000k6 on the light plate decoration board 5000f1, 5000g1, 5000h1, 5000i1, 5000k1 and the light guide plate lower decoration board 5000f2, 5000g2, 5000h2, 5000i2, 5000k2, as light guide plate information The second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2 and the third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3 included in the liquid crystal output substrate 3420 are included in the light guide plate designation information. , 4th light guide plate system Fourth light guide plate PWM control circuit 4955 of circuit 3420k4, fifth light guide plate PWM control circuit 4965 of fifth light guide plate control circuit 3420k5, and sixth light guide plate PWM control circuit of sixth light guide plate control circuit 3420k6 Each ID of 4975 is set, and data for turning off the LED is set as luminance information.

  The sound source built-in VDP 4160a is a predetermined game board side generation rule in which the light guide plate information and the electrical decoration information are added to the game board side drawing data of the screen drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). The drawing data generated in the game board display area VRGN1 is output from the channel CH1.

  The drawing data output from the channel CH1 is, as described above, the game board side effect display unit 1900 (liquid crystal display) in the first resolution conversion unit 3420gaa of the signal separation unit 3420ga in the game board side signal separation control circuit 3420g of the liquid crystal output board 3420. A plurality of game board side effect display units 1900 provided in the second resolution conversion unit 3420gab of the signal separation unit 3420ga in the game board side signal separation control circuit 3420g of the liquid crystal output board 3420. Light guide plate information for selecting one of the light guide plates, and among the decorative boards of the game board 4, a plurality of game board side VDP control target decorative boards that are controlled by the sound source built-in VDP 4160 a are directly controlled. Multiple LEDs (decorative LEDs) provided for each Against is separated into, and illuminations information. Based on the clock signal SCLK1 as serial data SDAT1 from the first serial controller 3420gd1, the separated light guide plate information is converted into the first light guide plate PWM control circuit 4950 and the second light guide plate control of the first light guide plate control circuit 3420k1. The second light guide plate PWM control circuit 4960 of the circuit 3420k2 and the third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3 are output to the clock signal SCLK2 as serial data SDAT2 from the second serial controller 3420gd2. Based on the fourth light guide plate PWM control circuit 4955 of the fourth light guide plate control circuit 3420k4, the fifth light guide plate PWM control circuit 4965 of the fifth light guide plate control circuit 3420k5, and the sixth light guide plate control circuit 3420k6. Sixth light guide plate PWM control circuit And outputs it to 975.

  As a result, the first light guide plate PWM control circuit 4950 of the first light guide plate control circuit 3420k1 sets the duty ratio of the first light guide plate PWM signal so that the luminance of the LED becomes the maximum luminance (100%). Then, control to output to the LED driver IC 4810 of the first light guide plate control circuit 3420k1 is performed. The first light guide plate 5000d and other light guide plates (second light guide plate 5000f, third light guide plate 5000g, fourth light guide plate 5000h, fifth light guide plate 5000i, and sixth light guide plate 5000k). In contrast, since the entire surface is formed as the light emitting region 5000d4, the non-light emitting region is not formed, and the region behind the non-light emitting region of the first light guide plate 5000d cannot be visually recognized.

  The second light guide plate PWM control circuit 4960 of the second light guide plate control circuit 3420k2, the third light guide plate PWM control circuit 4970 of the third light guide plate control circuit 3420k3, and the fourth light guide plate control circuit 3420k4. The fourth light guide plate PWM control circuit 4955, the fifth light guide plate PWM control circuit 4965 of the fifth light guide plate control circuit 3420k5, and the sixth light guide plate PWM control circuit 4975 of the sixth light guide plate control circuit 3420k6 The LED driver IC 4830 of the second light guide plate control circuit 3420k2 and the LED driver of the third light guide plate control circuit 3420k3 by setting the duty ratio of the PWM signal for the light guide plate to the PWM signal for the sixth light guide plate to zero%, respectively. IC 4850, LED driver IC 4815 of fourth light guide plate control circuit 3420k4, fifth light guide plate control circuit 3420k5 LED driver IC4835, performs control to output to the LED driver IC4855 sixth light guide plate control circuit 3420K6.

  The light emitting area 5000f4 of the second light guide plate 5000f, the light emitting area 5000g4 of the third light guide plate 5000g, the light emitting area 5000h4 of the fourth light guide plate 5000h, the light emitting area 5000i4 of the fifth light guide plate 5000i, and the sixth light guide plate Since all of the 5000k light emitting areas 5000k4 are extinguished, it is possible to visually recognize the rear in the entire light emitting area 5000f4 and non-light emitting area 5000f3 of the second light guide plate 5000f, and the light emitting area of the third light guide plate 5000g. The rear can be made visible in the entire area of 5000g4 and the non-light emitting area 5000g3, and the rear can be made visible in the entire area of the light emitting area 5000h4 and the non-light emitting area 5000h3 of the fourth light guide plate 5000h. The light emitting area 5000i4 and the non-light emitting area 5 of the fifth light guide plate 5000i In all areas of the 00i3 can be visible to the rear can be visible to the rear in the entire region between the light-emitting region 5000k4 a non-light-emitting region 5000k3 sixth light guide plate 5000k.

  At this time, the game board side drawing data separated by the first resolution conversion unit 3420gaa of the signal separation unit 3420ga is supplied to the game board side effect display unit 1900 (liquid crystal panel) via the game board side liquid crystal drive circuit 3420h on the liquid crystal output board 3420. 5000e). As a result, in the liquid crystal panel 5000e, the area corresponding to the light emitting area 5000d4 of the first light guide plate 5000d described above has a black background color as an effect image at the time of power recovery. The white character “” is displayed.

  In addition, in this embodiment, when selecting one light guide plate among the plurality of light guide plates provided in the game board side effect display unit 1900, the light guide plate upper decorative substrate and the light guide plate lower decorative substrate in one light guide plate. In order to turn on each LED, data for setting the LED brightness to the maximum brightness (100%) is set. Data may be dimmed to one high luminance within a predetermined high luminance side range (for example, 100% to 75%).

  In the present embodiment, when one light guide plate is selected from among the plurality of light guide plates provided in the game board side effect display unit 1900, the light guide plates in the other light guide plates are turned off so that the other light guide plates not selected are turned off. The LEDs on the optical board upper decorative board and the light guide board lower decorative board are respectively turned off, but the luminance of the LEDs is set in a predetermined low luminance side range from the minimum luminance (1%) to the maximum luminance (100%) (for example, 1% to 5%), the data may be dimmed to one low luminance. In this way, even if one light guide plate is selected from among the plurality of light guide plates provided in the game board side effect display unit 1900, each of the light guide plate upper decorative substrate and the light guide plate lower decorative substrate in the selected one light guide plate is selected. Although the magnitude of the brightness of the LED differs from the brightness of each LED on the light guide plate upper decorative substrate and the light guide plate lower decorative substrate in other light guide plates that are not selected, a plurality of guides provided in the game board side effect display unit 1900 are provided. Since all the LEDs on the light guide plate upper decorative substrate and the light guide plate lower decorative substrate in the optical plate can be turned on, the first light guide plate 5000d, the second light guide plate 5000f, and the third light guide plate 5000g. The light guide plate is exclusively selected from the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k. Even when the LEDs on the light guide plate upper decorative substrate and the light guide plate lower decorative substrate are lit longer, the first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000g, and the fourth light guide plate The lifetimes of the LEDs on the light guide plate upper decorative substrate and the light guide plate lower decorative substrate in the light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k can be matched.

  Further, the first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000g, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k are not selected. The light plate is not selected because the brightness of the LED is dimmed to the minimum brightness (1%) or one of the predetermined low brightness side ranges in order to light up in the standby state. The light emitted from the light guide plate is reflected in a state that is difficult for the user to visually recognize, that is, the light guide plate that is not selected is turned off and can be visually recognized by the user as a transparent state in which the rear can be visually recognized.

[13. Lamp drive circuit]
Next, the circuit of the lamp driving substrate 4170 shown in FIG. 17 will be described with reference to FIG. FIG. 38 is a block diagram of an ornamental LED control circuit for game board side peripheral control MPU control target. As shown in FIG. 38, the lamp driving board 4170 is a game board side peripheral control MPU control target decoration LED control circuit 4170k, and the game board side peripheral control MPU control target first decoration LED control circuit 4170k1 to the game board side. Peripheral control MPU control target eighth decorative LED control circuit 4170k8 (8 circuits in total) is provided.

  As described above, the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 receives the game board side light emission data SL-DAT from the game board side decorative board serial I / O port. It is output to the lamp driving substrate 4170 in synchronization with CLK.

  The game board side light emission data SL-DAT and the game board side light emission clock signal SL-CLK from the serial I / O port for the game board side decorative board of the peripheral control MPU 4150a are the game board side peripheral control MPU control target decoration LED control. The game board side peripheral control MPU control target first decoration LED control circuit 4170k1 to the game board side peripheral control MPU control target eighth decoration LED control circuit 4170k8 constituting the circuit 4170k, respectively. The game board side peripheral control MPU control target first decoration LED control circuit 4170k1 to the game board side peripheral control MPU control target eighth decoration LED control circuit 4170k8 is electrically connected as one serial connection (one serial system). The circuit configuration is connected to

  In this embodiment, the game board side peripheral control MPU control target first decoration LED control circuit 4170k1 to the game board side peripheral control MPU control target eighth decoration LED control circuit 4170k8 is derived from the same decoration LED driver IC. Each of the decorative boards of the game board 4 is configured by a plurality of LEDs (on each of the plurality of game board side peripheral control MPU control target decoration boards that are controlled by the peripheral control MPU 4150a). The light emitted from the decorative LED) can be dimmed. Here, the game board side peripheral control MPU control target first decoration LED control circuit 4170k1 will be briefly described below, and the game board side peripheral control MPU control target second decoration LED control circuit 4170k1 to game board side peripheral Description of the control MPU control target eighth decorative LED control circuit 4170k8 will be omitted.

  First, the game board side light emission data SL-DAT will be described. The “game board side light emission data” is information for designating the light emission mode, and is composed of illumination LED designation information and gradation information. The electrical LED designation information is the game board side peripheral control MPU control target first decoration LED control circuit 4170k1 to the game board side peripheral control MPU control target eighth decoration LED control circuit 4170k8, whichever game board side This is information indicating whether the peripheral control MPU control target decoration LED control circuit is designated, and an address (ID to be described later) for identifying an individual of the game board side peripheral control MPU control target decoration LED control circuit. Is set. The gradation information is information indicating which gradation degree is designated from the gradation degree 0 (zero) to the gradation degree 127.

  As shown in FIG. 38, the decoration LED driver IC constituting the first decoration LED control circuit 4170k1 to be controlled by the game board side peripheral control MPU has 24 output channels (ch), and each channel has a maximum of 80 mA. This is a 24ch constant current LED driver IC capable of outputting (milliampere) current. The LED driver IC for decoration mainly includes an address setting unit 4170k1a, a logic processing unit 4170k1b, a clock generation unit 4170k1c, a data buffer unit 4170k1d, a PWM unit 4170k1e, and a constant current drive unit 4170k1f.

  The address setting unit 4170k1a can set 64 addresses as IDs (IDs for identifying individuals) by voltages applied to six device address selection terminals (not shown). The voltage applied to the six device address selection terminals is one of a voltage raised to the control voltage (+5 V) side and a voltage lowered to the ground (GND) side.

  In this way, IDs that can identify the individual decoration LED driver ICs constituting the first decoration LED control circuit 4170k1 to be controlled by the gaming board side peripheral control MPU are applied to the six device address selection terminals. It is set in advance by the address setting unit 4170k1a depending on the hardware configuration of voltage, and is not set as appropriate by receiving data by software.

  The logic processing unit 4170k1b receives the game board side light emission data SL-DAT from the serial I / O port for the game board side decorative board of the peripheral control MPU 4150a based on the game board side light emission clock signal SL-CLK, and receives the data buffer unit 4170k1d. The data buffer unit 4170k1d includes its own ID in the illumination LED designation information in the game board side light emission data SL-DAT from the logic processing unit 4170k1b based on the address which is its own ID set by the address setting unit 4170k1a. When the game board side light emission data SL-DAT from the logic processing unit 4170k1b is determined to be for itself, the gradation level which is the gradation information in the game board side light emission data SL-DAT is taken in and taken in. While controlling the gradation level in each channel to be set in the PWM unit 4170k1e so that the gradation level is the gradation information, the illumination LED designation information in the game board side light emission data SL-DAT from the logic processing unit 4170k1b is controlled. Logic processing when your ID is not included It is determined that the game board side light emission data SL-DAT from 4170k1b is not for itself, and the gradation level which is the gradation information in the game board side light emission data SL-DAT is not taken in, and the current contents set in the PWM unit 4170k1e Control to maintain.

  The PWM unit 4170k1e can perform gradation control of the brightness (gradation degree) of the LED in each channel in 128 steps from gradation 0 (zero) to gradation degree 127 from turning off to lighting (maximum luminance). The gradation control is performed for one channel by one PWM gradation control unit. In other words, the PWM unit 4170k1e performs gradation control by the PWM gradation control unit 1 for the decoration LED in 1ch, and gradation control by the PWM gradation control unit 2 for the decoration LED in 2ch,. In addition, a total of 24 PWM gradation control units 1 to PWM gradation control unit 24, in which gradation control is performed by the PWM gradation control unit 24 on the decoration LEDs in 24ch, are configured. When the gradation levels are set, the PWM gradation control unit 1 to the PWM gradation control unit 24, based on the clock signal from the clock generation unit 4170k1c, cause a constant current to flow. The drive unit 4170k1f is controlled.

  The constant current drive unit 4170k1f is a full color LED that is a decoration LED by one constant current driver for one channel so as to have the gradation set in the PWM gradation control unit 1 to the PWM gradation control unit 24. A constant current is made to flow through the LED elements constituting the circuit element, and is composed of a total of 24 constant current drivers 1 to 24.

  The constant current driver 1 to the constant current driver 24 are electrically connected to one end of a resistor Rp1 for setting a maximum current to be supplied to the decoration LED in all channels 1ch to 24ch, and the other end of the resistor Rp1 is grounded. (GND) is grounded.

  The anode terminal of the red LED element, the anode terminal of the green LED element, and the anode terminal of the blue LED element constituting the full-color LED respectively corresponding to the constant current driver 1 to the constant current driver 24 are an electric power source for decoration ( Control power supply). The cathode terminals of the red LED elements constituting the full-color LEDs respectively corresponding to the constant current driver 1 to the constant current driver 8 are electrically connected to the LR1 terminal to the LR8 terminal, and are connected to the constant current driver 9 to the constant current driver 16, respectively. The cathode terminal of the green LED element constituting the corresponding full color LED is electrically connected to the LG1 terminal to LG8 terminal, and the blue LED element constituting the full color LED corresponding to the constant current driver 17 to constant current driver 24, respectively. The cathode terminal is electrically connected to the LB1 terminal to LB8 terminal.

  The constant current driver 1 to the constant current driver 8 apply constant currents LR1 individually set to the red LED elements constituting the full color LED, which is a decoration LED corresponding to each of the eight channels 1ch to 8ch. The constant current driver 9 to the constant current driver 16 are individually supplied to the green LED elements constituting the full-color LED corresponding to the eight channels from 9ch to 16ch, respectively. The constant current set to 1 is passed through the LG1 to LG8 terminals, respectively, and the constant current driver 17 to constant current driver 24 constitutes a full-color LED that is a decoration LED corresponding to each of the eight channels from 17ch to 24ch. Constant current set individually for each blue LED element Flow, respectively, via the B1 terminal ~LB8 terminal.

  It should be noted that the control voltage LVp is applied to the power supply terminal of the decoration LED driver IC that constitutes the first decoration LED control circuit 4170k1 to be controlled by the game board side peripheral control MPU, whereby the decoration LED driver IC is used as the internal power supply Vreg. The ground terminal is supplied to various internal circuits, and the ground terminal GND is grounded to the ground (GND), whereby the ground in the various internal circuits of the decorative LED driver IC is grounded to the ground (GND) of the lamp driving substrate 4170.

  In this way, the decoration LED driver ICs constituting the game board side peripheral control MPU control target first decoration LED control circuit 4170k1 to the game board side peripheral control MPU control target eighth decoration LED control circuit 4170k8, respectively, Since 24 elements, that is, 8 full-color LEDs, which are decorative LEDs, can be dimmed individually, such dimming lighting turns off, lights with one gradation, blinks with one gradation, etc. It can be performed. In addition, the decoration LED driver ICs constituting the game board side peripheral control MPU control target first decoration LED control circuit 4170k1 to the game board side peripheral control MPU control target eighth decoration LED control circuit 4170k8, respectively, are decoration LEDs 64 full-color LEDs (= 8 full-color LEDs × 8 decorative LED control circuits (decorative LED driver ICs)), that is, 192 (= red, green and blue three LED elements × 64) The full-color LED) LED element can be dimmed.

  Note that the gaming board side peripheral control MPU control target first decoration LED control circuit 4170k1 and the gaming board side peripheral control MPU control target second decoration LED control circuit 417021 are provided in the attacker unit 2100 shown in FIG. The attacker unit 2100 is illuminated and decorated by dimming a plurality of LEDs (decorative LEDs) provided on the gaming board side peripheral control MPU control target decoration board PM1. The game board side peripheral control MPU control target third decoration LED control circuit 4170k3 includes a plurality of LEDs (decoration) provided on the game board side peripheral control MPU control target decoration board PM2 provided in the side prize port member 2200 shown in FIG. The side prize port member 2200 is light-decorated by performing dimming lighting of the LED. The game board side peripheral control MPU control target fourth decoration LED control circuit 4170k4 to the game board side peripheral control MPU control target eighth decoration LED control circuit 4170k8 is a game board provided in the center accessory 2300 shown in FIG. The center accessory 2300 is light-decorated by performing dimming lighting of a plurality of LEDs (decorative LEDs) provided on the side peripheral control MPU control target decoration board PM3.

  Here, in the present embodiment, as described above, each decoration board of the game board 4 includes a plurality of game board side peripheral control MPU control target decoration boards that are controlled by the peripheral control MPU 4150a, and a sound source. There are a plurality of game board side VDP control target decoration boards that are controlled by the built-in VDP 4160a directly, and the plurality of decoration LEDs provided on the game board 4 are controlled to emit light by the peripheral control MPU 4150a. And those controlled to emit light by the built-in sound source VDP 4160a. This is because the plurality of LEDs (decorative LEDs) provided on each of the plurality of game board side peripheral control MPU control target decorative boards that are controlled by the peripheral control MPU 4150a are in the form of light emission. (E.g., the light emission mode fluctuates like a gentle wave, the light emission mode lasts for a predetermined time, or the light emission mode flashes fast enough to blink even if the light emission mode is fast ( A plurality of game board side VDP control target decorative boards that are controlled by the built-in sound source VDP 4160a. LED (decorative LED) is a dot display using LED (decorative LED) whose light emission mode changes rapidly according to the progress of production. As a light mode, a lightning flashing (flashing) as if expressing lightning, a fireworks display, an explosion, scrolling symbols, people and vehicles (These light emission modes correspond to the progress of the effects displayed in the display area of the game board side effect display unit 1900 provided in the game board 4 shown in FIG. 8.) It can change quickly and can be linked to the production). In other words, in the present embodiment, in the light emission control of the plurality of decoration LEDs provided on the game board 4, the peripheral control MPU 4150 a takes charge of processing that is difficult to be processed, whereas the peripheral control MPU 4150 a is responsible for processing. A mechanism is adopted in which the sound source source built-in VDP 4160a takes charge. As described above, the game board side peripheral control MPU control target first decoration LED control circuit 4170k1 to the game board side peripheral control MPU control target eighth decoration LED control circuit 4170k8 of the lamp driving board 4170 is the game board side. When the light emission data SL-DAT is not for itself, the current light emission mode is maintained by maintaining the current contents. In other words, when the light emission mode changes slowly along with the progress of the production, the time during which the light emission mode is the same becomes longer. Therefore, when the light emission mode changes, the peripheral control MPU 4150a By outputting the side light emission data SL-DAT, it is difficult to cause a processing load on the peripheral control MPU 4150a.

  As described above, in the present embodiment, for the plurality of LEDs (decorative LEDs) provided on each of the plurality of game board side VDP control target decorative boards that are controlled by the built-in sound source VDP 4160a, There is an effect that the change in the light emission mode is faster than the plurality of LEDs (decorative LEDs) provided on each of the plurality of game board side peripheral control MPU control target decorative boards that are controlled by the peripheral control MPU 4150a. Assigned. It should be noted that the control target directly controlled by the peripheral control MPU 4150a is also a plurality of LEDs (decorative LEDs) provided on each of the plurality of game board side VDP control target decorative boards that are controlled by the internal sound source VDP 4160a. In the same manner as the light emission mode of a plurality of LEDs (decorative LEDs) provided on each of the plurality of gaming board side peripheral control MPU control target decorative boards, the light emission mode changes slowly along the progress of the production Therefore, in this case, peripheral control is performed for a plurality of LEDs (decorative LEDs) provided on each of the plurality of game board side VDP control target decorative boards that are controlled by the built-in sound source VDP 4160a. Set on each of the plurality of game board side peripheral control MPU control target decorative boards that are controlled by the MPU 4150a. A plurality of compared to LED (decorative LED), a change in light emission mode is that the effect is assigned to the same.

  In the present embodiment, a decoration whose light emission mode is controlled by the first decoration LED control circuit 4170k1 to the game board side peripheral control MPU control target eighth decoration LED control circuit 4170k8. All the LEDs used are red LED elements, green LED elements, and blue LED elements that constitute a full-color LED. However, a single LED that is different from a full-color LED (the same color LED may be used or a plurality of different LEDs may be used). LED for one game board side peripheral control MPU control object decoration LED control circuit is a full color LED and another game board side peripheral control MPU control object decoration LED control circuit Can be a single LED (the same color LED or different color LEDs). It may be a combination plurality, such one and game board-side peripheral control MPU control object decorative LED control circuit and the other of the game board side peripheral control MPU control object decorative LED control circuit.

[14. Circuit of frame decoration drive amplifier board]
Next, the circuit of the frame decoration drive amplifier board 194 shown in FIG. 19 will be described with reference to FIGS. First, the configuration of the frame decoration drive amplifier board will be described, followed by the configuration of the frame-side VDP control target decoration LED control circuit and the configuration of the frame-side peripheral control MPU control target decoration LED control circuit. 39 is a block diagram of the frame decoration drive amplifier board, FIG. 40 is a diagram showing the correspondence between various serial controllers and output destinations in the frame side signal separation control circuit, and FIG. 41 is for frame side VDP control object decoration. FIG. 42 is a diagram illustrating a correspondence relationship between an LED control circuit and a plurality of LEDs (decorative LEDs) provided on a frame-side VDP control target decoration board, and FIG. 42 is a block diagram of the frame-side VDP control target decoration LED control circuit. FIG. 43 is a block diagram of the frame side peripheral control MPU control target decoration LED control circuit.

[14-1. Configuration of frame decoration drive amplifier board]
As shown in FIG. 39, the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 receives the frame side light emission data STL-DAT from the frame side decorative board serial I / O port. In synchronization with the signal, the frame is output to the frame decoration drive amplifier board 194 via the frame peripheral relay terminal plate 868 and the peripheral door relay terminal plate 882. The frame side light emission data STL-DAT and the frame side light emission clock signal STL-CLK from the frame side decorative board serial I / O port of the peripheral control MPU 4150a constitute a frame side peripheral control MPU control target decorative LED control circuit 194k. The frame-side peripheral control MPU control target first decoration LED control circuit 194k1 is input to the frame-side peripheral control MPU control target seventh decoration LED control circuit 194k7. The frame-side peripheral control MPU control target first decorative LED control circuit 194k1 to the frame-side peripheral control MPU control target seventh decorative LED control circuit 194k7 are electrically connected as one serial connection (one serial system). Circuit configuration.

  The VDP 4160a with built-in sound source of the liquid crystal and sound control unit 4160 on the peripheral control board 4140 has the above-described predetermined screen (in this embodiment, red (R): 50%, green (G): 50%, blue (B): The drawing data is generated in the door frame side display area VRGN2 provided on the VRAM as if the illumination information is attached to the door frame side drawing data of the gray screen having 50%) according to a predetermined door frame side generation rule. And output from channel CH2. As described above, the drawing data output from this channel CH2 includes three video signals, which are parallel signals, that is, a red video signal, a green video signal, and a blue video signal, a horizontal synchronization signal, a vertical synchronization signal, and a clock. Three synchronous signals called signals are serialized into a differential serial signal (serial data) called “V-by-One (registered trademark)” of THINE ELECTRONICS CO., LTD., Which is a kind of clockless transmission system. When these various signals are output (transmitted) and transmitted from the peripheral control board 4140 to the frame peripheral relay terminal plate 868, the peripheral door relay terminal plate 882, and the frame decoration drive amplifier 194 only with the pair cable, the frame decoration drive is performed. In the receiver IC 194f of the amplifier board 194, the parallel signal (that is, the VDP with built-in sound source) Drawing data output from the channel CH2 of 160a, three video signals of a red video signal, a green video signal, and a blue video signal, and three synchronization signals of a horizontal synchronization signal, a vertical synchronization signal, and a clock signal; ) Is restored.

  The receiver IC 194f restores the drawing data output from the channel CH2 and outputs it to the frame side signal separation control circuit 194g. This frame side signal separation control circuit 194g is the same circuit as the game board side signal separation control circuit 3420g of the liquid crystal output board 3420 shown in FIG.

  As shown in FIG. 39, the frame side signal separation control circuit 194g includes a signal separation unit 194ga, a buffer memory 194gb, a distribution output control unit 194gc, and a first serial controller 194gd1 to an eleventh serial controller 194gd11. When the parallel signal restored by the receiver IC 194f is input, it is input to the signal separation unit 194ga.

  The signal separation unit 194ga includes a first resolution conversion unit 194gaa and a second resolution conversion unit 194gab. The first resolution conversion unit 194gaa generates a predetermined screen (in this embodiment, red (R): 50%, green (G): 50%, blue (B): 50) from the drawing data restored to the parallel signal. Gray image having%) and three synchronization signals such as a red video signal, a green video signal, and a blue video signal, and a horizontal synchronization signal, a vertical synchronization signal, and a clock signal. The door frame side drawing data is separated from the drawing data restored to the parallel signal by cutting out the signal, while the second resolution conversion unit 194gab is configured to display each decoration of the door frame 5 from the drawing data restored to the parallel signal. Among the boards, a plurality of LEDs (decorative LEDs) provided on each of the plurality of frame side VDP control target decorative boards that are controlled by the sound source built-in VDP 4160a. A plurality of frame side VDP control target decorative boards that are controlled by the sound source built-in VDP 4160a among the decorative boards of the door frame 5 from the drawing data restored to the parallel signal by cutting out the electrical decoration information for The illumination information for a plurality of LEDs (decorative LEDs) provided in each is separated and output to the buffer memory 194gb to perform a write operation.

  In other words, the first resolution conversion unit 194gaa is generated from the drawing data restored to the parallel signal in the door frame side drawing data area VRGN2a of the door frame side display area VRGN2 provided in the built-in VRAM of the sound source built-in VDP 4160a. By cutting out the door frame side drawing data, the door frame side drawing data can be separated from the drawing data restored to a parallel signal (no output to other electronic components or other boards). The second resolution conversion unit 194gab generates drawing data in the door frame side associated information area VRGN2b of the door frame side display area VRGN2 provided on the built-in VRAM of the sound source built-in VDP 4160a from the drawing data restored to the parallel signal. The door frame 5 is drawn from the drawing data restored to the parallel signal by cutting out the decorated electrical information. Out of each decoration board, the decoration information for a plurality of LEDs (decoration LEDs) provided on each of the plurality of frame side VDP control target decoration boards which are controlled by the built-in sound source VDP 4160a is separated and buffered. A write operation can be performed by outputting to the memory 194gb.

  In the present embodiment, the door frame side drawing data generated in the door frame side drawing data region VRGN2a of the door frame side display region VRGN2 provided in the built-in VRAM of the sound source built-in VDP 4160a is cut out by the first resolution conversion unit 194gaa. However, no output is made to other electronic components or other substrates.

  In the present embodiment, the illumination information generated as drawing data in the door frame side accompanying information area VRGN2b of the door frame side display area VRGN2 provided on the built-in VRAM of the sound source built-in VDP 4160a is information written in the buffer memory 194gb. Accordingly, the second resolution conversion unit 194gab outputs the cut-out illumination information as it is to the buffer memory 194gb without performing the enlargement or reduction process, and performs the writing operation.

  The buffer memory 194gb is configured as a double buffer memory including a first buffer memory 194gb1 and a second buffer memory 194gb2, and one of the first buffer memory 194gb1 and the second buffer memory 194gb2 is written. When the operation is in progress, the contents already written in the other buffer memory are read out from the distribution output control unit 194gc. The distribution output control unit 194gc distributes the illumination information read from the buffer memory to the first serial controller 194gd1 to the 11th serial controller 194gd11 according to a predetermined door frame side generation rule.

  The first serial controller 194gd1 to the eleventh serial controller 194gd11 are the frame-side VDP control target first decorative LED control circuit 194i1 to the frame-side VDP control target 143 of the frame-side VDP control target decorative LED control circuit 194i. The illumination information is output to the decoration LED control circuit 194i143.

  More specifically, as shown in FIG. 40, the first serial controller 194gd1 uses the decoration information as serial data SDAT1 ′ based on the clock signal SCLK1 ′, which will be described later, for the frame-side VDP control target first decoration. The LED control circuit 194i1 outputs the frame-side VDP control target thirteenth decorative LED control circuit 194i13. Circuit configuration in which the frame-side VDP control target first decoration LED control circuit 194i1 to the frame-side VDP control target thirteenth decoration LED control circuit 194i13 are electrically connected as one serial connection (one serial system). It has become.

  As shown in FIG. 40, the second serial controller 194gd2 uses the frame side VDP control target fourteenth decoration LED control circuit 194i14 to the frame, which will be described later, based on the clock signal SCLK2 ′ with the decoration information as serial data SDAT2 ′. To the side VDP control target twenty-sixth decorative LED control circuit 194i26. The circuit configuration in which the frame-side VDP control target 14th decorative LED control circuit 194i14 to the frame-side VDP control target 26th decorative LED control circuit 194i26 are electrically connected as one serial connection (one serial system). It has become.

  As shown in FIG. 40, the third serial controller 194gd3 uses the frame side VDP control target 27th decoration LED control circuit 194i27 to the frame based on the clock signal SCLK3 ′ with the decoration information as serial data SDAT3 ′. To the side VDP control target 39th decorative LED control circuit 194i39. The circuit configuration in which the frame side VDP control target 27th decoration LED control circuit 194i27 to the frame side VDP control target 39th decoration LED control circuit 194i39 are electrically connected as one serial connection (one serial system). It has become.

  As shown in FIG. 40, the fourth serial controller 194gd4 uses the frame side VDP control target 40th decoration LED control circuit 194i40-frame, which will be described later, based on the clock signal SCLK4 ′ with the decoration information as serial data SDAT4 ′. To the side VDP control target 52nd decorative LED control circuit 194i52. Circuit configuration in which the frame-side VDP control target 40th decorative LED control circuit 194i40 to the frame-side VDP control target 52nd decorative LED control circuit 194i52 are electrically connected as one serial connection (one serial system) It has become.

  As shown in FIG. 40, the fifth serial controller 194gd5 uses the frame-side VDP control target 53th decoration LED control circuit 194i53 to the frame, which will be described later, based on the clock signal SCLK5 ′ with the decoration information as serial data SDAT5 ′. To the side VDP control target 65th decorative LED control circuit 194i65. The circuit configuration in which the frame-side VDP control target 53rd decorative LED control circuit 194i53 to the frame-side VDP control target 65th decorative LED control circuit 194i65 are electrically connected as one serial connection (one serial system). It has become.

  As shown in FIG. 40, the sixth serial controller 194gd6 converts the decoration information into serial data SDAT6 ′ and based on the clock signal SCLK6 ′, which will be described later, the frame-side VDP control target 66th decoration LED control circuit 194i66 to the frame. To the side VDP control target 78th decorative LED control circuit 194i78. The circuit configuration in which the frame side VDP control target 66th decorative LED control circuit 194i66 to the frame side VDP control target 78th decorative LED control circuit 194i78 are electrically connected as one serial connection (one serial system). It has become.

  As shown in FIG. 40, the seventh serial controller 194gd7 uses the frame-side VDP control target 79th decoration LED control circuit 194i79-frame, which will be described later, based on the clock signal SCLK7 ′ with the decoration information as serial data SDAT7 ′. To the side VDP control target 91st decorative LED control circuit 194i91. The circuit configuration in which the frame side VDP control target 79th decorative LED control circuit 194i79 to the frame side VDP control target 91st decorative LED control circuit 194i91 are electrically connected as one serial connection (one serial system). It has become.

  As shown in FIG. 40, the eighth serial controller 194gd8 uses the frame side VDP control target 92th decoration LED control circuit 194i92 to the frame, based on the clock signal SCLK8 ′ with the decoration information as serial data SDAT8 ′. To the side VDP control target 104th decorative LED control circuit 194i104. The circuit configuration in which the frame side VDP control target 92nd decoration LED control circuit 194i92 to the frame side VDP control target 104th decoration LED control circuit 194i104 are electrically connected as one serial connection (one serial system). It has become.

  As shown in FIG. 40, the ninth serial controller 194gd9 uses the frame side VDP control target 105th decoration LED control circuit 194i105-frame, which will be described later, based on the clock signal SCLK9 ′ with the decoration information as serial data SDAT9 ′. Output to the decorative LED control circuit 194i117 of the side VDP control target 117. The frame-side VDP control target 105th decorative LED control circuit 194i105 to the frame-side VDP control target 117th decorative LED control circuit 194i117 are electrically connected as one serial connection (one serial system). It has become.

  As shown in FIG. 40, the tenth serial controller 194gd10 uses the frame side VDP control target 118th decorative LED control circuit 194i118 to the frame based on the clock signal SCLK10 ′ with the decoration information as serial data SDAT10 ′. To the side VDP control target 130th decorative LED control circuit 194i130. The circuit configuration in which the frame-side VDP control target 118th decorative LED control circuit 194i118 to the frame-side VDP control target 130th decorative LED control circuit 194i130 are electrically connected as one serial connection (one serial system). It has become.

  As shown in FIG. 40, the eleventh serial controller 194gd11 uses the frame-side VDP control target 131st decoration LED control circuit 194i131 to the frame, which will be described later, based on the clock signal SCLK11 ′ with the decoration information as serial data SDAT11 ′. Output to the decorative LED control circuit 194i143 of the side VDP control target 143. The circuit configuration in which the frame-side VDP control target 131st decoration LED control circuit 194i131 to the frame-side VDP control target 143th decoration LED control circuit 194i143 are electrically connected as one serial connection (one serial system). It has become.

  The frame-side VDP control target first decorative LED control circuit 194i1 to the frame-side VDP control target 143 decorative LED control circuit 194i143 is a control target directly controlled by the sound source built-in VDP 4160a among the decorative boards of the door frame 5. This is a circuit that can adjust the luminance (gradation) of a plurality of LEDs (decorative LEDs) provided on each of the plurality of frame-side VDP control target decorative boards.

  Thus, the drawing data output from the channel CH2 of the liquid crystal and sound source built-in VDP 4160a of the sound control unit 4160 in the peripheral control board 4140 is the above-described predetermined screen (in this embodiment, red (R): 50%, (Gray screen with green (G): 50%, blue (B): 50%)) is provided on the VRAM as the door frame side drawing data attached with electrical decoration information according to a predetermined door frame side generation rule. The “predetermined door frame side generation rule” is generated in the door frame side display area VRGN2. The first resolution conversion unit 194gaa of the signal separation unit 194ga is a built-in VRAM of the sound source built-in VDP 4160a. The door frame side drawing data generated in the door frame side drawing data region VRGN2a of the door frame side display region VRGN2 provided in In addition, the second resolution conversion unit 194gab of the signal separation unit 194ga is configured to be capable of rendering data in the door frame side display information region VRGN2b of the door frame side display region VRGN2 provided on the built-in VRAM of the sound source built-in VDP 4160a. And the distribution output control unit 194gc reads out from the buffer memory 194gb in the frame-side signal separation control circuit 194g of the frame decoration drive amplifier board 194. The illumination information can be accurately distributed to the first serial controller 194gd1 to the eleventh serial controller 194gd11.

  More specifically, in the frame side signal separation control circuit 194g of the frame decoration driving amplifier board 194, the distribution output control unit 194gc reads the frame side VDP control target first decoration LED control circuit 194i1 read from the buffer memory 194gb. The frame-side VDP control target first decoration LED control circuit 194i1 can be accurately distributed to the first serial controller 194gd1 so that the illumination information for the frame-side VDP control target thirteenth decoration LED control circuit 194i13 can be accurately distributed. Lighting information, lighting information for the frame-side VDP control target second decoration LED control circuit 194i2, ..., and lighting information for the frame-side VDP control target thirteenth decoration LED control circuit 194i13 are predetermined. Screen (in this embodiment, red (R): 50%, green (G): 50%, blue B): generated gray screen) of the door frame side drawing data to the door frame side display area VRGN2 provided on the internal VRAM as denoted door frame side incidental information area VRGN2b with 50%.

  In addition, the distribution output control unit 194gc outputs second electric decoration information read from the buffer memory 194gb to the frame-side VDP control target fourteenth decoration LED control circuit 194i14 to the frame-side VDP control target twenty-sixth decoration LED control circuit 194i26. Lighting information for the frame-side VDP control target fourteenth decoration LED control circuit 194i14 and lighting for the frame-side VDP control target fifteenth decoration LED control circuit 194i15 so that it can be accurately distributed to the serial controller 194gd2. Information,..., And a screen on which electrical decoration information for the frame-side VDP control target 26th decorative LED control circuit 194i26 is predetermined (in this embodiment, red (R): 50%, green (G): 50) %, Blue (B): gray screen with 50%) It is generated to the door frame side incidental information area VRGN2b the door frame side display area VRGN2 provided on-chip VRAM.

  Also, the distribution output control unit 194gc corresponds to the lighting information read from the buffer memory 194gb for the frame side VDP control target 27th decoration LED control circuit 194i27 to the frame side VDP control target 39th decoration LED control circuit 194i39. In order to be able to accurately distribute to the third serial controller 194gd3, the electrical decoration information for the frame side VDP control target 27th decoration LED control circuit 194i27, the frame side VDP control target 28th decoration LED control circuit 194i28 Illumination information,..., And a screen in which the illumination information for the 39th decoration LED control circuit 194i39 for the frame side VDP control is predetermined (in this embodiment, red (R): 50%, green (G) : 50%, blue (B): gray screen with 50%) attached to door frame side drawing data It is generated to the door frame side incidental information area VRGN2b the door frame side display area VRGN2 provided on the internal VRAM with.

  Further, the distribution output control unit 194gc corresponds to the illumination information for the frame-side VDP control target 40th decoration LED control circuit 194i40 to the frame-side VDP control target 52nd decoration LED control circuit 194i52 read from the buffer memory 194gb. In order to be able to accurately distribute to the fourth serial controller 194gd4, the electric decoration information for the frame-side VDP control target 40th decoration LED control circuit 194i40, the frame-side VDP control target 41st decoration LED control circuit 194i41 Illumination information,..., And a screen in which the illumination information for the frame side VDP control target 52nd decoration LED control circuit 194i52 is predetermined (in this embodiment, red (R): 50%, green (G) : 50%, blue (B): gray screen with 50%) attached to door frame side drawing data It is generated to the door frame side incidental information area VRGN2b the door frame side display area VRGN2 provided on the internal VRAM with.

  Further, the distribution output control unit 194gc corresponds to the lighting information read from the buffer memory 194gb for the frame-side VDP control target 53rd decoration LED control circuit 194i53 to the frame-side VDP control target 65th decoration LED control circuit 194i65. In order to be able to accurately distribute to the fifth serial controller 194gd5, the electric decoration information for the frame-side VDP control target 53rd decoration LED control circuit 194i53, the frame-side VDP control target 54th decoration LED control circuit 194i54 Illumination information, ..., and a screen in which the illumination information for the frame-side VDP control target 65th decoration LED control circuit 194i65 is predetermined (in this embodiment, red (R): 50%, green (G) : 50%, blue (B): gray screen with 50%) attached to door frame side drawing data It is generated to the door frame side incidental information area VRGN2b the door frame side display area VRGN2 provided on the internal VRAM with.

  Further, the distribution output control unit 194gc corresponds to the lighting information read from the buffer memory 194gb for the frame-side VDP control target 66th decoration LED control circuit 194i66 to the frame-side VDP control target 78th decoration LED control circuit 194i78. In order to be able to accurately distribute to the sixth serial controller 194gd6, the electric decoration information for the frame side VDP control target 66th decoration LED control circuit 194i66, the frame side VDP control target 67th decoration LED control circuit 194i67 Illumination information, ..., and a screen in which the illumination information for the frame-side VDP control target 78th decoration LED control circuit 194i78 is predetermined (in this embodiment, red (R): 50%, green (G) : 50%, blue (B): gray screen with 50%) attached to door frame side drawing data It is generated to the door frame side incidental information area VRGN2b the door frame side display area VRGN2 provided on the internal VRAM with.

  Further, the distribution output control unit 194gc corresponds to the lighting information read from the buffer memory 194gb for the frame-side VDP control target 79th decoration LED control circuit 194i79 to the frame-side VDP control target 91st decoration LED control circuit 194i91. In order to be able to accurately distribute to the seventh serial controller 194gd7, the electric decoration information for the frame-side VDP control target 79th decoration LED control circuit 194i79, the frame-side VDP control target 80th decoration LED control circuit 194i80 Illumination information,..., And a screen in which the illumination information for the frame-side VDP control target 91st decoration LED control circuit 194i91 is predetermined (in this embodiment, red (R): 50%, green (G) : 50%, blue (B): gray screen with 50%) attached to door frame side drawing data It is generated to the door frame side incidental information area VRGN2b the door frame side display area VRGN2 provided on the internal VRAM with.

  Further, the distribution output control unit 194gc corresponds to the lighting information read from the buffer memory 194gb for the frame side VDP control target 92nd decoration LED control circuit 194i92 to the frame side VDP control target 104th decoration LED control circuit 194i104. In order to be able to accurately distribute to the eighth serial controller 194gd8, the electric decoration information for the frame-side VDP control target 92nd decoration LED control circuit 194i92, the frame-side VDP control target 93rd decoration LED control circuit 194i93 Illumination information,..., And a screen on which the illumination information for the frame-side VDP control target 104th decoration LED control circuit 194i104 is predetermined (in this embodiment, red (R): 50%, green (G) : 50%, Blue (B): Gray screen with 50%) It was produced on the door frame side incidental information area VRGN2b the door frame side display area VRGN2 provided on the internal VRAM as.

  Further, the distribution output control unit 194gc corresponds to the illumination information for the frame-side VDP control target 105th decoration LED control circuit 194i105 to the frame-side VDP control target 117th decoration LED control circuit 194i117 read from the buffer memory 194gb. In order to be able to accurately distribute to the ninth serial controller 194gd9, the electric decoration information for the frame-side VDP control target 105th decoration LED control circuit 194i105, the frame-side VDP control target 106th decoration LED control circuit 194i106 Screen in which the illumination information for the decoration LED control circuit 194i117 of the frame side VDP control target 117 is predetermined (in this embodiment, red (R): 50%, green (G) : 50%, blue (B): gray screen with 50%) It is generated to the door frame side incidental information area VRGN2b the door frame side display area VRGN2 provided on the internal VRAM as those subjected to data.

  Further, the distribution output control unit 194gc corresponds to the illumination information for the frame side VDP control target 118th decoration LED control circuit 194i118 to the frame side VDP control target 130th decoration LED control circuit 194i130 read from the buffer memory 194gb. In order to be able to accurately distribute to the tenth serial controller 194gd10, the electric decoration information for the frame side VDP control target 118th decoration LED control circuit 194i118, the frame side VDP control target 119 for the decoration LED control circuit 194i119 Illumination information,..., And a screen in which the illumination information for the frame-side VDP control target 130th decoration LED control circuit 194i130 is predetermined (in this embodiment, red (R): 50%, green (G) : 50%, blue (B): gray screen with 50%) door frame It is generated to the door frame side incidental information area VRGN2b the door frame side display area VRGN2 provided on the internal VRAM as denoted in the drawing data.

  Further, the distribution output control unit 194gc corresponds to the illumination information for the frame-side VDP control target 131st decoration LED control circuit 194i131 to the frame-side VDP control target 143 decoration LED control circuit 194i143 read from the buffer memory 194gb. The electric decoration information for the decoration LED control circuit 194i131 for the frame side VDP control target 131 and the decoration LED control circuit 194i132 for the frame side VDP control target 132 so that it can be accurately distributed to the eleventh serial controller 194gd11 Illumination information,..., And a screen in which the illumination information for the frame-side VDP control target 143 decoration LED control circuit 194i143 is predetermined (in this embodiment, red (R): 50%, green (G) : 50%, blue (B): gray screen with 50%) door frame It is generated to the door frame side incidental information area VRGN2b the door frame side display area VRGN2 provided on the internal VRAM as denoted in the drawing data.

  Thus, the drawing data output from the channel CH2 of the liquid crystal and sound source built-in VDP 4160a of the sound control unit 4160 in the peripheral control board 4140 is a predetermined screen (in this embodiment, red (R): 50%, green ( G): 50%, blue (B): gray screen with 50%) door frame-side drawing data provided with electrical decoration information according to a predetermined door frame-side generation rule. By generating the frame-side display area VRGN2, the first serial controller 194gd1 to the eleventh serial controller 194gd11 use the lighting information as serial data SDAT1 ′ to serial data SDAT11 ′, and the clock signal SCLK1 ′ to the clock signal SCLK11 ′. Based on the frame side VDP control target first decorative LED control circuit 194i1 to the frame-side VDP control target 143 decoration LED control circuit 194i143, among the decorative boards of the door frame 5, a plurality of frame-side VDPs to be controlled by the built-in sound source VDP 4160a. A plurality of LEDs (decorative LEDs) provided on each of the control target decorative substrates are driven. The brightness (gradation) of the decorative LED is adjusted by this drive control.

  The first serial controller 194gd1 to the eleventh serial controller 194gd11 select a common mode in which each output timing can be set to the same timing, and an individual mode in which each output timing can be set to different timings. Can be done. In the case of setting to the common mode in which the output timings of the first serial controller 194gd1 to the eleventh serial controller 194gd11 are set to the same timing, the output from the first serial controller 194gd1 to the eleventh serial controller 194gd11 is a very short period of time Even when a large current flows as an inrush current, the current shortage does not occur and no instantaneous power failure occurs. On the other hand, when the individual modes in which the output timings of the first serial controller 194gd1 to the eleventh serial controller 194gd11 are set to different timings are controlled by the outputs from the first serial controller 194gd1 to the eleventh serial controller 194gd11. When a large current flows as an inrush current to the object in a very short period of time, there is a possibility that an instantaneous power failure may occur due to power shortage.

  In the present embodiment, the individual modes in which the output timings of the first serial controller 194gd1 to the eleventh serial controller 194gd11 are different from each other are set. When the game board 4 is attached to a dedicated frame (outer frame 2, main body frame 3, and door frame 5) representing the world view expressed by the production, the game board 4 is provided on the game board 4 or the dedicated frame side. The power supply board 851 of the board unit 800 attached to the main body frame 3 so as to correspond to the power supplied to an electric drive source such as a plurality of LEDs (decorative LEDs) and a motor or solenoid for operating a plurality of movable bodies. Because the power generation circuit is designed, sufficient power is supplied so that no momentary power failure will occur even if the movable body starts operating with the start of lighting of multiple LEDs (decorative LEDs) and an electric drive source such as a motor or solenoid. Has capacity.

  However, a game board mounted on the main body frame 3 of the outer frame 2 already installed in the hall (a game board of another model different from the game board 4 (for example, the world view expressed by the production is different, LED (decorative The number of LEDs), the presence or absence of a movable body operated by an electric drive source such as a motor or a solenoid, and the number thereof may also be exchanged. Therefore, when the game board 4 is simply replaced, a plurality of LEDs ( When the lighting of the decoration LED) is started, or when the movable body starts to operate by an electric drive source such as a motor or a solenoid, there is a possibility that a momentary power failure may occur.

  Therefore, in the present embodiment, control is performed by the outputs from the first serial controller 194gd1 to the eleventh serial controller 194gd11 by setting the individual modes in which the output timings of the first serial controller 194gd1 to the eleventh serial controller 194gd11 are different timings. When a large current flows as an inrush current in a very short period with respect to the object, the power shortage can be prevented due to power shortage, and a power generation circuit that can withstand the inrush current described above is provided as a power supply substrate 851. There is no need to install it. Thereby, the load to the power supply board 851 of the board | substrate unit 800 attached to the main body frame 3 of the outer frame 2 already installed in the hole different from the exclusive frame mentioned above can be suppressed.

  Note that the liquid crystal and sound source built-in VDP 4160a in the peripheral control board 4140 is generated on the built-in VRAM because the frame frequency is set to 30 fps as described above (about every 33.3 ms). Since the drawing data is output from the channels CH1 and CH2, the drawing data output from the channel CH2 of the sound source built-in VDP 4160a is also input to the frame side signal separation control circuit 194g of the frame decoration drive amplifier board 194 approximately every 33.3 ms. Will be. Therefore, predetermined screens in the first resolution conversion unit 194gaa of the signal separation unit 194ga in the frame side signal separation control circuit 194g (in this embodiment, red (R): 50%, green (G): 50%, blue) (B: gray screen having 50%) door frame side drawing data is separated about every 33.3 ms, and in the second resolution conversion unit 194gab of the signal separation unit 194ga in the frame side signal separation control circuit 194g. The separated illumination information is all output from the first serial controller 194gd1 to the eleventh serial controller 194gd11 about serial data SDAT1 ′ to serial data SDAT11 ′ about every 33.3 ms based on the clock signals SCLK1 ′ to SCLK11 ′. The first serial controller 194gd1 11 The serial controller 194gd11 can produce effects synchronized with a plurality of controlled objects, and can prevent the deviation of the progress of the effects produced by these controlled objects. Can be suppressed.

[14-2. Configuration of LED control circuit for decoration on frame side VDP control target]
Next, the configuration of the frame-side VDP controlled object decoration LED control circuit will be described. The frame decoration drive amplifier board 194 is a frame side VDP control target decoration LED control circuit 194i, and among the decoration boards of the door frame 5, a plurality of frame side VDP controls that are controlled by the sound source built-in VDP 4160a are directly controlled. The frame-side VDP control target first decoration LED control circuit 194i1 to the frame-side VDP control target 143 decoration capable of dimming light emitted from a plurality of LEDs (decorative LEDs) provided on each of the target decoration substrates. LED control circuit 194i143 (total, 143 circuits).

  In the present embodiment, the first decoration-side LED control circuit 194i1 to the frame-side VDP control target and the thirteenth decoration-LED control circuit 194i13 of the frame-side VDP control target are dimmed and lighted as the first frame-side decoration group. It is managed. As shown in FIG. 41, the frame-side VDP control target first decoration LED control circuit 194i1 to the frame-side VDP control target thirteenth decoration LED control circuit 194i13 are arranged on the frame side in the right side decoration unit 200 of the door frame 5. A plurality of LEDs (104 LEDs (decorative LEDs)) provided on the VDP control target decorative board RV1 are dimmed and lit to decorate all of the first light emission decoration area RTV1.

  Also, what is dimmed by the frame side VDP control target 14th decoration LED control circuit 194i14 to the frame side VDP control target 26th decoration LED control circuit 194i26 is managed as the second frame side decoration group. Yes. As shown in FIG. 41, the frame side VDP control target 14th decoration LED control circuit 194i14 to the frame side VDP control target 26th decoration LED control circuit 194i26 are arranged on the frame side in the right side decoration unit 200 of the door frame 5. A plurality of LEDs (87 LEDs (decorative LEDs)) provided on the VDP control target decorative board RV2 and a plurality of LEDs (116 LEDs (decorative LEDs)) provided on the frame side VDP control target decorative board RV3 A predetermined number of LEDs (17 LEDs (decorative LEDs)) are dimmed and lighted, and all of the second light emission decoration area RTV2 and a part of the lower side of the third light emission decoration area RTV3 are Decorate with luminous.

  Also, the ones that are dimmed by the frame-side VDP control target 27th decorative LED control circuit 194i27 to the frame-side VDP control target 39th decorative LED control circuit 194i39 are managed as the frame-side decorative third group. Yes. As shown in FIG. 41, the frame-side VDP control target 27th decoration LED control circuit 194i27 to the frame-side VDP control target 39th decoration LED control circuit 194i39 are arranged on the frame side in the right side decoration unit 200 of the door frame 5. A predetermined number of LEDs (99 LEDs (decorative LEDs)) among the plurality of LEDs (116 LEDs (decorative LEDs)) provided on the VDP control target decorative substrate RV3, and the upper decorative unit 280 of the door frame 5 And dimming a predetermined number of LEDs (5 LEDs (decorative LEDs)) among a plurality of LEDs (265 LEDs (decorating LEDs)) provided on the frame side VDP control target decorative substrate RV4 in FIG. Thus, all the other parts except the lower part of the third light emission decoration region RTV3 and the lower part of the fourth light emission decoration region RTV4 are light emission decorated.

  Also, what is dimmed by the frame-side VDP control target 40th decoration LED control circuit 194i40 to the frame-side VDP control target 52nd decoration LED control circuit 194i52 is managed as a frame-side decoration fourth group. Yes. As shown in FIG. 41, the frame-side VDP control target 40th decorative LED control circuit 194i40 to the frame-side VDP control target 52nd decorative LED control circuit 194i52 are arranged in the frame-side VDP in the upper decorative unit 280 of the door frame 5. A predetermined number of LEDs (104 LEDs (decorative LEDs)) among a plurality of LEDs (265 LEDs (decorative LEDs)) provided on the control target decorative substrate RV4 are dimmed and lighted, and the fourth light emitting decorative region Light emitting decoration is performed from the portion excluding the lower part of the RTV 4 to the central portion.

  In addition, the lights controlled by the frame-side VDP control target 53rd decoration LED control circuit 194i53 to the frame-side VDP control target 65th decoration LED control circuit 194i65 are managed as the fifth frame-side decoration group. Yes. As shown in FIG. 41, the frame-side VDP control target 53rd decorative LED control circuit 194i53 to the frame-side VDP control target 65th decorative LED control circuit 194i65 are arranged in the frame-side VDP in the upper decorative unit 280 of the door frame 5. A predetermined number of LEDs (104 LEDs (decorative LEDs)) among a plurality of LEDs (265 LEDs (decorative LEDs)) provided on the control target decorative substrate RV4 are dimmed and lighted, and the fourth light emitting decorative region From the central portion of the RTV 4 to the portion excluding the upper part is decorated with light emission.

  Also, what is dimmed by the frame side VDP control target 66th decoration LED control circuit 194i66 to the frame side VDP control target 78th decoration LED control circuit 194i78 is managed as a frame side decoration sixth group. Yes. As shown in FIG. 41, the frame side VDP control target 66th decorative LED control circuit 194i66 to the frame side VDP control target 78th decorative LED control circuit 194i78 are arranged in the frame side VDP in the upper decorative unit 280 of the door frame 5. A predetermined number of LEDs (52 LEDs (decorative LEDs)) among a plurality of LEDs (265 LEDs (decorative LEDs)) provided on the control target decorative board RV4 and the frame side VDP control target decorative board LV4 A predetermined number of LEDs (52 LEDs (decorative LEDs)) among a plurality of provided LEDs (265 LEDs (decorative LEDs)) are dimmed and lighted above the fourth light emitting decorative region RTV4. A part and the upper part of the fourth light emitting decoration area LTV4 are decorated with light emission.

  In addition, what is dimmed by the frame-side VDP control target 79th decorative LED control circuit 194i79 to the frame-side VDP control target 91st decorative LED control circuit 194i91 is managed as a frame-side decorative seventh group. Yes. As shown in FIG. 41, the frame side VDP control target 79th decorative LED control circuit 194i79 to the frame side VDP control target 91st decorative LED control circuit 194i91 are arranged in the frame side VDP in the upper decorative unit 280 of the door frame 5. A predetermined number of LEDs (104 LEDs (decorative LEDs)) among the plurality of LEDs (265 LEDs (decorative LEDs)) provided on the control target decorative substrate LV4 are dimmed and lighted, and the fourth light emitting decorative region The LTV 4 is decorated with light emission from a portion excluding a part on the upper side to the center portion.

  Also, what is dimmed by the frame side VDP control target 92nd decoration LED control circuit 194i92 to the frame side VDP control target 104th decoration LED control circuit 194i104 is managed as the frame side decoration 8th group. Yes. As shown in FIG. 41, the frame-side VDP control target 92nd decorative LED control circuit 194i92 to the frame-side VDP control target 104th decorative LED control circuit 194i104 are arranged in the frame-side VDP in the upper decorative unit 280 of the door frame 5. A predetermined number of LEDs (104 LEDs (decorative LEDs)) among the plurality of LEDs (265 LEDs (decorative LEDs)) provided on the control target decorative substrate LV4 are dimmed and lighted, and the fourth light emitting decorative region The LTV 4 is decorated with light emission from the central part to the part excluding the lower part.

  Also, the frame side VDP control target 105th decoration LED control circuit 194i105 to the frame side VDP control target 117th decoration LED control circuit 194i117 are controlled by the 9th frame for the frame side decoration. Yes. As shown in FIG. 41, the frame-side VDP control target 105th decorative LED control circuit 194i105 to the frame-side VDP control target 117th decorative LED control circuit 194i117 are frame-side VDP in the upper decorative unit 280 of the door frame 5. Among a plurality of LEDs (265 LEDs (decorative LEDs)) provided on the control target decorative board LV4, a predetermined number of LEDs (five LEDs (decorative LEDs)) and the left side decorative unit 240 of the door frame 5 are provided. And dimming a predetermined number of LEDs (99 LEDs (decorative LEDs)) among a plurality of LEDs (116 LEDs (decorative LEDs)) provided on the frame side VDP control target decorative substrate LV3 in FIG. Thus, the lower part of the fourth light emitting decoration region LTV4 and all other parts excluding the lower part of the third light emitting decoration region LTV3 are decorated with light emission.

  Also, the ones that are dimmed by the frame-side VDP control target 118th decorative LED control circuit 194i118 to the frame-side VDP control target 130th decorative LED control circuit 194i130 are managed as the frame-side decorative 10th group. Yes. As shown in FIG. 41, the frame side VDP control target 118th decorative LED control circuit 194i118 to the frame side VDP control target 130th decorative LED control circuit 194i130 are arranged on the frame side in the left side decorative unit 240 of the door frame 5. Among a plurality of LEDs (116 LEDs (decorative LEDs)) provided on the VDP control target decorative board LV3, a predetermined number of LEDs (17 LEDs (decorative LEDs)) and the frame side VDP control target decorative board LV2 A plurality of LEDs (87 LEDs (decorative LEDs)) provided in the light are dimmed and lighted, and a lower part of the third light emitting decorative region LTV3 and the whole second light emitting decorative region LTV2 are provided. Decorate with luminous.

  In addition, the frame side VDP control target 131st decoration LED control circuit 194i131 to the frame side VDP control target 143 decoration LED control circuit 194i143 are controlled by the frame side VDP control target 143 decoration LED control circuit 194i143 as the 11th frame side decoration group. Yes. As shown in FIG. 41, the frame side VDP control target 131st decoration LED control circuit 194i131 to the frame side VDP control target 143 decoration LED control circuit 194i143 are arranged on the frame side in the left side decoration unit 240 of the door frame 5. A plurality of LEDs (104 LEDs (decorative LEDs)) provided on the VDP control target decorative board LV1 are dimmed and lit to decorate all of the first light emitting decorative area LTV1.

  In addition to its own control power supply, the frame decoration drive amplifier board 194 is used as a power supply for the frame-side VDP control target first decoration LED control circuit 194i1 to the frame-side VDP control target 143 decoration LED control circuit 194i143. Power (+5 V) is supplied from the power supply board 851 through the frame peripheral relay terminal plate 868 and the peripheral door frame relay terminal plate 882.

  The frame-side VDP control target first decoration LED control circuit 194i1 to the frame-side VDP control target 143 decoration LED control circuit 194i143 are each configured by the same decoration LED driver IC. The frame-side VDP control target first decoration LED control circuit 194i1 to the frame-side VDP control target 143 decoration LED control circuit 194i143 is the first board-side VDP control target of the liquid crystal output board 3420 shown in FIG. This is the same circuit as the decoration LED control circuit 3420i1 to the 27th decoration LED control circuit 3420i27 for the game board side VDP control.

  The decoration LED driver IC includes a plurality of LEDs (decoration for decoration) provided on each of a plurality of frame-side VDP control target decorative boards that are controlled by the built-in sound source VDP 4160a among the decorative boards of the door frame 5. LED) can be dimmed individually from extinction to high brightness (maximum brightness) in a total of 128 steps, with a gradation of 0 (zero) to a gradation of 127, with a gradation of 0 (zero). The light is turned off, and the brightness can be adjusted to the maximum brightness at the gradation 127. In this way, the frame-side VDP control target first decoration LED control circuit 194i1 to the frame-side VDP control target 143 decoration LED control circuit 194i143 can finely adjust the brightness of the decoration LEDs individually. Therefore, fine control such as dimming lighting of the decorative LED can be performed.

  The peripheral control MPU 4150a of the peripheral control unit 4150 on the peripheral control board 4140 controls the VDP 4160a with built-in sound source of the liquid crystal and sound control unit 4160. The sound source built-in VDP 4160a defines the configuration of the above-described predetermined screen (in this embodiment, a gray screen having red (R): 50%, green (G): 50%, blue (B): 50%). And a plurality of LEDs (decorative LEDs) provided on each of a plurality of frame-side VDP control target decorative boards that are controlled by the built-in sound source VDP 4160a among the decorative data of the door frame 5 When the light emission data defining the light emission mode is input from the peripheral control MPU 4150a, the liquid crystal and sound control ROM 4160b determines in advance based on the input screen data according to the above-described predetermined door frame side generation rule. Dummy data for drawing a screen (in this embodiment, a gray screen having red (R): 50%, green (G): 50%, blue (B): 50%) To generate sprite data and generate door frame side drawing data in the door frame side drawing data region VRGN2a of the door frame side display region VRGN2 provided on the built-in VRAM. Based on the liquid crystal and sound control ROM 4160b, among the decorative boards of the door frame 5, a plurality of LEDs (on each of the plurality of frame-side VDP control target decorative boards that are controlled by the sound source built-in VDP 4160a) Door frame side light emission mode setting image data for setting the light emission mode of the decoration LED) is extracted, and the door frame side incidental information VRRN2 of the door frame side display region VRGN2 provided on the built-in VRAM with the electric decoration information as drawing data It is generated in the use area VRGN2b. The sound source built-in VDP 4160a generates three video signals, ie, a red video signal, a green video signal, and a blue video signal, which are parallel signals of drawing data generated from the channel CH2 in the door frame side display area VRGN2, and a horizontal synchronization signal. , A vertical synchronization signal, and a clock signal, and a synchronous serial signal (serial data) called “V-by-One (registered trademark)” of THine Electronics Co., Ltd., which is a kind of clockless transmission system. And these various signals are output from the peripheral control board 4140 to the frame peripheral relay terminal board 868, the peripheral door relay terminal board 882, and the frame decoration drive amplifier 194 using only the differential 1-pair cable.

  As described above, the drawing data output from the channel CH2 of the sound source built-in VDP 4160a is a parallel signal (that is, the drawing data output from the channel CH2 of the sound source built-in VDP 4160a) in the receiver IC 194f of the frame decoration drive amplifier board 194. 3 video signals of a red video signal, a green video signal, and a blue video signal, and three synchronization signals of a horizontal synchronization signal, a vertical synchronization signal, and a clock signal). Is input to the signal separation unit 194ga in the frame side signal separation control circuit 194g. The signal separation unit 194ga displays the drawing data restored to the parallel signal on a screen predetermined in the first resolution conversion unit 194gaa (in this embodiment, red (R): 50%, green (G): 50%, blue). (B): gray screen having 50%) and the door frame side drawing data, and the second resolution conversion unit 194gab separates into the illumination information. The first resolution conversion unit 194gaa is a separated gray screen having the above-described predetermined screen (in this embodiment, red (R): 50%, green (G): 50%, blue (B): 50%). ) Is not output to other electronic components or other substrates. The second resolution conversion unit 194gab performs the writing operation by outputting the separated illumination information to the buffer memory 194gb in the frame side signal separation control circuit 194g.

  The distribution output control unit 194gc in the frame side signal separation control circuit 194g converts the illumination information read from the buffer memory 194gb into the first serial controllers 194gd1 to 11th according to the above-described predetermined door frame side generation rule. This is distributed to the serial controller 194gd11. As described above, the first serial controller 194gd1 to the eleventh serial controller 194gd11 use the decoration information as serial data SDAT1 ′ to serial data SDAT11 ′, and based on the clock signal SCLK1 ′ to clock signal SCLK11 ′, The luminance (gradation) can be adjusted and output to the frame-side VDP control target first decoration LED control circuit 194i1 to the frame-side VDP control target 143 decoration LED control circuit 194i143.

  As described above, the serial data SDAT1 ′ to serial data SDAT11 ′ and the clock signal SCLK1 ′ to clock signal SCLK11 ′ from the first serial controller 194gd1 to the eleventh serial controller 194gd11 are each connected in one serial connection (one serial system). The circuit configuration is electrically connected.

  By adopting such a single serial connection method, among the decorative boards of the door frame 5, a plurality of frame side VDP control target decorative boards that are controlled by the sound source built-in VDP 4160a are directly controlled. In order to individually dimm and illuminate a plurality of LEDs (decorative LEDs) provided on each of them, a parallel connection in which a control signal is output from each of the decorative LEDs individually, for example, from the frame decoration drive amplifier board 194 is used. Compared with the method, the number of wirings can be greatly reduced, so that the degree of freedom of wiring can be increased. And in the method of using one serial connection, it is easy to cope with the external noise not entering the wiring by reducing the number of wires. Can be suppressed.

  In the frame-side VDP control target first decorative LED control circuit 194i1 to the frame-side VDP control target 143 decorative LED control circuit 194i143, IDs that can identify the individual are duplicated by an address setting unit described later. It is set without.

  As described above, the serial data SDAT1 'to serial data SDAT11' from the first serial controller 194gd1 to the eleventh serial controller 194gd11 in the frame-side signal separation control circuit 194g convey electrical decoration information. Here, the illumination information separated in the second resolution conversion unit 194gab of the signal separation unit 194ga of the frame side signal separation control circuit 194g will be described.

  The “lighting information” has the same contents as the lighting information separated in the second resolution conversion unit 3420gab of the signal separation unit 3420ga of the game board side signal separation control circuit 3420g in the liquid crystal output board 3420 shown in FIG. It is shown and is information for designating the light emission mode, and is composed of illumination LED designation information and gradation information. The illumination LED designation information is the frame side VDP control target first decoration LED control circuit 194i1 to the frame side VDP control target 143 decoration LED control circuit 194i143, and any of the frame side VDP control target decoration LED control. This is information indicating whether a circuit is designated, and the ID described above is set. The gradation information is information indicating which gradation degree is designated from the gradation degree 0 (zero) to the gradation degree 127.

[14-2-1. Frame side VDP control object decoration LED control circuit]
In the present embodiment, the frame-side VDP control target first decoration LED control circuit 194i1 to the frame-side VDP control target 143 decoration LED control circuit 194i143 are respectively connected from the same decoration LED driver IC. Here, the frame-side VDP control target first decorative LED control circuit 194i1 will be briefly described below, and the frame-side VDP control target second decorative LED control circuit 194i2 to the frame-side VDP control target A description of the 143rd decorative LED control circuit 194i143 is omitted.

  As shown in FIG. 42, the decoration LED driver IC constituting the frame-side VDP control target first decoration LED control circuit 194i1 has 24 output channels (ch), and each channel has a maximum of 80 mA (milliamperes). This is a 24ch constant current LED driver IC capable of outputting a current of. The decoration LED driver IC mainly includes an address setting unit 194i1a, a logic processing unit 194i1b, a clock generation unit 194i1c, a data buffer unit 194i1d, a PWM unit 194i1e, and a constant current driving unit 194i1f.

  The address setting unit 194i1a can set 64 addresses as its own ID (an ID for identifying an individual) depending on the magnitude of a voltage applied to three address setting terminals (not shown). Yes. The voltage applied to the three address setting terminals is any one of a control voltage (+ 5V) DVp, 2 / 3DVp, 1 / 3DVp, and ground (GND), and 2 / 3DVp and 1 / 3DVp are control power supply DVp. And ground (GND) are divided by a plurality of resistors (not shown) electrically connected in series and taken out.

  For example, the control power supply DVp is supplied to one end of the first resistor, the other end of the first resistor is electrically connected to one end of the second resistor, and the other end of the second resistor is the third resistor. It is electrically connected to one end, and the other end of the third resistor is grounded to the ground (GND), and the resistance values of the three resistors are the same. As a result, the voltage at which the other end of the second resistor and the one end of the third resistor are electrically connected becomes 1/3 DVp, which is a third of the control voltage DVp, and the first resistor The voltage at which the other end of the second resistor and one end of the second resistor are electrically connected is 2/3 DVp, which is two-thirds of the control voltage DVp.

  As described above, the ID that can identify the individual LED driver ICs for decoration constituting the frame-side VDP control target first decoration LED control circuit 194i1 is a hardware that is a voltage applied to the three address setting terminals. With this configuration, the address setting unit 194i1a is set in advance, and is not set as appropriate by receiving data by software.

  The logic processing unit 194i1b receives the serial data SDAT1 'from the first serial controller 194gd3 in the frame side signal separation control circuit 194g based on the clock signal SCLK1' and transmits it to the data buffer unit 194i1d. When the data buffer unit 194i1d includes its own ID in the illumination LED designation information in the serial data SDAT1 ′ from the logic processing unit 194i1b based on the address that is its own ID set by the address setting unit 194i1a, It is determined that the serial data SDAT1 ′ from the logic processing unit 194i1b is for itself, and the gradation level which is the gradation information in the serial data SDAT1 ′ is captured, and the gradation level which is the captured gradation information is obtained. While the gradation level in each channel is controlled to be set in the PWM unit 194i1e, when the ID is not included in the illumination LED designation information in the serial data SDAT1 ′ from the logic processing unit 194i1b, the logic processing unit 194i1b Serial Without taking the gradient is the tone information in 'serial data SDAT1 determines that is not the one intended for it' over data SDAT1, control is performed to maintain the contents of the current state that is set in the PWM unit 194I1e.

  That is, when the frame-side VDP control target first decorative LED control circuit 194i1 receives the serial data SDAT1 ′ from the first serial controller 194gd3 in the frame-side signal separation control circuit 194g based on the clock signal SCLK1 ′, the serial data When the LED is not included in the illumination LED designation information in SDAT1 ′, the gradation information in serial data SDAT1 ′ is not taken in, and the sound source built-in VDP 4160a directly controls among the decorative boards of the corresponding door frame 5. For the plurality of LEDs (decorative LEDs) provided on each of the plurality of frame-side VDP control target decorative boards that are the control targets, the gradation level that is the gradation information captured last time is maintained. The frame-side VDP control target second decoration LED control circuit 194i2 to the frame-side VDP control target 143 decoration LED control circuit 194i143 are the same as the frame-side VDP control target first decoration LED control circuit 194i1. Further, when the serial data SDAT1 ′ to serial data SDAT11 ′ from the first serial controller 194gd1 to the eleventh serial controller 194gd11 in the frame side signal separation control circuit 194g are received based on the clock signal SCLK1 ′ to the clock signal SCLK11 ′, the serial data When the ID is not included in the illumination LED designation information in SDAT1 ′ to serial data SDAT11 ′, the gradation information in serial data SDAT1 ′ to serial data SDAT11 ′ is not taken in, respectively. Of each decorative board of the corresponding door frame 5, a plurality of LEDs (decorative LEDs) provided on each of the plurality of frame side VDP control target decorative boards that are controlled by the built-in sound source VDP 4160a The gradation level which is the gradation information fetched last time is maintained.

  The PWM unit 194i1e can perform gradation control of the brightness (gradation degree) of the LED in each channel in 128 steps from gradation 0 (zero) to gradation degree 127 from turning off to lighting (maximum luminance). The gradation control is performed for one channel by one PWM gradation control unit. That is, in the PWM unit 194i1e, gradation control is performed by the PWM gradation control unit 1 for the decoration LED in 1ch, gradation control is performed by the PWM gradation control unit 2 for the decoration LED in 2ch,... In addition, a total of 24 PWM gradation control units 1 to PWM gradation control unit 24, in which gradation control is performed by the PWM gradation control unit 24 on the decoration LEDs in 24ch, are configured. When the gradation levels are set, the PWM gradation control unit 1 to the PWM gradation control unit 24, based on the clock signal from the clock generation unit 194i1c, pass a constant current so as to flow a current having the set gradation level. The drive unit 194i1f is controlled.

  The constant current drive unit 194i1f is a full color LED that is a decoration LED by one constant current driver for one channel so as to have the gradation set in the PWM gradation control unit 1 to the PWM gradation control unit 24. A constant current is made to flow through the LED elements constituting the circuit element, and is composed of a total of 24 constant current drivers 1 to 24.

  The constant current driver 1 to the constant current driver 8 are electrically connected to one end of a resistor Rr1 ′ for setting a maximum current to flow through the decoration LED in eight channels from 1ch to 8ch, and the other end of the resistor Rr1 ′. Is grounded to the ground (GND), and one end of a resistor Rg1 ′ for setting the maximum current to flow through the decoration LED in the eight channels from 9ch to 16ch is electrically connected to the constant current driver 9 to the constant current driver 16 In addition, the other end of the resistor Rg1 ′ is grounded to the ground (GND), and the constant current driver 17 to the constant current driver 24 are resistors for setting a maximum current to be supplied to the decoration LEDs in eight channels from 17ch to 24ch. One end of Rb1 ′ is electrically connected, and the other end of the resistor Rb1 ′ is grounded to the ground (GND).

  The anode terminal of the red LED element, the anode terminal of the green LED element, and the anode terminal of the blue LED element constituting the full-color LED respectively corresponding to the constant current driver 1 to the constant current driver 24 are an electric power source for decoration ( Control power supply). The cathode terminals of the red LED elements constituting the full-color LEDs respectively corresponding to the constant current driver 1 to the constant current driver 8 are electrically connected to the LR1 terminal to the LR8 terminal, and are connected to the constant current driver 9 to the constant current driver 16, respectively. The cathode terminal of the green LED element constituting the corresponding full color LED is electrically connected to the LG1 terminal to LG8 terminal, and the blue LED element constituting the full color LED corresponding to the constant current driver 17 to constant current driver 24, respectively. The cathode terminal is electrically connected to the LB1 terminal to LB8 terminal.

  The constant current driver 1 to the constant current driver 8 apply constant currents LR1 individually set to the red LED elements constituting the full color LED, which is a decoration LED corresponding to each of the eight channels 1ch to 8ch. The constant current driver 9 to the constant current driver 16 are individually supplied to the green LED elements constituting the full-color LED corresponding to the eight channels from 9ch to 16ch, respectively. The constant current set to 1 is passed through the LG1 to LG8 terminals, respectively, and the constant current driver 17 to constant current driver 24 constitutes a full-color LED that is a decoration LED corresponding to each of the eight channels from 17ch to 24ch. Constant current set individually for each blue LED element Flow, respectively, via the B1 terminal ~LB8 terminal.

  Various internal circuits of the decoration LED driver IC are used as the internal power supply Vreg by applying the control voltage DVp to the power supply terminal of the decoration LED driver IC constituting the frame-side VDP control target first decoration LED control circuit 194i1. The GND terminal as the ground terminal is grounded to the ground (GND), so that the ground in the various internal circuits of the decoration LED driver IC is grounded to the ground (GND) of the frame decoration driving amplifier board 194.

  In this way, the decoration LED driver ICs constituting the frame-side VDP control target first decoration LED control circuit 194i1 to the frame-side VDP control target 143 decoration LED control circuit 194i143, respectively, have 24 LED elements, Since eight full-color LEDs that are decoration LEDs can be dimmed and lit individually, such dimming and lighting can be turned off, lit with one gradation, blinked with one gradation, and the like. Further, the decoration LED driver ICs constituting the frame side VDP control target first decoration LED control circuit 194i1 to the frame side VDP control target 143 decoration LED control circuit 194i143, respectively, are 1144 decoration LEDs (= 8). LED of full color LED × 143 decoration LED control circuit (decorative LED driver IC)), that is, LED of 3432 (= 3 LED elements of red, green and blue × 1144 full color LEDs) Dimmable lighting of an extremely large number of decorative LEDs called elements can be performed.

  In addition, the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 includes a plurality of frame side VDP control target decorative boards that are controlled by the sound source built-in VDP 4160a directly among the decorative boards of the door frame 5. Rather than directly outputting signals for dimming and lighting individually to a plurality of LEDs (decorative LEDs) provided for each of them, the first frame-side VDP control target that is a separate circuit from the peripheral control MPU 4150a The decorative LED control circuit 194i1 to the frame side VDP control target 143 of the decorative LED control circuits 194i143 of the decorative frames of the door frame 5 are controlled by the frame-side VDP 4160a directly controlled by the built-in sound source VDP 4160a. For dimming and lighting individually for a plurality of LEDs (decorative LEDs) provided on each control target decorative board By directly outputting the signals, the detailed control of the dimming and lighting of the plurality of LEDs is separated from the control by the peripheral control MPU 4150a, and the frame side VDP control target first decoration LED control circuit 194i1 is separated. The frame-side VDP control target 143 decoration LED control circuit 194i 143 can be left to each.

  As described above, the electrical decoration information includes a plurality of LEDs provided on each of the plurality of frame-side VDP control target decorative boards that are controlled by the built-in sound source VDP 4160a among the decorative boards of the door frame 5. A plurality of door frame side light emission mode setting image data for setting the light emission mode of (decorative LED) is stored in advance in the liquid crystal and sound control ROM 4160b. Then, the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 includes a plurality of frame side VDP control target decorative boards that are controlled by the sound source built-in VDP 4160a directly among the decorative boards of the door frame 5. The delicate control of a plurality of LEDs (decorative LEDs) provided for each of them, which is dimmed and lightly processed, is controlled by the first decoration LED control circuit 194i1 for the frame-side VDP control object and the decoration for the frame-side VDP control object 143. Since the LED control circuit 194i143 can be assigned to each of the peripheral control MPUs 4150a, it is possible to reduce the processing load of light emission control such as dimming lighting. As a result, even if the variation of the effects by the frame-side VDP control target first decoration LED control circuit 194i1 to the frame-side VDP control target 143 decoration LED control circuit 194i143 is increased, the light control is performed on the peripheral control MPU 4150a. Since the processing load of the light emission control of lighting does not increase, there is no limitation on the variation of effects. In other words, in the present embodiment, the variation of the production can be increased while reducing the processing load of the light emission control for the peripheral control MPU 4150a, so that the player's interest in the production can be made difficult to fade. . Therefore, it can contribute to suppressing a decrease in interest.

  In the present embodiment, as described above, the frame-side VDP control target first decoration LED control circuit 194i1 to the frame-side VDP control target 143 decoration LED control circuit 194i143 is the frame-side signal separation control circuit 194g. When serial data SDAT1 'to serial data SDAT11' from first serial controller 194gd1 to eleventh serial controller 194gd11 are received based on clock signal SCLK1 'to clock signal SCLK11', When the decoration LED designation information does not include its own ID, the gradation information in the serial data SDAT1 ′ to serial data SDAT11 ′ is not taken in, and the inside of the sound source among the respective decorative boards of the corresponding door frame 5 The gradation level, which is the gradation information captured last time, is maintained for a plurality of LEDs (decorative LEDs) provided on each of the plurality of frame-side VDP control target decorative substrates that are controlled directly by the VDP 4160a. It is configured as follows.

  In the present embodiment, as described above, since the frame frequency is set to 30 fps (approximately every 33.3 ms), drawing data is transmitted from the channel CH2 of the sound source built-in VDP 4160a to the frame peripheral relay terminal plate 868, and The signal is output to the frame decoration drive amplifier board 194 via the peripheral relay terminal board 882. As a result, the frame-side VDP control target first decoration LED control circuit 194i1 to the frame-side VDP control target 143 decoration LED control circuit 194i143 repeat the gradation level, which is gradation information, approximately every 33.3 ms. Since it can be updated, it is assumed that the gradation information in the drawing data output from the channel CH2 of the sound source built-in VDP 4160a has changed to something different from the normal content for some electrical reason. Even so, the opportunity to capture regular contents the next time, that is, after about 33.3 ms has elapsed, so that the decoration LED's light emission mode is changed from the normal light emission mode to the intended light emission mode in a very short period of about 33.3 ms. Even if the lighting mode changes, the player does not notice the change and the normal lighting mode (i.e., Can be corrected to atmospheric emission manner).

  The frame-side VDP control target first decorative LED control circuit 194i1 to the frame-side VDP control target 143 decorative LED control circuit 194i143 are frames included in the right-side decorative unit 200 of the door frame 5 shown in FIG. Right side VDP control target first light emission decoration region RTV1 to right side VDP control target third light emission decoration by performing dimming lighting of a plurality of LEDs (decorative LEDs) respectively provided on the side VDP control target decoration boards RV1 to RV3 The region RTV3 is decorated with light emission, and a plurality of LEDs (decorative LEDs) provided on the frame side VDP control target decoration board RV4 provided in the upper decoration unit 280 of the door frame 5 shown in FIG. The side VDP control target fourth light emission decoration region RTV4 is light emission decoration, and the frame side provided in the left side decoration unit 240 of the door frame 5 shown in FIG. The left side VDP control target first light emission decoration region LTV1 to the left side VDP control target third light emission decoration region by performing dimming lighting of a plurality of LEDs (decorative LEDs) provided on the DP control target decoration substrates LV1 to LV3, respectively. The left side is obtained by performing dimming lighting of a plurality of LEDs (decorative LEDs) provided on the frame side VDP control target decorative board LV4 provided in the upper decorative unit 280 of the door frame 5 shown in FIG. The VDP control target fourth light emission decoration area LTV4 is light emission decorated.

  In the present embodiment, the decoration LEDs whose emission modes are controlled by the frame-side VDP control target first decoration LED control circuit 194i1 to the frame-side VDP control target 143 decoration LED control circuit 194i143 are all full-color LEDs. A red LED element, a green LED element, and a blue LED element are used, but a single LED different from a full-color LED (the same color LED or a plurality of different color LEDs) is used. One group may be a full color LED and the other group may be a single LED (the same color LED or a plurality of different color LEDs). A plurality of one group and another group may be combined.

[14-3. Frame side peripheral control MPU control object decoration LED control circuit configuration]
Next, the configuration of the frame side peripheral control MPU control target decoration LED control circuit will be described. As shown in FIG. 43, the frame decoration drive amplifier board 194 is a frame-side peripheral control MPU control target decoration LED control circuit 194k, as a frame-side peripheral control MPU control target first decoration LED control circuit 194k1 to the frame-side peripheral. A seventh decorative LED control circuit 194k7 (7 circuits in total) to be controlled by the control MPU is provided.

  As described above, the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 synchronizes the frame side light emission data STL-DAT with the frame side light emission clock signal STL-CLK from the frame side decorative board serial I / O port. Then, the signal is output to the frame decoration drive amplifier board 194 via the frame peripheral relay terminal plate 868 and the peripheral door relay terminal plate 882.

  The frame side light emission data STL-DAT and the frame side light emission clock signal STL-CLK from the serial I / O port for the frame side decorative board of the peripheral control MPU 4150a are, as shown in FIG. The frame-side peripheral control MPU control target first decorative LED control circuit 194k1 to the frame-side peripheral control MPU control target seventh decorative LED control circuit 194k7 that constitute the LED control circuit 194k.

  In this embodiment, the frame-side peripheral control MPU control target first decorative LED control circuit 194k1 to the frame-side peripheral control MPU control target seventh decorative LED control circuit 194k7 are respectively configured from the same decorative LED driver IC. Among the decorative boards of the door frame 5, a plurality of LEDs (decorative LEDs) provided on each of the plurality of frame side peripheral control MPU control target decorative boards that are controlled by the peripheral control MPU 4150a directly. ) Can be dimmed. Here, the frame-side peripheral control MPU control target first decorative LED control circuit 194k1 will be briefly described below, and the frame-side peripheral control MPU control target second decorative LED control circuit 194k1 to the frame-side peripheral control MPU control. The description of the target seventh decorative LED control circuit 194k7 is omitted.

  First, the frame side light emission data STL-DAT will be described. “Frame-side light emission data” is information for designating a light emission mode, and is composed of illumination LED designation information and gradation information. The illumination LED designation information is the frame side peripheral control MPU control target first decorative LED control circuit 194k1 to the frame side peripheral control MPU control target seventh decorative LED control circuit 194k7, which frame side peripheral control MPU. This is information indicating whether or not a control target decoration LED control circuit is designated, and is set with an address (ID to be described later) for identifying an individual frame side peripheral control MPU control target decoration LED control circuit It is. The gradation information is information indicating which gradation degree is designated from the gradation degree 0 (zero) to the gradation degree 127.

  As shown in FIG. 43, the decorative LED driver IC constituting the frame-side peripheral control MPU control target first decorative LED control circuit 194k1 has 24 output channels (ch), and each channel has a maximum of 80 mA ( This is a 24ch constant current LED driver IC capable of outputting a current of milliampere. The decoration LED driver IC mainly includes an address setting unit 194k1a, a logic processing unit 194k1b, a clock generation unit 194k1c, a data buffer unit 194k1d, a PWM unit 194k1e, and a constant current driving unit 194k1f.

  The address setting unit 194k1a can set 64 addresses as IDs (IDs for identifying individuals) by voltages applied to six device address selection terminals (not shown). The voltage applied to the six device address selection terminals is one of a voltage raised to the control voltage (+5 V) side and a voltage lowered to the ground (GND) side.

  As described above, the ID that can identify the individual LED driver ICs for decoration constituting the frame-side peripheral control MPU control target first decoration LED control circuit 194k1 is a voltage applied to the six device address selection terminals. The address setting unit 194k1a is set in advance by the hardware configuration described above, and is not set as appropriate by receiving data from software.

  The logic processing unit 194k1b receives frame-side light emission data STL-DAT from the frame-side decorative board serial I / O port of the peripheral control MPU 4150a based on the frame-side light emission clock signal STL-CLK and transmits it to the data buffer unit 194k1d. To do. The data buffer unit 194k1d includes its own ID in the illumination LED designation information in the frame side light emission data STL-DAT from the logic processing unit 194k1b based on the address that is its own ID set by the address setting unit 194k1a. If it is determined that the frame side light emission data STL-DAT from the logic processing unit 194k1b is for itself, the gradation level, which is the gradation information in the frame side light emission data STL-DAT, is fetched, and the fetched gradation information Control is performed so that the gradation level in each channel is set in the PWM unit 194k1e so that the gradation level is equal to, while the ID is specified in the illumination LED designation information in the frame side light emission data STL-DAT from the logic processing unit 194k1b. When not included, the logic processing unit 194k1b It is determined that the side light emission data STL-DAT is not for itself, and the control is performed to maintain the current contents set in the PWM unit 194k1e without taking in the gradation that is the gradation information in the frame side light emission data STL-DAT. .

  The PWM unit 194k1e can perform gradation control of the brightness (gradation degree) of the LED in each channel in 128 steps from gradation 0 (zero) to gradation degree 127 from turning off to lighting (maximum luminance). The gradation control is performed for one channel by one PWM gradation control unit. That is, in the PWM unit 194k1e, gradation control is performed by the PWM gradation control unit 1 for the decoration LED in 1ch, and gradation control is performed by the PWM gradation control unit 2 for the decoration LED in 2ch. In addition, a total of 24 PWM gradation control units 1 to PWM gradation control unit 24, in which gradation control is performed by the PWM gradation control unit 24 on the decoration LEDs in 24ch, are configured. When the gradation levels are set, the PWM gradation control unit 1 to the PWM gradation control unit 24, based on the clock signal from the clock generation unit 194k1c, pass a constant current so as to flow a current having the set gradation level. The drive unit 194k1f is controlled.

  The constant current drive unit 194k1f is a full-color LED that is a decoration LED by one constant current driver for one channel so as to have the gradation set in the PWM gradation control unit 1 to the PWM gradation control unit 24. A constant current is made to flow through the LED elements constituting the circuit element, and is composed of a total of 24 constant current drivers 1 to 24.

  The constant current driver 1 to the constant current driver 24 are electrically connected to one end of a resistor Rp1 for setting a maximum current to be supplied to the decoration LED in all channels 1ch to 24ch, and the other end of the resistor Rp1 is grounded. (GND) is grounded.

  The anode terminal of the red LED element, the anode terminal of the green LED element, and the anode terminal of the blue LED element constituting the full-color LED respectively corresponding to the constant current driver 1 to the constant current driver 24 are an electric power source for decoration ( Control power supply). The cathode terminals of the red LED elements constituting the full-color LEDs respectively corresponding to the constant current driver 1 to the constant current driver 8 are electrically connected to the LR1 terminal to the LR8 terminal, and are connected to the constant current driver 9 to the constant current driver 16, respectively. The cathode terminal of the green LED element constituting the corresponding full color LED is electrically connected to the LG1 terminal to LG8 terminal, and the blue LED element constituting the full color LED corresponding to the constant current driver 17 to constant current driver 24, respectively. The cathode terminal is electrically connected to the LB1 terminal to LB8 terminal.

  The constant current driver 1 to the constant current driver 8 apply constant currents LR1 individually set to the red LED elements constituting the full color LED, which is a decoration LED corresponding to each of the eight channels 1ch to 8ch. The constant current driver 9 to the constant current driver 16 are individually supplied to the green LED elements constituting the full-color LED corresponding to the eight channels from 9ch to 16ch, respectively. The constant current set to 1 is passed through the LG1 to LG8 terminals, respectively, and the constant current driver 17 to constant current driver 24 constitutes a full-color LED that is a decoration LED corresponding to each of the eight channels from 17ch to 24ch. Constant current set individually for each blue LED element Flow, respectively, via the B1 terminal ~LB8 terminal.

  It should be noted that the control voltage DVp is applied to the power supply terminal of the decorative LED driver IC that constitutes the first decorative LED control circuit 194k1 to be controlled by the frame side peripheral control MPU, whereby various decorative LED driver ICs are used as the internal power supply Vreg. The ground terminal is supplied to the internal circuit, and the ground terminal GND is grounded to the ground (GND), whereby the ground in the various internal circuits of the decoration LED driver IC is grounded to the ground (GND) of the frame decoration drive amplifier board 194. .

  As described above, the decoration LED driver ICs constituting the frame-side peripheral control MPU control target first decorative LED control circuit 194k1 to the frame-side peripheral control MPU control target eighth decorative LED control circuit 194k8 respectively include LED elements. Since 24 LEDs, that is, eight full-color LEDs, which are decoration LEDs, can be dimmed individually, such dimming turns off, lights with one gradation, blinks with one gradation, etc. be able to. Further, the decoration LED driver ICs constituting the frame-side peripheral control MPU control target first decorative LED control circuit 194k1 to the frame-side peripheral control MPU control target seventh decorative LED control circuit 194k7 are 56 as decorative LEDs. (= 8 full-color LEDs × 7 decorative LED control circuits (decorative LED driver ICs)), that is, 168 (= 3 LED elements of red, green, and blue × 56 full colors) LED) can be dimmed and lit.

  Note that the frame-side peripheral control MPU control target first decorative LED control circuit 194k1 is provided on the frame-side peripheral control MPU control target decorative board RM1 provided in the right side decorative unit 200 of the door frame 5 shown in FIG. The right side peripheral control MPU control target first light emission decoration area RTM1 is light-decorated by performing dimming lighting of the LED (decorative LED), and the right side of the door frame 5 shown in FIG. The right side peripheral control MPU control target second light emitting decoration region RTM2 emits light by performing dimming lighting of a plurality of LEDs (decorative LEDs) provided on the frame side peripheral control MPU control target decorative board RM2 provided in the side decorative unit 200. It is designed to be decorated.

  The frame side peripheral control MPU control target second decorative LED control circuit 194k2 includes a plurality of LEDs provided on the frame side peripheral control MPU control target decorative board RM3 provided in the right side decorative unit 200 of the door frame 5 shown in FIG. The right side peripheral control MPU control target third light emission decoration region RTM3 is light-decorated by performing dimming lighting of (decorative LED), and the upper decoration unit of the door frame 5 shown in FIG. The right side peripheral control MPU control target fourth light emission decoration region RTM4 is illuminated and decorated by performing dimming lighting of a plurality of LEDs (decorative LEDs) provided on the frame side peripheral control MPU control target decoration board RM4 included in 280. It is like that.

  The frame side peripheral control MPU control target third decorative LED control circuit 194k3 includes a plurality of LEDs provided on the frame side peripheral control MPU control target decorative board LM1 provided in the left side decorative unit 240 of the door frame 5 shown in FIG. The left side peripheral control MPU control target first light emission decoration area LTM1 is light-decorated by performing dimming lighting of the (decorative LED), and the left side decoration of the door frame 5 shown in FIG. The second side peripheral control MPU control target second light emitting decoration area LTM2 is illuminated by performing dimming lighting of a plurality of LEDs (decorative LEDs) provided on the frame side peripheral control MPU control target decorative board LM2 provided in the unit 240. It has become so.

  The frame-side peripheral control MPU control target fourth decorative LED control circuit 194k4 includes a plurality of LEDs provided on the frame-side peripheral control MPU control target decorative board LM3 provided in the left side decorative unit 240 of the door frame 5 shown in FIG. By performing dimming lighting of the (decorative LED), the left side peripheral control MPU control target third light emitting decorative region LTM3 is adapted to emit light, and the upper decorative unit of the door frame 5 shown in FIG. The left side peripheral control MPU control target fourth light emitting decoration region LTM4 is illuminated and decorated by performing dimming lighting of a plurality of LEDs (decorative LEDs) provided on the frame side peripheral control MPU control target decorative board LM4 provided in 280. It is like that.

  The frame-side peripheral control MPU control target fifth decorative LED control circuit 194k5 to the frame-side peripheral control MPU control target seventh decorative LED control circuit 194k7 are connected to the plate unit 300 and the operation unit 400 shown in FIG. The entire plate unit 300 is light-decorated by performing dimming lighting of a plurality of LEDs (decorative LEDs) provided on each frame side peripheral control MPU control target decorative board, and an operation unit. The 400 dial operation unit 401 and the pressing operation unit 405 are decorated with light emission.

  Here, in this embodiment, as described above, each decorative board of the door frame 5 includes a plurality of frame side peripheral control MPU control target decorative boards that are controlled by the peripheral control MPU 4150a and a built-in sound source. There are a plurality of frame side VDP control target decorative boards that are controlled by the VDP 4160a, and a plurality of decorative LEDs provided on the door frame 5 are controlled to emit light by the peripheral control MPU 4150a, and a sound source It is divided into those whose emission is controlled by the built-in VDP 4160a. This is because a plurality of LEDs (decorative LEDs) provided on each of the plurality of frame-side peripheral control MPU control target decorative boards that are controlled by the peripheral control MPU 4150a are in the light emission mode. Things that change slowly along the way (for example, those whose light emission mode fluctuates like a gentle wave, those whose light emission mode lasts for a predetermined time, flashing at a speed that makes people blink even if the light emission mode is fast (flashing) A plurality of LEDs provided on each of the plurality of frame side VDP control target decorative boards that are controlled by the built-in sound source VDP 4160a. (Decoration LED) is a light emission mode in a dot display using LED (decoration LED) whose light emission mode changes rapidly according to the progress of production. Then, it flashes (flashes) as if it is lightning, it expresses a fireworks display, it expresses an explosion, it appears as if it is scrolling, and it displays a video of people and vehicles. (These light emission modes are quickly displayed in accordance with the progress of the effects displayed in the display area of the game board side effect display unit 1900 provided in the game board 4 shown in FIG. 8). And can be linked to the production). That is, in this embodiment, in the light emission control of the plurality of decorative LEDs provided on the door frame 5, the peripheral control MPU 4150a takes charge of the processing load which is difficult to be processed, whereas the peripheral control MPU 4150a has the processing load. A mechanism is adopted in which the sound source source built-in VDP 4160a takes charge. The frame-side peripheral control MPU control target first decorative LED control circuit 194k1 to the frame-side peripheral control MPU control target seventh decorative LED control circuit 194k7 of the frame decoration drive amplifier board 194, as described above, When the data STL-DAT is not for itself, the current light emission mode is maintained by maintaining the current contents. In other words, when the light emission mode changes slowly along with the progress of the production, the time of the same light emission mode becomes longer, so when the light emission mode changes, the peripheral control MPU 4150a is on the frame side. By outputting the light emission data STL-DAT, it is difficult to cause a processing load on the peripheral control MPU 4150a.

  As described above, in this embodiment, a plurality of LEDs (decorative LEDs) provided on each of the plurality of frame-side VDP control target decorative boards that are controlled by the built-in sound source VDP 4160a are As compared with the plurality of LEDs (decorative LEDs) provided on each of the plurality of frame side peripheral control MPU control target decorative boards that are the control targets directly controlled by the control MPU 4150a, an effect in which the change in the light emission mode is fast is assigned. ing. Note that the peripheral control MPU 4150a directly controls the plurality of LEDs (decorative LEDs) provided on each of the plurality of frame-side VDP control target decorative boards that are controlled by the built-in sound source VDP 4160a. In the same manner as the light emission modes of a plurality of LEDs (decorative LEDs) provided on each of the plurality of frame side peripheral control MPU control target decorative boards, the light emission mode may change slowly along the progress of the production. Therefore, in this case, the peripheral control MPU 4150a directly applies to a plurality of LEDs (decorative LEDs) provided on each of the plurality of frame-side VDP control target decorative boards that are controlled by the built-in sound source VDP 4160a. A plurality of LEDs provided on each of the plurality of frame side peripheral control MPU control target decorative boards that are controlled objects to be controlled Compared with decorative LED), a change in light emission mode is that the effect is assigned to the same.

  In the present embodiment, the decorative LED whose light emission mode is controlled by the frame-side peripheral control MPU control target first decorative LED control circuit 194k1 to the frame-side peripheral control MPU control target seventh decorative LED control circuit 194k7. Used a red LED element, a green LED element, and a blue LED element, all of which constitute a full color LED, but a single LED different from a full color LED (the same color LED may be used, or a plurality of different colors may be used). LED for one frame side peripheral control MPU control object decoration LED control circuit is a full color LED, and the other frame side peripheral control MPU control object decoration LED control circuit is a single LED. LED (same color LED or multiple different color LEDs) can be used, and such one frame side peripheral control It can also be a PU control target decorative LED control circuit and the other frame side peripheral control MPU control object decorative LED control circuit combines multiple.

[15. Various commands related to transmission / reception of main control board]
Next, various commands transmitted from the main control board 4100 to the payout control board 4110 and various commands transmitted from the main control board 4100 to the peripheral control board 4140 will be described with reference to FIGS. 44 is a table showing an example of various commands transmitted from the main control board to the payout control board, and FIG. 45 is a table showing an example of various commands transmitted from the main control board to the peripheral control board. FIG. 45 is a table showing a continuation of various commands transmitted from the main control board to the peripheral control board in FIG. 45, and FIG. 47 is a table showing an example of various commands from the payout control board received by the main control board. First, a prize ball command that is a command related to payout transmitted from the main control board to the payout control board will be described, and then various commands transmitted from the main control board to the peripheral control board will be described and received by the main control board. Various commands from the payout control board will be described.

[15-1. Various commands sent from the main control board to the payout control board]
The main control MPU 4100a of the main control board 4100 detects from the various winning switches such as the general winning opening switches 3020 and 3020, the first starting opening switch 3022, the second starting opening switch 2109, and the count switch 2110 shown in FIG. When the signal is input, based on these detection signals, a prize ball command for paying out a predetermined number of game balls as a prize ball is transmitted to the payout control board. This prize ball command is a command having a storage capacity of 1 byte (8 bits). In this embodiment, the pachinko gaming machine 1 and the CR unit 6 (communicating with the pachinko gaming machine 1 and driving the payout motor 744 of the pachinko gaming machine 1 (prize ball device 740) to store the upper plate 301 or When a device for paying out a game ball as a rented ball to the lower plate 302 is electrically connected (such a pachinko gaming machine is referred to as a “CR machine”), as shown in FIG. In addition, commands 10H to 1EH (“H” represents a hexadecimal number) are prepared as prize ball commands transmitted from the main control board 4100 to the payout control board 4110. In the command 10H, one prize ball is designated. In the command 11H, two prize balls are designated, and in the command 1EH, 15 prize balls are designated. The payout control board 4110 controls to pay out the game balls by driving the payout motor 744 for the designated number of prize balls.

  Also, a pachinko gaming machine 1 and a ball lending machine (a device that pays out game balls directly to the upper plate 301 and the lower plate 302 as balls for lending) are installed adjacent to the game hall (hall). When the gaming machine 1 and the ball lending machine are electrically connected (such a pachinko gaming machine is referred to as a “general machine”), as shown in FIG. 44 (b), paying out from the main control board 4100 Command 20H to command 2EH are prepared as prize ball commands to be transmitted to the control board 4110, one prize ball is designated by the command 20H, two prize balls are designated by the command 21H,... In 2EH, 15 prize balls are designated. The payout control board 4110 controls to pay out the game ball by driving the payout motor 744 for the designated number of prize balls.

  As a command common to the CR machine and the general machine, a command 30H is prepared as shown in FIG. 44C, and the self-check is designated in the command 30H. By transmitting a command 30H and checking whether or not an ACK signal is input when the transmitting side does not input an ACK signal output as a command reception confirmation from the receiving side for a predetermined period after the command is transmitted. Check the connection status. In the case of the CR machine in the present embodiment, the payout control board 4110 confirms the connection state with the CR unit 6.

[15-2. Various commands sent from the main control board to the peripheral control board]
Next, various commands transmitted from the main control board 4100 to the peripheral control board 4140 will be described. The main control MPU 4100a of the main control board 4100 transmits various commands to the peripheral control board 4140 based on the progress of the game. These various commands are commands having a storage capacity of 2 bytes (16 bits). As shown in FIGS. 45 and 46, a status indicating the type of command having a storage capacity of 1 byte (8 bits), and And a mode showing variations of performance having a storage capacity of 1 byte (8 bits).

  As shown in FIG. 45 and FIG. 46, the various commands are related to special figure 1 synchronized effect, special figure 2 synchronized effect related, jackpot related, power-on, general diagram synchronized effect related, ordinary electric role effect related, notification display, state Classified into display and other.

[15-2-1. Special Figure 1 Entrainment Production Related]
The special figure 1 tuning effect related is based on the detection signal from the first starter switch 3022 shown in FIG. 14, and, as shown in FIG. 45, the function display board 1191 shown in FIG. The upper special symbol display 1185 is composed of commands named special figure 1 synchronized effect start, special symbol 1 designation, special figure 1 synchronized effect end, and variable state designation. These various commands are assigned “A * H” as a status and “** H” (“H” represents a hexadecimal number) as a mode (“*” is a specific hexadecimal number). This is predetermined according to the specification contents of the pachinko gaming machine 1).

  The special figure 1 synchronized production start command instructs the start of the special figure synchronized production with the production pattern designated in the mode, and the special symbol 1 designated command designates the off, specific big hit and non-specific big hit. The special figure 1 tuning effect end command is for instructing the end of the special figure 1 tuning effect, and the variable state designation command is for instructing the probability and the short time state. Note that the probability and short-time state include a low-probability short-time state that indicates a low-probability state and a short-time state, a high-probability time-short state that indicates a high-probability state and a short-time state, and a low-probability state. It is composed of a low-probability non-time-short state that indicates that the state is not a short-time state, and a high-probability non-time-short state that indicates that the state is a high-probability state and not a short-time state (as a normal gaming state, Low probability non-short state is set). Here, the high probability state is a state in which the probability of a big hit is set higher than the low probability state (normal game state), and the short time state is, for example, the normal symbol display 1189 shown in FIG. Compared with the non-short-time state (normal game state), the time for displaying the symbols in a variable manner is shortened and stopped with a light emission pattern corresponding to the normal lottery result. In addition to increasing the number of stop displays compared to the non-short-time state, the period for opening and closing the movable piece 2106 shown in FIG. 8 is longer than that of the non-time-short state (normal game state) and shown in FIG. A state in which a lottery opportunity for a special symbol can be obtained without reducing the number of possessed balls by increasing the acceptance rate (entrance rate) of game balls to the second starting port 2102 (in other words, a non-short-time state In comparison, the determination of whether or not the movable piece 2106 is to be opened and closed is increased, and when the movable piece 2106 is opened and closed, the period of the opening and closing operation of the movable piece 2106 is lengthened, whereby the second start port 2102 is reached. The game ball acceptance rate (incidence rate) is increased).

  As the transmission timing of these various commands, the special symbol 1 tuning effect start command is transmitted at the start of the special symbol 1 variation, and the special symbol 1 designation command is transmitted immediately after the start of the special symbol 1 tuning effect. The effect end command is transmitted when the special symbol 1 variation time has elapsed (when the special symbol 1 is determined), and the variation state designation command is transmitted immediately after the special symbol winning information designation. These various commands are actually transmitted in the peripheral control board command transmission process in step S120 in the main control timer interrupt process described later.

[15-2-2. Special figure 2 synchronized production]
The special figure 2 synchronization effect related is based on the detection signal from the second start port switch 2109 shown in FIG. 14, and is divided into the function display board 1191 shown in FIG. 14 as shown in FIG. The special symbol display 1186 for the lower special symbol display 1186 is composed of commands with names of special figure 2 synchronization effect start, special symbol 2 designation, and special figure 2 synchronization effect end. These various commands are assigned “B * H” as a status and “** H” (“H” represents a hexadecimal number) as a mode (“*” is a specific hexadecimal number). This is predetermined according to the specification contents of the pachinko gaming machine 1).

  The special figure 2 synchronized production start command instructs the start of the special figure synchronized production with the production pattern designated in the mode, and the special symbol 2 designated command designates the off, specific big hit, and non-specific big hit. The special figure 2 synchronization effect end is an instruction to end the special figure 2 synchronization effect.

  As the transmission timing of these various commands, the special symbol 2 tuning effect start command is transmitted at the start of the special symbol 2 fluctuation start, and the special symbol 2 designation command is transmitted immediately after the start of the special symbol 2 tuning effect. The effect end command is transmitted when the special symbol 2 variation time has elapsed (when the special symbol 2 is confirmed). These various commands are actually transmitted in the peripheral control board command transmission process in step S120 in the main control timer interrupt process.

[15-2-3. Jackpot related]
As shown in FIG. 45, the jackpot-related category includes a jackpot opening, a grand prize opening 1 open Nth display, a big prize opening 1 closing display, a big prize opening 1 count display, a big hit ending, a big hit symbol display, and a small hit opening. , A small hit opening display, a small hit count display, and a command with the names of small hit ending. These commands are assigned “C * H” as a status and “** H” (“H” represents a hexadecimal number) as a mode (“*” is a specific hexadecimal number). This is predetermined according to the specification contents of the pachinko gaming machine 1).

  The jackpot opening command is for instructing the start of the jackpot opening, and the Nth display command for the winning prize opening 1 is started during the opening of the winning prize opening 1 for the 1st to 16th rounds (the attack unit 2100 shown in FIG. 8). The command indicating that the Nth round of the grand prize opening 2103 is being opened or the opening is started, and the grand prize opening 1 closing display command starts the closing of the grand prize opening 1 between rounds (the grand prize opening of the attacker unit 2100) 2103 during the closing of the round or start of closing), and the winning prize 1 count display command indicates that the number of game balls of 0 to 10 is counted (the count switch shown in FIG. 14). The number of game balls that have entered the big prize opening 2103 detected by the H.210, and the jackpot ending command is large. Ri is intended to instruct the ending start, big hit symbol display command is for instructing the big hit symbol information display.

  The small hit opening command is for instructing the start of the small hit opening, and the small hit opening display command is for starting the small hit opening (during opening or releasing the big winning opening 2103 of the attacker unit 2100 at the time of the small hit). The small hit count display command is used when the count switch 2110 detects a game ball that has entered the big winning opening 2103 during the small hit. The small hit ending command is an instruction to start the small hit ending.

  As the transmission timing of these various commands, the big hit opening command is sent at the start of the big hit opening, and the big winning opening 1 opening N-th display command is when the big winning opening 1 is opened in the 1st to 16th rounds (the large amount of the attacker unit 2100). The winning prize opening 1 closing display command is transmitted when the winning prize opening 1 is closed (the closing of the winning prize opening 2103 of the attacker unit 2100) and is sent to the winning prize. The mouth 1 count display command is used when the winning prize opening 1 is opened and when the count changes to the winning prize opening 1 (when the winning prize opening 2103 of the attacker unit 2100 is opened and when the game ball that has entered the winning prize opening 2103 is counted. The jackpot ending command is sent at the start of the jackpot ending. Transmitted, big hit symbol display command is sent during the special winning opening open (when opening the special winning opening 2103 attacker unit 2100).

  The small hit opening command is transmitted at the start of the small hit opening, and the small hit release display command is transmitted when the small hit is released (when the big winning opening 2103 of the attacker unit 2100 is opened at the small hit). The hit count display command is transmitted at the time of winning a small hit medium / large winning opening (when a game ball that has entered the large winning opening 2103 is detected by the count switch 2110 during the small hit), and the small hit ending command is Sent when a small hit ending starts. These various commands are actually transmitted in the peripheral control board command transmission process in step S120 in the main control timer interrupt process.

[15-2-4. Power on]
As shown in FIG. 45, the power-on category includes commands named “power-on state”, “power-on main control return destination”, and “power-on main prize ball number information output determination counter notification”. . These various commands are assigned “D * H” as a status and “** H” (“H” represents a hexadecimal number) as a mode (“*” is a specific hexadecimal number). This is predetermined according to the specification contents of the pachinko gaming machine 1).

  The power-on state command is for instructing the start of the RAM clear effect and the gaming state. When the power is turned on, the power-on state command includes the power-on state (including when the power is turned on, and when the power is restored due to a power failure or a momentary power failure). When the operation switch 860a is operated to clear the RAM, information indicating that, and when the power is turned on (in addition to when the power is turned on, including when the power is restored due to a power failure or a momentary power failure) )), The information indicating which state (probability and short-time state) to recover from among the low-probability short-time state, high-probability short-time state, low-probability non-short-time state, and high-probability non-short-time state, And information indicating the model code of the pachinko gaming machine. The model code of this pachinko machine, for example, when creating so-called max type, middle type, and sweet digital type, which game is for which copyright, what game specifications (for example, probability variation is When the game happens, the game will continue until the next jackpot game state is generated, and the game where the probability variation occurs when the number of changes in the special symbol is limited (for example, 30 times or 70 times). It is to specify whether it is a specification (so-called ST machine). In other words, the information on the model code of the pachinko machine specifies the series code for specifying which type is the max type, middle type, or sweet digital type indicating the model type, and the copyright of the work. Copyright code and game specifications (for example, if a probability change occurs, the game will continue until the next jackpot game state occurs, and the probability of a special symbol with a limited number of changes) It is mainly composed of a game specification code for specifying a game specification (ST machine, etc.) that causes fluctuation.

  The main control return destination command at power-on indicates the return destination of the main control board 4100 itself. The power-on main control return destination command is mainly composed of information for instructing the driving state of the start port solenoid 2105 shown in FIG. 14 and information for instructing the driving state of the attacker solenoid 2108 shown in FIG. ing.

  When the power is turned on, the main prize ball number information output determination counter notification command includes a first start port 2101, a second start port 2102, a general winning port 2104, 2201, and a big winning port where the main control board 4100 is provided in the game board 4. Instructs the value of the main prize ball number information output determination counter that counts the number of game balls to be paid out as prize balls based on the game balls entered in various winning holes such as 2103 It is stored and retained (backed up) as one piece of game backup information in the built-in RAM. The main prize ball number information output determination counter notification command at power-on is main when power is turned on (including when power is restored and when power is restored due to a power outage or momentary power failure). The value of the main prize ball number information output determination counter is read out and created from the game backup information stored and backed up (backed up) in the control built-in RAM. Note that when the RAM is cleared by operating the operation switch 860a of the payout control board 4110 shown in FIG. 15, the game backup information stored and backed up in the main control built-in RAM is initialized, and the main backup information is initialized. The value of the winning ball number information output determination counter is set to the initial value 0 (zero) (that is, when the operation switch 860a of the payout control board 4110 shown in FIG. 15 is operated to clear the RAM. Is forcibly set to zero game balls to be paid out as prize balls).

  As the transmission timing of the power-on status command, power-on main control return destination command, and power-on main prize ball number information output judgment counter notification command, the main control board power-on (in addition to power-on, (Including when power is restored due to a power outage or instantaneous power failure). Specifically, when the pachinko gaming machine 1 is turned on, when recovering from a power failure or a momentary power failure, the main control side power-on process described later is executed, and the peripheral control board in step S120 in the main control side timer interruption process In the command transmission process, a power-on state command, a power-on main control return destination command, and a power-on main prize ball number information output determination counter notification command are transmitted.

[15-2-5. General drawing related production]
The general-synchronization effect is based on the detection signal from the gate switch 2352 shown in FIG. 14, and is divided into the normal symbol display on the function display board 1191 shown in FIG. The command 1189 is composed of commands with the names of general drawing synchronization production start, universal symbol designation, universal drawing synchronization production end, and variable state designation. These various commands are assigned “E * H” as a status and “** H” (“H” represents a hexadecimal number) as a mode (“*” is a specific hexadecimal number). This is predetermined according to the specification contents of the pachinko gaming machine 1).

  The general pattern synchronization production start command is for instructing the general pattern synchronization production start with the production pattern specified in the mode, and the general pattern designation command is for specifying off, specific big hit, non-specific big hit, The figure synchronization effect end command is for instructing the end of the common figure synchronization effect, and the change state designation command is for instructing the probability and the short time state. As described above, the probability and the short time state include a low probability short time state that indicates a low probability state and a short time state, and a high probability short time state that indicates a high probability state and a short time state. A low-probability non-time-short state that indicates a low-probability state and not a time-short state, and a high-probability non-time-short state that indicates a high-probability state and not a time-short state (usually As the gaming state, a low probability non-short-time state is set).

  As the transmission timings of these various commands, the general symbol synchronization effect start command is transmitted at the time of the normal symbol 1 fluctuation start, the general symbol designation command is transmitted immediately after the general symbol synchronization effect start, and the general symbol synchronization effect end command is When the normal symbol variation time has elapsed (when the normal symbol is determined), the variation state designation command is transmitted immediately after the ordinary symbol winning information designation. These various commands are actually transmitted in the peripheral control board command transmission process in step S120 in the main control timer interrupt process.

[15-2-6. Ordinary electric role production related]
The ordinary electric role effect is related to the movable piece 2106 shown in FIG. 8 that is opened and closed by driving the start opening solenoid 2105 shown in FIG. It is composed of commands named Opening, Opening of Public Electricity, and Ending per General-purpose Map. These various commands are assigned “F * H” as a status and “** H” (“H” represents a hexadecimal number) as a mode (“*” is a specific hexadecimal number). This is predetermined according to the specification contents of the pachinko gaming machine 1).

  The opening command per base map is an instruction to start the opening per base map, and the general power open display command is the start during open general power (the movable piece 2106 is expanded in the left-right direction by driving the start opening solenoid 2105) Or the ending command per universal map is for instructing the start of ending per universal map.

  As the transmission timing of these various commands, the opening command per base map is transmitted at the start of the opening per base map, and the general power open display command is displayed when the general power is open (the movable piece 2106 is driven by the start solenoid 2105 in the left-right direction). The ending command per universal map is transmitted at the start of ending per universal map. These various commands are actually transmitted in the peripheral control board command transmission process in step S120 in the main control timer interrupt process.

[15-2-7. Notification display]
As shown in FIG. 46, the notification display section is composed of commands named as winning abnormality display, connection abnormality display, disconnection / short circuit abnormality display, magnetic detection switch abnormality display, door opening, and door closing. These various commands are assigned “6 * H” as a status and “** H” (“H” represents a hexadecimal number) as a mode (“*” is a specific hexadecimal number). This is predetermined according to the specification contents of the pachinko gaming machine 1).

  The winning anomaly display command is used when a winning ball is won other than during a big hit (while the condition device is operating) (a game ball enters the big winning port 2103 of the attacker unit 2100 even though it is not a big hit) (When the count switch 2110 detects), an instruction to start winning abnormality notification is instructed, and the connection abnormality display command is, for example, an electrical connection in a path between the main control board 4100 and the payout control board 4110. When there is an abnormality, an instruction to start connection abnormality notification is given, and the disconnection / short circuit abnormality display command includes, for example, the main control board 4100, the first start port switch 3022, the second start port switch 2109, and the count switch 2110. Instructs the start of a disconnection / short circuit abnormality display when a disconnection / short circuit of the electrical connection with the Normal display command is for instructing the start of magnetic detection switch abnormality notification when an abnormality occurs in the magnetic detection switch 3024 shown in FIG. 14.

  Further, the door opening command is sent from the door frame 5 to the main body frame 3 based on a detection signal (opening signal) from the door frame opening switch 618 input via the payout control board 4110 shown in FIG. When the door is opened, the door opening notification is instructed, and the door closing command indicates that the door frame 5 is closed with respect to the main body frame 3 based on a detection signal from the door frame opening switch 618. If the door is in the closed state, the end of door opening notification is instructed.

  As the transmission timing of these various commands, the winning abnormality display command is transmitted when winning a big winning opening other than during the big hit (the condition device is operating), and the connection abnormality displaying command is sent from the main control board 4100 to the payout control board 4110. The command is sent when there is no ACK reply (ACK signal) from the payout control board 4110 at the time of command transmission, and the disconnection / short circuit abnormality display command includes the first start port switch 3022, the second start port switch 2109, the count switch 2110, etc The magnetic detection switch abnormality display command is transmitted when an abnormality of the magnetic detection switch 3024 is detected. The door opening command is transmitted when door opening is detected (when the door frame 5 is in an open state with respect to the main body frame 3 based on a detection signal from the door frame opening switch 618). The closing command is transmitted when door closing is detected (when the door frame 5 is closed with respect to the main body frame 3 based on a detection signal from the door frame opening switch 618). These various commands are actually transmitted in the peripheral control board command transmission process in step S120 in the main control timer interrupt process.

[15-2-8. Status display]
As shown in FIG. 46, the status display section is composed of commands having names of a frame status 1 command, an error release navigation command, and a frame status 2 command. These various commands are assigned a status of “7 * H” and a mode of “** H” (“H” represents a hexadecimal number) (“*” is a specific hexadecimal number). This is predetermined according to the specification contents of the pachinko gaming machine 1).

  The frame status 1 command, the error canceling navigation command, and the frame status 2 command are commands having a storage capacity of 1 byte (8 bits) transmitted from the payout control board 4110, and detailed descriptions thereof will be described later. . When the main control MPU 4100a of the main control board 4100 receives the frame state 1 command, the error release navigation command, and the frame state 2 command from the payout control board 4110, as shown in FIG. 46, “7 * H” is displayed. While setting as a status, the received command is set as a mode as it is. That is, when the main control MPU 4100a receives the frame state 1 command, the error release navigation command, and the frame state 2 command from the payout control board 4110, it adds “7 * H” as additional information to these received commands. Thus, the command is shaped into a command having a storage capacity of 2 bytes (16 bits).

  The shaped frame status 1 command is transmitted when the power is restored, when the status of the frame is changed, and when the error cancellation navigation is performed. The error cancellation navigation command is transmitted when the error cancellation navigation is performed. And when the frame state changes. Note that the shaped frame state 1 command, error release navigation command, and frame state 2 command are actually transmitted in the peripheral control board command transmission process of step S120 in the main control timer interrupt process.

[15-2-9. Test related]
As shown in FIG. 46, the test-related classification includes various commands named “test”. This test command is assigned “8 * H” as a status and “** H” (“H” represents a hexadecimal number) as a mode (“*” is a specific hexadecimal number). And is predetermined according to the specification content of the pachinko gaming machine 1).

  The test command instructs various inspections of the peripheral control board 4140 (for example, the peripheral control unit 4150, the liquid crystal and sound control unit 4160, the motor drive board 4180, and the frame decoration drive amplifier board 194 shown in FIG. 17). Etc.) to inspect various substrates.

  As a test command transmission timing, it is transmitted when the main control board power is turned on when the RAM is not cleared and when the RAM is not cleared. Specifically, when the power of the pachinko gaming machine 1 is turned on, when the operation switch 860a of the payout control board 4110 is operated when the power is restored from a power failure or a momentary power interruption, the main control side power-on process described later And the test command is transmitted in the peripheral control board command transmission process in step S120 in the main control timer interrupt process.

[15-2-10. Others]
As shown in FIG. 46, the other categories include start opening prize, change shortening operation end designation, high probability end designation, special symbol 1 memory, special symbol 2 memory, normal symbol memory, special symbol 1 memory pre-reading effect, special It consists of a command with a name of design 2 memory pre-reading effect and main prize ball number information output. These various commands are assigned a status of “9 * H” and a mode of “** H” (“H” represents a hexadecimal number) (“*” is a specific hexadecimal number). This is predetermined according to the specification contents of the pachinko gaming machine 1).

  The start opening prize command is an instruction to start the start opening winning effect, and the start of the effect when a game ball enters the first start opening 2101 based on the detection signal from the first start opening switch 3022. , And the start of the effect when a game ball enters the second start port 2102 based on the detection signal from the second start port switch 2109, respectively, The command for instructing state transition from the shortened operating state to the variable shortening non-operating state, and the high probability end designation command is for instructing state transition from the high probability state to the low probability state. The special symbol 1 holds 0 to 4 pieces (the game ball enters the first start port 2101 shown in FIG. 8 and the special symbol display 1185 on the function display board 1191 changes the special symbol. The special symbol 2 storage command is used for 0 to 4 special symbol 2 reservations (the game ball is placed in the second start port 2102 shown in FIG. 8). The number of balls that have not yet been used to display the variation of the special symbol (reserved number) on the special symbol display 1186 under the function display board 1191 after entering the ball, and the normal symbol storage command is the normal symbol 1 hold 0 to 4 (the number of balls (the number of holdings) that the game ball has passed through the gate part 2150 shown in FIG. 8 and is not yet used in the normal symbol display 1189 of the function display board 1191 for the variable symbol display) The special symbol 1 storage pre-reading effect command is pre-read before the special symbol 1 hold is used for the special symbol change display on the special display 1118 on the function display board 1191. On hold The special symbol 2 storage pre-reading effect command instructs the start of the pre-reading effect informing the advance notice of the display result by the upper special symbol display 1185. In this case, the pre-reading effect is instructed to pre-read and notify the advance notice of the display result by the lower special symbol display unit 1186 based on the special symbol 2 hold before being used for the change display of the special symbol. The number information output command is based on game balls that the main control board 4100 has entered in various winning ports such as the first starting port 2101, the second starting port 2102, the general winning ports 2104, 2201, and the big winning port 2103. Each time the number of game balls to be paid out as 10 balls reaches 10, the main prize ball number information output signal is sent to the external terminal board 78 as the main prize ball number information. 4 is instructed to be transmitted to the hall computer.

  As the transmission timing of these various commands, the start opening winning command is the start opening winning (when the game ball enters the first start opening 2101 based on the detection signal from the first start opening switch 3022, When a game ball enters the second start port 2102 based on a detection signal from the start port switch 2109), the speaker accommodated in the speaker box 820 provided in the main body frame 3 shown in FIG. The change shortening operation end designation command is transmitted from the speaker 130 provided in the door frame 5 shown in order to notify the effect mainly by voice. The high probability end designation command is sent at the end of the stop period after the change is confirmed after digesting the high probability count in the case of “high probability N times” (after the stoppage stop period has elapsed). The special symbol 1 stored command is sent when the special symbol 1 operation holding ball number changes (the game ball enters the first start port 2101 and the special symbol display 1185 on the function display board 1191 displays the variation of the special symbol. In the state where there is a reserve number that is not yet used, when the game ball enters the first start port 2101 and the number of reserves increases, the special symbol is changed by the upper special symbol display 1185 from the hold number. The special symbol 2 storage command is used when the number of reserved balls is used for display, and when the number of special symbol 2 actuated balls changes (the game ball enters the second start port 2102 and the function display board) In the state where there is a reserve number that is not yet used for the change display of the special symbol on the lower special symbol display 1186 in 1191, when the game ball enters the second start port 2102 and the number of reserve increases, Number of holds The special symbol display command 1186 is used to display the fluctuation of the special symbol and the number of reserved symbols decreases. In the state where the ball has passed and there is the number of reservations that are not yet used for the normal symbol variation display on the normal symbol display 1189 of the function display board 1191, the game balls have passed through the gate portion 2150 and the number of reservations has increased. Or when the number of reserved symbols is reduced by using the normal symbol display 1189 to display the fluctuation of the normal symbol, the special symbol 1 memory pre-reading effect command The special symbol 2 memory pre-reading production command is transmitted when the number of reserved balls increases (second starting port). 2102 is sent when a game ball enters the ball 2102 and the number of held balls increases, and the main prize ball number information output command is the first one based on the detection signal from the first start port switch 3022 when winning the various prize holes. When a game ball enters the start port 2101, when a game ball enters the second start port 2102 based on a detection signal from the second start port switch 2109, detection signals from the general winning port switches 3020 and 3020. When a game ball enters the general winning opening 2104, 2201 and when a game ball enters the large winning opening 2103 based on the detection signal from the count switch 2110, Sent when the ball enters). These various commands are actually transmitted in the peripheral control board command transmission process in step S120 in the main control timer interrupt process.

  By the way, as described above, the start opening prize command is given at the start opening winning (when a game ball enters the first start opening 2101 based on the detection signal from the first start opening switch 3022, or the second start opening When a game ball enters the second starting port 2102 based on a detection signal from the switch 2109), a speaker housed in a speaker box 820 provided in the main body frame 3 and a speaker 130 provided in the door frame 5 However, how the peripheral control board 4140 shown in FIG. 17 uses the start opening winning command may differ depending on the specifications of the pachinko gaming machine. For example, in the pachinko gaming machine 1 in the present embodiment, in addition to notifying by voice from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, the presence or absence of fraudulent activity is monitored. It is the specification of using for the purpose. On the other hand, in other pachinko machines, the peripheral control board 4140 simply receives the start opening prize command, and the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker provided in the door frame 5 Some specifications do not notify by voice from 130.

[15-3. Various commands from the payout control board received by the main control board]
Next, various commands from the payout control board 4110 received by the main control board 4100 will be described.

  As shown in FIG. 47, the various commands from the payout control board 4110 are composed of commands named frame state 1, error release navigation, and frame state 2; frame state 1, error release navigation, and Priorities are set in the order of frame state 2.

  In the frame state 1 command, a ball breakage, a full tank, a connection abnormality and a CR non-connection are prepared in 50 or more stocks. Value 1 is set, bit 1 (B1) is set to 1 when full, bit 1 (B2) is set to 1 when there are 50 or more stocks, and bit 3 (B3) is set when connection is abnormal 1 is set, and the value 1 is set in bit 4 (B4) when the CR is not connected. In bit 5 (B5) to bit 7 (B7) of the frame state 1 command, a value 1 is set in B5, a value 0 is set in B6, and a value 0 is set in B7.

  In the error canceling navigation command, there are provided a sphere, a count switch error, and a retry error. In the case of a sphere, a value 1 is set in bit 2 (B2), and in a count switch error, a value is set in bit 3 (B3). 1 is set, and in the case of a retry error, the value 1 is set in bit 4 (B4). Here, “counting switch error” indicates whether or not the counting switch 751 shown in FIG. 15 has a problem. The “retry error” indicates that a game ball that is not consistent with the retry operation has been repeatedly paid out. Bit (B0), bit (B1), and bit 5 (B5) to bit 7 (B7) of the error cancellation navigation command have a value 0 for B0, a value 0 for B1, a value 0 for B5, a value 1 for B6, The value 0 is set in B7.

  In the frame state 2 command, a shot ball feed control circuit error is prepared, and in the shot ball feed control circuit error, a value 1 is set to bit 0 (B0). Bit 1 (B1) to Bit 7 (B7) of the frame status 2 command include a value 0 for B1, a value 0 for B2, a value 0 for B3, a value 0 for B4, a value 1 for B5, a value 1 for B6, and The value 0 is set in B7.

  As the transmission timing of these various commands, the frame status 1 command is transmitted when the power is restored, when the frame status is changed, and during error cancellation navigation, and the error cancellation navigation command is transmitted during error cancellation navigation. Is transmitted when the power is restored and when the frame state changes. These various commands are actually transmitted in the command transmission process in step S558 in the payout control unit main process of the payout control part power-on process described later.

[16. Various control processes of main control board]
Next, various control processes performed by the main control board 4100 shown in FIG. 14 according to the progress of the game of the pachinko gaming machine 1 will be described with reference to FIGS. 48 is a flowchart showing an example of main control-side power-on processing, FIG. 49 is a flowchart showing the main control-side power-on processing of FIG. 48, and FIG. 50 is an example of main control-side timer interrupt processing. It is a flowchart which shows. First, various random numbers used for game control will be described, and then the operation of the initial value update type counter, main control side power-on processing, and main control side timer interrupt processing will be described.

[16-1. Various random numbers]
As the various random numbers used for game control, a big hit determination random number used for determining whether or not to generate a big hit gaming state, and whether or not to generate a reach (reach out) when no big hit gaming state is generated Reach determination random number for use in determination, and a variable display pattern for use in determining the variable display pattern of the special symbol that is variably displayed on the upper special symbol display 1185 and the lower special symbol display 1186 shown in FIG. A random number for use in determining the jackpot symbol derived and displayed by the upper special symbol display unit 1185 and the lower special symbol display unit 1186 when the jackpot gaming state is generated, and the random number for the jackpot symbol Random number for determining the initial value for the big hit symbol for use in determining the initial value, the upper special symbol indicator 1185 for generating the small hit gaming state, and Random numbers for small hit symbols for use in determining the small hit symbols derived and displayed by the special symbol display 1186, random numbers for determining initial values for small hit symbols for use in determining the initial values of the random numbers for small hit symbols, etc. Is prepared. Further, in addition to these random numbers, a determination random number for normal symbols for use in determining whether or not to move the movable piece 2106 shown in FIG. 8 and an initial value of the random numbers for determination per normal symbol are determined. Random numbers for determining initial values for normal symbols to be used, random numbers for normal symbol variation display patterns for use in determining the variation display pattern of ordinary symbols that are variably displayed on the ordinary symbol display 1189 shown in FIG. Is prepared.

  Of the various random numbers used for such game control, the big hit determination random number is updated by hardware, while the other various random numbers are updated by software.

  For example, the big hit determination random number is directly updated by hardware by the main control built-in hardware random number circuit 4100an built in the main control MPU 4100a shown in FIG. As described above, when the main control MPU 4100a is reset, the main random number built-in circuit 4100an first sets a clock signal input to the main control MPU 4100a as an initial value within a predetermined numerical range. Based on (the clock signal output from the main control crystal oscillator MX0 shown in FIG. 24), other values within a predetermined numerical range are extracted one after another at a high speed, and all values within the predetermined numerical range are obtained. When the extraction is completed, one value within the predetermined numerical range is extracted again, and other values within the predetermined numerical range are extracted one after another based on the clock signal input to the main control MPU 4100a. To do. The main control built-in hard random number circuit 4100an repeats such a high-speed lottery, and the main control MPU 4100a wins the value extracted by the main control built-in hard random number circuit 4100an at the time of acquiring a value from the main control built-in hard random number circuit 4100an. It is set as a random number for judgment.

  On the other hand, the counter for updating the random number for determination per normal symbol is updated within a predetermined fixed numerical value range from the minimum value to the maximum value, and a range from the minimum value to the maximum value will be described later. Each time the main control side timer interrupt process is performed, the value is incremented by one. This counter counts up from the normal value for determining the initial value for determination per normal symbol toward the maximum value, and then counts up from the minimum value to the random number for determining the initial value for determination per normal symbol. When the counter finishes counting up the range from the minimum value to the maximum value of the random number for normal symbol determination, the random number for initial value determination for normal symbol is updated. Such a counter updating method is referred to as an “initial value updating type counter”. The random value for determining the initial value for normal symbol determination can be obtained by executing an initial value lottery process for drawing one value from the fixed numerical range of the counter for updating the random number for determination per normal symbol. .

  In this embodiment, when the operation switch 860a of the payout control board 4110 shown in FIG. 15 is operated when the power is turned on, or in the main control side power-on process described later, the main control MPU 4100a shown in FIG. The check sum value (sum value) obtained by calculating the sum of various information stored in the main control built-in RAM as numerical values is stored in the main control side power-off process (when the power is turned off). When the entire area of the main control built-in RAM is cleared, such as when the check sum value (sum value) does not match, the random number for determining the initial value for determining the normal value per symbol is the main control MPU 4100a shown in FIG. Takes out the ID code from the built-in non-volatile RAM, and based on this extracted ID code, it is a fixed numerical range of the counter that updates the random number for normal symbol determination Always run the initial value derivation process of deriving the same fixed value, a fixed value this derivation has a mechanism to be set. That is, the random value for determining the initial value for determining the normal symbol is always overwritten and updated with the same fixed value derived based on the ID code by executing the initial value deriving process. As described above, the value set as the random number for determining the initial value for determining the normal per symbol is derived using the ID code, and the nonvolatile RAM built into the main control MPU 4100a by the manufacturer that manufactured the main control MPU 4100a. If the ID code is stored in the ID code, the ID code is not rewritten even if an external device is used, and the ID code is executed by executing the initial value derivation process when clearing the entire area of the main control built-in RAM. The second security measure of deriving the same fixed value based on the above and the two steps of security measures are taken to prevent analysis.

  Here, an advantage will be described in which an ID code is extracted from a nonvolatile RAM incorporated in the main control MPU 4100a, and the extracted ID code is used as a random number for determining an initial value for normal symbol determination. For example, a person who illegally acquires a game ball to be paid out as a prize ball obtains the game board 4 by some method and disassembles it, and uses an ID code stored in advance in a nonvolatile RAM built in the main control MPU 4100a. Even if the counter value that is obtained illegally and the counter value for updating the determination random number per normal symbol and the determination value per normal symbol match can be grasped, the ID code is unique for identifying the individual. Since the reference numerals are attached, the ID codes are completely different from the ID codes stored in advance in the nonvolatile RAM built in the main control MPU 4100a ′ provided in the other game board 4 ′. In other words, in the other game boards 4 ′, the timing at which the counter value for updating the random number for normal symbol determination matches the normal symbol determination value is also completely different from that of the acquired game board 4. In other words, the ID code obtained by disassembling and analyzing the obtained game board 4 is not useful at all on the other game board 4 ', that is, the other pachinko gaming machine 1', so it is disassembled and analyzed. Even if a momentary power failure is generated at every predetermined interval and the game ball is passed through the gate portion 2150 shown in FIG. 8, the movable piece 2106 shown in FIG. A gaming state in which a game ball can be received at the second start port 2102 cannot be generated.

[16-2. Main control side power-on processing]
First, when the power is turned on to the pachinko gaming machine 1, the main control MPU 4100a is configured so that the stack pointer is set to a predetermined address as a default. This stack pointer indicates, for example, the address accumulated on the stack to temporarily store the contents of the memory element (register) being used, or the return address of this routine when the subroutine is terminated and the routine returns. This indicates the address accumulated on the stack for temporary storage, and the stack pointer advances each time the stack is stacked.

  The main control program described above performs main control side power-on processing as shown in FIGS. 48 and 49 under the control of the main control MPU 4100a of the main control board 4100. When the main control side power-on process is started, the main control program sets the RAM access permission under the control of the main control MPU 4100a (step S10). Update to the main control built-in RAM (game storage unit) can be performed by setting the RAM access permission.

  Subsequent to step S10, the main control program performs initial value setting and activation setting of the main control built-in WDT 4100af shown in FIG. 14 (step S12). Here, in order to set an initial value in the main control built-in WDT 4100af for monitoring whether or not the operation (system) of the main control MPU 4100a is operating normally, a watchdog timer control register (hereinafter referred to as “the main control MPU 4100a”). The timer setting value is set in the “WDT control register”), the main control built-in WDT 4100af is started, and the time measurement from when the main control MPU 4100a is reset is started. When the main control built-in WDT 4100af is activated, the time measurement by the main control built-in WDT 4100af is started, and the watch dock timer clear register ( Hereinafter, if the timer clear setting value is not set in “WDT clear register”), the main control MPU 4100a is forcibly reset by the main control built-in WDT 4100af. On the other hand, when the main control built-in WDT 4100af is activated and time measurement is started, the timer clear setting value is set in the WDT clear register until the time measured reaches the time set by the timer setting value. Timekeeping by the main control built-in WDT 4100af is cleared, and timekeeping is started again. As described above, the operation (system) of the main control MPU 4100a operates normally by repeatedly performing the process of clearing the time measurement by the main control built-in WDT 4100af until the time set by the timer set value is reached and starting the time measurement again. It can be monitored whether or not.

  Subsequent to step S12, the main control program performs a power failure clear process (step S14). In this electric power clearing process, first, output of a power outage clear signal is started to the power outage monitoring circuit 4100e shown in FIG. The power failure monitoring circuit 4100e includes a comparator MIC21 that is a voltage comparison circuit and a D-type flip-flop MIC22. The comparator MIC21, which is a voltage comparison circuit, compares the voltage between + 24V and the reference voltage, or compares the voltage between + 12V and the reference voltage, and outputs the comparison result. This comparison result shows that when no power failure or instantaneous power failure occurs, the logic becomes HI and is input to the PR terminal which is the preset terminal of the D-type flip-flop MIC22, while when a power failure or instantaneous power failure occurs. The logic becomes LOW and is input to the PR terminal which is a preset terminal of the D-type flip-flop MIC22.

  In the electric power clear process, first, output of a power outage clear signal is started to the power outage monitoring circuit 4100e, thereby starting output of the power outage clear signal to the CLR terminal which is a clear terminal of the D-type flip-flop MIC22. This power failure clear signal is input from the output terminal of the predetermined output port of the main control MPU 4100a to the CLR terminal which is the clear terminal of the D-type flip-flop IC via the main control output circuit 4100ca with a reset function by setting the logic to LOW. Is done. As a result, the main control MPU 4100a can release the latch state of the D-type flip-flop MIC22, and the logic input to the PR terminal which is the preset terminal of the D-type flip-flop MIC22 until the latch state is set. It can be inverted and output from the 1Q terminal, which is the output terminal, and the signal from the 1Q terminal can be monitored.

  Subsequently, in the electric power clear process, a wait timer process is performed to determine whether or not a power failure notice signal is input. The voltage does not increase immediately from when the power is turned on until the voltage reaches the predetermined voltage. On the other hand, when there is a power failure or a momentary power failure (a phenomenon in which the supply of power is temporarily stopped), when the voltage drops and becomes lower than the power failure warning voltage, a power failure warning signal is input as a power failure warning from the power failure monitoring circuit 4100e. Similarly, if the voltage becomes lower than the power failure warning voltage from when the power is turned on until it reaches the predetermined voltage, a power failure warning signal is input from the power failure monitoring circuit 4100e. Therefore, in the wait timer process, after the power is turned on, the process waits until the voltage becomes larger than the power failure warning voltage and stabilizes. In this embodiment, 200 milliseconds (ms) is set as the wait time (wait timer). Has been. Whether or not the power failure warning signal is input is determined based on the signal output from the 1Q terminal that is the output terminal of the D-type flip-flop MIC22 as the power failure warning signal.

  If the power failure warning signal is not input even after waiting for the voltage to become higher than the power failure warning voltage and stabilize after the power is turned on, the main control program sends a power failure clear signal to the CLR terminal which is the clear terminal of the D-type flip-flop MIC22. Stop output. Here, the power failure clear signal is output from the output terminal of a predetermined output port of the main control MPU 4100a, the logic is HI, and the CLR terminal which is the clear terminal of the D-type flip-flop IC via the main control output circuit 4100ca with reset function. Is input. As a result, the main control MPU 4100a can set the D-type flip-flop MIC22 to the latched state. When the D-type flip-flop MIC22 latches the state in which the logic is LOW and is input to the PR terminal which is the preset terminal, the D-type flip-flop MIC22 outputs a power failure warning signal from the 1Q terminal which is the output terminal.

  Subsequent to step S14, the main control program sets a state in which RAM clear processing for initializing the main control built-in RAM (game storage unit) for a predetermined time from the time of power-on can be executed. Specifically, the main control program first determines whether or not the operation switch 860a of the payout control board 4110 shown in FIG. 15 is operated (step S16). In this determination, the main control program is executed based on whether or not an error release navigation command based on an operation signal (detection signal) associated with the operation switch 860a of the payout control board 4110 being operated is input to the main control MPU 4100a. Based on the logic value of the operation signal, the main control program determines that the RAM is not instructed to be cleared when the logic value of the operation signal from the operation switch 860a is HI. On the other hand, when the logical value of the operation signal from the operation switch 860a is LOW, it is determined that the instruction to perform the RAM clear is made and it is determined that the operation switch 860a is operated.

  In step S16, when the operation switch 860a is operated, the main control program sets a value 1 to the RAM clear notification flag RCL-FLG (step S18). On the other hand, when the operation switch 860a is not operated in step S16, the main control program sets a value 0 to the RAM clear notification flag RCL-FLG (step S20). That is, the main control program can execute a RAM clear process that initializes the RAM (that is, the main control built-in RAM (game storage unit)) built in the main control MPU 4100a for a predetermined time from the time when the power is turned on. State. The RAM clear notification flag RCL-FLG described above is stored in the main control built-in RAM (game storage unit) of the main control MPU 4100a, and game information related to games such as probability variation, unpaid prize balls, and other information (for example, , A flag indicating whether or not to delete various information including information indicating the value of the main prize ball number information output determination counter). Value 1 when deleting various information, value 0 when not deleting various information Respectively. Note that the value of the RAM clear notification flag RCL-FLG set in step S18 and step S20 is stored in the general-purpose storage element (general-purpose register) of the main control MPU 4100a.

  Subsequent to step S18 or step S20, the main control program performs a wait time standby process (step S22). In this wait time standby processing, the system waits until the system for performing drawing control of the game board side effect display unit 1900 by the liquid crystal and sound control unit 4160 on the peripheral control board 4140 shown in FIG. 17 is started (booted). In this embodiment, 2.5 seconds (s) is set as a standby time (boot timer) until booting.

  Subsequent to step S22, the main control program determines whether or not a power failure notice signal is input (step S24). As described above, when the power of the pachinko gaming machine 1 is shut off, or when a power failure or instantaneous power failure occurs, a power failure warning signal is input from the power failure monitoring circuit 4100e as a power failure warning voltage when the voltage becomes equal to or lower than the power failure warning voltage. The determination in step S24 is made based on this power failure notice signal. When there is a power failure warning signal input in the determination in step S24, the main control program returns to the determination in step S24 again, and repeats the determination in step S24 as long as the power failure warning signal continues to be input. As a result, the timer clear setting value is set in the WDT clear register built in the main control MPU 4100a for the main control built-in WDT 4100af activated in step S12, the time measurement by the main control built-in WDT 4100af is cleared, and the time measurement is started again. The main control MPU 4100a is forcibly reset by the built-in main control WDT 4100af. Thereafter, the main control program performs this main control side power-on process again under the control of the main control MPU 4100a of the main control board 4100. A detailed description will be given later on that the determination in step S24 is performed following the wait time waiting process in step S22.

  When the power failure warning signal is not input in the determination in step S24, the main control program determines whether or not the RAM clear notification flag RCL-FLG is 0 (step S26). As described above, the RAM clear notification flag RCL-FLG is set to a value 1 when various information is erased and a value 0 when various information is not erased. When the RAM clear notification flag RCL-FLG is 0 in step S26, that is, when various information is not deleted, a checksum is calculated (step S28). This checksum is calculated by considering various information stored in the main control built-in RAM as numerical values.

  Subsequent to step S28, the main control program calculates the checksum value (sum value) stored in the main-control-side power-off process (at power-off) described later as the calculated checksum value (sum value). It is determined whether or not they match (step S30). If they match, the main control program determines whether or not the backup flag BK-FLG is 1 (step S32). The backup flag BK-FLG stores game information such as various information, checksum value (sum value) and backup flag BK-FLG in the main control built-in RAM in the main control side power-off process described later. This flag is set to a value of 1 when the main control-side power-off process is normally terminated, and a value of 0 when the main-control-side power-off process is not terminated normally. In the inspection process of the production line of the main control board 4100, when the main control board 4100 is turned on for the first time after being manufactured for inspection, the checksum is calculated in step S28 and the determination is made in step S30. A detailed description will be given later.

  When the backup flag BK-FLG has a value of 1 in step S32, that is, when the main control side power-off process has been normally terminated, the main control program sets the work area of the main control built-in RAM as the power is restored ( Step S34). In this setting, power recovery time information is read from a ROM (that is, main control internal ROM) built in the main control MPU 4100a, and the power recovery time information is set in the work area of the main control built-in RAM. Thereby, various information is read from the game backup information, and various commands corresponding to the various information are stored in a predetermined storage area of the main control built-in RAM. Note that “power recovery” refers to a state in which power is turned on from a power-off state, a state in which power is subsequently recovered from a power failure or a momentary power interruption, and unauthorized means (for example, an unauthorized person is placed on the skirt of his arm). A state in which the main control board 4100 is irradiated with a high frequency from the hidden high-frequency output device) and the main control MPU 4100a itself is reset and then restored is also included.

  Subsequent to step S34, the main control program sets a value 0 to the backup flag BK-FLG (step S36). As a result, various information, checksum value (sum value), and the like are changed by performing various processes thereafter, so that the main control side power-off process described later is terminated normally and the backup flag BK- If the value 1 is not set in FLG, as will be described later, the entire area of the main control built-in RAM is cleared.

  On the other hand, when the RAM clear notification flag RCL-FLG is not 0 (value 1) in step S26, that is, when various information is deleted, or when the checksum value (sum value) does not match in step S30. Alternatively, when the backup flag BK-FLG is not a value 1 (value 0) in step S32, that is, when the main control side power-off process has not been terminated normally, the main control program stores all the main control built-in RAM. The area is cleared (step S38). In other words, the main control program executes the game control side RAM clear process triggered by the input of the detection signal accompanying the operation of the operation switch 860a. Specifically, the main control program is executed by writing the value 0 in the main control built-in RAM. Alternatively, the main control program may read and set a predetermined value from the main control built-in ROM as an initial value. Further, the main control MPU 4100a instructs the RAM clear of the operation signal from the operation switch 860a, erases various information, does not match the sum value, or performs a process when the main control side power is cut off. When not completed normally, a unique ID code stored in advance in the non-volatile RAM of the main control MPU 4100a is taken out, and a fixed numerical range of a counter that updates a random number for judgment per ordinary symbol based on the taken out ID code The initial value derivation process for always deriving the same fixed value from is performed, and this fixed value is set as the normal value determining random number for determining the initial value for the normal symbol determining random value described above. To do.

  Subsequent to step S38, the main control program sets the work area of the main control built-in RAM as an initial setting (step S40). This setting is performed by reading the initial information from the main control built-in ROM and setting the initial information in the work area of the main control built-in RAM. Thereby, the game backup information is initialized, and for example, the value of the main prize ball number information output determination counter is set (set) to the initial value 0 (zero).

  Subsequent to step S36 or step S40, the main control program performs interrupt initialization (step S42). This setting is to set an interrupt cycle when a main control timer interrupt process described later is performed. In this embodiment, it is set to 4 milliseconds (ms).

  Subsequent to step S42, the main control program performs serial communication initial setting (step S44). Here, various serial input / output ports (for example, serial input / output ports (reception channels and transmission channels) for the payout control board 4110) and serial input / output ports (reception channels and transmission channels) for the peripheral control board 4140 are incorporated in the main control MPU 4100a. ) Corresponding to the transmission serial port prescaler, the transmission speed is set and the parity is set, and the transmission serial port control register is set to initialize the transmission circuit and set transmission permission.

  Subsequent to step S44, the main control program performs test signal output port initialization settings (step S46). Here, a test signal output port (not shown) for outputting various types of inspection information is initialized (set to OFF data output) when the power is turned on in the testing institution of the gaming machine.

  Subsequent to step S46, the main control program performs activation setting of the main random number circuit 4100an with built-in main control shown in FIG. 14 (step S48). Here, among the various random numbers related to the game, a hard random number control register built in the main control MPU 4100a for updating by hardware the random number for determining the big hit for use in determining whether or not to generate the big hit gaming state In addition, a setting such as latching and acquiring a random number is set, and activation of the hard random number circuit 4100an with built-in main control is set in the hard random number setting register. When the main control built-in hard random number circuit 4100an is activated by these settings, it is predetermined at a high speed based on the clock signal (clock signal output from the main control crystal oscillator MX0 shown in FIG. 24) input to the main control MPU 4100a. Extract other values in the numerical range one after another without duplication, and once all the values in the predetermined numerical range have been extracted, again extract one value in the predetermined numerical range, Based on the clock signal input to the main control MPU 4100a, other values within a predetermined numerical range are extracted one after another without overlapping. When the main control MPU 4100a acquires a random number (random number value) from the main random number 4100an with built-in main control, it outputs a latch signal to the main random number circuit 4100an with main control, and the main control when this latch signal is input. The random number (random number value) extracted by the built-in hard random number circuit 4100an is obtained from a hard random number latch register built in the main control built-in main control MPU 4100a. The main control MPU 4100a sets the acquired random number value as a jackpot determination random number.

  Subsequent to step S48, the main control program performs reservation setting for a command to be transmitted when the power is turned on (step S50). Here, in order to notify that the power has been turned on (power recovery) based on the power recovery time information set in the work area of the main control built-in RAM in the setting of the work area of the main control built-in RAM in step S34, FIG. Main control built-in RAM as transmission information by creating the power-on status command, the power-on main control return destination command, and the power-on main prize ball number information output determination counter notification command shown in Stored in the transmission information storage area. In the transmission information storage area of the main control built-in RAM, in the setting of the work area of the main control built-in RAM in step S34, various commands are read from the game backup information and various commands corresponding to the various information are stored. is there. In such a case, first after completion of transmission of various commands according to game information among various information, then power-on status command, power-on main control return destination command, and power-on main prize ball number information An output determination counter notification command is transmitted. These commands are transmitted in the main control side timer interrupt processing described later. A detailed description will be given later of reservation setting of a command to be transmitted at power-on in step S50.

  Subsequent to step S50, the main control program performs interrupt permission setting (step S52). With this setting, the main control side timer interrupt processing described later is repeated every interrupt cycle set in step S42, that is, every 4 ms.

  Subsequent to step S52, the main control program executes an error canceling navigation command associated with the operation of the operation switch 860a (operation switch) when a predetermined time elapses from when the power is turned on, that is, when the main process on the main control side is started. The execution of the game control side RAM clear process triggered by the receipt will be restricted. As described above, the main control program uses the error sharing navigation command for a predetermined time from the time of power-on as described above, based on the concept of time sharing, based on the concept of time sharing. In order to execute the RAM clear process triggered by the input, or to restrict the execution of the RAM clear process after the predetermined time has elapsed even if the error release navigation command is input, and to cancel the error notification associated with the generated error It is handled as a release switch. In other words, the operation switch 860a (error release unit) that should have been used to release an error that has occurred in relation to the payout operation is used as a game storage unit instead of a predetermined time after the power is turned on. The main control built-in RAM (and a payout control built-in RAM as a payout storage unit to be described later) functions as an operation unit for executing a RAM clear process for starting initialization, and after the predetermined time has elapsed, It can function as an operation unit for canceling an error that has occurred with respect to the ball dispensing operation.

  Next, the main control program determines whether or not a power failure notice signal is input (step S54). As described above, when the power of the pachinko gaming machine 1 is shut off, or when a power failure or instantaneous power failure occurs, a power failure warning signal is input from the power failure monitoring circuit 4100e as a power failure warning voltage when the voltage becomes equal to or lower than the power failure warning voltage. The determination in step S54 is made based on this power failure notice signal.

  When no power failure warning signal is input in step S54, the main control program performs a non-winning random number update process (step S56). In the non-winning random number update process, the above-described reach determination random number, variable display pattern random number, big hit symbol initial value determining random number, small hit symbol initial value determining random number, and the like are updated. In this way, in the non-winning random number update process, random numbers that are not involved in the winning determination (big hit determination) are updated by software. It should be noted that the above-described random numbers for normal symbol determination, random numbers for initial value determination for normal symbol determination, random numbers for normal symbol variation display pattern, and the like described above are also updated by this non-winning random number update process.

  Following step S56, the process returns to step S54 again, and the main control program determines whether or not a power failure warning signal has been input. If there is no power failure warning signal input, non-winning random number update processing is performed in step S56. Step S54 to Step S56 are repeated. The processes in steps S54 to S56 are referred to as “main control side main process”.

  On the other hand, when a power failure warning signal is input in step S54, the main control program performs interrupt prohibition setting (step S58). By this setting, the main control side timer interrupt processing described later is not performed, writing to the main control built-in RAM is prevented, and rewriting of various information including game information and other information described above is protected.

  Subsequent to step S58, the main control program starts outputting a power failure clear signal (step S60). Here, the same process as the process that started outputting the power failure clear signal in the power failure clear process in step S14 is performed. Thus, the main control program can release the latched state of the D-type flip-flop MIC22 under the control of the main control MPU 4100a.

  Subsequent to step S60, the main control program is shown in FIG. The drive signals output to the symbol memory display 1187, the normal symbol display 1189, the normal symbol memory display 1188, the game state display 1183, the round display 1190, etc. are stopped (step S62).

  Subsequent to step S62, the main control program calculates a checksum and stores the calculated value (step S64). This checksum is calculated by regarding the game information in the work area of the main control built-in RAM as a numerical value excluding the storage area for the checksum value (sum value) and backup flag BK-FLG described above.

  Subsequent to step S64, the main control program sets a value 1 to the backup flag BK-FLG (step S66). Thereby, storage of game backup information is completed.

  Subsequent to step S66, the main control program sets the RAM access prohibition (step S68). This RAM access prohibition setting prevents access to the main control built-in RAM (game storage unit), thereby preventing the contents of the main control built-in RAM (game storage unit) from being updated.

  Following step S68, an infinite loop is entered. In this infinite loop, the timer clear setting value is set in the WDT clear register incorporated in the main control MPU 4100a for the main control built-in WDT 4100af activated in step S12, the time measurement by the main control built-in WDT 4100af is cleared, and the time measurement is started again. As a result, the main control MPU 4100a is forcibly reset by the main control built-in WDT 4100af. Thereafter, the main control program performs this main control side power-on process again under the control of the main control MPU 4100a of the main control board 4100. The processing from step S58 to step S68 and the infinite loop are referred to as “main control side power-off processing”.

  The pachinko gaming machine 1 (main control MPU 4100a) is reset when a power failure occurs or when an instantaneous power failure occurs, and performs power-on processing on the main control side by subsequent power recovery.

  In step S30, it is checked whether or not the game backup information stored in the main control built-in RAM is normal. Subsequently, in step S32, whether or not the main control side power-off process has been normally completed. Are inspected. In this way, by checking the game backup information stored in the main control built-in RAM twice, it is checked whether or not the game backup information is stored by an illegal act.

  Here, the point where the presence / absence of the power failure notice signal in step S24 is determined following the wait time waiting process in step S22 will be described. First, regarding the problem in the case where the presence / absence of the power failure warning signal is not determined in step S24, that is, the value of the RAM clear flag in step S26 is determined after the wait time waiting process in step S22, and the subsequent processing is performed. The problems in will be described.

  As described above, the power supply terminal of the main control MPU 4100a is charged to the electrolytic capacitor MC2 shown in FIG. 24 when a power failure or a momentary power failure occurs and the power supply from the pachinko island facility is cut off. The electric charge is applied as +5 V for a period of about 7 milliseconds (ms) after the occurrence of a power failure or a momentary power failure. In other words, even when the power supply from the Pachinko island facility is shut off due to a momentary power failure or a power failure, the electric charge charged to the hardware called the electrolytic capacitor MC2 is applied as +5 V, so that the power supply from the pachinko island facility is The main control side power-off process can be completed within a period from when the power is shut off until about 7 ms elapses. This is because when a player is playing a game, that is, when the main control side main process or the main control side timer interrupt process described later is performed, a power failure or a momentary power failure occurs and the pachinko island facility When the power is cut off, the main control side power-off process can be completed with certainty.

  However, as an extremely rare phenomenon, the drawing control of the game board side effect display unit 1900 by the liquid crystal and sound control unit 4160 in the peripheral control board 4140 shown in FIG. Waiting time until the system starts (boots) (boot timer: 2.5 seconds is set in this embodiment) is started, and immediately before reaching the waiting time, a momentary power failure or power failure When the error occurs, the charge charged to the hardware called the electrolytic capacitor MC2 is applied as + 5V to the VDD terminal which is the power supply terminal of the main control MPU 4100a, but the interrupt initialization is performed in step S42 within a period of about 7 ms. Thereafter, the interrupt control is set in step S52, so that the main control side described later Timer interrupt processing is performed, the contents of the main control internal RAM be updated, it may be impossible to complete the main control side power-off time of processing in the main control side power-on process. For this reason, the main control side power-on process is started again at the time of power recovery without storing the calculated value of the checksum based on the contents of the main control built-in RAM.

  Then, the main control side power-on process is started at the time of the current power recovery, and the wait time waiting process in step S22 is completed without causing an instantaneous power failure or a power failure. Thereafter, in step S28, the main control built-in RAM If the value calculated in the checksum based on the contents of the checksum is compared with the value stored in the main control built-in RAM immediately before the instantaneous power failure or power failure occurs in step S30, the checksum value should match. In step S38, the entire area of the main control built-in RAM is cleared. In other words, even if the operation switch 860a is operated by the hall clerk at the time of power recovery and the intention of the hall clerk such as RAM clear is not indicated, the game backup information described above is forcibly stored in the main control built-in RAM. There is a problem that will be erased.

  Therefore, in this embodiment, immediately after the wait time waiting process in step S22, a process for determining whether or not a power failure warning signal is input is provided as step 24, and when a power failure warning signal is input, Returning to the determination in step S24, the determination in step S24 is repeatedly performed as long as the power failure warning signal continues to be input. As a result, the timer clear setting value is set in the WDT clear register built in the main control MPU 4100a for the main control built-in WDT 4100af activated in step S12, the time measurement by the main control built-in WDT 4100af is cleared, and the time measurement is started again. Therefore, the main control MPU 4100a can be forcibly reset by the main control built-in WDT 4100af. Although the RAM clear notification flag RCL-FLG is set to a value in the RAM clear notification flag RCL-FLG in step S18 or step S20 before the wait time waiting process in step S22, the value of the RAM clear notification flag RCL-FLG is as described above. Since it is stored in the general-purpose storage element (general-purpose register) of the control MPU 4100a, even if the RAM access permission is set in step S10, the contents (game information) of the main control built-in RAM are not changed at all.

  In this way, immediately after the wait time waiting process in step S22, a process for determining whether or not a power failure warning signal is input is provided as step 24, and when a power failure warning signal is input (ie, step If the power to the pachinko gaming machine 1 is cut off after waiting in the wait time waiting process of S22 (when determined by the determination of step S24), the process returns to the determination of step S24 again as long as the power failure warning signal continues to be input. By repeating the determination of step S24, the main control MPU 4100a of the main control board 4100 can be forcibly reset and the main control board 4100 can be restarted. Game information and other information (for example, the value of the main prize ball number information output determination counter) It is possible to prevent the various kinds of information including to information, etc.) is updated, so that never change occurs in the checksum calculation result. Thereby, when restarting, the main control MPU 4100a of the main control board 4100 determines that the checksum calculation result in step S28 matches the checksum calculation value stored in step S64. Therefore, the game information that is stored and held in the main control built-in RAM is not initialized immediately before a momentary power failure or power failure occurs. Therefore, at the time of power recovery, it is possible to prevent the game information immediately before the occurrence of a momentary power failure or a power failure from being initialized.

  Further, immediately after the wait time waiting process in step S22, a process for determining whether or not a power failure warning signal is input is provided as step 24, and when a power failure warning signal is not input (that is, in step S22). When the main control MPU 4100a of the main control board 4100 is proceeding with the game (when it is determined by the determination in step S24 that the power to the pachinko gaming machine 1 is not cut off after waiting in the wait time waiting process) Even if the power to the gaming machine 1 is cut off, the game information and other information by the progress of this game are supplied to the VDD terminal, which is the power terminal of the main control MPU 4100a, by supplying the power from the electrolytic capacitor MC2 shown in FIG. (For example, information indicating the value of the main prize ball number information output determination counter, etc.) is stored. Because the main control MPU 4100a of the main control board 4100 can complete the main control side power-off process constituted by the process of step S58 to step S68 and the infinite loop that is the backup process for When the main control MPU 4100a of the main control MPU 4100a is restarted, the checksum calculation result in step S28 and the checksum calculation result in the backup process (that is, the checksum calculation value stored in step S64) are displayed. Since it is determined that they match, the game information that is stored and held in the main control built-in RAM is not initialized immediately before a momentary power failure or power failure occurs. That is, the main control board 4100 can be activated by being restored to the game information immediately before the momentary power failure or power failure occurs.

  Further, immediately after the wait time waiting process in step S22, when it is determined in step S24 that a power failure warning signal has been input, the main control MPU 4100a is forcibly reset by the main control built-in WDT 4100af so that the contents of the main control built-in RAM The main control side power-off process can be started again without updating the process at all. On the other hand, immediately after the wait time standby process in step S22, if it is determined in step S24 that the power failure warning signal has not been input, As a result, it is possible to reliably complete the main control side power-off process within the “instantaneous power failure or power failure securing period” of about 7 ms. That is, in the present embodiment, when the main control side power-on process is performed at the time of power recovery, a power failure from the pachinko island facility is interrupted due to an instantaneous power failure or a power failure, and the main control MPU 4100a The electric charge charged in the electrolytic capacitor MC2 shown in FIG. 24 is applied to the VDD terminal as the power supply terminal as +5 V over a period of about 7 milliseconds (ms) after the occurrence of a power failure or a momentary power failure. Therefore, if the main control-side power-off process cannot be completed within the “instantaneous power failure or power supply securing period” of about 7 ms by the hardware of the electrolytic capacitor MC2, the wait time waiting process of step S22 is performed. In step 24 immediately after that, it is determined whether or not a power failure warning signal is input. If a power failure warning signal is input, step S24 is performed. Returning to the determination again, as long as the power failure warning signal continues to be input, the determination in step S24 is repeated to clear the timer in the WDT clear register built in the main control MPU 4100a with respect to the main control built-in WDT 4100af activated in step S12. The main control MPU 4100a can be forcibly reset by the main control built-in WDT 4100af by setting the set value and clearing the time measured by the main control built-in WDT 4100af and making it impossible to start the time measurement again. . The main control MPU 4100a is forcibly reset by such software built-in main control WDT 4100af, so that the step after step S24 (specifically, interrupt initialization is performed in step S42, and then in step S52). The contents of the main control built-in RAM (game information, and other information (for example, the number of main winning balls) are set by interrupt permission to prevent progress to the main control side timer interrupt processing described later. A mechanism is adopted in which it is possible to avoid updating various information) including information indicating information output determination counter values). Thus, when a power failure or a momentary power failure occurs and the power supply from the pachinko island facility is shut off, the contents of the main control built-in RAM (game information and other information (for example, main prize ball number information output determination counter) The various information including the information indicating the value of the data) is covered by software so that it will not be changed at all, and the contents of the main control built-in RAM (game information, and other The information (for example, various information including information indicating the value of the main prize ball number information output determination counter) is divided into two parts that are covered by hardware so that the information is not changed at all. It is possible to reliably prevent the contents of the control built-in RAM (game information and other information (for example, various information including the value of the main prize ball number information output determination counter)) from being changed. It has been cut way.

  Next, a description will be given of the reservation setting of the command to be transmitted when the power is turned on in step S50. In step S50, as described above, the fact that the power has been turned on (recovered) based on the power recovery time information set in the work area of the main control built-in RAM in the setting of the work area of the main control built-in RAM in step S34. In order to communicate, the power-on state command shown in FIG. 45, the power-on main control return destination command, and the power-on main prize ball number information output determination counter notification command are generated and transmitted. Information is stored in the transmission information storage area of the main control built-in RAM. As described above, the power-on main control return destination command mainly includes information for instructing the driving state of the start port solenoid 2105 and information for instructing the driving state of the attacker solenoid 2108 shown in FIG. Yes. Here, first, when the power-on main control return destination command does not include the information for instructing the driving state of the start-up solenoid 2105 and the information for instructing the driving state of the attacker solenoid 2108 shown in FIG. The problem in the case where the reservation setting of the command to be transmitted when the power-on main control return destination command is turned on in step S50 is not performed in step S50 will be described.

  For example, when the peripheral control board 4140 controls the display of the big hit game state screen (for example, the big hit game effect screen) in the display area of the game board side effect display unit 1900 shown in FIG. When the attacker solenoid 2108 is driven and the large winning opening 2103 shown in FIG. 8 is opened by the opening / closing member 2107, an instantaneous power failure or power failure occurs, and then the power is restored, the main control board 4100 Based on the power recovery time information set in the work area of the main control built-in RAM in the setting of the work area of the main control built-in RAM in S34, the game state immediately before the occurrence of a momentary power failure or power failure is restored. The drive of the solenoid 2108 is started to shift from the state where the special winning opening 2103 is closed by the opening / closing member 2107 to the opened state. To become.

  However, when a momentary power failure or a power failure occurs, the peripheral control board 4140 receives various commands from the main control board 4100 and returns when power is restored. Then, when the power is restored thereafter, the peripheral control board 4140 can return based on the probability indicated by the power-on state command received from the main control board 4100 at the time of power restoration and the short-time state. However, when the main control board 4100 is generating a big hit gaming state as a gaming state, if an instantaneous power failure or a power failure occurs, and then power is restored, the peripheral control board 4140 is in the main control board 4100 when power is restored. Even if the screen can be displayed in the display area of the game board side effect display unit 1900 and returned based on the probability and the time-short state based on the probability and the time-short state indicated by the power-on state command received from It is not possible to indicate at all which round of the jackpot gaming state. In other words, for example, a prize winning port 1 count display command for transmitting the number of gaming balls that are detected by the count switch 2110 shown in FIG. Even if the main control board 4100 transmits to the peripheral control board 4140 and the peripheral control board 4140 receives the peripheral control board 4140, the peripheral control board 4140 has a game ball ball that has entered the big winning opening 2103 on the screen according to the probability and the short time state. Even if the number can be displayed in the display area of the game board side effect display unit 1900, it is not possible to display which round of the big hit gaming state (that is, how many rounds).

  In such a situation, for example, when the main control board 4100 finishes the fourth round (fourth round) in the big hit gaming state, the driving of the attacker solenoid 2108 is stopped and the big winning opening 2103 is opened by the opening / closing member 2107. From the main control board 4100 to the peripheral control board for instructing to shift from the closed state to the closed state (that is, closing start between rounds of the big prize opening 2103 of the attacker unit 2100). 4140, when the main control board 4100 starts the fifth round of the big hit gaming state (the fifth round), the attack solenoid 2108 starts to be driven and the big prize opening 2103 is closed by the opening / closing member 2107 To the state of being released from the state (that is, the big prize opening 2103 To send a special winning opening open the fifth display command instructing the open start) times th round from the main control board 4100 to the peripheral control board 4140. As a result, the peripheral control board 4140 finally switches the screen of starting five rounds of the big hit gaming state from the screen corresponding to the above-described probability and time-shortening state and displays it on the display area of the game board side effect display unit 1900 Become.

  In addition, for example, a screen (for example, a message indicating that the movable piece is open) indicating that the game state is such that the game ball can be received at the second start port 2102 and the game state is advantageous to the player. When the peripheral control board 4140 controls the display on the display area of the game board side effect display unit 1900, the main control board 4100 drives the start port solenoid 2105 to move the movable piece 2106 shown in FIG. Is moved from the advanced position to the retracted position to open the second start port 2102. When an instantaneous power failure or a power failure occurs, and then the power is restored, the main control board 4100 causes step S34. In the setting of the work area of the main control built-in RAM, the game state immediately before the occurrence of a momentary power failure or power failure can be restored based on the power recovery information set in the work area of the main control built-in RAM. Makes it shifts to state that closes the second start hole 2102 is moved to the advanced position from the retracted position of the movable piece 2106 and starts driving the starting opening the solenoid 2105.

  However, when a momentary power failure or a power failure occurs, the peripheral control board 4140 receives various commands from the main control board 4100 and returns when power is restored. When power is restored thereafter, the peripheral control board 4140 can be restored based on the power-on state command received from the main control board 4100 at the time of power restoration. However, when the main control board 4100 is in a gaming state and a gaming state in which a gaming ball can be received in the second starting port 2102 is generated and a gaming state advantageous to the player is generated, a momentary power failure or power failure occurs. Then, when the power is restored after that, the peripheral control board 4140 displays the screen according to the probability and the time-short state based on the probability and the time-short state indicated by the power-on state command received from the main control board 4100 at the time of power recovery. Even if it can be displayed in the display area of the game board side effect display unit 1900 and returned, it becomes a gaming state in which a game ball can be received at the second start port 2102 and becomes a gaming state advantageous to the player. The peripheral control board 4140 cannot display the screen indicating that it is present in the display area of the game board side effect display unit 1900 at all. For this reason, a player who sits in front of a pachinko machine is surprised that a momentary power failure or power failure has occurred, and at the time of power recovery, a game ball is placed at the second start port 2102 immediately before the momentary power failure or power failure occurs. In some cases, the player may forget that the game state is acceptable. In such a case, the game state is restored to the second start port 2102 as the game state at the time of power recovery. In spite of this, the screen for instructing the game in the display area of the game board side effect display unit 1900 at the time of power recovery (that is, the screen for instructing the game to enter the game ball into the second start port 2102) is not displayed. As a result, there is also a problem that the player does not know what kind of game he plays.

  As described above, in the two examples described above, there is a problem that it is not possible to quickly return to the gaming state immediately before the instantaneous power failure or the power failure after the power is restored. In other words, a player who sits in front of a pachinko machine has a power outage after a momentary power failure or power failure, and when the power is restored, the pachinko machine system appears to be clumped, so-called frozen, and has failed. There was a problem of misunderstanding.

  Therefore, in the present embodiment, when the main control board 4100 is turned on (including when the power is turned on, and also when the power is restored due to a power failure or a momentary power failure), the power-on state command In step S50, the power-on state command and the power-on main control return destination command shown in FIG. 45 are transmitted to the peripheral control board 4140. Then, a counter notification command for determining the main prize ball number information output at power-on is created and stored as transmission information in the transmission information storage area of the main control built-in RAM. These commands are transmitted in a main control timer interrupt process described later.

  Thereby, the peripheral control board 4140, for example, in the above-described example, in the four rounds of the big hit gaming state, based on the power-on state command and the power-on main control return destination command received from the main control board 4100. When a momentary power failure or power failure occurs, and then the power is restored, as the return destination of the main control board 4100, the attacker solenoid 2108 starts to be driven and the special winning opening 2103 is released from the state closed by the opening / closing member 2107. The peripheral control board 4140 can tell the peripheral control board 4140 that it is to shift to the current state, so that the peripheral control board 4140 has specified that it is the fourth round of the big hit gaming state (that is, a screen showing how many rounds it is) ) Cannot be displayed in the display area of the game board side effect display unit 1900, A screen (for example, “It is a big hit. The big prize opening is open. A game is played in the big prize opening is started.) The drive of the tacker solenoid 2108 is started and the big prize opening 2103 is opened by the opening / closing member 2107. Please display a message that tells the player that the ball should enter the ball. ”Is displayed in the display area of the game board side effect display unit 1900 and returned to the player sitting in front of the pachinko machine. It is possible to instruct the game to enter the game ball into the grand prize opening 2103 after the electric power. For example, in the example described above, the game state is such that the game ball can be received at the second start port 2102. When a momentary power failure or power failure occurs in a game state that is advantageous to the player, and then power is restored, the main control board 4100 is returned to the start port A screen (e.g., “The movable piece is open”) is started to move the movable piece 2106 from the advanced position to the retracted position and the second start port 2102 is opened. “Perform the game so that the game ball enters the second starting port” is displayed in the display area of the game board side effect display unit 1900 by the peripheral control board 4140. Thus, it is possible to instruct the player sitting on the front surface of the pachinko gaming machine to enter the game ball into the second starting port 2102 after power is restored. Thereby, when a power failure occurs or a power failure occurs and then power is restored, the return destination of the peripheral control board 4140 can be finely instructed on the main control board 4100 side. Therefore, it is possible to quickly return to the gaming state immediately before the momentary power failure or power failure after the power recovery. In other words, a player who sits in front of a pachinko machine has a power outage after a momentary power failure or power failure, and when the power is restored, the pachinko machine system appears to be clumped, so-called frozen, and has failed. Misunderstanding can be prevented.

  Next, in the main control board inspection process, which is an inspection process for the production line of the main control board 4100, when the main control board 4100 is first turned on after being manufactured for inspection, Calculation and determination in step S30 will be described. In the main control board inspection process, when the main control board 4100 is turned on for the first time after being manufactured for inspection, the main control board is configured by the above-described processes of steps S58 to S68 which are backup processes and an infinite loop. Since the main control MPU 4100a of the main control board 4100 has never executed the control-side power-off process, even if the checksum based on the contents of the main control built-in RAM is calculated in step S28, in step S30. In the comparison determination, the checksum values cannot be matched, and the entire area of the main control built-in RAM is always cleared in step S38. Thus, when the reservation setting of the command to be transmitted at power-on is performed in step S50, the power-on state command, power-on main control return destination command, and power-on time shown in FIG. By creating a counter notification command for main prize ball number information output determination and storing it as transmission information in the transmission information storage area of the main control built-in RAM, a power-on status command, a power-on main control return destination command, and a power Only three commands, the counter notification command for main prize ball number information output determination at the time of insertion, are stored in the transmission information storage area of the main control built-in RAM as transmission information. In these main control side timer interrupt processing, which will be described later, first, a power-on state command is transmitted, followed by a power-on main control return destination command, followed by a power-on main prize ball number. An information output determination counter notification command is transmitted. Using this, in the main control board inspection process, when the main control board 4100 is first turned on after manufacturing for inspection, the power-on state command is sent from the main control board 4100 as the first command. It is transmitted to the inspection device in the main control board inspection process.

  By the way, as described above, the power-on state command is shown in FIG. 15 when the power is turned on (including when the power is turned on and when the power is restored due to a power failure or a momentary power failure). When the operation switch 860a of the payout control board 4110 shown in the figure is operated to clear the RAM, information indicating that and when the power is turned on (in addition to when the power is turned on, a power failure or a momentary power failure occurs, (Including the time of recovery to recover)) In any of the above states (probability and short-time state) among the low probability short-time state, high-probability short-time state, low-probability non-short-time state, and high-probability non-short-time state Information indicating whether or not to perform, and information indicating a model code of the pachinko gaming machine. Here, a problem in the case where the power-on state command does not include information indicating the model code of the pachinko gaming machine will be described.

  As described above, the model code of the pachinko gaming machine is the type of pachinko gaming machine 1 (to be precise, the main control board 4100) which is created when each of the so-called max type, middle type and sweet digital type is created. What kind of gaming specifications (for example, if the probability change occurs, the game will continue until the next big hit gaming state occurs, and the number of special symbol changes is limited ( For example, it is possible to specify whether the game specification (so-called ST machine) in which the probability variation occurs in the state of 30 times or 70 times))).

  In the production line of the manufacturer that manufactures the pachinko gaming machine 1, when the main control board 4100 is manufactured, the main control board 4100 for the copyrights of a plurality of types of works may be mixed. Then, the worker on the production line is responsible for the copyright of which work among the copyrights of a plurality of kinds of works (for example, the copyrights of the works of movie A, movie B, drama C, movie D, comic E, and comic F). It is difficult to know whether the main control board 4100 is flowing to the production line in order to manufacture the control board 4100, or the main control board for one copyright (for example, the copyright of the movie D) among a plurality of types of works. Although the main control board 4100 flows to the production line to manufacture the 4100, the main control board 4100 is used to manufacture the main control board 4100 for another copyright (for example, the copyright of the work of the comic F). There is also a misunderstanding and misunderstanding that it is flowing in the production line. For this reason, when manufacturing the main control board 4100 in the manufacturing line of the manufacturer that manufactures the pachinko gaming machine 1, if the main control boards 4100 for the copyrights of a plurality of types of works are mixed, the operator of the manufacturing line It is not possible to confirm which copyright of the work is the main control board 4100 manufactured in, and for any copyright of the same work, which model type (max type, middle type, sweet digital type, It is also not possible to confirm what type of game it is and what game specifications (game specifications or ST machines that will continue until the next jackpot gaming state occurs when probability changes occur) . Thus, when the main control board 4100 is manufactured in the production line of the manufacturer that manufactures the pachinko gaming machine 1 and the main control board 4100 for the copyrights of a plurality of types of works is mixed, the main control over the copyrights of the types of works is mixed. The board 4100 is mixed and sent to the game board assembly line for attaching the main control board 4100 to the game board 4. For this reason, the operator of the game board assembly line may attach the main control board 4100 that does not correspond to the game board 4 for the copyright of the work to the game board 4. As a result, there is a problem that the production efficiency of the game board 4 decreases.

  Therefore, in the present embodiment, when the main control board 4100 is turned on (including when the power is turned on, and also when the power is restored due to a power failure or a momentary power failure), the model of the pachinko gaming machine In order to transmit a power-on state command including information indicating a code to the peripheral control board 4140, in step S50, a power-on state command classified into power-on shown in FIG. A command and a main notice ball number information output determination counter notification command upon power-on are created and stored as transmission information in a transmission information storage area of the main control built-in RAM. These commands are transmitted in a main control timer interrupt process described later.

  Thereby, an operator of the manufacturing line of the manufacturer that manufactures the pachinko gaming machine 1 turns on the main control board 4100 in the main control board inspection process, which is the inspection process of the production line, so that the inspection apparatus can control the main control board. Based on the information indicating the model code of the pachinko gaming machine included in the power-on state command received from 4100, that is, the above-described max type indicating the model type, which constitutes the information indicating the model code of the pachinko gaming machine, A series code for specifying which type is a middle type or a sweet digital type, a copyright code for specifying the copyright of a work, and a game specification (for example, if a probability change occurs, the next jackpot In addition to the game specification that the state will continue until the game state occurs, the number of fluctuations of the special symbol is limited Based on a game specification code for specifying a game specification (ST machine, etc.) in which a probability variation occurs, the main control board 4100 determines which work piece the main control board 4100 displays by checking the detailed model information displayed on the inspection monitor. It is possible to determine whether it is for the copyright, and for the copyright of the same work, which model type (max type, middle type, and sweet digital type) and how It is also possible to determine whether the game specification is a game specification (a game specification or ST machine in which, if a probability change occurs, that state will continue until the next big hit gaming state occurs). Thereby, when manufacturing the main control board 4100 in the manufacturing line of the manufacturer that manufactures the pachinko gaming machine 1, even if the main control board 4100 for the copyrights of a plurality of types of works is mixed, the main control board inspection of the manufacturing line The operator of the process can determine the model type of the main control board 4100, the copyright of the work, and the game specifications accurately by visually checking the inspection monitor, so that the main control board 4100 with respect to the copyright of the work is sorted and followed. Can be sent to the game board assembly line. Then, the operator of the game board assembly line can securely attach the main control board 4100 corresponding to the game board 4 for the copyright of the work to the game board 4, and the main control board not corresponding to the game board 4 for the copyright of the work. It is possible to prevent the production efficiency of the game board 4 from being lowered due to the work of attaching 4100 to the game board 4. Therefore, it can contribute to the improvement of the production efficiency of the game board 4.

[16-3. Main control timer interrupt processing]
Next, the main control timer interrupt process will be described. The main control side timer interrupt process is repeatedly performed every interrupt period (4 ms in this embodiment) set in the main control side power-on process shown in FIGS.

  When the main control side timer interrupt process is started, on the main control board 4100, the main control program switches the register banks as shown in FIG. 50 under the control of the main control MPU 4100a (step S100). The general-purpose storage element (general-purpose register) of the main control MPU 4100a has two register banks each composed of a first register bank and a second register bank. The first register bank is used in the main control main process in the main control side power-on process described above, while the second register bank is used in the main control side timer interrupt process which is this routine. In step S100, since the second register bank is used in the main control side timer interrupt processing which is this routine, the second register bank is used from the first register bank used in the main control main processing in the main control side power-on processing. The register bank is switched to the register tank. In the present embodiment, when the main control timer interrupt process, which is this routine, is started, the process of saving each register to the stack is not necessary.

  Subsequent to step S100, the main control program performs timer subtraction processing (step S102). In this timer subtraction process, for example, the time during which the upper special symbol display 1185 and the lower special symbol display 1186 are turned on in accordance with the variable display pattern determined in the special symbol and special electric accessory control processing described later, In addition to the time that the normal symbol display 1189 is turned on in accordance with the normal symbol variation display pattern determined in the normal electric accessory control process, the payout control substrate 4110 is normal for various commands transmitted by the main control board 4100 (main control MPU 4100a). When it is determined whether or not a payer ACK signal indicating that it has been received is input, time management such as an ACK signal input determination time set as a determination condition is performed. Specifically, when the fluctuation time of the fluctuation display pattern or the normal symbol fluctuation display pattern is 5 seconds, the timer interruption period is set to 4 ms. Therefore, every time this timer subtraction process is performed, the fluctuation time is subtracted by 4 ms. When the subtraction result is 0, the fluctuation time of the fluctuation display pattern or the normal symbol fluctuation display pattern is accurately measured.

  In this embodiment, the ACK signal input determination time is set to 100 ms. Each time this timer subtraction process is performed, the ACK signal input determination time is subtracted by 4 ms, and the subtraction result becomes 0, thereby accurately measuring the ACK signal input determination time. The various times and the ACK signal input determination time are stored as time management information in the time management information storage area of the main control built-in RAM.

  Subsequent to step S102, the main control program performs switch input processing (step S104). In this switch input process, various signals input to input terminals of various input ports of the main control MPU 4100a are read and stored as input information in an input information storage area of the main control built-in RAM. Specifically, this main control program is, for example, a detection signal from the general winning opening switch 3020, 3020 shown in FIG. 14 for detecting a game ball that has entered the general winning opening 2104, 2201 shown in FIG. A detection signal from the count switch 2110 shown in FIG. 14 for detecting a game ball that has entered the grand prize opening 2103 shown in FIG. 8, and a game ball that has entered the first start port 2101 shown in FIG. 8 are detected. The detection signal from the first start port switch 3022 shown in FIG. 14, the detection signal from the second start port switch 2109 shown in FIG. 14 for detecting the game ball that has entered the second start port 2102 shown in FIG. 8, a detection signal from the gate switch 2352 shown in FIG. 14 that detects the game ball that has passed through the gate portion 2150 shown in FIG. 8, and a magnetism that detects fraud using the magnet shown in FIG. A payer ACK signal from the payout control board 4110 for indicating that the payout control board 4110 shown in FIG. 14 has normally received a detection signal from the payout switch 3024 and a prize ball command transmitted in a prize ball control process described later Each is read and stored as input information in the input information storage area. In addition, a detection signal from a first start port switch 3022 that detects a game ball that has entered the first start port 2101, a detection from a second start port switch 2109 that detects a game ball that has entered the second start port 2102 When each signal is read, the corresponding start port winning command shown in FIG. 46 corresponding to this is stored as transmission information in the transmission information storage area described above. That is, when there is a detection signal from the first start port switch 3022, a corresponding start port winning command is stored in the transmission information storage area as transmission information, and there is a detection signal from the second start port switch 2109. The start opening winning command corresponding to this is stored as transmission information in the transmission information storage area.

  In the present embodiment, the detection signal from the general winning opening switches 3020 and 3020 for detecting the game balls that have entered the general winning opening 2104 and 2201, and the count switch 2110 for detecting the gaming balls that have entered the large winning opening 2103 are shown. , A detection signal from the first start port switch 3022 that detects a game ball that has entered the first start port 2101, and a second start port switch 2109 that detects a game ball that has entered the second start port 2102 , And the detection signal from the gate switch 2352 that detects the game ball that has passed through the gate portion 2150 are first read as the first time when the switch input process is started, for a predetermined time (for example, 10 μs). ) After the passage, each is read again as the second time. Then, the result read at the second time is compared with the result read at the first time. It is determined whether there is a comparison result among the comparison results. Those that are not the same result are read again as the third time, and the result read at the third time is compared with the result read at the second time. It is determined again whether there is a comparison result among the comparison results. Those that are not the same result are read again as the fourth time, and the result read at the fourth time is compared with the result read at the third time. It is determined again whether there is a comparison result among the comparison results. Those with the same result are treated as having no game balls.

  Thus, in the switch input process, the main control program receives the detection signals from the general winning award port switches 3020 and 3020, the count switch 2110, the first start port switch 3022, the second start port switch 2109, and the gate switch 2352. Due to the influence of chattering, noise, etc., by reading twice, a total of two times of reading, which is compared twice for the first to third times, and twice for comparing the second time to the fourth time. Since erroneous detection can be avoided, detection signals from the general winning award port switches 3020 and 3020, the count switch 2110, the first start port switch 3022, the second start port switch 2109, and the gate switch 2352 are displayed. Reliability can be increased.

  Subsequent to step S104, the main control program performs a winning random number update process (step S106). In this winning random number update process, the big hit symbol random number and the small hit symbol random number described above are updated. Further, in addition to these random numbers, a big hit symbol initial value determination random number that is updated in the non-winning random number update process in step S56 in the main control side power-on process (main control side main process) shown in FIG. And the random number for determining the initial value for the small hit symbol is also updated. The random value for determining the initial value for the big hit symbol and the random number for determining the initial value for the small hit symbol are updated in the main control side main process and the main control side timer interrupt process, respectively, thereby improving the randomness. . On the other hand, since the big hit symbol random number and the small hit symbol random number are random numbers related to the winning determination (big hit determination), each counter is incremented only when the winning random number update process is performed. Note that the above-described random numbers for normal symbol determination and random numbers for determining the initial value for normal symbol determination are also updated by this winning random number update process.

  For example, as described above, the counter that updates the random number for normal symbol determination is an initial value update type counter, and is updated within a predetermined fixed numerical value range from the minimum value to the maximum value. To the maximum value, the value is incremented by adding 1 each time the main control timer interrupt process is performed. The random number for determining the initial value for determination per normal symbol is counted up toward the maximum value, and then the random number for determining the initial value for determination per normal symbol is counted up from the minimum value. When the counter finishes counting up the range from the minimum value to the maximum value of the random number for normal symbol determination, the random number for initial value determination for big hit determination is updated by this winning random number update processing. The random value for determining the initial value for normal symbol determination can be obtained by executing an initial value lottery process for drawing one value from the fixed numerical range of the counter for updating the random number for determination per normal symbol. .

  In the present embodiment, the big hit symbol initial value determining random number and the small hit symbol initial value determining random number are set in step S56 in the main control side power-on processing (main control side main processing) shown in FIG. The winning random number update process and the winning random number update process in step S106 in the main control timer interrupt process, which is this routine, are updated respectively. However, each time an interrupt timer is generated, the processing time of this routine becomes uneven. If the number of executions of the non-winning random number update process in step S56 is random by repeatedly executing the main process on the main control side within the remaining time until the interrupt timer is generated, a random number for determining the initial value for the big hit symbol , And the random number for determining the initial value for the small hit symbol may be updated only in the non-winning random number update process in step S56.

  Subsequent to step S106, the main control program performs prize ball control processing (step S108). In this prize ball control process, the prize information shown in FIG. 44 for reading out the input information from the above-mentioned input information storage area and paying out the game ball based on this input information is created, The self-check command shown in FIG. 44 for confirming the connection state between the board and the payout control board 4110 is created. Then, the created prize ball command and self-check command are transmitted to the payout control board 4110 as main payout serial data. For example, when one game ball enters the big prize opening 2103 shown in FIG. 8, a prize ball command for paying out 15 balls as a prize ball is created, and the number of game balls to be paid out as a prize ball Is set to 10 balls, the main prize ball number information output signal output is set in order to notify that, and is stored in the output information storage area as output information, and a prize ball command is transmitted to the payout control board 4110. If the payer ACK signal notifying that the payout control board 4110 has successfully received the prize ball command is not input within a predetermined time, the connection state between the main control board 4100 and the payout control board 4110 is confirmed. A self-check command to be generated is transmitted to the payout control board 4110.

  In the prize ball control process in step S108, when the input information is read from the above-described input information storage area and the number of game balls scheduled to be paid out as a prize ball reaches 10 based on this input information. In order to notify that, the main prize ball number information output command classified into others shown in FIG. 46 is created and stored as transmission information in the transmission information storage area. The main prize ball number information output command is created based on the value of the main prize ball number information output determination counter. The value of the main prize ball number information output determination counter is obtained by reading the input information from the input information storage area described above and based on this input information, that is, the first start port 2101 and the second start port provided in the game board 4. The number of game balls to be paid out as a prize ball is counted based on the game balls that have entered the various prize openings such as 2102, the general prize opening 2104, 2201, and the big prize opening 2103, and step S108. In the award ball control processing, the award ball schedule information storage area of the main control built-in RAM is stored and updated. In the prize ball control process of step S108, the value of the main prize ball number information output determination counter stored in the prize ball schedule information storage area of the main control built-in RAM is read, and the read main prize ball number information output determination counter is read. The input information is read from the input information storage area described above, and the number of game balls to be paid out as a prize ball is added based on this input information, and the value indicating the added number is 10 When the number of game balls is over (that is, when the number of game balls scheduled to be paid out as prize balls has reached 10), a main prize ball number information output command is created to inform the fact, and as transmission information The award ball schedule information storage area of the main control built-in RAM described above is stored in the output information storage area, and the value indicating the number of balls exceeding the value is used as the main prize ball number information output determination counter value. It is adapted to store update.

  Subsequent to step S108, the main control program performs a frame command reception process (step S110). In the payout control board 4110, the payout control program executes various commands of 1 byte (8 bits) classified into the status display shown in FIG. Send. On the other hand, as described later, the payout control program outputs an error cancellation navigation command based on the detection signal of the operation switch 860a. In the frame command reception process described above, when the main control program normally receives the various commands as payer serial data, information that informs the payout control board 4110 to that effect is stored as output information in the main control built-in RAM. Store in the area. In addition, the main control program reformats the command received normally as the payer serial data into a 2-byte (16-bit) command (various commands (frame status 1 command, error release classified into the status display in FIG. 46). The navigation command and the frame state 2 command))) are stored in the transmission information storage area described above as transmission information.

  Subsequent to step S110, the main control program performs a fraud detection process (step S112). In this fraud detection process, the abnormal state related to the prize ball is confirmed. For example, when the input information is read from the above-described input information storage area and the detection signal from the count switch 2110 is input when the game state is not a big hit game state (when a game ball enters the big prize opening 2103), etc. Then, a winning abnormality display command classified into the notification display shown in FIG. 46 as an abnormal state is created, and stored as transmission information in the transmission information storage area described above.

  Subsequent to step S112, the main control program performs a special symbol and special electric accessory control process (step S114). In this special symbol and special electric accessory control processing, a latch signal is output to the main random number circuit 4100an with built-in main control shown in FIG. 14, and the random number extracted by the main random number circuit 4100an with main control when the latch signal is input. (Random number value) is acquired from a hard random number latch register incorporated in main control built-in main control MPU 4100a, and the obtained random number value is set as a big hit determination random number. Whether or not the jackpot determination random number (that is, the random number value acquired from the hard random number latch register built in the main control built-in main control MPU 4100a) matches the jackpot determination value stored in advance in the main control built-in ROM. (Determining whether or not to generate a big hit gaming state (referred to as “special lottery”)) or taking out the value of the counter for updating the big hit symbol random number and pre-stored in the main control built-in ROM It is determined whether or not it matches with the probability variation determination value (determination of whether or not to generate a probability fluctuation). Here, “probability fluctuation” means that the probability of a big hit changes to a high probability (at the time of probability change) set higher than that at the normal time (low probability). In the present embodiment, the value 32668 to the value 32767 are set in the low probability as the range of the big hit determination value (big hit determination range) described above, and read from the normal determination table, whereas the value 31768 in the high probability. ˜value 32767 is set and read from the probability variation determination table. As described above, in the special symbol and special electric accessory control process in step S114, the big hit determination random number (that is, the random number value acquired from the hard random number latch register incorporated in the main control built-in main control MPU 4100a) and the built-in main control. When determining whether or not the jackpot determination value stored in advance in the ROM matches, the jackpot determination random number (that is, the random value acquired from the hard random number latch register built in the main control built-in main control MPU 4100a) Is determined by whether or not is included in the big hit determination range.

  When these determination results are based on the first start port switch 3022, various commands related to the special figure 1 synchronization effect shown in FIG. 45 are created, while the lottery results are based on the second start port switch 2109. In some cases, various commands related to the special figure 2 tuning effect shown in FIG. 45 are created and stored in the transmission information storage area as transmission information, and the upper special symbol display 1185 is set in accordance with the determined variation display pattern of the special symbol. Alternatively, the output of the lighting signal to the upper special symbol display 1185 or the lower special symbol display 1186 is set so that the lower special symbol display 1186 is lit, and the output information is stored in the output information storage area described above. In addition, depending on the game state to be generated, for example, when the game state is a big hit game state, various commands (big hit opening command, big prize opening 1 open Nth display command, big prize place 1 shown in FIG. Closing display command, winning prize 1 count display command, jackpot ending command, and jackpot symbol display command) are created and stored in the transmission information storage area as transmission information, or the opening / closing member 2107 shown in FIG. 8 is opened / closed. When the output of the drive signal to the attacker solenoid 2108 is set and stored in the output information storage area as output information, or when the number of times (round) when the special winning opening 2103 is opened from the closed state is two times, 2 to turn on the two-round indicator lamp 1190a of the round indicator 1190 shown in FIG. When the output of the lighting signal to the wind display lamp 1190a is set and stored in the output information storage area as output information, or when the round is 15 times, the 15 round display lamp 1190b of the round indicator 1190 shown in FIG. The lighting signal output to the 15-round display lamp 1190b is set so as to be lit, and stored as output information in the output information storage area, or to the gaming state display 1183 so that the presence / absence of probability variation is lit in a predetermined color The output of the lighting signal is set and stored as output information in the output information storage area.

  Subsequent to step S114, the main control program performs a normal symbol and normal electric accessory control process (step S116). In the normal symbol and normal electric accessory control process, the input information is read from the above-described input information storage area, and the gate winning process is performed based on the input information. In this gate winning process, it is determined from the input information whether the detection signal from the gate switch 2352 has been input to the input terminal. Based on this determination result, when a detection signal is input to the input terminal, the gate information storage area of the main control built-in RAM is extracted as gate information by extracting the counter value etc. for updating the random number for determination per normal symbol described above To remember.

  This gate information storage area is provided with 0th partition to 3rd partition (four partitions), and gate information is stored in the order of 0th partition, 1st partition, 2nd partition, and 3rd partition. It is like that. For example, when gate information is stored in the 0th to 2nd sections of the gate information storage, when the detection signal from the gate switch 2352 is input to the input terminal, the gate information is stored in the third section of the gate information storage. To do.

  The gate information stored in the 0th section of the gate information storage is set in the work area of the main control built-in RAM. When this gate information is set, the gate information of the first section of the gate information storage is in the 0th section of the gate information storage, the gate information of the second section of the gate information storage is in the first section of the gate information storage, The gate information of the third section of the information storage is shifted to the second section of the gate information storage, respectively, and the third section of the gate information storage becomes an empty area. For example, when gate information is stored in the first partition to the second partition of the gate information storage, the gate information of the first partition of the gate information storage is stored in the 0th partition of the gate information storage. The gate information of the two sections is shifted to the first section of the gate information storage, and the second section of the gate information storage and the third section of the gate information storage become empty areas. Here, when the gate information is stored in the first section to the third section of the gate information storage, the above-described gate information is turned on so that the normal symbol storage display 1188 is turned on using the total number of stored gate information as a holding ball. Based on the above, the output of the lighting signal of the normal symbol storage display 1188 is set and stored as output information in the output information storage area described above.

  Following the gate winning process, the gate information set in the work area of the main control built-in RAM is read out, and the normal design random number is extracted from the read gate information and stored in the main control built-in ROM in advance. It is determined whether or not it matches the determination value per normal symbol (referred to as “normal lottery”). Whether or not the movable piece 2106 is opened / closed is determined based on the determination result (the lottery result of the normal lottery). When the opening / closing operation is performed by this determination, the movable piece 2106 is moved from the advanced position to the retracted position, so that a game state in which a game ball can be received at the second start port 2102 is obtained. It will be an advantageous gaming state. The variable display pattern of the normal symbol corresponding to this determination is determined based on the random number for the normal symbol variable display pattern described above, and various commands classified as related to the common symbol synchronization effect shown in FIG. 45 are created and transmitted as transmission information. The output of the lighting signal to the normal symbol display 1189 is set so that the normal symbol display 1189 is turned on in accordance with the determined normal symbol variation display pattern, and is stored in the transmission information storage area described above. Store in the output information storage area. Further, for example, when the extracted random number for normal symbol determination matches the normal symbol determination value stored in advance in the main control built-in ROM, various commands related to the ordinary electric character effect shown in FIG. Is generated and stored as transmission information in the transmission information storage area, and the output of the drive signal to the start port solenoid 2105 is set so as to open and close the movable piece 2106, and is stored as output information in the output information storage area described above. On the other hand, when the extracted random number for normal symbol determination does not match the normal symbol determination value stored in advance in the main control built-in ROM, the normal symbol based on the normal symbol variation display pattern random number described above is used. The variable display pattern is determined, and various commands that are classified as related to the common figure synchronization effect shown in FIG. 45 are created and described above as the transmission information. The lighting information is stored in the signal information storage area, and the output of the lighting signal to the normal symbol display 1189 is set so that the normal symbol display 1189 is turned on according to the determined normal symbol variation display pattern. Store in the area.

  Subsequent to step S116, the main control program performs port output processing (step S118). In this port output processing, output information is read from the output information storage area described above from the output terminals of the various output ports of the main control MPU 4100a, and various signals are output based on the output information. This main control program, for example, outputs a main payout ACK signal when the various commands from the payout control board 4110 are normally received from the output terminal of a predetermined output port of the main control MPU 4100a based on the output information. Or a drive signal to the starter solenoid 2105 for opening / closing the movable piece 2106, or a drive signal for the opening / closing member 2107 of the winning prize opening 2103. 15 round jackpot information output signal, 2 round jackpot information output signal, probability changing information output signal, special symbol display information output signal, normal symbol display information output signal, short and medium time information output signal, start Pay various information (game information) signals related to the game, such as the winning prize information output signal And outputs to the control board 4110.

  Subsequent to step S118, the main control program performs peripheral control board command transmission processing (step S120). In the peripheral control board command transmission process, the main control program reads the transmission information from the transmission information storage area described above and transmits the transmission information to the peripheral control board 4140 as main peripheral serial data. The transmission information includes various commands created in the main control side timer interruption process which is this routine and shown in FIG. Various commands classified into commands and jackpot relations (for example, when a game ball that has entered the big winning opening 2103 (see FIG. 8) is detected, the big winning is based on the detection signal from the count switch 2110 (see FIG. 14). 46, winning command 1 count display command corresponding to mouth count command), various commands classified into power-on, various commands related to ordinary drawing synchronization effects, various commands classified into ordinary electric role effects, FIG. , Various commands classified into notification display, various commands classified into status display, various commands classified into test-related, and various types classified into other Mand (for example, a prize ball based on game balls in which the main control board 4100 has entered various winning ports such as the first starting port 2101, the second starting port 2102, the general winning ports 2104, 2201, and the big winning port 2103) Main prize for instructing the hall computer to transmit the main prize ball number information output signal via the external terminal board 784, every time the number of game balls to be paid out reaches ten, the main prize ball number information is used. Ball number information output command, etc.) are stored. The main serial data consists of 3 bytes per packet. Specifically, the main peripheral serial data includes a status indicating a type of command having a storage capacity of 1 byte (8 bits), a mode indicating a production variation having a storage capacity of 1 byte (8 bits), and a status. And a sum value obtained by calculating the sum with the mode regarded as a numerical value, and this sum value is created at the time of transmission.

  In this peripheral control board command transmission processing, the main control program transmits various commands as main peripheral serial data to the peripheral control board 4140 in the order of status, mode, and sum value. As described above, the charge charged in the electrolytic capacitor MC2 shown in FIG. 24 is applied to the VDD terminal, which is the power supply terminal of the main control MPU 4100a, as +5 V when a power failure or a momentary power failure occurs. Therefore, the main peripheral serial transmission port 4100ae incorporated in the main control MPU 4100a shown in FIG. 26 shifts at least the command set by the main control CPU core 4100aa in the transmission buffer register 4100aeb by the serial management unit 4100aec. The data can be transferred to the register 41aea and transmitted from the transmission shift register 4100aea as the main serial data. When the power to the pachinko machine 1 is turned on, or when power is restored after a power failure or a momentary power failure occurs after the power is turned on, In the reservation setting of the command to be transmitted, the power-on state command, the power-on main control return destination command, and the power-on main prize ball shown in FIG. Since the counter notification command for the number information output determination is created and stored as transmission information in the transmission information storage area of the main control built-in RAM, the status, mode, Then, it is sent to the peripheral control board 4140 in the order of the sum value, and then the status, mode, Are sent to the peripheral control board 4140 in the order of the sum value, and then the main prize ball number information output determination counter notification command at the time of power-on is configured. Send. In the transmission information storage area of the main control built-in RAM, various information is read from the game backup information in accordance with the various information in the setting of the work area of the main control built-in RAM in step S34 in the main control side power-on process. Various commands may be stored. In such a case, first after completion of transmission of various commands according to game information among various information, then power-on status command, power-on main control return destination command, and power-on main prize ball number information An output determination counter notification command is transmitted.

  Subsequent to step S120, the main control program clears the main control built-in WDT 4100af shown in FIG. 14 (step S122), and ends this routine. The main control built-in WDT 4100af in step S22 is cleared by setting a timer clear setting value in a WDT clear register built in the main control MPU 4100a. Thereby, the time count by the main control built-in WDT 4100af is cleared. Then, the timing by the main control built-in WDT 4100af is started again, so that the main control MPU 4100a is not forcedly reset by the main control built-in WDT 4100af.

  As described above, the main control board 4100 stores the game information according to the progress of the game before the power to the pachinko gaming machine 1 is cut off during the progress of the game. The power supply to the pachinko gaming machine 1 can be completed based on the game information on which the backup process was executed as a return destination of the game progress by the main control board 4100 at the time of power recovery. When the power is turned off, the power-on main control return destination command in FIG. 45 for instructing the driving state of the start port solenoid 2105 and the attacker solenoid 2108 which are electrical drive sources by the port output processing of step S118 in this routine is peripherally controlled. It is possible to output to the substrate 4140. That is, the main control board 4100 sets the main control side RAM in step S34 in the main control side power-on process of FIG. 49 in the reservation setting of the command transmitted when the power is turned on. Based on the power recovery information set in the work area of the control built-in RAM, the power-on status command classified as power-on in FIG. A control return destination command and a power-on main prize ball number information output determination counter notification command are created and stored as transmission information in the transmission information storage area of the main control built-in RAM, and the peripheral control board command in step S120 in this routine In the transmission process, as the main peripheral serial data, the status, mode , And are transmitted to the peripheral control board 4140 in the order of the sum value, and then transmitted to the peripheral control board 4140 in the order of the status, mode, and sum value constituting the main control return destination command when the power is turned on. It transmits to the peripheral control board 4140 in the order of status, mode, and thumb value, which constitutes the counter notification command for determining the main prize ball number information output at the time of insertion. For this reason, the peripheral control board 4140 determines the return destination of the progress of the game by the main control board 4100 at the time of power recovery based on the power-on main control return destination command from the main control board 4100. It is possible to display effects in the display area. As a result, when a player is playing a game, when a momentary power failure or power failure occurs, and when power is restored thereafter, the game state immediately before the power failure or power failure is restored immediately after power recovery. In addition, the return destination of the progress of the game by the main control board 4100 can be displayed and notified in the display area of the game board side effect display unit 1900, so that the system of the pachinko gaming machine 1 is gathered, so-called It is possible to prevent a player from being mistaken for a broken state that appears frozen. Therefore, it is possible to prevent the player from misunderstanding that the player has failed by quickly returning to the gaming state immediately before the momentary power failure or power failure after power recovery.

  In the main control board inspection process, which is an inspection process for the production line of the main control board 4100, when the main control board 4100 is first turned on after being manufactured for inspection, as described above, as shown in FIG. In step S38 in the main control side power-on process, the entire area of the main control built-in RAM is necessarily cleared. Thereby, in the reservation setting of the command to be transmitted at power-on in step S50 in the process, when the reservation setting of the command to be transmitted at power-on is performed, the power-on state command classified into power-on shown in FIG. When the power is turned on, a main control return destination command at power-on and a main notification ball count information output judgment counter notification command at power-on are created and stored as transmission information in the transmission information storage area of the main control built-in RAM. A state in which only three commands are stored as transmission information in the transmission information storage area of the main control built-in RAM: a status command, a main control return destination command when the power is turned on, and a counter notification command for determining the output of the main prize ball number information when the power is turned on In the peripheral control board command transmission process in step S120 in this routine, Status that constitutes a power-on state command as serial data, which is sent to the inspection device in the main control board inspection process in the order of status, mode, and sum value, and then constitutes a main control return destination command at power-on , Mode, and sum value are sent to the main control board inspection process inspection device, and then the main prize ball number information output judgment counter notification command is configured when the power is turned on. Status, mode, and sum value order Is transmitted to the inspection device of the main control board inspection process. Based on the information indicating the model code of the pachinko gaming machine included in the power-on state command received from the main control board 4100, that is, the information indicating the model code of the pachinko gaming machine, The series code for specifying which type of the above-described Max type, middle type, and sweet digital type, and the copyright code for specifying the copyright of the work, Game specifications (for example, a game specification in which if a probability change occurs, the state will continue until the next jackpot game state occurs, and a probability specification will occur with a limited number of special symbol changes. (ST machine) etc.), and detailed model information is displayed on the inspection monitor of the main control board inspection process based on the game specification code It has become way.

[17. Various control processing of payout control board]
Next, various control processes performed by the payout control board 4110 shown in FIG. 15 will be described with reference to FIGS. FIG. 51 is a flowchart showing an example of processing when the payout control unit is turned on. FIG. 52 is a flowchart showing a continuation of processing when the payout control unit is turned on in FIG. 51. FIG. 53 is a payout control unit following FIG. FIG. 54 is a flowchart showing an example of a payout control unit timer interruption process, FIG. 55 is a flowchart showing an example of a rotation angle switch history creation process, and FIG. 56 is a sprocket. 57 is a flowchart showing an example of the fixed position determination skip process, FIG. 57 is a flowchart showing an example of a ball spot determination process, and FIG. 58 is a flowchart showing an example of a prize ball stock number addition process for a prize ball. 59 is a flow chart showing an example of the winning ball stock number addition process, and FIG. 60 shows an example of the stock monitoring process. 61 is a flowchart showing an example of the payout ball movement determination setting process, FIG. 62 is a flowchart showing an example of the payout setting process, and FIG. 63 is an example of the ball movement setting process. 64 is a flowchart illustrating an example of a retry operation monitoring process, FIG. 65 is a flowchart illustrating an example of a mismatch counter reset determination process, and FIG. 66 is a flowchart illustrating an example of an error release operation determination process. FIG. 67 is a timing chart showing signal processing (A) and input signal confirmation processing (A) from the CR unit at the time of payout operation by ball lending.

  First, payout control unit power-on processing will be described, then payout control unit timer interruption processing, rotation angle switch history creation processing, sprocket fixed position determination skip processing, ball corner determination processing, prize ball stock number addition for prize ball Processing, winning ball stock count addition processing, stock monitoring processing, payout ball binding operation determination setting processing, payout setting processing, ball binding operation setting processing, retry operation monitoring processing, inconsistency counter reset determination processing, error cancellation The operation determination process will be described. In addition, rotation angle switch history creation processing, sprocket fixed position determination skip processing, ball curl determination processing, prize ball award ball stock number addition processing, rental ball award ball stock number addition processing, stock monitoring processing, payout ball fringe The operation determination setting process, the retry operation monitoring process, the inconsistency counter reset determination process, and the error release operation determination process are performed as one process of the main operation setting process in step S562 in the payout control unit power-on process described later. Switch history creation processing, sprocket fixed position determination skip processing, ball edge determination processing, retry operation monitoring processing, inconsistency counter reset determination processing, error release operation determination processing, prize ball prize ball number addition processing, ball rental award Priorities are set in the order of the ball stock count addition processing, stock monitoring processing, and payout ball engagement motion determination setting processing. .

[17-1. Discharge control unit power-on processing]
When the pachinko gaming machine 1 is turned on, the payout control unit 4120 in the payout control board 4110 has a payout control program as shown in FIGS. 51 to 53 under the control of the payout control MPU 4120a. Process at the time of input. When the payout control unit power-on process is started, the payout control program sets the interrupt mode in the payout control MPU 4120a (step S500). This interrupt mode is for setting the priority order of interrupts of the payout control MPU 4120a. In this embodiment, a payout control unit timer interrupt process, which will be described later, is set as the highest priority, and when an interrupt of this payout control unit timer interrupt process occurs, the process is preferentially performed.

  Subsequent to step S500, the payout control program performs input / output setting (I / O input / output setting) (step S502). In this I / O input / output setting, various input ports and various output ports of the payout control MPU 4120a are set.

  Subsequent to step S502, the payout control program performs wait timer process 1 (step S506), and determines whether or not a power failure warning signal is input (step S508). The voltage does not increase immediately from when the power is turned on until the voltage reaches the predetermined voltage. On the other hand, when a power failure or a momentary power failure (a phenomenon in which the supply of power is temporarily stopped) occurs, the voltage drops and becomes smaller than the power failure warning voltage. A warning signal (paid outage warning signal) is input. Similarly, when the voltage becomes lower than the power failure warning voltage from when the power is turned on until it reaches the predetermined voltage, a power failure warning signal (paid power failure warning signal) is input from the power failure monitoring circuit 4100e of the main control board 4100. Therefore, the wait timer process 1 in step S506 is a process for waiting until the voltage becomes higher than the power failure warning voltage and stabilizes after the power is turned on. In this embodiment, the wait timer process 1 is 200 milliseconds (wait timer). ms) is set. The determination in step S508 is performed based on a power failure warning signal (paid power failure warning signal) from the power failure monitoring circuit 4100e of the main control board 4100.

  Subsequent to step S508, the payout control program determines whether or not the operation switch 860a is operated (step S512). This determination is based on the logical value of the operation signal from the operation switch 860a, and when the logical value of the operation signal from the operation switch 860a is HI, it is determined that the RAM clear is not instructed. When it is determined that the operation switch 860a is not operated, the operation switch 860a is operated by determining that the RAM clear is instructed when the logical value of the operation signal from the operation switch 860a is LOW. judge.

  When the operation switch 860a is operated in step S512, the payout control program sets a value 1 to the payout RAM clear notification flag HRCL-FLG (step S514). That is, the payout control program can execute a RAM clear process for initializing a RAM (hereinafter referred to as “payout control built-in RAM”) built in the payout control MPU 4120a for a predetermined time from when the power is turned on. State. On the other hand, when the operation switch 860a is not operated in step S512, the payout control program sets a value 0 to the payout RAM clear notification flag HRCL-FLG (step S516). This payout RAM clear notification flag HRCL-FLG is stored in the payout control built-in RAM (payout storage unit) of the payout control MPU 4120a, for example, various flags, various information stored in various information storage areas, etc. (for example, The prize ball stock number PBS, real ball count PB, drive command number DRV, inconsistency counter INCC, etc. stored in the prize ball information storage area, and the logic of the PRDY signal stored in the CR communication information storage area Flag indicating whether or not the payout information related to payout of the set status (PRDY signal output setting information, etc.) is to be erased, and is set to a value of 1 when the payout information is erased and a value of 0 when the payout information is not erased. Is done. The payout RAM clear notification flag HRCL-FLG set in steps S514 and S516 is stored in a general-purpose storage element (general-purpose register) of the payout control MPU 4120a.

  Subsequent to step S514 or step S516, the payout control program performs setting for permitting access to the payout control built-in RAM (step S518). With this setting, the payout control built-in RAM can be accessed, and for example, payout information can be written (stored) or read out.

  Subsequent to step S518, the payout control program sets the stack pointer (step S520). The stack pointer indicates, for example, the address accumulated on the stack to temporarily store the contents of the memory element (register) being used, or temporarily returns the return address of this routine when returning to this routine after completing the subroutine. It indicates the address that has been stacked on the stack for storage, and the stack pointer advances each time the stack is stacked. In step S520, an initial address is set in the stack pointer, and the contents of the register, the return address, etc. are stacked on the stack from this initial address. Then, the stack pointer returns to the initial address by sequentially reading from the last stacked stack to the first stacked stack.

  Subsequent to step S520, the payout control program determines whether or not the payout RAM clear notification flag HRCL-FLG is 0 (step S522). As described above, the payout RAM clear notification flag HRCL-FLG is set to a value of 1 when the payout information is erased and to a value of 0 when the payout information is not erased.

  When the payout RAM clear notification flag HRCL-FLG is 0 in step S522, that is, when the payout information is not deleted, the payout control program calculates a checksum (step S524). This checksum calculates the sum by regarding the payout information stored in the payout control built-in RAM as a numerical value.

  Subsequent to step S524, the payout control program determines whether or not the calculated checksum value matches the checksum value stored in the payout control unit power-off process described later (at the time of power-off). (Step S526). If they match, the payout control program determines whether or not the payout backup flag HBK-FLG is 1 (step S528). This payout backup flag HBK-FLG is a flag indicating whether or not payout backup information such as payout information and checksum value is stored in the payout control built-in RAM in the payout control unit power-off process described later. A value of 1 is set when the control unit power-off process is normally terminated, and a value of 0 is set when the payout control unit power-off process is not normally terminated.

  When the payout backup flag HBK-FLG has a value of 1 in step S528, that is, when the payout control unit power-off process is normally terminated, the payout control program sets the work area of the payout control built-in RAM as power recovery. (Step S530). In this setting, in addition to the value 0 being set in the payout backup flag HBK-FLG, information at the time of power recovery is read from the ROM built in the payout control MPU 4120a (hereinafter referred to as “the payout control built-in ROM”). This power recovery information is set in the work area of the payout control built-in RAM. Accordingly, the above-mentioned payout backup information stored in the payout control built-in RAM, various flags, various information stored in various information storage areas, etc. (for example, prizes stored in the prize ball information storage area, PRDY signal output setting information in which the logic state of the PRDY signal stored in the CR communication information storage area, such as the ball stock number PBS, the real ball count PB, the drive command number DRV, the inconsistency counter INCC, and the like, Information used for various processes is set based on payout information relating to payout of inconsistency counter reset determination time (stored in the time management information storage area). Note that “recovery” includes not only a state in which the power is turned off from a state in which the power is turned off but also a state in which the power is restored after a power failure or a momentary power failure.

  On the other hand, when the payout RAM clear notification flag HRCL-FLG is not 0 (value 1) in step S522, that is, when the payout information is erased, or when the checksum values do not match in step S526, or step When the payout backup flag HBK-FLG is not a value 1 (value 0) in S528, that is, when the payout control unit power-off process is not normally terminated, the payout control program reads the entire area of the payout control built-in RAM. Clear (step S532). That is, the payout control program executes the payout control side RAM clear process triggered by the detection of the operation signal of the operation switch 860a. As a result, the payout backup information stored in the payout control built-in RAM is cleared.

  Subsequent to step S532, the payout control program sets the work area of the payout control built-in RAM as an initial setting (step S534). In this setting, the initial information is read from the payout control built-in ROM, and the initial information is set in the work area of the payout control built-in RAM.

  Subsequent to step S530 or step S534, the payout control program performs interrupt initialization (step S536). This setting is to set an interrupt cycle when a payout control unit timer interrupt process to be described later is performed. In this embodiment, it is set to 2 ms.

  Subsequent to step S536, the payout control program performs interrupt permission setting (step S538). With this setting, the payout control unit timer interrupt process is repeated every interrupt cycle set in step S536, that is, every 2 ms.

  Subsequent to step S538, the payout control program sets a value A in the watchdog timer clear register HWCL (step S539). The watchdog timer is cleared by setting the value A, the value B, and the value C in this watchdog timer clear register HWCL in order.

  Subsequent to step S539, the payout control program determines whether a power failure notice signal (payout power failure notice signal) has been input (step S540). As described above, when the power of the pachinko gaming machine 1 is cut off, or when a power failure or instantaneous power failure occurs, if the voltage falls below the power failure warning voltage, a power failure warning signal (paid power failure warning signal) is used as the power failure warning signal. 4100 is input from the power failure monitoring circuit 4100e. The determination in step S540 is made based on this power failure notice signal.

  When no power failure warning signal is input in step S540, the payout control program determines whether or not the 2 ms elapsed flag HT-FLG is a value 1 (step S542). This 2 ms elapsed flag HT-FLG is a flag for measuring 2 ms in a payout control unit timer interrupt process processed every 2 ms, which will be described later. Is set.

  When the 2 ms elapsed flag HT-FLG is 0 in step S542, that is, when 2 ms has not elapsed, the process returns to step S540, and the payout control program determines whether or not a power failure warning signal (paid power failure warning signal) has been input. Determine.

  On the other hand, when the 2 ms elapsed flag HT-FLG is 1 in step S542, that is, when 2 ms have elapsed, the payout control program sets the value 0 to the 2 ms elapsed flag HT-FLG (step S544).

  Subsequent to step S544, the payout control program sets a value B in the watchdog timer clear register HWCL (step S546). At this time, the value B is set in the watchdog timer clear register HWCL following the value A set in step S539.

  Subsequent to step S546, the payout control program performs port output processing (step S548). In this port output process, various information is read from the output information storage area of the payout control built-in RAM, and various signals are output from the output terminals of the various output ports of the payout control MPU 4120a based on the various information. In the output information storage area, for example, payer ACK information for notifying that various commands relating to payout from the main control board 4100 (award ball command and self-check command shown in FIG. 44) have been normally received, and a payout motor 744 are provided. Various information such as drive information for performing drive control, prize ball information on the number of balls actually paid out by the payout motor 744, LED display information displayed on the error LED display 860b, and the like are stored. When various commands relating to payout from the main control board 4100 are normally received from the output terminal of a predetermined output port of the payout control MPU 4120a based on the output information, a payer ACK signal is output to the main control board 4100, or a payout motor 744 outputs a drive signal, and the number of balls that the payout motor 744 actually pays out the game balls As a force signal, it is output to the external terminal board 784 (in this embodiment, every time the payout motor 744 actually pays out 10 game balls, a prize ball number information output signal is output to the external terminal board 784. Specifically, a prize ball number information output determination counter for determining whether or not to output prize ball number information is provided. The prize ball number information output determination counter is actually set by the payout motor 744. The number of game balls that have been paid out is counted based on the detection signal from the counting switch 751 shown in FIG. 15 in the port input processing in step S550 described later, and the game actually paid out by the payout motor 744. The award ball information storage area of the payout control built-in RAM is updated by a process (program) (not shown) for monitoring the number of balls. In a process (program) (not shown) for monitoring the number of game balls that have been paid out, the value of the prize ball number information output determination counter stored in the prize ball information storage area of the payout control built-in RAM is set to a step described later. In the port input process of S550, the number of game balls actually paid out by the payout motor 744 is added and updated based on the detection signal from the counting switch 751 shown in Fig. 15. In the port output process of step S548, When the value of the prize ball number information output determination counter is read from the prize ball information storage area and the value of the read prize ball number information output determination counter exceeds the value 10 (that is, the payout motor 744 is actually When the number of game balls paid out to 10 has reached 10), an award ball number information output signal is output to the external terminal board 784, and the number of balls exceeding the number Is stored and updated in the prize ball information storage area of the payout control built-in RAM described above as the value of the prize ball number information output determination counter. Or a display signal is output to the error LED display 860b.

  Subsequent to step S548, the payout control program performs port input processing (step S550). In this port input process, various signals input to input terminals of various input ports of the payout control MPU 4120a are read and stored as input information in an input information storage area of the payout control built-in RAM. For example, an operation signal of the operation switch 860a, a detection signal from the rotation angle switch 752, a detection signal from the counting switch 751, a detection signal from the full switch 550, a BRQ signal from the CR unit 6, a BRDY signal, and a CR connection signal, The main payment board ACK signal from the main control board 4100 that informs that the main control board 4100 has normally received various commands transmitted in the command transmission process described later is read and stored as input information in the input information storage area.

  Subsequent to step S550, the payout control program performs timer update processing (step S552). In this timer update process, when the determination is made as to whether or not a ball stagnation state has occurred due to the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted, the ball swatch determination set as the determination condition is performed. Time, skip determination time set when the fixed position determination of the payout rotating body is not performed, determination of whether or not the storage space of the foul cover unit 540 shown in FIG. Whether the number of game balls taken into the supply passage of the prize ball device 740 by the detection signal from the full ball determination switch 750, which is set as the determination condition when performing the game, is greater than or equal to a predetermined number In addition to performing time management such as the ball breakage judgment time set as the judgment condition when judging whether or not, the number of game balls delivered and received by the recess of the payout rotating body, and the actual When determining whether or not to reset the inconsistency counter INCC for monitoring whether or not the game balls that are not consistent with the number of balls detected by the count switch 751 are repeatedly paid out The management of the inconsistency counter reset determination time set with the determination condition is performed. For example, when the sphere collision determination time is set to 5005 ms, the timer interruption period is set to 2 ms. Therefore, every time this timer update process is performed, the sphere collision determination time is subtracted by 2 ms, and the subtraction result When the value becomes 0, the ball collision determination time is accurately measured.

  In this embodiment, the skip determination time is set to 22.75 ms, the full tank determination time is set to 504 ms, the ball breakage determination time is set to 119 ms, and the mismatch counter reset determination time is set to 7000 s (about 2 hours). Every time processing is performed, the full tank determination time, the ball breakage determination time, and the inconsistency counter reset determination time are subtracted by 2 ms, and the subtraction result becomes 0. Judgment time is accurately measured. These various determination times are stored as time management information in the time management information storage area of the payout control built-in RAM.

  Subsequent to step S552, the payout control program performs CR communication processing (step S554). In this CR communication processing, whether or not various signals (BRQ signal, BRDY signal, and CR connection signal) from the CR unit 6 are input based on the input information read from the input information storage area described above. Determine. Based on various signals from the CR unit 6, the payout control MPU 4120 a exchanges various signals with the CR unit 6. In the processing for setting the work area of the payout control built-in RAM in step S530, as described above, the payout backup information stored in the payout control internal RAM, various flags, and various information stored in the various information storage areas. (For example, the prize ball stock number PBS, the real ball count PB, the drive command number DRV, the inconsistency counter INCC, etc. stored in the prize ball information storage area, the PRDY stored in the CR communication information storage area, etc. Information to be used for various processes is set based on payout information relating to payout of PRDY signal output setting information or the like in which the logic state of the signal is set.

  By this process, for example, even if there is a momentary power failure or a power failure, values such as the prize ball stock number PBS, the real ball count PB, the drive command number DRV, and the inconsistency counter INCC at the time of power recovery are stored as payout backup information. The value of the award ball stock number PBS, the real ball count PB, the drive command number DRV, the inconsistency counter INCC, etc. immediately before the momentary power failure or power failure can be restored. As a result, when the game ball payout operation by the prize ball device 740 is being executed, even if the payout operation cannot be continued due to a momentary power failure or power failure, the payout operation should be continued at the time of power recovery. Therefore, the game balls can be paid out to the upper plate 301 and the lower plate 302 without excess or deficiency. In other words, in the CR communication process, the payout control MPU 4120a exchanges various signals with the CR unit 6 and, when paying out the game ball to the upper plate 301 or the lower plate 302, the payout control MPU4120a Even if the exchange of various signals with the unit 6 is interrupted and the payout of the game ball cannot be continued, the prize ball stock number PBS, the real ball count PB, the drive command number DRV, and the inconsistency counter INCC at the time of power recovery Etc. are restored to values such as the prize ball stock number PBS, the real ball count PB, the drive command number DRV, the inconsistency counter INCC, etc., which are stored as the payout backup information and immediately before the momentary power failure or power failure. Exchange of various signals between the pachinko gaming machine 1 (payout control MPU 4120a) and the CR unit 6 immediately before a momentary power failure or power failure And it is possible to continue from the time of power restoration, so that it is possible to continue to payout of game balls.

  As described above, the exchange of various signals between the pachinko gaming machine 1 (the payout control MPU 4120a) and the CR unit 6 is restored to the state immediately before the instantaneous power outage or stop at the time of power recovery even if the power outage stops or stops. Thus, various signals generated by the pachinko gaming machine 1 (payout control MPU 4120a) and the CR unit 6 are not changed by the influence of the instantaneous stop or stop. Therefore, the reliability of the exchange of various signals between the pachinko gaming machine 1 (payout control MPU 4120a) and the CR unit 6 can be enhanced.

  Various information stored in the CR communication information storage area is included in the payout backup information as described above. In the CR communication process, when power is restored, the PRDY signal output setting information is read from the CR communication information storage area stored in the payout control built-in RAM set in the process of setting the work area of the payout control built-in RAM in step S530. When the read PRDY signal output setting information is set to the logic state of the PRDY signal that indicates that the payout operation for paying out the rented ball is not possible, for example, the PRDY signal is paid out. The data is output to the CR unit 6 from the output terminal of the predetermined output port of the MPU 4120a. The value of the inconsistency counter INCC in the prize ball information storage area stored in the payout control built-in RAM, which is included in the payout backup information, for example, in the retry operation monitoring process performed as one process of the main action setting process Is determined whether the value of the mismatch counter INCC is smaller than the mismatch threshold INCTH. If the value of the mismatch counter INCC is not smaller than the mismatch threshold INCTH, the retry operation is abnormal. That is, it is determined that the game ball payout operation by the prize ball device 740 is in an abnormal state, the value 1 is set to the retry error flag RTERR-FLG, and the payout ball engagement operation determination setting process As an example of setting the error status output to the CR unit 6, for example, when not communicating with the CR unit 6 The logic state of the PRDY signal informing of dispensing operation is not possible (LOW) is set to PRDY signal output setting information stored in the CR communication information storage area for dispensing.

  Thereby, in the CR communication process, the logic state of this PRDY signal is read from the CR communication information storage area and the PRDY signal is output from the output terminal of the predetermined output port of the payout control MPU 4120a at the next timer interrupt from the power recovery. To the CR unit 6. Thus, for example, if the game ball payout operation by the prize ball device 740 is in an abnormal state immediately before the momentary stop, the state is restored at the time of power recovery. At an early stage, a PRDY signal notifying that a payout operation for paying out a ball cannot be performed can be output from the output terminal of a predetermined output port of the payout control MPU 4120a to the CR unit 6. It can be notified that the game ball payout operation by the prize ball device 740 is in an abnormal state. As a result, it is possible to prevent the BRDY, which is a useless lending request signal from the CR unit 6, from being output at an extremely early stage from the time of power recovery.

  In the CR communication process, when the CR connection signal is read from the input information storage area of the payout control built-in RAM and the logic is HI based on the CR connection signal in the port input process of step S550, that is, a pachinko game. When the machine 1 is powered on and when the payout control board 4110 and the CR unit 6 are electrically connected via the game ball lending device connection terminal plate 869, the payout of the ball is made. When the logic state of the PRDY signal is output to the CR unit 6 from the output terminal of the predetermined output port of the payout control MPU 4120a while the logic state of the PRDY signal is HI, In other words, when the pachinko gaming machine 1 is powered on, the payout control board 4110 and the CR unit 6 are used for lending devices such as game balls. When it is not electrically connected via the connecting terminal board 869, the logic state of the PRDY signal is set to LOW to notify that the payout operation for paying out the rented ball is impossible. Is output to the CR unit 6 from the output terminal of the output port. The logical state of the EXS signal that indicates that one payout operation has been started or ended is stored as EXS signal output setting information in the CR communication information storage area of the payout control built-in RAM, and the payout control board 4110 A CR connection signal that tells whether or not the CR unit 6 is electrically connected is stored in the state information storage area as CR connection information.

  Subsequent to step S554, the payout control program performs a full tank and ball break check process (step S556). In this full tank and out-of-ball check process, the input information is read from the above-mentioned input information storage area, and based on this input information, the accommodation space of the above-mentioned foul cover unit 540 is stored by the detection signal from the full tank switch 550. It is determined whether the game balls are full or the number of game balls taken into the supply path of the award ball device 740 is equal to or greater than a predetermined number based on a detection signal from the ball break switch 750. It is determined whether or not. For example, whether or not the storage space of the foul cover unit 540 is full with the game balls stored is determined by using the timer interruption period 2 ms and the full tank and full ball check processing at this time. The detection signal from 550 is ON, and when the detection signal from the full tank switch 550 is turned OFF in the last full (2 ms before) full ball and ball check check process, that is, the detection signal from the full tank switch 550 is ON from OFF. When the transition is made, the time for the full tank determination time (504 ms) described above is started in the timer update process in step S552. When the full tank determination time becomes 0 in the timer update process, that is, when the full tank determination time is reached, whether or not the detection signal from the full tank switch 550 is ON in this full tank and out-of-ball check process. Determine whether. In this determination, when the detection signal from the full tank switch 550 is ON, the above-mentioned state information memory stores the full tank information indicating that the storage space of the foul cover unit 540 is full with the stored game balls. Store in the area. On the other hand, when the detection signal from the full tank switch 550 is OFF, the full tank information indicating that the storage space of the foul cover unit 540 is not full with the stored game ball is stored in the state information storage area. .

  Whether or not the number of game balls taken into the supply path of the award ball apparatus 740 is equal to or greater than a predetermined number is also determined by using the timer interruption period 2 ms, When the detection signal from the ball break switch is ON, and when the detection signal from the ball break switch is turned OFF in the previous full (2 ms before) full ball and ball break check processing, that is, the detection signal from the ball break switch 750 is turned ON from OFF. When the transition is made, the timer update process in step S552 starts counting the ball breakage determination time (119 ms) described above. When the ball break determination time becomes 0 in the timer update process, that is, when the ball break determination time is reached, whether or not the detection signal from the ball break switch 750 is ON in the full tank and ball break check processing. Determine whether. In this determination, when the detection signal from the ball break switch 750 is ON, the ball break information indicating that the number of game balls taken into the supply passage of the prize ball device 740 is greater than or equal to a predetermined number is displayed. While the information is stored in the information storage area, when the detection signal from the ball break switch 750 is OFF, the ball break is transmitted to the effect that the number of game balls taken into the supply passage of the prize ball device 740 is not more than a predetermined number. Information is stored in the state information storage area.

  Subsequent to step S556, the payout control program performs a shot ball feed control circuit error check process (step S557). In this shot ball feed control circuit error check process, status information is obtained from the shot ball feed fault monitoring circuit 4120ah shown in FIG. 15 to determine whether or not a fault has occurred in the shot ball feed control circuit 4120ag. As described above, the firing ball feed failure monitoring circuit 4120ah determines whether or not a failure has occurred in the firing ball feed control circuit 4120ag that performs the launch control by the launch solenoid 654 and the ball feed control by the ball solenoid 585. Monitoring is performed, and the monitoring result (whether or not a defect occurs) can be stored and held as status information. The payout control program obtains status information from the launching ball sending defect monitoring circuit 4120ah to determine whether or not a trouble has occurred in the launching ball sending control circuit 4120ag. When the payout control program obtains the status information from the launching ball feed failure monitoring circuit 4120ah and determines that there is no malfunction in the launching ball feed control circuit 4120ag, the launching ball feed control circuit 4120ag performs the launch control of the game ball. In order to start, the launching operation permission is set for the launching ball feed control circuit 4120ag, and the launching operation permission information for notifying that the launching operation is permitted is stored in the state information storage area, while the launching ball feed control circuit 4120ag. When it is determined that a failure has occurred, the launching ball sending control circuit 4120ag is set to prohibit the launching operation in order to forcibly stop the launching control of the game ball by the launching ball feed control circuit 4120ag, and The launching operation prohibition information that indicates that the operation is prohibited is stored in the state information storage area.

  Subsequent to step S557, the payout control program performs command reception processing (step S558). In this command reception process, various commands related to payout from the main control board 4100 (award ball command and self-check command shown in FIG. 44) are received. When the various commands are normally received, the payer ACK information indicating that is stored in the output information storage area. On the other hand, when various commands cannot be received normally, a connection abnormality that indicates that an abnormality has occurred in the connection between the main control board 4100 and the payout control board 4110 (an abnormality has occurred in various command signals). Information is stored in the state information storage area described above.

  Subsequent to step S558, the payout control program performs command analysis processing (step S560). In this command analysis processing, the command received in step S558 is analyzed, and the analyzed command is stored as received command information in the received command information storage area of the payout control built-in RAM.

  Subsequent to step S560, the payout control program performs main operation setting processing (step S562). In this main operation setting process, operation settings such as winning balls, rental balls, ball removal and ball scoring are performed, retry operations are judged, and the number of unpaid balls (the number of winning ball stock) is monitored. To do.

  Subsequent to step S562, the payout control program performs LED display data creation processing (step S564). In this LED display data creation processing, various types of information are read from the state information storage area described above, display data to be displayed on the error LED indicator 860b of the payout control board 4110 is created, and LED display information is stored in the output information storage area described above. Remember. For example, when the above-mentioned ball piece information is read from the state information storage area and the number of game balls taken into the supply passage of the prize ball device 740 is not more than a predetermined number based on this piece of ball information, the corresponding display data (In this embodiment, a display value 1 (number “1”)) is created and LED display information is stored in the output information storage area.

  Subsequent to step S564, the payout control program performs command transmission processing (step S566). In this command transmission process, various types of information are read from the state information storage area described above, and various commands (frame state 1 command, error canceling navigation command, and frame state) classified into the state display shown in FIG. 47 based on the various types of information. 2 commands) is generated and transmitted to the main control board 4100. For example, when the out-of-ball information is read from the state information storage area, if the number of game balls taken into the supply passage of the prize ball device 740 is not equal to or greater than a predetermined number based on this out-of-ball information, a frame state 1 command is issued. When it is created and transmitted to the main control board 4100, or when the firing operation permission information is read from the state information storage area, a frame state 2 command (to notify that it is not a firing ball feed control circuit error) based on this firing operation permission information When the value 0 is set to B0 and transmitted to the main control board 4100 or when the firing operation prohibition information is read from the state information storage area, the frame state 2 command ( A value 1 is set in B0 in order to notify that it is a shot ball feed control circuit error.) Is generated and transmitted to the main control board 4100. Further, in this command transmission process, the payout control program has described that the payout RAM clear notification flag HRCL-FLG has a value of 1, that is, an operation signal corresponding to the operation of the operation switch 860a has been detected. Output error cancel navigation command.

  Subsequent to step S566, the payout control program sets a value C in the watchdog timer clear register HWCL (step S568). By setting the value C in the watchdog timer clear register HWCL in step S568, the value C is set in the watchdog timer clear register HWCL following the value B set in step S546. As a result, the value A, the value B, and the value C are sequentially set in the watchdog timer clear register HWCL, and the watchdog timer is cleared.

  Following step S568, the process returns to step S539 again, and the payout control program sets a value A to the watchdog timer clear register HWCL, and whether or not a power failure warning signal (paid power failure warning signal) is input in step S540. If this power failure warning signal (paid power failure warning signal) is not input, it is determined in step S542 whether or not the 2 ms elapsed flag HT-FLG has a value of 1, and the 2 ms elapsed flag HT-FLG has a value of 1. When 2 ms has elapsed, that is, when 2 ms has elapsed, the value 0 is set in the 2 ms elapsed flag HT-FLG in step S544, the value B is set in the watchdog timer clear register HWCL in step S546, and port output processing is performed in step S548 In step S550, port input processing is performed. In step S552, Immediate update processing is performed, CR communication processing is performed in step S554, full tank and out of ball check processing is performed in step S556, command reception processing is performed in step S558, command analysis processing is performed in step S560, and main processing is performed in step S562. Operation setting processing is performed, LED display data creation processing is performed in step S564, command transmission processing is performed in step S566, value C is set in watchdog timer clear register HWCL in step S568, and steps S539 to S568 are repeated. . The processing from step S539 to step S568 is referred to as “payout control unit main processing”.

  Depending on the progress of the game by the main control board 4100, the processing content of the payout control unit main process varies. For this reason, the time required for the processing of the payout control MPU 4120a varies. Accordingly, the payout control MPU 4120a preferentially outputs to the main control board 4100 a payer ACK signal notifying that various commands related to payout from the main control board 4100 have been normally received in the port output processing of step S548. Yes. As a result, the payout control MPU 4120a ensures the processing time so that other fluctuating processes can be sufficiently performed.

  On the other hand, when a power failure warning signal (paid power failure warning signal) is input in step S540, interrupt prohibition setting is performed (step S570). With this setting, the payout control unit timer interrupt processing described later is not performed, writing to the payout control built-in RAM is prevented, and rewriting of the payout information described above is protected.

  Subsequent to step S570, the payout control program stops outputting the drive signal to the payout motor 744 (step S574). Thereby, payout of the game ball is stopped.

  Subsequent to step S574, the payout control program performs clear setting of the watchdog timer (step S576). As described above, the clear setting is performed by sequentially setting the value A, the value B, and the value C in the watchdog timer clear register HWCL.

  Subsequent to step S576, the payout control program calculates a checksum and stores the calculated value (step S578). The checksum is calculated by regarding the payout information in the work area of the payout control built-in RAM as a numerical value excluding the storage area for the checksum value calculated in step S524 and the payout backup flag HBK-FLG.

  Subsequent to step S578, the payout control program sets a value 1 to the payout backup flag HBK-FLG (step S580). Thereby, storage of the payout backup information is completed.

  Subsequent to step S580, the payout control program performs prohibition of access to the payout control built-in RAM (step S582). With this setting, access to the payout control built-in RAM is prohibited and writing and reading cannot be performed, and payout backup information stored in the payout control internal RAM is protected.

  Following step S582, the payout control program enters an infinite loop. In this infinite loop, the value A, the value B, and the value C are not set in this order in the watchdog timer clear register HWCL, so that the watchdog timer is not cleared. Therefore, the payout control MPU 4120a is reset, and thereafter, the payout control program performs the payout control unit power-on process again under the control of the payout control MPU4120a. Note that the processing in step S570 to step S582 and the infinite loop are referred to as “payout control unit power-off processing”.

  The pachinko gaming machine 1 (payout control MPU 4120a) is reset when a power failure occurs or when an instantaneous power failure occurs, and performs a payout control unit power-on process upon power recovery thereafter.

  In step S526, it is checked whether or not the payout backup information stored in the payout control built-in RAM is normal, and then in step S528, whether or not the payout control unit power-off process is normally completed. Are inspected. In this way, by checking the payout backup information stored in the payout control built-in RAM twice, it is checked whether or not the payout backup information is stored by fraud.

[17-2. Payment control unit timer interrupt processing]
Next, the payout control unit timer interrupt process will be described. The payout control unit timer interrupt process is repeatedly performed every interrupt cycle (2 ms in the present embodiment) set in the payout control unit power-on process shown in FIGS.

  When the payout control unit timer interrupt process is started, in the payout control unit 4120 of the payout control board 4110, the payout control program sets the timer interrupt to be prohibited as shown in FIG. 54 under the control of the payout control MPU 4120a. Then, the register is switched (saved) (step S590). Here, the general purpose storage element (general purpose register) used in the above-described payout control unit main process is switched to the auxiliary register. By using this auxiliary register in the payout control unit timer interrupt process, the value of the general-purpose register is not overwritten. This prevents the contents of the general-purpose register used in the payout control unit main process from being destroyed.

  Subsequent to step S590, the payout control program sets a value 1 to the 2 ms elapsed flag HT-FLG (step S592). This 2 ms elapsed flag HT-FLG is a flag that counts 2 ms every time this payout control unit timer interrupt processing is performed, that is, every 2 ms. Each is set.

  Subsequent to step S592, the payout control program switches (returns) the register (step S594). This restoration is switched from the auxiliary register used in the payout control unit timer interrupt processing to the general-purpose storage element (general-purpose register). By using this general-purpose register in the payout control unit main process, the value of the auxiliary register is not overwritten. This prevents destruction of the contents of the auxiliary register used in the payout control unit timer interrupt process.

  Subsequent to step S594, the payout control program sets interrupt permission (step S596), and ends this routine.

[17-3. Rotation angle switch history creation process]
Next, rotation angle switch history creation processing will be described. In this rotation angle switch history creation processing, a history of detection signals from the rotation angle switch 752 shown in FIG. 15 is created.

  When the rotation angle switch history creation process is started, the payout control unit 4120 in the payout control board 4110 executes a payout control program from the payout control built-in RAM as shown in FIG. 55 under the control of the payout control MPU 4120a. The switch detection history information RSW-HIST is read (step S610). This rotation angle switch detection history information RSW-HIST is 1 byte (8 bits: most significant bits B7, B6, B5, B4, B3, B2, B1, least significant bit B0, "B" represents a bit). A history of detection signals from the rotation angle switch 752 is stored as rotation angle switch detection history information RSW-HIST in the rotation angle switch history information storage area of the payout control built-in RAM. In step S610, rotation angle switch detection history information RSW-HIST is read from the rotation angle switch history information storage area.

  Subsequent to step S610, the payout control program determines whether there is a detection signal from the rotation angle switch 752 (step S612). This determination is made based on the detection signal from the rotation angle switch 752 in the port input process of step S550 in the payout control part power-on process (payout control part main process) shown in FIG. Specifically, the detection signal is stored as input information in the input information storage area of the payout control built-in RAM. In step S612, input information is read from this input information storage area, and it is determined whether or not there is a detection signal from the rotation angle switch 752. When there is a detection signal from the rotation angle switch 752 in the input information, the payout control program detects the rotation position of the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted. It is determined that the shaft is in a state where the shaft has transitioned from the cut-off state to the non-cut-off state. On the other hand, when there is no detection signal from the rotation angle switch 752 in the input information, the payout control program determines that the detection slit has changed the optical axis of the rotation angle switch 752 from the non-blocking state to the blocking state.

  When the detection slit is in a state where the optical axis of the rotation angle switch 752 is changed from the blocked state to the non-blocked state in step S612, the payout control program performs the rotation angle switch detection history information shift process (step S614). In this rotation angle switch detection history information shift process, the rotation angle switch detection history information RSW-HIST read in step S610 is converted into the most significant bits B7 ← B6, B6 ← B5, B5 ← B4, B4 ← B3, B3 ← B2. , B2 ← B1, B1 ← the least significant bit B0, and so on, and is shifted bit by bit from the least significant bit B0 toward the most significant bit B7.

  Subsequent to step S614, the payout control program sets the value 1 to the least significant bit B0 of the rotation angle switch detection history information RSW-HIST (step S616), and ends this routine.

  On the other hand, when the detection slit is in a state where the optical axis of the rotation angle switch 752 is changed from the non-blocking state to the blocking state in step S612, the payout control program performs a rotation angle switch detection history information shift process (step S618). . In the rotation angle switch detection history information shift process, the payout control program performs the same process as the rotation angle switch detection history information shift process in step S614, and the rotation angle switch detection history information RSW-HIST read in step S610. From the least significant bit B0 to the most significant bit B7, such as B7 ← B6, B6 ← B5, B5 ← B4, B4 ← B3, B3 ← B2, B2 ← B1, B1 ← the least significant bit B0. Shift one bit at a time.

  Subsequent to step S618, the payout control program sets the value 0 to the least significant bit B0 of the rotation angle switch detection history information RSW-HIST (step S620), and ends this routine.

  Thus, each time this rotation angle switch history creation process is performed, the detection slit rotates after the rotation angle switch detection history information RSW-HIST is shifted bit by bit from the least significant bit B0 toward the most significant bit B7. Depending on the state in which the optical axis of the angle switch 752 has been changed from the non-blocking state to the non-blocking state or the state in which the detection slit has shifted the optical axis of the rotation angle switch 752 from the non-blocking state to the blocking state, Since the value 0 is set, a history of detection signals from the rotation angle switch 752 can be created.

[17-4. Sprocket fixed position determination skip processing]
Next, the sprocket fixed position determination skip process will be described. This sprocket fixed position determination skip process skips the determination of whether or not the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted is in a fixed position when a predetermined condition is satisfied. The fixed position determination of the payout rotator is also performed when the payout of the game ball by the prize ball device 740 is completed. Thereby, rotation of the rotating shaft of the payout motor 744 can be reliably started in a state in which no ball is generated.

  When the sprocket fixed position determination skip process is started, the payout control unit 4120 in the payout control board 4110 causes the payout control program to execute a fixed position determination skip flag SKP− as shown in FIG. 56 under the control of the payout control MPU 4120a. It is determined whether FLG is 0 (step S630). The fixed position determination skip flag SKP-FLG is a flag indicating whether or not the fixed position determination of the payout rotating body is to be performed, and is 1 when the fixed position determination of the payout rotating body is not performed (when skipping). The value is set to 0 when the body position determination is performed (when skipping is not performed).

  When the fixed position determination skip flag SKP-FLG is 0 (not skipped) in step S630, that is, when the fixed position determination of the payout rotating body is performed, the payout control program stores the rotation angle switch history information of the payout control built-in RAM. The rotation angle switch detection history information RSW-HIST is read from the storage area (step S632), and it is determined whether or not it matches the fixed position determination value (step S634). This fixed position determination value is stored in the payout built-in ROM, and is “00001111B (“ B ”represents a bit)” in this embodiment, and the upper 4 bits B7 to B4 are 0 and the lower 4 Bits B3 to B0 have a value of 1. In the determination in step S634, it is determined whether or not the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST match the lower 4 bits B3 to B0 of the fixed position determination value.

  Here, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST have the value 1, the above described detection slit is the optical axis of the rotation angle switch 752 continuously in four timer interruption cycles. Is a state in which the state is changed from the cut-off state to the non-cut-off state. In the occurrence of the four timer interruption cycles, the payout motor 744 shown in FIG. 15 rotates four steps. The rotation of the payout motor 744 is the rotation of the payout rotating body of the rotation detection board via the first gear, the second gear, and the third gear. Since these first gear, second gear, and third gear have play (backlash), the payout rotating body rotates clockwise or counterclockwise. Since the rotation is designed to be equivalent to about two steps of rotation of the payout motor 744, in this embodiment, when the fixed position determination of the payout rotating body is performed, the rotation angle switch 752 55. Detection signal history, rotation angle switch detection history information RSW-HIST is created by the rotation angle switch history creation processing shown in FIG. 55, and the lower 4 bits B3 to B0 of the created rotation angle switch detection history information RSW-HIST, This is performed based on a detection signal from the rotation angle switch 752 when the latest four timer interruption periods occur. As a result, in the four timer interruption cycles, the payout motor 744 rotates four steps, so that it rotates more than the rotation of the payout rotator due to backlash and absorbs the rotation of the payout rotator due to backlash. Can do. Accordingly, since it is possible to prevent erroneous detection of the fixed position of the payout rotating body due to backlash, the rotational position of the payout rotating body can be correctly managed by the rotational position of the payout motor 744. In the present embodiment, the four timer interrupt cycles are 8 ms (= 2 ms × 4 times), and are set as the backlash absorption time.

  In step S634, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S632 match the lower 4 bits B3 to B0 of the fixed position determination value, the payout control program A value 1 is set to the fixed position determination skip flag SKP-FLG (step S636). Thereby, it can set so that the fixed position determination of the paying-out rotating body is not performed (skip). The payout control MPU 4120a sets the rotation position of the payout rotating body in step S636 to the fixed position of the payout rotating body.

  Subsequent to step S636, the payout control program sets the skip determination time to be valid (step S638), and ends this routine. Here, the number of detection slits is three, which is the same as the number of recesses of the payout rotating body, and is formed equally (every 120 degrees) on the outer periphery of the rotation detection board. Further, as described above, the rotation of the payout motor 744 is the rotation of the payout rotating body of the rotation detection board via the first gear, the second gear, and the third gear. In the present embodiment, the rotation between the detection slits (120 degrees) of the rotation detection board (dispensing rotary body) is designed to correspond to the 18-step rotation of the dispensing motor 744.

  The payout control program manages the rotational position of the payout rotating body based on the number of steps of the payout motor 744 under the control of the payout control MPU 4120a. Specifically, (1) a transition state in which the detection slit changes the optical axis of the rotation angle switch 752 from a cutoff state to a non-blocking state (referred to as an “edge detection state”), and (2) the detection slit has a rotation angle. A state in which the optical axis of the switch 752 has transitioned from a blocked state to a non-blocked state (referred to as a “fixed position determined state”), and (3) a detection slit shifts the optical axis of the rotation angle switch 752 from a non-blocked state to a blocked state And three states (the “fixed position determination skip state”). The edge detection state of (1) corresponds to one step rotation of the payout motor 744, the fixed position determination state of (2) corresponds to four step rotation of the payout motor 744, and the fixed position determination skip state of (3). Corresponds to 13 steps of rotation of the payout motor 744, and the rotation position between the detection slits (120 degrees) of the rotation detection board, that is, the rotation position of the payout rotating body is managed by a total of 18 steps of rotation.

  In the fixed position determination skip state of (3), the detection slit is in a state where the optical axis of the rotation angle switch 752 has transitioned from the non-blocking state to the blocking state. Is set. As described above, since the timer interruption period is set to 2 ms, the skip determination time is 26 ms (= 2 ms × 13 steps).

  When the skip determination time becomes valid in step S638, the skip determination time is subtracted in the timer update process in step S552 in the payout control unit power-on process (payout control unit main process) shown in FIG. The payout control MPU 4120a subtracts the skip determination time, and when the subtraction result becomes 0, sets the initial value 0 to the fixed position determination skip flag SKP-FLG.

  On the other hand, when the fixed position determination skip flag SKP-FLG is not 0 (value 1) (when skipping) in step S630, that is, when the fixed position determination of the payout rotating body is not performed, or in step S634, step S632 is performed. When the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read out in step 4 do not match the lower 4 bits B3 to B0 of the fixed position determination value, the payout control program ends this routine as it is. . The fixed position determination skip flag SKP-FLG set in step S636 is stored in the general-purpose storage element (general-purpose register) of the payout control MPU 4120a.

  The game balls supplied from the pachinko island facility are stored in the prize ball tank 720 and the tank rail 731, taken into the supply path of the prize ball device 740, and guided to the prize ball device 740. When the game balls rub against each other and are charged, electrostatic discharge is generated and noise is generated. For this reason, the prize ball device 740 is susceptible to noise and is in an environment. The rotation angle switch board 753 of the prize ball apparatus 740 shown in FIG. 3 is provided with a rotation angle switch 752, and the detection signal from the rotation angle switch 752 is affected by noise due to electrostatic discharge of the game ball. Cheap. In addition, the wiring (harness) for connecting the payout control board 4110 and the board 754 in the prize ball case 740 in the prize ball apparatus 740 shown in FIG. 3 is also affected by noise due to electrostatic discharge of the game ball. Cheap.

  Therefore, in this embodiment, in order to suppress erroneous detection due to the influence of noise, the fixed position determination skip state (3) described above, that is, the detection slit changes the optical axis of the rotation angle switch 752 from the non-blocking state to the blocking state. In the transitioned state, the fixed position determination of the payout rotating body is not performed. Thereby, the precision of the fixed position determination of the paying-out rotating body is increased. In addition, since the period and period required for detecting the fixed position of the payout rotating body can be obtained by calculation in advance as described above, the skip determination time can be easily set and adjusted.

[17-5. Spherical spot detection processing]
Next, the sphere collision determination process will be described. In this ball collision determination process, it is determined whether or not a ball collision state has occurred due to the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted.

  When the ball collision determination process is started, the payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110 performs a rotation angle from the rotation angle switch history information storage area of the payout control built-in RAM as shown in FIG. The switch detection history information RSW-HIST is read (step S640).

  Subsequent to step S640, the payout control program determines whether there is a detection signal from the rotation angle switch 752 described above (step S642). In this determination, it is determined whether or not the rotation angle switch detection history information RSW-HIST read in step S640 matches the home position determination value. As described above, this fixed position determination value is stored in the payout built-in ROM, and in this embodiment, is “00001111B (“ B ”represents a bit)”, and the upper 4 bits B7 to B4 are the same. The value 0 and the lower 4 bits B3 to B0 are the value 1. In the determination in step S642, it is determined whether or not the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST match the lower 4 bits B3 to B0 of the fixed position determination value.

  In step S642, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S640 match the lower 4 bits B3 to B0 of the fixed position determination value, the payout control program This routine is finished as it is, assuming that the detection slit has changed the optical axis of the rotation angle switch 752 from the non-blocking state to the blocking state, that is, the payout rotating body is rotating, and no ball-spinning state has occurred. To do.

  On the other hand, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read out in step S640 and the lower 4 bits B3 to B0 of the fixed position determination value do not match in step S642, a sphere is seen. A value 1 is set in the middle flag PBE-FLG (step S644). This ball-spinning flag PBE-FLG is a flag indicating whether or not a ball-spinning state due to the payout rotating body has occurred. When the payout motor 744 performs a ball-spinning operation, the value 1 is set. When no operation is performed, the value is set to 0.

  Subsequent to step S644, the payout control program sets the ball collision determination time to be valid (step S646), and ends this routine. When the ball stagnation determination time becomes effective, the sphere sag determination time is subtracted in the timer update process of step S552 in the payout control unit power-on process (payout control unit main process) shown in FIG. .

[17-6. Various prize ball stock addition processing]
Next, various prize ball stock number addition processing will be described. The prize ball stock number addition process includes a prize ball prize ball number addition process and a rental ball prize ball number addition process. The prize ball stock number addition process is performed from the main control board 4100. This is a process for adding the number of balls to be paid out based on a prize ball command, which will be described later. is there. First, the award ball stock number addition process for prize balls will be described, and then the award ball stock number addition process for rental balls will be described. In this embodiment, the prize ball stock number addition process for prize balls is set to be performed preferentially, and according to the number of prize balls stock added in this prize ball stock number addition process. After the game ball is paid out by the prize ball device 740, it is set so that the number of prize ball stock for lending is added.

[17-6-1. Prize ball stock number addition process for prize balls]
When the prize ball stock number addition processing for the prize ball is started, the payout control unit 4120 in the payout control board 4110 executes a payout control program as shown in FIG. 58 under the control of the payout control MPU 4120a. It is determined whether or not there is (step S650). This determination is made based on the command analyzed in the command analysis process in step S560 in the payout control unit power-on process (payout control unit main process) shown in FIG. Specifically, the analyzed command is stored as received command information in the received command information storage area of the payout control built-in RAM. In step S650, the payout control program reads the received command information from the received command information storage area and determines whether or not it is a prize ball command.

  When the received command information is not a prize ball command in step S650, the payout control program ends this routine as it is. On the other hand, when the received command information is a prize ball command in step S650, the payout control program receives the prize ball command. The corresponding prize ball number PBV is read from the prize ball number information table (step S652). The prize ball number information table, which will be described in detail later, is an information table stored in advance in the payout built-in ROM in association with the prize ball command and the prize ball number PBV.

  Subsequent to step S652, the payout control program reads the prize ball stock number PBS from the payout control built-in RAM (step S654). This award ball stock PBS represents the number of game balls that have not yet been paid out by the prize ball device 740, that is, the number of unpaid balls, and in this embodiment has a storage capacity of 2 bytes (16 bits). ing. As a result, the award ball stock number PBS can store the number of unpaid balls from 0 to 32767. The prize ball stock PBS is stored in the prize ball information storage area of the payout control built-in RAM. In step S652, the prize ball stock number PBS is read from the prize ball information storage area.

  The payout control program adds the prize ball number PBV read in step S652 to the prize ball stock number PBS read in step S654 (step S656), and ends this routine. Note that after the addition in step S656, the prize ball command read in step S650 is erased from the received command information storage area.

[17-6-2. Addition of prize ball stock for rental balls]
Next, the processing for adding the number of winning ball stocks will be described. When the award ball stock number adding process for lending is started, the payout control unit 4120 in the payout control board 4110 executes a payout request as shown in FIG. 59 under the control of the payout control MPU 4120a. It is determined whether or not there is a signal (step S660). This determination is made based on the lending request signal from the CR unit 6 in the port input process of step S550 in the payout control part power-on process (payout control part main process) shown in FIG. Specifically, the lending request signal is stored as input information in the input information storage area of the payout control built-in RAM. In step S660, the payout control program reads input information from the input information storage area and determines whether or not there is a lending request signal.

  When there is no lending request signal in step S660, the payout control program ends this routine as it is. On the other hand, when there is a lending request signal in step S660, the payout control program reads the award ball information in the above-described payout control built-in RAM. The winning ball stock number PBS is read from the storage area (step S662), the rented ball number RBV is added to the winning ball stock number PBS (step S664), and this routine is finished. The number of rented balls RBV is a fixed value and is stored in advance in the payout built-in ROM. In the present embodiment, the value 25 is set as the number of rented balls RBV. In addition, after adding in step S664, the payout control program deletes the ball rental request signal read in step S660 from the input information storage area. Further, in this embodiment, the winning ball is prioritized (the winning ball and the lending are managed separately), so even if there is a lending request signal, the lending request signal is held. When a prize ball is paid out, a rental ball is paid out. Therefore, in this embodiment, the payout of the rented ball is performed after the prize ball stock PBS reaches the value 0.

[17-7. Stock monitoring process]
Next, the stock monitoring process will be described. This stock monitoring process monitors whether or not the player continues playing the game in a state where the storage space of the foul cover unit 540 shown in FIG. 1 is filled with the stored game balls (stocked state). It is processing to do.

  When the stock monitoring process is started, the payout control unit 4120 in the payout control board 4110 causes the payout control program to display the award ball information in the payout control built-in RAM as shown in FIG. 60 under the control of the payout control MPU 4120a. The prize ball stock number PBS is read from the storage area (step S670), and it is determined whether or not the read prize ball stock number PBS is equal to or greater than the careful threshold value TH (step S672). The caution threshold TH is a fixed value and is stored in advance in the payout built-in ROM. In the present embodiment, the value 50 is set as the caution threshold TH.

  When the winning ball stock number PBS is greater than or equal to the caution threshold TH in step S672, the payout control program sets a value 1 to the caution flag CA-FLG (step S674), and the routine is terminated. The caution flag CA-FLG indicates that the player starts stocking game balls in the accommodation space of the foul cover unit 540, and the number of game balls not paid out (the number of prize balls described above) exceeds the caution threshold TH. This flag indicates that the value has been reached, and is set to a value of 1 when the threshold value exceeds the caution threshold TH, and to a value of 0 when the threshold value does not exceed the caution threshold TH.

  On the other hand, when the winning ball stock number PBS is less than the caution threshold TH in step S672, the payout control program sets a value 0 to the caution flag CA-FLG (step S676), and this routine is ended.

  If the game state becomes a big hit, and the player relaxes and looks into the effects unfolded by the game board side effect display unit 1900 shown in FIG. 17, the player inadvertently wins a prize ball for one round. The game ball that has been paid out as shown in FIG. 7 may not be pulled out by operating the lower plate ball removal button 354 from the lower plate 302 shown in FIG. When the game is continued in this state, the lower plate 302 is filled with game balls, and the game balls are accumulated in the accommodation space of the foul cover unit 540. When the storage space of the foul cover unit 540 is filled with game balls, as described above, the value of the prize ball stock PBS increases to exceed the warning threshold value TH, and each decoration of the door frame 5 is used as a warning effect. Among the boards, a plurality of LEDs (decorative LEDs) provided on each of the plurality of frame side peripheral control MPU control target decorative boards that are controlled by the peripheral control MPU 4150a blink. By this blinking, for example, it is possible to inform a hall clerk of paying attention to the player's game. As a result, the hall clerk can tell the player that he / she wants to remove the game ball from the lower plate 302, and the player fills the lower plate 302 (the storage space of the foul cover unit 540) with the game ball full. It is possible to prevent the game from continuing.

  In the present embodiment, the careful threshold value TH is set to a value 50 corresponding to about one fifth of the upper limit value 255 that can be represented by 1 byte (8 bits). As a result, it is possible to inform the hall clerk that the player should be alerted to the game as early as possible.

[17-8. Dispensing ball edge motion determination setting process]
Next, the payout ball engagement operation determination setting process will be described. This paying ball sliding motion determination setting processing is performed by paying out the game ball to the upper plate 301 or the lower plate 302 shown in FIG. This is a process for setting whether or not to discharge or not.

  When the paying-ball ball movement determination setting process is started, the payout control unit 4120 in the payout control board 4110 has the payout control program built in the payout control described above as shown in FIG. 61 under the control of the payout control MPU 4120a. The rotation angle switch detection history information RSW-HIST is read from the rotation angle switch history information storage area of the RAM (step S680).

  Subsequent to step S680, the payout control program determines whether there is a detection signal from the rotation angle switch 752 shown in FIG. 15 (step S682). In this determination, it is determined whether or not the rotation angle switch detection history information RSW-HIST read in step S680 matches the home position determination value. As described above, this fixed position determination value is stored in the payout built-in ROM, and in this embodiment, is “00001111B (“ B ”represents a bit)”, and the upper 4 bits B7 to B4 are the same. The value 0 and the lower 4 bits B3 to B0 are the value 1. In the determination in step S682, it is determined whether or not the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST match the lower 4 bits B3 to B0 of the fixed position determination value.

  In step S682, when the payout control program matches the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read out in step S680 and the lower 4 bits B3 to B0 of the fixed position determination value, It is determined whether or not the retry error flag RTERR-FLG is 1 (step S684). The retry error flag RTERR-FLG is a flag indicating whether or not a retry operation described later is operating abnormally. The value is 1 when the retry operation is operating abnormally, and the retry operation is not operating abnormally (retry operation). When the operation is normal), the value is set to 0.

  If it is determined in step S682 that the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S680 do not match the lower 4 bits B3 to B0 of the fixed position determination value, or in step S684. When the retry error flag RTERR-FLG is not a value 1 (value 0), that is, when the retry operation is not operating abnormally, the payout control program determines whether or not the ball colliding flag PBE-FLG is a value 1. Is determined (step S686). This in-between-ball flag PBE-FLG is a flag that indicates whether or not a ball-bending state due to the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted. A value of 1 is set when the motion is being performed, and a value of 0 is set when the ball motion is not performed.

  When the ball-picking flag PEB-FLG is not the value 1 (value 0) in step S686, that is, when the ball-pushing operation is not performed, the payout control program stores the award ball information stored in the above-described payout control built-in RAM. The prize ball stock number PBS is read from the area (step S688), and it is determined whether or not the read prize ball stock number PBS is larger than 0 (step S690). In this determination, it is determined whether or not there are unpaid balls in the payout of game balls by the payout motor 744.

  When the winning ball stock number PBS is greater than 0 in step S690, that is, when there is an unpaid ball number, the payout control program determines whether or not the game ball in which the accommodation space of the foul cover unit 540 is stored is full. Is determined (step S692). This determination is performed based on the full tank information stored in the full tank and out-of-ball check process in step S556 in the payout control unit power-on process (payout control unit main process) shown in FIG. Specifically, the full tank information is stored in the state information storage area of the payout control built-in RAM described above. In step S692, the full tank information is read from the state information storage area to determine whether or not the storage space of the foul cover unit 540 is full with the stored game balls.

  When the storage space of the foul cover unit 540 is not full in step S692, the payout control program performs payout setting processing (to be described later) (step S694), and this routine is ended. In this payout setting process, a payout operation for paying out game balls to the upper plate 301 and the lower plate 302 is performed.

  On the other hand, when the game ball in which the accommodation space of the foul cover unit 540 is stored is full in step S692, the payout control program ends this routine as it is. In the pachinko gaming machine 1 of the present embodiment, the payout motor 744 is forcibly stopped when the storage space of the foul cover unit 540 is full with the stored game balls. When a prize ball is generated while the payout motor 744 is forcibly stopped, the number of unpaid balls by the payout motor 744 increases, and the prize ball stock number PBS is added by the prize ball stock number addition process shown in FIG. Will increase.

  On the other hand, when the winning ball stock number PBS is not greater than 0 (value 0) in step S690, that is, when there is no unpaid ball number, the payout control program ends this routine as it is. As a result, game balls are not paid out.

  On the other hand, when the ball bending flag PBE-FLG is 1 in step S686, that is, when the ball bending operation is being performed, the payout control program performs a ball bending operation setting process described later (step S700). Exit. In this ball-spinning operation setting process, a ball-spinning operation that cancels the ball-spinning state by the payout rotating body of the prize ball device 740 is performed.

  On the other hand, when the retry error flag RTERR-FLG is 1 in step S684, that is, when the retry operation is abnormal, the payout control program sets the output stop (stop) of the drive signal to the payout motor 744. (Step S702). In this setting, drive information for stopping the drive signal is set in the payout motor 744 and stored in the output information storage area of the payout control built-in RAM described above.

  Subsequent to step S702, the payout control program sets an error status output to the CR unit 6 (step S704), and ends this routine. In step S704, when the payout control program is not communicating with the CR unit 6 under the control of the payout control MPU 4120a in order to inform the CR unit 6 that the ball lending is not possible at present (CR unit 6). The logic of the PRDY signal from LOW, that is, held down and held), the logic of the PRDY signal is held LOW, that is, the state of falling is held, and the logic state of the PRDY signal is set in the PRDY signal output setting information And stored in the CR communication information storage area. Thus, the PRDY signal output setting information is read from the CR communication information storage area stored in the payout control built-in RAM in the CR communication process of step S554 in the payout control part main process of the payout control part power-on process of FIG. The read PRDY signal output setting information, that is, the PRDY signal whose logic is LOW, is transferred from the output terminal of a predetermined output port of the payout control MPU 4120a of the payout control unit 4120 via the game ball lending device connection terminal plate 869. Output to unit 6. On the other hand, when communicating with the CR unit 6 (when the BRDY logic from the CR unit 6 is HI, that is, rises and is held), the logic state of the EXS signal is maintained and the logic state of the EXS signal is maintained. Is set in the EXS signal output setting information and stored in the CR communication information storage area. Thus, the EXS signal output setting information is read from the CR communication information storage area stored in the payout control built-in RAM in the CR communication process of step S554 in the payout control part main process of the payout control part power-on process of FIG. The read EXS signal output setting information, that is, the EXS signal whose logic is maintained is output from the output terminal of a predetermined output port of the payout control MPU 4120a to the CR unit 6 via the gaming ball lending device connection terminal plate 869. . Note that “maintain the logic state of the EXS signal” means that when the logic of the EXS signal is LOW (when the EXS signal falls and is held), the logic of the EXS signal is HI. In some cases (when the EXS signal is held up), the logic HI is maintained.

[17-8-1. Withdrawal setting process]
Next, the payout setting process will be described. In this payout setting process, the payout motor 744 is driven to make a setting for paying out game balls.

  When the payout setting process is started, the payout control unit 4120 in the payout control board 4110 causes the payout control program to obtain the drive command number DRV from the payout control built-in RAM as shown in FIG. 62 under the control of the payout control MPU 4120a. Read (step S710). This drive command number DRV commands the number of game balls to be paid out by the payout motor 744, and is equivalent to the prize ball stock number PBS. The drive command number DRV is stored in the prize ball information storage area of the payout control built-in RAM. In step S710, the drive command number DRV is read from the prize ball information storage area.

  Subsequent to step S710, the payout control program determines whether or not the drive command number DRV is 0 (step S712). This determination is made based on the drive command number DRV as to whether or not the number of game balls to be paid out by the payout motor 744 remains.

  When the drive command number DRV is 0 in step S712, that is, when the number of game balls to be paid out by the payout motor 744 is zero, the payout control program stops outputting (stopping) the drive signal to the payout motor 744. ) Is set (step S714). In this setting, drive information for stopping the drive signal is set in the payout motor 744 and stored in the output information storage area of the payout control built-in RAM described above.

  Subsequent to step S714, the payout control program reads the prize ball stock number PBS from the prize ball information storage area of the payout control built-in RAM (step S716), and reads the real ball count PB (step S718). The actual ball count PB is obtained by counting the number of game balls actually paid out by the payout motor 744. The count will be described in detail later, but the count input from the count switch 751 shown in FIG. This is performed based on the detection signal. The real ball count PB is stored in the prize ball information storage area of the payout control built-in RAM. In step S718, the real ball count PB is read from this prize ball information storage area.

  Subsequent to step S718, the payout control program sets a value obtained by subtracting the actual ball count PB read in step S718 from the prize ball stock number PBS read in step S716 to the prize ball stock number PBS and the drive command number DRV. (Step S720), the real ball count PB is set to 0 (step S722), and this routine is terminated. When the drive command number DRV and the real ball count PB are 0, in step S722, the value of the prize ball stock number PBS read in step S716 is set as the drive command number DRV as it is.

  On the other hand, when the drive command number DRV is not 0 in step S712, that is, when there is a number of game balls to be paid out by the payout motor 744, the payout control program sets an output of a drive signal to the payout motor 744. (Step S724). In this setting, drive information for stopping the drive signal is set in the payout motor 744 and stored in the output information storage area of the payout control built-in RAM.

  Subsequent to step S724, the payout control program subtracts 1 from the drive command number DRV (decrements, step S726), and determines whether there is a detection signal from the count switch 751 (step S728). This determination is made based on the detection signal from the count switch 751 in the port input process in step S550 in the payout control part power-on process (payout control part main process) shown in FIG. Specifically, the detection signal is stored as input information in the input information storage area of the payout control built-in RAM. In step S728, the payout control program reads input information from the input information storage area and determines whether or not there is a detection signal from the counting switch 751.

  When there is a detection signal from the counting switch 751 in step S728, the payout control program adds 1 to the actual ball count PB (increments, step S730), and this routine is terminated. In step S730, the real ball count PB is incremented by incrementing the real ball count PB.

  On the other hand, when there is no detection signal from the counting switch 751 in step S728, the payout control program ends this routine as it is. As described above, the payout control program is a case where the drive command number DRV is decremented in step S726 under the control of the payout control MPU 4120a, and when there is no detection signal from the counting switch 751 in the determination in step S728, that is, If the ball count PB is not incremented, one game ball could not be paid out because the game ball was not received in the recess of the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 was transmitted. to decide. Therefore, the payout control program sets the value obtained by subtracting the real ball count PB from the prize ball stock number PBS to the drive command number DRV in step S720 described above in order to pay out one ball that should be paid out again. Thereby, when there is no detection signal from the counting switch 751 in the determination of step S728, that is, when the actual ball count PB is not incremented, the value 1 which is one ball that should be paid out is included in the prize ball stock number PBS. In other words, since the value 1 which is one ball to be paid out can be rounded into the winning ball stock number PBS, a retry operation of paying out the one ball to be paid out again can be performed. By performing this retry operation, the possibility of unpaid game balls to the player can be extremely reduced, and a player's disadvantage due to unpaid game balls can be prevented.

[17-8-2. Spherical motion setting process]
Next, the spherical cornering operation setting process will be described. This ball-spinning operation setting process is a process for performing a setting for canceling the ball-spinning state by the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 of the prize ball device 740 is transmitted.

  When the ball staking operation setting process is started, the payout control unit 4120 in the payout control board 4110 causes the payout control program to pass the ball scouring determination time as shown in FIG. 63 under the control of the payout control MPU 4120a. It is determined whether or not (step S750). This determination is made on the basis of the ball detection time subtracted in the timer update process of step S552 in the payout control part power-on process (payout control part main process) shown in FIG. Specifically, the ball collision determination time is stored as time management information in the time management information storage area of the above-described payout control built-in RAM. In step S750, the time management information is read from the time management information storage area to determine whether or not the ball stagnation determination time has elapsed.

  When it is determined in step S750 that the ball collision determination time has not elapsed, the payout control program reads the rotation angle switch detection history information RSW-HIST from the rotation angle switch history information storage area of the above-described payout control built-in RAM (step S752). .

  Subsequent to step S752, the payout control program determines whether there is a detection signal from the rotation angle switch 752 described above (step S754). In this determination, it is determined whether or not the rotation angle switch detection history information RSW-HIST read in step S752 matches the home position determination value. As described above, this fixed position determination value is stored in the payout built-in ROM, and in this embodiment, is “00001111B (“ B ”represents a bit)”, and the upper 4 bits B7 to B4 are the same. The value 0 and the lower 4 bits B3 to B0 are the value 1. In the determination in step S754, it is determined whether or not the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST match the lower 4 bits B3 to B0 of the fixed position determination value.

  In step S754, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S752 do not match the lower 4 bits B3 to B0 of the fixed position determination value, the payout control program The output of the drive signal to the payout motor 744 is set so as to perform the ball collapsing operation (step S756), and this routine is finished. In this setting, drive information for outputting a drive signal to the payout motor 744 is set and stored in the output information storage area of the payout control built-in RAM described above.

  On the other hand, in step S754, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S752 and the lower 4 bits B3 to B0 of the fixed position determination value match, the payout control program Sets the stop of the drive signal to the payout motor 744 (step S758). In this setting, drive information for stopping the drive signal is set in the payout motor 744 and stored in the output information storage area of the payout control built-in RAM.

  Subsequent to step S758, the payout control program sets a value of 0 to the in-ball flag PBE-FLG as the end of the ball-bending operation (step S760), and ends this routine. This ball-spinning flag PBE-FLG is a flag indicating whether or not a ball-spinning state due to the payout rotating body has occurred. When the payout motor 744 performs a ball-spinning operation, the value 1 is set. When no operation is being performed (end of the ball collapsing operation), the value is set to 0.

  On the other hand, when the ball collision determination time has elapsed in step S750, the payout control program sets stop of the drive signal to the payout motor 744 (step S762). In this setting, drive information for stopping the drive signal is set in the payout motor 744 and stored in the output information storage area of the payout control built-in RAM.

  Subsequent to step S762, the payout control program sets an error state output to the CR unit 6 (step S764). Here, in order to notify the CR unit 6 that the ball lending is not possible at present, the payout control MPU 4120a is not communicating with the CR unit 6 (the logic of BRDY from the CR unit 6 is LOW, that is, The logic of the PRDY signal is LOW, that is, the state of falling is held, and the logic state of the PRDY signal is set in the PRDY signal output setting information and stored in the CR communication information storage area. To do. Thus, the PRDY signal output setting information is read from the CR communication information storage area stored in the payout control built-in RAM in the CR communication process of step S554 in the payout control part main process of the payout control part power-on process of FIG. The read PRDY signal output setting information, that is, the PRDY signal whose logic is LOW, is transferred from the output terminal of a predetermined output port of the payout control MPU 4120a of the payout control unit 4120 via the game ball lending device connection terminal plate 869. Output to unit 6. On the other hand, when communicating with the CR unit 6 (when the BRDY logic from the CR unit 6 is HI, that is, rises and is held), the logic state of the EXS signal is maintained and the logic state of the EXS signal is maintained. Is set in the EXS signal output setting information and stored in the CR communication information storage area. Thus, the EXS signal output setting information is read from the CR communication information storage area stored in the payout control built-in RAM in the CR communication process of step S554 in the payout control part main process of the payout control part power-on process of FIG. The read EXS signal output setting information, that is, the EXS signal whose logic is maintained is output from the output terminal of a predetermined output port of the payout control MPU 4120a to the CR unit 6 via the gaming ball lending device connection terminal plate 869. . Note that “maintain the logic state of the EXS signal” means that, as described above, when the logic of the EXS signal is LOW (the EXS signal falls and is held), the logic LOW is maintained and the EXS signal is maintained. When the logic of HI is HI (the EXS signal is held high), the logic HI is maintained.

  Subsequent to step S764, the payout control program sets a value “0” to the ball-balling flag PBE-FLG as the ball-balling operation ends (step S766), and the routine is terminated.

[17-9. Retry operation monitoring process]
Next, the retry operation monitoring process will be described. This retry operation monitoring process is a process for monitoring whether or not a retry operation for paying out a game ball that should be paid out is performed normally.

  When the retry operation monitoring process is started, the payout control unit 4120 in the payout control board 4110 causes the payout control program to execute the rotation angle of the above-described payout control built-in RAM as shown in FIG. 64 under the control of the payout control MPU 4120a. The rotation angle switch detection history information RSW-HIST is read from the switch history information storage area (step S770).

  Subsequent to step S770, the payout control program determines whether there is a detection signal from the rotation angle switch 752 described above (step S772). In this determination, it is determined whether or not the rotation angle switch detection history information RSW-HIST read in step S770 matches the home position determination value. As described above, this fixed position determination value is stored in the payout control built-in ROM, and in this embodiment, is “00001111B (“ B ”represents a bit)”, and B7 to B4 of the upper 4 bits. Is the value 0, and the lower 4 bits B3 to B0 are the value 1. In the determination in step S772, it is determined whether or not the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST match the lower 4 bits B3 to B0 of the fixed position determination value.

  In step S772, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S770 match the lower 4 bits B3 to B0 of the fixed position determination value, the payout control program The value 1 is added to the inconsistency counter INCC (increment, step S774). The inconsistency counter INCC includes the number of game balls received and paid out by the recess of the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted, the number of balls detected by the counting switch 751, The number of game balls received and paid out by the recess of the payout rotor coincides with the number of balls detected by the counting switch 751. The value is 0. The payout control program performs a retry operation in the payout installation process shown in FIG. 62, so that the number of game balls received and paid out by the concave portion of the payout rotating body by this retry operation and the actual counting switch Whether or not paying out game balls that do not match with the number of balls detected in 751 is repeatedly performed is determined by monitoring with the inconsistency counter INCC. The inconsistency counter INCC is stored in the prize ball information storage area of the payout control built-in RAM. In step S774, the payout control program increments the inconsistency counter INCC stored in the prize ball information storage area.

  Subsequent to step S774 or in step S772, the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S770 do not match the lower 4 bits B3 to B0 of the fixed position determination value. Sometimes, the payout control program determines whether there is a detection signal from the counting switch 751 (step S776). This determination is made based on the detection signal from the count switch 751 in the port input process of step S550 in the payout control part power-on process (payout control part main process) shown in FIG. Specifically, as described above, the detection signal is stored as input information in the input information storage area of the above-described payout control built-in RAM. In step S776, the payout control program reads input information from the input information storage area and determines whether or not there is a detection signal from the counting switch 751.

  When there is a detection signal from the counting switch 751 in step S776, the payout control program subtracts 1 from the inconsistency counter INCC stored in the award ball information storage area of the payout control built-in RAM (decrements, step S778). .

  Subsequent to step S778 or when there is no detection signal from the counting switch 751 in step S776, the payout control program determines whether or not the value of the mismatch counter INCC is smaller than the mismatch threshold INCTH (step S780). ). In the pachinko gaming machine 1, it has been experimentally obtained that the probability that one game ball that does not fit due to the retry operation is paid out is about one millionth, and in this embodiment, the mismatch threshold value The value 5 is set as INCTH.

  In the process for setting the work area of the payout control built-in RAM in step S530 in the payout control unit power-on process in FIG. Information used for the retry operation monitoring process is set based on the inconsistency counter INCC stored in the prize ball information storage area. By this processing, for example, even if there is a momentary power failure or a power failure, the value of the inconsistency counter INCC at the time of power recovery is restored to the value of the inconsistency counter INCC just before the momentary power failure or power failure stored as payout backup information Can be done. As a result, in the determination in step S780, the game ball payout operation (retry operation) performed by the prize ball device 740, which has been performed until immediately before a momentary power failure or power failure, can be continued from the time of power recovery. ing. Therefore, for example, immediately before a momentary power failure or power failure, if the value of the mismatch counter INCC is smaller than the mismatch threshold INCTH in the determination of step S780, it is determined that the retry operation is operating normally, that is, a prize ball It is determined that the game ball payout operation by the device 740 is in a normal state, and it can be determined that the game ball payout operation by the prize ball device 740 is in a normal state by the determination in step S780 even during power recovery. On the other hand, when the value of the mismatch counter INCC is not smaller than the mismatch threshold INCTH in the determination in step S780, it is determined that the retry operation is abnormal, that is, the game ball payout operation by the prize ball device 740 is abnormal. Even when power is restored, it can be determined in step S780 that the game ball payout by the prize ball device 740 is in an abnormal state.

  If the value of the inconsistency counter INCC is smaller than the inconsistency threshold INCTH in step S780, this routine is terminated as it is. On the other hand, when the value of the mismatch counter INCC is not smaller than the mismatch threshold INCTH in step S780, that is, when the value of the mismatch counter INCC is equal to or greater than the mismatch threshold INCTH, the payout control program displays “Retry error”. In order to notify that “there is a payout control built-in RAM, retry error information for displaying the number“ 5 ”is set on the error LED indicator 860b, which is a segment indicator mounted on the payout control board 4110. Is set (stored) in the state information storage area (step S782). On the other hand, when notifying that “the prize ball is in stock”, the payout control program sets the information in the prize ball stock to display the number “9” on the error LED indicator 860b and incorporates the above-described payout control. It is set (stored) in the status information storage area of the RAM (step S782).

  Subsequent to step S782, the payout control program sets a value 0 (initial value 0) to the inconsistency counter INCC stored in the prize ball information storage area of the payout control built-in RAM (step S784). In step S784, the mismatch counter INCC determines that the value of the mismatch counter INCC is not smaller than the mismatch threshold INCTH in step S780, that is, the value of the mismatch counter INCC is greater than or equal to the mismatch threshold INCTH. Initialization is triggered by the occurrence of this internal factor. When the operation switch 860a is operated to clear the RAM when the power is turned on, the inconsistency counter INCC is initialized when the external factor occurs. When the operation switch 860a is operated when the power is turned on, as described above, an operation signal corresponding to the operation is input to the main control MPU 4100a of the main control board 4100 shown in FIG. 14 as a RAM clear signal. The main control program described above erases all the various information stored in the main control built-in RAM and controls the RAM clear notification command as shown in FIG. 14 under the control of the main control MPU 4100a. 4140. Thereby, the RAM clear notification sound flows from the speaker housed in the speaker box 820 provided in the main body frame 3 shown in FIG. 5 and the speaker 130 provided in the door frame 5 shown in FIG.

  Subsequent to step S784, the retry error flag RTERR-FLG is set to 1 (step S786), and this routine is terminated. This retry error flag RTERR-FLG is a flag indicating whether or not the retry operation is operating abnormally. The value is 1 when the retry operation is operating abnormally, and the retry operation is not operating abnormally (retry operation is not performed). It is set to a value of 0 when operating normally).

  Note that the payout control program shows the retry error information (or information in the prize ball stock) set (stored) in the output information storage area of the payout control built-in RAM in step S782 under the control of the payout control MPU 4120a. In the payout control unit power-on process (payout control unit main process), a retry error status command is created and transmitted to the main control board 4100 in the command transmission process in step S566, and LED display data creation in step S564 in the process is performed. In the process, display data to be displayed on the error LED display 860b is created and stored as LED display information in the output information storage area, and the LED display information stored in the output information storage area in the port output process of step S548 in the process is stored. Based on the error LED indicator 860b, To display the number "5" on the error LED display device 860b. In the main control board 4100 that has received the status command, the main control program transmits it to the peripheral control board 4140 in the peripheral control board command transmission process of step S120 in the main control timer interrupt process shown in FIG. The peripheral control board 4140 includes a plurality of LEDs (on each of the decorative boards of the door frame 5 provided on each of the plurality of frame side peripheral control MPU control target decorative boards that are controlled by the peripheral control MPU 4150a. In order to cause the decoration LED) to emit light in a predetermined color (red in the present embodiment), the above-mentioned frame side emission data is output to the frame decoration drive amplifier board 194 shown in FIG. Light with color. As described above, the store clerk or the like who notices the light emission of the plurality of LEDs opens the main body frame 3 with respect to the outer frame 2 to thereby display the number "" on the error LED display 860b mounted on the payout control board 4110. By visually observing that “5” is displayed, it can be confirmed that a “retry error” has occurred. Thereby, in order to investigate the cause of the occurrence, the store clerk of the hall, etc., confirms the malfunction of the counting switch 751, the disconnection of various harnesses extending from the counting switch 751 to the payout control board 4110, the contact failure of various connectors, and the like. Compared with the case where the light emission of the plurality of LEDs and the display content of the error LED indicator 860b are not notified, it can be performed very quickly.

  In addition, it has been described above that it is difficult to detect the game ball that is received by the concave portion of the payout rotating body to which the rotation of the rotary shaft of the payout motor 744 is transmitted by intentionally disabling the counting switch 751. Even if an illegal act of forcibly generating a retry operation and illegally acquiring a game ball paid out by the retry operation is performed, the value of the inconsistency counter INCC is equal to or greater than the inconsistency threshold INCTH. Of the decorative boards of the door frame 5, a plurality of LEDs (decorative LEDs) provided on each of the plurality of frame side peripheral control MPU control target decorative boards that are controlled by the peripheral control MPU 4150a emit light. Therefore, a hall clerk or the like rushes to confirm the state of the pachinko gaming machine 1. If it does so, the player who performs a fraudulent act will have to be interrupted so that the act may not be discovered, and the illegal game ball by a fraudulent act cannot be continuously acquired. Even if the value of the inconsistency counter INCC coincides with the inconsistency threshold INCTH, the number of game balls that can be obtained by a player who performs an illegal act is the same as the inconsistency threshold INCTH, that is, 5 balls Therefore, damage to the hall due to the act of intentionally deactivating the counting switch 751 can be suppressed to an extremely low level.

  Further, as described above, the mismatch counter INCC determines that the value of the mismatch counter INCC is not smaller than the mismatch threshold INCTH in step S780, that is, the value of the mismatch counter INCC is greater than or equal to the mismatch threshold INCTH. Initialization is triggered by the occurrence of an internal factor. As a result, the inconsistency counter INCC is not initialized when an external factor occurs, for example, that the operation switch 860a is operated to cancel the error. Therefore, even if the operation switch 860a or the like is illegally modified and the operation signal is input to the payout control MPU 4120a, the inconsistency counter INCC may be forcibly initialized by such an illegal action. Absent.

[17-10. Inconsistency counter reset judgment process]
Next, the mismatch counter reset process will be described. In this inconsistency counter reset process, the number of game balls received and paid out by the recess of the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted, and the number of balls detected by the counting switch 751 This is a process for determining whether or not to reset the inconsistency counter INCC that calculates the difference between.

  When the mismatch counter reset determination process is started, the payout control unit 4120 in the payout control board 4110 causes the payout control program to execute the inconsistency counter reset determination time as shown in FIG. 65 under the control of the payout control MPU 4120a. It is determined whether or not it has elapsed (step S790). This determination is performed based on the mismatch counter reset determination time updated in the timer update process of step S552 in the payout control unit power-on process (payout control unit main process) shown in FIG. Specifically, the mismatch counter reset determination time is stored as time management information in the time management information storage area of the payout control built-in RAM described above. In step S790, the time management information is read from the time management information storage area to determine whether or not the mismatch counter reset determination time has elapsed.

  When the mismatch counter reset determination time has not elapsed in step S790, the payout control program ends this routine as it is. On the other hand, when the mismatch counter reset determination time has elapsed in step S790, the payout control program initializes the mismatch counter reset determination time (step S792). By this initialization, an initial value of 7000 s (about 2 hours) is set as the mismatch counter reset determination time.

  Subsequent to step S792, the payout control program sets a value 0 (initial value 0) to the inconsistency counter INCC stored in the award ball information storage area of the payout control built-in RAM described above (step S794). Exit. As described above, the inconsistency counter INCC is detected by the counting switch 751 and the number of game balls received and received by the recess of the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted. It is a counter for calculating the difference between the number of balls, and the number of game balls received and paid out by the recess of the payout rotating body is usually equal to the number of balls detected by the counting switch 751. As a result, the value is 0. The payout control program performs a retry operation in the payout installation process shown in FIG. 62 under the control of the payout control MPU 4120a. The inconsistency counter INCC determines whether or not the game balls that are not consistent due to the discrepancy between the number and the number of balls actually detected by the counting switch 751 are repeatedly paid. In the pachinko gaming machine 1 of the present invention, it has been experimentally obtained that the probability that a game ball that does not fit in due to a retry operation is paid out is about one millionth.

  Here, as described above, the pachinko gaming machine 1 includes the game board 4 and a frame body such as the main body frame 3 to which the game board 4 is mounted, and the game board 4 is exchanged (new stand replacement). Since the game specifications can be changed, the payout control board 4110 for controlling the prize ball device 740, the power supply board 851 for generating the driving power for the prize ball device 740 and the control power for the payout control board 4110 are common. Equipped on the frame side as a function. In the payout control unit 4120 on the payout control board 4110, the payout control program monitors the inconsistency counter INCC as described above under the control of the payout control MPU 4120a to determine whether or not the retry operation is repeatedly performed. The payout control unit power-off process in the payout control unit power-on process shown in FIG. 53 stores an inconsistency counter INCC immediately before shutting off when the power is turned off. In the process of step S530 in the payout control unit power-on process shown in 52 (setting of the RAM work area when power is restored), the process is started again from the stored inconsistency counter INCC when the power is turned on.

  Then, when the game board 4 mounted on the pachinko gaming machine 1 is switched to a game board 4 'having a different game specification different from the game board 4 and turned on, the payout control is performed. The payout control MPU 4120a of the payout control unit 4120 on the substrate 4110 starts processing again from the mismatch counter INCC stored when the game board 4 is mounted on the pachinko gaming machine 1. That is, when the player plays the pachinko gaming machine 1 with the game board 4 ′ attached thereto, the mismatch counter INCC in the pachinko gaming machine 1 with the game board 4 before replacement is inherited as it is. For this reason, when a player plays the pachinko gaming machine 1 with the game board 4 ′ mounted, the probability of 1 / million million happens, and the number of game balls that do not match is generated and the inconsistency counter INCC When the inconsistency counter INCC becomes equal to or greater than the inconsistency threshold INCTH, the game board 4 is replaced with the game board 4 'and is determined as an abnormal operation of the retry operation by the payout control MPU 4120a in a short period. There is a risk. That is, in a short period of time after the game board 4 is replaced with the game board 4 ′, a malfunction of the counting switch 751, disconnection of various harnesses extending from the counting switch 751 to the payout control board 4110, contact failure of various connectors, and the like. In spite of this, there is a possibility that it is suddenly determined as an abnormal operation of the retry operation.

  As described above, when the game board 4 is replaced with the game board 4 ′ and it is determined as an abnormal operation of the retry operation in a short period of time, the impression that the replaced game board 4 ′ is new and easily breaks down. May be given to players. The probability of a millionth of a game ball being paid out due to a retry operation is one millionth of the time when a pachinko machine 1 is installed in the hall and operated continuously for one week during the hall's business hours. Since the probability that one game ball that does not match due to the retry operation is paid out is the same, the probability of 1 / million from the inconsistency counter INCC in the process of step S778 in the retry operation monitoring process shown in FIG. Thus, the value 1 is not subtracted. Then, the value 1 is incremented to the mismatch counter INCC in one week and the mismatch counter INCC becomes the value 1, and the value 1 is further incremented in the mismatch counter INCC and the mismatch counter INCC becomes the value 2 in 2 weeks. In week, value 1 is further incremented in inconsistency counter INCC, value in inconsistency counter INCC becomes value 3, in value 4 in inconsistency counter INCC is further incremented, value in inconsistency counter INCC becomes value 4, and in week 5 The value 1 is further incremented in the inconsistency counter INCC, and the inconsistency counter INCC becomes the value 5, which coincides with the inconsistency threshold INCTH described above. That is, when 5 weeks have elapsed, the inconsistency counter INCC matches the inconsistency threshold INCTH, so that the payout control program performs the operation of step S776 in the retry operation monitoring process shown in FIG. 64 under the control of the payout control MPU 4120a. In the determination, it is determined that there is no detection signal from the counting switch 751, and a malfunction of the counting switch 751, disconnection of various harnesses extending from the counting switch 751 to the payout control board 4110, poor contact of various connectors, and the like occur. 64 is a segment display mounted on the payout control board 4110 in order to notify that it is a “retry error” in the process of step S782 in the retry operation monitoring process shown in FIG. Retryer to display number “5” on error LED indicator 860b Set the information so that the set (stored) in the status information storage area of the payout control chip RAM.

  Therefore, when the payout control MPU 4120a determines that the inconsistency counter reset determination time has elapsed in the determination of step S790 in the inconsistency counter reset determination processing, that is, every 7000 s (about 2 hours), the inconsistency counter reset is repeated. By forcibly setting the inconsistency counter INCC to 0, that is, forcibly resetting the inconsistency counter INCC in the process of step S794 in the determination process, the inconsistency counter INCC that is generated with the probability of 1 / million million is increased. Invalidated. As a result, there is an error in the retry operation even though the malfunction of the counting switch 751, the disconnection of various harnesses extending from the counting switch 751 to the payout control board 4110, the contact failure of various connectors, and the like have not occurred. Can be prevented from being set (stored) in the status information storage area of the payout control built-in RAM.

  Note that the game ball that is received by the recess of the payout rotating body to which the rotation of the rotary shaft of the payout motor 744 is transmitted by deliberately disabling the counting switch 751 is difficult to detect. In the case where the counting switch 751 is intentionally repeatedly deactivated for a short time even if an illegal act of forcibly generating a retry operation and illegally acquiring a game ball paid out by the retry operation is performed, As described above, when the value of the mismatch counter INCC is equal to or greater than the mismatch threshold INCTH, among the decorative boards of the door frame 5, a plurality of frame side peripheral control MPUs that are controlled by the peripheral control MPU 4150a are directly controlled. Since a plurality of LEDs (decorative LEDs) provided on each of the control target decorative boards emit light, the hall clerk or the like is in the state of the pachinko gaming machine 1 So that the rush to to confirm. If it does so, the player who performs a fraudulent act will have to be interrupted so that the act may not be discovered, and the illegal game ball by a fraudulent act cannot be continuously acquired. On the other hand, when the count switch 751 is intentionally repeatedly inactivated for a long time so that the value of the mismatch counter INCC does not become equal to or greater than the mismatch threshold INCTH, the mismatch counter INCC is set every 7000 s (about 2 hours). Although reset, the number of game balls that can be acquired by a player who performs fraudulent action is that the inconsistency counter INCC is up to the inconsistency threshold INCTH and the count switch 751 is intentionally set as described above. Even if the player is repeatedly inactivated for a long time, the number of game balls that can be acquired by a player who performs an illegal act can be extremely reduced.

[17-11. Error release operation determination process]
Next, the error release operation determination process will be described. In this error release operation determination process, it is determined whether or not the operation switch 860a shown in FIG. 15 is being operated.

  When the error release operation determination process is started, the payout control unit 4120 in the payout control board 4110 causes the payout control program to release the error of the operation switch 860a as shown in FIG. 66 under the control of the payout control MPU 4120a. It is determined whether or not it has been operated (step S800). This determination is made based on the operation signal from the operation switch 860a in the port input process of step S550 in the payout control unit power-on process (payout control unit main process) shown in FIG. Specifically, the operation signal is stored as input information in the input information storage area of the payout control built-in RAM described above. In step S800, the payout control program reads the input information from the input information storage area, and determines that the error cancellation is not instructed when the logical value of the operation signal from the operation switch 860a is HI. When the operation switch 860a is determined not to be operated, when the logical value of the operation signal from the operation switch 860a is LOW, it is determined that the error cancellation is instructed, and the operation switch 860a is operated. It is determined that

  When the operation switch 860a is not operated in step S800, the payout control program ends this routine as it is. On the other hand, when the operation switch 860a is operated in step S800, the payout control program performs error flag state confirmation processing. This is performed (step S802). In this error flag state determination process, the state of the error flag corresponding to various types of error information regarding the prize ball device 740 is confirmed. For example, the state of the retry error flag RTERR-FLG indicating whether or not the retry operation is abnormal is confirmed. As described above, the retry error flag RTERR-FLG has a value of 1 when the retry operation is operating abnormally and a value of 0 when the retry operation is not operating abnormally (retry operation is operating normally), respectively. Since the payout control program is set, the payout control program checks whether the value of the retry error flag RTERR-FLG is 0 or 1 under the control of the payout control MPU 4120a.

  Subsequent to step S802, the payout control program performs state information setting processing (step S804). In this status information setting process, if the status of the error flag indicates that an error has occurred based on the error flag confirmed in step S802, the status information corresponding to the error flag is described above. Is set (stored) in the status information storage area of the payout control built-in RAM. As a result, various information (status information) is read from the status information storage area in the command transmission process of step S566 in the payout control section power-on process (payout control section main process) shown in FIG. Based on the information, a status command is created and transmitted to the main control board 4100. For example, when the retry error flag RTERR-FLG indicating whether or not the retry operation described above is operating abnormally is 1, that is, when the retry operation is operating abnormally, it indicates that an error has occurred in the retry operation. When the retry error information to be transmitted is set (stored) in the status information storage area of the payout control built-in RAM, the command transmission process in step S566 in the payout control unit power-on process (payout control part main process) shown in FIG. A retry error status command is created and transmitted to the main control board 4100.

  The main control board 4100 that has received the retry error information transmits the main control program to the peripheral control board 4140 in the peripheral control board command transmission process of step S120 in the main control timer interrupt process shown in FIG. In the control board 4140, the sub-control program performs a retry operation error notification process for notifying that an error has occurred in the retry operation. In this retry operation error notification process, the error notification announcement of the retry operation “Check the prize ball unit.” And “Check the payout control board harness.” 2 times) By repeatedly flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 shown in FIG. 5 and the speaker 130 provided in the door frame 5 shown in FIG. It is supposed to be. The store clerk or the like who has heard this retry operation error notification announces the malfunction of the counting switch 751 shown in FIG. Compared to the case where the error notification announcement of the retry operation does not flow from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, it can be confirmed very quickly. In the retry operation error notification process, a plurality of LEDs provided on each of a plurality of frame side peripheral control MPU control target decorative boards that are controlled by the peripheral control MPU 4150a among the decorative boards of the door frame 5. The (decorative LED) is forcibly set to a predetermined color (in this embodiment, red) to emit light.

  Subsequent to step S804, the payout control program performs release setting processing (step S806). In this cancellation setting process, when the error flag state indicates that an error has occurred based on the error flag corresponding to the various types of error information confirmed in step S802, the error flag corresponds to the error flag. The CR unit 6 indicates that the error is forcibly stopped or the ball can be lent out by the error LED indicator 860b which is a segment indicator already mounted on the payout control board 4110. In this case, the logic of the PRDY signal described above is held at HI, that is, the state in which the PRDY signal is raised, and the lending device connection terminal plate 869 such as a game ball is connected to the predetermined output port of the payout control MPU 4120a of the payout control unit 4120. Or output to the CR unit 6. For example, when the retry error flag RTERR-FLG indicating whether or not the retry operation described above is operating abnormally, that is, when the retry operation is operating abnormally, the error LED indicator 860b has already displayed. The retry error information stored in the status information storage area of the payout control built-in RAM is “normal” in order to forcibly stop the number “5” for informing that the “retry error” is present. This is forcibly overwritten on the information on which the graphic “-” for informing the effect is displayed. Further, in order to inform the CR unit 6 that the ball can be rented, the logic of the PRDY signal is held at HI, that is, the rising state is maintained, and the game ball is output from the output terminal of the predetermined output port of the payout control MPU 4120a. Output to the CR unit 6 through the equal lending device connection terminal plate 869.

  Subsequent to step S806, the payout control program performs error flag initialization processing (step S808), and this routine is terminated. In this error flag initialization process, if the error flag status indicates that an error has occurred based on the error flag corresponding to the various error information confirmed in step S802, the error flag is set. initialize. For example, when the retry error flag RTERR-FLG indicating whether or not the retry operation described above is operating abnormally is 1, that is, when the retry operation is operating abnormally, the retry error flag RTERR-FLG is set to 0. Set and initialize. At this time, the logic of the PRDY signal described above is held at HI, that is, the rising state is maintained, and the logic state of the PRDY signal is set in the PRDY signal output setting information and stored in the CR communication information storage area. Thus, the PRDY signal output setting information is read from the CR communication information storage area stored in the payout control built-in RAM in the CR communication process of step S554 in the payout control part main process of the payout control part power-on process of FIG. The read PRDY signal output setting information, that is, the PRDY signal whose logic is LOW, is output to the CR unit 6 from the output terminal of the predetermined output port of the payout control MPU 4120a through the gaming ball lending device connection terminal plate 869. .

  As described above, when the retry error flag RTERR-FLG is determined in step S780 in the retry operation monitoring process shown in FIG. 64 and the value of the mismatch counter INCC is greater than or equal to the mismatch threshold INCTH, this internal factor In response to the occurrence of the error, the retry error flag RTERR-FLG is set to a value of 1 in the process of step S786 of the same process. On the other hand, when the operation switch 860a is operated, this causes an external factor. When this occurs, the retry error flag RTERR-FLG is set to 0 and initialized. The retry error flag RTERR-FLG is operated to clear the RAM when the operation switch 860a is operated to clear the RAM when the power is turned on, that is, the operation switch 860a clears the RAM to release the error. Similar to the case where the switch 860a is operated, the initialization is triggered by the occurrence of this external factor.

  As described above, in the pachinko gaming machine 1, the main process on the main control side is executed from the time of power-on to the operation switch 860a (operation switch) that should have been originally used to cancel the error that has occurred regarding the payout operation. Instead, for the predetermined time until the operation is performed, an operation for exhibiting a RAM clear function for starting initialization of the main control built-in RAM (game storage unit) and the payout control built-in RAM (payout storage unit) instead. It functions as a part. Further, the pachinko gaming machine 1 causes the operation switch 860a to function as an operation unit for canceling an error that has occurred with respect to the game ball payout operation after the predetermined time has elapsed. Here, even if the hall clerk is not familiar with the operation of the pachinko machine, as long as he remembers the position of the operation switch 860a on the back of the gaming machine, If a predetermined time has elapsed since the power was turned on, the function of canceling the error that occurred in relation to the game ball payout operation is exhibited, while the predetermined time from the time the power is turned on according to the timing of operating the operation switch 860a. If it is within the time, the function of initializing the storage unit can be exhibited. Therefore, even if an error occurs in such a gaming machine, the hall clerk can take appropriate action without hesitating the switch operation by improving the efficiency of the switch operation at the time of handling the error, so that the game is interrupted. The game can be resumed before the played player loses his willingness to play.

[17-12. Exchange of various signals with CR unit]
Next, the CR communication process of step S554 in the payout control unit main process of the payout control part power-on process of FIG. 53 will be described using a timing chart. In this CR communication process, various signals are exchanged between the payout control board 4110 and the CR unit 6 shown in FIG. First, signal processing at the time of payout operation by ball lending will be described, and subsequently input signal confirmation processing from the CR unit 6 will be described. Here, the number of game balls of 200 yen as the amount (in this embodiment, 50 balls, and the payout operation of 25 balls of 100 yen as the amount is performed twice) is used as the number of rented balls. The case of paying out to the upper plate 301 and the lower plate 302 shown in FIG. 7 will be described. The BRQ signal, the BRDY signal, and the CR connection signal from the CR unit 6 are read out from the input information storage area of the payout control built-in RAM and stored in the read input information. Confirms the logical state of the BRQ signal, the BRDY signal, and the CR connection signal from the input information every 2 ms that is the interrupt timer period.

[17-12-1. Signal processing during payout by ball lending]
The payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110 reads out the PRDY signal output setting information from the CR communication information storage area of the payout control built-in RAM, and the read PRDY signal output setting information pays out a rental ball. When the logic state of the PRDY signal that indicates that the payout operation is possible is set, as shown in FIG. 67 (d), the payout operation for paying out the rental ball is possible. In order to transmit the signal, the logic of the PRDY signal is set to HI, that is, raised and held, and output from the output terminal of the predetermined output port of the payout control unit MPU4120a of the payout control unit 4120. It outputs to CR unit 6 via board 869 (timing H0). In this state, for example, when the player pushes the ball rental button 361 of the ball rental unit 360 shown in FIG. 2, the ball rental switch 365b is switched on (turned on). The operation signal is input as TDS shown in FIG. 16 from the frequency display board 365 to the CR unit 6 via the game ball lending device connection terminal board 869. As shown in FIG. 67 (a), the CR unit 6 to which this TDS is input pays out the number of game balls of 200 yen as the amount of money to the upper plate 301 and the lower plate 302 as the number of lent balls. The ball request signal BRDY is output from the CR unit 6 to the payout control board 4110 (payout control MPU 4120a) via the gaming ball lending device connection terminal plate 869, and the signal is raised and held (timing H1). . This BRDY is input as a BRDY signal to an input terminal of a predetermined input port of the payout control MPU 4120a.

  As shown in FIG. 67 (b), the payout control MPU 4120a to which this BRDY signal is input has a payout control program from the timing H1 to the lending request monitoring time HA (in this embodiment, from 20 milliseconds (ms) to 58 ms. A predetermined number of balls (in this embodiment, 25 balls) in one payout operation from the CR unit 6 through the gaming device lending device connection terminal plate 869 until the time elapses. , Which corresponds to 100 yen as a monetary amount) is monitored whether or not a BRQ which is a single payout operation start request signal for paying out the money rises.

  The CR unit 6 pays out the number of game balls of 100 yen out of the number of game balls of 200 yen as the amount of money to the upper plate 301 and the lower plate 302 as the number of rented balls. ), The BRQ is output from the CR unit 6 to the CR unit 6 via the lending device connection terminal plate 869 such as a game ball until the rental request monitoring time HA elapses from the timing H1, and the signal is Start up and hold (timing H2). This BRQ is input as a BRQ signal to an input terminal of a predetermined input port of the payout control MPU 4120a.

  As shown in FIG. 67 (c), the payout control MPU 4120a, when the BRQ signal rises from the timing H1 until the lending request monitoring time HA elapses, from the timing H2 to the BRQ request acknowledgment ACK monitoring time HB (in this embodiment, Is set to 20 ms ± 1 ms), the payout control MPU 4120a holds the logic of the EXS signal HI, that is, keeps the raised state, in order to notify that one payout operation has started. Is output from the output terminal of the predetermined output port and output to the CR unit 6 as EXS via the lending device connection terminal plate 869 such as a game ball (timing H3).

  As shown in FIG. 67 (b), the CR unit 6 to which this EXS is input has a lending instruction monitoring time HC (in this embodiment, set to 20 ms to 58 ms) from the timing H3. The BRQ that has been started up and held from timing H2 is output from the CR unit 6 to the payout control board 4110 via the gaming ball lending device connection terminal plate 869, and the signal is lowered and held (timing H4).

  As shown in FIG. 67 (c), the payout control MPU 4120a performs one payout operation from the timing H4 until the payout monitoring time HD (in this embodiment, the ball payout time is set) elapses. Then, only the predetermined number of rented balls, that is, the number of game balls for 100 yen is paid out to the upper plate 301 and the lower plate 302 as the number of lent balls. When the payout monitoring time HD elapses, the EXS signal that has been raised and held from the timing H3 is output from the output terminal of a predetermined output port of the payout control MPU 4120a while keeping its logic at LOW, that is, in the lowered state. , EXS is output to the CR unit 6 via the gaming ball rental device connecting terminal plate 869 (timing H5).

  Since the CR unit 6 pays out the remaining number of game balls for 100 yen out of the number of game balls for 200 yen as a monetary amount to the upper plate 301 and the lower plate 302 as shown in FIG. ), The BRQ is transferred from the CR unit 6 to the lending device connection terminal board such as a game ball until the next request confirmation timing HE (in this embodiment, the maximum is set to 268 ms) from the timing H5. 869 is output to the payout control board 4110 (payout control MPU 4120a), and the signal is raised and held (timing H6).

  Similarly, when the payout control MPU 4120a pays out the remaining 100 yen of game balls to the upper plate 301 or the lower plate 302 using the method described above, as shown in FIG. 67 (c). The EXS signal that has been raised and held is set to the logic level LOW, that is, held in the lowered state, and is output from the output terminal of the predetermined output port of the payout control MPU 4120a. It outputs to CR unit 6 via board 869 (timing H7).

  As shown in FIG. 67 (a), the CR unit 6 starts from the timing H1 until the CR unit lending completion monitoring time HF (in this embodiment, the maximum setting is 268 ms) elapses from the timing H7. The raised BRDY is output from the CR unit 6 to the payout control board 4110 (payout control MPU 4120a) via the gaming ball lending device connection terminal plate 869, and the signal is lowered and held (timing H8).

  The above-described lending request monitoring time HA, BRQ request acknowledgment ACK monitoring time HB, lending instruction monitoring time HC, payout monitoring time HD, next request confirmation timing HE, CR unit lending completion monitoring time HF are the payout control shown in FIG. The time is counted by the timer update process in step S552 in the power-on process (payout control part main process).

  The payout control MPU 4120a does not communicate with the CR unit 6 when a ball breakage, ball rounding, counting switch error, retry error, full tank, etc. occurs (the logic of BRDY from the CR unit 6). 67), the PRDY signal that is raised and held from the timing H1 is set to the logic level LOW, that is, in the lowered state, as shown in FIG. 67 (d). It is held and output from the output terminal of a predetermined output port of the payout control MPU 4120a, and is output as PRDY to the CR unit 6 via the game ball lending device connection terminal plate 869 (timing H9). On the other hand, when communicating with the CR unit 6 (when the BRDY logic from the CR unit 6 is HI, that is, rising and being held), although not shown, the logic state of the EXS signal is maintained and paid out. It outputs from the output terminal of the predetermined | prescribed output port of control MPU4120a, and outputs to CR unit 6 via the lending apparatus connection terminal board 869, such as game balls, as EXS. “Keep the logic state of the EXS signal” means that when the logic of the EXS signal is LOW (the EXS signal is held down), the logic of the EXS signal is HI. The logical HI is maintained when the EXS signal is held up.

  In this way, the CR unit 6 exchanges various signals with the payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110, and the payout control MPU 4120a sets the number of game balls for 200 yen as the amount of money as 100. By performing the payout operation of 25 balls for the yen twice, the game balls having the number of lent out balls of 50 are paid out to the upper plate 301 and the lower plate 302. A hall clerk or the like operates a setting unit (not shown) provided on the front side of the CR unit 6, and for example, the number of game balls for 100 yen as the amount of money is used for the upper plate 301 or When set to pay out to the lower plate 302, the payout control MPU 4120a performs a payout operation of 25 balls for 100 yen as a monetary amount, and the number of game balls for 500 yen as a monetary number When set to pay out to the upper plate 301 and the lower plate 302, the payout control MPU 4120a performs the payout operation of 25 balls of 100 yen as the amount of money five times, and sets the number of game balls of 1000 yen as the amount of money. When the number of rented balls is set to be paid out to the upper plate 301 or the lower plate 302, the payout control MPU 4120a performs the payout operation of 25 balls for 100 yen as the amount of money 10 times.

[17-12-2. Checking input signal from CR unit]
The payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110 is configured such that the CR unit 6 performs BRQ via the CR unit 6 via the lending device connection terminal board 869 such as a game ball even when the lending request monitoring time HA has elapsed. When the signal is not started up or when the above-described lending instruction monitoring time HC elapses, the CR unit 6 connects BRDY to the lending device such as a game ball from the CR unit 6. The CR unit 6 outputs the BRQ from the CR unit 6 to the payout control board 4110 via the terminal board 869, even when the signal has not fallen or when the next request confirmation timing HE described above has elapsed. A ball or other lending device connection terminal board 869 is used to output to the payout control board 4110 and the signal is not started up, or as described above. Even after the R unit lending completion monitoring time HF has elapsed, the CR unit 6 outputs BRDY to the payout control board 4110 from the CR unit 6 via the lending device connection terminal board 869 such as a game ball, and the signal is lowered. If not, the above-described PRDY and EXS are used to check whether BRQ and BRDY are normal. Specifically, as shown in FIGS. 67 (e) and 67 (f), the payout control MPU 4120a determines that BRQ and BRDY are not normal (timing J0), and starts a predetermined period JA (in this embodiment) from this timing J0. , 200 ms ± 1 ms), the logic of the PRDY signal is set to LOW, that is, the state of being lowered is held and output from the output terminal of the predetermined output port of the payout control MPU 4120a of the payout control unit 4120 Then, PRDY is output to the CR unit 6 through the gaming ball lending device connection terminal plate 869, and the logic of the EXS signal is set to LOW, that is, the state of being lowered is held and the predetermined output port of the payout control MPU 4120a Is output to the CR unit 6 through the rental device connection terminal plate 869 such as a game ball. To force (timing J1).

  Subsequently, the payout control MPU 4120a sets the logic of the PRDY signal held down and held from the timing J1 after the elapse of a predetermined period JB (in this embodiment, 200 ms ± 1 ms) from the timing J1 as the logic HI. In other words, it is held in the raised state, output from the output terminal of a predetermined output port of the payout control MPU 4120a, and output as PRDY to the CR unit 6 via the gaming ball lending device connection terminal plate 869 (timing J2 ).

  Subsequently, the payout control MPU 4120a sets the logic of the PRDY signal raised and held from the timing J2 after the elapse of a predetermined period JC from the timing J2 (in this embodiment, 100 ms ± 1 ms) as its logic LOW. In other words, it is held in a lowered state, outputted from the output terminal of a predetermined output port of the payout control MPU 4120a, and outputted as PRDY to the CR unit 6 via the game ball lending device connection terminal plate 869 (timing J3). ).

  Subsequently, after the elapse of a predetermined period JD (in this embodiment, 100 ms ± 1 ms) from the timing J3, the payout control MPU 4120a sets the logic of the PRDY signal held down from the timing J3 as HI. In other words, it is held in the raised state, output from the output terminal of the predetermined output port of the payout control MPU 4120a, and output as PRDY to the CR unit 6 via the game ball lending device connection terminal plate 869 (timing J4). ).

  Subsequently, the payout control MPU 4120a sets the logic of the PRDY signal raised and held from the timing J4 after the elapse of a predetermined period JE (in this embodiment, 100 ms ± 1 ms) from the timing J4 as the logic LOW. In other words, it is held in a lowered state, outputted from the output terminal of a predetermined output port of the payout control MPU 4120a, and outputted as PRDY to the CR unit 6 via the gaming ball lending device connection terminal plate 869 (timing J5). ).

  Subsequently, the payout control MPU 4120a sets the logic of the PRDY signal held down and held from the timing J5 after the elapse of a predetermined period JF from the timing J5 (in this embodiment, 10000 ms ± 1 ms) as the logic HI. In other words, it is held in the raised state, output from the output terminal of a predetermined output port of the payout control MPU 4120a, and output as PRDY to the CR unit 6 via the gaming ball lending device connection terminal plate 869 (timing J6). ).

  The predetermined period JA to the predetermined period JF described above are timed by the timer update process in step S552 in the payout control unit power-on process (payout control unit main process) shown in FIG.

[18. Various control processing of peripheral control board]
Next, various processes of the peripheral control board 4140 that receive various commands from the main control board 4100 (main control MPU 4100a) shown in FIG. 14 will be described with reference to FIGS. 68 is a flowchart showing an example of the peripheral control unit power-on process, FIG. 69 is a flowchart showing an example of the peripheral control unit V blank interrupt process, and FIG. 70 shows an example of the peripheral control unit 1 ms timer interrupt process. 71 is a flowchart showing an example of the peripheral control unit command reception interrupt process, FIG. 72 is a flowchart showing an example of the peripheral control unit power failure warning signal interrupt process, and FIG. 73 shows the transition to the power saving mode during power recovery. 74 is a flowchart showing an example of the determination process, FIG. 74 is a flowchart showing an example of the power consumption monitoring process, and FIG. 75 shows the relationship between the value set as the master volume value for power suppression and the power consumption suppression stage. The figure (a) to show, the relationship between the brightness | luminance set as a brightness | luminance for electric power suppression, and an electric power consumption suppression stage is shown FIG. 76 is a flowchart showing an example of the LOCKN signal history creation process, FIG. 77 is a flowchart showing an example of the connection failure determination process, and FIG. 78 is a flowchart showing an example of the connection recovery process. 79 is a timing chart for explaining the timing for outputting a connection confirmation signal to the INIT terminal of the upper plate side liquid crystal transmitter IC.

  As shown in FIG. 17, the peripheral control board 4140 includes a peripheral control unit 4150 and a liquid crystal and sound control unit 4160. Here, various control processes of the peripheral control unit 4150 will be described. First, the peripheral control unit power-on process will be described, followed by peripheral control unit V blank interrupt processing, peripheral control unit 1 ms timer interrupt processing, peripheral control unit command reception interrupt processing, peripheral control unit power failure warning signal interrupt processing, power recovery The power saving mode transition determination processing, power consumption monitoring processing, LOCKN signal history creation processing, connection failure determination processing, and connection recovery processing will be described. The power saving power saving mode transition determination process is the process of step S1004 in the peripheral control unit power-on process described later, and the power consumption monitoring process is in the peripheral control unit steady process of the peripheral control unit power-on process described later. The LOCKN signal history creation process, which is the process of step S1027, is executed as one process of the drawing state information acquisition process of step S1110 in the peripheral control unit 1 ms timer interrupt process described later. The connection failure determination process and the connection recovery process are described later. This is executed as one of the warning processes in step S1024 in the peripheral control part steady process of the peripheral control part power-on process, and the connection recovery process is executed following the connection failure determination process. In the present embodiment, the peripheral control unit power failure warning signal interrupt processing is set as the highest priority as the interrupt processing priority, followed by power consumption suppression signal interrupt processing, peripheral control unit 1 ms timer interrupt processing, peripheral control unit command reception. Interrupt processing and peripheral control section V blank interrupt processing are set in this order.

[18-1. Various control processes of peripheral control unit]
[18-1-1. Peripheral control unit power-on processing]
First, the peripheral control unit power-on process will be described with reference to FIG. When the pachinko gaming machine 1 is powered on, the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 17 performs a peripheral control unit power-on process as shown in FIG. When the peripheral control unit power-on process is started, the effect control program performs an initial setting process under the control of the peripheral control MPU 4150a (step S1000). In this initial setting process, the production control program performs a process of initializing the peripheral control MPU 4150a itself, a hot start / cold start determination process, a process of setting a wait timer after reset, and the like. The peripheral control MPU 4150a first performs a process of initializing itself. The time required for the process of initializing the peripheral control MPU 4150a is on the order of microseconds (μs), and the peripheral control MPU 4150a is initialized in a very short time. be able to. As a result, the peripheral control MPU 4150a is output from the main control board 4100, for example, in the peripheral control unit command reception interrupt processing described later, as shown in FIGS. 45 and 46, when the interrupt permission is set. Various commands such as commands relating to the control of game effects and commands relating to the state of the pachinko gaming machine 1 can be received.

  In the hot start / cold start determination process, for the peripheral control RAM 4150c shown in FIG. 18, effect backup information (1fr) that is backed up in Bank1 (1fr) and Bank2 (1fr) in the backup first area 4150cb. ) And the production backup information (1 ms), which is the contents backed up in Bank 1 (1 ms) and Bank 2 (1 ms), are compared, and Bank 3 (1 fr) and Bank 4 (1 fr) in the backup second area 4150 cc are compared. The production backup information (1fr), which is the content that is backed up at the same time, is compared, and the production backup information (the content that is backed up in Bank3 (1 ms) and Bank4 (1 ms)) ( ms), and when the compared contents match, the contents stored in Bank1 (1fr) with respect to Bank0 (1fr), which is a normally used storage area of the peripheral control RAM 4150c shown in FIG. The production backup information (1fr) and the production backup information (1ms) stored in Bank1 (1ms) with respect to Bank0 (1ms) are copied back to make a hot start, When the contents do not match (that is, when they do not match), the value 0 is forcibly written to Bank0 (1fr) and Bank0 (1 ms), which are normally used storage areas of the peripheral control RAM 4150c. And cold start.

  In the hot start / cold start determination processing, the effect backup information which is the contents backed up in the Bank 1 (SRAM) and the Bank 2 (SRAM) in the backup first area 4150 db also for the peripheral control SRAM 4150 d shown in FIG. (SRAM) is compared, and production backup information (SRAM), which is the contents backed up in Bank 3 (SRAM) and Bank 4 (SRAM), in the backup second area 4150 dc is compared. When the compared contents match, the production backup information (SRAM) which is the contents stored in Bank 0 (SRAM) with respect to Bank 0 (SRAM) which is the storage area normally used in the peripheral control SRAM 4150d shown in FIG. ) Is copied back to make a hot start, while when the compared contents do not match (that is, when they do not match), the value is relative to Bank0 (SRAM), which is a storage area normally used by the peripheral control SRAM 4150d. A 0 is forcibly written to make a cold start. Following such a hot start or cold start, the value 0 is forcibly written to the backup unmanaged work area 4150cf of the peripheral control RAM 4150c shown in FIG. The peripheral control MPU 4150a, after performing this initialization setting process, outputs a clear signal to the peripheral control built-in WDT 4150af shown in FIG. 18 and the peripheral control external WDT 4150e shown in FIG. 17, and resets to the peripheral control MPU 4150a. It is made so that it won't be applied.

  Subsequent to step S1000, the effect control program performs current time information acquisition processing (step S1002). In this current time information acquisition processing, calendar information specifying the date and time and time information specifying the hour, minute and second are acquired from the RTC built-in RAM 4165aa of the RTC 41654a of the RTC control unit 4165 shown in FIG. In the RTC information acquisition storage area 4150cad of the peripheral control RAM 4150c shown in FIG. 4, the current calendar information is set in the calendar information storage unit and the current time information is set in the time information storage unit.

  In the present embodiment, the peripheral control MPU 4150a acquires calendar information and time information from the RTC built-in RAM 4165aa of the RTC 4165a only once when the power is turned on. In addition, the peripheral control MPU 4150a outputs a clear signal to the peripheral control built-in WDT 4150af and the peripheral control external WDT 4150e after performing this current time information acquisition processing so that the peripheral control MPU 4150a is not reset.

  Subsequent to step S1002, a power saving power saving mode transition determination process is performed (step S1004). This power saving power saving mode transition determination process will be described in detail later. Based on the power consumption status history information stored in the power consumption status history RAM 4150f shown in FIG. Immediately before disconnection), the power situation consumed by the pachinko machine 1 is ascertained at the time of power recovery, and it is determined whether or not to enter the power saving mode at the time of power recovery that suppresses the power consumed by the pachinko machine 1. When shifting to the power saving mode, the setting of reducing the volume of the production sound flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, Settings are made such that the brightness of the plurality of LEDs provided on the decoration board and the plurality of LEDs provided on each decoration board of the game board 4 are reduced.

  Subsequent to step S1004, the effect control program sets a value 0 to the V blank signal detection flag VB-FLG (step S1006). This V blank signal detection flag VB-FLG is a flag for determining whether or not to execute a peripheral control unit steady process to be described later, and has a value of 1 when the peripheral control unit steady process is executed. Is set to 0 when not executing. The V blank signal detection flag VB-FLG, which will be described later, is executed when a V blank signal indicating that the screen data from the peripheral control MPU 4150a can be received is input from the sound source built-in VDP 4160a. The value 1 is set in the part V blank signal interrupt processing. In step S1006, the V blank signal detection flag VB-FLG is initialized once by setting the value 0 to the V blank signal detection flag VB-FLG. The peripheral control MPU 4150a outputs a clear signal to the peripheral control built-in WDT 4150af and the peripheral control external WDT 4150e after setting the value 0 to the V blank signal detection flag VB-FLG so that the peripheral control MPU 4150a is not reset. Yes.

  Subsequent to step S1006, the effect control program determines whether or not the V blank signal detection flag VB-FLG is 1 (step S1008). When the V blank signal detection flag VB-FLG is not 1 (value 0), the process returns to step S1008 and it is repeatedly determined whether or not the V blank signal detection flag VB-FLG is 1. By repeating such a determination, the process waits until the peripheral control unit steady process is executed. The peripheral control MPU 4150a outputs a clear signal to the peripheral control built-in WDT 4150af and the peripheral control external WDT 4150e after determining whether or not the V blank signal detection flag VB-FLG is 1, and resets to the peripheral control MPU 4150a. To prevent it

  When the V blank signal detection flag VB-FLG has a value of 1 in step S1008, that is, when the peripheral control unit steady process is executed, a value 1 is first set to the steady process flag SP-FLG (step S1009). The steady processing flag SP-FLG is set to a value of 1 when the peripheral control unit steady processing is being executed, and to a value of 0 when the peripheral control unit steady processing is completed.

  Subsequent to step S1009, the effect control program performs 1 ms interrupt timer activation processing (step S1010). In this 1 ms interrupt timer starting process, a 1 ms interrupt timer for executing a later-described peripheral control unit 1 ms timer interrupt process is started, and the number of times this 1 ms interrupt timer is started and the peripheral control unit 1 ms timer interrupt process is executed. The value 1 is set in the 1 ms timer interrupt execution count STN for counting the 1 ms timer interrupt execution count STN. This 1 ms timer interrupt execution count STN is updated by the peripheral control unit 1 ms timer interrupt processing.

  Subsequent to step S1010, the effect control program performs lamp data output processing (step S1012). In this ramp data output process, the effect control program performs DMA to a plurality of game board side peripheral control MPU control target decorative boards that are controlled by the peripheral control MPU 4150a directly among the decorative boards of the game board 4. Serial serial transmission is performed. Here, the peripheral I / O port continuous transmission for the game board side decorative board is performed using the peripheral control DMA controller 4150ac of the peripheral control MPU 4150a shown in FIG. When the serial transmission on the gaming board side decorative board serial I / O port is started, the transmission data storage for the gaming board side peripheral control MPU control target LED in the peripheral control RAM 4150c externally attached to the peripheral control MPU 4150a shown in FIG. A game board side for outputting a lighting signal, a blinking signal, or a gradation lighting signal to a plurality of LEDs (decorative LEDs) provided on each of the plurality of gaming board side peripheral control MPU control target decoration boards in the area 4150caa The light emission data SL-DAT is created and set in the lamp data creation process described later.

  The peripheral control CPU core 4150aa of the peripheral control MPU 4150a shown in FIG. 18 designates transmission of the serial I / O port for the game board side decorative board as a request factor of the peripheral control DMA controller 4150ac, and controls the game board side peripheral control MPU. The first byte of the game board side light emission data SL-DAT stored at the head address of the LED transmission data storage area 4150caa is played via the external bus 4150h, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai. Transfer and write to the transmission buffer register of the board side decorative board serial I / O port. Thereby, the serial I / O port for the game board side decorative board transfers the written data of the transmission buffer register to the transmission shift register, and synchronizes with the frame side light emission clock signal STL-CLK. Start transmitting byte data bit by bit.

  The peripheral control DMA controller 4150ac is triggered by a transmission interrupt request for the game board side decorative board serial I / O port (in this embodiment, the peripheral I / O port serial board I / O port). The 1-byte data written in the transmission buffer register is transferred to the transmission shift register, and the transmission buffer register is empty because the 1-byte data disappears.), The peripheral control CPU core 4150aa is the bus. When the game board side peripheral control MPU control target LED transmission data storage area 4150caa is not used, the remaining game board side light emission data SL-DAT stored in the LED is sent byte by byte, the external bus 4150h, and the peripheral control bus controller. Game board side decorative board via 4150ad and peripheral bus 4150ai By transferring and writing to the transmission buffer register of the serial I / O port, the serial I / O port for the game board side decorative board transfers the written data of the transmission buffer register to the transmission shift register, and the frame side light emission In synchronization with the clock signal STL-CLK, transmission of 1-byte data of the transmission shift register is started bit by bit, and continuous transmission is performed by the game board side decorative board serial I / O port.

  In the lamp data output process, the effect control program executes DMA serial to a plurality of frame side peripheral control MPU control target decorative boards that are controlled by the peripheral control MPU 4150a among the decorative boards of the door frame 5. Perform continuous transmission processing. Also here, the frame side decorative board serial I / O port continuous transmission is performed using the peripheral control DMA controller 4150ac of the peripheral control MPU 4150a. When the frame side decorative board serial I / O port continuous transmission is started, the frame side peripheral control MPU control target LED transmission data storage area 4150cab of the peripheral control RAM 4150c externally attached to the peripheral control MPU 4150a shown in FIG. In addition, frame side light emission data STL-DAT for outputting lighting signals, blinking signals, or gradation lighting signals to a plurality of LEDs (decorative LEDs) provided on each of the plurality of frame side peripheral control MPU control target decorative boards Is created and set in the ramp data creation process described later.

  The peripheral control CPU core 4150aa of the peripheral control MPU 4150a designates transmission of the frame side decorative board serial I / O port as a request factor of the peripheral control DMA controller 4150ac, and transmits the frame side peripheral control MPU control target LED transmission data storage area 4150cab. The first byte of the frame side light emission data STL-DAT stored at the head address of the frame side decorative board serial I / O via the external bus 4150h, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai Transfer and write to the port's transmit buffer register. As a result, the frame side decorative board serial I / O port transfers the data of the written transmission buffer register to the transmission shift register, and synchronizes with the frame side light emission clock signal STL-CLK. The data starts to be transmitted bit by bit.

  The peripheral control DMA controller 4150ac uses the frame-side decorative board serial I / O port transmission interrupt request as a trigger (in this embodiment, the frame-side decorative board serial I / O port transmission buffer). 1 byte data written to the register is transferred to the transmission shift register, and the transmission buffer register is empty because the 1 byte data disappears.), The peripheral control CPU core 4150aa uses the bus. If not, the remaining frame side emission data STL-DAT stored in the frame side peripheral control MPU control target LED transmission data storage area 4150cab is byte by byte, the external bus 4150h, the peripheral control bus controller 4150ad, and the peripheral Serial I / O port for frame side decorative board via bus 4150ai The frame side decorative board serial I / O port transfers the written data in the transmission buffer register to the transmission shift register, and the frame side light emission clock signal STL-CLK. 1 byte data of the transmission shift register is started to be transmitted one bit at a time, and is continuously transmitted by the frame side decorative board serial I / O port.

  Subsequent to step S1012, the effect control program performs an operation unit monitoring process (step S1014). In this operation unit monitoring process, in the operation unit information acquisition process in the peripheral control unit 1 ms timer interruption process described later, the dial operation unit 401 is based on detection signals from various detection switches provided in the operation unit 400 shown in FIG. Rotation (rotation direction) and various information obtained by operating the pressing operation unit 405 (for example, rotation of the dial operation unit 401 created based on detection signals from various detection switches provided in the operation unit 400 (rotation direction) ) History information, operation history information of the pressing operation unit 405, etc.) Based on the operation unit information acquisition storage area 4150cai of the peripheral control RAM 4150c shown in FIG. Monitor the presence or absence of operation of the unit 405, Appropriately determined whether to reflect the state of operation of the pressure operation unit 405 to the game effects.

  Subsequent to step S1014, the effect control program performs display data output processing (step S1016). In this display data output process, the drawing data for one screen (one frame) generated on the built-in VRAM of the sound source built-in VDP 4160a in the display data creation process described later is transmitted from the channels CH1 and CH2 shown in FIG. Output. Thereby, various screens (images) corresponding to one light guide plate used as a backlight among the plurality of light guide plates provided in the game board side effect display unit 1900 shown in FIG. 10 are drawn (displayed) on the liquid crystal panel 5000e. In addition, among the decorative boards of the game board 4, a plurality of LEDs (decorative LEDs) provided on each of the plurality of game board side VDP control target decorative boards that are controlled by the sound source built-in VDP 4160a directly Are emitted in various light emission modes, and among each decorative board of the door frame 5, a plurality of LEDs provided on each of the plurality of frame side VDP controlled target decorative boards that are controlled by the built-in sound source VDP 4160a (Decoration LED) emits light in various light emission modes. In the display data output process, when the drawing exceeding the drawing capability of the sound source built-in VDP 4160a is performed, the output of the generated drawing data for one screen (one frame) from the channels CH1 and CH2 is canceled. It has become. Thus, the processing time can be prevented from being delayed. However, although a so-called frame drop occurs, it is accommodated in the speaker box 820 provided in the main body frame 3 shown in FIG. 2 and a speaker 130 provided on the door frame 5 shown in FIG.

  Subsequent to step S1016, the effect control program performs sound data output processing (step S1018). In this sound data output process, the effect control program outputs to the audio data transmission IC 4160c as audio data obtained by serializing sound data such as music and sound effects set in the sound source built-in VDP 4160a in the sound data creation process described later, In addition to music and sound effects, the sound data of notification sound and notification sound is output to the audio data transmission IC 4160c as serialized audio data. When the audio data transmission IC 4160c receives the serialized audio data from the sound source built-in VDP 4160a, the audio data transmission IC 4160c is directed toward the frame decoration drive amplifier board 194 as differential serial data using the right audio data as a plus signal and a minus signal. At the same time, the left audio data is transmitted toward the frame decoration drive amplifier board 194 as differential serial data having a plus signal and a minus signal. As a result, in addition to the stereo reproduction of music, sound effects and the like adapted to various effects from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, the notification sound and the notification sound Is also played in stereo.

  Subsequent to step S1018, the effect control program performs scheduler update processing (step S1020). In this scheduler update process, the effect control program updates various schedule data set in the schedule data storage area 4150cae of the peripheral control RAM 4150c shown in FIG. For example, in the scheduler update process, among the screen data arranged in time series constituting the screen generation schedule data set in the schedule data storage area 4150cae, what number screen data from the top screen data is stored in the sound source built-in VDP 4160a. The pointer is updated to indicate whether to output.

  In addition, in the scheduler update process, among the light emission data arranged in time series constituting the light emission mode generation schedule data set in the schedule data storage area 4150cae, what number of light emission data from the first light emission data is assigned to the plurality of LEDs. The pointer is updated in order to indicate whether the light emission mode is selected. Here, as described above, the light emission mode generation schedule data is provided on each decoration board (a plurality of game board side peripheral control MPU control target decoration boards, a plurality of game board side VDP control target decoration boards). In addition, the light emission mode generation schedule data for a plurality of LEDs and the plurality of LEDs provided on each decoration board (a plurality of frame side peripheral control MPU control target decoration boards and a plurality of frame side VDP control target decoration boards) of the door frame 5 The order of the light emission mode generation schedule data, the bite, and the light emission mode are respectively defined. Further, the light emission mode generation schedule data for the plurality of LEDs provided on each decorative board of the game board 4 includes the contents of the light guide plates provided in the game board side effect display unit 1900 in addition to the contents for defining the light emission mode. Among them, the contents for defining (designating) one light guide plate used as a backlight are also included in the light emission data and arranged in time series.

  Also, in the scheduler update process, sound data such as music and sound effects, sound data of notification sound and notification sound, which are arranged in time series constituting the sound generation schedule data set in the schedule data storage area 4150cae, is instructed. Of the sound command data, the pointer is updated in order to indicate what number of sound command data from the head sound command data is to be output to the built-in sound source VDP 4160a.

  In the scheduler update process, the drive data of the electric drive sources such as motors and solenoids arranged in time series constituting the electric drive source schedule data set in the schedule data storage area 4150cae is used from the head drive data. The pointer is updated to indicate what number of drive data is to be output. The drive data of the electric drive sources such as motors and solenoids arranged in time series constituting the electric drive source schedule data is a peripheral control unit 1 ms timer interrupt which is repeatedly executed every time a 1 ms timer interrupt described later occurs. It is updated by the motor and solenoid drive process in the process. In the motor and solenoid drive processing that is repeatedly executed each time this 1 ms timer interrupt occurs, an electric drive source such as a motor or solenoid is driven according to the drive data indicated by the pointer, and the next drive specified in time series is performed. The pointer is updated to the data, and the pointer is updated every time its own process is executed. In other words, since the drive data indicated by the pointer updated in the motor and solenoid drive processing is forcibly updated in the scheduler update processing, the pointer is originally instructed for some reason in the motor and solenoid drive processing. Even if other drive data is instructed from the drive data to be performed, it is forcibly updated so as to instruct the drive data that should be instructed originally in the scheduler update processing.

  Also, in the scheduler update process, the number of game balls to be paid out as prize balls arranged in time series constituting the schedule data for the main prize ball information output signal set in the schedule data storage area 4150cae is 10 balls. The number of output waveform data from the first output waveform data to be output among the output waveform data for generating a main prize ball information output signal that informs the hall computer as main prize ball information that the current value has been reached. The pointer is updated to indicate. The output waveform data arranged in time series constituting the schedule data for the main prize ball information output signal is the number of main prize balls in the peripheral control unit 1 ms timer interrupt process that is repeatedly executed every time a 1 ms timer interrupt occurs, which will be described later. Updated by information output process. In the main prize ball number information output process that is repeatedly executed every time this 1 ms timer interrupt occurs, the main prize ball information output signal is output to the external terminal board 784 in accordance with the output waveform data indicated by the pointer, and is specified in time series. The pointer is updated to the next output waveform data, and the pointer is updated every time its own processing is executed. That is, since the output waveform data indicated by the pointer updated in the main prize ball number information output process is forcibly updated in the scheduler update process, the pointer is temporarily changed in the main prize ball number information output process. Even if other output waveform data is instructed from the output waveform data that should be instructed for some reason, it is forcibly updated to instruct the output waveform data that should be instructed in the scheduler update processing. It has become.

  Subsequent to step S1020, the effect control program performs a received command analysis process (step S1022). In the received command analysis process, the effect control program receives various commands transmitted from the main control board 4100 in a peripheral control unit command reception interrupt process to be described later, and analyzes the received various commands. Various commands from the main control board 4100 are received by the peripheral control unit command reception interrupt processing and stored in the reception command storage area 4150cac of the peripheral control RAM 4150c. In this reception command analysis processing, the effect control program Analyzes various commands stored in the received command storage area 4150cac. The effect control program stores screen generation schedule data, light emission mode generation schedule data, sound generation schedule data, electrical drive source schedule data, and the like, based on the analyzed various commands, in the peripheral control ROM 4150b of the peripheral control unit 4150. Alternatively, it is extracted from various control data copy areas 4150ce of the peripheral control RAM 4150c and set in the schedule data storage area 4150cae of the peripheral control RAM 4150c.

  In addition, in the effect control program, the command from the main control board 4100 received in the peripheral control unit command interrupt process is, for example, a start opening prize command for instructing start of a starting opening prize effect, the number of ordinary symbols held A normal symbol storage command for identifying (0 to 4), a symbol synchronization effect start command for instructing the start of a symbol synchronization effect, a symbol storage command that is output when the number of start suspension changes, It is analyzed whether or not it is a frame state 1 command indicating the content of full tank shown in FIG. 46, or a large winning port 1 count display command (big winning port count command) output every time a game ball is received. Recognize which gaming state is currently in effect.

  Various commands from the main control board 4100 are received by the peripheral control unit command reception interrupt process and stored in the reception command storage area 4150cac of the peripheral control RAM 4150c shown in FIG. The effect control program analyzes various commands stored in the received command storage area 4150cac. The various commands shown in FIG. 45 are classified into the various commands classified as related to the special figure 1 tuning effect, the various commands classified as related to the special figure 2 synchronous effect, the various commands classified as related to the jackpot, and the power-on. 46, various commands categorized in relation to ordinary drawing effect, various commands categorized in relation to ordinary electric role effect, various commands categorized in notification display shown in FIG. 46, and status display There are various commands, various commands classified as test-related, and various commands classified into others.

  Subsequent to step S1022, the effect control program performs warning processing (step S1024). In this warning process, when the command analyzed by the effect control program in the received command analysis process in step S1022 as described above includes various commands classified into the notification display shown in FIG. The screen generation schedule data, the light emission mode generation schedule data, the sound generation schedule data, the electrical drive source schedule data, and the like set in the abnormality display mode for executing the abnormality notification are stored in the peripheral control unit 4150. It is extracted from the various control data copy areas 4150ce of the peripheral control ROM 4150b or the peripheral control RAM 4150c and set in the schedule data storage area 4150cae of the peripheral control RAM 4150c. In the warning process, when multiple abnormalities occur at the same time, the abnormality notification is performed in the order of priority registered in advance, and the transition to other abnormality notifications remaining after the abnormality is resolved automatically It is supposed to be. This allows you to monitor multiple anomalies at the same time without losing the information that an anomaly has occurred due to the occurrence of another anomaly after the occurrence of the anomaly but before resolving the anomaly Can do.

  Next, following step S1024 described above, the effect control program performs main prize ball number information output determination processing (step S1025). In this main award ball number information output determination process, when the effect control program is a main award ball number information output command classified in the other shown in FIG. 46, the command analyzed in the received command analysis process of step S1022 Based on the value of the peripheral control side main award ball number information output determination counter, the main award that informs the hall computer as main award ball information that the number of game balls to be paid out as 10 award balls has reached 10 It is determined whether or not to output a sphere information output signal to the external terminal board 784. The peripheral control side main prize ball number information output determination counter is used as a prize ball based on the other main prize ball number information output command shown in FIG. The number of game balls to be paid out is counted and is updated in a prize ball schedule information storage area (not shown) of the peripheral control RAM 4150c. Since the main prize ball number information output command classified into others shown in FIG. 46 is to notify that the number of game balls to be paid out as a prize ball has reached 10 as described above. When this main prize ball number information output command is received, the value 10 is added to the value of the peripheral control side main prize ball number information output determination counter, and the value is stored and updated in a prize ball schedule information storage area (not shown) of the peripheral control RAM 4150c. It has become so.

  In the main prize ball number information output determination process, the effect control program is for determining the main prize ball number information output at power-on when the command analyzed in the received command analysis process in step S1022 is classified into the power-on shown in FIG. When it is a counter notification command, the main control board 4100 is provided in the game board 4 based on the contents instructed by the power-on main prize ball number information output determination counter notification command. Main counts the number of game balls to be paid out as prize balls based on the game balls entered in various prize openings such as 2101, second start opening 2102, general prize opening 2104, 2201, and big prize opening 2103 While the value of the winning ball number information output determination counter is set as the initial value of the peripheral control side main winning ball number information output determination counter, step S When the command analyzed in the received command analysis process 022 is a main prize ball number information output command classified into the other shown in FIG. 46, the main prize ball number information output command is a game scheduled to be paid out as a prize ball. Since the number of balls has reached ten, the value 10 is added to the value of the peripheral control side main prize ball number information management counter.

  In the main prize ball number information output determination process, the effect control program determines whether the command analyzed in the received command analysis process in step S1022 is classified into the power-on state shown in FIG. When the power supply is turned on, the main control board 4100 is provided on the game board 4 based on the content designated by the power-on main prize ball number information output determination counter notification command. The first start shown in FIG. The number of game balls to be paid out as prize balls is counted based on the game balls entered in the various prize openings such as the mouth 2101, the second start opening 2102, the general prize opening 2104, 2201, and the big prize opening 2103. When setting the value of the main prize ball number information output judgment counter as the initial value of the peripheral control side main prize ball number information output judgment counter Based on the time information acquired in the current time information acquisition process in step S1002 and set in the time information storage unit in the RTC information acquisition storage area 4150cad of the peripheral control RAM 4150c shown in FIG. When it is determined that the power to the gaming machine 1 is turned on (or the power to the pachinko island facility where the pachinko gaming machine 1 is installed), the peripheral control side main prize ball number information management counter Is forcibly reset and set to a default value to return the value to 0 (zero) as an initial value and store and update in a prize ball schedule information storage area (not shown) of the peripheral control RAM 4150c (for example, reception in step S1022) The command analyzed in the command analysis process is classified into power-on shown in FIG. This is a counter notification command for determining the main prize ball number information output at the time of turning on, and the counter notification command for determining the main prize ball number information output at the time of turning on the power indicates that the value of the counter for main prize ball number information output determination is the value 9. In the case of the contents shown, even if this value 9 is set as the initial value of the peripheral control side main prize ball number information output determination counter, it is reset and returned to the default value 0 (zero) as the initial value. As a result, if the command analyzed in the received command analysis processing in step S1022 is the main prize ball number information output command classified into the other shown in FIG. Every time it is received, the value 10 is added to the value of the peripheral control side main prize ball number information output determination counter, that is, on the main control board 4100 side. The value of the main prize ball number information output determination counter updated in this manner is the same as the value of the peripheral control side main prize ball number information output determination counter updated on the peripheral control board 4140 side. ) On the other hand, when it is determined that the power supply to the pachinko machine 1 is not turned on to start the hall operation, but the power is restored due to a power failure or a momentary power interruption during the hall operation. The value of the peripheral control side main prize ball number information management counter is not reset to the initial value by resetting the value of the peripheral control side main prize ball number information management counter to the default value, and the value of the peripheral control side main prize ball number information management counter (For example, the command analyzed in the received command analysis process in step S1022 is the power-on main prize ball number information output determination counter notification command classified into power-on shown in FIG. When the main prize ball number information output determination counter notification command is the content indicating that the value of the main prize ball number information output determination counter is the value 9 This value 9 is set as the initial value of the peripheral control side main prize ball number information output determination counter, whereby the command analyzed in the received command analysis processing in step S1022 is classified into the other shown in FIG. When it is a main prize ball number information output command, every time this main prize ball number information output command is received, a main prize ball number information output judgment value which is the value of the peripheral control side main prize ball number information output judgment counter The value 10 is added to the value 9 set as the counter value, that is, the value of the main prize ball number information output judgment counter updated on the main control board 4100 side and the peripheral control board 4140 side. The value of the updated peripheral control side main prize ball number information output determination counter is not the same value).

  In the main prize ball number information output determination process, the effect control program determines the value of the peripheral control side main prize ball number information management counter based on the added value of the peripheral control side main prize ball number information management counter. When the number exceeds 10, that is, when the number of game balls to be paid out as a prize ball has reached ten, a main prize ball information output signal is transmitted to the hall computer as main prize ball information. The main prize ball information output signal schedule data to be output to the external terminal board 784 is set in the schedule data storage area 4150cae of the peripheral control RAM 4150c shown in FIG. As a value of the control side main prize ball number information management counter, a prize ball schedule information storage area (not shown) of the peripheral control RAM 4150c is shown. It is adapted to store updated.

  Here, in the main award ball number information output determination process, a main award ball information output signal that informs the hall computer as main award ball information that the number of game balls to be paid out as award ball has reached 10 The point of maintaining or resetting the value of the peripheral control side main prize ball number information output determination counter for determining whether or not to output to the external terminal board 784 at the time of power recovery will be described. First of all, at the time of power recovery, it is always determined in step S1022 without determining whether the power is turned on from the state where the power is cut off or whether the power is restored after a power failure or instantaneous power failure. If the command analyzed in the received command analysis process is the power-on main prize ball number information output determination counter notification command shown in FIG. The first start port 2101, the second start port 2102, the general winning ports 2104, 2201, and the big winnings shown in FIG. Main prize ball number information output determination that counts the number of game balls scheduled to be paid out as prize balls based on the game balls entered in various winning holes such as the mouth 2103 The issues will be described in the case of directly set the value of the counter as the initial value of the peripheral control side main prize ball number information output determining counter.

  First, as described above, the main control MPU 4100a of the main control board 4100 enters the general winning ports 2104 and 2201 shown in FIG. 8 in the switch input process of step S104 in the main control timer interrupt process shown in FIG. A detection signal from the general winning opening switches 3020 and 3020 shown in FIG. 14 for detecting a game ball that has been balled, and a count switch 2110 shown in FIG. , A detection signal from the first start port switch 3022 shown in FIG. 14 for detecting a game ball that has entered the first start port 2101 shown in FIG. 8, and a second start port 2102 shown in FIG. A detection signal from the second start port switch 2109 shown in FIG. The input information is stored in the input information storage area of the RAM, and the input information is read from the input information storage area of the main control built-in RAM. Based on this input information, in the prize ball control process of step S108 in the same process, The number of game balls scheduled to be paid out as a ball is counted and the value of the main prize ball number information output determination counter is updated and stored. Based on the value of the main prize ball number information output determination counter, the number of main prize balls When the value of the information output determination counter has reached the value 10 (that is, when the number of game balls to be paid out as a prize ball has reached 10), in order to notify that, FIG. The main prize ball number information output command classified into the other shown in FIG. Then, the main control MPU 4100a of the main control board 4100 transmits a main prize ball number information output command to the peripheral control board 4140 in the peripheral control board command transmission process of step S120 in the same process.

  A staff member such as a hall clerk may perform maintenance with the pachinko gaming machine 1 turned on until late at midnight across the day after the hall is closed. Even when the power to the pachinko island facility where the pachinko gaming machine 1 is installed is shut off, the power (power) stored in the capacitor BC0 as the backup power source provided in the power board 851 shown in FIG. However, power (electric power) is supplied to the main control board 4100 for a predetermined time. As a result, the power (power) stored in the capacitor BC0 is completely discharged from the time when the power to the pachinko island facility is turned on until the time when the power to the pachinko island facility is turned on again in order to start operating the hall. If not, the capacitor BC0 causes the main control MPU 4100a to store various information in the main control built-in RAM. Then, when a staff member such as a hall clerk does not operate the operation switch 860a of the payout control board 4110 in order to initialize the main control built-in RAM (game storage unit) for a predetermined time after the power is turned on, In the step S34 in the main control side power-on process shown in FIG. 48, various information is read from the game backup information, and various commands corresponding to the various information are stored in a predetermined storage area of the main control built-in RAM. In the peripheral control board command transmission process of step S120 in the main control timer interruption process shown in FIG. 50, the state is restored, and the value of the main prize ball number information output determination counter of yesterday is inherited as it is. The problem of transmitting the main prize ball number information output command to the peripheral control board 4140 occurs.

  Therefore, in the present embodiment, the effect control program is a power supply in which the command analyzed in the received command analysis process in step S1022 is classified into the power-on shown in FIG. 45 in the main prize ball number information output determination process in step S1025. When it is a counter notification command for determining the main prize ball number information output at the time of turning on, the main control board 4100 is provided on the game board 4 based on the contents instructed by the counter notification command for outputting the main prize ball number information at the time of power-on. Will be paid out as a prize ball based on the game balls entered in various winning openings such as the first starting opening 2101, the second starting opening 2102, the general winning opening 2104, 2201 and the big winning opening 2103 shown in FIG. The value of the main prize ball number information output judgment counter that counts the number of game balls of the peripheral control side main prize ball number information output judgment When setting as the initial value of the counter, based on the time information acquired in the current time information acquisition process of step S1002 and set in the time information storage unit in the RTC information acquisition storage area 4150cad of the peripheral control RAM 4150c shown in FIG. This time information is set to a period before the start of business for starting business of the hall (or for starting maintenance of the pachinko machine 1) (in this embodiment, a period from 0:00 am to 9:00 am). And stored in advance in the peripheral control ROM 4150b.) The power to the pachinko gaming machine 1 is turned on (or the pachinko gaming machine 1 is installed to start the hall business). The number of main prize balls on the peripheral control side when it is determined that the power to the pachinko island facility is on) By forcibly resetting the value of the information management counter and setting it to the default value, the value is returned to the initial value 0 (zero), and is updated in the award ball schedule information storage area (not shown) of the peripheral control RAM 4150c. If the time information is within the period before the start of business for starting the business of the hall (or for starting the maintenance of the pachinko machine 1) (in this embodiment, during the business period of the hall) If the power supply to the pachinko machine 1 is not turned on in order to start the business, and if it is determined that the power is restored due to a power failure or a momentary power interruption during the hall business, the peripheral control side main The number of main prize balls on the peripheral control side is not reset to the initial value by forcibly resetting the value of the prize ball number information management counter and setting it to the default value. A mechanism that maintains the value of the information management counter is adopted.

  As a result, there is a very low probability of a power outage or momentary power failure between the start and end of the hall, but if a power outage or power outage occurs, the hall business has already started. FIG. 8 shows that the main control board 4100 is provided on the game board 4 based on the content of the counter notification command for main prize ball number information output determination at power-on from the main control board 4100 when power is restored. Number of game balls to be paid out as prize balls based on the game balls entered in various prize openings such as the first start opening 2101, the second start opening 2102, the general winning opening 2104, 2201, and the big winning opening 2103 When the value of the main prize ball number information output judgment counter that counts the value is set as the initial value of the peripheral control side main prize ball number information output judgment counter, it is paid out as a prize ball. Peripheral control side for determining whether or not to output to the external terminal board 784 a main prize ball information output signal that informs the hall computer as main prize ball information that the number of scheduled game balls has reached 10 Without forcibly resetting the value of the main prize ball number information output determination counter, maintaining the value, the value of the main prize ball number information output determination counter immediately before the occurrence of a power failure or momentary power failure, When power is restored after a power failure or a momentary power failure, the power is taken over as it is and set as the value of the peripheral control side main prize ball number information output determination counter.

  On the other hand, when the hall operation is ended and the hall operation is started again, the fact that the number of game balls scheduled to be paid out as a prize ball has reached 10 is sent to the hall computer as main prize ball information. To forcibly reset the value of the peripheral control side main prize ball number information output determination counter for determining whether or not to output the main prize ball information output signal to be transmitted to the external terminal board 784 and set it to the default value. Is returned to the initial value of 0 (zero), and when the hall is closed and the pachinko gaming machine 1 is turned off (or the pachinko island facility where the pachinko gaming machine 1 is installed is turned off) The value of the main prize ball number information output determination counter at the time of the power recovery to the pachinko machine 1 when the pachinko machine 1 is turned on to start the hall operation (or the pachinko machine 1 is installed) When the power of the pachinko island facility is restored), even if it is set as the value of the peripheral control side main prize ball number information output judgment counter, it is not taken over as it is, and this peripheral control side main prize ball number information output judgment Because the counter value is forcibly reset and set to the default value, it is reset to the initial value of 0 (zero), so it is updated from the start to the end of the hall operation. Based on the main prize ball number information output command from the main control board 4100 transmitted based on the stored value of the main prize ball number information output judgment counter, the peripheral control side main prize ball number information output judgment counter Whether or not to output the main prize ball number information to the external terminal board 784 based on the value of the peripheral control side main prize ball number information output determination counter by updating the value And it can now be determined. Thus, based on the value of the peripheral control side main prize ball number information output determination counter, accurate main prize ball information can be output from the peripheral control board 4140 to the hall computer via the external terminal board 784. As described above, the main prize ball number information is obtained from the output terminal PT10 provided in light blue on the external terminal board 784, from the first start port 2101, the second start port 2102, the general winning port 2104 shown in FIG. 2201 and main prize ball number information output that informs that every time the number of game balls to be paid out as prize balls reaches 10 on the basis of game balls entered in various prize openings such as the big prize opening 2103 The signal is output to the hall computer. Therefore, the hall computer can accurately grasp the number of game balls to be paid out until the hall business is started and ended.

  Next, following step S1025 described above, the effect control program performs an RCT acquisition information update process (step S1026). In this RTC acquisition information update process, the effect control program stores in the calendar information storage unit acquired in the current time information acquisition process in step S1002 and set in the RTC information acquisition storage area 4150cad of the peripheral control RAM 4150c shown in FIG. The updated calendar information and the time information stored in the time information storage unit are updated. By this RCT acquisition information update process, the hour, minute and second as time information stored in the time information storage unit are updated, and the year and month as calendar information stored in the calendar information storage unit based on the updated time information. The day is updated.

  Subsequent to step S1026, the effect control program performs power consumption monitoring processing (step S1027). This power consumption monitoring process is a process for adjusting the sound volume and the brightness of various LEDs in order to suppress this power consumption in accordance with the power consumption in the pachinko gaming machine 1, and will be described in detail later. To do.

  Subsequent to step S1027, the effect control program performs lamp data creation processing (step S1028). In this lamp data creation process, the effect control program updates the pointer in the scheduler update process in step S1020, and the pointer indicates the light emission data arranged in time series constituting the light emission mode generation schedule data. A plurality of LEDs provided on each of the plurality of game board side peripheral control MPU control target decoration boards, which are controlled objects directly controlled by the peripheral control MPU 4150a, among the decorative boards of the game board 4 based on the light emission data The game board side light emission data SL-DAT for outputting a lighting signal, blinking signal, or gradation lighting signal to (decorative LED), various control data copies of the peripheral control ROM 4150b or the peripheral control RAM 4150c of the peripheral control unit 4150 The peripheral control RAM 415 is created by extracting from the area 4150ce. c in the game board side peripheral control MPU control target LED transmission data storage area 4150caa, and among the decorative boards of the door frame 5, a plurality of frame side peripherals to be controlled by the peripheral control MPU 4150a directly Frame-side emission data STL-DAT for outputting lighting signals, blinking signals, or gradation lighting signals to a plurality of LEDs (decorative LEDs) provided on each of the decorative boards to be controlled by the MPU is sent to the peripheral control unit 4150. It is created by extracting from various control data copy areas 4150ce of the peripheral control ROM 4150b or the peripheral control RAM 4150c, and set in the frame side peripheral control MPU control target LED transmission data storage area 4150cab of the peripheral control RAM 4150c.

  Subsequent to step S1028, the effect control program performs display data creation processing (step S1030). In this display data creation process, the presentation control program updates the pointer in the scheduler update process in step S1020, and the screen data indicated by the pointer among the screen data arranged in time series constituting the schedule data for screen generation. Are extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or the various control data copy areas 4150ce of the peripheral control RAM 4150c and output to the sound source built-in VDP 4160a, and the pointer is updated in the scheduler update process in step S1020 to generate the light emission mode. Of the light emission data arranged in time series constituting the schedule data, the peripheral control unit 4150 is a control target directly controlled by the sound source built-in VDP 4160a based on the light emission data indicated by the pointer. Extracted from various control data copy area 4150ce near control ROM4150b or peripheral control RAM4150c outputs to the tone generator built VDP4160a.

  When the screen data and the light emission data are input from the peripheral control MPU 4150a, the sound source built-in VDP 4160a is connected to the game board side from the liquid crystal and sound control ROM 4160b shown in FIG. 19 based on the input screen data and the light emission data. The game board side character data to be drawn in the display area of the effect display unit 1900 and the above-described predetermined screen (in this embodiment, red (R): 50%, green (G): 50%, blue (B) : Gray screen having 50%) for extracting one dummy data for drawing and creating sprite data and drawing (displaying) on the game board side effect display unit 1900 (liquid crystal panel 5000e) (for one screen) Drawing data for one frame and a predetermined screen (in this embodiment, red (R): 50%, green (G): 50%, blue (B): 5) % And the drawing data of gray screen) draw (display) for one screen (one frame) having, for generating a built VRAM.

  More specifically, the sound source built-in VDP 4160a is composed of the screen data defining the screen configuration drawn on the game board side effect display unit 1900 (liquid crystal panel 5000e) and the sound board built-in VDP 4160a among the decorative boards of the game board 4. The peripheral control MPU 4150a receives light emission data defining light emission modes of a plurality of LEDs (decorative LEDs) provided on each of the plurality of game board side VDP control target decorative boards that are controlled by the computer. Then, in accordance with the above-described predetermined game board side generation rule, the game board side character for drawing in the display area of the game board side effect display unit 1900 from the liquid crystal and sound control ROM 4160b based on the input screen data. Game board side table provided on the built-in VRAM by creating sprite data by extracting data The game board side drawing data is generated in the game board side drawing data area VRGN1a of the game area VRGN1, and the sound source is selected from the liquid crystal and sound control ROM 4160b from the decorative boards of the game board 4 based on the inputted light emission data. Game board side light emission mode setting image for setting the light emission mode of a plurality of LEDs (decorative LEDs) provided on each of the plurality of game board side VDP control target decorative boards that are controlled by the built-in VDP 4160a. Data is extracted, and light guide plate information and electrical decoration information are generated as drawing data in the game board side accompanying information area VRGN1b of the game board side display area VRGN1 provided on the built-in VRAM. The effect control program is a predetermined game board in which the light guide plate information and the electrical decoration information are added to the game board side drawing data of the screen drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e). The drawing data generated in the game board side display area VRGN1 as attached according to the side generation rule is output from the channel CH1 of the sound source information VDP 4160a shown in FIG. 19 in the display data output process of step S1016.

  The sound source built-in VDP 4160a defines the configuration of a predetermined screen (in this embodiment, a gray screen having red (R): 50%, green (G): 50%, blue (B): 50%). And a plurality of LEDs (decorative LEDs) provided on each of a plurality of frame-side VDP control target decorative boards that are controlled by the built-in sound source VDP 4160a among the decorative data of the door frame 5 When the light emission data defining the light emission mode is input from the peripheral control MPU 4150a, the liquid crystal and sound control ROM 4160b determines in advance based on the input screen data according to the above-described predetermined door frame side generation rule. Dummy data for drawing a screen (in this embodiment, a gray screen having red (R): 50%, green (G): 50%, blue (B): 50%) Sprite data is extracted to generate door frame side drawing data in the door frame side drawing data region VRGN2a of the door frame side display region VRGN2 provided on the built-in VRAM, and based on the input light emission data. Among the decorative boards of the door frame 5 from the liquid crystal and sound control ROM 4160b, a plurality of LEDs (decorations) provided on each of the plurality of frame side VDP control target decorative boards that are controlled by the built-in sound source VDP 4160a. For the door frame side of the door frame side display area VRGN2 provided on the built-in VRAM using the illumination information as drawing data. Generated in the region VRGN2b. The effect control program is a door frame of a screen determined in advance as described above (in this embodiment, a gray screen having red (R): 50%, green (G): 50%, blue (B): 50%). FIG. 19 shows the drawing data generated in the door frame side display area VRGN2 in the display data output process in step S1016, with the illumination information attached to the side drawing data according to the above-described predetermined door frame side generation rule. It outputs from channel CH2 of the indicated sound source information VDP4160a.

  Subsequent to step S1030, the effect control program performs sound data creation processing (step S1032). In this sound data creation process, the effect control program updates the pointer in the scheduler update process in step S1020, and the pointer indicates the sound command data arranged in time series constituting the sound generation schedule data. The sound command data is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c and output to the sound source built-in VDP 4160a. When sound command data is input from the peripheral control MPU 4150a, the sound source built-in VDP 4160a extracts sound data such as music and sound effects stored in the liquid crystal and sound control ROM 4160b and controls the sound source by controlling the sound source. In addition to incorporating sound data such as music and sound effects according to the track number defined in the data, an output channel to be used is set according to the output channel number.

  In the sound data creation process, every time this sound data creation process is performed (that is, every time the peripheral control unit steady process is performed), the peripheral control A / D converter 4150ak shown in FIG. The voltage divided by the resistance value at the rotation position of the knob portion of 4140a is converted into a value of 1024 steps from 0 to 1023. In this embodiment, the value of 1024 steps is divided into seven and managed as substrate volumes 0 to 6, and the sound volume is set to the substrate volume 0, the maximum volume is set to the substrate volume 6, and the substrate volume 0 to the substrate volume are set. Each volume is set to increase toward the volume 6. By controlling the liquid crystal and the built-in sound source VDP 4160a of the sound control unit 4160 so that the volume is set to the substrate volume 0 to 6, audio data is obtained as audio data obtained by serializing the sound data in the sound data output process of step S1018 described above. By outputting to the transmission IC 4160 c, music and sound effects flow from the speakers housed in the speaker box 820 provided in the main body frame 3 and the speakers 130 provided in the door frame 5.

  In addition, the notification sound and the notification sound flow without depending on the volume adjustment based on the turning operation of the knob part, and the sound volume of the liquid crystal and sound control unit 4160 can be set by the program from the mute level to the maximum volume level. The built-in VDP 4160a can be controlled and adjusted. The volume adjusted by this program can be smoothly changed from the mute to the maximum volume, unlike the substrate volume divided into the above seven stages. For example, even when a store clerk or the like of the hall rotates the knob portion of the volume adjustment volume 4140a to set the volume to a low level, the hall and the door frame 5 are accommodated in the speaker box 820 provided in the main body frame 3. Although the production sound such as music and sound effects flowing from the provided speaker 130 is reduced, when the malfunction occurs in the pachinko gaming machine 1 or when the player is cheating, the volume is high (in this embodiment, The notification sound set to (maximum volume) can be played. Therefore, even if the volume of the production sound is reduced, it is possible to prevent the hall clerk or the like from becoming difficult to notice the occurrence of a malfunction or the player's cheating due to the notification sound. Also, based on the current board volume set by volume adjustment based on the turning operation of the knob part, the volume of the advertisement sound is reduced so as not to interfere with the music and sound effects. In addition to music and sound effects, there is a possibility that the screen unfolded on the game board side effect display unit 1900 will be rendered more powerful, or that it will shift to a gaming state advantageous to the player. You can also announce that it is expensive.

  Subsequent to step S1032, the effect control program performs backup processing (step S1034). In this backup process, the effect control program stores the contents stored in the peripheral control RAM 4150c externally attached to the peripheral control MPU 4150a shown in FIG. 18 into the backup first area 4150cb and the backup second area 4150cc. The contents are copied and backed up, and the contents stored in the peripheral control SRAM 4150d attached to the peripheral control MPU 4150a are copied and backed up in the backup first area 4150db and the backup second area 4150dc, respectively.

  Specifically, in the backup process, the peripheral control RAM 4150c is backed up every frame (1 frame) in the backup target work area 4150ca shown in FIG. 18, that is, every time the peripheral control unit steady process is executed. The production information (1fr), which is the contents stored in the received command storage area 4150cac, the RTC information acquisition storage area 4150cad, and the schedule data storage area 4150cae, included in the bank 0 (1fr) is converted to the production backup information (1fr). 1fr), the peripheral control DMA controller 4150ac makes a high-speed copy to Bank1 (1fr) and Bank2 (1fr) in the backup first area 4150cb, and Bank3 in the backup second area 4150cc. 1FR) and Bank4 (1FR) to peripheral control DMA controller 4150ac copies at high speed.

  The high-speed copy of the contents stored in Bank0 (1fr) by the peripheral control DMA controller 4150ac will be briefly described. The peripheral control MPU core 4150aa of the peripheral control MPU 4150a shown in FIG. The content stored in Bank0 (1fr) is designated to be copied to Bank1 (1fr) in the backup first area 4150cb, and the content stored in the first address of Bank0 (1fr) is changed to the end address of Bank0 (1fr) The stored contents are all copied in sequence starting from the first address of Bank 1 (1fr) in the backup first area 4150cb in succession by a predetermined number of bytes (for example, 1 byte), and the peripheral control MPU core 4150aa performs peripheral control D The content stored in Bank0 (1fr) is designated as the request factor of the A controller 4150ac, the copy to Bank2 (1fr) of the backup first area 4150cb is designated, and the content stored in the first address of Bank0 (1fr) is used as Bank0 The contents stored at the end address of (1fr) are all copied in order from the start address of Bank2 (1fr) of the backup first area 4150cb in succession by predetermined bytes (for example, 1 byte).

  Subsequently, the peripheral control MPU core 4150aa designates the content stored in Bank0 (1fr) as the request factor of the peripheral control DMA controller 4150ac, specifies the copy of the backup second area 4150cc to Bank3 (1fr), and Bank0 (1fr) ) To the content stored at the end address of Bank0 (1fr) to the content stored at the end address of Bank0 (1fr), the first address of Bank3 (1fr) in the backup second area 4150cc continuously by a predetermined byte (for example, 1 byte) The peripheral control MPU core 4150aa specifies the contents stored in Bank0 (1fr) as the request factor of the peripheral control DMA controller 4150ac, and specifies that the backup second area 4150cc is copied to Bank4 (1fr). Shi From the content stored at the beginning address of Bank0 (1fr) to the content stored at the end address of Bank0 (1fr), bank 4 (1fr) in the backup second area 4150cc is continuously provided by a predetermined number of bytes (for example, 1 byte). Copy everything starting from the first address.

  In the backup process, the peripheral control SRAM 4150d is a backup target every frame (1 frame) in the backup target work area 4150da shown in FIG. 18, that is, every time the peripheral control unit steady process is executed. The peripheral control DMA controller 4150ac operates at high speed in the bank 1 (SRAM) and the bank 2 (SRAM) of the backup first area 4150db by using the production information (SRAM) stored in the Bank 0 (SRAM) as production backup information (SRAM). Then, the peripheral control DMA controller 4150ac copies to Bank 3 (SRAM) and Bank 4 (SRAM) in the backup second area 4150dc at high speed.

  The high-speed copy of the contents stored in Bank 0 (SRAM) by the peripheral control DMA controller 4150ac will be briefly described. The peripheral control MPU core 4150aa of the peripheral control MPU 4150a shown in FIG. The content stored in Bank0 (SRAM) is designated to be copied to Bank1 (SRAM) in backup first area 4150db, and the content stored at the beginning address of Bank0 (SRAM) is changed to the end address of Bank0 (SRAM). The stored contents are all copied in sequence starting from the first address of Bank 1 (SRAM) in the backup first area 4150db in order of predetermined bytes (for example, 1 byte), and the peripheral control MPU core 4150aa The content stored in Bank0 (SRAM) as the request factor of the peripheral control DMA controller 4150ac, the copy to the Bank2 (SRAM) of the backup first area 4150db is designated, and the content stored in the first address of Bank0 (SRAM) To the contents stored at the end address of Bank 0 (SRAM) are copied in order from the start address of Bank 2 (SRAM) in the backup first area 4150 db in succession by a predetermined number of bytes (for example, 1 byte).

  Subsequently, the peripheral control MPU core 4150aa designates the contents stored in the Bank 0 (SRAM) as the request factor of the peripheral control DMA controller 4150ac, specifies the copy of the backup second area 4150dc to the Bank 3 (SRAM), and the Bank 0 (SRAM). ) To the content stored at the end address of Bank0 (SRAM) to the content stored at the end address of Bank0 (SRAM) by a predetermined number of bytes (for example, 1 byte) continuously, the top address of Bank3 (SRAM) in backup second area 4150dc The peripheral control MPU core 4150aa copies the contents stored in the bank 0 (SRAM) as the request factor of the peripheral control DMA controller 4150ac to the bank 4 (SRAM) of the backup second area 4150dc. P2 is specified, and the content stored in the bank 0 (SRAM) start address to the content stored in the bank 0 (SRAM) end address is continuously backed up by a predetermined byte (for example, 1 byte) in a second backup area 4150dc. Are all copied in order from the top address of Bank 4 (SRAM).

  Subsequent to step S1034, the effect control program performs a WDT clear process (step S1036). In this WDT clear process, a clear signal is output to the peripheral control built-in WDT 4150af and the peripheral control external WDT 4150e so that the peripheral control MPU 4150a is not reset.

  Subsequent to step S1036, the effect control program sets the value 0 in the steady processing flag SP-FLG as the completion of the peripheral control unit steady processing (step S1038), returns to step S1006 again, and the V blank signal detection flag VB. -FLG is initialized by setting value 0, and the determination in step S1008 is repeated until value 1 is set in V blank signal detection flag VB-FLG in the peripheral control unit V blank signal interrupt processing described later. That is, in step S1008, the process waits until a value 1 is set in the V blank signal detection flag VB-FLG. If it is determined in step S1008 that the V blank signal detection flag VB-FLG is 1, the process proceeds from step S1009 to step S1009. The process of S1038 is performed, and the process returns to step S1006 again. As described above, when it is determined in step S1008 that the V blank signal detection flag VB-FLG has a value of 1, processing in steps S1009 to S1038 is performed. The processing from step S1009 to step S1038 is referred to as “peripheral control unit steady processing”.

  The peripheral control unit steady process starts from the fact that the effect control program first sets the value 1 in the steady processing flag SP-FLG, assuming that the peripheral control unit steady process is being executed in step S1009, and 1 ms in step S1010. When the interrupt timer activation process is performed, each process of steps S1014,..., And step S1036 is performed, and finally, in step S1038, the execution of the peripheral control unit steady process is completed and the steady process flag SP-FLG is set to 0. Will be completed. The peripheral control unit steady process is executed when the V blank signal detection flag VB-FLG is 1 in step S1008. As described above, the V blank signal detection flag VB-FLG is executed when the V blank signal that indicates that the screen data from the peripheral control MPU 4150a can be received is input from the sound source built-in VDP 4160a. The value 1 is set in the peripheral control unit V blank signal interrupt processing described later. In the present embodiment, the game board side effect display unit 1900 and the above-described predetermined screen (in the present embodiment, red (R): 50%, green (G): 50%, blue (B): 50%). As described above, the frame frequency (the number of times the screen is updated per second), which is the frequency at which drawing data for one screen (one frame) with the gray screen) is updated, is set to approximately 30 fps per second as described above. Therefore, the interval at which the V blank signal is input is approximately 33.3 ms (= 1000 ms ÷ 30 fps). That is, the peripheral control unit steady process is repeatedly executed about every 33.3 ms.

[18-1-2. Peripheral control unit V blank signal interrupt processing]
Next, as shown in FIG. 17, a V blank signal indicating that the screen data from the peripheral control MPU 4150a of the peripheral control unit 4150 can be received is input from the VDP 4160a with built-in sound source of the liquid crystal and sound control unit 4160. The peripheral control unit V blank signal interrupt processing executed with this as an opportunity will be described. When the peripheral control unit V blank signal interrupt processing is started, the peripheral control MPU 4150a of the peripheral control unit 4150 determines whether the steady processing flag SP-FLG is 0 as shown in FIG. S1045). As described above, the steady processing flag SP-FLG has a value of 1 when the peripheral control unit steady processing in steps S1009 to S1038 in the peripheral control unit power-on processing of FIG. It is set to a value of 0 when execution of the process is completed.

  If the steady process flag SP-FLG is not 0 (value 1) in step S1045, that is, if the peripheral control unit steady process is being executed, this routine is terminated. On the other hand, when the steady processing flag SP-FLG is 0 in step S1045, that is, when the execution of the peripheral control unit steady processing is completed, the value 1 is set to the V blank signal detection flag VB-FLG (step S1050). This routine ends. As described above, the V blank signal detection flag VB-FLG is a flag for determining whether or not to execute the peripheral control unit steady process. When the part steady process is not executed, the value is set to 0.

  In this embodiment, it is determined in step S1045 whether or not the steady processing flag SP-FLG is 0, that is, whether or not the peripheral control unit steady processing has been completed, and the peripheral control unit steady processing has been completed. Sometimes the value 1 is set to the V blank signal detection flag VB-FLG in step S1050. This is because the V blank signal is input and the V blank signal is input when the peripheral control unit steady processing is being executed. When the value 1 is set to the signal detection flag VB-FLG, it is assumed that the peripheral control unit steady process is executed in step S1008 in the peripheral control unit power-on process of FIG. Forcibly canceling the process in the middle and starting execution of the peripheral control unit steady process from the beginning. The peripheral control unit V blank signal, which is this routine, indicates that the peripheral control unit steady processing is being executed by setting the value 1 to the steady processing flag SP-FLG in step S1009 in the processing (peripheral control unit steady processing). In step S1038 in the peripheral control unit power-on process (peripheral control unit steady process) in FIG. 68, the peripheral control unit steady process is completed by setting the value 0 to the steady process flag SP-FLG. This is communicated to the peripheral control unit V blank signal interrupt process, which is this routine, so that the steady processing flag SP-FLG is 0 in the determination of step S1045 in the peripheral control unit V blank signal interrupt process, which is this routine. It is determined whether or not there is, that is, whether or not the peripheral control unit steady process has been executed. In other words, this is a measure for the case where the peripheral control unit steady-state processing cannot be completed before the next V blank signal is input and the next V blank signal is input, so-called processing failure.

  As a result, in the current peripheral control unit steady process, if the process cannot be completed in about 33.3 ms and the process is dropped, the next determination is made in step S1008 in the peripheral control unit power-on process of FIG. It is in a state of waiting until the V blank signal is input. That is, the time required to execute the current peripheral control unit steady process that has been dropped is about 66.6 ms. Normally, a peripheral control unit 1 ms timer interrupt process, which will be described later, is repeatedly executed every time a 1 ms interrupt timer is generated by starting the 1 ms interrupt timer in step S1010 in the peripheral control unit power-on process (peripheral control unit steady process) in FIG. Is executed only 32 times for one peripheral control unit steady process. However, if there is a current peripheral control unit steady process that has been dropped as described above, the peripheral control unit 1 ms timer interrupt process is not performed 64 times. No, it is executed only 32 times. In other words, even when the peripheral control unit steady process is lost, the consistency between the presentation progress state by the peripheral control unit steady process and the presentation progress state by the peripheral control unit 1 ms timer interrupt process, which is timer interrupt control, is consistent. It is designed not to collapse. Therefore, even if the peripheral control unit steady process is lost, it is possible to reliably match the progress state of the performance.

[18-1-3. Peripheral control unit 1ms timer interrupt processing]
Next, the peripheral control unit 1 ms timer interrupt process that is repeatedly executed every time the 1 ms interrupt timer is generated by starting the 1 ms interrupt timer in step S1010 in the peripheral control unit steady process of the peripheral control unit power-on process of FIG. 68 will be described. . When this peripheral control unit 1 ms timer interrupt process is started, the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 17 determines whether the 1 ms timer interrupt execution count STN is smaller than 33 times as shown in FIG. Is determined (step S1100). As described above, this 1 ms timer interrupt execution count STN is determined by this routine when the 1 ms interrupt timer is activated in the 1 ms interrupt timer activation process of step S1010 in the peripheral control part steady process of the peripheral control part power-on process of FIG. It is a counter that counts the number of times a peripheral control unit 1 ms timer interrupt process is executed. In the present embodiment, the game board side effect display unit 1900 and the above-described predetermined screen (in the present embodiment, red (R): 50%, green (G): 50%, blue (B): 50%). As described above, the frame frequency (the number of times the screen is updated per second), which is the frequency at which drawing data for one screen (one frame) with the gray screen) is updated, is set to approximately 30 fps per second as described above. Therefore, the interval at which the V blank signal is input is approximately 33.3 ms (= 1000 ms ÷ 30 fps). That is, since the peripheral control unit steady process is repeatedly executed about every 33.3 ms, after starting the 1 ms interrupt timer in step S1010 in the peripheral control unit steady process, the next peripheral control unit steady process is performed. The peripheral control unit 1 ms timer interrupt process is executed only 32 times before. Specifically, when the 1 ms interrupt timer is started in step S1010 in the peripheral control unit steady process, the first 1 ms timer interrupt is generated first, then the second,... Will occur.

  When the 1 ms timer interrupt execution count STN is not smaller than 33 times in step S1100, that is, when the 33 ms 1 ms timer interrupt is generated and the peripheral control unit 1 ms timer interrupt processing is started, this routine is ended as it is. In the present embodiment, when the 33rd 1 ms timer interrupt occurs accidentally before the next generation of the V blank signal, in the present embodiment, the peripheral control unit 1 ms timer interrupt process is the peripheral control unit V as the priority of interrupt processing. Although set higher than the blank interrupt process, the start of the peripheral control unit 1 ms timer interrupt process by the 33rd 1 ms timer interrupt is forcibly canceled. In other words, in the present embodiment, the V blank signal is a signal that dominates the entire system of the peripheral control board 4140. Therefore, when the occurrence of the 1st timer interrupt for the 33rd time happens to precede the generation of the next V blank signal. In order to execute the peripheral control unit V blank interrupt process, the start of the peripheral control unit 1 ms timer interrupt process by the 33rd 1 ms timer interrupt is forcibly canceled. Then, after the 1 ms interrupt timer is started again in step S1010 in the peripheral control unit steady process due to the generation of the V blank signal, the peripheral control unit 1 ms timer interrupt process is newly started by the first 1 ms timer interrupt generation. ing.

  On the other hand, when the 1 ms timer interrupt execution count STN is smaller than 33 in step S1100, the value 1 is added to the 1 ms timer interrupt execution count STN (increment, step S1102). When the value 1 is added to this 1 ms timer interrupt execution count STN, the 1 ms interrupt timer is activated in the 1 ms interrupt timer activation process of step S1010 in the peripheral control unit steady process of the peripheral control unit power-on process of FIG. The number of times that the peripheral control unit 1 ms timer interrupt process, which is this routine, is executed is increased by one.

  Subsequent to step S1102, motor and solenoid drive processing is performed (step S1104). In this motor and solenoid drive processing, the electric drive source schedule data set in the schedule data storage area 4150cae of the peripheral control RAM 4150c externally attached to the peripheral control MPU 4150a shown in FIG. 18 is arranged in time series. According to the drive data indicated by the pointer among the drive data of the electrical drive sources such as the motor and the solenoid, the electrical drive sources such as the motor and the solenoid of the frame decoration drive amplifier board 194 and the motor drive board 4180 shown in FIG. And the pointer is updated to the next drive data defined in time series, and the pointer is updated each time the motor and solenoid drive processing is executed.

  Specifically, in the motor and solenoid drive processing, for example, DMA serial continuous transmission processing to the frame decoration drive amplifier board 194 is performed. Here, the frame I / O port motor serial I / O port continuous transmission is performed using the peripheral control DMA controller 4150ac of the peripheral control MPU 4150a shown in FIG. When this frame decoration drive amplifier board motor serial I / O port continuous transmission starts, first, the electrical drive source schedule data set in the schedule data storage area 4150cae of the peripheral control MPU 4150a and the externally attached peripheral control RAM 4150c is stored. A drive signal to the dial drive motor 414 of the operation unit 400 shown in FIG. 7 based on drive data indicated by a pointer among drive data of electric drive sources such as motors and solenoids arranged in time series. 18 is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c, and the peripheral control RAM 4150c shown in FIG. Frame decoration It is set to send a dynamic amplifier board-side motor data storage area 4150Caf. The peripheral control CPU core 4150aa of the peripheral control MPU 4150a designates transmission of the frame decoration drive amplifier board motor serial I / O port as a request factor of the peripheral control DMA controller 4150ac, and stores frame decoration drive amplifier board side motor transmission data. Frame decoration drive amplifier board motor via the external bus 4150h, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai with the first byte of the door side motor drive data STM-DAT stored in the head address of the area 4150caf Transfer and write to the transmission buffer register of the serial I / O port As a result, the frame decoration drive amplifier board motor serial I / O port transfers the written transmission buffer register data to the transmission shift register, and synchronizes with the door side motor drive clock signal STM-CLK. The 1-byte data starts to be transmitted bit by bit.

  The peripheral control DMA controller 4150ac is triggered every time a transmission interrupt request for the frame decoration drive amplifier board motor serial I / O port is generated (in this embodiment, the frame decoration drive amplifier board motor serial I / O 1 byte data written in the transmission buffer register of the port is transferred to the transmission shift register, and the transmission buffer register is empty because the 1 byte data disappears.), Peripheral control CPU core 4150aa When the bus does not use the bus, the remaining door side motor drive data STM-DAT stored in the frame decoration drive amplifier board side motor transmission data storage area 4150caf is stored byte by byte, external bus 4150h, peripheral control bus controller 4150ad, and via peripheral bus 4150ai, By transferring and writing to the transmission buffer register of the decorative drive amplifier board motor serial I / O port, the frame decoration drive amplifier board motor serial I / O port transmits the data of the written transmission buffer register to the transmission shift register. 1 byte data of the transmission shift register is started bit by bit in synchronization with the door side motor drive clock signal STM-CLK, and the frame decoration drive amplifier board motor serial I / O port continuously transmits. Is going.

  In the motor and solenoid drive processing, for example, DMA serial continuous transmission processing to the motor drive board 4180 is performed. Also here, serial transmission of the motor drive board serial I / O port is performed using the peripheral control DMA controller 4150ac of the peripheral control MPU 4150a shown in FIG. When the serial I / O port continuous transmission for the motor drive board is started, first, when configuring the electrical drive source schedule data set in the schedule data storage area 4150cae of the peripheral control MPU 4150a and the peripheral control RAM 4150c attached externally A motor for moving various movable bodies provided in the game board 4 shown in FIG. 8 based on drive data indicated by a pointer among drive data of electric drive sources such as motors and solenoids arranged in series. The game board side motor drive data SM-DAT for outputting the drive signal to the solenoid and the solenoid is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or the various control data copy areas 4150ce of the peripheral control RAM 4150c and created. Peripheral control RAM 415 shown in FIG. Set to the motor drive board side transmission data storage area 4150cag of c. The peripheral control CPU core 4150aa of the peripheral control MPU 4150a designates transmission of the motor drive board serial I / O port as a request factor of the peripheral control DMA controller 4150ac, and stores it in the head address of the motor drive board side transmission data storage area 4150cag. The first 1 byte of the game board side motor drive data SM-DAT thus obtained is transmitted to the serial I / O port for the motor drive board via the external bus 4150h, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai. Transfer and write to register. As a result, the serial I / O port for the motor drive board transfers the written data of the transmission buffer register to the transmission shift register, and 1 of the transmission shift register is synchronized with the game board side motor drive clock signal SM-CLK. Start transmitting byte data bit by bit.

  The peripheral control DMA controller 4150ac is triggered by the transmission interrupt request for the motor drive board serial I / O port (in this embodiment, in the transmission buffer register of the motor drive board serial I / O port). The written 1-byte data is transferred to the transmission shift register, and the transmission buffer register is empty because the 1-byte data disappears.), The peripheral control CPU core 4150aa is using the bus. If not, the remaining game board side motor drive data SM-DAT stored in the motor drive board side transmission data storage area 4150cag is transferred byte by byte via the external bus 4150h, peripheral control bus controller 4150ad, and peripheral bus 4150ai. , Serial I / O port for motor drive board By transferring and writing to the transmission buffer register, the motor drive board serial I / O port transfers the written data of the transmission buffer register to the transmission shift register, and the game board side motor drive clock signal SM-CLK and Synchronously, transmission of 1-byte data of the transmission shift register is started bit by bit, and continuous transmission is performed by the serial I / O port for the motor drive board.

  Following step S1104, movable body information acquisition processing is performed (step S1106). In this movable body information acquisition process, it is determined whether or not detection signals from various detection switches provided on the game board 4 are input, thereby history information (for example, original position history information) of detection signals from the various detection switches. , Movable position history information, etc.) is created and set in the movable body information acquisition storage area 4150cah of the peripheral control MPU 4150a and the externally attached peripheral control RAM 4150c shown in FIG. From the history information of the detection signals from the various detection switches set in the movable body information acquisition storage area 4150cah, the original positions and the movable positions of the various movable bodies provided on the game board 4 can be acquired.

  Subsequent to step S1106, an operation unit information acquisition process is performed (step S1108). In this operation unit information acquisition process, it is determined whether or not detection signals from various detection switches provided in the operation unit 400 are input, whereby history information of detection signals from various detection switches (for example, a dial operation unit) Rotation (rotation direction) history information 401, operation history information of the pressing operation unit 405, etc.) is created, and the operation unit information acquisition storage area of the peripheral control MPU 4150a and the peripheral control RAM 4150c externally shown in FIG. Set to 4150cai. The rotation direction of the dial operation unit 401 and the presence / absence of the operation of the pressing operation unit 405 can be acquired from the history information of detection signals from various detection switches set in the operation unit information acquisition storage area 4150cai.

  Following step S1108, drawing state information acquisition processing is performed (step S1110). In this drawing state information acquisition process, history information of the LOCKN signal output from the LOCKN terminal of the receiver IC 194f included in the frame decoration drive amplifier board 194 shown in FIG. 19 is created, and the peripheral control MPU 4150a shown in FIG. The drawing state information acquisition storage area 4150cak of the attached peripheral control RAM 4150c is set. As described above, when the receiver IC 194f provided in the frame decoration drive amplifier board 194 determines that the drawing data received from the transmitter IC 4160d provided in the peripheral control board 4140 is abnormal data, the LOCKN signal is transmitted to the effect. Specifically, it is a signal to be output. Specifically, the connection between the transmitter IC 4160d provided in the peripheral control board 4140 and the receiver IC 194f provided in the frame decoration drive amplifier board 194, that is, the connection between the transmitter and the receiver is confirmed (recovered). ) Is a signal output to request transmission of a predetermined data pattern (SYNC pattern). From the history information of the LOCKN signal set in the drawing state information acquisition storage area 4150cak, it is possible to acquire the frequency of defects and the state of occurrence of defects between the connection between the peripheral control board 4140 and the frame decoration drive amplifier board 194.

  Subsequent to step S1110, a main winning ball number information output process is performed (step S1112). In this main prize ball number information output process, when the schedule data for the main prize ball information output signal set in the schedule data storage area 4150cae of the peripheral control MPU 4150a and the peripheral control RAM 4150c externally shown in FIG. Output waveform data for generating a main prize ball information output signal that informs the hall computer as main prize ball information that the number of game balls to be paid out as a prize ball has reached 10 balls arranged in a series The main prize ball information output signal is output to the external terminal board 784 shown in FIG. 33 according to the output waveform data indicated by the pointer, and the pointer is updated to the next output waveform data defined in time series. Each time the main prize ball number information output process is executed, the pointer is updated.

  Subsequent to step S1112, power consumption status history information creation processing is performed (step S1113). In this power consumption status history information creation processing, the value (power consumption suppression stage) transmitted by the power consumption suppression signal from the power supply board 851 is sampled, and the power consumption of the peripheral control unit 4150 shown in FIG. Sequentially stored in the status history RAM 4150f. As described above, the power consumption suppression signal is output from the power consumption monitoring circuit 855da. As shown in FIG. 22A, the power consumption monitoring circuit 855da includes a power measurement circuit 855daa and a power consumption suppression stage determination circuit 855dab. + 37V supplied from the smoothing circuit 855c is supplied to the + 5V power generation circuit 855db, the + 12V power generation circuit 855dc, and the + 24V power supply generation circuit 855dd via the power measurement circuit 855daa. The power measurement circuit 855daa measures the power consumption of + 37V supplied from the smoothing circuit 855c in real time and outputs it to the power consumption suppression stage determination circuit 855dab. The power consumption suppression stage determination circuit 855dab determines a power consumption suppression stage indicating how much power consumption should be suppressed based on the power consumption measured by the power measurement circuit 855daa. By setting the value of the power consumption suppression signal configured as a signal wiring and outputting it to the frame peripheral relay terminal plate 868, the power consumption suppression signal is input to the peripheral control unit 4150 via the frame peripheral relay terminal plate 868. It has come to be. As described above, the power consumption suppression signal is configured as three signal wirings (that is, configured as three parallel signals), and transmits eight values from 0 to 7. Can be done.

  As described above, the power consumption suppression stage determination circuit 855dab determines that it is stage 0 as the power consumption suppression stage when the power consumption of + 37V measured by the power measurement circuit 855daa is 0% or more and less than 10%. When the value of 0 is set as the value of the suppression signal and the power consumption of + 37V measured by the power measurement circuit 855daa is 10% or more and less than 20%, it is determined as stage 1 as the power consumption suppression stage and the power consumption suppression signal The value 1 is set as the value, and when the power consumption of +37 V measured by the power measuring circuit 855daa is 20% or more and less than 30%, it is determined as the stage 2 as the power consumption suppression stage and the value as the value of the power consumption suppression signal 2 and when the power consumption of + 37V measured by the power measurement circuit 855daa is 30% or more and less than 40%, When the power consumption suppression signal is determined to be stage 3 as the suppression stage and the value 3 is set as the value of the power consumption suppression signal and the power consumption of +37 V measured by the power measurement circuit 855daa is 40% or more and less than 50%, the power consumption suppression stage When the power consumption suppression signal is determined to be step 4 and the value 4 is set as the value of the power consumption suppression signal and the power consumption of + 37V measured by the power measurement circuit 855daa is 50% or more and less than 60%, the power consumption suppression step is performed in step 5 If a value 5 is set as the value of the power consumption suppression signal after determination and the power consumption of +37 V measured by the power measurement circuit 855daa is 60% or more and less than 70%, it is determined that the power consumption suppression stage is stage 6. When the value 6 is set as the value of the power consumption suppression signal, the power consumption of +37 V measured by the power measurement circuit 855daa is 70% or more. It is adapted to set the value 7 as the value of the power consumption suppression signal to determine a phase 7 as a power consumption inhibiting step for.

  Thus, in the power consumption status history information creation process, every time this routine is executed, that is, every 1 ms, the value (value 0 to value 7) transmitted by the power consumption suppression signal from the power supply board 851 is sampled. By sequentially storing in the power consumption status history RAM 4150f of the peripheral control unit 4150 as the power consumption suppression steps (step 0 to step 7), the power consumption suppression steps are arranged as power consumption status history information in time series.

  Subsequent to step S1113, backup processing is performed (step S1114), and this routine is terminated. In this backup processing, the contents stored in the peripheral control MPU 4150a and the externally attached peripheral control RAM 4150c shown in FIG. 18 are copied to the backup first area 4150cb and the backup second area 4150cc for backup. At the same time, the contents stored in the peripheral control MPU 4150a and the externally attached peripheral control SRAM 4150d are copied to the backup first area 4150db and the backup second area 4150dc for backup.

  Specifically, in the backup process, the peripheral control RAM 4150c executes the 1 ms timer interrupt process of the peripheral control unit, which is this routine, whenever the 1 ms interrupt timer is generated in the backup target work area 4150ca shown in FIG. Each time, the frame decoration drive amplifier board-side motor transmission data storage area 4150caf, the motor drive board-side transmission data storage area 4150cag, and the movable body information acquisition storage area 4150cah included in Bank0 (1 ms) to be backed up. The production information (1 ms), which is the content stored in the operation unit information acquisition storage area 4150cai, is used as production backup information (1 ms), and Bank 1 (1 ms) and Bank 2 (1) of the backup first area 4150 cb Peripheral control DMA controller 4150ac in s) is copied at high speed, and backup Bank3 second area 4150cc (1ms) and peripheral control DMA controller 4150ac to Bank4 (1 ms) is copied at high speed.

  The high-speed copy of the contents stored in Bank 0 (1 ms) by the peripheral control DMA controller 4150ac will be briefly described. The peripheral control MPU core 4150aa of the peripheral control MPU 4150a shown in FIG. The content stored in Bank0 (1 ms) is designated to be copied to Bank1 (1 ms) in backup first area 4150cb, and the content stored at the beginning address of Bank0 (1 ms) is changed to the end address of Bank0 (1 ms). The stored contents are all copied in sequence starting from the first address of Bank 1 (1 ms) in the backup first area 4150cb in succession to a predetermined byte (for example, 1 byte), and the peripheral control MPU core 4150aa performs peripheral control D. The content stored in Bank 0 (1 ms) as the request factor of the A controller 4150ac is designated to be copied to Bank 2 (1 ms) in the backup first area 4150cb, and the content stored in the first address of Bank 0 (1 ms) is used as Bank 0 The contents stored at the end address of (1 ms) are all copied in order from the start address of Bank 2 (1 ms) of the backup first area 4150cb in succession by predetermined bytes (for example, 1 byte).

  Subsequently, the peripheral control MPU core 4150aa designates the contents stored in Bank0 (1 ms) as the request factor of the peripheral control DMA controller 4150ac, specifies the copy of the second backup area 4150cc to Bank3 (1 ms), and Bank0 (1 ms) ) To the content stored at the end address of Bank 0 (1 ms) from the content stored at the head address of) in the backup second area 4150 cc of bank 3 (1 ms) The peripheral control MPU core 4150aa specifies the contents stored in Bank0 (1ms) as the request factor of the peripheral control DMA controller 4150ac, and specifies the copy to Bank4 (1ms) in the backup second area 4150cc. Shi From the content stored at the beginning address of Bank0 (1 ms) to the content stored at the end address of Bank0 (1 ms), bank 4 (1 ms) in the backup second area 4150 cc continuously by a predetermined byte (for example, 1 byte) Copy everything starting from the first address.

  As described above, in the peripheral control unit 1 ms timer interruption process, various processes related to the effects in steps S1104 to S1108 are executed as the progress of the effects within a period of 1 ms. On the other hand, in the peripheral control unit steady-state process in the peripheral control unit power-on process of FIG. 68, various processes relating to the effects in steps S1012 to S1032 described above are executed as the progress of the effects within a period of about 33.3 ms. doing. In the peripheral control unit 1 ms timer interrupt process, when the 1 ms timer interrupt execution count STN is not smaller than the value 33 in step S1100, that is, when the first 1 ms timer interrupt is generated and the peripheral control unit 1 ms timer interrupt process is started. Since this routine is ended as it is, even if the occurrence of the 33rd 1 ms timer interrupt happens to occur before the next V blank signal, the peripheral control unit by this 33rd 1 ms timer interrupt. The start of the 1 ms timer interrupt process is forcibly canceled, and after the 1 ms interrupt timer is started again in step S1010 in the peripheral control unit steady process due to the generation of the V blank signal, the peripheral control is newly performed by the first 1 ms timer interrupt. 1ms timer division It is adapted to start the actual processing. That is, the consistency between the progress state of the effect by the peripheral control unit steady process and the progress state of the effect by the peripheral control unit 1 ms timer interrupt process which is the timer interrupt control is not lost. Therefore, it is possible to reliably match the progress of the production.

  Further, as described above, the interval at which the V blank signal is output depends on the liquid crystal size of the game board side effect display unit 1900 and a predetermined screen (in this embodiment, red (R): 50%, green (G). : 50%, blue (B): gray screen having 50%) and the V blank signal in the manufacturing lot of the peripheral control board 4140 on which the peripheral control MPU 4150a and the sound source built-in VDP 4160a are mounted. In some cases, the interval at which is output varies slightly. In this embodiment, since the V blank signal is a signal that dominates the entire system of the peripheral control board 4140, if the occurrence of the first 1 ms timer interrupt happens to precede the next generation of the V blank signal, the peripheral control is performed. In order to execute the part V blank interrupt process, the start of the peripheral control part 1 ms timer interrupt process by the 33rd 1 ms timer interrupt is forcibly canceled. In other words, in the present embodiment, even if the interval at which the V blank signal is output changes slightly, by forcibly canceling the start of the peripheral control unit 1 ms timer interrupt process by the 33rd 1 ms timer interrupt, A time shift due to a slight change in the interval at which the V blank signal is output can be absorbed.

[18-1-4. Peripheral control unit command reception interrupt processing]
Next, the peripheral control unit command reception interrupt process for receiving various commands from the main control board 4100 will be described. The peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 17 starts main transmission of main peripheral serial data in the peripheral control MPU 4150a when various commands from the main control board 4100 are started to be transmitted as serial data. One byte (8 bits) of information is taken into the reception buffer at the board serial I / O port, and when this fetching is completed, an interrupt is generated as a trigger, and peripheral control unit command reception interrupt processing is performed. The main circumference serial data is composed of 3 bytes per packet, the status is assigned as the first byte, the mode is assigned as the second byte, and the status and mode are regarded as numerical values as the third byte and the total The sum value that is calculated is assigned.

  When the peripheral control unit command reception interrupt process is started, the peripheral control MPU 4150a of the peripheral control unit 4150 determines whether or not the 1-byte reception period timer has timed out as shown in FIG. 71 (step S1200). The 1-byte reception period timer sets a period during which 1-byte (8-bit) information can be received from the main peripheral serial data transmitted from the main control board 4100.

  When the 1-byte reception period timer has not timed out in step S1200, that is, when it is within a period in which 1-byte (8-bit) information can be received from the main peripheral serial data transmitted from the main control board 4100, the peripheral The 1-byte information received from the reception buffer of the main I / O port for the main control board incorporated in the control MPU 4150a is fetched (step S1202), and the value 1 is added to the reception counter SRXC (increment, step S1204). This reception counter SRXC is a counter indicating the number of times the data has been extracted from the reception buffer. When the status, which is the first byte of the main peripheral serial data, is extracted from the reception buffer, the value is 1, and the mode is the second byte of the main peripheral serial data. The value is 2 when extracted from the reception buffer, and the value is 3 when the sum value, which is the third byte of the main serial data, is extracted from the reception buffer. The reception counter SRXC is set to an initial value 0 when the power is turned on.

  Subsequent to step S1204, it is determined whether or not the reception counter SRXC has a value of 3, that is, whether or not the sum value that is the third byte of the main peripheral serial data has been extracted from the reception buffer (step S1206). In this determination, the status that is the first byte of the main peripheral serial data, the mode that is the second byte of the main peripheral serial data, and the sum value that is the third byte of the main peripheral serial data are sequentially received from the reception buffer. It is determined whether or not it has been taken out.

  When the reception counter SRXC is not the value 3 in step S1206, that is, following the status that is the first byte of the main peripheral serial data, the mode that is still the second byte of the main peripheral serial data, and the third byte of the main peripheral serial data When the sum values are not sequentially taken out from the reception buffer, the 1-byte reception period timer is set (step S1208), and this routine is terminated. By setting the 1-byte reception period timer in step S1208, a mode in which the mode which is the second byte of the main circumference serial data or the sum value which is the third byte of the main circumference serial data can be received is set.

  On the other hand, when the reception counter SRXC has a value of 3 in step S1206, that is, following the status that is the first byte of the main peripheral serial data, the mode that is the second byte of the main peripheral serial data, and the main peripheral serial data 3 When the sum value which is the byte is taken out from the reception buffer in order, the initial value 0 is set in the reception counter SRXC (step S1210), and the sum value is calculated (step S1212). In this calculation, the status that is the first byte of the main circumference serial data and the mode that is the second byte of the main circumference serial data, which have already been extracted from the reception buffer in step S1202, are regarded as numerical values and the sum (sum value). ) Is calculated.

  Subsequent to step S1212, it is determined whether or not the sum value that is the third byte of the main serial data already extracted from the reception buffer in step S1202 matches the sum value calculated in step S1212 (step S1212). S1214). The sum value that is the third byte of the main circumference serial data already extracted from the reception buffer in step S1202 is the sum value allocated as the third byte of the main circumference serial data from the main circumference serial data from the main control board 4100. Therefore, it should match the sum value calculated in step S1212. However, the pachinko gaming machine 1 is supplied with game balls from the pachinko island facility, and when the game balls rub against each other and are charged, electrostatic discharge is generated to generate noise, so the pachinko gaming machine 1 is affected by noise. The environment is susceptible. Therefore, in this embodiment, the peripheral controller 4150 side regards the status assigned as the first byte of the received main circumference serial data and the mode assigned as the second byte of the main circumference serial data as numerical values. The sum (sum value) is calculated, and the calculated sum value matches the sum value allocated as the third byte of the main circumference serial data among the main circumference serial data from the main control board 4100. It is determined whether or not. As a result, the peripheral control MPU 4150a determines whether or not the main peripheral serial data is changed to the main peripheral serial data different from the normal due to the influence of noise between the main control board 4100 and the peripheral control board 4140. be able to.

  In step S1214, if the sum value that is the third byte of the main circumference serial data already extracted from the reception buffer in step S1202 matches the sum value calculated in step S1212, the received main circumference serial data is received. The status assigned as the first byte and the mode assigned as the second byte of the main peripheral serial data are shown in FIG. 18 as the received command storage area 4150cac of the peripheral control RAM 4150c externally attached to the peripheral control MPU 4150a. (Step S1216), and this routine is terminated. The reception command storage area 4150cac is used as a ring buffer, and the status allocated as the first byte of the main circumference serial data and the mode allocated as the second byte of the main circumference serial data are: It is stored in the peripheral control unit reception ring buffer of 4150cac. This “peripheral control unit reception ring buffer” is a buffer that is used so that the end and the beginning of the buffer are connected. Remember. When the peripheral control MPU 4150a stores the received data in the peripheral control unit reception ring buffer in step S1216, the peripheral control MPU 4150a allocates the received status assigned as the first byte of the main peripheral serial data and the second byte of the main peripheral serial data. Are stored in association with each other, and the sum value allocated as the third byte is discarded.

  On the other hand, when the 1-byte reception period timer has not timed out in step S1200, that is, it exceeds the period in which 1-byte (8-bit) information can be received from the main peripheral serial data transmitted from the main control board 4100. Sometimes, or in step S1214, if the sum value that is the third byte of the main peripheral serial data already extracted from the reception buffer in step S1202 and the sum value calculated in step S1212 do not match, this routine is directly executed. finish.

[18-1-5. Peripheral control unit power failure warning signal interrupt processing]
Next, the peripheral control unit power failure warning signal executed when the power failure warning signal (peripheral power failure warning signal) from the power failure monitoring circuit 4100e of the main control board 4100 shown in FIG. The interrupt process will be described. When the peripheral control unit power failure warning signal interruption process is started, the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 17 first activates a 2 microsecond timer (step S1300), and a power failure notification signal (peripheral power failure notification). It is determined whether or not a signal is input (step S1302). If no power failure warning signal (peripheral power failure warning signal) is input in this determination, this routine is terminated as it is.

  On the other hand, when a power failure warning signal is input in step S1302, it is determined whether or not 2 microseconds have elapsed (step S1304). In this determination, it is determined whether or not the timer started in step S1300 has passed 2 microseconds. If it is determined in step S1304 that 2 macroseconds have not elapsed, the process returns to step S1302 to determine whether or not a power failure warning signal has been input. If a signal is input, it is determined again in step S1304 whether 2 microseconds have elapsed. That is, in the determination in step S1304, it is determined whether or not the power failure warning signal is continuously input for 2 microseconds after the peripheral control unit power failure warning signal interrupt processing, which is this routine, is started.

  When the peripheral control unit power failure warning signal interrupt processing, which is this routine, is started in step S1304 and the power failure warning signal is continuously input for 2 microseconds, power saving processing is performed (step S1306). In this power saving process, the entire system of the pachinko gaming machine 1 is sequentially executed by turning off the backlight of the game board side effect display unit 1900, turning off the excitation of motors and solenoids provided in the game board 4, and turning off various LEDs. By suppressing this power consumption, stable operation is ensured only for a period of 20 milliseconds, which is the time during which the peripheral control MPU 4150a can operate even when the power of the pachinko gaming machine 1 is cut off.

  Subsequent to step S1306, command reception standby processing is performed (step S1308). In this command reception standby process, assuming that there are various commands being transmitted by the main control board 4100, the peripheral control MPU 4150a can receive at least a period of 17 milliseconds so that the command being transmitted can be received. It is supposed to wait. When the command is received, the peripheral control unit command reception interrupt process described above is started, and the received command storage area 4150cac (peripheral control unit reception ring buffer of the peripheral control RAM 4150c externally attached to the peripheral control MPU 4150a shown in FIG. ) Stores the received command.

  Subsequent to step S1308, command backup processing is performed (step S1310). In the backup processing of this command, the contents stored in the received command storage area 4150cac included in Bank0 (1fr) in the backup target work area 4150ca shown in FIG. The peripheral control DMA controller 4150ac copies to Bank2 (1fr) at high speed, and the peripheral control DMA controller 4150ac copies to Bank3 (1fr) and Bank4 (1fr) in the backup second area 4150cc at high speed.

  Briefly describing the high-speed copy of the contents stored in the received command storage area 4150cac included in Bank0 (1fr) by the peripheral control DMA controller 4150ac, the peripheral control MPU core 4150aa of the peripheral control MPU 4150a shown in FIG. Specify the contents stored in the received command storage area 4150cac included in Bank0 (1fr) as the request factor of the control DMA controller 4150ac, and copy to the received command storage area included in Bank1 (1fr) of the backup first area 4150cb Then, from the contents stored at the head address of the received command storage area 4150cac included in Bank0 (1fr), the end address of the received command storage area 4150cac included in Bank0 (1fr) is stored. Are copied in order from the start address of the received command storage area included in Bank1 (1fr) of the backup first area 4150cb in succession to a predetermined byte (for example, 1 byte), and the peripheral control MPU core The content stored in the received command storage area 4150cac included in Bank0 (1fr) as the request factor of the peripheral control DMA controller 4150ac is transferred to the received command storage area included in Bank2 (1fr) of the backup first area 4150cb. From the content stored at the start address of the received command storage area 4150cac included in Bank0 (1fr) to the content stored at the end address of the received command storage area 4150cac included in Bank0 (1fr) by designating copy , A predetermined number of bytes (e.g., 1 byte) all copies sequentially from the start address of the received command storage area included in the Bank2 (1FR) of the backup successively by the first area 4150Cb.

  Subsequently, the peripheral control MPU core 4150aa includes the contents stored in the received command storage area 4150cac included in Bank0 (1fr) as a request factor of the peripheral control DMA controller 4150ac in Bank3 (1fr) of the backup second area 4150cc. To the received command storage area 4150cac included in Bank0 (1fr) from the contents stored in the start address of the received command storage area 4150cac included in Bank0 (1fr). All the contents up to the specified contents are copied in order from the start address of the received command storage area included in Bank 3 (1fr) of the backup second area 4150cc in succession by a predetermined byte (for example, 1 byte), and peripheral control is performed. The PU core 4150aa uses the contents stored in the received command storage area 4150cac included in Bank0 (1fr) as a request factor of the peripheral control DMA controller 4150ac, and the received command storage area included in Bank4 (1fr) of the backup second area 4150cc. From the content stored at the start address of the received command storage area 4150cac included in Bank0 (1fr) to the content stored at the end address of the received command storage area 4150cac included in Bank0 (1fr) All the data are copied sequentially from the start address of the received command storage area included in Bank4 (1fr) of the backup second area 4150cc successively by a predetermined byte (for example, 1 byte).

  Subsequent to step S1310, it is determined whether a power failure warning signal (peripheral power failure warning signal) is input (step S1312). If a power failure warning signal is input in this determination, WDT clear processing is performed (step S1314). In this WDT clear process, the peripheral control MPU 4150a outputs a clear signal to the peripheral control built-in WDT 4150af shown in FIG. 18 and the peripheral control external WDT 4150e shown in FIG. 17 so that the peripheral control MPU 4150a is not reset. .

  On the other hand, when the power failure warning signal is not input in step S1312, or following step S1314, the process returns to step S1312, and it is determined whether the power failure warning signal is input. That is, it is determined indefinitely whether or not a power failure warning signal (peripheral power failure warning signal) is input. By continuing the determination infinitely in this way, when the power failure warning signal (peripheral power failure warning signal) is not input in step S1312, the peripheral control MPU 4150a clears the peripheral control built-in WDT 4150af and the peripheral control external WDT 4150e. Cannot be output and the peripheral control MPU 4150a is reset. On the other hand, when a power failure warning signal is input in step S1312, the WDT clear process is performed in step S1314, and the peripheral control MPU 4150a is not reset. When the peripheral control MPU 4150a is reset, the peripheral control unit power-on process shown in FIG. 68 is started again.

  As described above, when the power failure warning signal (peripheral power failure warning signal) continues to be input in the infinite loop as determined in step S1312, the peripheral control is performed immediately before the power failure state is established by executing the WDT clear process in step S1314. The MPU 4150a is not reset. On the other hand, when the input of the power failure warning signal is canceled without being continued in the infinite loop in the determination in step S1312, the WDT clear process is not executed, so the peripheral control built-in WDT 4150af and the peripheral control external WDT 4150e are The output of the clear signal is interrupted. As a result, even if the peripheral control unit power failure warning signal interrupt processing, which is this routine, is started erroneously due to noise or the like and the noise is generated beyond the period of 2 microseconds, the determination of step S1302 is passed. If the input of the power failure warning signal (peripheral power failure warning signal) is canceled without being continued in the infinite loop as determined in S1312, the peripheral control MPU 4150a is reset because the WDT clear process in step S1314 is not executed. Therefore, it is possible to cope with such noise by automatically resetting and returning.

[18-1-6. Power saving mode transition judgment process at power recovery]
Next, when the power is turned off (immediately before the power is turned off), the power state consumed by the pachinko gaming machine 1 is grasped at the time of power restoration, and the power saving mode is switched to the power saving mode for suppressing power consumed by the pachinko gaming machine 1 In the case of shifting to the power saving mode at the time of power recovery, the volume of the effect sound flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 is reduced. The power saving mode transition determination process at the time of power recovery will be described in which setting is made to reduce the brightness of the plurality of LEDs provided on each decorative board of the door frame 5 and the plurality of LEDs provided on each decorative board of the game board 4. . This power saving mode transition determination process at the time of power recovery is performed in the process of step S1004 in the peripheral control part steady process of the peripheral control part power-on process shown in FIG.

  When the power saving power saving mode transition determination process is started, the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 17 specifies the power consumption suppression stage based on the power consumption status history information as shown in FIG. (Step S1350). As described above, the power consumption status history information is a value (which is transmitted by the power consumption suppression signal from the power supply board 851 in the power consumption status history information generation processing in step S1113 in the peripheral control unit 1 ms timer interrupt processing shown in FIG. By sampling values 0 to 7) and sequentially storing them in the power consumption status history RAM 4150f of the peripheral control unit 4150 shown in FIG. 17 as the power consumption suppression stage (stage 0 to stage 7), the power consumption suppression stage is timed. Arranged in series. The power consumption status history RAM 4150f stores the power consumption status history information of the power consumption status history storage unit 4150f by supplying backup power from the battery 4150g of the peripheral control unit 4150 shown in FIG. It has come to be.

  In step S1350, among the power consumption status history information in which the values sampled and stored by the peripheral control MPU 4150a are arranged in time series, the power of the pachinko gaming machine 1 is turned off (power failure or momentary power failure due to power consumption of the pachinko gaming machine 1). For example, in addition to power outages due to lightning strikes and momentary power outages due to lightning strikes, power outages supplied to halls, momentary power outages due to instability of power supplied to halls, pachinko machines by hall staffs, etc. Including the power shutdown to 1.) The value sampled and stored immediately before is extracted, and the power consumption suppression stage immediately before the power shutdown is specified. Thereby, the power consumption suppression stage immediately before the power-off of the pachinko gaming machine 1 can be grasped.

  Following step S1350, it is determined whether the power consumption suppression stage has reached a threshold value (step S1352). In this determination, it is determined whether or not the power consumption suppression stage immediately before the power-off of the pachinko gaming machine 1 specified in step S1350 has reached a threshold value. In the present embodiment, stage 7 is set as the threshold value.

  When the power consumption suppression stage has not reached the threshold value in step S1352, the power saving mode transition flag ECO-FLG at power recovery is set to 0 (step S1354), and this routine is terminated, while power consumption is performed in step S1352. When the suppression stage has reached the threshold value, the power-saving power saving mode transition flag ECO-FLG is set to a value 1 (step S1356), and power-saving power saving mode timer activation processing is performed (step S1358). Exit.

  The power saving mode transition flag ECO-FLG at the time of power recovery indicates that the effect sound flowing from the speaker housed in the speaker box 820 provided on the main body frame 3 and the speaker 130 provided on the door frame 5 when the pachinko gaming machine 1 is restored. Transition to power-saving mode for power recovery when setting to decrease the volume, setting to decrease the brightness of the plurality of LEDs provided on each decoration board of the door frame 5 or the plurality of LEDs provided on each decoration board of the game board 4 Whether or not to shift to the power saving mode at the time of power recovery, and to 0 when shifting to the power saving mode at the time of power recovery.

  The power-saving power-saving mode timer activated in step S1358 measures the power-saving power-saving mode state maintenance period during which the pachinko gaming machine 1 is activated as the power-saving power-saving mode. In the embodiment, 5 minutes is set as the power saving mode state maintenance period at the time of power recovery. When the power saving power saving mode timer is started and the time of the power saving power saving mode state maintenance period is started and the power saving power saving mode state maintenance period elapses, the power saving power saving mode timer is stopped and the power saving power mode timer is stopped as shown in FIG. In order to suppress this power consumption according to the power consumption in the pachinko gaming machine 1 by the power processing amount monitoring process in step S1027 in the peripheral control unit steady process of the peripheral control unit power-on process shown in FIG. 3 on the loudspeaker housed in the loudspeaker box 820 and the loudspeaker 130 provided on the door frame 5, the plurality of LEDs provided on each decorative board of the door frame 5, and the decorative boards of the game board 4. The brightness of the plurality of LEDs provided is adjusted.

[18-1-7. Power consumption monitoring process]
Next, the power consumption monitoring process for adjusting the volume and the brightness of various LEDs in order to suppress the power consumption according to the power consumption in the pachinko gaming machine 1 will be described. This power consumption monitoring process is performed in the process of step S1027 in the peripheral control part steady process of the peripheral control part power-on process shown in FIG.

  When the power consumption monitoring process is started, the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 17 specifies the power consumption suppression stage based on the power consumption suppression signal as shown in FIG. 74 (step S1400). ). As described above, the power consumption suppression signal is output from the power consumption monitoring circuit 855da. As shown in FIG. 22A, the power consumption monitoring circuit 855da includes a power measurement circuit 855daa and a power consumption suppression stage determination circuit 855dab. + 37V supplied from the smoothing circuit 855c is supplied to the + 5V power generation circuit 855db, the + 12V power generation circuit 855dc, and the + 24V power supply generation circuit 855dd via the power measurement circuit 855daa. The power measurement circuit 855daa measures the power consumption of + 37V supplied from the smoothing circuit 855c in real time and outputs it to the power consumption suppression stage determination circuit 855dab. The power consumption suppression stage determination circuit 855dab determines a power consumption suppression stage indicating how much power consumption should be suppressed based on the power consumption measured by the power measurement circuit 855daa. By setting the value of the power consumption suppression signal configured as a signal wiring and outputting it to the frame peripheral relay terminal plate 868, the power consumption suppression signal is input to the peripheral control unit 4150 via the frame peripheral relay terminal plate 868. It has come to be. As described above, the power consumption suppression signal is configured as three signal wirings (that is, configured as three parallel signals), and transmits eight values from 0 to 7. Can be done.

  As described above, the power consumption suppression stage determination circuit 855dab determines that it is stage 0 as the power consumption suppression stage when the power consumption of + 37V measured by the power measurement circuit 855daa is 0% or more and less than 10%. When the value of 0 is set as the value of the suppression signal and the power consumption of + 37V measured by the power measurement circuit 855daa is 10% or more and less than 20%, it is determined as stage 1 as the power consumption suppression stage and the power consumption suppression signal The value 1 is set as the value, and when the power consumption of +37 V measured by the power measuring circuit 855daa is 20% or more and less than 30%, it is determined as the stage 2 as the power consumption suppression stage and the value as the value of the power consumption suppression signal 2 and when the power consumption of + 37V measured by the power measurement circuit 855daa is 30% or more and less than 40%, When the power consumption suppression signal is determined to be stage 3 as the suppression stage and the value 3 is set as the value of the power consumption suppression signal and the power consumption of +37 V measured by the power measurement circuit 855daa is 40% or more and less than 50%, the power consumption suppression stage When the power consumption suppression signal is determined to be step 4 and the value 4 is set as the value of the power consumption suppression signal and the power consumption of + 37V measured by the power measurement circuit 855daa is 50% or more and less than 60%, the power consumption suppression step is performed in step 5 If a value 5 is set as the value of the power consumption suppression signal after determination and the power consumption of +37 V measured by the power measurement circuit 855daa is 60% or more and less than 70%, it is determined that the power consumption suppression stage is stage 6. When the value 6 is set as the value of the power consumption suppression signal, the power consumption of +37 V measured by the power measurement circuit 855daa is 70% or more. It is adapted to set the value 7 as the value of the power consumption suppression signal to determine a phase 7 as a power consumption inhibiting step for.

  In step S1400, the value of the power consumption suppression signal set by the power consumption suppression level determination circuit 855dab can be acquired, and the power consumption suppression level can be identified from the acquired value.

  Subsequent to step S1400, it is determined whether or not the power saving mode transition flag ECO-FLG at the time of power recovery is a value 1 (step S1402). As described above, the power saving power saving mode transition flag ECO-FLG is set in the power saving power saving mode transition determination process in step S1004 in the peripheral control part steady process of the peripheral control part power-on process shown in FIG. At the time of power recovery of the pachinko gaming machine 1, a setting for reducing the volume of the production sound flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, and each decoration of the door frame 5 It is set whether or not to shift to the power saving mode at the time of power recovery for setting the brightness of the plurality of LEDs provided on the board or the plurality of LEDs provided on each decoration board of the game board 4 to be reduced. A value of 0 is set when not entering the power saving mode, and a value of 0 is set when entering the power saving mode when the power is restored.

  When the power saving power saving mode transition flag ECO-FLG is not a value 1 (value 0) in step S1402, that is, when the power saving power saving mode is not entered, a normal power suppression volume setting process is performed (step S1404). . In this normal power suppression volume setting process, the master volume value for adjusting the volume of the output channel specified in the sound command data constituting the sound generation schedule data is forcibly changed to the master volume value for power suppression. Change to

  The value set as the master volume value for power suppression will be briefly described. As shown in FIG. 75A, the peripheral control MPU 4150a uses the stage 0 to stage 7 as the power consumption suppression stage on the horizontal axis. The ratio to the master volume value for adjusting the volume of the output channel specified in the command data (hereinafter referred to as “the master volume value specified in the sound command data”) (that is, as the master volume value for power suppression) Assuming that the set value) is the vertical axis, when the power consumption suppression stage is stage 0 or stage 1, that is, when the power consumption suppression stage acquired in step S1400 is stage 0 or stage 1, the master volume for power suppression The volume is 100% of the master volume value defined in the sound command data (in other words, power suppression When the power consumption suppression stage is stage 2 or stage 3, that is, the power consumption suppression stage acquired in step S1400 is stage 2 or When it is stage 3, the volume of 90% is set as the master volume value for the sound command data as the master volume value for power suppression, and when the power consumption suppression stage is stage 4, that is, the power acquired in step S1400 When the consumption suppression stage is stage 4, a volume of 80% is set as the master volume value for power control as the master volume value for power suppression, and when the power consumption suppression stage is stage 5, that is, step S1400. When the power consumption suppression step acquired in step 5 is step 5, When the volume level is set to 70% with respect to the master volume value defined in the sound command data as the volume value and the power consumption suppression stage is stage 6, that is, when the power consumption suppression stage acquired in step S1400 is stage 6. As a master volume value for power suppression, a volume of 60% is set with respect to the master volume value defined in the sound command data, and when the power consumption suppression stage is stage 7, that is, the power consumption suppression stage acquired in step S1400 is staged. When it is 7, the volume of 50% is set as the master volume value for power suppression with respect to the master volume value defined by the sound command data.

  The plurality of output channels of the built-in sound source of the built-in sound source VDP 4160a include the sound data of the effect sound incorporated in the track to be used and the effect sound incorporated in the track to be used among the plurality of tracks in the sound source of the built-in sound source of the sound source VDP 4160a. The sub volume value for adjusting the volume is synthesized, and the volume of the synthesized performance sound is actually obtained from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5. Amplification is performed up to a master volume value for power suppression, which is a flowing volume, and the amplified effect sound is serialized and output as audio data to the audio data transmission IC 4160c. In other words, when the normal power suppression volume setting process is performed, the content of the effect by the effect sound does not change, but the sound volume of the effect sound is the master volume defined by the sound command data in the power consumption suppression steps from stage 0 to stage 1. While the value itself becomes the volume, the volume set as the master volume value for power suppression becomes substantially smaller as the power consumption suppression stage proceeds from stage 2 to stage 7, so the volume of the production sound Has become smaller.

  Returning to FIG. 74, following step S1404, normal power suppression luminance setting processing is performed (step S1406). In this normal power suppression brightness setting process, the brightness of various LEDs in the light emission mode of the various LEDs defined in the light emission data constituting the light emission mode generation schedule data is forcibly changed and set from the brightness for power suppression.

  The brightness set as the power-suppressing brightness will be briefly described. As shown in FIG. 75B, the peripheral control MPU 4150a uses the steps 0 to 7 as the power consumption suppression steps on the horizontal axis to generate the light emission data. When the vertical axis represents the ratio (that is, the luminance set as the luminance for power suppression) to the luminance of various LEDs (hereinafter referred to as “luminance specified for light emission data”) in the light emission mode of the various LEDs specified, When the power consumption suppression stage is one of stage 0, stage 1, stage 2, stage 3, and stage 4, that is, the power consumption suppression stage acquired in step S1400 is stage 0, stage 1, stage 2, Of the stage 3 and stage 4, when it is one stage, the brightness for power suppression is 100% of the brightness specified in the emission data (in other words, the brightness for power suppression). When the power consumption suppression stage is stage 5, that is, when the power consumption suppression stage acquired in step S1400 is stage 5, the brightness of the emission data regulations is set as the brightness for power suppression. On the other hand, when the luminance of 70% is set and the power consumption suppression stage is stage 6, that is, when the power consumption suppression stage acquired in step S1400 is stage 6, the luminance for power suppression is set to the luminance specified in the emission data. When the power consumption suppression stage is stage 7, that is, when the power consumption suppression stage acquired in step S1400 is stage 7, the brightness of the emission data is defined as the brightness for power suppression. Set the brightness to 50%.

  When the brightness setting process for power suppression at normal time is performed, although the contents of the effect by the light emission mode of the plurality of LEDs provided on each decoration board of the door frame 5 and the plurality of LEDs provided on each decoration board of the game board 4 are not changed. The brightness of various LEDs is set as the brightness for power suppression as the power consumption suppression stage proceeds from stage 5 to stage 7 while the power consumption suppression stage reaches the brightness specified in the emission data from stage 0 to stage 4. Since the brightness to be reduced is reduced, the brightness of various LEDs is reduced.

  Subsequent to step S1406, the power saving mode transition notification LED 4150k shown in FIG. 17 is set to the non power saving notification mode (step S1407a). As described above, the power saving mode transition notification LED 4150k employs a high-luminance single color light emitting in green. The non-power-saving notification mode is to notify a staff member such as a hall clerk that the mode does not shift to the power saving mode at the time of power recovery, and is in a lighting state (that is, a lighting state in which light is emitted in green). The power saving mode transition notification LED 4150k set in step S1407a is configured so that the non power saving notification mode (that is, the lighting state in which the LED emits green light) is directly defined (set) every time this routine is executed. The light emission modes of the various LEDs described above are different in that they are configured to be defined by the light emission data constituting the light emission mode generation schedule data. An attendant such as a hall clerk inserts a key into the cylinder lock 1010 of the lock device 1000 shown in FIGS. 1 and 5 and rotates to release the closed state of the main body frame 3 with respect to the outer frame 2. 2. Opening the main body frame 3 for 2 and grasping that the light-emitting mode of the power-saving mode transition notification LED 4150k does not shift to the power-saving mode during power recovery by visually observing the non-power-saving notification mode (that is, the green lighting state) can do.

  Subsequent to step S1407a, the output of the power saving mode information output signal is set to stop (step S1407b), and this routine ends. As described above, the power saving mode information output signal is used to notify the hall computer of the transition state to the power saving mode during power recovery via the external terminal board 784 shown in FIG. 17, and in step S1402, the power saving mode during power recovery If not, the power saving mode information output signal is set not to be output in step S1407b.

  On the other hand, when the power saving power saving mode transition flag ECO-FLG is 1 (not 0) in step S1402, that is, when shifting to the power saving power saving mode, the power saving power saving mode timer has reached the upper limit time. It is determined whether or not (step S1408). As described above, the power-saving power-saving mode timer measures the power-saving power-saving mode state maintenance period during which the pachinko machine 1 is maintained in the power-saving power-saving mode. Then, 5 minutes is set as the power-saving power saving mode state maintenance period. The upper limit time used for the determination is 5 minutes of the power saving mode state maintenance period at the time of power recovery.

  In step S1408, when the power saving power saving mode timer has not reached the upper limit time, that is, when the power saving power saving mode timer has not reached 5 minutes of the power saving power saving mode state maintaining period, Setting processing is performed (step S1410). In this power reduction volume setting process for power recovery, similarly to the normal power suppression volume setting process in step S1404 described above, the volume of the output channel specified in the sound command data constituting the sound generation schedule data is set. Although it is forcibly changed from the master volume value for adjustment to the master volume value for power suppression, the volume level is always set to 50% of the master volume value specified in the sound command data as the master volume value for power suppression. It is different in point to do. In other words, in the power suppression volume setting process for power recovery, the master volume value for power suppression set when the power consumption suppression stage is stage 7 in the normal power suppression volume setting process is always set. ing.

  When the power reduction volume setting process at power recovery is performed, the content of the effect by the effect sound does not change, but the sound volume of the effect sound is set to the lowest power consumption suppression stage of Step 7. (In other words, the volume of the effect sound is set such that the power consumption suppression stage is stage 7 and the power consumption is minimized).

  Subsequent to step S1410, a power setting luminance setting process for power reduction is performed (step S1412). In the power setting luminance setting process for power recovery, in the light emission mode of various LEDs defined in the light emission data constituting the light emission mode generation schedule data, similarly to the normal power suppression luminance setting process in step S1406 described above. Although it is forcibly changed from the brightness of various LEDs to the brightness for power suppression, the difference is that the brightness of 50% is always set as the brightness for power suppression with respect to the brightness specified for the light emission data. That is, in the power setting luminance setting process for power recovery, the luminance for power suppression set when the power consumption suppression stage is stage 7 in the power setting luminance setting process for normal power is always set. .

  When the brightness setting process for power suppression during power recovery is performed, the contents of the effect by the light emission mode of the plurality of LEDs provided on each decoration board of the door frame 5 and the plurality of LEDs provided on each decoration board of the game board 4 are not changed. However, the brightness of each LED is set to the lowest power consumption suppression level of 7 (in other words, the brightness of each LED has the lowest power consumption level of 7 in the power consumption suppression stage). The smaller one is set).

  Subsequent to step S1412, the power saving mode transition notification LED 4150k is set to a power saving notification mode (step S1413a). In the power saving notification mode, a staff member such as a store clerk in the hall is notified that the power saving mode is to be entered when power is restored, and the power saving notification mode is turned off. The power-saving mode transition notification LED 4150k set in step S1413a is configured to be directly defined (set) every time this routine is executed, and thus the various LEDs described above. Are different from each other in that the light emission modes are defined by the light emission data constituting the light emission mode generation schedule data. An attendant such as a hall clerk inserts a key into the cylinder lock 1010 of the lock device 1000 shown in FIGS. 1 and 5 and rotates to release the closed state of the main body frame 3 with respect to the outer frame 2. 2, the main body frame 3 is opened, and the light-emitting mode of the power-saving mode transition notification LED 4150k is grasped to be in the power-saving mode upon power recovery by visually observing the power-saving notification mode (that is, the extinguishing state). it can. In the present embodiment, as the light emission mode of the power saving mode transition notification LED 4150k, the lighting state is set when the power saving mode is not shifted to the power recovery mode, while the light emitting mode is set to the off state when the power saving mode is restored. However, since it is necessary to suppress the power consumption in the power saving mode at the time of power recovery, the power saving mode transition notification LED 4150k is turned on when the power saving mode is not shifted to at the time of power recovery. When shifting to the power saving mode, the power saving mode transition notification LED 4150k is turned off.

  Subsequent to step S1413a, the output of the power saving mode information output signal is set to start (step S1413b), and this routine ends. When the power saving mode information output signal is output in step S1413b when the power saving mode is set in the power recovery mode in step S1402, the power saving mode timer is set to the upper limit in step S1408 every time this routine is executed. In step S1413b, the state where the power saving mode information output signal is output is maintained until the time is reached, that is, until the power saving power saving mode timer reaches 5 minutes of the power saving power saving mode state maintaining period. Is output to the external terminal board 784 and transmitted to the hall computer via the external terminal board 784, and the hall computer recognizes that the pachinko gaming machine 1 is in a state of shifting to the power saving mode upon power recovery.

  On the other hand, when the power saving power saving mode timer reaches the upper limit time in step S1408, that is, when the power saving power saving mode timer reaches 5 minutes of the power saving power saving mode state maintenance period, the power saving power saving motor In order to end the transition, the power saving power saving mode transition flag ECO-FLG is set to 0 (step S1414), the power saving power saving mode timer is stopped (step S1416), and this routine is terminated. In the power saving power saving mode timer stop process, only the process of stopping the power saving power saving mode timer is performed, and the process of initializing (resetting) the power saving power saving mode timer is not included. This is because even if the power saving mode shift flag ECO-FLG during power recovery changes from the value 0 to the value 1 due to some cause (for example, due to the influence of noise), the process proceeds to step S1408 as determined in step S1402. In the power-saving power-saving mode timer stop process, the power-saving power-saving mode timer is stopped for 5 minutes of the power-saving power-saving mode state maintenance period, which is the upper-limit time. By maintaining the state that has reached the power saving power saving mode state maintenance period of 5 minutes, the process proceeds to step S1414 in the determination of step S1408, and the power saving power saving mode transition flag is set in step S1414. This is because the value of ECO-FLG can be forcibly returned to the normal value 0. In the initial setting process of step S1000 in the peripheral controller power-on process shown in FIG. 68, the power saving power saving mode timer is initialized (reset).

  In step S1408, the power saving power saving mode timer reaches the upper limit time, and in step S1414, the power saving power saving mode transition flag ECO-FLG is set to 0 in order to end the power saving power saving mode transition flag. As a result, when this routine is executed again, the process proceeds from the step S1404 to the step 1407b in order by the determination in the step S1402, and the output state of the power saving mode information output signal is stopped in the step S1407b. That is, when the power saving power saving mode timer reaches the upper limit time in step S1408, the output state of the power saving mode information output signal is maintained every time this routine is executed again, and the power saving mode The state in which the information output signal is not output to the external terminal board 784 is transmitted to the hall computer via the external terminal board 784, and the pachinko gaming machine 1 in the hall computer has finished the state of shifting to the power saving mode at the time of power recovery. Will be grasped. At the time of power recovery, if it is determined in step S1402 that the power saving mode does not shift to power recovery mode, a state in which a power saving mode information output signal is not output to the external terminal board 784 is transmitted to the hall computer via the external terminal board 784 in step S1407b. In the hall computer, it is grasped that the pachinko gaming machine 1 is not in the power saving mode at the time of power recovery.

  Thus, in the power saving power saving mode transition determination process in step S1004 in the peripheral control part steady process of the peripheral control part power-on process shown in FIG. Setting to reduce the volume of the production sound flowing from the speaker housed in the provided speaker box 820 and the speaker 130 provided in the door frame 5, a plurality of LEDs provided on each decorative board of the door frame 5, and each decoration of the game board 4 When it is determined whether or not to shift to the power saving mode at the time of power recovery in which the setting of reducing the brightness of the plurality of LEDs provided on the substrate is made, and this determination result is not to shift to the power saving mode at the time of power recovery In step S1400, the value of the power consumption suppression signal set by the power consumption suppression stage determination circuit 855dab is acquired, and the power consumption suppression is determined from the acquired value. Since the floor can be specified, according to the power consumption in the pachinko gaming machine 1, the power consumption suppression stage is specified from among the stages 0 to 7, and each stage is determined. Corresponding to the master volume value for power suppression forcibly changed and set in the normal power suppression volume setting process in step S1404, and the normal power suppression luminance setting process in step S1406 corresponding to each stage. It is possible to control the progress of the production by the power-saving luminance that is forcibly changed and set by the low power consumption. Therefore, it is possible to prevent a power failure from occurring due to the power consumption of the pachinko gaming machine 1 itself. Moreover, it is possible to prevent the game from being interrupted due to a power failure caused by the power consumption of the pachinko gaming machine 1 itself.

  On the other hand, in the power saving power saving mode transition determination process at step S1004 in the peripheral control part steady process of the peripheral control part power-on process shown in FIG. Setting for reducing the volume of the production sound flowing from the speaker housed in the speaker box 820 and the speaker 130 provided on the door frame 5, the plurality of LEDs provided on each decorative board of the door frame 5, and each decorative board of the game board 4 When it is determined whether or not to shift to the power-saving power saving mode for performing settings for reducing the brightness of the plurality of LEDs provided, and this determination result is to shift to the power-saving power saving mode, In step S1410, the power suppression master volume value forcibly changed and set in the power recovery power suppression volume setting process in step S1410 (that is, the normal power suppression volume setting process The power suppression master volume value set when the consumption suppression stage is stage 7) and the power suppression brightness (forcibly changed and set in the power recovery brightness suppression brightness setting process in step S1412 described above) In other words, the progress of the presentation with the smallest power consumption according to the power consumption luminance setting process when the power consumption suppression stage is stage 7 in the normal power suppression luminance setting process, and the power saving mode timer during power recovery Can be controlled over 5 minutes of the power saving mode state maintenance period at the time of power recovery, which is the upper limit time. This does not cause a power outage or a momentary power failure due to power consumption of the pachinko gaming machine 1 but a power failure, for example, when a power failure due to a lightning strike or a momentary power failure due to a lightning strike causes the pachinko gaming machine 1 to power off. In addition, when the power supply of the pachinko gaming machine 1 is cut off due to a power outage of the power supplied to the hall or instability of the power supplied to the hall, and the staff of the hall or the like takes the pachinko gaming machine 1 to the pachinko gaming machine 1 Even when the power is shut off and the power is cut off, the power situation consumed by the pachinko gaming machine 1 at the time of power off (immediately before the power off) can be grasped at the time of power restoration. In step S7, the pachinko gaming machine 1 can be started in a state in which the performance can proceed with the smallest power consumption of step 7. Therefore, it is possible to prevent a power outage from occurring due to the power consumption of the pachinko gaming machine 1 itself even during power recovery. Moreover, it is possible to prevent the game from being interrupted due to a power failure caused by the power consumption of the pachinko gaming machine 1 itself.

  Also, in the present embodiment, when the normal power suppression volume setting process in step S1404 described above is performed, the content of the effect by the effect sound does not change, but the effect sound volume is changed from the power consumption suppression stage from stage 0 to stage 0. The volume of the master volume value stipulated by the sound command data is up to 1 while the volume set as the master volume value for power suppression is substantially reduced as the power consumption suppression stage proceeds from stage 2 to stage 7. Therefore, the volume of the production sound is reduced, and when the above-described normal power suppression luminance setting process in step S1406 is performed, a plurality of LEDs provided on each decorative board of the door frame 5 and the game board 4 are displayed. Although the contents of the effect by the light emission mode of the plurality of LEDs provided on each decorative board are not changed, the brightness of various LEDs is set at the power consumption suppression stage. While the luminance of the emission data is determined from 0 to step 4, the luminance set as the power suppression luminance decreases as the power consumption suppression step proceeds from step 5 to step 7. The brightness of various LEDs is reduced. In this embodiment, when the power consumption suppression stage proceeds to stage 2, the volume of the effect sound is controlled to be smaller than the brightness of various LEDs first. This is because multiple types of pachinko machines are installed in the hall and each produces various production sounds at a high volume, so even if the production sound volume is reduced, the player is not aware of the production sound. The player's willingness to play is not reduced due to the decrease in the volume of the game, and the power consumed by the pachinko gaming machine 1 can be suppressed by reducing the volume of the effect sound.

[18-1-8. LOCKN signal history creation process]
Next, the LOCKN signal history creation process executed as one process of the drawing state information acquisition process in step S1110 in the peripheral control unit 1 ms timer interrupt process shown in FIG. 70 will be described. In this LOCKN signal history creation process, a history of the LOCKN signal output from the LOCKN terminal of the receiver IC 194f included in the frame decoration drive amplifier board 194 shown in FIG. 19 is created. As described above, when the receiver IC 194f included in the frame decoration drive amplifier board 194 determines that the drawing data received from the transmitter IC 4160d included in the peripheral control board 4140 illustrated in FIG. This signal is output to convey that fact. Specifically, it is between the connection between the transmitter IC 4160d provided on the peripheral control board 4140 and the receiver IC 194f provided on the frame decoration drive amplifier board 194, that is, between the transmitter and the receiver. This signal is output to request transmission of a predetermined data pattern (SYNC pattern) for confirming (recovering) the connection.

  When the LOCKN signal history creation process is started, the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 17 is connected to the peripheral control MPU 4150a externally attached to the peripheral control MPU 4150a shown in FIG. LOCKN signal detection history information LOCKN-HIST is read out from the drawing state information acquisition storage area 4150cak (step S1500). This LOCKN signal detection history information LOCKN-HIST is stored in 1 byte (8 bits: most significant bits B7, B6, B5, B4, B3, B2, B1, and least significant bit B0, "B" represents a bit). The history of the LOCKN signal output from the LOCKN terminal of the receiver IC 194f provided in the frame decoration drive amplifier board 194 is stored in the drawing state information acquisition storage area 4150cak as LOCKN signal detection history information LOCKN-HIST. .

  Subsequent to step S1500, it is determined whether there is a LOCKN signal output from the LOCKN terminal of the receiver IC 194f included in the frame decoration drive amplifier board 194 (step S1502). This determination is made when there is a LOCKN signal from the receiver IC 194f, and the receiver IC 194f determines that the drawing data received from the transmitter IC 4160d is abnormal data, that is, between the connection between the transmitter IC 4160d and the receiver IC 194f, that is, the transmitter and receiver. While it is determined that a predetermined data pattern (SYNC pattern) for confirming (recovering) the connection with the receiver IC 194f is not transmitted, the receiver IC 194f receives the signal from the transmitter IC 4160d. It is determined that the drawn data is not abnormal data (normal data), and the connection between the transmitter IC 4160d and the receiver IC 194f, that is, the connection between the transmitter and the receiver is determined. Determines that sure (recovery) predetermined data pattern (SYNC pattern) for not transmitting the request.

  If there is a LOCKN signal from the receiver IC 194f in step S1502, the LOCKN signal detection history information is shifted (step S1504). In this LOCKN signal detection history information shift process, when there is a LOCKN signal from the receiver IC 194f, the LOCKN signal detection history information LOCKN-HIST read in step S1500 is converted into the most significant bits B7 ← B6, B6 ← B5, B5 ← B4. , B4 ← B3, B3 ← B2, B2 ← B1, B1 ← the least significant bit B0, and so on, and is shifted bit by bit from the least significant bit B0 toward the most significant bit B7.

  When the LOCKN signal detection history information LOCKN-HIST is shifted in step S1504, the value 1 is set to the least significant bit B0 of the LOCKN signal detection history information LOCKN-HIST (step S1506), and this routine is terminated.

  On the other hand, when there is no LOCKN signal from the receiver IC 194f in step S1502, the LOCKN signal detection history information is shifted (step S1508). In the LOCKN signal detection history information shift process, the same process as the LOCKN signal detection history information shift process in step S1504 is performed. When there is no LOCKN signal from the receiver IC 194f, the LOCKN signal detection history information LOCKN read in step S1500 is obtained. -HIST is changed from the least significant bit B0 to the most significant bit B7, such as the most significant bit B7 ← B6, B6 ← B5, B5 ← B4, B4 ← B3, B3 ← B2, B2 ← B1, B1 ← the least significant bit B0. Shift one bit at a time.

  When the LOCKN signal detection history information LOCKN-HIST is shifted in step S1508, the value 0 is set to the least significant bit B0 of the LOCKN signal detection history information LOCKN-HIST (step S1510), and this routine is ended.

  In this way, each time this LOCKN signal history creation process is executed, the LOCKN signal detection history information LOCKN-HIST is shifted bit by bit from the least significant bit B0 toward the most significant bit B7, and then the least significant bit B0. Since the value 1 or the value 0 is set, the history of the LOCKN signal from the receiver IC 194f can be created.

[18-1-9. Connection failure judgment process]
Next, a connection failure determination process executed as one process of the warning process in step S1024 in the peripheral control part steady process of the peripheral control part power-on process shown in FIG. 68 will be described. In this connection failure determination process, based on the history of the LOCKN signal output from the LOCKN terminal of the receiver IC 194f provided in the frame decoration drive amplifier board 194 shown in FIG. 19, the transmitter IC 4160d provided in the peripheral control board 4140 and the frame decoration drive It is determined whether or not a failure occurs in the connection between the receiver IC 194f provided on the amplifier board 194, that is, the connection between the transmitter and the receiver.

  When the connection failure determination process is started, the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 17 is connected to the peripheral control MPU 4150a externally attached to the peripheral control MPU 4150a shown in FIG. The LOCKN signal detection history information LOCKN-HIST is read from the drawing state information acquisition storage area 4150cak (step S1520). In the LOCKN signal detection history information LOCKN-HIST, as described above, the history of the LOCKN signal output from the LOCKN terminal of the receiver IC 194f included in the frame decoration drive amplifier board 194 is stored. As described above, the LOCKN signal is used to notify the receiver IC 194f provided in the frame decoration drive amplifier board 194 when the drawing data received from the transmitter IC 4160d provided in the peripheral control board 4140 is abnormal data. Specifically, the connection between the transmitter IC 4160d provided on the peripheral control board 4140 and the receiver IC 194f provided on the frame decoration drive amplifier board 194, that is, the connection between the transmitter and the receiver is confirmed ( This is a signal output to request transmission of a predetermined data pattern (SYNC pattern) for recovery.

  Following step S1520, it is determined whether there is a LOCKN signal from the receiver IC 194f (step S1522). In this determination, it is determined whether or not the LOCKN signal detection history information LOCKN-HIST read in step S1520 matches the connection confirmation determination value. This connection confirmation determination value is stored in advance in the peripheral control ROM 4150b shown in FIG. 17, and in this embodiment, is “00001111B (“ B ”represents a bit)”, and the upper 4 bits B7 to B4. Is the value 0, and the lower 4 bits B3 to B0 are the value 1. In the determination in step S1522, it is determined whether or not the lower 4 bits B3 to B0 of the LOCKN signal detection history information LOCKN-HIST match the lower 4 bits B3 to B0 of the connection confirmation determination value.

  In step S1522, when the lower 4 bits B3 to B0 of the LOCKN signal detection history information LOCKN-HIST read in step S1520 do not match the lower 4 bits B3 to B0 of the connection confirmation determination value, the peripheral control board 4140 is provided. It is determined that there is no problem in the connection between the transmitter IC 4160d and the receiver IC 194f included in the frame decoration drive amplifier board 194, that is, the connection between the transmitter and the receiver, and this routine is finished as it is. .

  On the other hand, in step S1522, when the lower 4 bits B3 to B0 of the LOCKN signal detection history information LOCKN-HIST read in step S1520 match the lower 4 bits B3 to B0 of the connection confirmation determination value, the peripheral control board 4140 The communication check counter CC− is determined to be in a state in which there is a problem between the connection between the transmitter IC 4160d included in the receiver and the receiver IC 194f included in the frame decoration drive amplifier board 194, that is, between the transmitter and the receiver. Add 1 to CNT (increment, step S1524). Each time this routine is executed, the communication check counter CC-CNT counts up the number of times determined in step S1522 that the connection between the transmitter and the receiver is defective. (Counting the cumulative number of times). Note that the communication check counter CC-CNT is reset when the pachinko gaming machine 1 is turned on and is set to 0, but is not reset by an instantaneous power failure or a power failure. The power is restored to the value of the communication check counter CC-CNT just before the moment or power failure occurs during power transmission.

  Subsequent to step S1524, it is determined whether the value of the communication check counter CC-CNT is smaller than the cumulative number upper limit CC-LMT (step S1526). In this determination, when the value of the communication check counter CC-CNT is smaller than the cumulative number upper limit value CC-LMT, the cumulative number determined to be in a state where a connection between the transmitter and the receiver is in trouble is the cumulative number. While it is determined that the upper limit value CC-LMT has not been reached, if the value of the communication check counter CC-CNT is not smaller (larger) than the cumulative number upper limit value CC-LMT, a problem has occurred in the connection between the transmitter and the receiver. It is determined that the cumulative number of times determined to be in the state has reached the cumulative number upper limit CC-LMT.

  When the value of the communication check counter CC-CNT is smaller than the cumulative number upper limit value CC-LMT in step S1526, that is, the cumulative number determined that the connection between the transmitter and the receiver is defective is the cumulative number. When the upper limit value CC-LMT has not been reached, the communication abnormality flag CC-FLG is set to 0 (step S1528), and this routine is terminated. On the other hand, when the value of the communication check counter CC-CNT is not smaller (larger) than the cumulative number upper limit value CC-LMT in step S1526, that is, it is determined that there is a problem in the connection between the transmitter and the receiver. When the accumulated number of times reaches the accumulated number upper limit CC-LMT, a value of 1 is set in the communication abnormality flag CC-FLG (step S1530), and this routine is terminated. The communication abnormality flag CC-FLG indicates that the accumulated number of times determined that the connection between the transmitter and the receiver is in trouble has reached the accumulated number upper limit CC-LMT, and the connection between the transmitter and the receiver. This flag indicates whether or not a failure has occurred. Value 1 when the connection between the transmitter and the receiver is definitely defective. A failure has occurred in the connection between the transmitter and the receiver. When the accumulated number of times determined to be in the state is not reaching the accumulated number upper limit CC-LMT, the value is set to 0, respectively. Note that the communication abnormality flag CC-FLG is reset when the pachinko gaming machine 1 is turned on and is reset with a value of 0. It is restored to the value of the communication abnormality flag CC-FLG immediately before a moment or power failure occurs during power transmission.

[18-1-10. Connection recovery process]
Next, the connection recovery process executed as one process of the warning process of step S1024 in the peripheral control part steady process of the peripheral control part power-on process shown in FIG. 68 will be described. In this connection recovery process, the connection failure determination process shown in FIG. 77 is executed. Between the connection between the transmitter IC 4160d provided in the peripheral control board 4140 and the receiver IC 194f provided in the frame decoration drive amplifier board 194, that is, the transmitter A predetermined data pattern (SYNC pattern) is output in order to confirm (recover) the connection between the receiver and the fact that the connection between the transmitter and the receiver is abnormal is notified.

  When the connection recovery process is started, the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 17 performs the peripheral control unit power-on process shown in FIG. In the scheduler update process in step S1020, it is determined whether the schedule data for screen generation is being activated among the various schedule data set in the schedule data storage area 4150cae of the peripheral control RAM 4150c shown in FIG. S1540). In this determination, in the scheduler update process, out of the screen data arranged in time series constituting the screen generation schedule data, the number of the screen data from the top screen data is to be output to the built-in sound source VDP 4160a. Then, it is determined whether or not the pointer has been updated. In other words, in the scheduler update process, when the pointer is being updated, the presentation is progressing along the screen generation schedule data. When the presentation is completed along with the data and all the pointer updates are completed, it is determined that the screen generation schedule data is not activated. In this determination, a demonstration is performed by the game board side effect display unit 1900 during the period when the start-up screen at the time of power-on of the pachinko gaming machine 1 is displayed on the game board side effect display unit 1900, or in a waiting state. It is possible to determine whether or not the current period is on the basis of the screen generation schedule data, and the start-up screen when the power of the pachinko gaming machine 1 is turned on is displayed on the game board side effect display unit 1900. If the game board is in a waiting state or a period during which a demonstration by the game board side effect display unit 1900 is being performed, the process proceeds to step S1542 which will be described later, while the startup screen when the pachinko gaming machine 1 is turned on is displayed. The period displayed on the game board side effect display unit 1900 or the waiting state If it is not a period that is doing a demonstration by the game board side effect display unit 1900 in the (mere, it is when in the standby state of the customer wait), which is as it is to terminate this routine.

  When the production is progressing along the screen generation schedule data in step S1540, that is, when the screen generation schedule data is being activated, this routine is finished as it is, while in step S1540, the screen generation schedule data is followed. When the presentation is completed and the updating of all the pointers is completed, that is, when the screen generation schedule data is not activated, it is determined whether or not the value of the communication check counter CC-CNT is not 0 (step) S1542). As described above, the communication check counter CC-CNT includes a transmitter IC 4160d provided in the peripheral control board 4140 and a frame each time the connection failure determination process shown in FIG. 77 is executed in the determination of step S1522. This counts up the number of times it is determined that there is a problem in the connection between the receiver IC 194f provided on the decorative drive amplifier board 194, that is, the connection between the transmitter and the receiver (counts the cumulative number). is there. In this determination, it is determined whether or not the number of times when it is determined that the connection between the transmitter and the receiver is in a state where a failure has occurred is even one.

  When the value of the communication check counter CC-CNT is 0 in step S 1542, that is, when the number of times determined that the connection between the transmitter and the receiver is in trouble is not once, this is left as it is. While the routine is finished, the number of times when it is determined in step S1542 that the value of the communication check counter CC-CNT is not 0, that is, the connection between the transmitter and the receiver is in trouble is even once. If there is, it is determined whether or not the value of the communication abnormality flag CC-FLG is 0 (step S1544). As described above, the communication abnormality flag CC-FLG indicates that the cumulative number of times determined that there is a problem in the connection between the transmitter and the receiver has reached the cumulative number upper limit CC-LMT, This flag indicates whether or not there is a problem with the connection between the receiver and the value 1 when the connection between the transmitter and the receiver is definitely defective. When the accumulated number of times determined to be in a state in which the connection has not reached the accumulated number upper limit CC-LMT, the value is set to 0.

  When the value of the communication abnormality flag CC-FLG is 0 in step S1544, that is, the accumulated number of times determined that the connection between the transmitter and the receiver is defective is the accumulated number upper limit value CC-LMT. If not, SYNC pattern output processing is performed (step S1546), and this routine is terminated. In this SYNC pattern output process, the peripheral control MPU 4150a outputs a connection confirmation signal to the INIT terminal of the transmitter IC 4160d provided in the peripheral control board 4140, whereby the transmitter IC 4160d provided in the peripheral control board 4140 is supplied to the frame decoration drive amplifier board 194. A predetermined data pattern (SYNC pattern) is output to the receiver IC 194f provided. This predetermined data pattern (SYNC pattern) is stored in advance in the transmitter IC 4160d and is output to the receiver IC 194f. The connection between the transmitter IC 4160d and the receiver IC 194f, that is, between the transmitter and the receiver Is to restore the connection between.

  On the other hand, when the value of the communication abnormality flag CC-FLG is not 0 (value 1) in step S1544, that is, when there is a certain failure in the connection between the transmitter and the receiver, communication error display processing is performed. (Step S1548), and this routine is finished. In this communication error display process, the display area of the game board side effect display unit 1900 provided in the game board 4 shown in FIG. 8 is used to notify that the connection between the transmitter and the receiver is surely defective. Process to draw on. For example, a message “A problem has occurred between the transmitter and the receiver. Please call the store clerk” is displayed in the display area of the game board side effect display unit 1900. Further, in the communication error display processing, a period during which the start-up screen at the time of power-on of the pachinko gaming machine 1 is displayed on the game board side effect display unit 1900, or a demonstration by the game board side effect display unit 1900 in a waiting state. In the period when the transmitter IC 4160d provided on the peripheral control board 4140 and the receiver IC 194f provided on the frame decoration drive amplifier board 194 are connected, that is, the connection between the transmitter and the receiver is defective. In order to confirm whether the LOCKN signal output request data is transmitted from the LOCKN signal output request serial I / O port built in the peripheral control MPU 4150a, the receiver IC 194f receives a LOCKN signal output request data from the LOCKN terminal as a response signal. L When the CKN signal is output to the peripheral control MPU 4150a and the LOCKN signal is not input, it is determined that a problem has occurred in the connection between the transmitter and the receiver, and a notification image (for example, “transmitter” "Please call the store clerk.") Is displayed in the display area of the game board side effect display unit 1900 and a notification sound (for example, "between the transmitter and the receiver ”) Is repeatedly performed from the speaker 130 provided on the door frame 5. At this time, you may make it perform the process which lights all the some LED provided in each decoration board of the door frame 5, and the some LED provided in each decoration board of the game board 4. FIG.

  Next, the timing at which the peripheral control MPU 4150a outputs a connection confirmation signal to the INIT terminal of the transmitter IC 4160d provided in the peripheral control board 4140 shown in FIG. 19 will be described using the timing chart of FIG.

  First, the decorative symbols variably displayed in the display area of the game board side effect display unit 1900 included in the game board 4 shown in FIG. 8 will be briefly described. Peripheral control of the peripheral control unit power-on process shown in FIG. The decorative symbol variation display is executed by a part steady process or the like, and the main control side of the main control side power-on process shown in FIG. 49 by the main control MPU 4100a of the main control board 4100 shown in FIG. The first special lottery result drawn by receiving the game ball to the first start port 2101 shown in FIG. 8 by the main process, the main control side timer interruption process shown in FIG. 50, or the like shown in FIG. When the result of the second special lottery drawn by accepting game balls to the start opening 2102 is “big hit”, the number of repetitions (number of rounds) of the opening / closing operation of the big winning opening 2103 shown in FIG. From 15 to 15 rounds, a total of 15 rounds, and in each round, within a predetermined time (for example, 30 seconds), a game ball enters the winning prize opening 2103 and the number of balls is a predetermined number (for example, 9 balls). ), The round is digested, and a predetermined number (for example, 15 balls) of game balls are paid out each time one game ball enters the big prize opening 2103. .

  The first special lottery result drawn by accepting game balls to the first start port 2101 or the second special lottery result drawn by accepting game balls to the second start port 2102 is obtained from the main control board 4100. Based on the command, the peripheral control unit 4150 on the peripheral control board 4140 controls the liquid crystal and sound control unit 4160, so that the left decorative pattern is on the left side of the display area of the game board side effect display unit 1900 and the central decorative is in the center. On the right side, the change display of the right decoration design is started on the right side, and after the predetermined time has passed, the change display of the left decoration design, the center decoration design, and the right decoration design is stopped, and the first special lottery result or the second special lottery The player can recognize the result, and at this time, the upper special symbol display 1185 or the function display unit 1180 shown in FIG. So that the user can confirm the first special lottery result or the second special lottery results in the first special symbol or the second special symbol that is displayed under the special symbol display device 1186. When the left decorative symbol, the central decorative symbol, and the right decorative symbol are displayed variably, the left decorative symbol, the central decorative symbol, and the right decorative symbol are translucent to the extent that the background image is visible. From the upper left to the lower left of the area, the central decorative symbol rotates from the upper center of the display area to the lower central, and the right decorative pattern rotates from the upper right to the lower right of the display area. When the left decorative symbol, the central decorative symbol, and the right decorative symbol are stopped, the left decorative symbol, the central decorative symbol, and the right decorative symbol correspond to the stopped decorative display. The left decorative design, the central decorative design, and the right decorative design are opaque so that the background image at the position is difficult to see. As described above, the first special symbol or the second special symbol that is displayed in the upper special symbol display 1185 or the lower special symbol display 1186 shown in FIG. The left decorative symbol, the central decorative symbol, and the right decorative symbol, which are started and stopped in the display area of the side effect display unit 1900, are synchronized.

  The peripheral control unit 4150 in the peripheral control board 4140 is a first special lottery result drawn by receiving a game ball in the first start port 2101 or a second lottery drawn by receiving a game ball in the second start port 2102. When a command from the main control board 4100 that conveys the result of the special lottery is received, the liquid crystal and sound control unit 4160 is controlled based on the received command, and as shown in FIG. 79, the game board shown in FIG. When the display of the left decorative symbol, the central decorative symbol, and the right decorative symbol is started to be displayed in the display area of the side effect display unit 1900 (timing K0), the peripheral control unit of the power-on process shown in FIG. In the scheduler update process in step S1020 in the steady process, the schedule data storage in the peripheral control RAM 4150c shown in FIG. Pointer for designating what number of screen data from the top of the screen data arranged in time series constituting the screen generation schedule data set in the area 4150cae is to be output to the built-in sound source VDP 4160a. Is updated, that is, when the pointer is updated in the scheduler update process, the production progresses according to the schedule data for screen generation. 68. When the schedule data is being activated, that is, until the change display of the left decorative design, the central decorative design, and the right decorative design is started and stopped, the peripheral control unit shown in FIG. 68 is turned on. In the warning process in step S1024 in the process peripheral control unit steady process, FIG. Be executed by the connection recovery process is determined in step S1540 in this connection restoration process, and it so as to end the routine forcibly.

  As a result, the communication check counter CC-CNT of the communication check counter CC-CNT is displayed in the display area of the game board side effect display unit 1900 until the variable display of the left decorative design, the central decorative design, and the right decorative design is started and stopped. Even when the value is not 0, that is, there is a problem between the connection between the transmitter IC 4160d provided on the peripheral control board 4140 and the receiver IC 194f provided on the frame decoration drive amplifier board 194 (that is, connection between the transmitter and the receiver). Even if the number of times it is determined that the state has occurred is the process of recovering the connection between the transmitter and the receiver without performing the SYNC pattern output process of step S1546 in the connection recovery process Step S1548 in the connection recovery process. Communication error display processing is not performed. For example, the message “A failure has occurred between the transmitter and the receiver. Therefore, the LOCKN signal from the receiver IC 194f that informs that the drawing data received from the transmitter IC 4160d is abnormal data is invalidated.

  When the display of the left decorative symbol, the central decorative symbol, and the right decorative symbol is started and stopped in the display area of the game board side effect display unit 1900 (timing K1), the peripheral control unit shown in FIG. 68 is turned on. In the scheduler update process of step S1020 in the peripheral control unit steady process of the time process, the presentation is completed along the screen generation schedule data set in the schedule data storage area 4150cae of the peripheral control RAM 4150c shown in FIG. Since all the updates have been completed, that is, in the scheduler update process, while the screen generation schedule data is not started and the screen generation schedule data is not started, the peripheral control unit shown in FIG. 68 is turned on. Step S1024 in the peripheral processing unit steady process of the time process In the connection recovery process shown in FIG. 78 executed as one process of the warning process, the process proceeds to the process of step S1542 in the process, and when the value of the communication check counter CC-CNT is 0, that is, the transmitter When it is determined that there is no failure in the connection between the receiver and the receiver, the routine is terminated as it is, but when the value of the communication check counter CC-CNT is not 0, that is, If it is determined that the connection between the transmitter and the receiver is in a state where there is a problem, the process proceeds to step S1544 in the same process, and the value of the communication abnormality flag CC-FLG is set to a value. When 0, that is, there is a problem with the connection between the transmitter and receiver If the cumulative number determined to be present does not reach the cumulative number upper limit CC-LMT, the process proceeds to step S1546 in the process, the above-described SYNC pattern output process is performed, and the routine is terminated while the communication abnormality flag CC- When the value of FLG is not 0 (value 1), that is, when there is a certain failure in the connection between the transmitter and the receiver, the process proceeds to step S1548 in the process, and the communication error display described above is performed. Perform processing and end the routine. In other words, while the left decorative symbol, the central decorative symbol, and the right decorative symbol are stopped in the display area of the game board side effect display unit 1900, the connection between the transmitter IC 4160d and the receiver IC 194f, that is, the transmitter and receiver The cumulative number of times determined that the connection between the transmitter and the receiver has failed even once, and the connection between the transmitter and the receiver is defective is the cumulative number upper limit. When the value CC-LMT has not been reached, the SYNC pattern output process is always performed, so that the connection between the transmitter IC 4160d and the receiver IC 194f, that is, the connection between the transmitter and the receiver is restored. There is a problem with the connection between When the cumulative number of times determined to be equal to the cumulative number upper limit value CC-LMT (that is, a problem has occurred in the connection between the transmitter and the receiver), a communication error display process is always performed. As a result, for example, in the display area of the game board side effect display unit 1900, a message “A problem has occurred between the transmitter and the receiver. Please call the store clerk” is displayed and notified. The LOCKN signal from the receiver IC 194f that informs that the drawing data received from the transmitter IC 4160d is abnormal data is validated.

  In the display area of the game board side effect display unit 1900, the left decorative pattern, the central decorative pattern, and the right decorative pattern are started and stopped, and the left decorative symbol, the central decorative symbol, and the right decorative symbol are displayed again. Since the left decorative pattern, the central decorative pattern, and the right decorative pattern are stopped and displayed in the display area of the game board side effect display unit 1900 in the interval period until the game is started, as described above, The LOCKN signal from the receiver IC 194f that informs that the drawing data received from the transmitter IC 4160d is abnormal data is validated, and a problem occurs between the connection between the transmitter IC 4160d and the receiver IC 194f, that is, between the transmitter and the receiver. If there is even one state When the cumulative number of times determined that the connection between the mitter and the receiver is in a state of failure does not reach the cumulative number upper limit CC-LMT, the SYNC pattern output process is always performed, so that the transmitter IC 4160d While performing processing to recover the connection between the receiver IC 194f, that is, the connection between the transmitter and the receiver, the cumulative number of times determined that the connection between the transmitter and the receiver is defective is the cumulative number. When the upper limit value CC-LMT has been reached (that is, the connection between the transmitter and the receiver has definitely failed), by performing communication error display processing, for example, game board side effect display In the display area of unit 1900, “There was a problem between the transmitter and the receiver. Please call your members. "Displays a message that to have so as to perform the process of informing.

  When the display of the left decorative design, the central decorative design, and the right decorative design is started again (timing K2), as described above, since the screen generation schedule data is being activated, the left decorative design and the central decorative design are activated. And until the right decorative symbol is stopped and displayed (timing K3), even when the value of the communication check counter CC-CNT is not 0, that is, the transmitter IC 4160d provided in the peripheral control board 4140, and the frame Even if the number of times that it is determined that a failure has occurred between the connection between the receiver IC 194f and the receiver IC 194f included in the decorative drive amplifier board 194 (that is, the connection between the transmitter and the receiver) is 1, The SYNC pattern output process of step S1546 in the connection recovery process is not performed, and the transmitter and the receiver For example, in the display area of the game board side effect display unit 1900, “transmitter” is not performed. The message “Please call the store clerk.” Is not displayed between the receiver IC 194f and the receiver IC 194f that informs that the drawing data received from the transmitter IC 4160d is abnormal data. Disable the LOCKN signal.

  In this manner, the left decorative pattern, the central decorative pattern, and the right decorative pattern are started and stopped in the display area of the game board side effect display unit 1900, and then the left decorative pattern, the central decorative pattern, and the right decorative pattern are displayed again. In the interval period until the variable display of symbols is started, the LOCKN signal from the receiver IC 194f that informs that the drawing data received from the transmitter IC 4160d is abnormal data is validated, while the game board side effect display unit In the display area 1900, the drawing data received from the transmitter IC 4160d is reported to be abnormal data until the left decorative symbol, the central decorative symbol, and the right decorative symbol change display is started and stopped. LOCKN signal from receiver IC 194f is invalidated Going on. In the display area of the game board side effect display unit 1900, the combination result of the stop display of the left decorative symbol, the central decorative symbol, and the right decorative symbol is the information most interesting to the player, which is beneficial to the player. Since the player can determine whether or not the jackpot gaming state to which the game is given occurs, the left decorative symbol, the central decorative symbol, and the right decorative symbol are variably displayed in the display area of the game board side effect display unit 1900. Then, until the left decorative symbol, the central decorative symbol, and the right decorative symbol are stopped and displayed, the processing on the game board side is not performed, but the process for recovering the connection failure between the transmitter and the receiver is not performed. By displaying the left decorative symbol, the central decorative symbol, and the right decorative symbol in the display area of the display unit 1900, the most interesting information of the player is drawn. It is made to Ryo.

  In this regard, the peripheral control MPU 4150a of the peripheral control unit 4150 on the peripheral control board 4140 displays a start-up screen when the pachinko gaming machine 1 is turned on on the game board side effect display unit 1900, or a waiting state for the customer During the period of demonstration by the game board side effect display unit 1900, the LOCKN signal output request data from the built-in LOCKN signal output request serial I / O port is supplied to the differential circuit 4160e provided in the peripheral control board 4140. This is very different from the transmission. This LOCKN signal output request data is a demonstration by the game board side effect display unit 1900 during the period when the start-up screen at the time of power-on of the pachinko gaming machine 1 is displayed on the game board side effect display unit 1900 or in the waiting state of the customer In the period during which the peripheral control MPU 4150a performs, the transmitter IC 4160d provided in the peripheral control board 4140 and the receiver provided in the frame decoration drive amplifier board 194 This is transmitted in order to confirm whether or not a failure has occurred in the connection between the IC 194f, that is, the connection between the transmitter and the receiver.

  The LOCKN signal output request data, which is serial data output from the LOCKN signal output request serial I / O port built in the peripheral control MPU 4150a, is different from the plus signal and the minus signal in the differential circuit 4160e provided in the peripheral control board 4140. When activated, as described above, the two signals differentiated into the plus signal and the minus signal in the differencing circuit 4160e are input to the forced switching circuit 4160f provided in the peripheral control board 4140. The forcible switching circuit 4160f is connected to the circuit so as to transmit the two signals that are differentiated into the plus signal and the minus signal in the differentiation circuit 4160e. Two signals are transmitted from the peripheral control board 4140 to the frame decoration drive amplifier board 194 of the door frame 5. When the receiver IC 194f included in the frame decoration drive amplifier board 194 determines that the two received signals are the LOCKN signal output request data from the LOCKN signal output request serial I / O port, the LOCKN signal output request data is originally used. As described above, since the data format is different from the signal output from the transmitter IC 4160d, it is determined that the data is abnormal, and the LOCKN signal is transmitted to the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140. Output. As a result, the peripheral control MPU 4150a can determine that there is no problem in the connection between the transmitter and the receiver when the LOCKN signal is input as a response signal to the transmission of the LOCKN signal output request data. When the LOCKN signal is not input, it is determined that a problem has occurred in the connection between the transmitter and the receiver, and a notification image (for example, “There is a problem between the transmitter and the receiver. Please call the store clerk. ”) Is output to the game board side effect display unit 1900 by controlling the VDP 4160a with built-in sound source, and a notification sound (for example,“ There is a problem between the transmitter and the receiver). To control the VDP4160a with a built-in sound source. Informing sound flows from the speaker 130 provided in the door frame 5 by outputting the audio data transmission IC4160c. Thereby, notification can be performed by the notification image displayed in the display area of the game board side effect display unit 1900 and the notification sound that repeatedly flows from the speaker 130 provided on the door frame 5. At this time, all of the plurality of LEDs provided on each decorative board of the door frame 5 and the plurality of LEDs provided on each decorative board of the game board 4 may be lit.

  As described above, when the peripheral control MPU 4150a of the peripheral control unit 4150 transmits the LOCKN signal output request data, which is serial data, from the built-in LOCKN signal output request serial I / O port, the forcible switching circuit 4160f performs the LOCKN signal output request data. Since the receiver IC 194f receives the LOCKN signal output request data and outputs the LOCKN signal from the LOCKN terminal of the receiver IC 194f to the peripheral control MPU 4150a as a response signal. When the LOCKN signal is input, it can be determined that there is no malfunction in the connection between the transmitter and the receiver, while when the LOCKN signal is not input, the transmitter and the receiver Defect in the connection between the bus can be determined to have occurred. When the peripheral control MPU 4150a determines that a problem has occurred between the transmitter and the receiver, the peripheral control MPU 4150a can execute the communication error display process of step S1548 in the connection recovery process of FIG. 78 as a notification process. It has become. In other words, when the peripheral control MPU 4150a finds a problem between the transmitter and the receiver, it can notify the store clerk or the like of the hall by executing the notification process. The store clerk can easily check whether there is a problem between the transmitter and the receiver before the player plays the game, and the check is not time-consuming. . Therefore, the trouble between the transmitter and the receiver can be found without trouble.

  Further, as described above, when the receiver IC 194f provided in the frame decoration drive amplifier board 194 determines that the drawing data received from the transmitter IC 4160d provided in the peripheral control board 4140 is abnormal data, the LOCKN signal notifies the fact. Specifically, it is a signal to be output, specifically, the connection between the transmitter IC 4160d provided in the peripheral control board 4140 and the receiver IC 194f provided in the frame decoration drive amplifier board 194, that is, the connection between the transmitter and the receiver is confirmed. Since this is a signal output to request transmission of a predetermined data pattern (SYNC pattern) for (recovery), the receiver IC 194f and the receiver IC 194f are not able to normally receive an image transmitted from the transmitter IC 4160d. A LOCKN signal can be output to the peripheral control MPU 4150a of the peripheral control unit 4150 in order to inform that the drawing data received due to a communication failure occurs during image communication with the mitter IC 4160d. ing. As a result, the peripheral control MPU 4150a to which the LOCKN signal is input outputs a connection confirmation signal indicating that transmission of a predetermined data pattern (SYNC pattern) from the transmitter IC 4160d to the receiver IC 194f is started. It is possible to eliminate communication problems in In other words, the peripheral control MPU 4150a can detect a problem between the transmitter and the receiver due to a communication problem between image communications at an early stage, and can act on the transmitter IC 4160d to eliminate the problem. Therefore, it is possible to suppress a decrease in the player's willingness to play by finding and solving a problem between the transmitter and the receiver.

  Further, the receiver IC 194f that receives an image transmitted from the transmitter IC 4160d informs that a communication failure has occurred between the image communications between the receiver IC 194f and the transmitter IC 4160d when the image transmitted from the transmitter IC 4160d cannot be normally received. Since the LOCKN signal, which is a communication failure occurrence signal, can be output to the peripheral control MPU 4150a of the peripheral control unit 4150, which is an effect control microprocessor, the peripheral control MPU 4150a, to which the LOCKN signal is input, includes liquid crystal and sound. An image indicating that a communication failure has occurred by controlling the VDP 4160a with built-in sound source of the control unit 4160, “A failure has occurred between the transmitter and the receiver. Please call the store clerk”. It generates cormorants message, so that it is possible to notify to display the generated image on the display area of the game board side effect display unit 1900. In other words, the peripheral control MPU 4150a discovers a malfunction between the transmitter and the receiver at an early stage due to a communication malfunction between image communications, and notifies the player sitting on the front of the pachinko gaming machine 1 to that effect. Since the player can notify the hall clerk, etc., or directly notify the hall clerk who passed by in front of the pachinko gaming machine 1, the hall clerk, etc. You can start working on the problem at an early stage. Therefore, it is possible to suppress a decrease in the player's willingness to play by detecting and resolving a problem between the transmitter and the receiver at an early stage.

  Furthermore, the peripheral control MPU 4150a of the peripheral control unit 4150 connects the transmitter IC 4160d provided in the peripheral control board 4140 and the receiver IC 194f provided in the frame decoration drive amplifier board 194 in the period (interval period) from timing K1 to timing K2. In other words, it is determined that the connection between the transmitter and the receiver is defective even once, and the connection between the transmitter and the receiver is defective. When the cumulative number does not reach the cumulative number upper limit CC-LMT, transmission of a predetermined data pattern (SYNC pattern) for activating the LOCKN signal and eliminating communication troubles between image communications from the transmitter IC 4160d to the receiver IC 194f is started. To do The connection confirmation signal transmitted to the transmitter IC4160d, until the cumulative number reaches the accumulated count upper limit value CC-LMT, and is capable to continue to repeatedly output. As a result, the peripheral control MPU 4150a of the peripheral control unit 4150 starts changing the first special symbol or the second special symbol game in the upper special symbol display 1185 or the lower special symbol display 1186 by the main control MPU 4100a of the main control board 4100. Since the connection confirmation signal can be continuously output only during the period in which the game is not stopped and the game is not being executed, the communication failure can be solved.

  The peripheral control MPU 4150a of the peripheral control unit 4150 is connected between the connection between the transmitter IC 4160d provided in the peripheral control board 4140 and the receiver IC 194f provided in the frame decoration drive amplifier board 194 in the period (interval period) from timing K1 to timing K2. In other words, it is a case where there is a failure in the connection between the transmitter and the receiver even once, and it is determined that there is a failure in the connection between the transmitter and the receiver. When the number of times does not reach the cumulative number upper limit CC-LMT, transmission of a predetermined data pattern (SYNC pattern) for activating the LOCKN signal and eliminating communication troubles between image communications is started from the transmitter IC 4160d to the receiver IC 194f. To the effect When the main control MPU 4100a of the main control board 4100 continuously outputs the connection confirmation signal to the transmitter IC 4160d until the cumulative count reaches the cumulative count upper limit CC-LMT. When the special symbol display 1186 starts changing the first special symbol or the second special symbol game and starts executing the game again, the connection confirmation signal is stopped and the transmitter IC 4160d is output from the peripheral control MPU 4150a. When the connection confirmation signal is stopped and the connection confirmation signal is not input, transmission of a predetermined data pattern (SYNC pattern) to the receiver IC 194f is stopped, and an image generated by the liquid crystal and sound source built-in VDP 4160a of the sound control unit 4160 is generated. Output to the receiver IC 194f It has become to so that. As a result, the peripheral control MPU 4150a of the peripheral control unit 4150 starts changing the first special symbol or the second special symbol game in the upper special symbol display 1185 or the lower special symbol display 1186 by the main control MPU 4100a of the main control board 4100. By continuing to output the connection confirmation signal, which is a problem resolution signal, only during the period when the game is not stopped and the progress of the game is not executed, it is possible to move toward a direction in which the communication problem is resolved. Therefore, the main control MPU 4100a of the main control board 4100 starts changing the first special symbol or the second special symbol game on the upper special symbol display 1185 or the lower special symbol display 1186, and stops the display. When the connection confirmation signal is repeatedly output only during the period of not being executed, the main control board 4100 Even if the control MPU 4100a starts to fluctuate the first special symbol or the second special symbol game in the upper special symbol display 1185 or the lower special symbol display 1186 and starts to execute the game again, the control MPU 4100a Each time the main control MPU 4100a of the main control board 4100 starts executing the game again and ends it (every time period from the timing K1 to the timing K2 (interval period)), the defect may be caused to be resolved. it can.

[19. Screen displayed in the display area of the game board side effect display unit]
Next, screens displayed in the display area of the game board side effect display unit 1900 provided in the game board 4 shown in FIG. 8 will be briefly described with reference to FIGS. The screen displayed in the display area of the game board side effect display unit 1900 is the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 shown in FIG. Displayed by executing the control unit steady process or the like. Thereby, various effects are advanced in the display area of the game board side effect display unit 1900. Here, an example of a variable display effect displayed in the display area of the game board side effect display unit 1900 will be described first, and then displayed in the display area of the game board side effect display unit 1900 with the switching of the light guide plate. An example of the effect to be performed will be described. FIG. 80 is a diagram showing an example of a variable display effect displayed in the display area of the game board side liquid crystal display device, and FIG. 81 is displayed in the display area of the game board side effect display unit with the switching of the light guide plate. 82 is a diagram showing an example of the effect, FIG. 82 is a diagram showing an example of the continuation effect of FIG. 81, FIG. 83 is a diagram showing an example of the continuation effect of FIG. 82, and FIG. 84 is a continuation of FIG. It is a figure which shows an example of no effect.

[19-1. Variation display effect displayed in display area of game board side effect display unit]
First, a variation display effect displayed in the display area of the game board side effect display unit 1900 will be described with reference to FIG. FIG. 8 shows the main control side main process of the main control side power-on process shown in FIG. 49 by the main control MPU 4100a of the main control board 4100 shown in FIG. 14 and the main control side timer interrupt process shown in FIG. The first special lottery result drawn by accepting game balls to the first start port 2101 or the second special lottery result drawn by accepting game balls to the second start port 2102 shown in FIG. In the case of “big hit”, the number of repetitions (number of rounds) of the opening and closing operation of the grand prize opening 2103 shown in FIG. 8 is 15 rounds from 1 round to 15 rounds, and each round is within a predetermined time (for example, 30 seconds). When a game ball enters the grand prize opening 2103 and the number of balls reaches a predetermined number (for example, nine balls), the round is digested. Each time technique sphere is 1 ball entering the sphere, a predetermined number (e.g., 15 balls) game ball is adapted to be paid out.

  The first special lottery result drawn by accepting game balls to the first start port 2101 or the second special lottery result drawn by accepting game balls to the second start port 2102 is obtained from the main control board 4100. The peripheral control unit 4150 of the peripheral control board 4140 shown in FIG. 17 controls the liquid crystal and sound control unit 4160 based on the effect commands related to the game effects, which are various commands shown in FIG. As shown in the figure, the decorative display 1950a is displayed on the left side of the display area of the game board side effect display unit 1900, the decorative design 1950b is displayed on the center, and the decorative design 1950c is displayed on the right side. The variation display of symbols 1950a to 1950c is stopped so that the player can recognize the first special lottery result or the second special lottery result. Going on. At this time, the first special lottery result or the second special symbol is also displayed in the first special symbol or the second special symbol displayed on the upper special symbol display 1185 or the lower special symbol display 1186 shown in FIG. The lottery result can be confirmed. When the decorative symbols 1950a to 1950c are variably displayed, the decorative symbols 1950a to 1950c are translucent to the extent that the background image can be visually recognized, and the decorative symbol 1950a extends from the upper left to the lower left of the display area. Is displayed variably from the upper center of the display area toward the lower center, and the decorative pattern 1950c is variably displayed as if the reels are rotating from the upper right to the lower right of the display area. Yes.

  Specifically, in the peripheral control unit command reception interrupt process of FIG. 71, the effect control program executed by the peripheral control MPU 4150 a receives various commands from the main control board 4100. Then, in the received command analysis process of step S1022 in the peripheral control part steady process of the peripheral control part power-on process of FIG. 68, the effect control program analyzes various commands received in the peripheral control part command reception interrupt process of FIG. I do. If the analyzed command is, for example, a special figure 1 synchronized production start command classified as related to the special figure 1 synchronous production shown in FIG. 45, the production pattern shown in FIG. The display control schedule data, the light emission mode generation schedule data, the sound generation schedule data, the electrical drive source schedule data, etc., set in the variable display mode of the decorative symbols 1950a to 1950b shown in FIG. The data is extracted from the various control data copy areas 4150ce of the peripheral control ROM 4150b or the peripheral control RAM 4150c of 4150 and set in the schedule data storage area 4150cae of the peripheral control RAM 4150c.

  For example, the screen generation schedule data set in the variable display mode of the decorative symbols 1950a to 1950b is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or the various control data copy areas 4150ce of the peripheral control RAM 4150c, and the schedule of the peripheral control RAM 4150c. When set in the data storage area 4150cae, the pointer is updated in the scheduler update process in step S1020 in the peripheral control part steady process of the peripheral control part power-on process in FIG. 68, and in the display data creation process in step S1030 in the same process Of the screen data arranged in time series constituting the screen generation schedule data, the screen data indicated by the pointer is used as the peripheral control ROM 4150b or the peripheral control RAM of the peripheral control unit 4150. Extracted from 150c various control data copy area 4150ce outputs to the tone generator built VDP4160a.

  When the screen data and the light emission data are input from the peripheral control MPU 4150a, the sound source built-in VDP 4160a is supplied from the liquid crystal and sound control ROM 4160b to the game board side effect display unit 1900 based on the input screen data and the light emission data. The game board side character data to be drawn in the display area of the liquid crystal panel 5000e provided (the display area of the game board side effect display unit 1900) and the predetermined screen described above (in this embodiment, red (R): 50%, Dummy data for drawing green (G): 50%, blue (B): 50%) is extracted to create sprite data, and the game board side effect display unit 1900 (liquid crystal panel) 5000e) is drawn (displayed) for one screen (one frame) of drawing data and a predetermined screen (in this embodiment, Built-in drawing data for one screen (one frame) for drawing (displaying) red (R): 50%, green (G): 50%, blue (B): 50% Generate on VRAM.

  Specifically, the built-in sound source VDP 4160a includes the screen data that defines the configuration of the screen drawn on the game board side effect display unit 1900 (liquid crystal panel 5000e) and the sound board built-in VDP 4160a among the decorative boards of the game board 4. The peripheral control MPU 4150a inputs the light emission data that defines the light emission mode of the plurality of LEDs (decorative LEDs) provided on each of the plurality of game board side VDP control target decorative boards that are to be directly controlled. In accordance with a predetermined game board side generation rule, game board side character data for drawing in the display area of the game board side effect display unit 1900 is extracted from the liquid crystal and sound control ROM 4160b based on the input screen data. The game board side display area VRGN provided on the built-in VRAM by creating sprite data The game board side drawing data area VRGN1a is generated in the game board side drawing data area VRGN1a, and the sound source built-in VDP 4160a among the decorative boards of the game board 4 from the liquid crystal and sound control ROM 4160b is based on the inputted light emission data. Extracting game board side light emission mode setting image data for setting a light emission mode of a plurality of LEDs (decorative LEDs) provided on each of the plurality of game board side VDP control target decorative boards that are controlled directly Then, the light guide plate information and the illumination information are generated as drawing data in the game board side accompanying information area VRGN1b of the game board side display area VRGN1 provided on the built-in VRAM.

  Here, as the light guide plate information, the content of surface light emission by selecting the first light guide plate 5000d shown in FIG. The light guide plate (the second light guide plate 5000f, the third light guide plate 5000g, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k) that does not emit light is designated. Yes.

  In the display data output process of step S1016 in the same process, the effect control program outputs the drawing data for one screen (one frame) generated on the built-in VRAM of the sound source built-in VDP 4160a in the display data creation process described above. . That is, the light guide plate information and the illumination information are attached to the game board side drawing data of the screen drawn (displayed) on the game board side effect display unit 1900 (liquid crystal panel 5000e) according to the above-described predetermined game board side generation rule. As described above, the drawing data generated in the game board side display area VRGN1 is output from the channel CH1 shown in FIG. Thereby, in the display area of the game board side effect display unit 1900, the variable display screen of the decorative symbols 1950a to 1950b shown in FIG. 80A is drawn (displayed).

  As shown in FIG. 80 (a), after the predetermined time has elapsed since the change display of the decorative symbols 1950a to 1950c is started, the stop symbols of the decorative symbols 1950a to 1950c are stopped and displayed with the same decorative symbol. It will be a “big hit”. On the other hand, after the predetermined time has elapsed since the start of the display of the decorative symbols 1950a to 1950c, as shown in FIG. It becomes “out of”.

  In the present embodiment, when a state where the game ball does not enter the first start port 2101 and the second start port 2102 continues and the state where the retained balls are digested and become zero is continued for a predetermined time (for example, In this embodiment, for 60 seconds), the first light guide plate 5000d is selected from the plurality of light guide plates provided in the game board side effect display unit 1900 to emit light, and the customer shown in FIG. A demonstration screen serving as a standby screen is drawn (displayed) in the display area of the game board side effect display unit 1900. At this time, sound effects and music are set to mute. When the demonstration screen is displayed a predetermined number of times (for example, 15 times in the present embodiment) and displayed in the display area of the game board side effect display unit 1900, the display shifts to the power saving mode, and the game board side effect is displayed. A state in which nothing is displayed in the display area of the display unit 1900 (that is, a state in which a black screen is formed) is achieved. At this time, various lamps provided on the door frame 5 shown in FIG. 2 and various lamps provided on the game board 4 are also turned off.

[19-2. Effect displayed with switching of light guide plate in display area of game board effect display unit]
Next, effects (hereinafter referred to as “specific effects”) displayed with the switching of the light guide plate in the display area of the game board-side effect display unit 1900 will be described with reference to FIGS. . The effect accompanied by the switching of the light guide plate is performed during the specific effect execution period from when the variable symbols 1950a to 1950b shown in FIG.

  The first special lottery result drawn by accepting game balls to the first start port 2101 or the second special lottery result drawn by accepting game balls to the second start port 2102 is obtained from the main control board 4100. The peripheral control unit 4150 of the peripheral control board 4140 shown in FIG. 17 controls the liquid crystal and sound control unit 4160 based on the effect commands related to the game effects, which are various commands shown in FIG. As shown in the figure, a variation display of the decorative symbol 1950a on the left side of the display area of the game board side effect display unit 1900, the decorative symbol 1950b on the center, and the decorative symbol 1950c on the right side is started. Then, after the effect accompanied by the switching of the light guide plate is performed, the variable display of the decorative symbols 1950a to 1950c is stopped and the first special lottery result or So that the can be the player to recognize the second special lottery result. At this time, the first special lottery result or the second special lottery result is confirmed also in the first special symbol or the second special symbol displayed on the upper special symbol display 1185 or the lower special symbol indicator 1186 of the function display unit 1180. Be able to.

  When the decorative symbols 1950a to 1950c are variably displayed, the decorative symbols 1950a to 1950c are translucent to the extent that the background image can be visually recognized, and the decorative symbol 1950a extends from the upper left to the lower left of the display area. Is displayed variably from the upper center of the display area toward the lower center, and the decorative pattern 1950c is variably displayed as if the reels are rotating from the upper right to the lower right of the display area. Yes. Then, when the variation display of the decorative symbols 1950a to 1950c is started and the specific effect execution period comes, the decorative symbols 1950a to 1950c are directed to the lower right corner after the display area of the liquid crystal effect display unit 1900. While moving, the overall shape is reduced and the variable display is continued, and when the movement is completed to the lower right corner, the existence disappears. At this time, the variable display of the first special symbol or the second special symbol displayed on the upper special symbol display 1185 or the lower special symbol display 1186 is continued.

  Then, after the specific effect execution period has passed, the other effects are advanced, and the decorative symbols 1950a to 1950c are displayed again in the lower right corner after the display area of the liquid crystal effect display unit 1900. While moving from the corner on the side to the original position at the start of variation, the entire shape is enlarged so as to have the original size, and the variation display of the decorative symbols 1950a to 1950c is stopped, and the first special lottery result or the second The player can recognize the special lottery result.

  When the specific effect execution period arrives, the first light guide plate 5000d of the liquid crystal side effect display unit 1900 on which the decorative symbols 1950a to 1950c are variably displayed until then is selected, so this first light guide plate 5000d. (In this case, the light guide plate information specifies the content of the surface light emission by selecting the first light guide plate 5000d from among the plurality of light guide plates provided in the game board side effect display unit 1900). The other light guide plates (the second light guide plate 5000f, the third light guide plate 5000g, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k) are turned off without surface emission. The content is specified.) As shown in FIG. 81 (a), the display area of the liquid crystal panel 5000e of the liquid crystal side effect display unit 1900 has an image key. Rakuta CHA appears. Then, the process proceeds to an effect in which bullets fly toward the image character CHA.

  When a predetermined number of bullets fly toward the image character CHA, the second light guide plate 5000f becomes a backlight by switching from the first light guide plate 5000d of the liquid crystal side effect display unit 1900 to the second light guide plate 5000f. (In this case, the light guide plate information specifies the content of surface light emission by selecting the second light guide plate 5000f among the plurality of light guide plates provided in the game board side effect display unit 1900, and other light guide plates. The contents to be turned off without surface emitting are specified for the first light guide plate 5000d, the third light guide plate 5000g, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k. ) Display of the liquid crystal panel 5000e of the liquid crystal side effect display unit 1900 corresponding to the light emitting area 5000f4 formed on the second light guide plate 5000f. As shown in FIG. 81 (b), a predetermined number of holes where bullets flew toward the image character CHA are opened in the area, and an area RGN formed by these holes (that is, formed in the second light guide plate 5000f). Through the non-light emitting area 5000f3), the player sitting on the front surface of the pachinko gaming machine 1 is a part of the object (hereinafter referred to as “first part”) existing behind the liquid crystal side effect display unit 1900. It will be in the state which can be visually recognized. At this time, among the objects existing behind the liquid crystal side effect display unit 1900, the rotating light emitting device 3100 shown in FIG. 8 is lit in red and rotates (this rotating lighting mode is as described above). It is realized by adjusting the order in which a plurality of LEDs mounted on the decorative board are lit, not realized by rotating the reflector by an electric drive source such as a motor. For this reason, the red light becomes stronger or weaker through the region RGN (that is, the non-light emitting region 5000f3 formed in the second light guide plate 5000f).

  When a predetermined number of bullets fly toward the image character CHA, the third light guide plate 5000g is backlit by switching from the second light guide plate 5000f of the liquid crystal side effect display unit 1900 to the third light guide plate 5000g. (In this case, the light guide plate information specifies the content of the surface light emission by selecting the third light guide plate 5000g among the plurality of light guide plates provided in the game board side effect display unit 1900, and other guides). The content of turning off the light plate (the first light guide plate 5000d, the second light guide plate 5000f, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k) that does not emit light is specified. .), The liquid crystal panel 5000e of the liquid crystal side effect display unit 1900 corresponding to the light emitting area 5000g4 formed on the third light guide plate 5000g. As shown in FIG. 82 (c), the display area is further opened with a predetermined number of holes in which bullets fly toward the image character CHA (that is, the non-light emitting area 5000g3 formed on the third light guide plate 5000g). In addition to the holes opened so far, the player sitting on the front surface of the pachinko gaming machine 1 through the region RGN formed by the holes opened this time, among the objects existing behind the liquid crystal side effect display unit 1900, In addition to the first part, other parts (hereinafter referred to as “second part”) can be visually recognized. At this time, among the objects existing behind the liquid crystal side effect display unit 1900, the rotary light emitting device 3100 is in a rotating lighting mode. For this reason, the red light becomes stronger or weaker through the region RGN (that is, the non-light emitting region 5000g3 formed in the third light guide plate 5000g). The strength can be greatly felt by the player.

  When a predetermined number of bullets fly toward the image character CHA, the fourth light guide plate 5000h is backlit by switching from the third light guide plate 5000g of the liquid crystal side effect display unit 1900 to the fourth light guide plate 5000h. (In this case, the light guide plate information specifies the content of surface light emission by selecting the fourth light guide plate 5000h from among the plurality of light guide plates provided in the game board side effect display unit 1900, and other guides). The light-off content that does not emit light is specified for the optical plates (the first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k). .), The liquid crystal panel 5000e of the liquid crystal side effect display unit 1900 corresponding to the light emitting area 5000h4 formed on the fourth light guide plate 5000h. In the display area, as shown in FIG. 82 (d), a predetermined number of holes in which bullets flew toward the image character CHA are further opened, and in addition to the holes that have been opened so far, the holes that have been opened this time are formed. The player who sits on the front surface of the pachinko gaming machine 1 through the region RGN (that is, the non-light emitting region 5000h3 formed on the fourth light guide plate 5000h) is the object existing behind the liquid crystal side effect display unit 1900. In addition to the second part, another part can be visually recognized. At this time, among the objects existing behind the liquid crystal side effect display unit 1900, the rotary light emitting device 3100 is in a rotating lighting mode. For this reason, the red light becomes stronger or weaker through the region RGN (that is, the non-light emitting region 5000h3 formed in the fourth light guide plate 5000h). The strength can be felt even more by the player.

  When a predetermined number of bullets fly toward the image character CHA, the fifth light guide plate 5000i is backlit by switching from the fourth light guide plate 5000h of the liquid crystal side effect display unit 1900 to the fifth light guide plate 5000i. (In this case, the light guide plate information specifies the content of the surface light emission by selecting the fifth light guide plate 5000i from among the plurality of light guide plates provided in the game board side effect display unit 1900, and other guides). The contents to be turned off without surface emitting are specified for the optical plates (first light guide plate 5000d, second light guide plate 5000f, third light guide plate 5000h, fourth light guide plate 5000h, and sixth light guide plate 5000k). .), The liquid crystal panel 5000e of the liquid crystal side effect display unit 1900 corresponding to the light emitting area 5000i4 formed on the fifth light guide plate 5000i. In the display area, as shown in FIG. 83 (e), the display area of the liquid crystal panel 5000e is broken as a result of the holes that have been opened so far, and a plurality of pieces are peeled off, and a plurality of pieces are formed by peeling off the pieces. The player sitting on the front surface of the pachinko gaming machine 1 through the region RGN (that is, the non-light emitting region 5000i3 formed on the fifth light guide plate 5000i) has a plurality of objects existing behind the liquid crystal side effect display unit 1900. It will be in the state which can visually recognize that there is a point. At this time, among the objects existing behind the liquid crystal side effect display unit 1900, the rotary light emitting device 3100 is in a rotating lighting mode. For this reason, the red light becomes stronger or weaker through the region RGN (that is, the non-light emitting region 5000i3 formed in the fifth light guide plate 5000i). The strength and weakness can be felt by the player.

  After that, the sixth light guide plate 5000k becomes a backlight by switching from the fifth light guide plate 5000i of the liquid crystal side effect display unit 1900 to the sixth light guide plate 5000k (in this case, the light guide plate information includes The content of surface light emission by selecting the sixth light guide plate 5000k among the plurality of light guide plates provided in the game board side effect display unit 1900 is specified, and other light guide plates (first light guide plate 5000d, first light guide plate) The second light guide plate 5000f, the third light guide plate 5000h, the fourth light guide plate 5000h, and the fifth light guide plate 5000i) are designated to be turned off so as not to emit light)), and the sixth light guide plate 5000k. In the display area of the liquid crystal panel 5000e of the liquid crystal side effect display unit 1900 corresponding to the light emitting area 5000k4 to be formed, as shown in FIG. A message MSG “Press detonation button!” Is displayed in a strip shape below the area, and an area RGN (that is, formed on the sixth light guide plate 5000k) formed above the area where the message MSG is displayed. Through the non-light emitting area 5000k3), the player sitting on the front surface of the pachinko gaming machine 1 can visually recognize the rotary light emitting device 3100 existing behind the liquid crystal side effect display unit 1900, and the sixth light guide plate The model 3400 imitating the detonator and the model 3500 imitating the dynamite excluding the region corresponding to the light emitting region 5000k4 formed at 5000k can be seen. At this time, among the objects existing behind the liquid crystal side effect display unit 1900, the rotary light emitting device 3100 is in a rotating lighting mode. For this reason, the red light becomes stronger or weaker through the region RGN (that is, the non-light emitting region 5000k3 formed in the sixth light guide plate 5000k). The strength and weakness can be felt by the player.

  After that, the first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000g, the fourth light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k are all surfaces. In this case, the light guide plate information includes a plurality of light guide plates included in the game board side effect display unit 1900, that is, the first light guide plate 5000d, the second light guide plate 5000f, 3 light guide plate 5000h, fourth light guide plate 5000h, fifth light guide plate 5000i, and sixth light guide plate 5000k are designated to be turned off without surface emission), and liquid crystal of liquid crystal side effect display unit 1900 Since nothing is displayed in the display area of the panel 5000e, as shown in FIG. 84 (g), as shown in FIG. 3100, a state that can be visually recognized model 3400 detonators simulating, and all models 3500 imitating dynamite. At this time, among the objects existing behind the liquid crystal side effect display unit 1900, the rotary light emitting device 3100 is in a rotating lighting mode. For this reason, the red light becomes stronger or weaker through the region RGN (that is, the non-light emitting region 5000k3 formed in the sixth light guide plate 5000k). The player can feel the strength very much and the player can operate the detonator button 3400a of the model 3400 that imitates the detonator so that the detonator can be operated. It can be prompted also by the effect of mode.

  Thereafter, when the player operates the pressing operation unit 405 of the operation unit 400 attached to the upper center of the dish unit 300 in the door frame 5 shown in FIG. 2 in order to press the initiation button 3400a so that the initiation device is activated, In conjunction with this (when triggered by this), if the specific effect execution period has elapsed, or if the specific effect execution period has elapsed without the player operating the pressing operation unit 405, the liquid crystal side effect display unit 1900 The first light guide plate 5000d serves as a backlight, and the liquid crystal panel of the liquid crystal side effect display unit 1900 corresponding to the light emitting region 5000d4 (that is, the entire surface of the first light guide plate 5000d) formed in the first light guide plate 5000d. In the display area of 5000e, an image (screen) by another effect is displayed, and the effect progresses. Then, again, the decorative symbols 1950a to 1950c are displayed in the lower right corner after the display area of the liquid crystal side effect display unit 1900, and the entire pattern is moved while moving from the lower right corner to the original position at the start of the change. Each of the shapes is enlarged so as to have the original size, and the variation display of the decorative symbols 1950a to 1950c is stopped, so that the player can recognize the first special lottery result or the second special lottery result. .

  As described above, the first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000g, the fourth light guide plate 5000h, and the fifth light guide plate 5000d of the liquid crystal side effect display unit 1900 as the specific effect progresses. The light guide plate 5000i and the sixth light guide plate 5000k cause surface light emission in order, and display of the liquid crystal panel 5000e of the liquid crystal side effect display unit 1900 corresponding to surface light emission by one of the plurality of light guide plates. Since the image (screen) is drawn (displayed) in the area, the liquid crystal panel 5000e physically having another shape even though the liquid crystal panel 5000e has a rectangular shape. As a completely different existence, a display unit on which an image (screen) is drawn (displayed) appears. Such a novel effect by a specific effect can be provided to the player.

  According to the pachinko gaming machine 1 of the present embodiment described above, it is possible to produce effects based on the progress of the game, and among the decorative boards of the door frame 5 in FIG. A plurality of LEDs (decorative LEDs) provided on each of the plurality of frame-side VDP control target decorative boards to be controlled, the liquid crystal on the peripheral control board 4140 in FIG. 17 and the liquid crystal of the sound control unit 4160 as information storage means And a sound control ROM 4160b, a liquid crystal and sound control unit 4160 built-in sound source VDP 4160a in the peripheral control board 4140 in FIG. 19 as image object creation means, a parallel signal output unit in the sound source VDP 4160a in FIG. As a signal converting means, the peripheral control board 4140 in FIG. The transmitter IC 4160d, the receiver IC 194f of the frame decoration drive amplifier board 194 of FIG. 19 as signal restoration means, the frame side signal separation control circuit 194g of the frame decoration drive amplifier board 194 of FIG. 19 as extraction means, and the frame decoration of FIG. 42 as drive control means. The frame side VDP control target decoration LED control circuit 194i of the drive amplifier board 194 includes a frame side VDP control target first decoration LED control circuit 194i1 to a frame side VDP control target 143 decoration LED control circuit 194i143. .

  The liquid crystal and sound control ROM 4160b can store a plurality of types of information related to effects. Specifically, the liquid crystal and sound control ROM 4160b includes the game board side character data to be drawn in the display area of the game board side effect display unit 1900, and the above-described predetermined screen (in this embodiment, red (R)). : 50%, Green (G): 50%, Blue (B): Gray screen with 50%) and the decorative board of the game board 4 are directly controlled by the VDP 4160a with built-in sound source Game board side light emission mode setting image data for setting a light emission mode of a plurality of LEDs (decorative LEDs) provided on each of the plurality of game board side VDP control target decorative boards to be controlled, and a door frame 5, a plurality of LEDs (decoration L) provided on each of the plurality of frame side VDP control target decorative boards that are controlled by the sound source built-in VDP 4160a. A door frame-side light emission mode setting image data for setting a light emitting mode of the D), music, sound effects, and various sound data, such as alarm sound, and notification sounds, but are stored in advance.

  The sound source built-in VDP 4160a includes electrical decoration information as an image as control information for a plurality of LEDs (decorative LEDs) mounted on various decorative boards of the door frame 5 based on information read from the liquid crystal and sound control ROM 4160b. A frame-side image object can be created.

  Specifically, first, as described above, the peripheral control MPU 4150a performs time series on the screen generation schedule data according to the screen generation schedule data and the light emission mode generation schedule data set in the schedule data storage area 4150cae. Each time the V blank signal is input, the screen data arranged in the above and the light emission data arranged in time series in the light emission mode generation schedule data, one each from the top screen data, from the top light emission data. One by one is output to the sound source built-in VDP 4160a.

  The screen generation schedule data is configured by arranging screen data defining the configuration of the screen in time series, and includes screen generation schedule data for the game board side effect display unit 1900 (liquid crystal panel 5000e), and the upper plate side. Screen generation schedule data for the liquid crystal display device 470, and the order of screens to be drawn (displayed) is defined. The light emission mode generation schedule data is composed of light emission data defining the light emission mode arranged in time series, and the light emission mode generation schedule data for the plurality of LEDs provided on each decorative board of the game board 4 and the door There are schedule data for light emission mode generation for a plurality of LEDs provided on each decorative board of the frame 5, and the order of the light emission modes is defined respectively.

  The sound source built-in VDP 4160a defines a predetermined screen (in this embodiment, a gray screen having red (R): 50%, green (G): 50%, blue (B): 50%). Data and light emission of a plurality of LEDs (decorative LEDs) provided on each of a plurality of frame-side VDP control target decorative boards that are controlled by the built-in sound source VDP 4160a among the decorative boards of the door frame 5 When the light emission data defining the mode is input from the peripheral control MPU 4150a, a predetermined screen (the main screen) is selected from the liquid crystal and sound control ROM 4160b based on the input screen data according to a predetermined door frame side generation rule. In the embodiment, dummy data for drawing red (R): 50%, green (G): 50%, blue (B): 50%) is extracted and sputtered. The door frame side drawing data is generated in the door frame side drawing data region VRGN2a of the door frame side display region VRGN2 provided on the built-in VRAM, and the liquid crystal and the display data are generated based on the input light emission data. Among each decorative board of the door frame 5 from the sound control ROM 4160b, a plurality of LEDs (decorative LEDs) provided on each of the plurality of frame side VDP control target decorative boards that are controlled by the built-in sound source VDP 4160a. The door frame side light emission mode setting image data for setting the light emission mode is extracted, and the illumination information is generated as drawing data in the door frame side associated information region VRGN2b of the door frame side display region VRGN2 provided on the built-in VRAM. To do.

  The channel CH2 of the sound source built-in VDP 4160a in FIG. 19 is capable of outputting a parallel signal including a frame-side image object created by the sound source built-in VDP 4160a.

  Specifically, the channel CH2 of the sound source built-in VDP 4160a uses a parallel interface. The drawing data output from the channel CH2 is composed of three video signals, a red video signal, a green video signal, and a blue video signal, and three synchronization signals, a horizontal synchronization signal, a vertical synchronization signal, and a clock signal. ing. The sound source built-in VDP 4160a has door frame side drawing data generated in the door frame side drawing data area VRGN2a of the door frame side display area VRGN2 provided on the built-in VRAM as a frame side image object created by itself, and built-in The red video signal, the green video signal, and the blue video signal with drawing data including the illumination information generated in the door frame side accompanying information area VRGN2b of the door frame side display area VRGN2 provided on the VRAM as parallel signals Are output, and three synchronizing signals such as a horizontal synchronizing signal, a vertical synchronizing signal, and a clock signal.

  The transmitter IC 4160d of the peripheral control board 4140 converts the parallel signal output from the channel CH2 of the sound source built-in VDP 4160a into a clockless transmission system signal as a serial signal composed of a normal phase signal and a reverse phase signal. It can be output.

  Specifically, the transmitter IC 4160d is a parallel signal output from the channel CH2 of the sound source built-in VDP 4160a, which is a red video signal, a green video signal, and a blue video signal, a horizontal synchronization signal, and a vertical synchronization signal. , And clock signal are serialized into a differential serial signal (serial data) called “V-by-One (registered trademark)” of Zain Electronics Co., Ltd. which is a kind of clockless transmission system. (In other words, a parallel signal composed of three video signals, that is, a red video signal, a green video signal, and a blue video signal, and three synchronization signals such as a horizontal synchronization signal, a vertical synchronization signal, and a clock signal is multiplexed. Differential serial signal Serialized to serial data), and these various signals are transmitted from the peripheral control board 4140 to the frame peripheral relay terminal board 868 only with a differential one-pair cable in which one wiring is in the normal phase and the other wiring is in the reverse phase. , Output (transmit) to the peripheral door relay terminal plate 882 and the frame decoration drive amplifier 194.

  A twisted pair cable, which is a differential one-pair cable, is configured by twisting together a wiring that transmits a positive-phase signal and a wiring that transmits a negative-phase signal. Specifically, one wiring of the twisted pair cable is configured as a wiring for transmitting a normal phase signal, and the other wiring of the twisted pair cable is configured as a wiring for transmitting a reverse phase signal.

  The receiver IC 194f of the frame decoration drive amplifier board 194 can restore a serial signal composed of a normal phase signal and a reverse phase signal input via a twisted pair cable to a parallel signal and output the parallel signal. .

  Specifically, when receiving the serial signal (serial data) from the peripheral control board 4140 via the twisted pair cable, the receiver IC 194f outputs various serialized signals from the parallel signal (that is, the channel CH2 of the sound source built-in VDP 4160a). The drawing data is restored to three video signals, namely, a red video signal, a green video signal, and a blue video signal, and three synchronization signals such as a horizontal synchronization signal, a vertical synchronization signal, and a clock signal. The signal is output to the side signal separation control circuit 194g.

  The frame-side signal separation control circuit 194g can extract and output illumination information as control information from the frame-side image object created by the sound source built-in VDP 4160a based on the restored parallel signal output by the receiver IC 194f. It is.

  Specifically, the frame-side signal separation control circuit 194g determines the above-described predetermined screen (in this embodiment, red (R): 50%, green (G): 50 from the parallel signal restored by the receiver IC 194f. %, Blue (B): gray screen having 50%), three video signals of a red video signal, a green video signal, and a blue video signal, a horizontal synchronization signal, and a vertical synchronization signal. , And a clock signal, and among the decorative boards of the door frame 5, a plurality of frame-side VDP control target decorative boards that are controlled by the sound source built-in VDP 4160a are provided. It isolate | separates into the electrical decoration information with respect to LED (LED for decoration).

  The frame-side VDP control object decoration LED control circuit 194i of the frame-side VDP control object decoration LED control circuit 194i of the frame decoration drive amplifier board 194 in FIG. 42 has a frame-side VDP control object 143 decoration LED control circuit. 194i143 is a plurality of frames that are controlled by the built-in sound source VDP 4160a among the decorative boards of the door frame 5 based on the electrical decoration information as the control information output by the frame side signal separation control circuit 194g. It is possible to perform drive control of a plurality of LEDs (decorative LEDs) provided on each of the side VDP control target decorative boards.

  Specifically, the frame-side signal separation control circuit 194g is based on the decoration information separated from the parallel signal restored by the receiver IC 194f, and the frame-side VDP control target decoration LED control circuit 194i has a frame-side VDP control target number 194i. 1 of the decorative LED control circuit 194i1 to the frame-side VDP control target 143 of the decorative LED control circuit 194i143 of the decorative frame of the door frame 5 is the control target directly controlled by the VDP 4160a with built-in sound source. By outputting a signal to the plurality of frame side VDP control target decoration boards, a plurality of LEDs (decoration LEDs) provided on each of the plurality of frame side VDP control target decoration boards emit light. As a result, the frame-side VDP control object decoration LED control circuit 194i uses the frame-side VDP control object first decoration LED control circuit 194i1 to the frame-side VDP control object 143 decoration LED control circuit 194i143 to perform frame-side signal separation. Based on the electrical decoration information as control information separated by the control circuit 194g, among the decorative boards of the door frame 5, a plurality of frame side VDP control target decorative boards that are controlled by the sound source built-in VDP 4160a are directly controlled. A light emission effect can be performed by a plurality of LEDs (decorative LEDs) provided in each.

  That is, among each decorative board of the door frame 5, a light emission effect by a plurality of LEDs (decorative LEDs) provided on each of the plurality of frame-side VDP control target decorative boards that are controlled by the built-in sound source VDP 4160a. Can be executed.

  Thus, based on the information read from the liquid crystal and sound control ROM 4160b, the electrical decoration information is included as an image as control information for a plurality of LEDs (decorative LEDs) mounted on various decorative boards of the door frame 5. The frame-side image object is created by the sound source built-in VDP 4160a, and the parallel signal including the created frame-side image object is output from the channel CH2 of the sound source built-in VDP 4160a. The parallel signal is obtained from the positive phase signal and the reverse phase signal. The transmitter IC 4160d converts the serial signal to be configured, and the converted serial signal is a differential one-pair cable configured by twisting a wiring for transmitting a normal phase signal and a wiring for transmitting a reverse phase signal. It is designed to be input to the receiver IC 194f via a certain twisted pair cable.That is, on the transmission path from the transmitter IC 4160d to the receiver IC 194f, a serial signal is transmitted via a twisted pair cable. The receiver IC 194f restores the input serial signal again to a parallel signal, and the frame-side signal separation control circuit 194g extracts the illumination information as control information from the frame-side image object based on the restored parallel signal. Based on the electrical decoration information as control information, among the decorative boards of the door frame 5, a plurality of frame-side VDP control target decorative boards provided on each of the frame-side VDP control target decorative boards that are directly controlled by the sound source built-in VDP 4160a are provided. LED (decorative LED) drive control is performed by the frame-side VDP control target decorative LED control circuit 194i in the frame-side VDP control target decorative LED control circuit 194i1 through the frame-side VDP control target 143 decorative LED control. Circuit 194i 143 can do this.

  A twisted pair cable is composed of a wire that transmits a positive-phase signal and a wire that transmits a reverse-phase signal, so that when noise enters the twisted-pair cable, the wire transmits a positive-phase signal. As a result, noise enters the wirings that transmit signals of opposite phases. Then, the noise that has entered the normal phase signal and the noise that has entered the reverse phase signal cancel each other, so that the receiver IC 194f can restore the parallel signal again with the noise removed. Therefore, accurate control can be realized for the controlled object.

[20. Another example]
It should be noted that the present invention is not limited to the above-described embodiment, and it goes without saying that the present invention can be implemented in various modes as long as it belongs to the technical scope of the present invention.

  For example, in the embodiment described above, the length of the wiring for sending drawing data from the liquid crystal and sound source built-in VDP 4160a of the peripheral control board 4140 shown in FIG. 19 is compared to the channel CH1 of the sound source built-in VDP 4160a. For the channel CH2 of the VDP 4160a with a built-in sound source that is extremely long, it is a kind of clockless transmission method between the transmitter and the receiver in the transmitter IC 4160d of the peripheral control board 4140 and the receiver IC 194f of the frame decoration drive amplifier board 194. Although differential communication called “V-by-One (registered trademark)” of THine Electronics Co., Ltd. was adopted, other ICs may be used as long as they are clockless transmission systems. In the embodiment described above, the transmitter IC 4160d, which is a dedicated IC, is used as the transmitter, and the receiver IC 194f, which is a dedicated IC, is used as the receiver. However, a serial that can be used by switching between the transceiver operation and the receiver operation. A transmission transceiver IC can also be used.

  Here, the serial transmission transceiver IC will be briefly described with reference to FIGS. 85 and 86. FIG. FIG. 85 is a schematic explanatory diagram of various terminals of the serial transmission transceiver IC, and FIG. 86 is a schematic diagram of a usage example of the serial transmission transceiver IC. The serial transmission transceiver IC 7000 is an IC capable of switching between the Tonsumitter operation and the receiver operation (transmitter / receiver). As shown in FIG. 85, the TX_XRX terminal as the switching terminal, the HS terminal, the VS terminal, and the PCLK as the input / output terminals. Terminal, R0 terminal, R1 terminal, R2 terminal, R3 terminal, R4 terminal, R5 terminal, R6 terminal, R7 terminal, G0 terminal, G1 terminal, G2 terminal, G3 terminal, G4 terminal, G5 terminal, G6 terminal, G7 terminal, B0 terminal, B1 terminal, B2 terminal, B3 terminal, B4 terminal, B5 terminal, B6 terminal, B7 terminal, DFXTX + terminal as differential output transmitter plus terminal, DFTX- terminal as differential output transmitter minus terminal, differential receiver plus terminal DFRX + terminal, differential receiver minus terminal DFRX- terminal includes ERR terminal to have the status output terminal, VDD pin as a power supply terminal, a GND terminal as a ground terminal.

  The TX_XRX terminal can be set for transceiver operation when a control voltage (eg, + 3.3V) is applied, and can be set for receiver operation when grounded to ground (GND).

  The HS terminal can input and output a horizontal synchronization signal, the VS terminal can input and output a vertical synchronization signal, and the PCLK terminal can input and output a clock signal.

  The R0 terminal, R1 terminal, R2 terminal, R3 terminal, R4 terminal, R5 terminal, R6 terminal, and R7 terminal can input and output red video signals, and the G0 terminal, G1 terminal, G2 terminal, G3 terminal, G4 The terminal, G5 terminal, G6 terminal, and G7 terminal can input and output a green video signal. The B0 terminal, B1, B2, B3, B4, B5, B6, and B7 terminals are Blue video signal can be input and output.

  The DFXTX + terminal and the DFTX− terminal are a horizontal synchronization signal input to the HS terminal, a vertical synchronization signal input to the VS terminal, a clock signal input to the PCLK terminal, an R0 terminal, an R1 terminal, an R2 terminal, Red video signal input to R3 terminal, R4 terminal, R5 terminal, R6 terminal and R7 terminal and input to G0 terminal, G1 terminal, G2 terminal, G3 terminal, G4 terminal, G5 terminal, G6 terminal and G7 terminal Serialized into a clockless transmission system based on the green video signal and the blue video signal input to the B0 terminal, B1 terminal, B2 terminal, B3 terminal, B4 terminal, B5 terminal, B6 terminal, and B7 terminal The output signal can be output by a differential method. Note that a predetermined termination resistor (for example, 50 ohms) is incorporated in the DFXTX + terminal and the DFTX− terminal of the differential transmitter of the serial transmission transceiver IC7000.

  The DFRX + terminal and the DFRX− terminal can receive a signal serialized in a clockless transmission system that is output in a differential system. The serial transmission transceiver IC 7000 has a built-in clock data recovery (CDR) function (parallel data restored to 8 bits from each of the red video signal, the green video signal, and the blue video signal as serial data). And clocks (horizontal synchronization signal, vertical synchronization signal, and clock signal). Note that a predetermined termination resistor (for example, 50 ohms) is incorporated in the DFRX + terminal and the DFRX− terminal of the differential receiver of the serial transmission transceiver IC7000.

  When the serial transmission transceiver IC 7000 is set to transceiver operation, the ERR terminal can output a transmission state and can output a normal transmission logic that conveys a stable time, while a transmission abnormal logic that conveys a transmission unstable time. (The logic obtained by inverting the normal transmission logic) can be output. On the other hand, when the serial transmission transceiver IC 7000 is set to the receiver operation, the ERR terminal can output the reception error check result, and can output the reception normal logic for transmitting the reception normality. It is possible to output a reception abnormality logic (a logic obtained by inverting the reception normal logic) that conveys a reception abnormality.

  A control voltage (for example, +3.3 V) is applied to the VDD terminal, and the GND terminal is grounded to the ground (GND).

  Next, a circuit will be described in which the serial transmission transceiver IC 7000 is set for transmitter operation and provided on the peripheral control board 4140, while the serial transmission transceiver IC 7000 is set for receiver operation and provided on the frame decoration drive amplifier board 194. As shown in FIG. 86, when the serial transmission transceiver IC 7000 is provided on the peripheral control board 4140, the TX_XRX terminal is applied to the control voltage in order to perform the transmitter operation. As described above, the image data output from the channel CH2 of the sound source built-in VDP 4160a includes three images: a red video signal (8-bit width), a green video signal (8-bit width), and a blue video signal (8-bit width). Signal, and three synchronization signals, a horizontal synchronization signal, a vertical synchronization signal, and a clock signal. The horizontal synchronization signal is input to the HS terminal, the vertical synchronization signal is input to the VS terminal, and the clock signal is A red video signal (8-bit width) is input to the PCLK terminal, and is input to each of the R0 terminal, R1 terminal, R2 terminal, R3 terminal, R4 terminal, R5 terminal, R6 terminal, and R7 terminal. Width) is input to the G0 terminal, G1 terminal, G2 terminal, G3 terminal, G4 terminal, G5 terminal, G6 terminal, and G7 terminal, respectively, and the blue video signal (8 Tsu-wide) is B0 terminal, B1 terminal, B2 terminals, B3 terminals, B4 terminal, B5 terminal, are input to B6 terminals, and B7 terminal.

  The DFTX + terminal and the DFXT− terminal are provided with capacitors (for coupling) TCX1 and TCX2, respectively. Clockless transmission to the frame peripheral relay terminal plate 868, the peripheral door relay terminal plate 882, and the frame decoration drive amplifier board 194 The signal serialized to the system is output (transmitted) using the differential system.

  The DFRX + terminal, the DFRX− terminal, and the ERR terminal are not electrically connected. The same control voltage as that of the TX_XRX terminal is applied to the VDD terminal, and the GND terminal is grounded to the ground (GND).

  On the other hand, when the serial transmission transceiver IC 7000 is provided on the frame decoration drive amplifier board 194, the TX_XRX terminal is grounded to the ground for receiver operation. The serial transmission transceiver IC 7000 provided on the frame decoration drive amplifier board 194 is connected to the serial signal from the DFTX + terminal and the DFTX- terminal of the serial transmission transceiver IC 7000 set as a transceiver operation provided on the peripheral control board 4140, respectively. For input (reception) to DFRX + terminal and DFRX- terminal via RCX1 and RCX2, and data (red video signal, green video signal, and blue video signal as serial data) by built-in clock data recovery (CDR) function To parallel data restored to 8 bits) and a clock (horizontal synchronizing signal, vertical synchronizing signal, and clock signal).

  The serial transmission transceiver IC 7000 provided on the frame decoration drive amplifier board 194 outputs a horizontal synchronization signal from the HS terminal to the frame side signal separation control circuit 194g, and a vertical synchronization signal from the VS terminal to the frame side signal separation control circuit 194g. The clock signal is output from the PCLK terminal to the frame side signal separation control circuit 194g, and the red video is output from the R0 terminal, R1 terminal, R2 terminal, R3 terminal, R4 terminal, R5 terminal, R6 terminal, and R7 terminal as a parallel signal. The signal is output to the frame side signal separation control circuit 194g, and the green video signal is controlled as a parallel signal from the G0 terminal, G1 terminal, G2 terminal, G3 terminal, G4 terminal, G5 terminal, G6 terminal, and G7 terminal. Output to the circuit 194g, G0 terminal, G1 terminal, G2 terminal, G3 terminal, G4 terminal, G5 terminal, G6 terminal, and And it outputs a blue video signal to the frame side signal isolation control circuit 194g as a parallel signal from the G7 terminal.

  The serial transmission transceiver IC 7000 provided on the frame decoration drive amplifier board 194 transmits the reception error check result to the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 from the ERR terminal to the peripheral door relay terminal board 882, The frame peripheral relay terminal board 868 and the peripheral control board 4140 output the reception normal logic or the reception abnormal logic. The peripheral control MPU 4150a monitors the reception normal logic or the reception abnormal logic output from the ERR terminal of the serial transmission transceiver IC 7000 provided on the frame decoration drive amplifier board 194, so that the peripheral control board 4140, the frame peripheral relay terminal board 868, It is possible to monitor whether or not a failure has occurred in the transmission path extending from the peripheral door relay terminal plate 882 and the frame decoration drive amplifier board 194. If a failure has occurred, a message “A failure has occurred in the transmission path to the door frame” is displayed in the display area of the game board effect display unit 1900 and a speaker provided on the door frame 5 Control is performed from 130 to play a voice saying “There is a problem in the transmission path to the door frame”.

  In the serial transmission transceiver IC 7000 provided on the frame decoration drive amplifier board 194, the DFTX + terminal and the DFRT− terminal are not electrically connected. A control voltage is applied to the VDD terminal, and the GND terminal is grounded to the ground (GND).

  In this way, the serial transmission transceiver IC 7000 capable of setting the transceiver operation and the receiver operation can be provided on the peripheral control board 4140 side and the frame decoration drive amplifier board 194, respectively. This eliminates the need to purchase separate electronic components for the transceiver and the receiver, so that twice the number of common ICs and separate electronic components can be purchased. be able to. Therefore, it can contribute to the suppression of the manufacturing cost of the pachinko gaming machine 1 and can also contribute to the suppression of the number of managed electronic components.

  In the above-described embodiment, the first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000g, the fourth light guide plate 5000h, and the fifth light guide plate included in the game board side effect display unit 1900. In the plurality of light guide plates composed of 5000i and the sixth light guide plate 5000k, a light emitting region and a non-light emitting region were formed by light from the upper end surface and the lower end surface of each light guide plate, For example, the upper light emitting region and the upper non-light emitting region are formed by light from the upper end surface of the light guide plate, while the side light emitting region and the side non-light emitting region are formed by light from the side end surface of the light guide plate Also good. In this case, for example, in the second light guide plate 5000f, the decorative plate 5000f1 on the light guide plate is disposed on the upper end surface of the second light guide plate 5000f, and the side end surface (for example, viewed from the front) of the second light guide plate 5000f. The light guide plate side decorative substrate 5000f2 ′ is disposed on the right end surface. The light guide plate decorative substrate 5000f1 is controlled by the LED driver IC 4810 in the first light guide plate control circuit 3420k1, and the light guide plate side decorative substrate 5000f2 ′ is controlled by the LED driver IC 4810 ′ in the first light guide plate control circuit 3420k1. The

  A number of reflective portions are formed on the back surface (back surface) of the second light guide plate 5000 so that the upper light emitting area emits light when the light source of the light guide plate upper decorative substrate 5000f1 is turned on. Thus, a large number of reflective portions are formed on the back surface (back surface) of the second light guide plate 5000 so that the side light emitting region emits light. As a result, the light of the upper light emitting area that is surface-emitted by the second light guide plate 5000f when the light source of the decorative substrate 5000f1 on the light guide plate is turned on is incident on the liquid crystal panel 5000e. According to the control mode of the liquid crystal panel 5000e, in the liquid crystal panel 5000e, an image can be easily visually recognized in the inner portion of the upper light emitting region. On the other hand, the light source on the light guide plate side decorative substrate 5000f2 ′ is turned on. The light of the side light emitting region that is surface-emitted by the light guide plate 5000f is incident, and when viewed from the front, the liquid crystal panel 5000e has an inner portion of the side light emitting region according to the control mode of the liquid crystal panel 5000e. An image can be easily visually recognized. In addition, the size and position of the non-light emitting region and the light emitting region can be changed by changing the angle of light incident on one light guide plate.

  Furthermore, in the above-described embodiment, the game board side effect display unit 1900 includes the first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000g, and the fourth as the backlight of the liquid crystal panel 5000e. The light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k are provided with a plurality of light guide plates. However, the liquid crystal panel 5000e and the plurality of light guide plates may be replaced with self-light emission. An organic EL display device that can be used may be used. When an organic EL display device is used, both an area displaying an image and an object existing behind the area other than the area displaying the image are visually recognized through the organic EL display apparatus. can do.

  Furthermore, in the above-described embodiment, the game board side effect display unit 1900 includes the first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000g, and the fourth as the backlight of the liquid crystal panel 5000e. Of sequentially switching a plurality of light guide plates composed of the first light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k from the first light guide plate 5000d to the sixth light guide plate 5000k. However, for example, the first light guide plate 5000d → the third light guide plate 5000g → the fifth light guide plate 5000i may be switched in order, or the first light guide plate 5000d → the second light guide plate Light plate 5000f → third light guide plate 5000g → second light guide plate 5000f → third light guide plate 5000g →... It may be or forward.

  In the above-described embodiment, the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board is arranged in time series in the screen generation schedule data according to the screen generation schedule data and the light emission mode generation schedule data. Each time the V blank signal described above is input, the screen data and the light emission data arranged in time series in the light emission mode generation schedule data, one from the top screen data and one from the top light emission data. Each of them is output to the liquid crystal and sound source built-in VDP 4160a of the peripheral control board 4140. As described above, the screen generation schedule data is configured by arranging the screen data defining the configuration of the screen in time series, and the screen generation schedule data for the game board side effect display unit 1900 (liquid crystal panel 5000e). And the order of screens to be drawn (displayed) is specified. As described above, the light emission mode generation schedule data is configured by arranging the light emission data defining the light emission mode in time series. There are schedule data and light emission mode generation schedule data for a plurality of LEDs provided on each decorative board of the door frame 5, and the order of the light emission modes is defined respectively. As described above, a plurality of these schedule data are stored in advance in the peripheral control ROM 4150b of the peripheral control unit 4150 in the peripheral control board. Therefore, the peripheral control MPU 450a is configured to store a plurality of screen generation and light emission mode generation schedule data in which the screen generation schedule data and the light emission mode generation schedule data are one schedule data in the peripheral control ROM 4150b in advance. Each time the above-mentioned V blank signal is input to the screen data and the light emission data arranged in time series in the screen generation and light emission mode generation schedule data in accordance with the screen generation and light emission mode generation schedule data, You may comprise so that it may output to VDP4160a with built-in sound source one by one from screen data and light emission data in order.

  In the above-described embodiment, the game board side effect display unit 1900 includes the first light guide plate 5000d, the second light guide plate 5000f, the third light guide plate 5000g, and the fourth as the backlight of the liquid crystal panel 5000e. The non-light-emitting areas of the plurality of light guide plates composed of the light guide plate 5000h, the fifth light guide plate 5000i, and the sixth light guide plate 5000k are formed in a circular shape or a polygonal shape. The relationship with the shape of the non-light emitting area is appropriately determined according to the world view of the effect that the developer of the pachinko gaming machine 1 wants to realize.

  Further, in the above-described embodiment, the drawing data output from the channel CH1 of the liquid crystal and sound source built-in VDP 4160a of the sound control unit 4160 in the peripheral control board 4140 are the clock signal differential 1 pair cable and the TA signal differential 1 pair. It is transmitted to the liquid crystal output board 3420 via the cable, the differential pair cable for TB signal, the differential pair cable for TC signal, and the differential pair cable for TD signal, and the RGB conversion circuit 3420f of the liquid crystal output board 3420. In FIG. 2, the signals are converted into parallel signals based on signals transmitted by the LVDS method (that is, clock signals, TA signals, TB signals, TC signals, and TD signals). Therefore, between the peripheral control board 4140 and the liquid crystal output board 3420, a clock signal differential 1 pair cable, a TA signal differential 1 pair cable, a TB signal differential 1 pair cable, and a TC signal differential By connecting multiple pairs of cables, one pair cable and differential pair cable for TD signal, the number of cables increases, which may make it difficult to route the cables. In some cases, a large dedicated space is provided behind the game board 4 for routing. Therefore, between the peripheral control board 4140 and the liquid crystal output board 3420, three video signals such as a red video signal, a green video signal, and a blue video signal, and three signals such as a horizontal synchronization signal, a vertical synchronization signal, and a clock signal are provided. Only the differential 1-pair cable that serializes the synchronization signal to the differential serial signal (serial data) called the clockless transmission system described above, with one wire being in the positive phase and the other wire in the opposite phase. In such a case, these various signals may be transmitted.

  In this case, the RGB conversion circuit 3420f of the liquid crystal output board 3420 shown in FIG. 20 is provided on the peripheral control board 4140, and drawing data transmitted by the LVDS method from the channel CH1 of the sound source built-in VDP 4160a is received in the RGB conversion circuit. , A red video signal, a green video signal, and a blue video signal, and a parallel signal composed of three synchronization signals such as a horizontal synchronization signal, a vertical synchronization signal, and a clock signal. A peripheral control board 4140 is provided with a transmitter for serializing the converted parallel signal into a differential serial signal (serial data) called a clockless transmission system. Various serialized signals are converted into parallel signals (that is, three video signals such as a red video signal, a green video signal, and a blue video signal, and three synchronization signals such as a horizontal synchronization signal, a vertical synchronization signal, and a clock signal) )) Is provided on the liquid crystal output substrate 3420. The parallel signal restored by the receiver is input to the game board side signal separation control circuit 3420g. In this way, between the peripheral control board 4140 and the liquid crystal output board 3420, that is, between the transmitter and the receiver, only the differential one-pair cable, and the three video signals of the red video signal, the green video signal, and the blue video signal , Horizontal synchronization signal, vertical synchronization signal, and clock signal can be transmitted, so that the number of cables can be reduced, so that the cable can be routed very easily and the cables can be routed. Therefore, it is not necessary to provide a large dedicated space on the back side of the game board 4.

  The RGB conversion circuit 3420f of the liquid crystal output board 3420 is provided on the peripheral control board 4140, and the drawing data transmitted by the LVDS method from the channel CH1 of the sound source built-in VDP 4160a is converted into a red video signal, green color in the RGB conversion circuit. A differential method called a clockless transmission method is converted into a parallel signal composed of three video signals, a video signal and a blue video signal, and three synchronization signals, a horizontal synchronization signal, a vertical synchronization signal, and a clock signal. When the peripheral control board 4140 is provided with a transmitter for serializing serial signals (serial data), drawing data from the channels CH1 and CH2 of the sound source built-in VDP 4160a is sent to a board outside the peripheral control board 4140 via the transmitter. Transmitted Therefore, the drawing data from the channel CH1 is transmitted to the liquid crystal output board 3420 and the drawing data from the channel CH2 is transmitted to the frame decoration drive amplifier board 194 via the frame peripheral relay terminal board 868 and the peripheral door relay terminal board 882. The drawing data from the channel CH1 may be transmitted to the frame decoration drive amplifier board 194 via the frame peripheral relay terminal plate 868 and the peripheral door relay terminal plate 882, and from the channel CH2. The drawing data may be transmitted to the liquid crystal output substrate 3420.

  Furthermore, in the embodiment described above, the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 sends the game board side motor drive data from the motor drive board serial I / O port via the peripheral control output circuit. Then, by transmitting to the motor drive board 4180, control is performed to output a drive signal to an electric drive source such as a motor or solenoid that operates various movable bodies provided on the game board 4. In other words, the peripheral control MPU 4150a directly outputs the game board side motor drive data, thereby outputting a drive signal to an electric drive source such as a motor or a solenoid for operating various movable bodies provided in the game board 4 Had gone. Therefore, the control target of an electrical drive source on the game board 4 side may be separated from the control by the peripheral control MPU 4150a and controlled by the sound source VDP 4160a.

  For example, as described above, the eleventh serial controller 3420gd11 in the game board side signal separation control circuit 3420g shown in FIG. 35 uses the electrical information as serial data SDAT11 based on the clock signal SCLK11, 25 decoration LED control circuit 3420i25, game board side VDP control object 26th decoration LED control circuit 3420i26, game board side VDP control object 27th decoration LED control circuit 3420i27, and game board side VDP control object The 25th decoration LED control circuit 3420i25, the game board side VDP control object 26th decoration LED control circuit 3420i26, and the game board side VDP control object 27th decoration LED control circuit 3420i27 are connected to one serial connection (one Serial connection) Has been a circuit configured to be.

  Therefore, here, the 25th decoration LED control circuit 3420i25 for the game board side VDP control object, the 26th decoration LED control circuit 3420i26 for the game board side VDP control object, and the 27th decoration LED control for the game board side VDP control object A circuit 3420i27 and an output control circuit 3420it1 capable of setting its own ID are provided on the liquid crystal output board 3420, and are electrically connected as one serial connection (one serial system). The ID of the output control circuit 3420it1 is different from the ID set for each of the 25th decoration LED control circuit 3420i25 to the game board side VDP control target 27th decoration LED control circuit 3420i27. Is set.

  Then, the eleventh serial controller 3420gd11 in the game board side signal separation control circuit 3420g uses the decoration information as serial data SDAT11, based on the clock signal SCLK11, the 25th decoration LED control circuit 3420i25 for the game board side VDP control, The board side VDP control target 26th decoration LED control circuit 3420i26, the game board side VDP control target 27th decoration LED control circuit 3420i27, and the output control circuit 3420it1 are output. As described above, the illumination information is information for designating the light emission mode, and is composed of the illumination LED designation information and the gradation information, and the electric drive corresponding to the output control circuit 3420it1. The power source drive is added. The electrical drive source drive is information for designating the drive mode of the electrical drive source on the game board 4 side, and is composed of output control designation information and output information. The output control designation information is information for designating the output control circuit 3420it1, and is set with the ID described above. The output information is information for driving and controlling the electrical drive source on the game board 4 side.

  The output control circuit 3420it1 will be briefly described. The output control circuit 3420it1 includes an address setting unit, a logic processing unit, a shift register, and an output port. The address setting unit can set the ID according to the magnitude of the voltage applied to the plurality of address setting terminals. The logic processing unit receives the serial data SDAT11 from the eleventh serial controller 3420gd11 in the game board side signal separation control circuit 3420g based on the clock signal SCLK11, and based on the address which is its own ID set by the address setting unit, When the output control designation information in the serial data SDAT11 includes its own ID, it is determined that the serial data SDAT11 is for itself and the output information in the serial data SDAT11 is taken in by the shift register and restored to parallel data. While control is performed to write to the output port, if the output control designation information in the serial data SDAT11 does not include its own ID, it is determined that the serial data SDAT11 is not for itself. Without taking the output information in Rudeta SDAT11 a shift register (or not written to the output port to restore the parallel data be incorporated), control is performed to maintain the last written contents (contents of the current).

  The output port is capable of outputting a parallel signal according to the parallel data written by the logic processing unit. A motor drive board 4180, which is a separate board from the liquid crystal output board 3420, is shown in a drive source drive circuit 4180a that can output drive signals to a motor (electric drive source) that operates various movable bodies provided in the game board 4. And a solenoid drive circuit (not shown) in the drive source drive circuit 4180a that can output a drive signal to a solenoid (electric drive source) that operates various movable bodies provided in the game board 4. In addition, a parallel signal from the output port of the output control circuit 3420it1 provided on the liquid crystal output board 3420 is used as a control signal via an electric wiring (not shown), a motor drive circuit of a drive source drive circuit 4180a provided on the motor drive board 4180, and a solenoid It is input to the drive circuit. The motor drive circuit is a motor that operates various movable bodies provided in the game board 4 according to the logic of the parallel signal (control signal) from the output port (for example, the button unit 3400a imitating the initiation button shown in FIG. The drive signal to the motor (electric drive source) that operates the model 3500 simulating dynamite) can be output, and the solenoid drive circuit can play games according to the logic of the parallel signal (control signal) from the output port. Drive signals to solenoids that actuate various movable bodies provided on the panel 4 (for example, solenoids (electric drive sources) that actuate the button portion 3400a imitating the detonation button and the model 3500 imitating dynamite shown in FIG. 8). Can be output. In this way, the output control circuit 3420it1, the motor drive circuit of the drive source drive circuit 4180a, and the solenoid drive circuit constitute a game board side drive control circuit. This game board side drive control circuit eliminates the need for providing the motor control board side transmission data storage area 4150cag shown in FIG. 18 in which the game board side motor drive data is set in the peripheral control RAM 4150c, and the above-described backup management object. In addition, the processing load of the peripheral control MPU 4150a can be reduced.

  A motor drive circuit (not shown) in a drive source drive circuit 4180a capable of outputting a drive signal to a motor (electric drive source) that operates various movable bodies provided on the game board 4 and various movable bodies provided on the game board 4 The solenoid drive circuit (not shown) in the drive source drive circuit 4180a that can output a drive signal to the solenoid (electric drive source) that operates the motor is provided with an enable signal input circuit, respectively, from the peripheral control MPU 4150a. The transmission path is formed so that the enable signal is input. Specifically, a motor enable signal is sent from a parallel I / O port of the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 via a peripheral control output circuit (not shown) of a motor drive circuit (not shown) of the motor drive board 4180. The signal is input to the enable signal input circuit. In addition, the solenoid enable signal is input from the parallel I / O port of the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 via the peripheral control output circuit (not shown) to the solenoid drive circuit (not shown) of the motor drive board 4180. It is input to the circuit.

  A motor drive circuit (not shown) operates various movable bodies provided in the game board 4 in accordance with the logic of the parallel signal (control signal) from the output port described above based on the logic of the motor enable signal from the peripheral control MPU 4150a. The output of the drive signal to the motor to be operated (for example, the motor (electric drive source) that operates the button 3400a imitating the initiation button shown in FIG. 8 or the model 3500 imitating the dynamite) is permitted or not permitted ( Prohibited). The motor enable signal includes a first motor enable signal for a motor (electric drive source) that operates a button portion 3400a that imitates an initiation button, and a motor (electric drive source) that operates a model 3500 that imitates dynamite. And a second motor enable signal. Here, the logic of the motor enable signal from the peripheral control MPU 4150a will be briefly described. When the logic of the motor enable signal from the peripheral control MPU 4150a is set to the operation permission logic (valid logic), the electric drive source. The peripheral control MPU 4150a permits the output of the drive signal to the electrical drive source according to the logic of the parallel signal (control signal) from the output port described above by the motor drive circuit (not shown) On the other hand, when the logic of the motor enable signal from the peripheral control MPU 4150a is set to the operation non-permission logic (invalid logic (a logic obtained by inverting the operation permission logic (valid logic))), As a drive prohibition state that prohibits driving, the peripheral control MPU 4150a is a motor not shown Dynamic circuit is in a state to prohibit the output of the drive signal to the electric driving source in accordance with the logic of the parallel signal (control signal) from the output port mentioned above.

  A solenoid drive circuit (not shown) operates various movable bodies provided in the game board 4 according to the logic of the parallel signal (control signal) from the output port described above based on the logic of the solenoid enable signal from the peripheral control MPU 4150a. The output of the drive signal to the solenoid to be activated (for example, the solenoid (electric drive source) that operates the button 3400a imitating the initiation button and the model 3500 imitating the dynamite shown in FIG. 8) is permitted or not permitted ( Prohibited). The solenoid enable signal includes a first solenoid enable signal for a solenoid (electrical drive source) that activates a button portion 3400a that imitates an initiation button, and a solenoid (electrical drive source) that activates a model 3500 that imitates dynamite. For the second solenoid. Here, the logic of the solenoid enable signal from the peripheral control MPU 4150a will be briefly described. When the logic of the solenoid enable signal from the peripheral control MPU 4150a is set to the operation permission logic (valid logic), the electric drive source. The peripheral control MPU 4150a permits the output of the drive signal to the electrical drive source according to the logic of the parallel signal (control signal) from the output port described above by the solenoid drive circuit (not shown) On the other hand, when the logic of the solenoid enable signal from the peripheral control MPU 4150a is set to the operation non-permission logic (invalid logic (the logic obtained by inverting the operation permission logic (valid logic))), As a drive prohibition state in which drive is prohibited, the peripheral control MPU 4150a It shows no solenoid drive circuit is a state to prohibit the output of the drive signal to the logical electric driving source in response to the parallel signal (control signal) from the output port mentioned above.

  The peripheral control MPU 4150a sets the logic of the motor enable signal and the solenoid enable signal, thereby allowing the output of the drive signal of the electric drive source to operate the motor and the solenoid, or driving the electric drive source. The output of the signal is prohibited and the operation of the motor and solenoid can be stopped. Thereby, for example, when giving a behavior to operate the button part 3400a imitating a detonation button or the model 3500 imitating a dynamite, the peripheral control MPU 4150a makes a winning determination by a unique random number and starts the fluctuation of the special symbol described above. The special symbol 1 from the time of change to the stop of the change is performed at predetermined intervals (for example, 3 seconds) or at random within the changing period, and when the determination result is won, the logic of the motor enable signal and solenoid enable signal is activated. While the permission logic (valid logic) is set, the logic of the motor enable signal and solenoid enable signal is set to the operation disapproval logic (invalid logic) when the determination result is lost. As a result, the button part 3400a imitating the detonation button and the model 3500 imitating the dynamite are activated, stopped, activated again, and so on. The button part 3400a imitating the detonation button and the dynamite are imitated. An effect of intermittently operating the model 3500 can be created in real time. As described above, the peripheral control MPU 4150a sets the logic of the motor enable signal and the solenoid enable signal independently, thereby enabling the real time variation of the effect by the button unit 3400a imitating the initiation button and the model 3500 imitating the dynamite. You can increase it. Therefore, a decrease in interest can be suppressed.

  It should be noted that, for example, the game board side VDP control target 22nd decoration LED control circuit 3420i22 to the game board side VDP control target 26th decoration LED control circuit 3420i26 simulates a button portion 3400a imitating an initiation button or a model 3500 imitating dynamite. When driving (emitting) a plurality of LEDs (hereinafter referred to as “LEDs for decoration of the button portion 3400a and the model 3500”) as decoration LEDs provided on each of the decoration substrates provided in the game board, An enable signal input circuit is provided in each of the 22nd decoration LED control circuit 3420i22 to the VDP control object 3420i22 for the VDP control object to the 26th decoration LED control circuit 3420i26 for the game board side VDP control object, and the game board side VDP control object number from the peripheral control MPU 4150a is provided. 22 decoration LED control circuit enable signal to game board side VDP control Elephant enable signal 26 decorative LED control circuit may be formed transmission route as input, respectively. Specifically, the 22nd decoration LED control circuit enable for the VDP control object on the game board side from the parallel I / O port of the peripheral control MPU 4150a of the peripheral control unit 4150 on the peripheral control board 4140 via a peripheral control output circuit (not shown). Signal to game board side VDP control target 26th decoration LED control circuit enable signal corresponding to liquid crystal output circuit 3420 game board side VDP control target 22nd decoration LED control circuit 3420i22 to game board side VDP control target number 26 are input to the enable signal input circuits in the decorative LED control circuit 3420i26.

  The game board side VDP control target 22nd decoration LED control circuit enable signal to the game board side VDP control target 26th decoration LED control circuit enable signal are light emission permission logic (valid logic) and light emission non-permission logic ( Any one of the invalid logic (a logic obtained by inverting the light emission permission logic (valid logic)), and the light emission permission logic (valid logic) is set to the motor enable signal or solenoid enable signal described above. This is the same logic as the operation enable logic (valid logic), and the light emission non-permission logic (invalid logic) is the same as the operation disable logic (invalid logic) set in the motor enable signal and solenoid enable signal described above. It is logic. When the light emission permission logic (valid logic) is set in the logic of the game board side VDP control target 22nd decoration LED control circuit enable signal to the game board side VDP control target 26th decoration LED control circuit enable signal As a drive permission state (light emission permission state) for permitting the drive (light emission) of the decoration LED of the button unit 3400a and the model 3500, the peripheral control MPU 4150a is the 22nd decoration LED control circuit 3420i22 to the game board side VDP control target. While the gaming board side VDP control target 26th decoration LED control circuit 3420i26 allows the adjustment of the luminance (gradation) of the decoration LED of the button unit 3400a and the model 3500 based on the above-described electrical decoration information, Board-side VDP control target 22nd decoration LED control circuit enable signal to game board side VDP control target 26th decoration When the light emission non-permission logic (invalidity logic (a logic obtained by inverting the light emission permission logic (valid logic))) is set in the logic of the LED control circuit enable signal, the decoration LED of the button unit 3400a or the model 3500 is driven (light emission). ) Is prohibited, the peripheral control MPU 4150a is connected to the game board side VDP control target 22nd decoration LED control circuit 3420i22 to the game board side VDP control target 26th decoration LED control circuit 3420i26. Are in a state where the adjustment of the brightness (gradation) of the decorative LED of the decorative LED of the button 3400a or the model 3500 based on the above-described electrical decoration information is prohibited. As a result, the button part 3400a imitating the detonation button and the model 3500 imitating the dynamite are activated, stopped, activated again, and so on. The button part 3400a imitating the detonation button and the dynamite are imitated. The button 3400a and the decorative LED of the model 3500 can be driven (emitted) when the model 3500 is operated intermittently. Therefore, the button 3400a simulating the explosion button and the operation of the model 3500 simulating dynamite It is possible to provide a player with a sense of unity by interlocking (synchronizing) the light emission modes of the decorative LED of the button portion 3400a and the model 3500.

  The process for performing the above-described winning determination (hereinafter referred to as “game board side movable effect execution winning determination process”) is performed by the effect control program, for example, peripheral control of the peripheral control unit power-on process shown in FIG. In the received command analysis process of step S1022 in the part steady process, various commands stored in the received command storage area 4150cac are analyzed, and the analyzed command activates the button part 3400a imitating a detonation button and the model 3500 imitating a dynamite. When giving the behavior to be performed, the winning determination is performed at predetermined intervals (for example, 3 seconds) or randomly. Then, the motor enable signal, solenoid enable signal, game board side VDP control target 22nd decoration LED control circuit enable signal to game board side VDP control target based on the determination result by the game board side movable effect execution winning determination process The logic setting and output of the 26th decoration LED control circuit enable signal is performed by newly providing enable signal logic setting and output processing in the above-described peripheral control unit steady-state processing (this enable signal logic setting and output processing is The peripheral control unit 1 ms timer interrupt process shown in FIG. 70 may be provided as a process). When the special symbol 1 fluctuation period ends (when a special figure 1 tuning effect end command and a special figure 2 tuning effect end command are received), the logic of the motor enable signal and the solenoid enable signal are set to initial values (that is, Operation permission logic, light emission permission logic (validation logic)), motor enable signal, solenoid enable signal, game board side VDP control target No. 22 decoration LED control circuit enable signal to game board side VDP control target The 26th decoration LED control circuit enable signal is output in the enable signal logic setting and output process. Note that the determination result by the game board side movable effect execution winning determination process may be configured to be maintained and updated by providing a dedicated area, for example, in Bank0 (1fr) in the backup management target work area 4150ca as backup target information. Good. The logics of the motor enable signal, solenoid enable signal, game board side VDP control target 22nd decoration LED control circuit enable signal to game board side VDP control target 26th decoration LED control circuit enable signal are: The operation permission logic and the light emission permission logic (valid logic) are set as initial values when the power is turned on. When power is restored due to a power outage or momentary power failure during hall operation, the motor enable signal, solenoid enable signal, game board side VDP control target 22nd decoration LED control circuit enable signal The logic of the enable signal for the 26th decorative LED control circuit for the game board side VDP control target may be set to an initial value (that is, operation permission logic, light emission permission logic (valid logic)). Even if the operation permission logic, the light emission permission logic (valid logic), the operation non-permission logic, or the light emission non-permission logic (invalid logic) is set based on the dedicated area provided in the backup management target work area 4150ca. Good. Also, the enable signal for the motor, the enable signal for the solenoid, the enable signal for the 22nd decoration LED control circuit for the game board side VDP control object to the enable signal for the 26th decoration LED control circuit for the game board side VDP control object, respectively, Although configured as individual signals, they may be configured to be used as one common enable signal. In this way, it is possible to contribute to reducing the processing load of the peripheral control MPU 4150a by reducing the number of signals for setting logic, and it is also possible to contribute to cost reduction by reducing the number of wirings.

  In the above-described embodiment, the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 receives the door-side motor drive data from the frame decoration drive amplifier board motor serial I / O port, the peripheral control output circuit, the frame By transmitting to the frame decoration drive amplifier board 194 via the peripheral relay terminal plate 868 and the peripheral door relay terminal plate 882, the dial operation unit 401 of the operation unit 400 in the door frame 5 is rotated or a click feeling is given. Control is performed to output a drive signal to the dial drive motor 414 (electrical drive source) that can give various behaviors such as vibration or vibration. In other words, the peripheral control MPU 4150a performs control to output a drive signal to the dial drive motor 414 (electric drive source) by directly transmitting the door side motor drive data. Therefore, the control target of the electric drive source on the door frame 5 side may be separated from the control by the peripheral control MPU 4150a and controlled by the sound source VDP 4160a.

  For example, the eleventh serial controller 194gd11 in the frame-side signal separation control circuit 194g shown in FIG. 40 uses the frame-side VDP control target based on the clock signal SCLK11 ′ with the illumination information as the serial data SDAT11 ′ as described above. 131 of the decorative LED control circuit 194i131 to the frame-side VDP control target 143 of the decorative LED control circuit 194i143, and the frame-side VDP control target of the decorative LED control circuit 194i131 of the frame-side VDP control target 143 The decoration LED control circuit 194i143 has a circuit configuration that is electrically connected as one serial connection (one serial system).

  Therefore, here, the frame side VDP control target 131st decoration LED control circuit 194i131, the frame side VDP control target 131st decoration LED control circuit 194i131,..., The frame side VDP control target 143rd decoration LED A control circuit 194i143 and an output control circuit 194it1 capable of setting its own ID are provided on the frame decoration drive amplifier board 194 to be electrically connected as one serial connection (one serial system). . The ID of the output control circuit 194it1 is different from the ID set for each of the frame-side VDP control target 131st decoration LED control circuit 194i131 to the frame-side VDP control target 143 decoration LED control circuit 194i143. The

  Then, the eleventh serial controller 194gd11 in the frame-side signal separation control circuit 194g uses the decorating information as serial data SDAT11 ′, and based on the clock signal SCLK11 ′, the frame-side VDP control target 131st decoration LED control circuit 194i131, To the side VDP control target 131st decoration LED control circuit 194i131,..., The frame side VDP control target 143 decoration LED control circuit 194i143, and the output control circuit 194it1. As described above, the illumination information is information for designating the light emission mode, and is composed of the illumination LED designation information and the gradation information, and the electric drive corresponding to the output control circuit 194it1. Source driving information is added. The electrical drive source drive is information for designating the drive mode of the electrical drive source on the door frame 5 side, and is composed of output control designation information and output information. The output control designation information is information for designating the output control circuit 194it1, and the ID described above is set therein. The output information is information for driving and controlling the electrical drive source on the door frame 5 side.

  The output control circuit 194it1 will be briefly described. The output control circuit 194it1 includes an address setting unit, a logic processing unit, a shift register, and an output port. The address setting unit can set the ID according to the magnitude of the voltage applied to the plurality of address setting terminals. The logic processing unit receives the serial data SDAT11 ′ from the eleventh serial controller 194gd11 in the frame side signal separation control circuit 194g based on the clock signal SCLK11 ′, and based on the address which is its own ID set by the address setting unit. When the output control designation information in the serial data SDAT11 ′ includes its own ID, it is determined that the serial data SDAT11 ′ is for itself, the output information in the serial data SDAT11 ′ is taken in by the shift register, and the parallel data If the ID is not included in the output control designation information in the serial data SDAT11 ′, it is determined that the serial data SDAT11 ′ is not for itself. Not captured in the shift register output information in the serial data SDAT11 '(or not written to the output port to restore the parallel data be incorporated), control is performed to maintain the last written contents (contents of the current).

  The output port is capable of outputting a parallel signal according to the parallel data written by the logic processing unit. The frame decoration drive amplifier board 194 includes a motor drive circuit (not shown) that can output a drive signal to the dial drive motor 414 (electric drive source), and a parallel signal from the output port is used as a control signal to drive the motor. It is input to the circuit. The motor drive circuit can output a drive signal to the dial drive motor 414 (electric drive source) according to the logic of the parallel signal (control signal) from the output port. Thus, the door-side drive control circuit is configured by the output control circuit 194it1 and the motor drive circuit (not shown) that can output a drive signal to the dial drive motor 414 (electric drive source). This door side drive control circuit eliminates the need for providing the frame decoration drive amplifier board side motor transmission data storage area 4150caf shown in FIG. 18 in which the door side motor drive data is set in the peripheral control RAM 4150c, and the backup management described above. It can contribute to the reduction of the processing load of the peripheral control MPU 4150a.

  According to the pachinko gaming machine 1 of this embodiment that adopts this aspect, it is possible to produce effects based on the progress of the game, and the dial drive motor 414 provided in the operation unit 400 of the door frame 5 of FIG. As the information storage means, the liquid crystal and sound control ROM 4160b of the liquid crystal and sound control unit 4160 in the peripheral control board 4140 of FIG. 17, and the sound source built-in VDP 4160a of the liquid crystal and sound control part 4160 of the peripheral control board 4140 of FIG. The channel CH2 of the sound source built-in VDP 4160a in FIG. 19 as a parallel signal output unit, the twisted pair cable as a stranded wire, the transmitter IC 4160d of the peripheral control board 4140 in FIG. 19 as signal conversion means, and the frame decoration drive amplifier board 194 in FIG. Receiver IC19 f, the frame side signal separation control circuit 194g of the frame decoration drive amplifier board 194 in FIG. 19 as the take-out means, and the frame in the frame side VDP control target decoration LED control circuit 194i of the frame decoration drive amplifier board 194 in FIG. 42 as the drive control means. Side VDP control target first decoration LED control circuit 194i1 to frame side VDP control target 143 decoration LED control circuit 194i143.

  The liquid crystal and sound control ROM 4160b can store a plurality of types of information related to effects. Specifically, the liquid crystal and sound control ROM 4160b includes the game board side character data to be drawn in the display area of the game board side effect display unit 1900, and the above-described predetermined screen (in this embodiment, red (R)). : 50%, Green (G): 50%, Blue (B): Gray screen with 50%) and the decorative board of the game board 4 are directly controlled by the VDP 4160a with built-in sound source Game board side light emission mode setting image data for setting a light emission mode of a plurality of LEDs (decorative LEDs) provided on each of the plurality of game board side VDP control target decorative boards to be controlled, and a door frame 5, a plurality of LEDs (decoration L) provided on each of the plurality of frame side VDP control target decorative boards that are controlled by the sound source built-in VDP 4160a. A door frame-side light emission mode setting image data for setting a light emitting mode of the D), music, sound effects, and various sound data, such as alarm sound, and notification sounds, but are stored in advance.

  The sound source built-in VDP 4160a is based on information read from the liquid crystal and sound control ROM 4160b, and a plurality of LEDs (decorative LEDs) mounted on various decorative boards of the door frame 5 and a dial drive provided in the operation unit 400 of the door frame 5. The frame-side image object can be created so that the illumination information and the output information are included as an image as control information for the motor 414.

  Specifically, first, as described above, the peripheral control MPU 4150a performs time series on the screen generation schedule data according to the screen generation schedule data and the light emission mode generation schedule data set in the schedule data storage area 4150cae. Each time the V blank signal is input, the screen data arranged in the above and the light emission data arranged in time series in the light emission mode generation schedule data, one each from the top screen data, from the top light emission data. One by one is output to the sound source built-in VDP 4160a.

  The screen generation schedule data is configured by arranging screen data defining the configuration of the screen in time series, and includes screen generation schedule data for the game board side effect display unit 1900 (liquid crystal panel 5000e), and the upper plate side. Screen generation schedule data for the liquid crystal display device 470, and the order of screens to be drawn (displayed) is defined. The light emission mode generation schedule data is composed of light emission data defining the light emission mode arranged in time series, and the light emission mode generation schedule data for the plurality of LEDs provided on each decorative board of the game board 4 and the door There are schedule data for light emission mode generation for a plurality of LEDs provided on each decorative board of the frame 5, and the order of the light emission modes is defined respectively.

  The sound source built-in VDP 4160a defines a predetermined screen (in this embodiment, a gray screen having red (R): 50%, green (G): 50%, blue (B): 50%). Data and light emission of a plurality of LEDs (decorative LEDs) provided on each of a plurality of frame-side VDP control target decorative boards that are controlled by the built-in sound source VDP 4160a among the decorative boards of the door frame 5 When the light emission data defining the mode is input from the peripheral control MPU 4150a, a predetermined screen (the main screen) is selected from the liquid crystal and sound control ROM 4160b based on the input screen data according to a predetermined door frame side generation rule. In the embodiment, dummy data for drawing red (R): 50%, green (G): 50%, blue (B): 50%) is extracted and sputtered. The door frame side drawing data is generated in the door frame side drawing data region VRGN2a of the door frame side display region VRGN2 provided on the built-in VRAM, and the liquid crystal and the display data are generated based on the input light emission data. Among each decorative board of the door frame 5 from the sound control ROM 4160b, a plurality of LEDs (decorative LEDs) provided on each of the plurality of frame side VDP control target decorative boards that are controlled by the built-in sound source VDP 4160a. The door frame side light emission mode setting image data for setting the light emission mode is extracted, and the illumination information is generated as drawing data in the door frame side associated information region VRGN2b of the door frame side display region VRGN2 provided on the built-in VRAM. To do. The illumination information is information for designating the light emission mode, and is composed of illumination LED designation information and gradation information, to which electric drive source drive information corresponding to the output control circuit 194it1 is added. It is supposed to be configured. The electrical drive source drive is information for designating the drive mode of the electrical drive source on the door frame 5 side, and is composed of output control designation information and output information. The output control designation information is information for designating the output control circuit 194it1, and the ID described above is set therein. The output information is information for driving and controlling a dial drive motor 414 provided in the operation unit 400 of the door frame 5 that is an electrical drive source on the door frame 5 side.

  The channel CH2 of the sound source built-in VDP 4160a in FIG. 19 is capable of outputting a parallel signal including a frame-side image object created by the sound source built-in VDP 4160a.

  Specifically, the channel CH2 of the sound source built-in VDP 4160a uses a parallel interface. The drawing data output from the channel CH2 is composed of three video signals, a red video signal, a green video signal, and a blue video signal, and three synchronization signals, a horizontal synchronization signal, a vertical synchronization signal, and a clock signal. ing. The sound source built-in VDP 4160a has door frame side drawing data generated in the door frame side drawing data area VRGN2a of the door frame side display area VRGN2 provided on the built-in VRAM as a frame side image object created by itself, and built-in The red video signal, the green video signal, and the blue video signal with drawing data including the illumination information generated in the door frame side accompanying information area VRGN2b of the door frame side display area VRGN2 provided on the VRAM as parallel signals Are output, and three synchronizing signals such as a horizontal synchronizing signal, a vertical synchronizing signal, and a clock signal.

  The transmitter IC 4160d of the peripheral control board 4140 converts the parallel signal output from the channel CH2 of the sound source built-in VDP 4160a into a clockless transmission system signal as a serial signal composed of a normal phase signal and a reverse phase signal. It can be output.

  Specifically, the transmitter IC 4160d is a parallel signal output from the channel CH2 of the sound source built-in VDP 4160a, which is a red video signal, a green video signal, and a blue video signal, a horizontal synchronization signal, and a vertical synchronization signal. , And clock signal are serialized into a differential serial signal (serial data) called “V-by-One (registered trademark)” of Zain Electronics Co., Ltd. which is a kind of clockless transmission system. (In other words, a parallel signal composed of three video signals, that is, a red video signal, a green video signal, and a blue video signal, and three synchronization signals such as a horizontal synchronization signal, a vertical synchronization signal, and a clock signal is multiplexed. Differential serial signal Serialized to serial data), and these various signals are transmitted from the peripheral control board 4140 to the frame peripheral relay terminal board 868 only with a differential one-pair cable in which one wiring is in the normal phase and the other wiring is in the reverse phase. , Output (transmit) to the peripheral door relay terminal plate 882 and the frame decoration drive amplifier 194.

  A twisted pair cable, which is a differential one-pair cable, is configured by twisting together a wiring that transmits a positive-phase signal and a wiring that transmits a negative-phase signal. Specifically, one wiring of the twisted pair cable is configured as a wiring for transmitting a normal phase signal, and the other wiring of the twisted pair cable is configured as a wiring for transmitting a reverse phase signal.

  The receiver IC 194f of the frame decoration drive amplifier board 194 can restore a serial signal composed of a normal phase signal and a reverse phase signal input via a twisted pair cable to a parallel signal and output the parallel signal. .

  Specifically, when receiving the serial signal (serial data) from the peripheral control board 4140 via the twisted pair cable, the receiver IC 194f outputs various serialized signals from the parallel signal (that is, the channel CH2 of the sound source built-in VDP 4160a). The drawing data is restored to three video signals, namely, a red video signal, a green video signal, and a blue video signal, and three synchronization signals such as a horizontal synchronization signal, a vertical synchronization signal, and a clock signal. The signal is output to the side signal separation control circuit 194g.

  The frame-side signal separation control circuit 194g extracts and outputs electrical information and output information as control information from the frame-side image object created by the sound source built-in VDP 4160a based on the restored parallel signal output by the receiver IC 194f. It is something that can be done.

  Specifically, the frame-side signal separation control circuit 194g determines the above-described predetermined screen (in this embodiment, red (R): 50%, green (G): 50 from the parallel signal restored by the receiver IC 194f. %, Blue (B): gray screen having 50%), three video signals of a red video signal, a green video signal, and a blue video signal, a horizontal synchronization signal, and a vertical synchronization signal. , And a clock signal, and among the decorative boards of the door frame 5, a plurality of frame-side VDP control target decorative boards that are controlled by the sound source built-in VDP 4160a are provided. It is divided into electrical decoration information for the LED (decorative LED) and output information for the dial drive motor 414 provided in the operation unit 400 of the door frame 5 which is an electrical drive source on the door frame 5 side. To.

  The frame-side VDP control object decoration LED control circuit 194i of the frame-side VDP control object decoration LED control circuit 194i of the frame decoration drive amplifier board 194 in FIG. 42 has a frame-side VDP control object 143 decoration LED control circuit. 194i143 is a plurality of frames that are controlled by the built-in sound source VDP 4160a among the decorative boards of the door frame 5 based on the electrical decoration information as the control information output by the frame side signal separation control circuit 194g. It is possible to perform drive control of a plurality of LEDs (decorative LEDs) provided on each of the side VDP control target decorative boards. The output control circuit 194it1 provided in the frame side VDP control target decoration LED control circuit 194i of the frame decoration drive amplifier board 194 is based on the output information as the control information output by the frame side signal separation control circuit 194g. The drive control of the dial drive motor 414 provided in the operation unit 400 can be performed.

  Specifically, the frame-side signal separation control circuit 194g is based on the decoration information separated from the parallel signal restored by the receiver IC 194f, and the frame-side VDP control target decoration LED control circuit 194i has a frame-side VDP control target number 194i. 1 of the decorative LED control circuit 194i1 to the frame-side VDP control target 143 of the decorative LED control circuit 194i143 of the decorative frame of the door frame 5 is the control target directly controlled by the VDP 4160a with built-in sound source. By outputting a signal to the plurality of frame side VDP control target decoration boards, a plurality of LEDs (decoration LEDs) provided on each of the plurality of frame side VDP control target decoration boards emit light. As a result, the frame-side VDP control object decoration LED control circuit 194i uses the frame-side VDP control object first decoration LED control circuit 194i1 to the frame-side VDP control object 143 decoration LED control circuit 194i143 to perform frame-side signal separation. Based on the electrical decoration information as control information separated by the control circuit 194g, among the decorative boards of the door frame 5, a plurality of frame side VDP control target decorative boards that are controlled by the sound source built-in VDP 4160a are directly controlled. A light emission effect can be performed by a plurality of LEDs (decorative LEDs) provided in each.

  The frame-side signal separation control circuit 194g controls a motor drive circuit (not shown) included in the frame decoration drive amplifier board 194 via the output control circuit 194it1 based on the output information separated from the parallel signal restored by the receiver IC 194f. A signal can be output to produce an effect by the dial drive motor 414 provided in the operation unit 400 of the door frame 5. Thereby, the output control circuit 194it1 can execute an effect by the dial drive motor 414 provided in the operation unit 400 of the door frame 5 based on the output information as the control information separated by the frame side signal separation control circuit 194g. it can.

  Thus, based on the information read from the liquid crystal and sound control ROM 4160b, the output information is included as an image as control information for a plurality of LEDs (decorative LEDs) mounted on various decorative boards of the door frame 5. The side image object is created by the sound source built-in VDP 4160a, the parallel signal including the created frame side image object is output from the channel CH2 of the sound source built-in VDP 4160a, and the parallel signal is composed of a normal phase signal and a reverse phase signal. The transmitter IC 4160d converts a serial signal to be transmitted, and the converted serial signal is a differential one-pair cable configured by twisting a wiring for transmitting a positive-phase signal and a wiring for transmitting a reverse-phase signal. It is designed to be input to the receiver IC 194f via a twisted pair cable.That is, on the transmission path from the transmitter IC 4160d to the receiver IC 194f, a serial signal is transmitted via a twisted pair cable. The receiver IC 194f restores the input serial signal again to a parallel signal, and the frame-side signal separation control circuit 194g takes out output information as control information from the frame-side image object based on the restored parallel signal. Based on the output information as control information, the output control circuit 194it1 outputs a control signal to a motor drive circuit (not shown) provided in the frame decoration drive amplifier board 194 to drive the dial drive motor 414 provided in the operation unit 400 of the door frame 5. Control can be performed.

  A twisted pair cable is composed of a wire that transmits a positive-phase signal and a wire that transmits a reverse-phase signal, so that when noise enters the twisted-pair cable, the wire transmits a positive-phase signal. As a result, noise enters the wirings that transmit signals of opposite phases. Then, the noise that has entered the normal phase signal and the noise that has entered the reverse phase signal cancel each other, so that the receiver IC 194f can restore the parallel signal again with the noise removed. Therefore, accurate control can be realized for the controlled object.

  In addition to the dial drive motor 414 capable of imparting various behaviors to the dial operation unit 401, the door frame 5 is provided with a plurality of movable bodies and a plurality of motors capable of operating the plurality of movable bodies. When the door frame 5 is provided with an electrical drive source such as a solenoid or a solenoid, similarly to the dial drive motor 414, a motor drive circuit (not shown) provided on the frame decoration drive amplifier board 194 via the output control circuit 194it1 described above, A drive signal from a solenoid drive circuit (not shown) to a motor or solenoid (electric drive source) can be output. Examples of the movable body provided in the door frame 5 include a gaming device provided with a rotating body, a gaming device capable of moving the slide member in the left-right or up-down direction, and the like. The rotating body or the slide member may include a decoration LED or may not include a decoration LED.

  The motor drive circuit (not shown) capable of outputting a drive signal to the dial drive motor 414 (electric drive source) is provided with an enable signal input circuit, and an enable signal from the peripheral control MPU 4150a is input. A transmission path is formed as shown. Specifically, the enable signal is sent from the parallel I / O port of the peripheral control MPU 4150a of the peripheral control unit 4150 on the peripheral control board 4140 via the peripheral control output circuit (not shown) to the frame peripheral relay terminal plate 868 and the peripheral door relay terminal 882. Via the enable signal input circuit of the motor drive circuit (not shown) of the frame decoration drive amplifier board 194.

  A motor drive circuit (not shown) drives the dial drive motor 414 (electric drive source) according to the logic of the parallel signal (control signal) from the output port based on the logic of the enable signal from the peripheral control MPU 4150a. Enable or disable (prohibit) signal output. Here, the logic of the enable signal from the peripheral control MPU 4150a will be briefly described. When the logic of the enable signal from the peripheral control MPU 4150a is set to the operation permission logic (valid logic), the dial drive motor 414 (electric drive) As a drive permission state for permitting the drive of the power source), the peripheral control MPU 4150a is configured so that the motor drive circuit (not shown) has a dial drive motor 414 (electric drive source) according to the logic of the parallel signal (control signal) from the output port described above. While enabling the output of the drive signal to the peripheral control MPU 4150a, the logic of the enable signal from the peripheral control MPU 4150a is set to the operation non-permission logic (invalid logic (the logic obtained by inverting the operation permission logic (valid logic))). Drive that prohibits the drive of the dial drive motor 414 (electric drive source) In the stopped state, the peripheral control MPU 4150a prohibits the output of the drive signal to the dial drive motor 414 (electric drive source) according to the logic of the parallel signal (control signal) from the output port described above by the motor drive circuit (not shown). State

  The peripheral control MPU 4150a sets the logic of the enable signal, thereby allowing the dial drive motor 414 (electric drive source) to output the drive signal and rotating the dial drive motor 414, or the dial drive motor 414 (electrical drive). The output of the drive signal of the drive source) is prohibited, and the dial drive motor 414 can be stopped. Thereby, for example, when giving the behavior of rotating the dial operation unit 401 in the clockwise direction, the peripheral control MPU 4150a performs a special determination ranging from the start of change of the special symbol described above to the stop of change by the unique random number. Performed at predetermined intervals (for example, 3 seconds) or randomly within the period of fluctuation of symbol 1 and when the determination result is won, the logic of the enable signal is set to the operation permission logic (valid logic), while the determination result is lost. When this occurs, the logic of the enable signal is set to the operation disapproval logic (invalid logic). As a result, it is possible to create an effect in real time that the dial operation unit 401 rotates clockwise, stops, rotates clockwise again, and so on. Can do. In addition, in the case of giving the behavior of rotating the dial operation unit 401 counterclockwise, the peripheral control MPU 4150a independently performs a winning determination by a random number every predetermined interval (for example, 3 seconds) within one variation of the symbol or When the determination result is won, the logic of the enable signal is set to the operation permission logic (valid logic), while the logic of the enable signal is set to the operation disapproval logic (invalid logic) when the determination result is lost. . As a result, the dial operation unit 401 rotates counterclockwise, stops, rotates counterclockwise again, and so on. Can be produced. As described above, the peripheral control MPU 4150a can increase the variation of the effect by the dial operation unit 401 in real time by uniquely setting the logic of the enable signal. Therefore, a decrease in interest can be suppressed.

  The frame-side peripheral control MPU control target fifth decorative LED control circuit 194k5 to the frame-side peripheral control MPU control target seventh decorative LED control circuit 194k7 are the dish unit 300 shown in FIG. The whole dish unit 300 is decorated with light emission by performing dimming lighting of a plurality of LEDs (decorative LEDs) provided on each frame side peripheral control MPU control target decorative board provided in the operation unit 400. At the same time, the dial operation unit 401 and the pressing operation unit 405 of the operation unit 400 are decorated with light emission. Here, for example, the frame side VDP control target 131st decoration LED control circuit 194i131, the frame side VDP control target 131st decoration LED control circuit 194i131,..., The frame side VDP control target 143rd decoration LED A control circuit 194i143, an output control circuit 194it1, and a frame side VDP control target 145 decoration LED control circuit 194i145 are provided on the frame decoration drive amplifier board 194 and electrically connected as one serial connection (one serial system). The circuit configuration is as follows. The ID of the frame-side VDP control target 145 decoration LED control circuit 194i145 includes the frame-side VDP control target 131st decoration LED control circuit 194i131 to the frame-side VDP control target 143 decoration LED control circuit 194i143, and the output. Different IDs are set in the control circuit 194it1. Then, the decoration LED control circuit 194i145 of the frame side VDP control target 145 is a decoration LED (hereinafter referred to as “decoration LED of the operation unit 400”) as a plurality of LEDs mounted on each decoration board provided in the operation unit 400. In the case of driving (light emission), an enable signal input circuit is provided in each of the decorative LED control circuits 194i145 of the frame side VDP control target 145, and the LED enable signal from the peripheral control MPU 4150a is input. A transmission path may be formed as described above. Specifically, the LED enable signal is sent from the parallel I / O port of the peripheral control MPU 4150a of the peripheral control unit 4150 on the peripheral control board 4140 via a peripheral control output circuit (not shown) to the frame peripheral relay terminal plate 868, peripheral door relay terminal. 882 is input to the enable signal input circuit in the decorative LED control circuit 194i145 of the frame-side VDP control target 145 of the frame decoration drive amplifier board 194.

  The LED enable signal is set to one of a light emission permission logic (valid logic) and a light emission non-permission logic (invalid logic (a logic obtained by inverting the light emission permission logic (valid logic))). (Valid logic) is the same logic as the operation permission logic (valid logic) set in the enable signal described above, and the light emission disapproval logic (invalid logic) is set in the enable signal described above. Logic). When the light emission permission logic (valid logic) is set in the logic of the LED enable signal, the peripheral control MPU 4150a is in a drive permission state (light emission permission state) that permits driving (light emission) of the decoration LED of the operation unit 400. The frame-side VDP control target 145 decoration LED control circuit 194i145 is in a state of permitting adjustment of the brightness (gradation) of the decoration LED of the operation unit 400 based on the above-described electrical decoration information, while the LED enable signal When the light emission non-permission logic (invalid logic (a logic obtained by inverting the light emission permission logic (valid logic))) is set in the logic, a drive prohibition state (light emission prohibition) for prohibiting driving (light emission) of the decoration LED of the operation unit 400 As the state), the peripheral control MPU 4150a has the above-mentioned decoration LED control circuit 194i145 of the frame side VDP control target 145. A state that prohibits adjustment of decorative LED brightness of the operation unit 400 based on the distribution (gradation). As a result, when the dial operation unit 401 rotates, stops, rotates again, and so on, the decoration operation LED of the operation unit 400 is driven (light emission) when the dial operation unit 401 is intermittently rotated. Therefore, it is possible to provide a player with a sense of unity by linking (synchronizing) the operation of the dial operation unit 401 and the light emission mode of the decoration LED of the operation unit 400.

  The process for performing the above-described winning determination (hereinafter referred to as “door frame side movable effect execution winning determination process”) is performed by the effect control program, for example, the peripheral control of the peripheral control unit power-on process shown in FIG. In the received command analysis process of step S1022 in the steady part process, various commands stored in the received command storage area 4150cac are analyzed, and the analyzed command gives a behavior of rotating the dial operation unit 401 clockwise. When giving the behavior of rotating the dial operation unit 401 counterclockwise, the winning determination is performed at predetermined intervals (for example, 3 seconds) or randomly. The logic setting and output of the enable signal and the LED enable signal based on the determination result of the door frame side movable effect execution winning determination process are newly provided with the enable signal logic setting and output process in the peripheral control unit steady process described above. (This enable signal logic setting and output process may be performed as one process of the peripheral control unit 1 ms timer interrupt process shown in FIG. 70). When the special symbol 1 fluctuation period ends (when a special figure 1 tuning effect end command and a special figure 2 tuning effect end command are received), the logic of the enable signal is the initial value (that is, the operation permission logic, the light emission permission logic). (Valid logic)) and the enable signal is output in the enable signal logic setting and output process. It should be noted that the determination result by the door frame side movable effect execution winning determination process may be configured to be maintained and updated by providing a dedicated area, for example, in Bank0 (1fr) in the backup management target work area 4150ca as backup target information. Good. The logic of the enable signal and the LED enable signal is set to an operation permission logic and a light emission permission logic (effective logic) as initial values when the power is turned on. When power is restored due to a power failure or momentary power failure during hall operation, the logic of the enable signal and the LED enable signal is the initial value (that is, operation permission logic, light emission permission logic (valid logic)) ) May be set, operation permission logic, light emission permission logic (valid logic) or operation disabling logic, light emission disapproval logic (invalid) based on the dedicated area provided in the backup management target work area 4150ca Logic) may be set. The enable signal and the LED enable signal are configured as individual signals, but may be configured to be used as one common enable signal. In this way, it is possible to contribute to reducing the processing load of the peripheral control MPU 4150a by reducing the number of signals for setting logic, and it is also possible to contribute to cost reduction by reducing the number of wirings.

  In addition to the dial drive motor 414 capable of imparting various behaviors to the dial operation unit 401, the door frame 5 is provided with a plurality of movable bodies and a plurality of motors capable of operating the plurality of movable bodies. When the door frame 5 is provided with an electrical drive source such as a solenoid or a solenoid, similarly to the dial drive motor 414, a motor drive circuit (not shown) provided on the frame decoration drive amplifier board 194 via the output control circuit 194it1 described above, A drive signal from a solenoid drive circuit (not shown) to a motor or solenoid (electric drive source) can be output. Even in such a case, the logic of the above-described enable signals (motor enable signal, solenoid enable signal) is set and output from the peripheral control MPU 4150a, and the drive signal to the motor and solenoid (electric drive source) is output. By permitting output or disallowing (prohibiting), it is possible to create an effect by a plurality of movable bodies in the door frame 5 in real time and increase the variation of the effect in real time. Examples of the movable body provided in the door frame 5 include a gaming device provided with a rotating body, a gaming device capable of moving the slide member in the left-right or up-down direction, and the like. The rotating body or the slide member may include a decoration LED or may not include a decoration LED.

  Further, in the above-described embodiment, the sound source built-in VDP 4160a of FIG. 19 has two channels CH1 and CH2, the channel CH1 uses a differential interface by a serial method called LVDS, and the channel CH2 has a parallel method. However, it may have a plurality of channels including three channels and four channels. In this case, either one or both of the channels CH3 and CH4 may use a serial differential interface called LVDS or a parallel interface. When the sound source built-in VDP 4160a has a plurality of channels, an area for creating drawing data for each channel may be provided on the built-in sound source VDP 4160a, or may be externally attached to the sound source built-in VDP 4160a. Each RAM (frame memory) may be provided.

  Furthermore, in the above-described embodiment, the sound source built-in VDP 4160a has a predetermined screen (in this embodiment, red (R): 50%, green (G): 50%, blue (B): 50% gray having a 50%. Screen data defining the configuration of the screen) and a plurality of frame-side VDP control target decorative boards that are controlled by the sound source built-in VDP 4160a among the decorative boards of the door frame 5. When light emission data defining the light emission mode of the LED (decorative LED) is input from the peripheral control MPU 4150a, the liquid crystal and sound control is performed based on the input screen data in accordance with a predetermined door frame side generation rule. To draw a predetermined screen from the ROM 4160b (in this embodiment, a gray screen having red (R): 50%, green (G): 50%, blue (B): 50%). Dummy data is extracted to create sprite data, and door frame side drawing data is generated in the door frame side drawing data region VRGN2a of the door frame side display region VRGN2 provided on the built-in VRAM. Based on the data, among the decorative boards of the door frame 5 from the liquid crystal and sound control ROM 4160b, a plurality of frame side VDP control target decorative boards that are controlled by the sound source built-in VDP 4160a are provided. Door frame side light emission mode setting image data for setting the light emission mode of LED (decorative LED) is extracted, and the door frame side of the door frame side display area VRGN2 provided on the built-in VRAM with the electrical decoration information as drawing data By generating in the accompanying information area VRGN2b, a predetermined screen (in this embodiment, red (R): 50%, green (G : 50%, blue (B): gray screen having 50%), the door frame side display area VRGN2 is assumed to be obtained by attaching the illumination information to the door frame side drawing data according to a predetermined door frame side generation rule. The drawing data generated in the above is output from the channel CH2, but a plurality of LEDs (on each of the plurality of frame side VDP control target decorative boards that are controlled by the built-in sound source VDP 4160a) Only the door frame side light emission mode setting image data for setting the light emission mode of the decoration LED) is extracted, and the electrical decoration information is generated as drawing data in the door frame side display area VRGN2 provided on the built-in VRAM and drawn. Data may be output from channel CH2. That is, the door frame side display area VRGN2 is not provided at all in the door frame side display area VRGN2, and the door frame side display area VRGN2 is provided as the door frame side accompanying information area VRGN2b.

  In such a configuration, as the above-described predetermined door frame side generation rule, the first resolution conversion unit of the signal separation unit 194ga in the frame side signal separation control circuit 194g of the frame decoration drive amplifier board 194 shown in FIG. Since the door frame side drawing data for cutting out by 194gaa does not exist at all, the door frame side drawing data is not cut out at all, and the second resolution conversion unit 194gab of the signal separation unit 194ga includes the sound source built-in VDP 4160a. It is configured so that the illumination information generated as drawing data can be accurately cut out in the door frame side accompanying information region VRGN2b of the door frame side display region VRGN2 provided on the built-in VRAM, and the distribution output control unit 194gc converts the lighting information read from the buffer memory 194gb to the first serial controller. Each roller 194gd1~ 11 serial controller 194gd11 is configured to be able to accurately dispensed. According to the predetermined door frame side generation rule configured as described above, the signal separation unit 194ga does not cut out the door frame side drawing data at all in the first resolution conversion unit 194gaa, and the second resolution conversion unit 194gab. , The plurality of frame-side VDP control target decorative boards provided on each of the decorative boards of the door frame 5 from the drawing data restored to the parallel signal are controlled by the sound source built-in VDP 4160a. By cutting out the illumination information for the LED (decorative LED), a plurality of frames that are controlled by the built-in sound source VDP 4160a among the decorative boards of the door frame 5 from the drawing data restored to the parallel signal The illumination information for a plurality of LEDs (decorative LEDs) provided on each of the side VDP control target decoration substrates is separated. The performing the write operation is output to the buffer memory 194Gb.

  Furthermore, in the embodiment described above, the pachinko gaming machine 1 has been described as an example. However, the gaming machine to which the present invention can be applied is not limited to the pachinko gaming machine, and a gaming machine other than the pachinko gaming machine, for example, a slot machine. The present invention can also be applied to a (revolving game machine) or a fusion game machine in which a pachinko game machine and a slot machine are fused (one that uses a game ball to play a slot game). Here, a slot machine as a rotating game machine will be described with reference to FIG. FIG. 87 is a schematic perspective view of the slot machine.

  As shown in FIG. 87, the slot machine 6000 includes a front door 6002 and a main body portion 6004. Front door 6002 and main body portion 6004 are connected to each other via a hinge (not shown). With this hinge as the center of rotation, the front door 6002 can be opened from the main body portion 6004 by inserting a key into a key hole 6005 provided at the right end of the front door 6002 and turning it clockwise.

  The upper half of the front door 6002 is provided with a game panel 6006, and the lower half of the front door 6002 is formed with a protruding portion protruding forward from the game panel 6006. In the protruding portion, a medal slot 6008, bet buttons 6010 and 6012, a start lever 6014, a left stop button 6016, a middle stop button 6018, a right stop button 6020, and the like are arranged along the lower edge of the game panel 6006. A storage and settlement button 6022 and a decorative plate 6024 are arranged on the lower half of the front door 6002, and a tray 6026 is provided below the decorative plate 6024. These bet buttons 6010 and 6012, a start lever 6014, a left stop button 6016, a middle stop button 6018, a right stop button 6020, a storage settlement button 6022, and the like are a main control board (main control MPU) that controls the progress of a game (not shown). ) Is electrically connected.

  A rectangular display window (not shown) is formed at a substantially central position of the game panel 6006, and through the display window, three variable rotators (not shown) installed inside the slot machine 6000, a rendering device and the like are seen through. Be able to. On these variable rotators, translucent symbol bands on which a plurality of types of symbols (for example, bell, watermelon, cherry, 7, V, etc.) are printed as symbol information are affixed to the respective cylindrical frameworks. ing. Such a cylindrical variable rotating body is called a reel or a drum in a gaming machine such as a slot machine, and an output shaft of a stepping motor (not shown) and each variable rotating body are connected to each other. These stepping motors are driven and controlled by a main control board (main control MPU), and by rotating the output shaft of the stepping motor, a plurality of types of symbols are continuously displayed from above to the bottom from the display window. It seems to change to.

  The effect device includes a plurality of movable bodies (the above-described rotary light emitting device 3100, a model 3400 imitating an initiation device, and a model 3500 imitating dynamite), an effect display unit (the effect display unit 1900 described above), Each of the decorative substrates on which the LEDs are mounted. An effect control board (not shown) (sound source built-in VDP) is based on various commands from the main control board (main control MPU) and controls the drawing control of the liquid crystal panel in the effect display unit and the switching of a plurality of light guide plates of the effect display unit. The progress of the production is controlled by performing various controls such as the light emission control of the plurality of LEDs provided on each decorative board. The main control board and the effect control board are installed in the slot machine 6000.

  On the main control board (main control MPU), a predetermined number of medals are inserted as medal into the medal slot 6008, and the symbol information fluctuation display is started based on the operation of the start lever 6014. The change display of the symbol information is stopped based on the operation of the button 6018 and the right stop button 6020 or the elapse of a predetermined time. The main control board (main control MPU) generates a profit granting state (big hit gaming state) on the condition that the symbol information is in a predetermined specific display mode, and receives a large amount of medals as game media in the tray 6026. Pay out.

  In the fusion gaming machine, the medal slot 6008 becomes the ball slot 6008 ′, and the main control board (main control MPU) has a predetermined number of game balls thrown in the ball slot 6008 ′ as a game medium, and the start lever The symbol information variation display is started based on the operation 6014, and the symbol information variation display is stopped based on the operation of the left stop button 6016, the middle stop button 6018, the right stop button 6020, or the elapse of a predetermined time. Then, the main control board (main control MPU) generates a profit-giving state (big hit game state) on the condition that the symbol information is in a predetermined specific display mode, and receives a large amount of game balls as a game medium in the receiving tray 6026. Pay out.

  DESCRIPTION OF SYMBOLS 1 ... Pachinko machine, 2 ... Outer frame, 3 ... Main body frame, 4 ... Game board, 5 ... Door frame, 192 ... Handle relay terminal board, 300 ... Plate unit, 470 ... Upper plate side liquid crystal display device, 650 ... Hitting ball Launching device, 740 ... Prize ball device, 744 ... Dispensing motor, 751 ... Count switch, 784 ... External terminal board, 851 ... Power supply board, 855 ... Power supply control unit, 855d ... Power generation circuit, 855da ... Power consumption monitoring circuit, 855daa ... Power measurement circuit, 855db ... Power consumption suppression stage determination circuit, 855db ... + 5V power supply creation circuit, 855dc ... + 12V power supply creation circuit, 855dd ... + 24V power supply creation circuit, 860a ... Operation switch, 860b ... Error LED display, 1100 ... Game Area, 1900 ... Game board side effect display unit, 2100 ... Attacker unit, 2105 ... Start-up solenoid 2108 ... Attacker solenoid, 4100 ... Main control board, 4100a ... Main control MPU, 4110 ... Dispensing control board, 4120 ... Dispensing control section, 4120a ... Dispensing control MPU, 4120ag ... Launch ball feeding control circuit, 4120ah ... Launch ball feeding fault monitoring Circuit, 4140 ... Peripheral control board, 4150 ... Peripheral control unit, 4150a ... Peripheral control MPU, 4150f ... Power consumption status history RAM, 4150g ... Battery, 4150k ... Power saving mode transition notification LED, 4160 ... Liquid crystal and sound control unit, 4160a ... Sound source built-in VDP, 4165... RTC controller, 4165a... RTC, 4165b... Battery, 4180.

Claims (1)

A gaming machine that produces effects based on the progress of the game,
Control object,
Information storage means capable of storing a plurality of types of information related to the production;
Image object creation means capable of creating an image object so that control information for the control target is included as an image based on information read from the information storage means;
A parallel signal output unit for outputting a parallel signal including the image object created by the image object creating means;
A signal conversion means for converting the parallel signal output by the parallel signal output unit into a serial signal composed of a positive-phase signal and a reverse-phase signal and outputting the serial signal;
A stranded wire formed by twisting together a wiring that transmits the signal of the normal phase and a wiring that transmits the signal of the reverse phase;
A signal restoration means for restoring a serial signal composed of the positive phase signal and the negative phase signal input via the stranded wire to a parallel signal and outputting the parallel signal;
Extraction means for extracting and outputting the control information from the image object created by the image object creation means based on the restored parallel signal output by the signal restoration means;
Drive control means for performing drive control of the controlled object based on the control information output by the take-out means;
A gaming machine comprising: