JP6724723B2 - Switching circuit - Google Patents

Description

The technology disclosed in this specification relates to a switching circuit.

In an inverter or the like, a plurality of switching elements may be connected in parallel as power increases. A common drive signal is supplied to the gates of the plurality of switching elements connected in parallel, and the plurality of switching elements operate like one switching element. By sharing the power with the plurality of switching elements, it becomes possible to handle a large amount of power as a whole. Patent Document 1 discloses a switching circuit in which a plurality of switching elements are connected in parallel.

JP, 2013-247734, A

As described above, the common drive signal is supplied to the plurality of switching gates connected in parallel. However, due to the difference in the characteristics of the switching elements, a slight shift may occur in the switching timing among the plurality of switching elements even if the common drive signal is supplied. A difference in switching timing may cause a potential difference between the gate potentials of the plurality of switching elements, and the potential difference may cause an oscillation phenomenon between the plurality of switching elements connected in parallel. As a result, the gate voltage of the switching element may become excessive. The present specification discloses a technique capable of promptly turning off the gate of a switching element when an oscillation phenomenon of the switching element occurs.

A switching circuit disclosed in the present specification charges and discharges a first switching element, a second switching element connected in parallel to the first switching element, a gate of the first switching element and a gate of the second switching element. A control circuit, a first differentiating circuit that detects a time change amount of the potential of the gate of the first switching element, and a second differentiating circuit that detects a time change amount of the potential of the gate of the second switching element. There is. The control circuit turns off the first switching element and the second switching element when at least one of the time change amount detected by the first differentiating circuit and the time change amount detected by the second differentiating circuit becomes equal to or more than a threshold value.

When the switching timing is deviated between the first switching element and the second switching element, a potential difference occurs between the gate potential of the first switching element and the gate potential of the second switching element. As a result, the oscillation phenomenon starts. When the oscillation phenomenon occurs, the gate voltages of the first switching element and the second switching element change greatly in a short time. For this reason, the time change amount of the gate voltage becomes large as compared with the change of the gate voltage of the switching element in the normal operation. In the above switching circuit, the first differentiating circuit detects the time change amount of the potential of the gate of the first switching element, and the second differentiating circuit detects the time change amount of the potential of the gate of the second switching element. Then, the control circuit turns off the first switching element and the second switching element when at least one of the time change amount detected by the first differentiating circuit and the time change amount detected by the second differentiating circuit becomes equal to or more than a threshold value. To do. As described above, when the oscillation phenomenon occurs, the first switching element and the second switching element are quickly turned off, so that the gate voltage of the switching element can be prevented from becoming excessive.

The circuit diagram of the inverter 90. The circuit diagram of the switching circuit 10. The graph which shows change of each value at the time of normal operation. The graph which shows the change of each value at the time of oscillation.

FIG. 1 shows a circuit diagram of an inverter 90 to which the switching circuit 10 is applied. The inverter 90 has a high potential wiring 92 and a low potential wiring 94. A DC voltage is applied between the high-potential wiring 92 and the low-potential wiring 94 by a DC power supply (not shown). A DC voltage is applied so that the high potential wiring 92 has a high potential with respect to the low potential wiring 94. The inverter 90 converts this DC power into AC power and supplies it to the motor 95.

Between the high potential wiring 92 and the low potential wiring 94, three sets of circuits in which two switching circuits 10 are connected in series by the connection wiring 96 are provided. The configurations of the switching circuits 10 are equal to each other. FIG. 2 shows a circuit diagram of each switching circuit 10. The switching circuit 10 has a first switching element 11 and a second switching element 12. In this embodiment, the switching elements 11 and 12 are IGBTs (Insulated Gate Bipolar Transistors). The collector c1 of the first switching element 11 and the collector c2 of the second switching element 12 are connected, and the emitter e1 of the first switching element 11 and the emitter e2 of the second switching element 12 are connected. That is, the two switching elements 11 and 12 are connected in parallel. The parallel circuit of the two switching elements 11 and 12 is inserted in the connection wiring 96 so that the collectors c1 and c2 face the high potential wiring 92 side and the emitters e1 and e2 face the low potential wiring 94 side. A diode 21 is connected to the first switching element 11 in antiparallel. That is, the anode of the diode 21 is connected to the emitter e1 and the cathode of the diode 21 is connected to the collector c1. The diode 22 is connected to the second switching element 12 in antiparallel. That is, the anode of the diode 22 is connected to the emitter e2, and the cathode of the diode 22 is connected to the collector c2.

The inverter 90 has three intermediate wirings 98. Each intermediate wiring 98 is connected to each of the connection wirings 96 between the two switching circuits 10 connected in series. The other end of each intermediate wiring 98 is connected to the motor 95. Each switching circuit 10 switches the switching elements 11 and 12. As a result, the DC voltage applied between the high potential wiring 92 and the low potential wiring 94 is converted into a three-phase AC voltage, and the converted three-phase AC voltage is output between the three intermediate wirings 98. The three-phase AC voltage is supplied to the motor 95 via the three intermediate wirings 98.

Next, the structure of the switching circuit 10 will be described in more detail. As described above, the structures of the switching circuits 10 are equal to each other. Therefore, here, one switching circuit 10 will be described. As shown in FIG. 2, the switching circuit 10 includes a gate drive circuit 100 that charges and discharges the gates of the first switching element 11 and the second switching element 12.

A common drive signal is supplied from the gate drive circuit 100 to the gate g1 of the first switching element 11 and the gate g2 of the second switching element 12. Therefore, the first switching element 11 and the second switching element 12 switch at substantially the same timing. Therefore, a current having a total value of current capacities of the first switching element 11 and the second switching element 12 can be passed through the parallel circuit of the first switching element 11 and the second switching element 12.

The gate drive circuit 100 includes a control circuit 30, a first differentiating circuit 41, a second differentiating circuit 42, a first comparing circuit 51, and a second comparing circuit 52.

The control circuit 30 is connected to the gate g1 of the first switching element 11 and the gate g2 of the second switching element 12. Although not shown, the control circuit 30 receives a PWM signal from outside to instruct ON/OFF of the first switching element 11 and the second switching element 12. The control circuit 30 charges and discharges the gate g1 of the first switching element 11 and the gate g2 of the second switching element 12 according to the PWM signal. As a result, the potential Vge1 of the gate g1 of the first switching element 11 (that is, the potential of the gate g1 with respect to the emitter e1) and the potential Vge2 of the gate g2 of the second switching element 12 (that is, the potential of the gate g2 with respect to the emitter e2). Controlled. The control circuit 30 is also connected to the first comparison circuit 51 and the second comparison circuit 52. When receiving a predetermined signal from the first comparison circuit 51 or the second comparison circuit 52, the control circuit 30 discharges the gate g1 and the gate g2 regardless of the PWM signal.

The first differentiating circuit 41 has an input terminal 41a and an output terminal 41b. The input terminal 41a is connected to the gate g1. The output terminal 41b is connected to the first comparison circuit 51. Further, the first differentiating circuit 41 has a capacitor C1, an operational amplifier 44, and a resistor R1.

One electrode of the capacitor C1 is connected to the input terminal 41a. The operational amplifier 44 has an output terminal, a non-inverting input terminal, and an inverting input terminal. The output terminal of the operational amplifier 44 is connected to the output terminal 41b of the first differentiating circuit 41. The non-inverting input terminal of the operational amplifier 44 is connected to the ground (potential of the emitter e1). The inverting input terminal of the operational amplifier 44 is connected to the other electrode of the capacitor C1. Further, the inverting input terminal is connected to the output terminal via the resistor R1.

The potential Vge1 of the gate g1 of the first switching element 11 is applied to the input terminal 41a of the first differentiating circuit 41. The first differentiating circuit 41 outputs the potential Vamp1 corresponding to the time variation amount dVge1/dt of the potential Vge1 to the output terminal 41b.

The first comparison circuit 51 has an input terminal 51a and an output terminal 51b. The input terminal 51a is connected to the output terminal 41b of the first differentiating circuit 41. The output terminal 51b is connected to the control circuit 30. The first comparison circuit 51 also includes a comparator 54, a reference power supply V1, and resistors R3 and R4.

The comparator 54 has an output terminal, a non-inverting input terminal, and an inverting input terminal. The output terminal of the comparator 54 is connected to the output terminal 51b of the first comparison circuit 51. The non-inverting input terminal of the comparator 54 is connected to the input terminal 51a. The above-mentioned potential Vamp1 is applied to the non-inverting input terminal of the comparator 54. The inverting input terminal of the comparator 54 is connected to the resistance voltage dividing circuit 58 composed of the reference power source V1 and the resistors R3 and R4. The reference potential Vth1 output from the resistance voltage dividing circuit 58 is applied to the inverting input terminal of the comparator 54. The comparator 54 applies the signal CMP1 to the output terminal of the comparator 54 according to the potential Vamp1 and the reference potential Vth1. The signal CMP1 has a high potential when the potential Vamp1 is equal to or higher than the reference potential Vth1, and the signal CMP1 has a low potential when the potential Vamp1 is lower than the reference potential Vth1. The operation of the comparator 54 is equivalent to determining whether the time variation amount dVge1/dt is greater than or equal to the threshold value X (fixed value corresponding to the reference potential Vth1). That is, the signal CMP1 has a high potential when the time variation dVge1/dt is equal to or more than the threshold value X, and the signal CMP1 has a low potential when the time variation amount dVge1/dt is less than the threshold value X. Further, the comparator 54 maintains the signal CMP1 at a high potential when the repeated potential Vamp1 becomes equal to or higher than the reference potential Vth1 in a short time.

The second differentiating circuit 42 has an input terminal 42a and an output terminal 42b. The input terminal 42a is connected to the gate g2. The output terminal 42b is connected to the second comparison circuit 52. Further, the first differentiating circuit 41 has a capacitor C2, an operational amplifier 46, and a resistor R2. The second differentiating circuit 42 outputs the potential Vamp2 corresponding to the time variation amount dVge2/dt of the potential Vge2 of the gate g2 of the second switching element 12. Since the detailed configuration of the second differentiating circuit 42 is the same as the configuration of the first differentiating circuit 41, its description is omitted.

The second comparison circuit 52 has an input terminal 52a and an output terminal 52b. The input terminal 52a is connected to the output terminal 42b of the second differentiating circuit 42. The output terminal 52b is connected to the control circuit 30. The second comparison circuit 52 also includes a comparator 56, a reference power supply V2, and resistors R5 and R6. The second comparison circuit 52 compares the potential Vamp2 output from the second differentiating circuit 42 with the reference potential Vth2 output from the resistance voltage dividing circuit 59 including the reference power source V2 and the resistors R5 and R6, and the comparison result. A signal CMP2 corresponding to The detailed configuration of the second comparison circuit 52 is the same as the configuration of the first comparison circuit 51, and thus the description thereof is omitted. In this embodiment, the reference potential Vth2 is set equal to the reference potential Vth1. That is, the operation of the comparator 56 is equivalent to determining whether the time variation amount dVge2/dt is equal to or greater than the threshold value X.

The above-mentioned signal CMP1 and signal CMP2 are input to the control circuit 30. When at least one of the signal CMP1 and the signal CMP2 has a high potential (that is, when at least one of the time variation dVge1/dt and the time variation dVge2/dt is equal to or more than the threshold value X), the control circuit 30 determines that The gate g1 of the first switching element 11 and the gate g2 of the second switching element 12 are discharged regardless of the PWM signal to forcibly turn off the first switching element 11 and the second switching element 12.

Next, the operation of the switching circuit 10 will be described. Below, although it demonstrates focusing only on the operation|movement of the 1st switching element 11, the 1st differentiating circuit 41, and the 1st comparison circuit 51, the 2nd switching element 12, the 2nd differentiating circuit 42, and the 2nd comparison circuit 52. The same applies to the operation of. FIG. 3 shows the operation of the switching circuit 10 under normal conditions (when no oscillation phenomenon occurs).

In the period before the timing t1 in FIG. 3 (the period between the timing t0 and the timing t1), the control circuit 30 connects the gate g1 of the first switching element 11 to the ground. Therefore, the potential Vge1 is approximately 0 V, and the first switching element 11 is off. Therefore, the potential Vamp1 output from the first differentiating circuit 41 is approximately 0 V (that is, the time variation dVge1/dt of the potential Vge1 of the gate g1 is approximately zero). Since the potential Vamp1 is approximately 0 V, the comparator 54 determines that the potential Vamp1 (time change amount dVge1/dt) is lower than the reference potential Vth1 (threshold value X). Therefore, the signal CMP1 has a low potential.

At timing t1, the control circuit 30 starts charging the gate g1 based on the PWM signal. That is, a current is supplied from the control circuit 30 to the gate g1 and the gate g1 is gradually charged. Here, the capacitance between the gate g1 and the emitter e1 is charged. Therefore, the potential Vge1 gradually increases immediately after the timing t1 (the period between the timing t1 and the timing t2). Since the potential Vge1 has risen, the time variation dVge1/dt of the potential Vge1 increases during this period. That is, the potential Vamp1 output from the operational amplifier 44 becomes high. The above-mentioned threshold value X (threshold value with respect to time variation dVge1/dt) is set to a value larger than the time variation dVge1/dt of the potential Vge1 of the gate g1 when the first switching element 11 is normally turned on. Therefore, the comparator 54 determines that the potential Vamp1 is lower than the reference potential Vth1. Therefore, the signal CMP1 has a low potential.

At timing t2, the potential Vge1 of the gate g1 reaches the mirror voltage Vm. Then, the collector current starts flowing through the first switching element 11. As a result, the capacitance between the collector c1 and the gate g1 is charged, and the capacitance between the gate g1 and the emitter e1 is no longer charged. Therefore, after the timing t2 (between the timing t2 and the timing t3), the potential Vge1 is maintained at the mirror voltage Vm. The period from timing t2 to timing t3 is a mirror period. During the mirror period, the time change amount dVge1/dt of the potential Vge1 is substantially zero, which is smaller than the threshold value X. Therefore, the signal CMP1 has a low potential during the mirror period.

At timing t3, the capacitance between the collector c1 and the gate g1 is completed, and the capacitance between the gate g1 and the emitter e1 is charged again. Therefore, the mirror period ends at the timing t3, and the potential Vge1 of the gate g1 rises after the timing t3. Therefore, the time change amount dVge1/dt of the potential Vge1 becomes large. As described above, the threshold value X is set to a value larger than the time variation amount dVge1/dt of the potential Vge1 of the gate g1 when the first switching element 11 is normally turned on. Therefore, the comparator 54 determines that the potential Vamp1 is lower than the reference potential Vth1. Therefore, the signal CMP1 has a low potential.

After that, when the potential Vge1 reaches the target voltage at the timing t4, the control circuit 30 maintains the potential Vge1 at the target voltage after the timing t4. Therefore, the comparator 54 maintains the signal CMP1 at a low potential.

As described above, in the normal operation of the switching circuit 10, the signal CMP1 is always maintained at the low potential. Therefore, the control circuit 30 controls the potential Vge1 of the gate g1 of the first switching element 11 based on the PWM signal.

Next, the operation of the switching circuit 10 when the oscillation phenomenon occurs will be described. First, the oscillation phenomenon will be described.

The first switching element 11 and the second switching element 12 are switched from off to on at substantially the same time, but the timing of turning on between the first switching element 11 and the second switching element 12 may be shifted due to the difference in element characteristics. .. Hereinafter, the case where the first switching element 11 is turned on first will be considered. The wiring (conductor) connecting the emitter e1 of the first switching element 11 and the emitter e2 of the second switching element 12 has an inductance. Therefore, when the first switching element 11 is turned on, a current flows through the wiring on the first switching element 11 side, and an induced current is generated by the inductance. Due to this induced current, the potential of the emitter e1 of the first switching element 11 rises and the potential of the emitter e2 of the second switching element 12 falls. In the first switching element 11, the potential difference between the gate g1 and the emitter e1 becomes small, and the first switching element 11 that has been turned on once again turns off. On the other hand, in the second switching element 12, the potential difference between the gate g2 and the emitter e2 becomes large, and the second switching element 12 is turned on. Then, the current flowing through the wiring on the first switching element 11 side decreases, and the current flowing through the wiring on the second switching element 12 side increases. In response to the change in current at this time, an induced current in the opposite direction to the above occurs due to the inductance. Due to this induced current, the potential of the emitter e1 of the first switching element 11 decreases and the potential of the emitter e2 of the second switching element 12 increases. In the first switching element 11, the potential difference between the gate g1 and the emitter e1 becomes large, and the first switching element 11 is turned on again. On the other hand, in the second switching element 12, the potential difference between the gate g2 and the emitter e2 becomes small, and the second switching element 12 is turned off. In this way, the first switching element 11 is turned on first, so that the first switching element 11 and the second switching element 12 are repeatedly turned on and off. The same oscillation phenomenon may occur when the second switching element 12 is turned on first.

FIG. 4 shows the operation of the switching circuit 10 when the above-described oscillation phenomenon occurs (that is, when the switching timings of the first switching element 11 and the second switching element 12 are deviated). The operation in the period from the timing t0′ to the timing t4′ in FIG. 4 is the same as the operation in the normal time (the period from the timing t0 to the timing t4 in FIG. 3), and thus the description thereof will be omitted.

At timing t4′, when the potential Vge1 reaches the target voltage, the first switching element 11 is turned on. Then, the above-mentioned oscillation phenomenon occurs in the first switching element 11 after the timing t4′ due to the shift in the on-timing of the first switching element 11 and the second switching element 12. That is, the potential Vge1 of the gate g1 periodically changes in a short time, and the first switching element 11 repeats on and off in a short time. Since the potential Vge1 greatly changes, the time change amount dVge1/dt of the potential Vge1 increases during this period. That is, the potential Vamp1 output from the operational amplifier 44 becomes high. The threshold value X described above is set to a value smaller than the time variation dVge1/dt of the potential Vge1 of the gate g1 when the oscillation phenomenon occurs. Therefore, the comparator 54 determines that the potential Vamp1 (time change amount dVge1/dt) is higher than the reference potential Vth1 (threshold value X). Therefore, the comparator 54 switches the signal CMP1 from the low potential to the high potential at the timing t5′. As described above, the comparator 54 maintains the signal CMP1 at a high potential when the repeated potential Vamp1 becomes equal to or higher than the reference potential Vth1 in a short time. Therefore, after the timing t5′ (the period between the timing t5′ and the timing t6′), the comparator 54 maintains the signal CMP1 at the high potential. As a result, the control circuit 30 detects that the signal CMP1 has a high potential. Then, at the timing t6′, the control circuit 30 connects the gate g1 of the first switching element 11 to the ground and discharges the gate g1. Therefore, after the timing t6′, the potential Vge1 of the gate g1 drops and the first switching element 11 is completely turned off. Then, at timing t7′, the discharge of the gate g1 of the first switching element 11 is completed. Note that after the timing t6′, the control circuit 30 also discharges the gate g2 of the second switching element 12 at the same time. Then, after the timing t6′, the potential Vge2 of the gate g2 is lowered and the second switching element 12 is also completely turned off.

As described above, the switching circuit 10 can detect that the oscillation phenomenon has started to occur and promptly start the discharge of the gate g1. Therefore, the gate g1 can be discharged before the potential Vge1 of the gate g1 exceeds the withstand voltage of the switching element 11 due to the oscillation phenomenon. Further, even when the oscillation phenomenon occurs in the second switching element 12, the gate g1 of the first switching element 11 and the gate g1 of the second switching element 12 can be discharged similarly to the above description.

The switching circuit 10 described above has a configuration in which the two switching elements 11 and 12 are connected in parallel. However, the technology disclosed in this specification can also be applied to a switching circuit in which three or more switching elements are connected in parallel. By providing a differentiating circuit and a comparing circuit for each switching element, the gate of each switching element can be quickly discharged even when an oscillation phenomenon occurs in each switching element.

Moreover, in the switching circuit 10, the IGBT in which the current flows from the collector to the emitter is used as the switching element. However, the technology disclosed in this specification is not limited to the IGBT, and can be applied to other switching elements (for example, MOSFET). Further, the switching element may be of PNP type or NPN type. That is, it can also be applied to a switching element in which a current flows from the emitter to the collector.

Specific examples of the present invention have been described above in detail, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in the present specification or the drawings exert technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technique illustrated in the present specification or the drawings achieves a plurality of purposes at the same time, and achieving the one purpose among them has technical utility.

10: switching circuit 11: first switching element 12: second switching element 30: control circuit 41: first differentiating circuit 42: second differentiating circuit 51: first comparing circuit 52: second comparing circuit

Claims (1)

A first switching element,
A second switching element connected in parallel with the first switching element;
A control circuit for charging and discharging the gate of the first switching element and the gate of the second switching element;
A first differentiating circuit for detecting a time change amount of the potential of the gate of the first switching element;
A second differentiating circuit for detecting a time change amount of the potential of the gate of the second switching element,
Have
The control circuit, when at least one of the time change amount detected by the first differentiating circuit and the time change amount detected by the second differentiating circuit becomes a threshold value or more, the first switching element and the first switching element. 2 Turn off the switching element ,
The threshold is a time change amount of the potential of the gate of the first switching element caused by a current supplied from the control circuit to the gate of the first switching element and the gate of the second switching element, and the second value. Greater than the time variation of the potential of the gate of the switching element,
Switching circuit.

Images