JP2002141465A - Semiconductor module for electric power - Google Patents
Semiconductor module for electric powerInfo
- Publication number
- JP2002141465A JP2002141465A JP2000333207A JP2000333207A JP2002141465A JP 2002141465 A JP2002141465 A JP 2002141465A JP 2000333207 A JP2000333207 A JP 2000333207A JP 2000333207 A JP2000333207 A JP 2000333207A JP 2002141465 A JP2002141465 A JP 2002141465A
- Authority
- JP
- Japan
- Prior art keywords
- igbt
- resistor
- oscillation
- emitter
- igbts
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
- H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Power Conversion In General (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、例えばＮＰＴ（No
n Punch Through）型ＩＧＢＴ（Insulated GateBipolar
Transistor）を用いたワイヤ型のモジュールのテール
電流発生時の発振対策に関する。The present invention relates to, for example, NPT (No.
n Punch Through (IGBT) Insulated Gate Bipolar
The present invention relates to a countermeasure against oscillation when a tail current is generated in a wire-type module using a transistor.
【０００２】[0002]
【従来の技術】一般に、電圧駆動型電力用半導体素子と
して、ＩＧＢＴが知られている。ＩＧＢＴは、高入力イ
ンピーダンス特性、高速動作という特徴を有しており、
このＩＧＢＴにより構成されるＩＧＢＴモジュールが、
大容量インバータ等の用途に幅広く使用されている。2. Description of the Related Art Generally, an IGBT is known as a voltage-driven power semiconductor device. The IGBT has characteristics of high input impedance characteristics and high-speed operation,
An IGBT module constituted by this IGBT is:
Widely used for applications such as large capacity inverters.
【０００３】図４は、一般に使用されるＮＰＴ型ＩＧＢ
Ｔの断面図である。このＩＧＢＴは、図４に示すよう
に、ｐ＋型半導体基板２１上に気相成長により堆積され
たｎ―層２２内にｐ＋型拡散層２３が形成されている。
このｐ＋型拡散層２３内にｎ＋型拡散層２４が形成され
ている。ｎ＋型拡散層２４、ｐ＋型拡散層２３、ｎ―層
２２の上方には、絶縁膜２５ａにより絶縁されたＭＯＳ
ＦＥＴのゲート電極Ｇが設けられている。また、ｐ＋型
拡散層２３及び絶縁膜２５ｂ上にエミッタ電極Ｅとして
の配線２６が設けられている。コレクタ電極Ｃは前記ｐ
＋型半導体基板２１より取り出される。FIG. 4 shows a commonly used NPT type IGB.
It is sectional drawing of T. In this IGBT, as shown in FIG. 4, ap + type diffusion layer 23 is formed in an n − layer 22 deposited on a p + type semiconductor substrate 21 by vapor phase growth.
An n + -type diffusion layer 24 is formed in the p + -type diffusion layer 23. Above the n + type diffusion layer 24, the p + type diffusion layer 23, and the n − layer 22, a MOS insulated by an insulating film 25a is provided.
A gate electrode G of the FET is provided. Further, a wiring 26 as an emitter electrode E is provided on the p + type diffusion layer 23 and the insulating film 25b. The collector electrode C is
It is taken out from the + type semiconductor substrate 21.
【０００４】上記構成において、ゲート電極に印加され
る電圧により、コレクタ・エミッタ間に流れる電流が制
御される。すなわち、ＩＧＢＴは、スイッチング素子と
して動作する。In the above configuration, the current flowing between the collector and the emitter is controlled by the voltage applied to the gate electrode. That is, the IGBT operates as a switching element.
【０００５】図５は、ＩＧＢＴの等価回路を示してい
る。図５において、ＳＥは図４には示していないエミッ
タ電流検出用のセンスエミッタである。このセンスエミ
ッタＳＥは、電流制御回路ＲＴＣに接続される。この電
流制御回路ＲＴＣは、センスエミッタにより検出された
電流によりゲート電圧を制御する機能を有する。FIG. 5 shows an equivalent circuit of the IGBT. In FIG. 5, SE is a sense emitter for detecting an emitter current not shown in FIG. This sense emitter SE is connected to a current control circuit RTC. This current control circuit RTC has a function of controlling the gate voltage based on the current detected by the sense emitter.
【０００６】上記構成ＩＧＢＴが回路基板上に複数配置
され、これらが例えば並列接続される。さらに、ゲー
ト、エミッタ、コレクタ電極に外部電極等が設けられる
ことにより、ＩＧＢＴモジュールが形成される。複数の
ＩＧＢＴの各電極の相互接続手段としては、各電極をボ
ンディングワイヤにより接続する構成と、電極相互に金
属板を圧接する構成が知られている。A plurality of the above-mentioned IGBTs are arranged on a circuit board, and these are connected in parallel, for example. Furthermore, an IGBT module is formed by providing external electrodes and the like on the gate, emitter, and collector electrodes. As a means for interconnecting each electrode of a plurality of IGBTs, a configuration in which each electrode is connected by a bonding wire and a configuration in which a metal plate is pressed against each other are known.
【０００７】[0007]
【発明が解決しようとする課題】ところで、２チップ以
上で構成されるＩＧＢＴモジュールにおいて、コレクタ
電流のテール部分で発振現象が生ずることが知られてい
る。この発振現象は、ＩＧＢＴのＭＯＳＦＥＴ部がオフ
になった後（ゲート電圧が逆バイアス値に達した後）コ
レクタテール電流が切れる直前で発生する。この発振現
象は、エミッタで起こっており、ゲート・エミッタ間電
圧としても測定できる。このため、一般にゲート発振と
呼んでいる。In an IGBT module composed of two or more chips, it is known that an oscillation phenomenon occurs at a tail portion of a collector current. This oscillation phenomenon occurs immediately before the collector tail current is cut off after the MOSFET portion of the IGBT is turned off (after the gate voltage reaches the reverse bias value). This oscillation phenomenon occurs at the emitter, and can be measured as a gate-emitter voltage. For this reason, it is generally called gate oscillation.
【０００８】図６（ａ）は、２個のＮＰＴ型ＩＧＢＴを
並列接続した際の、テール電流発生時の状態を概略的に
示している。また、図６（ｂ）は、図６（ａ）に示す状
態の等価回路を示している。図６（ａ）において、２２
ａはｎ―層２２の空乏化していない領域であり、２２ｂ
は空乏化したそれを示している。各ＩＧＢＴのコレクタ
電極は回路基盤としてのＤＢＣ（Direct Bond Copper）
により接続され、エミッタ電極相互はボンディングワイ
ヤを介して接続されている。Ｌｅはボンディングワイヤ
のインダクタンスである。また、図６（ｂ）中のＣｅは
空乏化されたｎ ―層２２ａの容量を示し、可変抵抗Ｒは
空乏化されていないｎ―層２２ｂの抵抗を示している。FIG. 6A shows two NPT-type IGBTs.
Schematic of the state when tail current occurs when connected in parallel
Is shown. FIG. 6B shows the state shown in FIG.
2 shows an equivalent circuit of the state. In FIG. 6A, 22
a is n―A region of the layer 22 that is not depleted, 22b
Shows that it is depleted. Collector of each IGBT
Electrodes are DBC (Direct Bond Copper) as a circuit board
And the emitter electrodes are bonded together.
Connected via a LeIs a bonding wire
Is the inductance of Further, C in FIG.eIs
Depleted n ―The variable resistance R indicates the capacitance of the layer 22a.
N not depleted―This shows the resistance of the layer 22b.
【０００９】発振のメカニズムは次のように推測され
る。ＩＧＢＴがターンオフすると、ｎ ―層２２ｂの一部
は空乏化されない状態で残る。このｎ―層２２ｂにコレ
クタからホールが注入されると、伝導度変調効果でｎ―
層２２ｂの抵抗値は低下し、負性抵抗を示す。各ＩＧＢ
Ｔは特性にばらつきがあり、負性抵抗領域に入るタイミ
ングがそれぞれ異なる。このため、各ＩＧＢＴの抵抗
Ｒ、容量Ｃｅ、及びボンディングワイヤインダクタンス
Ｌｅにより発振が起こる。The mechanism of oscillation is assumed as follows.
You. When the IGBT turns off, n ―Part of layer 22b
Remains undepleted. This n―This on layer 22b
When holes are injected from the reactor, the conductivity modulation effect causes n―
The resistance value of the layer 22b decreases, indicating negative resistance. Each IGB
T has a variation in the characteristics, and the timing
Ring is different. Therefore, the resistance of each IGBT
R, capacity CeAnd bonding wire inductance
LeCauses oscillation.
【００１０】この発振は、図示せぬゲート抵抗ＲＧ、ゲ
ート・エミッタ間に外付けされたコンデンサの容量Ｃ
ＧＥ、及び、ゲート・エミッタ間電圧ＶＧＥ等のゲート
回路の状態に依存しない。すなわち、ドライブ条件に依
存しない特徴を有する。このため、例えば、ゲート配線
に所謂アモビーズ等のフェライトコアを配置しても発振
を回避することはできない。This oscillation is caused by a gate resistance R G (not shown) and a capacitance C of a capacitor externally connected between the gate and the emitter.
It does not depend on the state of the gate circuit such as GE and the gate-emitter voltage V GE . That is, it has a feature that does not depend on the drive conditions. Therefore, for example, even if a ferrite core such as so-called amobeads is arranged on the gate wiring, oscillation cannot be avoided.
【００１１】また、圧接型のＩＧＢＴモジュールの場
合、チップ周囲にパーマロイリングを装着し、上記発振
を防ぐ方法も考えられている。しかしながら、パーマロ
イリングは高価であるため、高コストとなる問題があ
る。さらに、このパーマロイリングはワイヤ型ＩＧＢＴ
モジュールには、適用できない。In the case of a press-contact type IGBT module, a method for preventing the above-mentioned oscillation by mounting a permalloy ring around the chip has been considered. However, since the permalloy ring is expensive, there is a problem that the cost is high. Furthermore, this permalloy ring is a wire type IGBT
Not applicable to modules.
【００１２】本発明は、上記課題を解決するためになさ
れたものであり、その目的とするところは、テール電流
発生時における発振を回避することが可能で、安価な電
力用半導体モジュールを提供しようとするものである。SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object thereof is to provide an inexpensive power semiconductor module which can avoid oscillation when a tail current is generated. It is assumed that.
【００１３】[0013]
【課題を解決するための手段】本発明の電力用半導体モ
ジュールは、上記課題を解決するため、並列接続された
少なくとも２つ以上のＭＯＳゲート駆動型スイッチング
デバイスと、前記各ＭＯＳゲート駆動型スイッチングデ
バイスのエミッタ電極相互間に接続された抵抗とを具備
することを特徴とする。In order to solve the above-mentioned problems, a power semiconductor module according to the present invention comprises at least two or more MOS gate driving switching devices connected in parallel, and each of the MOS gate driving switching devices. And a resistor connected between the emitter electrodes.
【００１４】本発明の電力用半導体モジュールは、基板
上に並列接続して配置された第１、第２のＭＯＳゲート
駆動型スイッチングデバイスと、前記基板上で前記第
1、第２のＭＯＳゲート駆動型スイッチングデバイスの
近傍にそれぞれ設けられ、前記第１、第２のＭＯＳゲー
ト駆動型スイッチングデバイスのエミッタ電極がそれぞ
れ接続される第１、第２の配線と、前記第１、第２の配
線の相互間に接続された抵抗とを具備することを特徴と
する。A power semiconductor module according to the present invention comprises a first and a second MOS gate drive type switching device arranged in parallel on a substrate, and the first and second MOS gate driving switching devices on the substrate.
First and second wirings respectively provided near the first and second MOS gate drive switching devices and connected to the emitter electrodes of the first and second MOS gate drive switching devices, respectively; 1, and a resistor connected between the second wirings.
【００１５】また、前記抵抗の抵抗値は５乃至２００Ω
であることを特徴とする。The resistance value of the resistor is 5 to 200Ω.
It is characterized by being.
【００１６】[0016]
【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照して説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００１７】図１は本発明に係る電力用半導体モジュー
ルの内部構造を概略的に示す平面図である。図１はＭＯ
Ｓゲート駆動型スイッチングデバイスとしてのＩＧＢＴ
を用いた２つのＩＧＢＴモジュールＭ１、Ｍ２を示して
いる。これらＩＧＢＴモジュールＭ１、Ｍ２は、同一構
成であるためモジュールＭ１についてのみ説明する。Ｉ
ＧＢＴモジュールＭ１において、１はセラミックス基板
に、例えばコレクタ、エミッタ、ゲート等の各種電極を
独特な方法で張り合わせた周知のＤＢＣ基板である。こ
のＤＢＣ基板１上には、例えば第１、第２のＩＧＢＴチ
ップ（以下、単にＩＧＢＴと称す）Ｑ１、Ｑ２が配置さ
れている。FIG. 1 is a plan view schematically showing the internal structure of a power semiconductor module according to the present invention. Figure 1 shows MO
IGBT as S gate drive type switching device
2 shows two IGBT modules M1 and M2. Since these IGBT modules M1 and M2 have the same configuration, only the module M1 will be described. I
In the GBT module M1, reference numeral 1 denotes a well-known DBC substrate in which various electrodes such as a collector, an emitter, and a gate are bonded to a ceramic substrate by a unique method. On the DBC substrate 1, for example, first and second IGBT chips (hereinafter simply referred to as IGBTs) Q1 and Q2 are arranged.
【００１８】第１、第２のＩＧＢＴＱ１、Ｑ２の表面に
は複数のエミッタ電極２ａ、ゲート電極２ｂ、及びセン
スエミッタ電極２ｃがそれぞれ配置されている。第１、
第２のＩＧＢＴＱ１、Ｑ２の裏面には、図示せぬコレク
タ電極が設けられ、これらコレクタ電極はＤＢＣ１によ
り接続されている。ＤＢＣ１の表面には、第１、第２の
ＩＧＢＴＱ１、Ｑ２に沿って、例えば銅線による配線３
ａ、３ｂがそれぞれ設けられている。第１、第２のＩＧ
ＢＴＱ１、Ｑ２のエミッタ電極２ａのうち、１つのエミ
ッタ電極はボンディングワイヤ４により前記配線３ａ、
３ｂにそれぞれ接続されている。A plurality of emitter electrodes 2a, gate electrodes 2b, and sense emitter electrodes 2c are arranged on the surfaces of the first and second IGBTs Q1, Q2, respectively. First,
Collector electrodes (not shown) are provided on the back surfaces of the second IGBTs Q1 and Q2, and these collector electrodes are connected by DBC1. On the surface of the DBC1, along with the first and second IGBTs Q1 and Q2, a wiring
a, 3b are provided respectively. First and second IG
One of the emitter electrodes 2a of the BTQ1 and Q2 is connected to the wiring 3a by a bonding wire 4.
3b.
【００１９】また、前記配線３ａ、３ｂの相互間には、
抵抗素子、例えばチップ抵抗５が半田付けにより配置さ
れ、配線３ａ、３ｂはこの抵抗５を介して接続されてい
る。したがって、第１、第２のＩＧＢＴＱ１、Ｑ２のエ
ミッタ電極は、この抵抗５を介して接続される。Further, between the wirings 3a and 3b,
A resistance element, for example, a chip resistor 5 is arranged by soldering, and the wirings 3a and 3b are connected via the resistor 5. Therefore, the emitter electrodes of the first and second IGBTs Q1 and Q2 are connected via the resistor 5.
【００２０】なお、上記抵抗５としてチップ抵抗を使用
したが、前記配線３ａ、３ｂを相互に接続して抵抗素子
とすることもできる。すなわち、配線３ａ、３ｂ相互間
に抵抗が形成される構成であればよい。Although a chip resistor is used as the resistor 5, the wires 3a and 3b may be connected to each other to form a resistor. That is, any configuration may be used as long as a resistance is formed between the wirings 3a and 3b.
【００２１】前記ＤＢＣ１の表面には、第１、第２のＩ
ＧＢＴＱ１、Ｑ２に対応して２個ずつ、第１、第２のＩ
ＧＢＴＱ１、Ｑ２への逆流電流を阻止するフライホイー
リングダイオード６が配置されている。これらフライホ
イーリングダイオード６のアノードは第１、第２のＩＧ
ＢＴＱ１、Ｑ２の対応するエミッタ電極２ａにボンディ
ングワイヤにより接続されるとともに、ＤＢＣ１の表面
に設けられたエミッタ電極用の配線３ｃにボンディング
ワイヤにより接続されている。また、これらフライホイ
ーリングダイオード６の図示せぬカソードは、ＤＢＣ１
を介して第１、第２のＩＧＢＴＱ１、Ｑ２の対応するコ
レクタに接続されている。On the surface of the DBC1, first and second I
First and second I, two each corresponding to GBT Q1, Q2
A flywheeling diode 6 for preventing a backflow current to GBTs Q1 and Q2 is arranged. The anodes of these flywheeling diodes 6 are the first and second IGs.
The emitter electrodes 2a of the BTs Q1 and Q2 are connected to the corresponding emitter electrodes 2a by bonding wires, and are also connected to the emitter electrode wiring 3c provided on the surface of the DBC 1 by bonding wires. The cathodes (not shown) of these flywheeling diodes 6 are DBC1
To the corresponding collectors of the first and second IGBTs Q1, Q2.
【００２２】さらに、ＤＢＣ基盤１の表面には、コレク
タ電極配線７、及び図示せぬサーミスタが接続される接
続端子８が設けられている。Further, a collector electrode wiring 7 and a connection terminal 8 to which a thermistor (not shown) is connected are provided on the surface of the DBC substrate 1.
【００２３】図２は、上記構成のＩＧＢＴモジュールＭ
１の等価回路図であり、図１と同一部分には同一符号を
付す。第１及び第２のＩＧＢＴＱ１、Ｑ２のエミッタ電
極相互間は抵抗５により接続されている。尚、Ｌはエミ
ッタのボンディングワイヤによるインダクタンスを示し
ている。このような構成とすることにより、並列接続さ
れたＩＧＢＴ回路のＱを低下させ、回路が発振すること
を防ぐことができる。FIG. 2 shows an IGBT module M having the above configuration.
2 is an equivalent circuit diagram of FIG. 1, and the same parts as those of FIG. The resistor 5 is connected between the emitter electrodes of the first and second IGBTs Q1 and Q2. L indicates the inductance of the bonding wire of the emitter. With such a configuration, the Q of the IGBT circuits connected in parallel can be reduced, and oscillation of the circuits can be prevented.
【００２４】上記Ｑの値は、抵抗５の抵抗値、インダク
タンスにより相違する。図３は、抵抗の抵抗値と発振開
始電圧との関係を示している。図３に示すように、抵抗
値がほぼ２乃至１０００Ωの範囲の場合、コレクタ・エ
ミッタ間電圧が１０００Ｖ乃至１５００Ｖの範囲で発振
しないことが確認できた。測定装置の関係でこれ以上の
電圧に関して測定することができなかったが、１５００
Ｖ以上の電圧でも発振しないものと推定される。抵抗値
の範囲としては、２乃至１０００Ωに限定されるもので
はなく、好ましい範囲は１５００Ｖでも発振しないほぼ
５乃至２００Ωであり、最適値はほぼ１００Ωである。The value of Q differs depending on the resistance value of the resistor 5 and the inductance. FIG. 3 shows the relationship between the resistance value of the resistor and the oscillation start voltage. As shown in FIG. 3, it was confirmed that when the resistance value was in the range of approximately 2 to 1000 Ω, the oscillation did not occur when the collector-emitter voltage was in the range of 1000 V to 1500 V. Due to the measuring device, it was not possible to measure any more voltage, but 1500
It is presumed that oscillation does not occur even at a voltage higher than V. The range of the resistance value is not limited to 2 to 1000Ω, and a preferable range is approximately 5 to 200Ω which does not oscillate even at 1500 V, and the optimum value is approximately 100Ω.
【００２５】上記実施例によれば、並列接続された第
１、第２のＩＧＢＴＱ１、Ｑ２の配線３ａ、３ｂ相互間
に抵抗５を挿入している。このため、第１、第２のＩＧ
ＢＴＱ１、Ｑ２からなる回路のＱを低下することができ
る。したがって、テール電流時の発振を防ぐことができ
る。According to the above embodiment, the resistor 5 is inserted between the wirings 3a and 3b of the first and second IGBTs Q1 and Q2 connected in parallel. Therefore, the first and second IGs
The Q of the circuit composed of BTQ1 and Q2 can be reduced. Therefore, oscillation at the time of tail current can be prevented.
【００２６】また、前記抵抗５をＤＢＣ基板１上の、配
線３ａ、３ｂ相互間に半田付けにより配置している。こ
のため、この抵抗５を第１、第２のＩＧＢＴＱ１、Ｑ２
の近傍に配置することができ、しかも、熱による抵抗の
はがれも防止することができる。The resistor 5 is disposed on the DBC substrate 1 between the wirings 3a and 3b by soldering. Therefore, this resistor 5 is connected to the first and second IGBTs Q1 and Q2.
, And the resistance can be prevented from peeling off due to heat.
【００２７】さらに、抵抗を挿入するという簡易な方法
により、発振を防いでいる。したがって、安価で、確実
に発振を回避できる電力用半導体モジュールを実現でき
る。Further, oscillation is prevented by a simple method of inserting a resistor. Therefore, an inexpensive power semiconductor module that can reliably avoid oscillation can be realized.
【００２８】その他、本発明の要旨を変えない範囲にお
いて種々変形実施可能なことは勿論である。It goes without saying that various modifications can be made without departing from the spirit of the present invention.
【００２９】[0029]
【発明の効果】以上、詳述したように本発明によれば、
テール電流発生時における発振を回避することが可能
で、安価な電力用半導体モジュールを提供できる。As described in detail above, according to the present invention,
Oscillation during tail current generation can be avoided, and an inexpensive power semiconductor module can be provided.
【図１】本発明に係る半導体モジュールの内部を示す平
面図。FIG. 1 is a plan view showing the inside of a semiconductor module according to the present invention.
【図２】図１に示すＩＧＢＴモジュールの等価回路を示
す図。FIG. 2 is a diagram showing an equivalent circuit of the IGBT module shown in FIG.
【図３】図１の例における、挿入抵抗と発振開始電圧と
の関係を示す図。FIG. 3 is a diagram showing a relationship between an insertion resistance and an oscillation start voltage in the example of FIG. 1;
【図４】一般的なＩＧＢＴを示す断面図。FIG. 4 is a sectional view showing a general IGBT.
【図５】ＩＧＢＴの回路構成を示す図。FIG. 5 is a diagram showing a circuit configuration of an IGBT.
【図６】テール電流発生時のＩＧＢＴの状態を示す概略
図、及び等価回路。FIG. 6 is a schematic diagram showing an IGBT state when a tail current is generated, and an equivalent circuit.
Ｍ１、Ｍ２…ＩＧＢＴモジュール、 Ｑ１、Ｑ２…ＩＧＢＴチップ、 １…ＤＢＣ基盤、 ２ａ…エミッタ電極、 ２ｂ…ゲート電極、 ２ｃ…センスエミッタ電極、 ３ａ、３ｂ…配線、 ４…ボンディングワイヤ、 ５…抵抗、 ６…フライホイールダイオード、 ７…コレクタ電極配線、 ８…サーミスタ接続端子。 M1, M2: IGBT module, Q1, Q2: IGBT chip, 1: DBC board, 2a: Emitter electrode, 2b: Gate electrode, 2c: Sense emitter electrode, 3a, 3b: Wiring, 4: Bonding wire, 5: Resistance, 6 ... flywheel diode, 7 ... collector electrode wiring, 8 ... thermistor connection terminal.
Claims (3)
ＯＳゲート駆動型スイッチングデバイスと、 前記各ＭＯＳゲート駆動型スイッチングデバイスのエミ
ッタ電極相互間に接続された抵抗とを具備することを特
徴とする電力用半導体モジュール。1. At least two or more M connected in parallel
A power semiconductor module comprising: an OS gate drive switching device; and a resistor connected between emitter electrodes of each of the MOS gate drive switching devices.
第２のＭＯＳゲート駆動型スイッチングデバイスと、 前記基板上で前記第1、第２のＭＯＳゲート駆動型スイ
ッチングデバイスの近傍にそれぞれ設けられ、前記第
１、第２のＭＯＳゲート駆動型スイッチングデバイスの
エミッタ電極がそれぞれ接続される第１、第２の配線
と、 前記第１、第２の配線の相互間に接続された抵抗とを具
備することを特徴とする電力用半導体モジュール。2. The method according to claim 1, further comprising:
A second MOS gate drive switching device; and emitters of the first and second MOS gate drive switching devices provided on the substrate in the vicinity of the first and second MOS gate drive switching devices, respectively. A power semiconductor module comprising: first and second wirings to which electrodes are respectively connected; and a resistor connected between the first and second wirings.
ることを特徴とする請求項１、２のいずれかに記載の電
力用半導体モジュール。3. The power semiconductor module according to claim 1, wherein a resistance value of said resistor is 5 to 200 Ω.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000333207A JP2002141465A (en) | 2000-10-31 | 2000-10-31 | Semiconductor module for electric power |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000333207A JP2002141465A (en) | 2000-10-31 | 2000-10-31 | Semiconductor module for electric power |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002141465A true JP2002141465A (en) | 2002-05-17 |
Family
ID=18809322
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000333207A Abandoned JP2002141465A (en) | 2000-10-31 | 2000-10-31 | Semiconductor module for electric power |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002141465A (en) |
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| JP2008288435A (en) * | 2007-05-18 | 2008-11-27 | Mitsubishi Electric Corp | Design method of power semiconductor module |
| JP2012038803A (en) * | 2010-08-04 | 2012-02-23 | Mitsubishi Electric Corp | Power module |
| CN102856308A (en) * | 2011-06-29 | 2013-01-02 | 株式会社日立制作所 | Power semiconductor module |
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