JP6719541B2 - Circuit board structure and manufacturing method thereof - Google Patents

Circuit board structure and manufacturing method thereof Download PDF

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JP6719541B2
JP6719541B2 JP2018235034A JP2018235034A JP6719541B2 JP 6719541 B2 JP6719541 B2 JP 6719541B2 JP 2018235034 A JP2018235034 A JP 2018235034A JP 2018235034 A JP2018235034 A JP 2018235034A JP 6719541 B2 JP6719541 B2 JP 6719541B2
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laser
hole
circuit board
board structure
conductive layer
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JP2020013973A (en
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微▲か▼ 婁
微▲か▼ 婁
奇 孫
奇 孫
政明 呂
政明 呂
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Tripod Wuxi Electronic Co Ltd
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Tripod Wuxi Electronic Co Ltd
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/429Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0296Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298Multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/115Via connections; Lands around holes or via connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0017Etching of the substrate by chemical or physical means
    • H05K3/0026Etching of the substrate by chemical or physical means by laser ablation
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0044Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0047Drilling of holes
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/10Using electric, magnetic and electromagnetic fields; Using laser light
    • H05K2203/107Using laser light

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Laser Beam Processing (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Description

本発明は回路基板に関し、特に機械方式による穿孔を必要としない回路基板構造及びその製造方法に関する。 The present invention relates to a circuit board, and more particularly to a circuit board structure that does not require mechanical perforation and a method for manufacturing the same.

図1に示されるように、従来の回路基板構造100’では、その多層板1’を貫通している貫通孔2’を形成するには、機械方式による穿孔方法が使用されるのが一般的である。しかしながら、回路基板構造の設計密度が高まると、上記機械方式による穿孔方法では生産にかかる時間を延ばすだけでなく、回路基板構造の配線密度を減少させることが予測される。 As shown in FIG. 1, in a conventional circuit board structure 100′, a mechanical drilling method is generally used to form a through hole 2′ penetrating the multilayer board 1′. Is. However, as the design density of the circuit board structure increases, it is expected that the mechanical drilling method not only prolongs the production time but also reduces the wiring density of the circuit board structure.

また、図示しない別の従来の回路基板構造では、多層板の層ごとにレーザ穿孔方式で板を貫通させてめっきすることで、多層板に貫通孔及び貫通孔内にめっきされている導電体を形成する。しかしながら、上記のように層ごとにレーザ穿孔を行う方式によれば、生産にかかる時間を著しく延ばし、さらに回路基板構造の生産コストを上昇させる。 Further, in another conventional circuit board structure (not shown), a plate is pierced by a laser perforation method for each layer of the multilayer board to plate the multilayer board to form a through hole and a conductor plated in the through hole. Form. However, the method of performing laser drilling layer by layer as described above significantly increases the production time and further increases the production cost of the circuit board structure.

このため、本発明者は、上記欠点を改善するために、鋭意研究を重ねて科学原理を活用した結果、設計が合理的で且つ上記欠点を効果的に改善する本発明を提供している。 Therefore, the present inventor has provided the present invention in which the design is rational and the aforesaid drawbacks are effectively ameliorated as a result of intensive studies and utilization of scientific principles in order to ameliorate the aforesaid drawbacks.

本発明の目的は、従来の回路基板構造の製造方法で発生し得る欠点を効果的に改善するために、回路基板構造及びその製造方法を提供することである。 SUMMARY OF THE INVENTION It is an object of the present invention to provide a circuit board structure and a method of manufacturing the same in order to effectively improve the drawbacks that may occur in the conventional method of manufacturing a circuit board structure.

本発明は、N層(Nは2より大きい正整数である)の導電層を有する多層板を提供する準備ステップと、N層の前記導電層のうちの1層目の前記導電層からレーザ穿孔を行い、N層の前記導電層のうちのN層目の前記導電層まで貫通していない第1レーザ孔を形成する第1レーザ穿孔ステップと、N層の前記導電層のうちのN層目の前記導電層からレーザ穿孔を行い、前記第1レーザ孔まで連通している第2レーザ孔を形成する第2レーザ穿孔ステップと、前記第1レーザ孔と前記第2レーザ孔内に、前記1層目の前記導電層とN層目の前記導電層を接続する導電体を形成する導通ステップとを含む、回路基板構造の製造方法を開示する。本発明の実施形態はさらに、上記回路基板構造の製造方法により製造される回路基板構造を開示する。 The present invention provides a preparatory step of providing a multilayer board having N conductive layers (N is a positive integer greater than 2), and laser drilling from the first conductive layer of the N conductive layers. And a first laser drilling step of forming a first laser hole that does not penetrate to the Nth conductive layer of the N conductive layers, and the Nth conductive layer of the N conductive layers. Laser drilling from the conductive layer to form a second laser hole communicating with the first laser hole, and the first laser hole and the second laser hole in the first laser hole. Disclosed is a method for manufacturing a circuit board structure, which includes a conductive step of forming a conductor connecting the conductive layer of the Nth layer and the conductive layer of the Nth layer. Embodiments of the present invention further disclose a circuit board structure manufactured by the method for manufacturing a circuit board structure described above.

また、本発明は、N層(Nは2より大きい正整数である)の導電層を含み、且つ互いに連通している第1レーザ孔と第2レーザ孔を有し、前記第1レーザ孔がN層の前記導電層のうちの1層目の前記導電層から凹設されてなり、前記第2レーザ孔がN層の前記導電層のうちのN層目の前記導電層から凹設されてなり、前記第1レーザ孔の孔径と前記第2レーザ孔の孔径が両方の接合部から互いに離れる方向へ増加していく多層板と、前記第1レーザ孔と前記第2レーザ孔内に位置し、且つ1層目の前記導電層とN層目の前記導電層を接続する導電体とを備える、回路基板構造を開示する。 The present invention also includes a first laser hole and a second laser hole which include N conductive layers (N is a positive integer greater than 2) and are in communication with each other, wherein the first laser hole is The first laser conductive layer of the N conductive layers is recessed from the first conductive layer, and the second laser hole is recessed from the N conductive layer of the N conductive layers. A multilayer plate in which the hole diameter of the first laser hole and the hole diameter of the second laser hole increase in the direction away from each other from both joints; and the first laser hole and the second laser hole. Also disclosed is a circuit board structure including a conductor connecting the first conductive layer and the Nth conductive layer.

以上のように、本発明で開示されている回路基板構造及びその製造方法は、完全にレーザ穿孔方式を使用し、且つ少ないレーザ穿孔回数で、多層板を貫通している第1レーザ孔と第2レーザ孔を形成するものであり、機械的穿孔を使用しないようにすることで、回路基板構造及びその製造方法の生産にかかる時間を短縮させ、生産コストを削減させ、さらにより高密度の配線設計に適用できる。 As described above, the circuit board structure and the manufacturing method thereof disclosed in the present invention completely use the laser perforation method, and the first laser hole and the first laser hole penetrating the multilayer board with a small number of laser perforations. 2 Laser holes are formed, and by not using mechanical perforations, it is possible to shorten the time required for producing the circuit board structure and the manufacturing method thereof, reduce the production cost, and further increase the wiring density. Applicable to design.

本発明の特徴及び技術をより把握するために、以下、本発明に係る詳細な説明及び図面を参照できるが、このような説明及び図面は本発明を説明するためのものに過ぎず、本発明の保護範囲を制限するものではない。 In order to better understand the features and techniques of the present invention, the detailed description and drawings according to the present invention can be referred to as follows, but such description and drawings are only for explaining the present invention, and the present invention It does not limit the scope of protection.

従来の回路基板構造の模式図である。It is a schematic diagram of the conventional circuit board structure. 本発明に係る回路基板構造の製造方法のステップS110の模式図である。It is a schematic diagram of step S110 of the manufacturing method of the circuit board structure which concerns on this invention. 本発明に係る回路基板構造の製造方法のステップS120の模式図である。It is a schematic diagram of step S120 of the manufacturing method of the circuit board structure which concerns on this invention. 本発明に係る回路基板構造の製造方法のステップS130の模式図である。It is a schematic diagram of step S130 of the manufacturing method of the circuit board structure which concerns on this invention. 本発明に係る回路基板構造の製造方法のステップS141の模式図である。It is a schematic diagram of step S141 of the manufacturing method of the circuit board structure which concerns on this invention. 本発明に係る回路基板構造の製造方法のステップS142の模式図である。It is a schematic diagram of step S142 of the manufacturing method of the circuit board structure which concerns on this invention. 本発明に係る回路基板構造の製造方法のステップS150の模式図(1)である。It is a schematic diagram (1) of step S150 of the manufacturing method of the circuit board structure which concerns on this invention. 本発明に係る回路基板構造の製造方法のステップS150の模式図(2)である。It is a schematic diagram (2) of step S150 of the manufacturing method of the circuit board structure which concerns on this invention.

図2−図6Bには、本発明の実施形態が示されている。なお、本実施形態に対する対応図面に示された数や外形は、本発明の内容を把握できるように、本発明の実施形態を説明するためのものに過ぎず、本発明の保護範囲を制限するものではない。 2-6B, an embodiment of the present invention is shown. It should be noted that the numbers and outer shapes shown in the drawings corresponding to the present embodiment are only for explaining the embodiment of the present invention so that the content of the present invention can be grasped, and limit the protection scope of the present invention. Not a thing.

本実施形態は、回路基板構造及びその製造方法を開示し、且つ本実施形態では、前記回路基板構造は、該回路基板構造の製造方法により製造されるが、本発明はそれに制限されない。つまり、本発明の図示しないほかの実施形態では、前記回路基板構造はほかの製造方法によって製造されてもよい。 The present embodiment discloses a circuit board structure and a method for manufacturing the same, and in the present embodiment, the circuit board structure is manufactured by the method for manufacturing the circuit board structure, but the present invention is not limited thereto. That is, in another embodiment (not shown) of the present invention, the circuit board structure may be manufactured by another manufacturing method.

また、前記回路基板構造の具体的な構造を理解しやすくするために、以下、本実施形態の回路基板構造の製造方法を説明し、その後、回路基板構造の具体的な構造を説明する。
[回路基板構造の製造方法]
なお、本実施形態の説明の便宜上、図面には関連する部分構造だけが示されている。図2−図6Bに示されるように、本実施形態では、前記回路基板構造の製造方法は、準備ステップS110、第1レーザ穿孔ステップS120、第2レーザ穿孔ステップS130、導通ステップS140、及び層追加ステップS150を含むが、本発明は、上記ステップS110〜S150の順番又は実施態様に制限されない。
Further, in order to facilitate understanding of a specific structure of the circuit board structure, a method of manufacturing the circuit board structure of the present embodiment will be described below, and then a specific structure of the circuit board structure will be described.
[Method for manufacturing circuit board structure]
Note that, for convenience of description of the present embodiment, only relevant partial structures are shown in the drawings. As shown in FIG. 2 to FIG. 6B, in the present embodiment, the method for manufacturing the circuit board structure includes a preparation step S110, a first laser perforation step S120, a second laser perforation step S130, a conduction step S140, and a layer addition. Although including step S150, the present invention is not limited to the order or implementation of steps S110 to S150.

たとえば、本発明の図示しないほかの実施形態において、上記ステップS110〜S150について、実際の設計ニーズに応じて、調整したり増減したりすることが可能である。また、以下、それぞれ本実施形態の回路基板構造の製造方法の各ステップS110〜S150を説明する。 For example, in another embodiment (not shown) of the present invention, steps S110 to S150 can be adjusted or increased/decreased according to actual design needs. Further, each step S110 to S150 of the method for manufacturing the circuit board structure of the present embodiment will be described below.

図2に示されるように、前記準備ステップS110を実施する。つまり、多層板体11及び上記多層板体11の表面に設置されたN層(Nは2より大きい正整数である)の導電層12を含む多層板1を提供する。本実施形態では、前記多層板1の板体11の数はN−1層であり、且つNは好ましくは4〜10(たとえば、図中、Nは4である)であるが、それに制限されない。 As shown in FIG. 2, the preparation step S110 is performed. That is, the multilayer board 1 including the multilayer board 11 and the N-layer (N is a positive integer larger than 2) conductive layer 12 provided on the surface of the multilayer board 11 is provided. In the present embodiment, the number of plate bodies 11 of the multilayer board 1 is N-1 layers, and N is preferably 4 to 10 (for example, N is 4 in the drawing), but is not limited thereto. ..

図3に示されるように、前記第1レーザ穿孔ステップS120を実施する。つまり、N層の前記導電層12のうちの1層目の導電層12(たとえば、図3中の最上層の導電層12)からレーザ穿孔を行い、N層の前記導電層12のうちのN層目の導電層12(たとえば、図3中の最下層の導電層12)まで貫通していない第1レーザ孔13を形成する。 As shown in FIG. 3, the first laser perforation step S120 is performed. That is, laser drilling is performed from the first conductive layer 12 of the N conductive layers 12 (for example, the uppermost conductive layer 12 in FIG. 3), and N of the N conductive layers 12 is drilled. A first laser hole 13 that does not penetrate to the conductive layer 12 of the layer (for example, the lowermost conductive layer 12 in FIG. 3) is formed.

前記第1レーザ孔13の孔径D13は、好ましくは、上記1層目の導電層12からN層目の導電層12の方向(たとえは、図3中の下向き)へ徐々に小さくなり、このように、円錐台状に類似した構造が形成されているが、本発明はそれに制限されない。さらに、上記第1レーザ孔13の孔径の最大値(たとえば、1層目の導電層12に対応した第1レーザ孔13の孔径)は、好ましくは、従来の機械的穿孔による孔径の最小値以下である。 The hole diameter D13 of the first laser hole 13 is preferably gradually reduced in the direction from the first conductive layer 12 to the Nth conductive layer 12 (for example, downward in FIG. 3). In addition, although a structure similar to a truncated cone is formed, the present invention is not limited thereto. Further, the maximum value of the hole diameter of the first laser hole 13 (for example, the hole diameter of the first laser hole 13 corresponding to the first conductive layer 12) is preferably equal to or smaller than the minimum value of the hole diameter by the conventional mechanical drilling. Is.

図4に示されるように、前記第2レーザ穿孔ステップS130を実施する。つまり、N層の前記導電層12のうちのN層目の導電層12(たとえば、図4中の最下層の導電層12)からレーザ穿孔を行い、前記第1レーザ孔13に連通している第2レーザ孔14を形成する。 As shown in FIG. 4, the second laser perforation step S130 is performed. That is, laser drilling is performed from the Nth conductive layer 12 (for example, the lowermost conductive layer 12 in FIG. 4) of the N conductive layers 12 and communicates with the first laser hole 13. The second laser hole 14 is formed.

前記第2レーザ孔14の孔径は、好ましくは、N層目の導電層12から1層目の導電層12の方向(たとえば、図4中の上向き)へ徐々に小さくなり、円錐台状と類似した構造が形成されるが、本発明はそれに制限されない。さらに、上記第2レーザ孔14の孔径の最大値(たとえば、N層目の導電層12に対応した第2レーザ孔14の孔径)は、好ましくは、従来の機械的穿孔による孔径の最小値以下である。 The diameter of the second laser hole 14 is preferably gradually reduced in the direction from the Nth conductive layer 12 to the first conductive layer 12 (for example, upward in FIG. 4 ), similar to a truncated cone shape. However, the present invention is not limited thereto. Further, the maximum value of the hole diameter of the second laser hole 14 (for example, the hole diameter of the second laser hole 14 corresponding to the Nth conductive layer 12) is preferably equal to or smaller than the minimum value of the hole diameter by the conventional mechanical drilling. Is.

より具体的には、本実施形態では、前記第1レーザ孔13の孔径の最大値は、第2レーザ孔14の孔径の最大値とほぼ同じであり、且つ前記第1レーザ孔13の孔径と第2レーザ孔14の孔径は、両方の接合部から互いに離れる方向(たとえば、図4中、上向きと下向き)へ増加していき、上記接合部とは、略中央部に位置する板体11であるが、本発明は上記条件に制限されない。 More specifically, in the present embodiment, the maximum value of the hole diameter of the first laser hole 13 is substantially the same as the maximum value of the hole diameter of the second laser hole 14, and is the same as the hole diameter of the first laser hole 13. The hole diameter of the second laser hole 14 increases from both joints in a direction away from each other (for example, upward and downward in FIG. 4), and the joint is the plate body 11 located substantially at the center. However, the present invention is not limited to the above conditions.

さらに、本実施形態では、前記第1レーザ孔13と第2レーザ孔14は、N層の前記導電層12のうちすべての導電層12を共同で貫通しているが、本発明はそれに制限されない。たとえば、本発明の図示しないほかの実施形態では、前記1層目とN層目の導電層12の間に位置するほかの導電層12のうち、少なくとも一層の導電層12(つまり、2層目〜N−1層目の導電層12のうちの少なくとも一層の導電層12)は上記第1レーザ孔13と第2レーザ孔14に対応した部位に形成されなくてもよい。従って、上記レーザ穿孔により貫通されていない。また、本実施形態に記載の回路基板構造の製造方法では、実施されるレーザ穿孔回数は、好ましくは、1より大きく且つN−2以下である。 Further, in the present embodiment, the first laser hole 13 and the second laser hole 14 jointly penetrate all the conductive layers 12 of the N conductive layers 12, but the present invention is not limited thereto. .. For example, in another embodiment (not shown) of the present invention, at least one conductive layer 12 among the other conductive layers 12 located between the first conductive layer 12 and the Nth conductive layer 12 (that is, the second conductive layer 12). At least one conductive layer 12) of the (N-1)th conductive layer 12 does not have to be formed in a portion corresponding to the first laser hole 13 and the second laser hole 14. Therefore, it is not penetrated by the laser drilling. Further, in the method of manufacturing a circuit board structure according to the present embodiment, the number of laser perforations performed is preferably larger than 1 and N-2 or less.

図5A及び図5Bに示されるように、前記導通ステップS140を実施する。つまり、前記第1レーザ孔13と第2レーザ孔14内に、上記1層目の導電層12とN層目の導電層12を接続する導電体2a、2bを形成する。言い換えれば、本実施形態の導電体2a、2bは機械的穿孔による孔に設置されていない。 As shown in FIGS. 5A and 5B, the conduction step S140 is performed. That is, the conductors 2a and 2b for connecting the first conductive layer 12 and the Nth conductive layer 12 are formed in the first laser hole 13 and the second laser hole 14, respectively. In other words, the conductors 2a and 2b of this embodiment are not installed in the holes formed by mechanical perforation.

さらに、本実施形態では、第1レーザ孔13と第2レーザ孔14は、N層の前記導電層12のうちのすべての導電層12を共同で貫通するため、上記導電体2a、2bは、N層の前記導電層12のうちのすべての導電層12を接続しているが、本発明はそれに制限されない。 Furthermore, in the present embodiment, the first laser hole 13 and the second laser hole 14 jointly penetrate all the conductive layers 12 of the N conductive layers 12, so that the conductors 2a and 2b are Although all of the N conductive layers 12 are connected, the present invention is not limited thereto.

より具体的には、上記導電体2a、2bは、めっき方式で形成されるが、設計ニーズに応じて、前記導通ステップS140は、選択的に第1電気めっきステップS141又は上記第1電気めっきステップS141と異なる第2電気めっきステップS142で実施してもよい。以下、それぞれ前記導通ステップS140に含まれる第1電気めっきステップS141と第2電気めっきステップS142を説明する。 More specifically, the conductors 2a and 2b are formed by a plating method, but the conduction step S140 is selectively performed by the first electroplating step S141 or the first electroplating step according to design needs. It may be carried out in the second electroplating step S142 different from S141. Hereinafter, the first electroplating step S141 and the second electroplating step S142 included in the conduction step S140 will be described.

図5Aに示されるように、前記第1電気めっきステップS141を実施する。つまり、前記導電体2aが前記第1レーザ孔13の孔壁及び第2レーザ孔14の孔壁にめっきされ、且つ前記導電体2aの内面が取り囲む空間21aを形成する。つまり、本実施形態における第1電気めっきステップS141において形成された導電体2aは中空構造である。 As shown in FIG. 5A, the first electroplating step S141 is performed. That is, the conductor 2a is plated on the hole wall of the first laser hole 13 and the hole wall of the second laser hole 14, and forms the space 21a surrounded by the inner surface of the conductor 2a. That is, the conductor 2a formed in the first electroplating step S141 in this embodiment has a hollow structure.

図5Bに示されるように、前記第2電気めっきステップS142を実施する。つまり、前記導電体2bが前記第1レーザ孔13及び第2レーザ孔14にめっきされ、且つ前記第1レーザ孔13と第2レーザ孔14を充填するように前記導電体2bがめっきされている。つまり、本実施形態の第2電気めっきステップS142において形成される導電体2bは中実構造である。 As shown in FIG. 5B, the second electroplating step S142 is performed. That is, the conductor 2b is plated in the first laser hole 13 and the second laser hole 14, and the conductor 2b is plated so as to fill the first laser hole 13 and the second laser hole 14. .. That is, the conductor 2b formed in the second electroplating step S142 of this embodiment has a solid structure.

図6Aと図6Bに示されるように、前記層追加ステップS150を実施する。つまり、前記多層板1の両面(たとえば、図6A又は図6B中、最上層の板体11の上面及び最下層の板体11の下面)のそれぞれに少なくとも1つの層状構造3を増設する。前記導電体2a、2bは上記少なくとも2つの層状構造3の間に挟持(又は埋設)される。なお、図6A中、前記導電体2aの内側の空間21aが上記層状構造3により埋められる。 As shown in FIGS. 6A and 6B, the layer adding step S150 is performed. That is, at least one layered structure 3 is added to each of both surfaces (for example, the upper surface of the uppermost plate 11 and the lower surface of the lowermost plate 11 in FIG. 6A or 6B) of the multilayer board 1. The conductors 2a and 2b are sandwiched (or embedded) between the at least two layered structures 3. In FIG. 6A, the space 21 a inside the conductor 2 a is filled with the layered structure 3.

前記のとおり、前記回路基板構造の製造方法では、上記ステップS110〜S150を実施すると、より高配線密度に適し且つ生産にかかる時間が短い回路基板構造100が製造される。しかし、本発明の回路基板構造100の製造は上記ステップS110〜S150に実施する場合に制限されない。以下、本実施形態の回路基板構造100の具体的な構造を簡単に説明し、必要に応じて、上記説明した詳細な特徴を参照できる。
[回路基板構造]
なお、本実施形態の説明の便宜上、図面には関連する部分構造だけが示されている。図6Aと図6Bに示されるように、前記回路基板構造100は、本実施形態では、多層板1と、上記多層板1内に埋設された導電体2a、2bと、それぞれ前記多層板1及び導電体2a、2bの両面に被覆された2つの層状構造3とを備える。
As described above, in the method of manufacturing a circuit board structure, when steps S110 to S150 are performed, the circuit board structure 100 suitable for higher wiring density and shorter in production time is manufactured. However, the manufacture of the circuit board structure 100 of the present invention is not limited to the case of performing the steps S110 to S150. Hereinafter, a specific structure of the circuit board structure 100 of the present embodiment will be briefly described, and the detailed features described above can be referred to as necessary.
[Circuit board structure]
Note that, for convenience of description of the present embodiment, only relevant partial structures are shown in the drawings. As shown in FIGS. 6A and 6B, in the present embodiment, the circuit board structure 100 includes a multilayer board 1, conductors 2a and 2b embedded in the multilayer board 1, and the multilayer board 1 and the multilayer board 1 respectively. And two layered structures 3 coated on both sides of the conductors 2a, 2b.

前記多層板1は、多層の板体11及び上記多層の板体11の表面に設置されたN層(Nは2より大きい正整数である)の導電層12を含む。前記多層板1には、互いに連通している第1レーザ孔13と第2レーザ孔14が形成され、且つ上記第1レーザ孔13と第2レーザ孔14は、上記多層板1を貫通している貫通孔を共同で構成する。 The multi-layer board 1 includes a multi-layer board 11 and N conductive layers 12 (N is a positive integer larger than 2) provided on the surface of the multi-layer board 11. A first laser hole 13 and a second laser hole 14 communicating with each other are formed in the multilayer plate 1, and the first laser hole 13 and the second laser hole 14 penetrate the multilayer plate 1. Through-holes are jointly configured.

さらに、前記第1レーザ孔13は、N層の前記導電層12のうちの1層目の導電層12(たとえば、図6A又は図6B中、最上層の導電層12)から凹設され、前記第2レーザ孔14は、N層の前記導電層12のうちのN層目の導電層12(たとえば、図6A又は図6B中、最下層の導電層12)から凹設され、且つ前記第1レーザ孔13の孔径と前記第2レーザ孔14の孔径は、両方の接合部から互いに離れる方向へ増加していく。 Further, the first laser hole 13 is recessed from the first conductive layer 12 of the N conductive layers 12 (for example, the uppermost conductive layer 12 in FIG. 6A or 6B), and The second laser hole 14 is recessed from the Nth conductive layer 12 (for example, the lowermost conductive layer 12 in FIG. 6A or FIG. 6B) of the N conductive layers 12, and the first laser hole 14 is provided. The hole diameter of the laser hole 13 and the hole diameter of the second laser hole 14 increase in the direction away from each other at both joints.

図6Aと図6Bに示されるように、前記導電体2a、2bは、上記多層板1の第1レーザ孔13と第2レーザ孔14内に位置し、且つ上記導電体2a、2bは1層目の導電層12とN層目の導電層12を接続し、本実施形態では、上記導電体2a、2bはN層の前記導電層12のうちのすべての導電層12を接続するが、本発明はそれに制限されない。 As shown in FIGS. 6A and 6B, the conductors 2a and 2b are located in the first laser hole 13 and the second laser hole 14 of the multilayer board 1, and the conductors 2a and 2b are one layer. The conductive layer 12 of the second layer is connected to the conductive layer 12 of the Nth layer. In the present embodiment, the conductors 2a and 2b are connected to all the conductive layers 12 of the conductive layers 12 of the Nth layer. The invention is not so limited.

より具体的には、本実施形態では、前記導電体は図6Aと図6Bに示される2種のタイプを含む。図6Aに示されるように、前記導電体2aは上記第1レーザ孔13の孔壁及び第2レーザ孔14の孔壁にめっきされ、且つ前記導電体2aの内面が取り囲む空間21aを形成する。つまり、図6Aに示される導電体2aは中空構造である。さらに、図6Bに示されるように、前記導電体2bは上記第1レーザ孔13及び第2レーザ孔14にめっきされ、且つ前記第1レーザ孔13と第2レーザ孔14を充填するように導電体2bがめっきされ、つまり、図6Bに示される導電体2bは中実構造である。
[本発明の実施形態の技術的効果]
以上のように、本発明の実施形態に開示されている回路基板構造100及びその製造方法では、完全にレーザ穿孔方式を用い且つ少ないレーザ穿孔回数で、多層板1を貫通している第1レーザ孔13と第2レーザ孔14が形成されることによって、機械的穿孔を必要とせずに、回路基板構造100及びその製造方法は生産にかかる時間を短縮させて、生産コストを削減させ、また、より高密度の配線設計に適応できる。
More specifically, in this embodiment, the conductor includes two types shown in FIGS. 6A and 6B. As shown in FIG. 6A, the conductor 2a is plated on the hole wall of the first laser hole 13 and the hole wall of the second laser hole 14 and forms a space 21a surrounded by the inner surface of the conductor 2a. That is, the conductor 2a shown in FIG. 6A has a hollow structure. Further, as shown in FIG. 6B, the conductor 2b is plated on the first laser hole 13 and the second laser hole 14, and is electrically conductive so as to fill the first laser hole 13 and the second laser hole 14. The body 2b is plated, that is, the conductor 2b shown in FIG. 6B is a solid structure.
[Technical effects of the embodiment of the present invention]
As described above, in the circuit board structure 100 and the manufacturing method thereof disclosed in the embodiment of the present invention, the first laser which completely penetrates the multilayer board 1 by using the laser perforation method and with a small number of laser perforations. Since the holes 13 and the second laser holes 14 are formed, the circuit board structure 100 and the method of manufacturing the circuit board structure 100 can reduce the production time, reduce the production cost, and eliminate the need for mechanical perforation. Applicable to higher density wiring design.

以上は本発明の好適実施形態であり、本発明の保護範囲を制限するものではなく、本発明の特許請求の範囲を逸脱せずに実施される均等な変形や修飾はいずれも本発明の特許請求の範囲の保護範囲に属する。 The above is a preferred embodiment of the present invention, which does not limit the protection scope of the present invention, and any equivalent variations and modifications that are implemented without departing from the scope of the claims of the present invention It belongs to the protection scope of the claims.

[従来技術]
100’:回路基板構造
1’:多層板
2’:貫通孔
[本発明の実施形態]
100:回路基板構造
1:多層板
11:板体
12:導電層
13:第1レーザ孔
14:第2レーザ孔
2a:導電体
21a:空間
2b:導電体
3:層状構造
S110:準備ステップ
S120:第1レーザ穿孔ステップ
S130:第2レーザ穿孔ステップ
S140:導通ステップS140
S141:第1電気めっきステップ
S142:第2電気めっきステップ
S150:層追加ステップ
[Prior art]
100': Circuit board structure 1': Multilayer board 2': Through hole [Embodiment of the present invention]
100: Circuit board structure 1: Multilayer plate 11: Plate 12: Conductive layer 13: First laser hole 14: Second laser hole 2a: Conductor 21a: Space 2b: Conductor 3: Layered structure S110: Preparation step S120: First laser perforation step S130: Second laser perforation step S140: Conduction step S140
S141: First electroplating step S142: Second electroplating step S150: Layer addition step

Claims (6)

回路基板構造の製造方法であって、
N層(Nは2より大きい正整数である)の導電層を有する多層板を提供する準備ステップと、
N層の前記導電層のうちの1層目の前記導電層からレーザ穿孔を行い、N層の前記導電層のうちのN層目の前記導電層まで貫通していない第1レーザ孔を形成する第1レーザ穿孔ステップと、
N層の前記導電層のうちのN層目の前記導電層からレーザ穿孔を行い、前記第1レーザ孔まで連通している第2レーザ孔を形成する第2レーザ穿孔ステップと、
前記第1レーザ孔と前記第2レーザ孔内に、前記1層目の前記導電層とN層目の前記導電層を接続する導電体を形成する導通ステップとを含み、
前記導通ステップにおいて、前記導電体は前記第1レーザ孔及び前記第2レーザ孔にめっきされ、且つ前記第1レーザ孔と前記第2レーザ孔全体にわたり前記導電体がめっきされていることを特徴とする回路基板構造の製造方法。
A method of manufacturing a circuit board structure, comprising:
A preparatory step of providing a multilayer board having N layers of conductive layers (N is a positive integer greater than 2);
Laser drilling is performed from the first conductive layer of the N conductive layers to form a first laser hole that does not penetrate to the N conductive layer of the N conductive layers. A first laser drilling step,
A second laser perforation step of performing laser perforation from the Nth conductive layer of the N conductive layers to form a second laser hole communicating with the first laser hole;
The first laser aperture and the second laser bore, see contains a conduction forming a conductor for connecting the conductive layer and the N-th layer the conductive layer of the first layer,
In the conducting step, the conductor is plated in the first laser hole and the second laser hole, and the conductor is plated over the entire first laser hole and the second laser hole. Method of manufacturing a circuit board structure.
前記第1レーザ孔と前記第2レーザ孔は、N層の前記導電層のうちのすべての前記導電層を共同で貫通し、且つ前記導電体はN層の前記導電層のうちのすべての前記導電層を接続している請求項1に記載の回路基板構造の製造方法。 The first laser hole and the second laser hole jointly penetrate all the conductive layers of the N conductive layers, and the conductor is used for all the N conductive layers. The method of manufacturing a circuit board structure according to claim 1, wherein conductive layers are connected. 前記レーザ穿孔の実施回数が1より大きく且つN−2以下であり、且つNは4〜10に限定される請求項1に記載の回路基板構造の製造方法。 The method for manufacturing a circuit board structure according to claim 1, wherein the number of times of laser drilling is greater than 1 and N-2 or less, and N is limited to 4 to 10. 前記導通ステップの後、前記多層板の両面のそれぞれに少なくとも1つの層状構造を増設する層追加ステップをさらに行う請求項1に記載の回路基板構造の製造方法。 The method for manufacturing a circuit board structure according to claim 1, further comprising a layer adding step of adding at least one layered structure to each of both surfaces of the multilayer board after the conducting step. 回路基板構造であって、
請求項1−4のいずれか一項に記載の回路基板構造の製造方法により製造されることを特徴とする回路基板構造。
Circuit board structure,
A circuit board structure manufactured by the method for manufacturing a circuit board structure according to claim 1.
回路基板構造であって、
N層(Nは2より大きい正整数である)の導電層を含み、且つ互いに連通している第1レーザ孔と第2レーザ孔を有し、前記第1レーザ孔がN層の前記導電層のうちの1層目の前記導電層から凹設されてなり、前記第2レーザ孔がN層の前記導電層のうちのN層目の前記導電層から凹設されてなり、前記第1レーザ孔の孔径と前記第2レーザ孔の孔径が両方の接合部から互いに離れる方向へ増加していく多層板と、
前記第1レーザ孔と前記第2レーザ孔内に位置し、且つ1層目の前記導電層とN層目の前記導電層を接続する導電体とを備え
前記導電体は前記第1レーザ孔及び前記第2レーザ孔にめっきされ、且つ前記第1レーザ孔と前記第2レーザ孔全体にわたり前記導電体がめっきされていることを特徴とする回路基板構造。
Circuit board structure,
The conductive layer includes an N-layer (N is a positive integer greater than 2) conductive layer and has a first laser hole and a second laser hole which are in communication with each other, and the first laser hole is an N-layer. The first laser layer is recessed from the first conductive layer, and the second laser hole is recessed from the Nth conductive layer of the N conductive layers. A multilayer plate in which the hole diameter of the hole and the hole diameter of the second laser hole increase in a direction away from each other at both joints;
A conductor located in the first laser hole and the second laser hole and connecting the first conductive layer and the Nth conductive layer ;
The conductor is plated on the first laser aperture and the second laser aperture, and the circuit board structure the conductor throughout the second laser holes and the first laser cavity is characterized that you have been plated.
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